# DAQ/DAQe-2213/2214 16-ch High Performance Low-Cost Data Acquisition Card User’s Manual Manual Rev. 1.0 Revision Date: Dec. 29, 2023 Part No: 50M-12267-1000 Revision History
RevisionRelease DateDescription of Change(s)
1.002004-02-12Previous version PN: 50-11034-100
1.02023-12-28Initial release under new part number.Added 1.4 Software Support.Added 2.4 Switch and Jumper Settings.Added 4.1.6 Bus-mastering DMA Data Transfer.
# Preface # Copyright © 2023 ADLINK Technology Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.daq-daqe-221x-50m-12267-1000-10/6c9256fa38322e6f71aa3f3863a1eb04869359ed058f23eb535b241fb73efffb.jpg) Battery Labels (for products with battery) ![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.daq-daqe-221x-50m-12267-1000-10/32eef3897a0781e7afb8cf2c3bcd920eaaee551e067b6c72ff7d41175e136ec1.jpg) ![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.daq-daqe-221x-50m-12267-1000-10/d19f5d2d0a172d439eff850e55f21db9927136a8560e5e057422f746a0b6c23e.jpg) Li-ion ![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.daq-daqe-221x-50m-12267-1000-10/1b978150a448b3dc1b7c133e5c46843e08d17b910571c2563006acefc6d62b89.jpg) ![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.daq-daqe-221x-50m-12267-1000-10/e2371b2106bc2cfa947814388044fa8706432c78c9ed5480aeb364557f2de317.jpg) ᘄ㟁ụㄳᅇᨲ # California Proposition 65 Warning ![This image displays a standard warning sign: a yellow equilateral triangle with a thick black border, containing a large black exclamation point in its center.](.daq-daqe-221x-50m-12267-1000-10/179c8e9947a91fa217dba877cc7206de93874d307781116b181fe1bd7276387c.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image shows an icon of a white piece of paper featuring horizontal lines running across it and its top-right corner folded down. A large, thick red checkmark is superimposed over the center of the paper.](.daq-daqe-221x-50m-12267-1000-10/012416d45fa6781c88ecccd60eb6b93faa661ecb75c741a52b61fd046c8e3413.jpg) NOTE: Additional information, aids, and tips that help users perform tasks. ![The image displays a standard warning sign featuring a yellow equilateral triangle with a thick black border. Centered inside the triangle is a large black exclamation point.](.daq-daqe-221x-50m-12267-1000-10/61102a7057e77c24ff9efd7ca513a7778f251d8a93041f930bfe99bf2af24095.jpg) CAUTION: Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image displays a maroon triangle pointing upwards, containing a large white exclamation mark in the center. At the very top edge of the image, there is a black bar containing the white text 'Warning,' which is partially cut off.](.daq-daqe-221x-50m-12267-1000-10/c204af836454a18f3814e84d65f2ad07bd051ac114614e56a443ff247374604f.jpg) WARNING: Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # Table of Contents # Preface ........ iii # List of Tables......... . vii # List of Figures ....... ix # 1 Introduction ......... 1.1 Features.... 2 1.2 Applications .. 3 1.3 Specifications... 3 1.4 Software Support .. 9 # 2 Installation ....... 13 2.1 Contents of Package ..... 1 3 2.2 Unpacking.... 14 2.3 DAQ/DAQe-2213/2214 Layout .. 1 5 2.4 Switch and Jumper Settings . 1 6 2.5 PCI Configuration . 20 # 3 Signal Connections....... . 21 3.1 Connector Pin Assignment . 21 3.2 Analog Input Signal Connection ... 28 # 4 Operation Theory ........ . 31 4.1 A/D Conversion... 3 1 4.2 D/A Conversion (for DAQ/DAQe-2214 only)..... . 48 4.3 Digital I/O .. 5 8 4.4 General Purpose Timer/Counter Operation.. 5 9 4.5 Trigger Sources .. 6 7 4.6 User-controllable Timing Signals .... 73 # 5 Calibration ........ .... 81 5.1 Loading Calibration Constants... . 81 5.2 Auto-calibration .... 82 5.3 Saving Calibration Constants.... 82 # Important Safety Instructions....... . 83 # Getting Service ....... ..... 85 # List of Tables Table 1-1: Programmabel Input Range.. 3 Table 1-2: Bandwidth. 4 Table 1-3: System Noise... . 4 Table 1-4: CMRR (DC to 60 Hz) ..... 5 Table 1-5: Settling Time to Full Scale Step.. 5 Table 2-1: Board ID SW1 DIP Switch Settings .... . 17 Table 3-1: CN1 Pin Assignment for DAQ/DAQe-2213/2214........... 22 Table 3-2: CN2 Pin Assignment for DAQ/DAQe-2213... .. 23 Table 3-3: CN2 Pin Assignment for DAQ/DAQe-2214... .. 24 Table 3-4: CN1/CN2 Signal Description .. .. 25 Table 3-5: SSI Connector Pin Assignment for DAQ/DAQe-2213 ... 26 Table 3-6: SSI Connector Pin Assignment for DAQ/DAQe-2214 ... 26 Table 3-7: SSI Connector Legend . .. 27 Table 4-1: Bipolar Analog Input Range and Output Digital Code ... 32 Table 4-2: Unipolar Analog Input Range and Output Digital Code . 32 Table 4-3: Bipolar Output Code Table (Vref=10V if internal reference is selected) . .. 48 Table 4-4: Unipolar Output Code Table (Vref=10V if internal reference is selected) . 49 Table 4-5: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic.. . 68 Table 4-6: User-controllable Timing Signals and Functionalities .... 74 Table 4-7: Auxiliary Function Input Signals and Functionalities...... 76 Table 4-8: SSI Timing Signal and Functions.. . 78 This page intentionally left blank. # List of Figures Figure 2-1: PCB Layout of DAQ/DAQe-2213/2214.. . 15 Figure 2-2: Board ID SW1 DIP Switch . . 16 Figure 2-3: Enable Board ID Configuration... . 18 Figure 2-4: DIO Initial Status (JP4) .. . 19 Figure 3-1: Floating Source and RSE Input Connections ........... 29 Figure 3-2: Ground-referenced Sources and NRSE Input Connections.... . 29 Figure 3-3: Ground-referenced Source and Differential Input..... 30 Figure 3-4: Floating Source and Differential Input .. .. 30 Figure 4-1: Scan Timing...... ... 35 Figure 4-2: Pre-trigger (Trigger occurs after M scans)................ 37 Figure 4-3: Pre-trigger (Trigger with scan in progress) ..... .. 38 Figure 4-4: Pre-trigger with M\_enable=0 (Trigger occurs before M scans)... . 39 Figure 4-5: Pre-trigger with M\_enable=1 .. 40 Figure 4-6: Middle-Trigger with M\_enable = 1 ... .. 41 Figure 4-7: Middle-Trigger (Trigger occurs when a scan is in progress)............. 42 Figure 4-8: Post-trigger .. ... 43 Figure 4-9: Delay trigger .. .. 44 Figure 4-10: Post trigger with Re-trigger.. .. 45 Figure 4-11: Linked List of PCI Address DMA Descriptors ........... 47 Figure 4-12: Typical D/A Timing of Waveform Generation ........... 51 Figure 4-13: Post Trigger Waveform Generation.... .. 52 Figure 4-14: Delay Trigger Waveform Generation..... .. 53 Figure 4-15: Re-triggered Waveform Generation with Post-Trigger (DLY2\_Counter=0)... . 53 Figure 4-16: Finite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0).. 54 Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0).. . 55 Figure 4-18: Stop Mode I .. . 56 Figure 4-19: Stop Mode II . . 57 Figure 4-20: Stop Mode III .. .. 57 Figure 4-21: Mode 1 Operation.... .. 60 Figure 4-22: Mode 2 Operation.... ... 61 Figure 4-23: Mode 3 Operation.... .. 62 Figure 4-24: Mode 4 Operation... . 63 Figure 4-25: Mode 5 Operation... ... 64 Figure 4-26: Mode 6 Operation.... ... 65 Figure 4-27: Mode 7 Operation.. . 66 Figure 4-28: Mode 8 Operation.. . 66 Figure 4-29: Analog Trigger Block Diagram.. . 68 Figure 4-30: Below-Low Analog Trigger Condition .. .69 Figure 4-31: Above-High Analog Trigger Condition ... . 69 Figure 4-32: Inside-Region Analog Trigger Condition.. . 70 Figure 4-33: High-Hysteresis Analog Trigger Condition........ . 71 Figure 4-34: Low-Hysteresis Analog Trigger Condition ...... . 72 Figure 4-35: External Digital Trigger . . 72 Figure 4-36: DAQ signals routing.. . 73 # 1 Introduction The ADLINK DAQ/DAQe-221x Series is a 16-ch low cost, highperformance multifunction DAQ card that can sample up to 16 analog input channels with different gain settings and scan sequences, making it ideal for dealing with analog signals with various input ranges and sampling speeds. The ADLINK DAQ/ DAQe-221x Series also offers differential modes for 8 AI channels in order to achieve maximum noise elimination. DAQ/DAQe-221x Series has 2-ch 12-bit analog output with waveform generation capabilities. The DAQ/DAQe-221x Series also features analog and digital triggering, 24-ch programmable digital I/O lines, and 2-ch 16-bit general-purpose timers/counters. Like all the other members in DAQ/DAQe-2000 family, multiple DAQ/DAQe-221x Series cards can be synchronized through the system synchronization interface (SSI) bus. Auto-calibration adjusts the gain and offset to within specified accuracies eliminate the need to manually adjust trimpots. # 1.1 Features The DDAQ/DAQe-221x Series Advanced Data Acquisition Card provides the following advanced features:  32-bit PCI-Bus, Plug and Play  Up to 16 single-ended inputs or 8 differential inputs, mixing of SE and DI analog input signals is possible  512 word analog input Channel Gain Queue configuration size  16-bit Analog input resolution with sampling rate up to 250kHz  Programmable Bipolar/Unipolar analog input  Programmable gain: x1, x2, x4, x8  A/D FIFO size: 1024 samples Versatile trigger sources: software trigger, external digital trigger, analog trigger, and triggers from the System Synchronization Interface (SSI)  A/D Data transfer: software polling & bus-mastering DMA with Scatter/Gather functionality  Four A/D trigger modes: post-trigger, delay-trigger, pre-trigger, and middle-trigger  2 channel D/A outputs with waveform generation capability (2214 only)  1024 word length output data FIFO for D/A channels (2214 only)  D/A Data transfer: software update and bus-mastering DMA with Scatter/Gather functionality (2214 only)  System Synchronization Interface (SSI)  A/D fully auto-calibration  Completely jumper-less and software configurable # 1.2 Applications  Automotive Testing  Cable Testing  Transient signal measurement  ATE  Laboratory Automation  Biotech measurement # 1.3 Specifications # Analog Input (AI)  Programmable channels:  16 single-ended (SE) or 8 differential input (DI)  Mixing of SE and DI analog signal sources (Software selectable per channel)  A/D converter: AD7663 or equivalent  Max sampling rate: 250 kS/s  Resolution: 16-bit, no missing code  Input coupling: DC  Programmable input range:
Bipolar input rangeUnipolar input range
±10 V0 to 10 V
±5 V0 to 5 V
±2.5 V0 to 2.5 V
±1.25 V0 to 1.25 V
Table 1-1: Programmabel Input Range  Operational common mode voltage range: ±11V max.  Over-voltage protection:  Power on: Continuous ±30V  Power off: Continuous ±15V  FIFO buffer size: 1024 samples  Data transfers:  Programmed I/O  Bus-mastering DMA with scatter/gather  Channel Gain Queue configuration size: 512 words  Bandwidth (Typical $2 5 ^ { \circ } \mathrm { C } )$ :
Input rangeSmall signal bandwidth (-3dB)Large signal bandwidth (1% THD)
±10 V0 V to 10 V760 kHz280 kHz
±5 V0 V to 5 V720 kHz300 kHz
±2.5 V0 V to 2.5 V610 kHz310 kHz
±1.25 V0 V to 1.25 V450 kHz330 kHz
Table 1-2: Bandwidth  System Noise (LSBrms, including Quantization, Typical, $2 5 ^ { \circ } \mathrm { C } )$
Input RangeSystem NoiseInput RangeSystem Noise
±10 V0.8 LSBrms0 V to 10 V0.9 LSBrms
±5 V0.85 LSBrms0 V to 5 V1.0 LSBrms
±2.5 V0.85 LSBrms0 V to 2.5 V1.0 LSBrms
±1.25 V0.9 LSBrms0 V to 1.25 V1.2 LSBrms
Table 1-3: System Noise  Input impedance:  Normal power on: 1 G/100 pF  Power off: 820   Overload: 820   CMRR (DC to 60 Hz, Typical)
Input RangeCMRRInput RangeCMRR
±10 V83 dB0 V to 10 V87 dB
±5 V87 dB0 V to 5 V90 dB
±2.5 V90 dB0 V to 2.5 V92 dB
±1.25 V92 dB0 V to 1.25 V93 dB
Table 1-4: CMRR (DC to 60 Hz)  Settling time to full-scale step (Typical, $2 5 ^ { \circ } \mathrm { C } )$ :
Input RangeConditionSettling time
All RangesMultiple channels,multiple ranges.All samples in unipolar OR bipolar mode.4 μs to 0.01% error
All RangesMultiple channels,multiple ranges.All samples in unipolar AND/OR bipolar mode.4 μs to 0.01% error
Table 1-5: Settling Time to Full Scale Step  Time-base source:  Internal 40 MHz or external clock Input $( \mathfrak { f } _ { \mathrm { m a x } } )$ : 40 MHz, $\mathsf { f } _ { \mathsf { m i n } } \colon$ 1 MHz, 50% duty cycle)  Trigger modes: Post-trigger, delay-trigger, pre-trigger and middle-trigger  Offset error: ±1 mV max  Gain error: 0.01% of reading max # Analog Output (AO) (for DAQ/DAQe-2214 only)  Channels: Two-channel analog voltage output  DA converter: LTC7545 or equivalent  Max update rate: 1 MS/s  Resolution: 12 bits  FIFO buffer size:  512 samples per channel when both channels are enabled for timed output  1024 samples when only one channel is used for timed output  Data transfers:  Programmed I/O  Bus-mastering DMA with scatter/gather Output range: ±10 V, 0 V to 10 V, ±AOEXTREF, 0 to AOEX-TREF  Settling time: 3µS to 0.5LSB accuracy  Slew rate: 20 V/µS  Output coupling: DC  Protection: Short-circuit to ground  Output impedance: 0.1 typical  Output driving current: ±5 mA max  Stability: Any passive load, up to 1500 pF  Power-on state: 0V steady-state  Power-on glitch: ±1.5 V/500 µS  Relative accuracy: ±0.5 LSB typical, ±1 LSB max  DNL: ±0.5 LSB typical, ±1.2 LSB max  Offset error: ±1 mV max  Gain error: ±0.02% of output max # General Purpose Digital I/O (G.P. DIO, 82C55A)  Channels: 24 programmable input/output  Compatibility: TTL  Input voltage:  Logic Low: VIL=0.8 V max; IIL=0.2 mA max  High: VIH=2.0 V max; IIH=0.02 mA max  Output voltage:  Low: VOL=0.5 V max; IOL=8 mA max  High: VOH=2.7 V min; IOH=400 µA  Synchronous Digital Inputs (SDI):  Channels: 4 digital inputs sampled simultaneously with the analog signal input  Compatibility: TTL/CMOS  Input voltage: Logic Low: VIL=0.8 V max; IIL=0.2mA max Logic High: VIH=2.0 V min; IIL=0.02mA max # General Purpose Timer/Counter (GPTC)  Channels: 2 independent up/down timer/counters  Resolution: 16 bits  Compatibility: TTL  Clock source: Internal or external  Max source frequency: 10 MHz # Analog Trigger (A.Trig)  Source:  All analog input channels  External analog trigger (EXTATRIG)  Level: ±Full-scale, internal; ±10 V external  Resolution: 8 bits  Slope: Positive or negative (software-selectable)  Hysteresis: Programmable  Bandwidth: 400 kHz # External Analog Trigger Input (EXTATRIG)  Input Impedance: 20 k  Coupling: DC  Protection: Continuous ±35 V maximum # Digital Trigger (D.Trig)  Compatibility: TTL/CMOS  Response: Rising or falling edge  Pulse Width: 10 ns min # System Synchronous Interface (SSI)  Trigger lines: 7 # Stability  Recommended warm-up time: 15 minutes  Onboard calibration reference:  Level: 5.000 V  Temperature coefficient: ±2 ppm/C  Long-term stability: 6 ppm/1000 Hr # Physical  Dimensions: 175mm by 107mm  I/O connector: 68-pin female VHDCI type (e.g. AMP-787254-1) # Power Requirement (typical)  +5 VDC, 1.2 A # Operating Environment  Ambient temperature: $0 ^ { \circ } \mathsf { C }$ to $5 5 ^ { \circ } \mathrm { C }$  Relative humidity: 10% to 90% non-condensing # Storage Environment  Ambient temperature: - $\scriptstyle 2 0 ^ { \circ } \complement$ to $70 \textdegree$  Relative humidity: 5% to 95% non-condensing # 1.4 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platforms. By leveraging low-level kernel management and a user friendly API, users can easily manage devices under a Windows environment and focus on developing applications. ![This diagram illustrates a layered software architecture for MAPS (Measurement & Automation eXchange) Core. It is organized into three distinct horizontal sections:\n\n**Top Section (Application & Management Layer)**\nThis section is divided into a left panel and three right-hand columns.\n\n* **Left Panel (Red Background):**\n * Header: **MAPS Core Device Management**\n * Block 1: **Device Manager (ACE)**\n * Block 2: **PXI Platform Resource Mgmt. Utility**\n * Block 3: **PXI Platform ChassisWatch Utility**\n * Block 4: **DAQ/IO Module Function Test Utility**\n\n* **Right Columns (White Backgrounds):**\n * **Column 1:** Top block **User APPs in C/C++** sits directly above an orange block labeled **MAPS/C C/C++ SDK for DAQ/IO module**.\n * **Column 2:** Top block **User APPs in LabVIEW** sits directly above a green block labeled **MAPS/LV LabVIEW SDK for DAQ/IO module**.\n * **Column 3:** Top block **User APPs in C#** sits directly above a purple block labeled **MAPS/C# C# SDK for DAQ/IO module Coming soon**.\n\n**Middle Section (Runtime Layer)**\nA wide red bar spans the width of the diagram below the top section.\n* Left text: **MAPS Core -Device Runtime**\n* Right text: **PXI Platform Service DAQ/IO Module Device Driver DAQ/IO Module Runtime Library**\n\n**Bottom Section (Hardware Layer)**\nA blue strip at the bottom displays images of physical hardware components, labeled from left to right:\n* **Digitizers**\n* **DAQ**\n* **Edge Platform**\n* **PXle Controllers**\n* **PXle/PXI Chassis**\n\n**Connections:**\nThe diagram depicts a vertical stack. The 'User APPs' utilize the 'SDK' blocks beneath them. Both the 'MAPS Core Device Management' tools and the 'SDK' layers rest upon the 'MAPS Core -Device Runtime' layer. Finally, the 'Device Runtime' layer (containing drivers and libraries) interfaces directly with the hardware components listed in the bottom blue section.](.daq-daqe-221x-50m-12267-1000-10/c9a4f53c69962ae68228c390c5a727bf4951af974d836d1b2987a398e071903c.jpg) # 1.4.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment. ![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\nGeneral\n0: PCI9112 Device 'PCI-9'\nUSB\nSettings\nAlias Name PCI-9112-0\nVendor ADLINK Technology Inc.\nModel PCI9112 Device\nPCI Bus 2\nPCI Device 11\nPCI Function 0\nDMA Buffer\nAI 1024 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch\nCorelib](.daq-daqe-221x-50m-12267-1000-10/8ea05d7a2ec6bc9bf2ebbc9e2e203d9637fa3aeb4385abec24583afaf47a84cb.jpg) ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen. ![| Time (Sec) | Voltage (Vpp) |\n| ---------- | ------------- |\n| 0.00 | 5 |\n| 0.03 | 5 |\n| 0.035 | -5 |\n| 0.08 | -5 |\n| 0.085 | 5 |\n| 0.10 | 5 |](.daq-daqe-221x-50m-12267-1000-10/053ecd707b1e083083da3910d747ebe290c71957376954206a8348ff85e9954d.jpg) # 1.4.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual: https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_LV # 1.4.3 MAPS/C, C & C++ Support Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website. https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_C # 2 Installation This chapter describes how to install the DAQ/DAQe-2213/2214. The contents of the package and unpacking information are outlined first. # 2.1 Contents of Package In addition to this User's Manual, the package includes the following items:  DAQ/DAQe-2213/2214 Low-Cost Data Acquisition Card  Software Installation Guide If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future. # 2.2 Unpacking The DAQ/DAQe-2213/2214 card contains electro-static sensitive components that can be easily damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage. Shipping and handling may cause damage to the module. Be sure there is no shipping and handling damage on the carton before continuing. After opening the card module carton, extract the module and place it only on a grounded anti-static surface with component side up. Again, inspect the module for damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module placed on a firm flat surface. ![The image displays a white document icon with a folded top-right corner and faint horizontal lines. A large, bold red checkmark is superimposed over the center of the document.](.daq-daqe-221x-50m-12267-1000-10/c920ffeae014c61866c7ab390716b4e4e328ff6c32fb2df7bd18e04f27c50375.jpg) NOTE: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED. You are now ready to install your DAQ/DAQe-2213/2214. # 2.3 DAQ/DAQe-2213/2214 Layout ![CN1\n68 PIN Connector\nBoard to Board connector\nDaughter Board\nCN2\nBoard to Board connector\nSSI connector\nCarrier Board](.daq-daqe-221x-50m-12267-1000-10/fbbc629252bd3c74e1fa57d74254fa69be341bbaea3a7e077da6112d52dd6380.jpg) Figure 2-1: PCB Layout of DAQ/DAQe-2213/2214 # 2.4 Switch and Jumper Settings # 2.4.1 Board ID (SW1) The DAQ/DAQe-2213/2214 has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for identifying each card’s device number. After setting each DAQ/DAQe-2213/2214 card, you can identify each card in the system with different device numbers. The default value of the Board ID is 0 and if you need to adjust it to another value, set the SW1 switch as shown in the table below. ![ON\nDIP\n1 2 3 4](.daq-daqe-221x-50m-12267-1000-10/021e0e5c6c5cc41143603156c7468b265d653de4c804648cc6f71b4c93298f24.jpg) Figure 2-2: Board ID SW1 DIP Switch
SW1Pin 1Pin 2Pin 3Pin 4
Board IDID0ID1ID2ID3
0OffOffOffOff
1OnOffOffOff
2OffOnOffOff
3OnOnOffOff
4OffOffOnOff
5OnOffOnOff
6OffOnOnOff
7OnOnOnOff
8OffOffOffOn
9OnOffOffOn
10OffOnOffOn
11OnOnOffOn
12OffOffOnOn
13OnOffOnOn
14OffOnOnOn
15OnOnOnOn
Table 2-1: Board ID SW1 DIP Switch Settings ![The image shows a white icon representing a document or piece of lined paper with a folded top-left corner. A large red checkmark is superimposed diagonally across the center of the paper.](.daq-daqe-221x-50m-12267-1000-10/200db0fedca9d15263a53208b450c87b16ad517d1c78db111d2d81711543c801.jpg) NOTE: Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K\_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select your Card Type and uncheck Ignore Board ID. See figure below. ![DAQ2000 Device Driver Configuration\nThis utility is used for the cards that will perform continuous AI, DI or DO operation\nCard Type: Daq2016\nDaq2010\nDaq2205\nDaq2206\nAI : Daq2005\nDaq2204\nAO : Daq2006\nDaq2501\nDaq2502\nDI : Daq2208\nDaq2213\nDO : Daq2214\nIgnore Board ID No Reset\nOK Apply Cancel](.daq-daqe-221x-50m-12267-1000-10/bd3596dcf3a9c983c1a9168f2361d68f26b3b6d7a777f584191876f458289fca.jpg) Figure 2-3: Enable Board ID Configuration # 2.4.2 DIO Initial Status (JP4) The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below. ![Disabled\nJP4\nEnabled\nJP4](.daq-daqe-221x-50m-12267-1000-10/8f1ce29df8783f32bf8b711a2e804a06a42b88d9988f4e82e8313fc934f1ca52.jpg) Figure 2-4: DIO Initial Status (JP4) # 2.5 PCI Configuration # 2.5.1 Plug and Play With support for plug and play, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. # 2.5.2 Configuration The board configuration is done on a board-by-board basis for all PCI boards in the system. Because configuration is controlled by the system and software, there is no jumper setting required for base address, DMA, and interrupt IRQ. The configuration is subject to change with every boot of the system as new boards are added or removed. # 2.5.3 Troubleshooting If your system doesn’t boot or if you experience erratic operation with your PCI board in place, it is likely caused by an interrupt conflict. The BIOS Setup may be incorrectly configured. Consult the BIOS documentation that comes with your system to solve this problem. # 3 Signal Connections This chapter describes the connectors of the DAQ/DAQe-2213/ 2214 and the signal connection between the DAQ/DAQe-2213/ 2214 and external devices. # 3.1 Connector Pin Assignment DAQ/DAQe-2213/2214 is equipped with two 68-pin VHDCI-type connectors (AMP-787254-1) and one 20-pin ribbon male connector. It is used for digital input / output, analog input, and timer/ counter signaling, etc. The pin assignment for the connectors are illustrated below. # 3.1.1 CN1 Connector
AI0 (AIH0)135(AIL0) AI32
AI1 (AIH1)236(AIL1) AI33
AI2 (AIH2)337(AIL2) AI34
AI3 (AIH3)438(AIL3) AI35
AI4 (AIH4)539(AIL4) AI36
AI5 (AIH5)640(AIL5) AI37
AI6 (AIH6)741(AIL6) AI38
AI7 (AIH7)842(AIL7) AI39
NC943NC
NC1044NC
NC1145NC
NC1246NC
NC1347NC
NC1448NC
NC1549NC
NC1650NC
AISENSE1751AIGND
NC1852NC
NC1953NC
NC2054NC
NC2155NC
NC2256NC
NC2357NC
NC2458NC
NC2559NC
NC2660NC
NC2761NC
NC2862NC
NC2963NC
NC3064NC
NC3165NC
NC3266NC
NC3367NC
EXTATRIG3468AIGND
Table 3-1: CN1 Pin Assignment for DAQ/DAQe-2213/2214 \* Symbols in $" ( ) "$ are for differential mode connection. # 3.1.2 CN2 Connector
NC135NC
NC236NC
NC337NC
NC438NC
DGND539DGND
RESERVED640DGND
EXTDTRIG741DGND
SSHOUT842DGND
RESERVED943DGND
RESERVED1044DGND
RESERVED1145DGND
AFI01246DGND
GPTC0_SRC1347DGND
GPTC0_GATE1448DGND
GPTC0_UPDOWN1549DGND
GPTC0_OUT1650DGND
GPTC1_SRC1751DGND
GPTC1_GATE1852DGND
GPTC1_UPDOWN1953DGND
GPTC1_OUT2054DGND
EXTTIMEBASE2155DGND
PB72256PB6
PB52357PB4
PB32458PB2
PB12559PB0
PC72660PC6
PC52761PC4
DGND2862DGND
PC32963PC2
PC13064PC0
PA73165PA6
PA53266PA4
PA33367PA2
PA13468PA0
Table 3-2: CN2 Pin Assignment for DAQ/DAQe-2213
DA0OUT135AOGND
DA1OUT236AOGND
AOEXTREF337AOGND
NC438NC
DGND539DGND
EXTWFTRIG640DGND
EXTDTRIG741DGND
SSHOUT842DGND
RESERVED943DGND
RESERVED1044DGND
AFI11145DGND
AFI01246DGND
GPTC0_SRC1347DGND
GPTC0_GATE1448DGND
GPTC0_UPDOWN1549DGND
GPTC0_OUT1650DGND
GPTC1_SRC1751DGND
GPTC1_GATE1852DGND
GPTC1_UPDOWN1953DGND
GPTC1_OUT2054DGND
EXTTIMEBASE2155DGND
PB72256PB6
PB52357PB4
PB32458PB2
PB12559PB0
PC72660PC6
PC52761PC4
DGND2862DGND
PC32963PC2
PC13064PC0
PA73165PA6
PA53266PA4
PA33367PA2
PA13468PA0
Table 3-3: CN2 Pin Assignment for DAQ/DAQe-2214 CN1/CN2 Connector Signal Description
Signal NameReferenceDirectionDescription
AIGND——Analog ground for AI. All three ground references (AIGND, AOGND, and DGND) are connected together on board.
AI<0..16/95>AIGNDInputAnalog Input Channels 0~16. Each channel pair, AI(i=0..7) can be configured either two single-ended inputs or one differential input pair (marked as AIH<0..8> and AIL<0..8>).
AISENSEAIGNDInputAnalog Input Sense. This pin is the reference for any channels AI<0..16> in NRSE input configuration.
EXTATRIGAIGNDInputExternal AI analog trigger
DA0OUTAOGNDOutputAO channel 0
DA1OUTAOGNDOutputAO channel 1
AOEXTREFAOGNDInputExternal reference for AO channels
AOGND——Analog ground for AO
EXTWFTRIGDGNDInputExternal AO waveform trigger
EXTDTRIGDGNDInputExternal AI digital trigger
RESERVED—OutputReserved. Please leave it open
GPTC<0,1>_SRCDGNDInputSource of GPTC<0,1>
GPTC<0,1>_GATEDGNDInputGate of GPTC<0,1>
GPTC<0,1>_OUTDGNDInputOutput of GPTC<0,1>
GPTC<0,1>_UPDOWNDGNDInputUp/Down of GPTC<0,1>
EXTTIMEBASEDGNDInputExternal Timebase
DGND——Digital ground
PB<7,0>DGNDPIO*Programmable DIO of 8255 Port B
PC<7,0>DGNDPIO*Programmable DIO of 8255 Port C
PA<7,0>DGNDPIO*Programmable DIO of 8255 Port A
Table 3-4: CN1/CN2 Signal Description
Signal NameReferenceDirectionDescription
AFI0DGNDInputAuxiliary Function Input 0 (ADCONV, AD_START)
AFI1DGNDInputAuxiliary Function Input 1 (DAWR, DA_START)
Table 3-4: CN1/CN2 Signal Description # 3.1.3 SSI Connector
SSI_TIMEBASE12DGND
SSI_ADCONV34DGND
RESERVED56DGND
SSI_SCAN_START78DGND
RESERVED910DGND
SSI_AD_TRIG1112DGND
RESERVED1314DGND
RESERVED1516DGND
RESERVED1718DGND
RESERVED1920DGND
Table 3-5: SSI Connector Pin Assignment for DAQ/DAQe-2213
SSI_TIMEBASE12DGND
SSI_ADCONV34DGND
SSI_DAWR56DGND
SSI_SCAN_START78DGND
RESERVED910DGND
SSI_AD_TRIG1112DGND
SSI_DA_TRIG1314DGND
RESERVED1516DGND
RESERVED1718DGND
RESERVED1920DGND
Table 3-6: SSI Connector Pin Assignment for DAQ/DAQe-2214 SSI Connector Signal Description:
SSI Timing SignalSettingFunction
SSI_TIMEBASEMasterSend the TIMEBASE out
SlaveAccept the SSI_TIMEBASE to replace the internal TIMEBASE signal.
SSI_ADCONVMasterSend the ADCONV out
SlaveAccept the SSI_ADCONV to replace the internal ADCONV signal.
SSI_SCAN_STARTMasterSend the SCAN_START out
SlaveAccept the SSI_SCAN_START to replace the internal SCAN_START signal.
SSI_AD_TRIGMasterSend the internal AD_TRIG out
SlaveAccept the SSI_AD_TRIG as the digital trigger signal.
SSI_DAWRMasterSend the DAWR out.
SlaveAccept the SSI_DAWR to replace the internal DAWR signal.
SSI_DA_TRIGMasterSend the DA_TRIG out.
SlaveAccept the SSI_DA_TRIG as the digital trigger signal.
Table 3-7: SSI Connector Legend # 3.2 Analog Input Signal Connection The DAQ/DAQe-2213/2214 provides up to 16 single-ended or 8 differential analog input channels. Users can fill the Channel Gain Queue to get desired combination of the input signal types. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and obtain a more accurate measurement from the A/D conversion, it is important to understand the signal source type and how to choose the analog input modes: RSE, NRSE, and DIFF mode. # 3.2.1 Types of signal sources Floating Signal Sources A floating signal source means it is not connected in any way to the buildings ground system. A device with an isolated output is a floating signal source, such as optical isolator outputs, transformer outputs, and thermocouples. # Ground-Referenced Signal Sources A ground-referenced signal means it is connected in some way to the building system. That is, the signal source is already connected to a common ground point with respect to the DAQ/ DAQe-2213/2214, assuming that the computer is plugged into the same power system. Non-isolated out-puts of instruments and devices that plug into the buildings power system are ground-referenced signal sources. # 3.2.2 Input Configurations Single-Ended Connections A single-ended connection is used when the analog input signal is referenced to a ground that can be shared with other analog input signals. There are two types of single-ended connections: RSE and NRSE. In RSE configuration, the DAQ/ DAQe-2213/2214 board provides the grounding point for the external analog input signals and is suitable for floating signal sources. In the NRSE configuration the board does not provide the grounding point, the external analog input signal provides its own reference grounding point and is suitable for groundreferenced signals. # Referenced Single-ended (RSE) Mode In referenced single-ended mode, all input signals are connected to the ground provided by the DAQ/DAQe-2213/2214. This is suitable for connections with floating signal sources. Figure 3-1 shows an illustration. Note that when more than two floating sources are connected, these sources will be referenced to the same common ground. ![Based on the provided block diagram, here is an accurate and concise description of the blocks and connections:\n\n**1. Floating Signal Source (Left Side)**\n* There is a label **'Floating Signal Source'** pointing to two AC voltage source symbols (circles with sine waves).\n* The sources are labeled **'V1'** and **'V2'**.\n* Below these sources is the text **'n = 0, ..., 15'**.\n\n**2. Input Bus (Middle Left)**\n* A vertical bar represents the input bus.\n * The top portion is labeled **'Aln'**.\n * The bottom-most dot is labeled **'AIGND'**.\n* **Connections:**\n * The positive terminal of **V1** connects to the top dot of the 'Aln' bus.\n * The positive terminal of **V2** connects to the second dot from the top.\n * There are 14 additional horizontal lines connecting to the intermediate dots between the V2 connection and the bottom 'AIGND' dot.\n * A common bottom line connects the negative terminals of **V1** and **V2** to the **'AIGND'** dot.\n\n**3. Muxiplexer (Center)**\n* A rectangular block is labeled **'CN1 Input Muxiplexer'** (note the spelling).\n* It receives inputs from the top 15 dots of the vertical 'Aln' bus.\n\n**4. Instrumentation Amplifier (Right Side)**\n* A triangular block is labeled **'Instrumentation Amplifier'**.\n* The output of the 'CN1 Input Muxiplexer' connects to the non-inverting input ('+') of the amplifier.\n* The inverting input ('-') connects to the common bottom ground line (indicated by a ground symbol).\n\n**5. Output (Far Right)**\n* The output line from the amplifier extends to the right.\n* There is a **'+'** sign above the line and a **'-'** sign below the line end.\n* The text **'To A/D Converter'** is placed above the output line.](.daq-daqe-221x-50m-12267-1000-10/35e18338830757fb78ccd30a04261273a3a5086caa464c7319684beae0043427.jpg) Figure 3-1: Floating Source and RSE Input Connections # Non-Referenced Single-ended (NRSE) Mode To measure ground-referenced signal sources, which are connected to the same ground point, you can connect the signals in NRSE mode. Figure 3-2 illustrates the connection. The signals local ground reference is connected to the negative input of the instrumentation Amplifier (AISENSE pin on CN1 connector), and the common-mode ground potential between signal ground and the ground on board will be rejected by the instrumentation amplifier. ![Based on the provided image, here is the description of the flowchart/block diagram:\n\n**Labeled Blocks and Components:**\n* **Left Side:**\n * 'Ground-Referenced Signal Source'\n * Two AC voltage sources labeled **V1** and **V2**.\n * One AC voltage source labeled **Vcm**.\n * Text: 'Common-mode noise & Ground potential'\n * Text: 'n = 0, ..., 15'\n* **Center:**\n * A rectangular block labeled **Input Multiplexer**.\n * A vertical column of terminals labeled **AIn**.\n * A vertical column of terminals labeled **AISENSE**.\n* **Right Side:**\n * A triangle symbol labeled **Instrumentation Amplifier** (with + and - inputs).\n * Text: 'To A/D Converter'\n\n**Connections:**\n* **V1** connects to the top terminal of the **AIn** block.\n* **V2** connects to the second terminal of the **AIn** block.\n* **Vcm** connects to the bottom terminal of the **AISENSE** block.\n* The output from the **Input Multiplexer** connects to the positive (+) input of the **Instrumentation Amplifier**.\n* The **AISENSE** terminal connects to the negative (-) input of the **Instrumentation Amplifier**.\n* The output line from the **Instrumentation Amplifier** extends to the text 'To A/D Converter'.](.daq-daqe-221x-50m-12267-1000-10/03c6193d8c6411e0867933397bf91fa85e1330dca81d494e66674c22f7fa8602.jpg) Figure 3-2: Ground-referenced Sources and NRSE Input Connections # 3.2.3 Differential Input Mode The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 3-3 shows the connection of ground-referenced signal sources under differential input mode. ![**Blocks and Labels:**\n* **Ground Referenced Signal Source** (AC voltage source symbol)\n* **Common-mode noise & Ground potential** (DC voltage source labeled \$V_{cm}\$ and ground symbol)\n* **x = 0, ..., 7** (Label above the input bus)\n* **A1xH** (Label for the top input line)\n* **A1xL** (Label for the middle input line)\n* **AIGND** (Label for the bottom input line)\n* **Input Multiplexer** (Label above two rectangular blocks)\n* **Instrumentation Amplifier** (Label above a triangle symbol)\n* **To A/D Converter** (Label at the output)\n\n**Connections:**\n* The top terminal of the **Ground Referenced Signal Source** connects to the top input of the vertical bus line, labeled **A1xH**.\n* The bottom terminal of the signal source connects to a node that splits to the top terminal of the **Common-mode noise & Ground potential** source (\$V_{cm}\$) and to the fourth input of the vertical bus line, labeled **A1xL**.\n* The bottom terminal of the \$V_{cm}\$ source connects to a ground symbol.\n* The bottom-most input of the vertical bus line is labeled **AIGND** and connects to a ground symbol.\n* The vertical bus line has eight input dots. The top four dots feed into the upper rectangular block of the **Input Multiplexer**. The bottom four dots feed into the lower rectangular block.\n* The output of the upper multiplexer block connects to the positive (\$+\$) input of the **Instrumentation Amplifier**.\n* The output of the lower multiplexer block connects to the negative (\$-\$) input of the amplifier.\n* The negative (\$-\$) input of the amplifier is connected to a ground symbol.\n* The output of the amplifier connects to the **To A/D Converter**.](.daq-daqe-221x-50m-12267-1000-10/474d42dc4e60749195905fd39c3283381f1542784981a408185ab9933139bf74.jpg) Figure 3-3: Ground-referenced Source and Differential Input # Ground-referenced Source and Differential Input Figure 3-4 shows how to connect a floating signal source to the DAQ/DAQe-2213/2214 in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. If the source impedance is less than 100ohms, you can simply connect the negative side of the signal to AIGND as well as the negative input of the Instrumentation Amplifier without any resistors. In differential input mode, less noise couples into the signal connections than in single-ended mode. ![Ground\nReferenced\nSignal\nSource\nx = 0, ..., 7\nInput Multiplexer\nInstrumentation\nAmplifier\nTo A/D\nConverter\nAIXH\nAIXL\nAIGND\n-](.daq-daqe-221x-50m-12267-1000-10/5869af98014bc501f5f715d223a97fecaaa2ba1cb3708870244419ac90dd8a4f.jpg) Figure 3-4: Floating Source and Differential Input # 4 Operation Theory The operation theory of the DAQ/DAQe-2213/2214 functions are described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O, and general purpose counter/ timer. The operation theory can help you understand how to configure and program the DAQ/DAQe-2213/2214. # 4.1 A/D Conversion When using an A/D converter, you must know about the properties of the signal to be measured. You may decide which channel to use and how to connect the signals to the card. In addition, users should define and control the A/D signal configurations, including channels, gains, and polarities (unipolar/bipolar). The A/D acquisition is initiated by a trigger source and you must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched. After the end of an A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data can now be transferred into the system memory for further processing. Two acquisition modes, Software Polling and Scan acquisition are described below. Timing, trigger modes, trigger sources, and transfer methods are included. # 4.1.1 DAQ/DAQe-2213/2214 AI Data Format The data format of the acquired 16-bit A/D data is two’s complement coding. Table 4-1and Table 4-2 shows the valid input ranges and the ideal transfer characteristics.
DescriptionBipolar Analog Input RangeDigital code
Full-scale Range±10V±5V±2.5V±1.25V—
Least significant bit305.2μV152.6μV76.3μV38.15μV—
FSR-1LSB9.999695V4.999847V2.499924V1.249962V7FFF
Midscale +1LSB305.2μV152.6μV76.3μV38.15μV0001
Midscale0V0V0V0V0000
Midscale -1LSB-305.2μV-152.6μV-76.3μV-38.15μVFFFF
-FSR-10V-5V-2.5V-1.25V8000
Table 4-1: Bipolar Analog Input Range and Output Digital Code
DescriptionUnipolar Analog Input RangeDigital code
Full-scale Range0V to 10V0 to +5V0 to +2.5V0 to +1.25V—
Least significant bit152.6μV76.3μV38.15μV19.07μV—
FSR-1LSB9.999847V4.999924V2.499962V1.249981V7FFF
Midscale +1LSB5.000153V2.500076V1.250038V0.625019V0001
Midscale5V2.5V1.25V0.625V0000
Midscale -1LSB4.999847V2.499924V1.249962V0.624981VFFFF
-FSR0V0V0V0V8000
Table 4-2: Unipolar Analog Input Range and Output Digital Code # 4.1.2 Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled by the software. However, it is difficult to control the A/D conversion rate. # Specifying Channel, Gain, and Input Configurations in the Channel Gain Queue In Software Polling and Programmable Scan Acquisition mode, the channel, gain, polarity, and input configuration (RSE, NRSE, or DIFF) can be specified in the Channel Gain Queue. You can fill the channel number in the Channel Gain Queue in any order. The channel order of acquisition will be the same as the order you set in the Channel Gain Queue. Therefore, you can acquire data with user-defined channel orders and with different settings on each channel. When the specified channels have been sampled from the first data to the last data in the Channel Gain Queue, the settings in Channel Gain Queue are maintained. You do not need to reconfigure the Channel Gain Queue if you want to keep on sampling data in the same order. The maximum number of entries you can set in the Channel Gain Queue is 512. # Example: First you can set entries in Channel Gain Queue:  Ch3 with bipolar ±10V, RSE connection  Ch1 with bipolar ±2.5V, DIFF connection  Ch2 with unipolar 5V, NRSE connection  Ch1 with bipolar ±2.5V, DIFF connection If you read 10 data by software polling method, then the acquisition sequence of channels is 3, 1, 2, 1, 3, 1, 2, 1, 3, 1.... # 4.1.3 Programmable Scan Acquisition Mode Scan Timing and Procedure It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least four counters which need to be specified:  SI\_counter (24-bit): Specify the Scan Interval = SI\_counter / Timebase  SI2\_counter (16-bit): Specify the data Sampling Interval = SI2\_counter/Timebase  PSC\_counter (24-bit): Specify Post Scan Counts after a trigger event  NumChan\_counter (9-bit): Specify the number of samples per scan The acquisition timing and the meanings of the 4 counters are illustrated in Figure 4-1. # TIMEBASE Clock Source IIn scan acquisition mode, all the A/D conversions start on the output of counters, which use Timebase as the clock source. With software users can specify the Timebase to be either an internal clock source (onboard 40MHz) or an external clock input (EXTTIMEBASE) on CN2. The external clock is useful when you want to acquire data at rates not available with the internal A/D sample clock. The external clock source should generate TTL-compatible continuous clocks, and the maximum frequency is 40MHz while the minimum is 1MH. Refer to section 4.6 for information on user-controllable timing signals. ![| Signal Event | Channel Sequence | Timeframe Labels |\n|--------------|------------------|-------------------|\n| Scan_start | Ch2 | |\n| Scan_start | Ch3 | |\n| AD_conversion | Ch1 | |\n| AD_conversion | Ch0 | |\n| SSHOUT | Ch2 | |\n| SSHOUT | Ch3 | |\n| Acquisition | Ch1 | |\n| Acquisition | Ch0 | |\n| Sampling | | |\n| Sampling | | SI2_COUNTER/TimeBase |\n| Scan Interval | | SI2_COUNTER/TimeBase |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |\n| Channel Sequence | Channel Gains | |](.daq-daqe-221x-50m-12267-1000-10/82b5e53dec04ab980b0752eb7682b5c75d6cc00cc4d4b0dbcbdf21d1e195ebac.jpg) Figure 4-1: Scan Timing There are four trigger modes to start the scan acquisition. Refer to section 4.1 for details. The data transfer mode is discussed in the following section. ![The image displays an icon of a white document with faint grey horizontal lines. A large, bold red checkmark is superimposed diagonally over the document.](.daq-daqe-221x-50m-12267-1000-10/611868ae21659ea9d88af35fff042e8974c40b495139b9171eb215da9334ecf7.jpg) NOTE: 1. The maximum A/D sampling rate is 250kHz. Therefore, the minimum setting for SI2\_counter is 160 while using the internal Timebase. 2. The SI\_counter is a 24-bit counter and the SI2\_counter is a 16-bit counter. Therefore, the maximum scan interval using the internal Timebase = 224/40Ms = 0.419s, and the maximum sampling interval between 2 channels using the internal Timebase = 216/40Ms = 1.638ms. 3. The scan interval cannot be smaller than the product of the data sam- pling interval and the NumChan\_counter value. The relationship can be represented as: SI\_counter>=SI2\_counter \* NumChan\_counter. # Scan with SSH You can send the SSHOUT signal on CN2 to external S&H circuits to sample and hold all signals if you want to simultaneously sample all channels in a scan, as illustrated in Figure 4-1. ![The image shows a white document icon with a folded top-right corner. Several horizontal gray lines represent text on the page, and a large red checkmark is superimposed over the center.](.daq-daqe-221x-50m-12267-1000-10/b94d3ea407e5d95970d8c077f6040db1e2a5b20cd757d9a245bd633e65b86792.jpg) NOTE: The ‘SSHOUT’ signal is sent to external S&H circuits to hold the analog signal. Users must implement external S&H circuits on their own to carry out the S&H function. There are no onboard S&H circuits. # 4.1.4 Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue Like software polling acquisition mode, the channel, gain, and input configurations can be specified in the Channel Gain Queue under the scan acquisition mode. Note that in scan acquisition mode, the number of entries in the Channel Gain Queue is normally equivalent to the value of NumChan\_counter (that is, the number of samples per scan). # Example: # Set  SI2\_counter = 160  SI\_counter = 640  PSC\_counter = 3  NumChan\_counter = 4  Timebase = Internal clock source  Channel entries in the Channel Gain Queue: ch1, ch2, ch0, ch2 # Then  Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2  Sampling interval: 160/40 Ms = 4 µs  Scan interval: 640/40 Ms = 16 µs  Equivalent sampling rate of ch0, ch1: 62.5 kHz  Equivalent sampling rate of ch2: 125 kHz # 4.1.5 Trigger Modes DAQ/DAQe-2213/2214 provides 3 trigger sources (internal software, external analog, and digital trigger sources). Only select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source (For example, a rising edge on the external digital trigger input). There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger, and delay-trigger) working with the 4 trigger sources to initiate different scan data acquisition timing when a trigger event occurs. For information of trigger sources, refer to section 4.5. # Pre-Trigger Acquisition Use pre-trigger acquisition in applications to collect data before a trigger event. The A/D starts when the specified function calls are executed to begin the operation, and it stops when the external trigger event occurs. Users must program the value M in M\_counter (16 bits) to specify the amount of stored scanned data before the trigger event. If an external trigger occurs after M scans of data are converted, the program only stores the last M scans of data, as illustrated in Figure 4-2, where M\_counter = M = 3, NumChan\_counter = 4, PSC\_counter = 0. The total stored amount of data = NumChan\_counter \*M\_counter = 12. ![(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nAquired data\nAcquired & stored data\n(M scans)](.daq-daqe-221x-50m-12267-1000-10/f64ac7f6e408f201d91e95453839637840bcacdfcb283faa46f423fc43ad21eb.jpg) Figure 4-2: Pre-trigger (Trigger occurs after M scans) Note that if a trigger event occurs when a scan is in progress, the data acquisition won't stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan\_counter), no matter when a trigger signal occurs, as illustrated in Figure 4-3, where M\_counter = M =3, NumChan\_counter = 4, PSC\_counter = 0. ![(M_counter = M = 3, NumChan_counter =4, PSC_counter=0)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nTrigger occurs\nData acquisition\nwon't stop until a\nscan completes\nAquired data\nAcquired & stored data\n(M scans)](.daq-daqe-221x-50m-12267-1000-10/a90e6610e1a8e207963f8b9c56a1b3e35da2debfe7ffa5e1e4335dac7feff1f2.jpg) Figure 4-3: Pre-trigger (Trigger with scan in progress) When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the originally specified amount M\_counter, as illustrated in Figure 4-4. This situation can be avoided by setting M\_enable. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-5. However, if M\_enable is set to 0, the trigger signal will be accepted any time, as shown in Figure 4-4. Note that the total amount of stored data is still always a multiple of NumChan\_counter (number of samples per scan) because the data acquisition won’t stop until a scan is completed. ![| Operation Start | Trigger | Scan_start | AD_conversion | Scan_in_progress (SSHOUT)(pin8 on CN2) | Acquisition_in_progress |\n| --------------- | ------- | ---------- | ------------- | ------------------------------------- | ----------------------- |\n| Operation start | - | - | - | - | - |\n| Operation start | - | - | - | - | - |\n| Operation start | - | - | - | - | - |\n| Operation start | - | - | - | - | - |\n| Operation start | - | - | - | - | - |\n| Operation start | - | - | - | - | - |\n| Operation start (Acquired & stored data) (2 scans) | - | - | - | - | - |\n| Operation start (Acquired & stored data) (2 scans) (Operation start) | - | - | - | - | - |\n| Operation start (Acquired & stored data) (2 scans) (Operation start) | - | - | - | - | - |\n| Operation start (Acquired & stored data) (2 scans) (Operation start) (Acquired & stored data) (2 scans) (Operation start) | - | - | - | - | - |\n| Operation start (Acquired & stored data) (2 scans) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data) (Operation start) (Acquired & stored data)](.daq-daqe-221x-50m-12267-1000-10/6937fd40ebc829c33d77d37c8a9269d9fa4c103359dc5bb426c442e5fa427aca.jpg) Figure 4-4: Pre-trigger with M\_enable=0 (Trigger occurs before M scans) (M\_counter = M = 3, NumChan\_counter=4, PSC\_counter=0) ![The first M scans\nTrigger signals which occur in the shadow region(the first M scans) will be ignored\nTrigger\nScan_start\nAD_conversion\nScan_in_progress (SSHOUT)(pin2 on CN2)\nAcquisition_in_progress\nAquired data\nAcquired & stored data (M scans)\nOperation start](.daq-daqe-221x-50m-12267-1000-10/d9828ce627dabe0273646ba1d57fd524a6a4dbfc903ef79ce13c120757f3af0e.jpg) Figure 4-5: Pre-trigger with M\_enable=1 ![The image displays a document icon featuring a white sheet of paper with several horizontal black lines. A large, bold red checkmark is superimposed over the left side of the document.](.daq-daqe-221x-50m-12267-1000-10/9f3a8bd42e7d3f6fdd1c0666a9ff73cb87a224d3ad705240b63bfc285338f81f.jpg) NOTE: The PSC\_counter is set to 0 in pre-trigger acquisition mode. # Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified by M\_counter, while the number of scans (N) after the trigger is specified by PSC\_counter. Like pre-trigger mode, the number of stored data could be less than the specified amount of data (NumChan\_counter \*(M+N)), if an external trigger occurs before M scans of data are converted. The M\_enable bit in middle-trigger mode takes the same effect as in pre-trigger mode. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user with (M+N) scans of data under middle-trigger mode. However, if M\_enable is set to 0, the trigger signal will be accepted at any time. Figure 4-6 shows the acquisition timing with M\_enable=1. ![**Header:**\n* `(M_Counter=M=3, PSC_Counter=N=1)`\n\n**Signal Labels (Left Side):**\n* `Trigger`\n* `Scan_start`\n* `ADCONV`\n* `Acquisition_in_progress`\n* `Post Scan Count`\n\n**Annotations and Waveforms:**\n* **Trigger Line:** Features a hatched shaded region labeled with an arrow `The first M scans`. Text annotation points to this region: `Triggers signals which occur in the shadow region (the first M scans) will be ignored`. The line shows pulses corresponding to the shaded region, a single pulse, and another pulse later.\n* **Scan_start & ADCONV:** Both show a series of periodic pulses (upward for Scan_start, downward for ADCONV).\n* **Acquisition_in_progress:** A signal line that goes high and remains high for a duration before dropping low.\n* **Post Scan Count:** Shows a value of `1` which drops to `0`. The value `0` aligns with the final pulse in the sequence.\n\n**Bottom Annotations and Connections:**\n* **Vertical Dashed Lines:** Drop down from the 3rd, 4th, and 5th `Scan_start` pulses, connecting them to the timeline below.\n* **Horizontal Arrows:**\n * `Acquired data`: Spans the region between the vertical dashed lines from the 3rd and 5th `Scan_start` pulses.\n * `M scans before trigger`: Spans the region to the left of the trigger pulse.\n * `N scans after trigger`: Spans the region to the right, starting from the 5th `Scan_start` pulse.\n* **Text Labels:**\n * `Operation start`\n * `Acquired & stored data (M+N scans)` with a long arrow spanning the entire duration from the start of the acquisition to the end.](.daq-daqe-221x-50m-12267-1000-10/d7adf759c20438c8822b68362d597e223fd9973ddb2a9eccd03d3156825d513e.jpg) Figure 4-6: Middle-Trigger with M\_enable = 1 If a trigger event occurs when a scan is in progress, the stored N scans of data would include this scan. The first stored data will always be the first channel entry of a scan, as illustrated in Figure 4-7. ![(M Counter=M=2, PSC Counter=N=2)\nTrigger occurs when a scan is in progress\nTrigger\nScan start\nADCONV\nAcquisition_In_progress\nPost Scan Count 2\n1 0\nAcquired data\nM scans before\nligger\nN scans at and\nafter ligger\nOperation start\nAcquired & stored data\n(M+N scans)](.daq-daqe-221x-50m-12267-1000-10/98128de28de7c7f3a436ee1e4cee2b9327316c0e3c09a06e63c33547c9107a1c.jpg) Figure 4-7: Middle-Trigger (Trigger occurs when a scan is in progress) # Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC\_counter, as illustrated in Figure 4-8. The total acquired data length = NumChan\_counter \* PSC\_counter. ![(NumChan_Counter=4, PSC_Counter=3)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(3 scans)](.daq-daqe-221x-50m-12267-1000-10/25efcf20de8198c04ea43045d1cb74b1dc029f7ddac3730e3202ff2e24e2bec4.jpg) Figure 4-8: Post-trigger # Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay\_counter (16 bits). The counter counts down on the rising edge of the Delay\_counter clock source after the trigger condition is met. The clock source can be software-programmed either by the TIMEBASE clock (40 MHz) or A/D sampling clock (TIMEBASE / SI2\_counter). When the count reaches 0, the counter stops and the card starts to acquire data. The total acquired data length = NumChan\_counter \* PSC\_counter. ![The image displays a timing diagram with the header text '(NumChan_Counter=4, PSC_Counter=3)'.\n\nOn the left side, five signal labels are listed vertically:\n* Trigger\n* Scan_start\n* AD_conversion\n* Scan_in_progress (SSHOUT)(pin8 on CN2)\n* Acquisition_in_progress\n\nAt the bottom, two horizontal arrows indicate time intervals with the following labels:\n* The left arrow reads 'Delay until Delay_Counter reaches 0'.\n* The right arrow reads 'Acquired & stored data (3 scans)'.\n\nA vertical dashed line is labeled 'Operation start' at the bottom left.](.daq-daqe-221x-50m-12267-1000-10/2df47cc4052997531da1ab8779b6b34ba9c1f0032bdb10d71fc32e76399db34c.jpg) Figure 4-9: Delay trigger ![The image displays a white document icon with a folded top-left corner and faint horizontal lines running across the lower section. A large, bold red checkmark is superimposed diagonally across the center of the paper, extending from the bottom left to the top right.](.daq-daqe-221x-50m-12267-1000-10/1748284a343eb4ab541cd8f28c6dd1f85d3bb18ddbb47dacb264f54cedc3724d.jpg) NOTE: When the Delay\_counter clock source is set to Timebase, the maximum delay time $= 2 ^ { 1 6 } / 4 0 \mathsf { M s } = 1 . 6 3 8 \mathsf { m s }$ , and when set to A/D sampling clock, the maximum delay time can be higher $( 2 ^ { 1 6 \star } \mathsf { S } | 2$ \_counter/40M ). # Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC\_counter, and users could program Retrig\_no to specify the re-trigger numbers. Figure 4-10 illustrates an example. In this example, two scans of data is acquired after the first trigger signal, then the card waits for the re-trigger signal (re-trigger signals which occur before the first two scans is completed will be ignored). When the re-trigger signal occurs, two more scans are performed. The process repeats until specified amount of re-trigger signals are detected. The total acquired data length = NumChan\_counter \* PSC\_counter \* Re-trig\_no. ![(NumChan Counter=4, PSC Counter=2, retrig_no=3)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(6 scans)](.daq-daqe-221x-50m-12267-1000-10/2dd85c6a7341077f4e066e60d3e0e7af28a9c21dd38d0748c87324c07203291b.jpg) Figure 4-10: Post trigger with Re-trigger # 4.1.6 Bus-mastering DMA Data Transfer In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI busmastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention. Bus-mastering DMA provides the fastest data transfer rate on a PCI bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a userdefined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA. The DMA transfer mode is very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a high-level programming library for high speed DMA data acquisition, you convert through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA. The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list. In a multi-user or multitasking OS, like Windows or Linux, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the non-continuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-6 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address cycle support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs. ![**Labeled Blocks:**\n\n* **Local Memory (FIFO)**\n* **PCI Bus**\n* **Top-Left Block:**\n * First PCI Address\n * First Dual Address\n * Transfer Size\n * Next Descriptor\n* **Top-Middle Block:**\n * PCI Address\n * Dual Address\n * Transfer Size\n * Next Descriptor\n* **Top-Right Block:**\n * PCI Address\n * Dual Address\n * Transfer Size\n * Next Descriptor\n\n**Connections:**\n\n* An arrow points upward from **Local Memory (FIFO)** to **PCI Bus**.\n* An arrow points upward from **PCI Bus** to the **Top-Middle Block**.\n* An arrow points to the right from the **Top-Left Block** to the **Top-Middle Block**.\n* An arrow points to the right from the **Top-Middle Block** to the **Top-Right Block**.](.daq-daqe-221x-50m-12267-1000-10/6e0a2f4eefdb620146459e6d0cdf1edadb4359575e0f21ac5b199a9ed11e12d0.jpg) Figure 4-11: Linked List of PCI Address DMA Descriptors In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multibuffered mode DMA. # 4.2 D/A Conversion (for DAQ/DAQe-2214 only) There are two 12-bit D/A output channels available in the DAQ/ DAQe-2214. When using D/A converters, you should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. You could also set the output polarity to unipolar or bipolar. The reference selection control lets you utilize in full the multiplying characteristics of the D/A converters. Internal 10V reference and external reference inputs are available in the DAQ/DAQe-2214. The range of the D/A output is directly related to the reference. The digital codes that are updated to the D/A converters will multiply with the reference to generate the analog output. While using internal 10V reference, the full range would be –10V to +9.9951V in the bipolar output mode, and 0V to 9.9976V in the unipolar output mode. While using an external reference, you can reach different output ranges by connecting different references. For example, if connecting a DC –5V with the external reference, then you can get a full range from –4.9976V to +5V in the bipolar output with inverting characteristics due to the negative reference voltage. You could also have an amplitude modulated (AM) output by feeding a sinusoidal signal into the reference input. The range of the external reference should be within ±10V. Table 4-3 and Table 4-4 illustrates the relationship between digital code and output voltages with Vref=10V and if internal reference is selected.
Digital CodeAnalog Output
111111111111Vref * (2047/2048)
100000000001Vref * (1/2048)
1000000000000V
01111111111-Vref * (1/2048)
000000000000-Vref
Table 4-3: Bipolar Output Code Table (Vref=10V if internal reference is selected)
Digital CodeAnalog Output
11111111111Vref * (4095/4096)
100000000000Vref * (2048/4096)
000000000001Vref * (1/4096)
0000000000000V
Table 4-4: Unipolar Output Code Table (Vref=10V if internal reference is selected) The D/A conversion is initiated by a trigger source. You must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from the computer’s main memory to a buffering Data FIFO. Two D/A conversion modes are available: Software Update and Timed Waveform Generation. These are described below, including the timing, trigger source control, trigger modes, and data transfer methods. Either mode may be applied to D/A channels independently. You can simultaneously software update DA CH0 while generating timed waveforms on CH1. # 4.2.1 Software Update This is the easiest way to generate D/A output. To do this: 1. Specify the D/A output channels. 2. Set output polarity (unipolar or bipolar) and reference source (internal 10V or external AOEXTREF). 3. Update the digital values into D/A data registers through a software output command. # 4.2.2 Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters. The D/A output timing is provided through a combination of counters in the FPGA on board. There are a total of five counters to be specified. These counters include:  UI\_counter (24 bits): specify the DA update interval is equal to CHUI\_counter/TIMEBASE  UC\_counter (24 bits): specify the total update counts in a single waveform  IC\_counter (24 bits): specify the iteration counts of waveform  DA\_DLY1\_counter (16 bits): specify the delay from the trigger to the first update start  DA\_DLY2\_counter (16 bits): specify the delay between two consecutive waveform generations Figure 4-12 shows a typical D/A timing diagram assuming the data in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on each rising edge of DAWR. The meaning of the counters enumerated above are discussed in the following sections. ![| Signal Event | Description | Value |\n|--------------|---------------------------------|-------|\n| Trigger | UCRuver | 4 |\n| DAWR | UCRuver | 4 |\n| WFG_in_progress | Delay until DLY1_Counter reaches 0 | 0 |\n| Output Waveform | DA update_interval t= UI_Counter/Timebase | 4 |\n| Operation start | IC_Counter = 3 | -4 |](.daq-daqe-221x-50m-12267-1000-10/aedbd1fd5cf527a73f8b9e46f9f5fddc43b61798892e7cc6f06257381cc614b6.jpg) Figure 4-12: Typical D/A Timing of Waveform Generation ![The image displays a graphic of a white document or piece of paper with the top right corner folded over. The paper features several horizontal gray lines, suggesting text. Superimposed over the document is a large, bold red checkmark that extends diagonally from the bottom left to the upper right.](.daq-daqe-221x-50m-12267-1000-10/a19dea3c32ccdb0afd7947d8f37c56c40f6d329e573b744644fb7d87eea97e3c.jpg) NOTE: The maximum D/A update rate is 1MHz. Therefore; the minimum setting of UI\_counter is 40 while using the internal Timebase (40MHz). # 4.2.3 Trigger ModesPost-Trigger Generation Use post-trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1\_Counter is ignored and not be specified. Figure 4-13 shows a single waveform generated right after a trigger signal is detected and assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. The trigger signal could come from a software command, an analog trigger or a digital trigger. Refer to section 4.5 for detailed information. ![| Operation start | Trigger | DAWR | WFG_in_progress | Output Waveform |\n| --------------- | ------- | ---- | --------------- | ---------------- |\n| 0 | 0 | 0 | 0 | 0 |\n| 1 | 0 | 0 | 0 | 0 |\n| 2 | 0 | 0 | 0 | 0 |\n| 3 | 0 | 0 | 0 | 0 |\n| 4 | 0 | 0 | 0 | 0 |\n| 5 | 0 | 0 | 0 | 0 |\n| 6 | 0 | 0 | 0 | 0 |\n| 7 | 0 | 0 | 0 | 0 |\n| 8 | 0 | 0 | 0 | 0 |\n| 9 | 0 | 0 | 0 | 0 |\n| 10 | 0 | 0 | 0 | 0 |\n| 11 | 0 | 0 | 0 | 0 |\n| 12 | 0 | 0 | 0 | 0 |\n| 13 | 0 | 0 | 0 | 0 |\n| 14 | 0 | 0 | 0 | 0 |\n| 15 | 0 | 0 | 0 | 0 |\n| 16 | 0 | 0 | 0 | 0 |\n| 17 | 0 | 0 | 0 | 0 |\n| 18 | 0 | 0 | 0 | 0 |\n| 19 | 0 | 0 | 0 | 0 |\n| 20 | 0 | 0 | 0 | 0 |\n| 21 | 0 | 0 | 0 | 0 |\n| 22 | 0 | 0 | 0 | 0 |\n| 23 | 0 | 0 | 0 | 0 |\n| 24 | 0 | 0 | 0 | 0 |\n| 25 | 0 | 0 | 0 | 0 |\n| 26 | 0 | 0 | 0 | 0 |\n| 27 | 0 | 0 | 0 | 0 |\n| 28 | 0 | 0 | 0 | 0 |\n| 29 | 0 | 0 | 0 | 0 |\n| 30 | 0 | 0 | 0 | 0 |\n| Note: The actual values for Trigger, DAWR, WFG_in_progress, Output Waveform are not provided in the code. The values for each waveform are labeled as '2' or '4'. The numbers inside the waveform are '6', '3', '4' above the corresponding lines. The '4' line is also labeled '4'.](.daq-daqe-221x-50m-12267-1000-10/69dc52ac61c0ebf944ae96ae4b6ffae5e388a0994ecf5ae7260fba8509db987d.jpg) Figure 4-13: Post Trigger Waveform Generation # Delay-Trigger Generation Use delay trigger when you want to delay the waveform generation after a trigger event. In Table 4-14, DA\_DLY1\_counter determines the delay time from the trigger signal to the start of the waveform generation, assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. DLY1\_counter counts down on the rising edge of its clock source after the trigger condition is met. When the count reaches 0, the counter stops and the DAQ/DAQe-2214 card starts the waveform generation. This DLY1\_Counter is 16-bit wide and you can set the delay time in units of TIMEBASE (delay time = DLY1\_Counter/TIME-BASE) or in units of update period (delay time = DLY1\_Counter \* UI\_counter/TIMEBASE), so the delay time can reach a wider range. ![8 update counts, 1 iterations\nTrigger\n(UC Counter=8, IC Counter=1)\nDAWR\nWFG_in_progress\nOutput Waveform\nDelay until\nDLY1 counter\nreaches 0\nOperation start](.daq-daqe-221x-50m-12267-1000-10/fbbd1c4c83384dbc2e1b89a6bf96f421a6a822ad821dd462794541eede8d92f8.jpg) Figure 4-14: Delay Trigger Waveform Generation # Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-15, each trigger signal will initiate a waveform generation assuming the data in the data buffer are 2V, 4V, 2V, and 0V. However, the trigger event would be ignored while the waveform generation is ongoing. ![4 update counts, 2 iterations\n(UC_Co#nter=4, IC_Co#nter=2) Ignored\nTrigger\nDAWR\nWFG_in_progress\nOutput Waveform\nOperatb start\nCall software stop\nfunction to terminate\nretrigger mode\nwave form generation](.daq-daqe-221x-50m-12267-1000-10/28851b2f284e544eb5a8d8e9ec2f16ff32c860481342aa48735237545479a5e0.jpg) Figure 4-15: Re-triggered Waveform Generation with Post-Trigger (DLY2\_Counter=0) # Iterative Waveform Generation Set IC\_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number and the iterations may be finite (Figure 4-16) or infinite (Figure 4-17). Take note that in infinite mode the waveform generation does not stop until software stop function is executed and IC\_Counter is still valid when stop mode III is selected. Both figures assume that the data in the data buffer are 2V, 4V, 2V, and 0V. An onboard data FIFO is used to buffer the digital data for DA output. If the data size of a single waveform you specified (That is, Update Counts in UC\_counter) is less than the FIFO size, after initially transferring the data from the host PC memory to the FIFO on board, the data in the FIFO will be automatically re-transmitted whenever a single waveform is completed. Therefore, it does not occupy the PCI bandwidth when repetitive waveforms are performed. However, if the size of a single waveform were larger than that of the FIFO, it needs to be intermittently loaded from the host PC’s memory via DMA, when a repetitive waveforms is performed thus PCI bandwidth would be occupied. The data FIFO size on the DAQ/DAQe-2214 is 1024 (words) when one DA channel is enabled, or 512 (words) when both DA channels are enabled. ![4 update counts, 3 iterations\n(UC _Counter=4, IC Counter=3)\nTrigger\nDAWR\nWFG_in_progress\nOutput Waveform\nOperation start\nA single waveform](.daq-daqe-221x-50m-12267-1000-10/cb01b6f549415323456c0fbaa454bc16d1e581d17dc0f3514f980fb5090e1159.jpg) Figure 4-16: Finite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0) ![| Signal | Event Description |\n|-----------------|----------------------------------------|\n| Trigger | Trigger event with step |\n| DAWR | Waveform generator starting |\n| WFG_h_progress | Waveform generator starting |\n| Output Waveform | Waveform generator starting |\n| Operation start | Operation start |](.daq-daqe-221x-50m-12267-1000-10/d2268bf371b954dce6b05783f4557dea8df44341f6c1695cd123f5113e6f1786.jpg) Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0) # Delay2 in Iterative Waveform Generation To stretch out the flexibility of the D/A waveform generation, we add a DLY2\_Counter to separate two consecutive waveforms in iterative waveform generation. The time between two waveforms is assigned by setting the value of the DLY2\_Counter. The DLY2\_Counter starts to count down after a waveform generation finishes and the next waveform generation starts right after it counts down to zero, as shown in Figure 4-18. This DLY2\_Counter is 16-bit wide and you may set the delay time in unit of TIMEBASE (delay time = DLY2\_Counter/TIMEBASE) or in unit of update period (delay time = DLY2\_Counter \* UI\_Counter/TIMEBASE), so the delay time can reach a wider range. # Stop Modes of Scan Update You can call software stop function to stop waveform generation when it is still in progress. Three stop modes are provided for timed waveform generation meant to stop the waveform generation. You can apply these three modes to stop waveform generation no matter infinite or finite waveform generation mode is selected. Figure 4-18 illustrates an example for stop mode I, assuming the data in the data buffer are 2V, 4V, 2V, and 0V. In this mode, the waveform stops immediately when software command is asserted. ![| Signal | Value |\n| ------------------ | ----- |\n| Trigger | 1 |\n| DAWR | 1 |\n| WFG_In_progress | 1 |\n| Output Waveform | ? |\n| Operation start | 0 |\n| Software stop command | 1 |](.daq-daqe-221x-50m-12267-1000-10/1f1fdc3fa216a3c5322a0fdd637e405f0a0148633c12243bf80800806b572029.jpg) Figure 4-18: Stop Mode I In stop mode II, after a software stop command is given, the waveform generation does not stop until a complete single waveform is finished. See Figure 4-19. Since the UC\_counter is set to four, the total DA update counts (number of pulses of DAWR signal) must be a multiple of four (update counts = 20 in this example). ![| Signal | Event Description |\n|-----------------|----------------------------------------|\n| Trigger | Trigger event pulses |\n| DAWR | Diagonal waveform with square pulses |\n| WFG_h_progress | Diagonal waveform with square pulses |\n| Output Waveform | Waveform pulses with square pulses |\n| Operation start | Operatu start |\n| Software stop command | Software stop command |](.daq-daqe-221x-50m-12267-1000-10/1bf13f15eec125794a6e72e6194082022b3b00893eee44294f3ff68d4a26f4b8.jpg) Figure 4-19: Stop Mode II In stop mode III, after a software stop command is given, the waveform generation does not stop until the performed number of waveforms is a multiple of the IC\_Counter. See Figure 4-20. Since the IC\_Counter is set to three, the total generated waveforms must be a multiple of three (waveforms = 6 in this example), and the total DA update counts must be a multiple of 12 (UC\_counter \* IC\_Counter). ![| Signal | Value |\n|-----------------|-------|\n| Trigger | High |\n| DAWR | Low |\n| WFG_In_progress | Low |\n| Output Waveform | Low |](.daq-daqe-221x-50m-12267-1000-10/9df2931c333bdf523cd8a96264230ffbc1c3a54b93cea00a9748a8c82d0d278b.jpg) Figure 4-20: Stop Mode III # 4.3 Digital I/O The DAQ/DAQe-2213/2214 contains 24-lines of general-purpose digital I/O (GPIO), which are provided through an 82C55A chip. The 24-lines GPIO are separated into three ports: Port A, Port B, and Port C. Port A, Port B, Port C high nibble (bit-4 to bit-7), and low nibble (bit 0 to bit 3) can be programmed to be input or output individually. At system startup and reset, all the I/O pins are all reset to be input configuration, that is, high impedance. # 4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following features:  Count up/down controlled by hardware or software  Programmable counter clock source (internal or external clock up to 10 MHz)  Programmable gate selection (hardware or software control)  Programmable input and output signal polarities (high active or low active)  Initial count can be loaded from software  Current count value can be read-back by software without affecting circuit operation # 4.4.1 The Basics of Timer/Counter Functions Each timer/counter has three inputs that can be controlled via hardware or software: clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UPDOWN). The GPTC\_CLK input provides a clock source input to the timer/ counter. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UPDOWN input controls whether the counter counts up or down. The GPTC\_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications. The output of timer/counter is GPTC\_OUT. After power-up, GPTC\_OUT is pulled high by a pull-up resister about 10kΩ. Then GPTC\_OUT goes low after the DAQ/DAQe-2213/2214 initialization. All the polarities of input/output signals can be programmed by software. In this chapter, for easier explanation, GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT are assumed to be active high or rising-edge triggered in the figures. # 4.4.2 General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the software-start is re-executed. The operating theories under different modes are described in the following sections. # Mode 1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC\_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software any time without affecting the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-21 illustrates the operation with initial count = 5, countdown mode. ![| Count value | Gate | CLK |\n| ----------- | ---- | --- |\n| 5 | | |\n| 5 | | |\n| 4 | | |\n| 3 | | |\n| 2 | | |\n| 1 | | |\n| 1 | | |\n| 0 | | |\n| ffff | | |](.daq-daqe-221x-50m-12267-1000-10/af9198dd66a08a2f918f858a6515b7257794d13ed226e204299c2b09b984f2d9.jpg) Figure 4-21: Mode 1 Operation # Mode 2: Single Period Measurement In this mode, the counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by software. Figure 4-22 illustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-221x-50m-12267-1000-10/4243d22f595765682da78e7837416601adedd92d3824d4c00648d3039164de02.jpg) Figure 4-22: Mode 2 Operation # Mode 3: Single Pulse-width Measurement In this mode, the counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT outputs high, then current count value can be read-back by software. Figure 4-23 illustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-221x-50m-12267-1000-10/6d3460998e6a9de1bcce32d1e16000401dc192d6a5bf9771990e4234b68ef68e.jpg) Figure 4-23: Mode 3 Operation # Mode 4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC\_CLK input by software. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-24 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|------------|-------|\n| Gate | 2 |\n| CLK | 2 |\n| Count value| 2 |\n| OUT | 2 |](.daq-daqe-221x-50m-12267-1000-10/98b5a7a5d0c3ee4c7075e5f9c895935cbedad1464896ac978c91ccc83009331c.jpg) Figure 4-24: Mode 4 Operation # Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC\_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC\_CLK input. Once the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until the software-start is re-executed. Figure 4-25 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|------------|-------|\n| Gate | 1 |\n| CLK | 2 |\n| Count value| 2 |\n| OUT | 1 |](.daq-daqe-221x-50m-12267-1000-10/1743b171d4376fdefe21edc6d1a74bada9b3fe3de8d9361367da374950691b3f.jpg) Figure 4-25: Mode 5 Operation # Mode 6: Re-triggered Single Pulse Generation This mode is similar to Mode 5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After the software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE triggers that occur when the prior pulse is not completed would be ignored. Figure 4-26 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four. ![Software start\nGate\nCLK\nCount value 2 2 1 0 3 2 1 0 2 2 1 0 3 2 1 0 2 2\nOUT\nIgnored](.daq-daqe-221x-50m-12267-1000-10/7a18ba280a6cb219f591c7005fca633af0d80100369a47c4555f073c154a7c91.jpg) Figure 4-26: Mode 6 Operation # Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. Once the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until the software-start is re-executed. Figure 4-27 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value 4 4 3 2 1 0 2 1 0 3 2 1 0 2 1 0 3 2\nOUT](.daq-daqe-221x-50m-12267-1000-10/afe119d62f4a6562e55b0705c6d2bd7c93fee73a9e91ac01514aa876e11ec6a6.jpg) Figure 4-27: Mode 7 Operation # Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-28 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value + + 3 3 2 1 0 2 1 0 3 2 1 0 2 1 1 0 3\nOUT](.daq-daqe-221x-50m-12267-1000-10/f41f1a51fe8687d29de24677771f24d5eb035072f74429d099cedf3b1524158b.jpg) Figure 4-28: Mode 8 Operation # 4.5 Trigger Sources ADLINK provides flexible trigger selections in the DAQ/DAQe-2213/2214. In addition to the internal software trigger, the DAQ/ DAQe-2213/2214 also supports external analog, digital triggers, and SSI triggers. You can configure the trigger source by software for A/D and D/A processes individually. # 4.5.1 Software-Trigger This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function calls to begin the operation. # 4.5.2 External Analog Trigger The analog trigger circuitry routing is shown in Figure 4-29. The analog multiplexer can select either a direct analog input from the EXTATRIG pin (SRC1 in Figure 4-29) in the 68-pin connector CN1 or the input signal of ADC. (The first channel input filled in the Channel Gain Queue.) SRC1 can be used for all trigger modes while SRC2 can only be used for post and delay trigger modes. The range of trigger level for SRC1 is ±10V and the resolution is 78mV (refer to Table 4-4), while the trigger range of SRC2 is the full-scale range of the first channel input in Channel Gain Queue, and the resolution is the desired range divided by 256. For example, if the first channel input in Channel Gain Queue is CH0 with bipolar ±5V range, the trigger voltage would be 4.96V when the trigger level code is set to 0xFF while –4.96V when the code is set to 0x01. ![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Blocks:**\n* **CN1 Input Multiplexer**: A vertical bar on the far left acting as an input interface.\n* **Instrumentation Amplifier**: A triangular block.\n* **A/D Converter**: A rectangular block.\n* **MUX**: A rectangular block.\n* **Analog Trigger Circuit**: A rectangular block.\n\n**Connections and Labels:**\n* **CN1 Input Multiplexer**: This section has inputs labeled **AIn** and **n = 0, ..., 15** which feed into a rectangular switch component. The output of this switch connects to the **Instrumentation Amplifier**.\n* **Instrumentation Amplifier**: The output of this amplifier connects to the **A/D Converter**.\n* **SRC2**: A signal line branches off from the connection between the Instrumentation Amplifier and the A/D Converter, labeled **SRC2**, and enters the **MUX** block.\n* **EXTATRIG**: An input at the bottom of the vertical bar labeled **EXTATRIG** connects via a line labeled **SRC1** into the **MUX** block.\n* **MUX**: The **MUX** block receives inputs **SRC2** and **SRC1** and its output connects to the **Analog Trigger Circuit**.\n* **Analog Trigger Circuit**: The output of this circuit points to the right with a waveform icon above the arrow.](.daq-daqe-221x-50m-12267-1000-10/45cf10a6a9a525235df24e56d79ac7dfc5e5f90492fa10faa1790ca08f394dd8.jpg) Figure 4-29: Analog Trigger Block Diagram
Trigger level digital settingTrigger voltage
0xFF9.92V
0xFE9.84V
0x810.08V
0x800
0x7F-0.08V
0x01-9.92V
# Table 4-5: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic The trigger signal is generated when the analog trigger condition is satisfied. There are five analog trigger conditions in the DAQ/ DAQe-2213/2214. The DAQ/DAQe-2213/2214 uses two threshold voltages, Low\_Threshold and High\_Threshold to build the five different trigger conditions. You can configure the trigger conditions easily by software. # Below-Low Analog Trigger Condition Figure 4-30 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low\_Threshold voltage, and the High\_Threshold setting is not used in this trigger condition. ![Low_Threshold\nTrigger](.daq-daqe-221x-50m-12267-1000-10/4ebf3e21043522fa127753175584b81deee07e3c221bf7d4f73d78fc34a5acca.jpg) Figure 4-30: Below-Low Analog Trigger Condition # Above-High Analog Trigger Condition Figure 4-31 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than the High\_Threshold voltage, and the Low\_Threshold setting is not used in this trigger condition. ![High_Threshold\nTrigger](.daq-daqe-221x-50m-12267-1000-10/e14995f81d9d6e7d0f07da9ca92ae03368ad3f797e1854781d3f33f8027c5397.jpg) Figure 4-31: Above-High Analog Trigger Condition # Inside-Region Analog Trigger Condition Figure 4-32 shows the inside-region analog trigger condition, the trigger signal is generated when the input analog signal level falls in the range between the High\_Threshold and the Low\_Threshold voltages. Note the High\_Threshold setting should be always higher than the Low\_Threshold voltage setting. ![| Trigger | High_Threshold | Low_Threshold |\n| ------- | ------------- | ------------ |\n| 0 | Low | Low |\n| 1 | High | Low |\n| 2 | Low | Low |\n| 3 | High | Low |\n| 4 | Low | Low |\n| 5 | High | Low |\n| 6 | Low | Low |\n| 7 | High | Low |\n| 8 | Low | Low |\n| 9 | High | Low |\n| 10 | Low | Low |\n| 11 | High | Low |\n| 12 | Low | Low |\n| 13 | High | Low |\n| 14 | Low | Low |\n| 15 | High | Low |\n| 16 | Low | Low |\n| 17 | High | Low |\n| 18 | Low | Low |\n| 19 | High | Low |\n| 20 | Low | Low |\n| 21 | High | Low |\n| 22 | Low | Low |\n| 23 | High | Low |\n| 24 | Low | Low |\n| 25 | High | Low |\n| 26 | Low | Low |\n| 27 | High | Low |\n| 28 | Low | Low |\n| 29 | High | Low |\n| 30 | Low | Low |\n| 31 | High | Low |\n| 32 | Low | Low |\n| 33 | High | Low |\n| 34 | Low | Low |\n| 35 | High | Low |\n| 36 | Low | Low |\n| 37 | High | Low |\n| 38 | Low | Low |\n| 39 | High | Low |\n| 40 | Low | Low |\n| 41 | High | Low |\n| 42 | Low | Low |\n| 43 | High | Low |\n| 44 | Low | Low |\n| 45 | High | Low |\n| 46 | Low | Low |\n| 47 | High | Low |\n| 48 | Low | Low |\n| 49 | High | Low |\n| 50 | Low | Low |\n| 51 | High | Low |\n| 52 | Low | Low |\n| 53 | High | Low |\n| 54 | Low | Low |\n| 55 | High | Low |\n| 56 | Low | Low |\n| 57 | High | Low |\n| 58 | Low | Low |\n| 59 | High | Low |\n| 60 | Low | Low |\n| 61 | High | Low |\n| 62 | Low | Low |\n| 63 | High | Low |\n| 64 | Low | Low |\n| 65 | High | Low |\n| 66 | Low | Low |\n| 67 | High | Low |\n| 68 | Low | Low |\n| 69 | High | Low |\n| 70 | Low | Low |\n| 71 | High | Low |\n| 72 | Low | Low |\n| 73 | High | Low |\n| 74 | Low | Low |\n| 75 | High | Low |\n| 76 | Low | Low |\n| 77 | High | Low |\n| 78 | Low | Low |\n| 79 | High | Low |\n| 80 | Low | Low |\n| 81 | High | Low |\n| 82 | Low | Low |\n| 83 | High | Low |\n| 84 | Low | Low |\n| 85 | High | Low |\n| 86 | Low | Low |\n| 87 | High | Low |\n| 88 | Low | Low |\n| 89 | High | Low |\n| 90 | Low | Low |\n| 91 | High | Low |\n| 92 | Low | Low |\n| 93 | High | Low |\n| 94 | Low | Low |\n| 95 | High | Low |\n| 96 | Low | Low |\n| 97 | High | Low |\n| 98 | Low | Low |\n| 99 | High | Low |\n| 100 | Low | Low |\n| Trigger (bottom) - Trigger (top) (Top) → Trigger (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) (bottom) ( bottom of bottom)](.daq-daqe-221x-50m-12267-1000-10/5ced98a6b9497c97a9dbfd31443b4aac1a387c4812482657dc9d78c1481ee65f.jpg) Figure 4-32: Inside-Region Analog Trigger Condition # High-Hysteresis Analog Trigger Condition Figure 4-33 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High\_Threshold voltage, and the Low\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting. ![| Time Segment | Value |\n| ------------ | ----- |\n| Trigger | Low_Threshold |\n| High_Threshold | High_Threshold |](.daq-daqe-221x-50m-12267-1000-10/dc029a734b4e4623339d8e4fe01235b522804a6701ea615b4272f6c3ec21eb4d.jpg) Figure 4-33: High-Hysteresis Analog Trigger Condition # Low-Hysteresis Analog Trigger Condition Figure 4-34 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low\_Threshold voltage, and the High\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting. ![| Trigger | High_Threshold | Low_Threshold |\n| ------- | -------------- | ------------- |\n| Low | Peak | Low |\n| High | Peak | Peak |](.daq-daqe-221x-50m-12267-1000-10/3d50088a22eb0296609d87fb163cfe1c73a5ebf0e2df9f2f473afb972d208bf7.jpg) Figure 4-34: Low-Hysteresis Analog Trigger Condition # External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT-DTRIG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process. Users can program the trigger polarity through ADLINK’s software drivers easily. Note that the signal level of the external digital trigger signals should be TTL-compatible, and the minimum pulse is 20ns. ![The image displays two waveforms illustrating trigger events.\n\n**Labeled Blocks (Text):**\n* 'Positive-edge trigger event occurs'\n* 'Negative-edge trigger event occurs'\n\n**Connections/Visual Relationships:**\n* **'Positive-edge trigger event occurs':** This text is positioned to the left of a waveform line that transitions from a low level to a high level (a rising edge). An arrow points upward along this vertical transition.\n* **'Negative-edge trigger event occurs':** This text is positioned to the right of a waveform line that transitions from a high level to a low level (a falling edge). An arrow points downward along this vertical transition.](.daq-daqe-221x-50m-12267-1000-10/e8d6735981973104e6444b7dff3189c7d40a064dff4d87f9fc9abdf643bb4633.jpg) Figure 4-35: External Digital Trigger # 4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and the requirements for synchronizing multiple cards, the DAQ/DAQe-2213/2214 provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/DAQe-2213/2214 is composed of a bunch of counters and trigger signals in the FPGA. These timing signals are related to the A/D conversions and Timer/Counter applications. These timing signals can be inputs to or outputs from the I/O connectors, the SSI connector. Therefore the internal timing signals can be used to control external devices or circuitry’s operation. We implemented signal multiplexers in the FPGA to individually choose the desired timing signals for the DAQ operations, as shown in Figure 4-36. ![The diagram illustrates a signal routing process involving the following labeled blocks and connections:\n\n**Input Blocks (Left Side):**\n* **Internal timing signals**\n* **SSI timing Signals**\n* **AFI timing signals**\n\nThese three blocks each connect via three parallel horizontal lines to a vertical trapezoidal interface on the left.\n\n**Central Block:**\n* **DAQ timing signals**\n\nThis block is connected to the left vertical interface and also to a right vertical interface via three parallel horizontal lines on each side.\n\n**Output Blocks (Right Side):**\n* **SSI timing Signals**\n* **Trigger_Out timing signals**\n\nThe right vertical trapezoidal interface connects to these two blocks, splitting the signal path. Three parallel lines connect to 'SSI timing Signals' and another three parallel lines connect to 'Trigger_Out timing signals'.](.daq-daqe-221x-50m-12267-1000-10/f8f592d334f12e07a03c792953474fe2b0bcf818572e78d28fc7413af56197c5.jpg) Figure 4-36: DAQ signals routing Users can utilize the flexible timing signals through our software drivers, and simply and correctly connect the signals with the DAQ/DAQe-2213/2214 cards. Here is the summary of the DAQ timing signals and the corresponding functionalities for DAQ/ DAQe-2213/2214.
Timing signal categoryCorresponding functionality
SSI signalsMultiple cards synchronization
AFI signalsControl card by external timing signals
Table 4-6: User-controllable Timing Signals and Functionalities # 4.6.1 DAQ timing signals ![The image displays a white document icon with a folded top-left corner and a thin black border. Faint, horizontal gray lines are visible on the page surface. A large, bold red checkmark is superimposed diagonally across the document.](.daq-daqe-221x-50m-12267-1000-10/16b169b1fd1c117cc568f0a364f3116689d576c86d51553d51ddd86fa61a14ee.jpg) NOTE: Refer to section 4.1 for the internal timing signal definition. The user-controllable DAQ timing-signals contain: 1. TIMEBASE, providing TIMEBASE for all DAQ operations, which could be from internal 40 MHz oscillator, EXTTIMEBASE from I/O connector or the SSI\_TIMEBASE. Note that the frequency range of the EXTTIMEBASE is 1 MHz to 40 MHz, and the EXTTIME-BASE must be TTL-compatible. 2. AD\_TRIG, the trigger signal for the A/D operation, which could come from external digital trigger, analog trigger, internal software trigger, and SSI\_AD\_TRIG. Refer to section 4.5 for detailed description. 3. SCAN\_START, the signal to start a scan, which would bring the following ADCONV signals for AD conversion, and could come from the internal SI\_counter, AFI[0] and SSI\_AD\_START. This signal is synchronous to the TIMEBASE. Note that the AFI[0] should be TTL-compatible and the minimum pulse width should be the pulse width of the TIMEBASE to guarantee correct functionalities. 4. ADCONV, the conversion signal to initiate a single conversion, which could be derived from internal counter, AFI[0] or SSI\_ADCONV. Note that this signal is edgesensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effective conversion signal. Also note that the AFI[0] signal should be TTL-compatible and the minimum pulse width is 20 ns. 5. DA\_TRIG (DAQ/DAQe-2214), the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trigger, internal software trigger, and SSI\_AD\_TRIG. Refer to section 4.5 for detailed description. 6. DAWR (DAQ/DAQe-2214), the update signal to initiate a single D/A conversion, which could be derived from internal counter, AFI[1] or SSI\_DAWR. Note that this signal is edge-sensitive. When using AFI[1] as the external DAWR source, each rising edge of AFI[1] would bring an effective update signal. Also note that the AFI[1] signal should be TTL-compatible and the minimum pulse width is 20 ns. # 4.6.2 Auxiliary Function Inputs (AFI) Users can use the AFI in applications that take advantage of external circuitry to directly control the DAQ/DAQe-2213/2214 cards. The AFI includes 2 categories of timing signals: one group is the dedicated input, and the other is the Low-Cost input. Table 4-7 illustrates this categorization.
CategoryTiming signalFunctionalityConstraints
Dedicated inputEXTTIMEBASEReplace the internal TIME-BASETTL-compatible1 MHz to 40 MHzAffects on both A/D and D/A operations.
EXTDTRIGExternal digital trigger input for A/D operationTTL-compatibleMinimum pulse width = 20nsRising edge or falling edge
EXTWFTRG (for DAQ/DAQe-2214)External digital trigger input for D/A operationTTL-compatibleMinimum pulse width = 20nsRising edge or falling edge
Multi-function inputAFI[0] (Dual-functions)Replace the internal ADCONVTTL-compatibleMinimum pulse width = 20nsRising-edge sensitive only
Replace the internal SCAN_STARTTTL-compatibleMinimum Pulse width > 2/TIMEBASE
AFI[1] (for DAQ/DAQe-2214)Replace the internal DAWRTTL-compatibleMinimum pulse width = 20nsRising-edge sensitive only
Table 4-7: Auxiliary Function Input Signals and Functionalities # EXTDTRIG and EXTWFTRIG EXTDTRIG and EXTWFTRIG are dedicated digital trigger input signals for A/D and D/A operations respectively. Refer to section 4.5 for details. # EXTTIMEBASE When applications need specific sampling frequency or update rate that the card cannot generate from its internal TIMEBASE, the 40MHz clock, then users can utilize the EXTTIMEBASE with internal counters to achieve the specific timing intervals for the A/D operations. # AFI[0] Alternatively, you can also directly apply an external A/D conversion signal to replace the internal ADCONV signal. This is another way to achieve customized sampling frequencies. The external ADCONV signal can only be inputted from the AFI[0]. As section 4.1 describes, the SI\_counter triggers the generation of the A/D conversion signal, ADCONV, but when using the AFI[0] to replace the internal ADCONV signal, the SI\_counter and the internally generated SCAN\_START is not effective. By controlling the ADCONV externally, you can sample the data according to external events. In this mode, the Trigger signal and trigger mode settings are not available. AFI[0] could also be used as SCAN\_START signal for A/D operations. Refer to section 4.1 and section 4.6 for detailed descriptions of the SCAN\_START signal. When using external signal (AFI[0]) to replace the internal SCAN\_START signal, the pulse width of the AFI[0] must be greater than two time of the period of Timebase. Note that the AFI[0] is a multi-purpose input, and it can only be utilized for one function at any one time. # AFI[1] (for DAQ/DAQe-2214) Regarding the D/A operations, users could directly input the external D/A update signal to replace the internal DAWR signal. This is another way to achieve customized D/A update rates. The external DAWR signal can only be inputted from the AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. AFI[1] currently only has one function. ADLINK reserves it for future development. # 4.6.3 System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing synchronization between multiple cards. In the DAQ/DAQe-2213/ 2214, we designed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI signals are designed for card synchronization only, not for external devices.
SSI Timing SignalSettingFunction
SSI_TIMEBASEMasterSend the TIMEBASE out
SlaveAccept the SSI_TIMEBASE to replace the internal TIMEBASE signal.
SSI_ADCONVMasterSend the ADCONV out
SlaveAccept the SSI_ADCONV to replace the internal ADCONV signal.
SSI_SCAN_STARTMasterSend the SCAN_START out
SlaveAccept the SSI_SCAN_START to replace the internal SCAN_START signal.
SSI_AD_TRIGMasterSend the internal AD_TRIG out
SlaveAccept the SSI_AD_TRIG as the digital trigger signal.
SSI_DAWR (for DAQ/DAQe-2214)MasterSend the DAWR out.
SlaveAccept the SSI_DAWR to replace the internal DAWR signal.
SSI_DA_TRIG (for DAQ/DAQe-2214)MasterSend the DA_TRIG out.
SlaveAccept the SSI_DA_TRIG as the digital trigger signal.
Table 4-8: SSI Timing Signal and Functions In the PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector position. All the SSI signals are routed to the 20-pin connector from the FPGA. To synchronize multiple cards, users can connect a special ribbon cable (ACL-SSI) to all the cards in a daisy-chain configuration. The 4 (DAQ/DAQe-2213) / 6 (DAQ/DAQe-2214) internal timing signals can be routed to the SSI bus through software drivers. Refer to section 4.6 for detailed information on the internal timing signals. Physically, the signal routings are accomplished in the FPGA. Cards that are connected together through the SSI bus will still achieve synchronization on the timing signals. # The SSI Mechanism We adopt master-slave configuration for SSI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with SSI function disabled. For each timing signal, the SSI master does not have to be in a single card. For example: We want to synchronize the A/D operation through the ADCONV signal for four DAQ/DAQe-2213/2214 cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisition. The SSI setting could be:  Set the SSI\_ADCONV signal of Card 1 to be the master.  Set the SSI\_ADCONV signals of Card 2, 3, 4 to be the slaves.  Set external digital trigger for Card 1’s A/D operation.  Set SI\_counter, SI2\_counter, NumChan\_counter, and the post scan counter (PSC) on all other cards.  Start DMA operations for all cards, so all the cards are waiting for the trigger event. When the digital trigger condition of Card 1 occurs, Card 1 will internally generate the ADCONV signal and output this ADCONV signal to SSI\_ADCONV signal of Cards 2, 3, and 4 through the SSI connectors. Thus we can achieve 4-channel acquisition simultaneously. Users can arbitrarily choose each of the 4 timing signals as the SSI master from any one of the cards. The SSI master can output the internal timing signals to the SSI slaves. With the SSI, users can achieve better card-to-card synchronization. Note that during power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals. This page intentionally left blank. # 5 Calibration This chapter introduces the calibration process to minimize AD measurement errors. # 5.1 Loading Calibration Constants The DAQ/DAQe-2213/2214 is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the on-board EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability. That means the calibration constants do not retain their values after the system power is turned off. Loading calibration constants is the process of loading the values of TrimDACs stored in the on-board EEPROM. ADLINK provides software to make it easy to read the calibration constants automatically when necessary. There is a dedicated space for calibration constants in the EEPROM. In addition to the default bank of factory calibration constants, there are three extra user-modifiable banks. Users can load the TrimDACs values either from the original factory calibration or from a calibration that is subsequently performed. Because of the fact that errors in measurements and outputs will vary with time and temperature, it is recommended re-calibration when the card is installed in the users’ environment. The auto-calibration function used to minimize errors will be introduced in the next sub-section. # 5.2 Auto-calibration By using the auto-calibration feature of the DAQ/DAQe-2213/ 2214, the calibration software can measure and correct almost all calibration errors without any external signal connections, reference voltages, or measurement devices. The DAQ/DAQe-2213/2214 has an onboard calibration references to ensure the accuracy of auto-calibration. The reference voltage is measured at the factory and adjusted through a digital potentiometer by using an ultra-precision calibrator. The impedance of the digital potentiometer is memorized after this adjustment. It is not recommended that users adjust the on-board calibration reference except when an ultra-precision calibrator is available. • Warm the card up for at least 15 minutes before initiating auto-calibration. For DAQ/DAQe-2214, remove the cable before an auto-calibration procedure is initiated because the DA outputs would be changed in the process of calibration. # 5.3 Saving Calibration Constants After an auto-calibration is completed, users can save the new calibration constants into one of the three user-modifiable banks in the EEPROM. The date and the temperature when you ran the auto-calibration will be saved accompanied with the calibration constants. This means users can store three sets of calibration constants according to three different environments and re-load the calibration constants later. # Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.  Read these safety instructions carefully.  Keep the User’s Manual for future reference.  Read the Specifications section of this manual for detailed information on the recommended operating environment.  The device can be operated at an ambient temperature of 50ºC. When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing:  Turn off power and unplug any power cords/cables.  Reinstall all chassis covers before restoring power.  To avoid electrical shock and/or damage to device:  Keep device away from water or liquid sources.  Keep device away from high heat or humidity.  Keep device properly ventilated (do not block or cover ventilation openings).  Always use recommended voltage and power source settings.  Always install and operate device near an easily accessible electrical outlet.  Secure the power cord (do not place any object on/over the power cord).  Only install/attach and operate device on stable surfaces and/or recommended mountings.  If the device will not be used for long periods of time, turn off and unplug it from its power source  Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools  A Lithium-type battery may be provided for uninterrupted backup or emergency power. ![The image features a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle is a white horizontal bar containing the text 'CAUTION:' in black, uppercase letters.](.daq-daqe-221x-50m-12267-1000-10/50d0b2cf189b0b30a9c84b2ef480600d36b60cc57017874fa55258130d48d0ad.jpg) Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately. Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.  The device must be serviced by authorized technicians when:  The power cord or plug is damaged.  Liquid has entered the device interior.  The device has been exposed to high humidity and/or moisture.  The device is not functioning or does not function according to the User’s Manual.  The device has been dropped and/or damaged and/or shows obvious signs of breakage. Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.  It is recommended that the device be installed only in a server room or computer room where access is:  Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.  Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location. ![Yellow triangular warning sign with black smoke symbol indicating hot weather](.daq-daqe-221x-50m-12267-1000-10/3e3ff7d4902a9e15c67cd69da9a45d4b718fbdc2eed6c757c176cf1ab9352d8f.jpg) # BURN HAZARD Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching. # RISQUE DE BRÛLURES Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher. # Getting Service Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5723 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Straße 11 D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. 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