# DAQ/DAQe/PXI-2005/2006/2010 4-ch, Simultaneous, High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. 1.0 Revision Date: Dec. 29, 2023 Part No: 50M-12257-1000 Revision History
RevisionRelease DateDescription of Change(s)
2.002006-04-20Previous release PN: 50-11020-1030
1.02023-12-29Initial release under new part number.Added 1.4 Software Support.Added 2.4 Switch and Jumper Settings.Added SSI connector pin assignment on PXI J2.Added Bus-mastering DMA Data Transfer.
# Preface # Copyright © 2023 ADLINK Technology Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. 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In the center is a large black exclamation point. There is no other text present.](.daq-daqe-pxi-20xx-50m-12257-1000-10/5d6bf41742fb681c5a269395247da695b9c5a193e36acc1002ee66897ec560c8.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image displays a white document icon with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.daq-daqe-pxi-20xx-50m-12257-1000-10/9523f29114fa5c6df40870ebd015c75d08ae6a472c5daa361221a627d0bc24f6.jpg) NOTE: Additional information, aids, and tips that help users perform tasks. ![A yellow triangular warning sign with a black border containing a large black exclamation point in the center.](.daq-daqe-pxi-20xx-50m-12257-1000-10/9845155951fafd22da4f6428a085174a7dd5303f3a4bb9e877742a201c791bad.jpg) CAUTION: Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image displays a red triangular warning sign with a white exclamation mark centered inside it, set against a white background.](.daq-daqe-pxi-20xx-50m-12257-1000-10/7ae0cbb30debc1a4cf03b3e28f5cb8f4fc564ba73a26db55d95cdaf11989b3fc.jpg) WARNING: Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # Table of Contents # Preface ......... iii # List of Tables......... . vii # List of Figures ........ ix # 1 Introduction ......... 1.1 Features.... 2 1.2 Applications .. 3 1.3 Specifications.... 4 1.4 Software Support .. 1 1 # 2 Installation ....... . 15 2.1 Contents of Package ..... 1 5 2.2 Unpacking.... 1 6 2.3 DAQ/DAQe/PXI-20xx Layout... 1 7 2.4 Switch and Jumper Settings . 1 8 2.5 PCI Configuration . 2 2 # 3 Signal Connections....... 2 3 3.1 Connectors Pin Assignment . 2 3 3.2 Analog Input Signal Connection ... 28 # 4 Operation Theory ........ . 31 4.1 A/D Conversion... 3 1 4.2 D/A Conversion... 4 8 4.3 Digital I/O .. 5 7 4.4 General Purpose Timer/Counter Operation.. 5 8 4.5 Trigger Sources .. 6 4 4.6 User-controllable Timing Signals .... 69 # 5 Calibration ........ .. 77 5.1 Loading Calibration Constants.... . 77 5.2 Auto-calibration .... 78 5.3 Saving Calibration Constants.... 78 # Important Safety Instructions....... . 79 # Getting Service ........ ..... 81 # List of Tables Table 1-1: -3dB small signal bandwidth 5 Table 1-2: System Noise . 6 Table 1-3: CMRR: (DC to 60Hz) . 7 Table 2-1: Board ID SW1 DIP Switch Settings 1 9 Table 3-1: 68-pin VHDCI-type pin assignment 2 3 Table 3-2: 68-pin VHDCI-type Connector Legend 2 4 Table 3-3: SSI connector pin assignment for DAQ/DAQe-20xx . 26 Table 3-4: SSI Connector Pin Assignment on PXI J2 . 27 Table 3-5: Legend of SSI connector . 2 7 Table 4-1: Bipolar analog input range and the output digital code on DAQ/DAQe/PXI-2010 3 3 Table 4-2: Unipolar analog input range and the output digital code on DAQ/DAQe/PXI-2010 3 3 Table 4-3: Bipolar analog input range and the output digital code on the DAQ/DAQe/PXI-2005/2006 34 Table 4-4: Unipolar analog input range and the output digital code on the DAQ/DAQe/PXI-2005/2006 3 4 Table 4-5: Bipolar output code table (Vref=10V if internal reference is selected) 4 8 Table 4-6: Unipolar output code table (Vref=10V if internal reference is selected) 49 Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic . 6 5 Table 4-8: Summary of user-controllable timing signals and the corresponding functionalities 70 Table 4-9: Auxiliary function input signals and the corresponding functionalities 72 Table 4-10: Summary of SSI timing signals and the corresponding functionalities as the master or slave . 74 This page intentionally left blank. # List of Figures Figure 2-1: PCB Layout of the DAQ/DAQe-20xx .... 17 Figure 2-2: PCB Layout of the PXI-20XX.. 17 Figure 2-3: Board ID SW1 DIP Switch . 1 8 Figure 2-4: Enable Board ID Configuration.. 2 0 Figure 2-5: DIO Initial Status (JP4) .. 2 1 Figure 3-1: Single-Ended connections... 29 Figure 3-2: Ground-referenced source and differential input ..... 29 Figure 3-3: Floating source and differential input... 3 0 Figure 4-1: Synchronous Digital Inputs Block Diagram ............ 3 2 Figure 4-2: Synchronous Digital Inputs timing ...... 3 2 Figure 4-3: Scan Timing.. 3 6 Figure 4-4: Pre-trigger (trigger occurs after at least M scans acquired)... 3 8 Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a conversion is in progress).... 3 8 Figure 4-6: Pre-trigger with M\_enable = 0 (Trigger occurs before M scans).. 3 9 Figure 4-7: Pre-trigger with M\_enable = 1 .. 3 9 Figure 4-8: Middle trigger with M\_enable = 1.. 41 Figure 4-9: Middle trigger (trigger when scan in progress) ........ 42 Figure 4-10: Post trigger . 4 3 Figure 4-11: Delay trigger . 44 Figure 4-12: Post trigger with re-trigger . 4 5 Figure 4-13: Linked List of PCI Address DMA Descriptors .......... 47 Figure 4-14: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V)... 50 Figure 4-15: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V).. 51 Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)... 52 Figure 4-17: Re-triggered waveform generation (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) ... 52 Figure 4-18: Finite iterative waveform generation with Post-trigger and DLY2\_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V)... 53 Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2\_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) .. 54 Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V).. 55 Figure 4-21: Stop mode II . 56 Figure 4-22: Stop mode III .. 56 Figure 4-23: Mode 1 Operation. 59 Figure 4-24: Mode 2 Operation. 60 Figure 4-25: Mode 3 Operation.. 60 Figure 4-26: Mode 4 Operation.. 61 Figure 4-27: Mode 5 Operation.. 61 Figure 4-28: Mode 6 Operation. 62 Figure 4-29: Mode 7 Operation. 62 Figure 4-30: Mode 8 Operation. 63 Figure 4-31: Analog trigger block diagram. 65 Figure 4-32: Below-Low analog trigger condition.. 66 Figure 4-33: Above-High analog trigger condition... 66 Figure 4-34: Inside-Region analog trigger condition ..... 67 Figure 4-35: High-Hysteresis analog trigger condition ........... . 67 Figure 4-36: Low-Hysteresis analog trigger condition......... 68 Figure 4-37: External digital trigger .. 68 Figure 4-38: DAQ signals routing... 69 # 1 Introduction The DAQ/DAQe/PXI-20xx is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap-plications in medical, process control, etc. # 1.1 Features The DAQ/DAQe/PXI-20xx Advanced Data Acquisition Card provides the following advanced features:  32-bit PCI-Bus, plug and play  4-channel simultaneous differential analog inputs  DAQ/DAQe/PXI-2010: 14-bit Analog input resolution with sampling rate up to 2MS/s  DAQ/DAQe/PXI-2005: 16-bit Analog input resolution with sampling rate up to 500KS/s  DAQ/DAQe/PXI-2006: 16-bit Analog input resolution with sampling rate up to 250KS/s  Programmable bipolar/unipolar analog input  Programmable gain (x1, x2, x4, x8 for all DQ-20XX)  DAQ/DAQe/PXI-2010: Total 8K samples A/D FIFO  DAQ/DAQe/PXI-2005/2006: Total 512 samples A/D FIFO Versatile trigger sources: software trigger, external digital trigger, analog trigger and trigger from System Synchronization Interface (SSI).  A/D Data transfer: software polling & bus-mastering DMA with Scatter/Gather functionality  Four A/D trigger modes: post-trigger, delay-trigger, pre-trigger and middle-trigger  2 channel DA outputs with waveform generation capability  2K samples output data FIFO for DA channels  DA Data transfer: software update and bus-mastering DMA with Scatter/Gather functionality  System Synchronization Interface (SSI)  A/D/DA fully auto-calibration  Completely jumper-less and software configurable # 1.2 Applications  Automotive Testing  Cable Testing  Transient signal measurement  ATE  Laboratory Automation  Biotech measurement # 1.3 Specifications # Analog Input (AI)  Number of channels: 4 differential  A/D converter:  2010: LTC1414 or equivalent  2005: A/D7665 or equivalent  2006: A/D7663 or equivalent  Max sampling rate:  2010: 2MS/s  2005: 500kS/s  2006: 250kS/s  Resolution:  2010: 14 bits, no missing code  2005/2006:16 bits, no missing code  FIFO buffer size:  2010:8K samples  2005/2006: 512 samples  Programmable input range:  Bipolar: 10V, 5V, 2.5V, 1.25V  Unipolar: 0\~10V, 0\~5V, 0\~2.5V, 0\~1.25V  Operational common mode voltage range: 11V  Overvoltage protection:  Power on: continuous 30V  Power off: continuous 15V  Input impedance: 1G/100pF  -3dB small signal bandwidth: (Typical, $2 5 ^ { \circ } \mathrm { C } )$
DeviceInput RangeBandwidth (-3dB)Input RangeBandwidth (-3dB)
2010±10V1170 kHz0~10V1090 kHz
±5V1050 kHz0~5V1020 kHz
±2.5V800 kHz0~2.5V790 kHz
±1.25V530 kHz0~1.25V530 kHz
2005±10V1160 kHz0~10V1210 kHz
±5V1050 kHz0~5V1050 kHz
±2.5V780 kHz0~2.5V770 kHz
±1.25V520 kHz0~1.25V530 kHz
2006±10V630 kHz0~10V640 kHz
±5V620 kHz0~5V620 kHz
±2.5V540 kHz0~2.5V540 kHz
±1.25V410 kHz0~1.25V420 kHz
Table 1-1: -3dB small signal bandwidth  Large signal bandwidth (1% THD): 300 kHz  System Noise: (Typical)
DeviceInput RangeSystem noiseInput RangeSystem noise
2010±10V0.6 LSBrms0~10V0.8 LSBrms
±5V0.6 LSBrms0~5V0.8 LSBrms
±2.5V0.6 LSBrms0~2.5V0.9 LSBrms
±1.25V0.6 LSBrms0~1.25V0.9 LSBrms
2005±10V1.2 LSBrms0~10V1.9 LSBrms
±5V1.2 LSBrms0~5V2.0 LSBrms
±2.5V1.3 LSBrms0~2.5V2.1 LSBrms
±1.25V1.3 LSBrms0~1.25V2.2 LSBrms
2006±10V1.0 LSBrms0~10V1.5 LSBrms
±5V1.0 LSBrms0~5V1.6 LSBrms
±2.5V1.1 LSBrms0~2.5V1.7 LSBrms
±1.25V1.1 LSBrms0~1.25V1.8 LSBrms
Table 1-2: System Noise  CMRR: (DC to 60Hz, Typical)
DeviceInput RangeCMRRInput RangeCMRR
2010±10V90 dB0~10V89 dB
±5V92 dB0~5V92 dB
±2.5V95 dB0~2.5V94 dB
±1.25V97 dB0~1.25V97 dB
2005±10V86 dB0~10V85 dB
±5V88 dB0~5V88 dB
±2.5V91 dB0~2.5V90 dB
±1.25V93 dB0~1.25V93 dB
2006±10V87 dB0~10V86 dB
±5V89 dB0~5V88 dB
±2.5V91 dB0~2.5V91 dB
±1.25V93 dB0~1.25V93 dB
Table 1-3: CMRR: (DC to 60Hz)  Time-base source:  Internal 40MHz or External clock Input (fmax: 40MHz, fmin: 1MHz, 50% duty cycle)  Trigger modes:  Post-trigger, Delay-trigger, Pre-trigger and Middle-trigger  Data transfers:  Programmed I/O, and bus-mastering DMA with scatter/ gather  Input coupling: DC  Offset error:  ±8mV max for DAQ/DAQe/PXI-2010  ±3mV max for DAQ/DAQe/PXI-2005/2006  Gain error: 0.5% of output max for DAQ/DAQe/PXI-2010, ±0.05% of output max for DAQ/DAQe/PXI-2005/2006 # Analog Output (AO)  Number of channels: 2 channel voltage output  DA converter: LTC7545 or equivalent  Max update rate: 1MS/s  Resolution: 12 bits  FIFO buffer size:  1k samples per channel when both channels are enabled for timed DA output, and 2k samples when only one channel is used for timed DA output  Data transfers:  Programmed I/O, and bus-mastering DMA with scatter/ gather  Output range:  Bipolar: ±10V or ±AOEXTREF  Unipolar: 0\~10V or 0\~AOEXTREF  Settling time: 3S to 0.5 LSB accuracy  Slew rate: 20V/S  Output coupling: DC  Protection: Short-circuit to ground  Output impedance: 0.3 typical  Output driving current: ±5mA max.  Stability: Any passive load, up to 1500pF  Power-on state: 0V steady-state  Power-on glitch: ±1.5V/500uS  Relative accuracy:  ±0.5 LSB typical, ±1 LSB max  DNL:  ±0.5 LSB typical, ±1.2 LSB max  Offset error: ±1mV max  Gain error: ±0.05% of output max  General Purpose Digital I/O (G.P. DIO, 82C55A)  Number of channels: 24 programmable Input/Output  Compatibility: TTL/CMOS  Input voltage:  Logic Low: VIL=0.8V max; IIL=0.2mA max.  High: VIH=2.0V max; IIH=0.02mA max  Output voltage:  Low: VOL=0.5V max; IOL=8mA max.  High: VOH=2.7V min; IOH=400A  Synchronous Digital Inputs (SDI, for DAQ/DAQe/PXI-2010 only)  Number of channels: 8 digital inputs sampled simultaneously with the analog signal input  Compatibility: TTL/CMOS  Input voltage:  Logic Low: VIL=0.8V max; IIL=0.2mA max.  Logic High: VIH=2.7V min; IIL=0.02mA max. # General Purpose Timer/Counter (GPTC)  Number of channel: 2 Up/Down Timer/Counters  Resolution: 16 bits  Compatibility: TTL  Clock source: Internal or external  Max source frequency: 10MHz # Analog Trigger (A.Trig)  Source:  All analog input channels; external analog trigger (EXTATRIG)  Level: ±Full-scale, internal; ±10V external  Resolution: 8 bits  Slope: Positive or negative (software selectable)  Hysteresis: Programmable  Bandwidth: 400khz # External Analog Trigger Input (EXTATRIG)  Input Impedance:  40k for DAQ/DAQe/PXI-2010  2k for DAQ/DAQe/PXI-2005/2006  Coupling: DC  Protection: Continuous ±35V maximum # Digital Trigger (D.Trig)  Compatibility: TTL/CMOS  Response: Rising or falling edge  Pulse Width: 10ns min # System Synchronous Interface (SSI)  Trigger lines: 7 # Stability  Recommended warm-up time: 15 minutes  Onboard calibration reference:  Level: 5.000V  Temperature coefficient: ±2ppm/C  Long-term stability: 6ppm/1000Hr # Physical  Dimensions:  175mm by 107mm for DAQ/DAQe-20xx  Standard CompactPCI form factor for PXI-20XX  I/O connector: 68-pin female VHDCI type (e.g. AMP-787254-1) # Power Requirement (typical)  +5VDC: 1.82 A for DAQ/DAQe/PXI-2010  2.04 A for DAQ/DAQe/PXI-2005  1.82 A for DAQ/DAQe/PXI-2006 # Operating Environment  Ambient temperature: 0 to $5 5 ^ { \circ } \mathrm { C }$  Relative humidity: 10% to 90% non-condensing # Storage Environment  Ambient temperature: -20 to ${ 8 0 ^ { \circ } \mathrm { C } }$  Relative humidity: 5% to 95% non-condensing # Interface Connector  68-pin AMP-787254-1 or equivalent # 1.4 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platforms. By leveraging low-level kernel management and a user friendly API, users can easily manage devices under a Windows environment and focus on developing applications. ![The diagram is organized into three horizontal layers representing a software and hardware stack.\n\n**Top Layer (Software & SDKs)**\n* **Left Column (Red Background):** A vertical block labeled **'MAPS Core Device Management'** contains four stacked grey buttons:\n * 'Device Manager (ACE)'\n * 'PXI Platform Resource Mgmt. Utility'\n * 'PXI Platform ChassisWatch Utility'\n * 'DAQ/IO Module Function Test Utility'\n* **Right Section (Three Columns):**\n * **Orange Column:** Top block 'User APPs in C/C++' sits above an orange block labeled **'MAPS/C'** and **'C/C++ SDK for DAQ/IO module'**.\n * **Green Column:** Top block 'User APPs in LabVIEW' sits above a green block labeled **'MAPS/LV'** and **'LabVIEW SDK for DAQ/IO module'**.\n * **Purple Column:** Top block 'User APPs in C#' sits above a purple block labeled **'MAPS/C#'**, **'C# SDK for DAQ/IO module'**, and **'Coming soon'**.\n\n**Middle Layer (Runtime Services)**\n* A wide red horizontal bar spanning the width contains the text **'MAPS Core -Device Runtime'** on the left and **'PXI Platform Service'**, **'DAQ/IO Module Device Driver'**, and **'DAQ/IO Module Runtime Library'** on the right.\n\n**Bottom Layer (Hardware)**\n* A blue horizontal bar displays images of hardware devices labeled below:\n * 'Digitizers'\n * 'DAQ'\n * 'Edge Platform'\n * 'PXle Controllers'\n * 'PXle/PXI Chassis'](.daq-daqe-pxi-20xx-50m-12257-1000-10/5bca1516ec989961ad285763ec26d17ad9f71943c655ffdfe31a466c66e45ec0.jpg) # 1.4.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment. ![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCI9112 Device 'PCI-9'\nUSB\nGeneral\nSettings\nAlias Name PCI-9112-0\nVendor ADLINK Technology Inc.\nModel PCI9112 Device\nPCI Bus 2\nPCI Device 11\nPCI Function 0\nDMA Buffer\nAI 1024 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch\nCorelib](.daq-daqe-pxi-20xx-50m-12257-1000-10/df66e40a64542af5cb0c5738b8d3de6988ab06a0bc24ec22ab64ee09125e67be.jpg) ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen. ![| Time (Sec) | Voltage (Vpp) |\n| ---------- | ------------- |\n| 0.00 | 5.0 |\n| 0.02 | 10.0 |\n| 0.03 | 5.0 |\n| 0.04 | 0.0 |\n| 0.05 | -5.0 |\n| 0.06 | -10.0 |\n| 0.08 | -5.0 |\n| 0.10 | 5.0 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/9afde5601b48cb9f58182b3260d8520f1dc37cf786d7a8eba5dbaad9cd9cfe93.jpg) # 1.4.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual: https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_LV # 1.4.3 MAPS/C, C & C++ Support Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website. https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_C # 2 Installation This chapter describes how to install the DAQ/DAQe/PXI-20xx. The contents of the package and unpacking information that you should be aware of are outlined first. # 2.1 Contents of Package In addition to this User's Guide, the package should include the following items:  DAQ/DAQe/PXI-20xx Multi-function Data Acquisition Card  Software Installation Guide If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future. # 2.2 Unpacking Your DAQ/DAQe/PXI-20xx Series card contains electro-static sensitive components that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damages. Shipping and han-dling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing. After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up. Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. You are now ready to install your DAQ/DAQe/PXI-20xx. ![The image displays a standard warning sign. It features a maroon triangle containing a white exclamation point in its center. Directly below the triangle is the word 'WARNING' printed in white capital letters on a black background.](.daq-daqe-pxi-20xx-50m-12257-1000-10/1a895b4e64550855d91b280fb243b059ec8e9a03425897ddf6d88e0c331213fd.jpg) DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED. # 2.3 DAQ/DAQe/PXI-20xx Layout ![Board to Board Connector\nSSI Connector\n2005/2006/2010\nDaughter Board\nCarrier Board\n6B-PIN Connector\nBoard to Board Connector](.daq-daqe-pxi-20xx-50m-12257-1000-10/a546d2b1a3ed4e9effa7ce8766a484a0575e9318a2329c7e77e515c22a3330e4.jpg) Figure 2-1: PCB Layout of the DAQ/DAQe-20xx ![68-PIN Connector\n2005/2006/2010\nDaughter Board\nBoard to Board Connector\nPXL-2000 Carrier Board](.daq-daqe-pxi-20xx-50m-12257-1000-10/ab3380974574330c1846d353423d71b6c36ed926b9231d9a8e73b72e93a9209d.jpg) Figure 2-2: PCB Layout of the PXI-20XX # 2.4 Switch and Jumper Settings # 2.4.1 Board ID (SW1) The DAQ/DAQe/PXI-20xx Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for identifying each card’s device number. After setting each DAQ/ DAQe/PXI-20xx Series card, you can identify each card in the system with different device numbers. The default value of the Board ID is 0 and if you need to adjust it to another value, set the SW1 switch as shown in the table below. ![ON\nDIP\n1 2 3 4](.daq-daqe-pxi-20xx-50m-12257-1000-10/fd0171f4ee9a078b5156932c0cfde17a001f8011c6bb9bc791c0d9d50c83ea26.jpg) Figure 2-3: Board ID SW1 DIP Switch
SW1Pin 1Pin 2Pin 3Pin 4
Board IDID0ID1ID2ID3
0OffOffOffOff
1OnOffOffOff
2OffOnOffOff
3OnOnOffOff
4OffOffOnOff
5OnOffOnOff
6OffOnOnOff
7OnOnOnOff
8OffOffOffOn
9OnOffOffOn
10OffOnOffOn
11OnOnOffOn
12OffOffOnOn
13OnOffOnOn
14OffOnOnOn
15OnOnOnOn
Table 2-1: Board ID SW1 DIP Switch Settings ![The image displays a white document icon with a folded top-right corner and faint horizontal lines, overlaid by a large red checkmark.](.daq-daqe-pxi-20xx-50m-12257-1000-10/1756c8ad4517f91ff4d705bbdd0b4e5a41cc62170b84401b97d97f06114b76be.jpg) NOTE: Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K\_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select your Card Type and uncheck Ignore Board ID. See figure below. ![DAQ2000 Device Driver Configuration\nThis utility is used for the cards that will perform continuous AI, DI or DO operation\nCard Type: Daq2016\nDaq2010\nDaq2205\nDaq2206\nAI : Daq2005\nDaq2204\nAO : Daq2006\nDaq2501\nDaq2502\nDI : Daq2208\nDaq2213\nDO : Daq2214\nIgnore Board ID No Reset\nOK Apply Cancel](.daq-daqe-pxi-20xx-50m-12257-1000-10/763fa249ab678c6e02f7555530650e3d81d806c03c23303b09f089ee4972a68c.jpg) Figure 2-4: Enable Board ID Configuration # 2.4.2 DIO Initial Status (JP4) The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below. ![Disabled\nJP4\nEnabled\nJP4](.daq-daqe-pxi-20xx-50m-12257-1000-10/f4878f4510bef4074ab9ecbf4103bf3ec5f4290a8e4c4f8f349591f6017a33b7.jpg) Figure 2-5: DIO Initial Status (JP4) # 2.5 PCI Configuration # 1. Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. # 2. Configuration: The board configuration is done on a board-by-board basis for all PCI boards on your system. Because configuration is controlled by the system and software, there is no jumper setting required for base-address, DMA, and interrupt IRQ. The configuration is subject to change with every boot of the sys-tem as new boards are added or removed. # 3. Troubleshooting: If your system doesn’t boot or if you experience erratic operation with your PCI board in place, it’s likely caused by an interrupt con-flict (perhaps the BIOS Setup is incorrectly configured). In general, the solution, once you determine it is not a simple oversight, is to consult the BIOS documentation that comes with your system. # 3 Signal Connections This chapter describes the connectors of the DAQ/DAQe/PXI-20xx, and the signal connection between the DAQ/DAQe/PXI-20xx and external devices. # 3.1 Connectors Pin Assignment The DAQ/DAQe/PXI-20xx is equipped with one 68-pin VHDCItype connector (AMP-787254-1). It is used for digital input/output, analog input / output, and timer/counter signals, etc. One 20-pin ribbon male connector is used for SSI (System Synchronous Interface) in DAQ/DAQe-20xx. The pin assign-ments of the connectors are defined in Table 3-1 and Table 3-2.
CH0+135CH0-
CH1+236CH1-
CH2+337CH2-
CH3+438CH3-
EXTATRIG539AIGND
DA1OUT640AOGND
DA0OUT741AOGND
AOEXTREF842AOGND
SDI3_1 / NC*943SDI3_0 / NC*
SDI2_1 / NC*1044SDI2_0 / NC*
SDI1_1 / NC*1145SDI1_0 / NC*
SDI0_1 / NC*1246SDI0_0 / NC*
AO_TRIG_OUT1347EXTWFTRG
AI_TRIG_OUT1448EXTDTRIG
GPTC1_SRC1549DGND
GPTC0_SRC1650DGND
GPTC0_GATE1751GPTC1_GATE
GPTC0_OUT1852GPTC1_OUT
GPTC0_UPDOWN1953GPTC1_UPDOWN
EXTTIMEBASE2054DGND
Table 3-1: 68-pin VHDCI-type pin assignment
AFI12155AFI0
PB72256PB6
PB52357PB4
PB32458PB2
PB12559PB0
PC72660PC6
PC52761PC4
DGND2862DGND
PC32963PC2
PC13064PC0
PA73165PA6
PA53266PA4
PA33367PA2
PA13468PA0
Table 3-1: 68-pin VHDCI-type pin assignment \* SDI for DAQ/DAQe/PXI-2010 only; NC for DAQ/DAQe/PXI-2005/2006 Legend:
Pin #Signal NameReferenceDirectionDescription
1~4CH<0..3>+CH0<0..3>-InputDifferential positive input for AI channel <0..3>
5EXTATRIGAIGNDInputExternal AI analog trigger
6DA0OUTAOGNDOutputAO channel 0
7DA1OUTAOGNDOutputAO channel 1
8AOEXTREFAOGNDInputExternal reference for AO channels
9~12SDI<3..0>_1 (2010) NC (2005/2006)DGNDInputSynchronous digital inputs
13AO_TRIG_OUTDGNDOutputAO trigger signal
14AI_TRIG_OUTDGNDOutputAI trigger signal
Table 3-2: 68-pin VHDCI-type Connector Legend
Pin #Signal NameReferenceDirectionDescription
15,16GPTC<0,1>_SRCDGNDInputSource of GPTC<0,1>
17,51GPTC<0,1>_GATEDGNDInputGate of GPTC<0,1>
18,52GPTC<0,1>_OUTDGNDInputOutput of GPTC<0,1>
19,53GPTC<0,1>_UPDOWNDGNDInputUp/Down of GPTC<0,1>
20EXTTIMEBASEDGNDInputExternal TIME-BASE
21,28,49,50,54,62DGND--------Digital ground
22,56,23,57,24,58,25,59PB<7,0>DGNDPIO*Programmable DIO pins of 8255 Port B
26,60,27,61,29,63,30,64PC<7,0>DGNDPIO*Programmable DIO pins of 8255 Port C
31,65,32,66,33,67,34,68PA<7,0>DGNDPIO*Programmable DIO pins of 8255 Port A
35~38CH<0..3>-----InputDifferential nega-tive input for AI channel <0..3>
39AIGND--------Analog ground for AI
40~42AOGND--------Analog ground for AO
43~46SDI<3..0>_0 (2010) NC (2005/2006)DGNDInputSynchronous dig-ital inputs
47EXTWFTRIGDGNDInputExternal AO waveform
trigger
48EXTDTRIGDGNDInputExternal AI digital trigger
Table 3-2: 68-pin VHDCI-type Connector Legend
Pin #Signal NameReferenceDirectionDescription
55AFI0DGNDInputAuxiliary Function Input 0 (ADCONV, AD_START)
21AFI1DGNDInputAuxiliary Function Input 1 (DAWR, DA_START)
Table 3-2: 68-pin VHDCI-type Connector Legend \*PIO means programmable I/O
SSI_TIMEBASE12DGND
SSI_ADCONV34DGND
SSI_DAWR56DGND
SSI_SCAN_START78DGND
RESERVED910DGND
SSI_AD_TRIG1112DGND
SSI_DA_TRIG1314DGND
RESERVED1516DGND
RESERVED1718DGND
RESERVED1920DGND
Table 3-3: SSI connector pin assignment for DAQ/DAQe-20xx SSI Connector Signal Description on PXI J2:
Sync. SignalPXI J2 locationPXI Trigger Bus
SSI_TIMEBASEB18PXI_TRIG4
SSI_ADCONVA16PXI_TRIG1
SSI_SCAN_STARTA18PXI_TRIG3
SSI_AD_TRIGC18PXI_TRIG5
SSI_DAWRA17PXI_TRIG2
SSI_DA_STARTB16PXI_TRIG0
SSI_DA_TRIGE18PXI_TRIG6
Table 3-4: SSI Connector Pin Assignment on PXI J2 Legend:
SSI timing signalFunctionality
SSI_TIMEBASESSI master: send the TIMEBASE outSSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.
SSI_ADCONVSSI master: send the ADCONV outSSI slave: accept the SSI_ADCONV to replace the internal ADCONV signal.
SSI_SCAN_STARTSSI master: send the SCAN_START outSSI slave: accept the SSI_SCAN_START to replace the internal SCAN_START signal.
SSI_AD_TRIGSSI master: send the internal AD_TRIG outSSI slave: accept the SSI_AD_TRIG as the digital trigger signal.
SSI_DAWRSSI master: send the DAWR out.SSI slave: accept the SSI_DAWR to replace the internal DAWR signal.
SSI_DA_TRIGSSI master: send the DA_TRIG out.SSI slave: accept the SSI_DA_TRIG as the digital trigger signal.
Table 3-5: Legend of SSI connector # 3.2 Analog Input Signal Connection The DAQ/DAQe/PXI-20xx provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals. # 3.2.1 Types of signal sources # Ground-Referenced Signal Sources A ground-referenced signal means it is connected in some way to the building system. That is, the signal source is already connected to a common ground point with respect to the DAQ/ DAQe/PXI-20xx, assuming that the computer is plugged into the same power system. Non- isolated out-puts of instruments and devices that plug into the buildings power system are ground-referenced signal sources. # Floating Signal Sources A floating signal source means it is not connected in any way to the buildings ground system. A device with an isolated output is a floating signal source, such as optical isolator outputs, transformer outputs, and thermocouples. # 3.2.2 Single-Ended Measurements For single-ended connection, the analog input signal is referenced to the common ground of the system. In this case, all the negative ends of analog input channels should be connected to the AIGND on the connector in-stead of floating. Please refer to the Figure 3-1. ![Vin\nCHn+\nAIGND\nPGA\n-\n+\nVm=Gain*CHn+\n-](.daq-daqe-pxi-20xx-50m-12257-1000-10/17a36fd4f827b151b461ee98682ca0f18d3208d349e2b246abe422262b662501.jpg) Figure 3-1: Single-Ended connections In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential configurations. Therefore, the single-ended connection is not recommended unless minimal wire connections are necessary. # 3.2.3 Differential Measurements # Differential Connection for Grounded-Reference Signal Sources The differential analog input provides two inputs that respond to the signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 3-2 shows the connection of ground-referenced signal sources under the differential input mode. ![CHn+\nVin\nCHn-\nVcm\nPGA\n-\n+\nVm=Gain*(CHn+-CHn-)\n-](.daq-daqe-pxi-20xx-50m-12257-1000-10/fb49a7f0c3ca324bf98aa025e4f4f5ea9e45feff754c6623dff5b5a6186655af.jpg) Figure 3-2: Ground-referenced source and differential input # Differential Connection for Floating Signal Sources Figure 3-3 shows how to connect a floating signal source to DAQ/DAQe/PXI-20xx in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. If the source impedance is less than 100ohms, you can simply connect the negative side of the signal to AGND as well as the negative input of the Instru-mentation Amplifier, without any resistors at all. In differential input mode, less noise couples into the signal connections than in single-ended mode. ![CHn+\nVin\nCHn-\nBias\nResistor\nPGA\nVm=Gain*(CHn+-CHn-)\n+](.daq-daqe-pxi-20xx-50m-12257-1000-10/98c090eed50450bae24e43f7d49ffd8757a37be5be83eafee0de7442d574dc75.jpg) Figure 3-3: Floating source and differential input # 4 Operation Theory The operation theory of the functions on the DAQ/DAQe/PXI-20xx is described in this chapter. The functions include the A/D conversion, D/A conversion, Digital I/O and General Purpose Counter/ Timer. The operation theory can help you understand how to configure and program the DAQ/DAQe/PXI-20xx. The whole DAQ/DAQe/PXI-2000 series cards, including DAQ/ DAQe/PXI-20xx, DAQ/DAQe/PXI-22xx and DAQ/DAQe/PXI-25xx, are designed based on the same logic-timing template of DAQ/ DAQe/PXI-22xx. In the DAQ/DAQe/PXI-22xx cards, all the A/D related timings are for multiplexing A/D sampling based on scanning, so that DAQ/DAQe/PXI-20xx also adopts the same concept, except there is only one conversion signal in a scan which could generate up to 4 samples from the different 4 channels at the same time. In the following description, to conform to the original timing design, we still use “scan” as the unit of A/D data acquisition. All the DA and GPTC functions are the same in DAQ/DAQe/ PXI-20xx and DAQ/DAQe/PXI-22xx, while DAQ/DAQe/PXI-25xx provides improved DA timing comparing the former 2 series. # 4.1 A/D Conversion When using an A/D converter, users should first know about the properties of the signal to be measured. Users can decide which channel to use and where to connect the signals to the card. Please refer to 3.2 for signal connections. In addition, users should define and control the A/D signal configurations, including channels, gains, and A/D signal types. There are 2 ways to initiate A/D conversion, either by Software Polling or Programmable Scan Acquisition; these are described below. The A/D acquisition is initiated by a trigger source; users must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched. After the end of A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data should be transferred into the PC's memory for further processing. # 4.1.1 DAQ/DAQe/PXI-2010 AI Data Format Synchronous Digital Inputs (for DAQ/DAQe/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>\_X per channel from J5 will be latched into the 16-bit register and data FIFO, as shown in Figure 8 and Figure 9. Therefore, users can simultaneously sample one analog signal with four digital signals. The data format of every acquired 16-bit data is as follows: ```txt D13, D12, D11 ..... D1, D0, b1, b0 Where D13, D12, D11 ..... D1, D0: 2's complement A/D 14-bit data b1, b0: Synchronous Digital Inputs SDI<1..0> ``` ![Based on the provided image, here is the accurate description of the flowchart:\n\n**Blocks and Internal Labels:**\n* **ADC Block:** Contains the text 'ADC', 'Ain', 'nADBUSY', and 'nADCONV'.\n* **16-bit Register Block:** Contains the text '16-bit Register' and 'CLK'.\n* **AD Data FIFO Block:** Contains the text 'AD Data FIFO'.\n\n**Connections and External Inputs:**\n* **SDI(1.0) Connection:** A wire labeled 'SDI(1.0)' (marked with a slash and '2') originates from the text 'SDI(1.0) from CN2' at the top left and connects to the top of the **16-bit Register**.\n* **ADC Inputs:**\n * The text 'From Instrumentation Amplifier' points to 'Ain' inside the **ADC** block.\n * The text 'AD_conversion' points to 'nADCONV' inside the **ADC** block.\n* **ADC to Register Connection (Data):** A thick wire labeled 'AD(13..0)' (marked with a slash and '14') connects the right side of the **ADC** block to the middle of the **16-bit Register**.\n* **ADC to Register Connection (Clock/Control):** A thin wire labeled 'nADBUSY' connects the bottom-right side of the **ADC** block to the bottom-right side of the **16-bit Register** (near the 'CLK' label).\n* **Register to FIFO Connection:** A thick arrow connects the right side of the **16-bit Register** to the **AD Data FIFO** block. This connection is marked with a slash and '16'.](.daq-daqe-pxi-20xx-50m-12257-1000-10/97a10cc36c3054f0c25ef30ee78df16379a4a429bb394f75196059da83729bc8.jpg) Figure 4-1: Synchronous Digital Inputs Block Diagram ![AD_conversion\nnADBUSY\n16 bits data(including AD (13..0) and SDI(1..0)\nlatched into AD Data FIFO](.daq-daqe-pxi-20xx-50m-12257-1000-10/8a16b21b69a85c00235f85ab2dd4f32186deb800092ae08fd55662e064d66920.jpg) Figure 4-2: Synchronous Digital Inputs timing ![The image displays a document icon featuring a white page with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed over the document. Below the icon, the text 'NOTE:' is written in bold, black, uppercase letters.](.daq-daqe-pxi-20xx-50m-12257-1000-10/6a9fa25dab15690e8322e748306bdebcbe4c43ebb276f5335f26ea83be9ccde8.jpg) Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D\_conversion signal), while SDI<1..0> are sam-pled right after an A/D conversion completes (rising edge of nADBUSY signal). Precisely SDI<1..0> are sampled within 220 to 400ns lag to the analog signal, due to the variation of the conversion time of the A/D converters. Table 4-1 and 4-2 illustrate the ideal transfer characteristics of various input ranges of DAQ/DAQe/PXI-20xx. The converted digital codes for DAQ/DAQe/PXI-2010 are 14-bit and 2’s complement, and here we present the codes as hexa-decimal numbers. Note that the last 2 bits of the transferred data, which are the synchronous digital input (SDI), should be ignored when retrieving the analog data.
DescriptionBipolar Analog Input RangeDigital code
Full-scale Range±10V±5V±2.5V±1.25V
Least significant bit1.22mV0.61mV0.305mV0.153mV
FSR-1LSB9.9988V4.9994V2.4997V1.2499V1FFF
Midscale +1LSB1.22mV0.61mV0.305mV0.153mV0001
Midscale0V0V0V0V0000
Midscale -1LSB-1.22mV-0.61mV-0.305mV-0.153mV3FFF
-FSR-10V-5V-2.5V-1.25V2000
Table 4-1: Bipolar analog input range and the output digital code on DAQ/ DAQe/PXI-2010 Note that the last 2 digital codes are $\mathsf { S D } | < 1 . . 0 >$ .
DescriptionUnipolar Analog Input RangeDigital code
Full-scale Range0V to 10V0 to +5V0 to +2.5V0 to +1.25V
Least significant bit0.61mV0.305mV0.153mV76.3uV
FSR-1LSB9.9994V4.9997V2.9999V1.2499V1FFF
Midscale +1LSB5.00061V2.50031V1.25015V625.08mV0001
Midscale5V2.5V1.25V625mV0000
Midscale -1LSB4.99939V2.49970V1.24985V624.92mV3FFF
-FSR0V0V0V0V2000
Table 4-2: Unipolar analog input range and the output digital code on DAQ/ DAQe/PXI-2010 Note that the last 2 digital codes are $\mathsf { S D } | < 1 . . 0 >$ . # 4.1.2 DAQ/DAQe/PXI-2005/2006 AI Data Format The data format of the acquired 16-bit A/D data is Binary coding. Table 7 and 8 illustrate the valid input ranges and the ideal transfer characteristics. The converted digital codes for DAQ/DAQe/ PXI-2005/2006 are 16-bit and direct binary, and here we present the codes as hexadecimal numbers.
DescriptionBipolar Analog Input RangeDigital code
Full-scale Range±10V±5V±2.5V±1.25V
Least significant bit305.2uV152.6uV76.3uV38.15uV
FSR-1LSB9.999695V4.999847V2.499924V1.249962VFFFF
Midscale +1LSB305.2uV152.6uV76.3uV38.15uV8001
Midscale0V0V0V0V8000
Midscale -1LSB-305.2uV-152.6uV-76.3uV-38.15uV7FFF
-FSR-10V-5V-2.5V-1.25V0000
Table 4-3: Bipolar analog input range and the output digital code on the DAQ/ DAQe/PXI-2005/2006
DescriptionUnipolar Analog Input RangeDigital code
Full-scale Range0V to 10V0 to +5V0 to +2.5V0 to +1.25V
Least signifi-cant bit152.6uV76.3uV38.15uV19.07uV
FSR-1LSB9.999847V4.999924V2.499962V1.249981VFFFF
Midscale +1LSB5.000153V2.500076V1.250038V0.625019V8001
Midscale5V2.5V1.25V0.625V8000
Midscale -1LSB4.999847V2.499924V1.249962V0.624981V7FFF
-FSR0V0V0V0V0000
Table 4-4: Unipolar analog input range and the output digital code on the DAQ/ DAQe/PXI-2005/2006 # 4.1.3 Software conversion with polling data transfer acqui-sition mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled under software. However, it is difficult to control the A/D con-version rate. # Specifying Channel, Gain, and Polarity In both the Software Polling and programmable scan acquisition mode, the channel, gain, and polarity for each channel can be specified and selected. With this configuration, signal sources must be connected to the right connector as the specified settings. When the specified channels have been sampled from the first to the last data, the settings applied to each channel would be the same until next change. # Example: Typically you can set the input configuration for different channels: ```txt Ch1 with unipolar ±10V Ch2 with bipolar ±2.5V Ch3 with no signal input (disabled) Ch4 with bipolar ±1.25V ``` # 4.1.4 Programmable scan acquisition mode Scan Timing and Procedure It's recommended that this mode be used if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least 2 counters, which need to be specified: ```txt SI_counter (24 bit): Specify the Scan Interval = SI_counter / TIMEBASE PSC_counter (24 bit): Specify Post Scan Counts, i.e. the total sample count after a trigger event, ``` The acquisition timing and the meanings of the 2 counters are illustrated in Figure 10. The SCAN\_START signal is derived from the SI\_counter, which will lead to the A/D conversion signal generation. Note that the DAQ/DAQe/PXI-20xx Series is a simultaneous sampling A/D card, so the “scan interval” equals to the “sampling interval”. Example: (Post-trigger acquisition) ```txt Set SI_counter = 160 PSC_counter = 30 TIMEBASE = Internal clock source Then Scan Interval = 160/40M s = 4 us Total acquisition time = 30 X 4 us = 120 us ``` # TIMEBASE clock source In scan acquisition mode, all the A/D conversions start on the output of counters, which use TIMEBASE as the clock source. By software you can specify the TIMEBASE to be either an internal clock source (Onboard 40MHz clock) or an external clock input (EXTTIMEBASE) on J5 connector (68-pin VHDCI). The external TIMEBASE is useful when you want to ac-quire data at rates not available with the internal A/D sample clock. The external clock source should generate TTL-compatible continuous clocks; with a maximum frequency of 40MHz while the minimum should be 1MHz. Please refer to 4.6 for information of user-controllable timing signals. ![| Scan Start | ADCONV | Acquisition_in_progress | Post Scan Count |\n| ---------- | ------ | ------------------------ | --------------- |\n| 0 | 0 | 0 | 0 |\n| 1 | 1 | 1 | 1 |\n| 2 | 2 | 2 | 2 |\n| 3 | 3 | 3 | 3 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/0d64be613c9c31b19b3ec5948a0fa9fca1e69f5493f4f06810d8757c9f5ae36b.jpg) Figure 4-3: Scan Timing There are 4 trigger modes to start the scan acquisition, please refer to section 4.1for more details. The data transfer mode is discussed below. ![The image displays a white document icon featuring horizontal gray lines and a large red checkmark superimposed over it. Below the icon is the text 'NOTE:' in black capital letters.](.daq-daqe-pxi-20xx-50m-12257-1000-10/865f3ad70a7c9b1fe79a9218539ead5adcb1f2a1d268f2dda77fc91a68fb630d.jpg) The maximum A/D sampling rate is 2MHz for DAQ/ DAQe/PXI-2010, 500kHz for DAQ/DAQe/PXI-2005, 250kHz for DAQ/DAQe/PXI-2006. Therefore, the minimum setting of SI\_counter is 20 for DAQ/DAQe/PXI-2010, 80 for DAQ/DAQe/PXI-2005, 160 for DAQ/ DAQe/PXI-2006 while using the internal TIMEBASE. The SI\_counter is a 24-bit counter. Therefore, the maximum scan in-terval while using an internal TIMEBASE = 224/40M s = 0.419s. # 4.1.5 Trigger Modes DAQ/DAQe/PXI-20xx provides 4 trigger sources (internal software trigger, ex-ternal analog trigger, external digital trigger or SSI trigger signals). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source (For example, a rising edge on the external digital trigger input). Please refer to section 4.6 for more information about SSI signals. There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger, and delay-trigger) working with the 4 trigger sources to initiate different scan data acquisition timing when a trigger event occurs. They are described as follows. For information of trigger sources, please refer to section 4.5. # Pre-Trigger Acquisition Use pre-trigger acquisition in applications where you want to collect data before a trigger event. The A/D starts to sample when you execute the specified function calls to begin the pretrigger operation, and it stops when the trigger event occurs. Users must program the value M in M\_counter (16 bits) to specify the amount of the stored scans before the trigger event. If an external trigger occurs, the program only stores the last M scans of data converted before the trigger event, as illustrated in Figure 4-4, where M\_counter = M =3, PSC\_counter = 0. The post scan count is 0 because there is no sampling after the trigger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels \* M\_counter. ![(M_counter = M = 3, PSC_counter=0)\nTrigger\nScan_start\nADCONV\nAcquisition_in_progress\nOperation start\nAcquired data\nAcquired & stored data\n(M samples)](.daq-daqe-pxi-20xx-50m-12257-1000-10/462637dc5ef2d49f414249f71e925195e2910fe61476d2fe2c69fa67f7e4a3f8.jpg) Figure 4-4: Pre-trigger (trigger occurs after at least M scans acquired) Note that If the trigger event occurs when a conversion is in progress, the data acquisition won’t stop until this conversion is completed, and the stored M scans of data include the last scan, as illustrated in Figure 4-5, where M\_counter = M =3, PSC\_counter = 0. ![(M_counter = M = 3, PSC_counter=0)\nTrigger\nScan_start\nADCONV\nAcquisition_In_progress\nTrigger occurs\nData acquisition\nwon't stop until\nthis conversion\ncompletes\nAcquired data\nAcquired & stored data\n(M samples)\nOperation start](.daq-daqe-pxi-20xx-50m-12257-1000-10/3248929c3b43ee661ebb514ae5f9d96c5b16511f5b233349fdcbf6ca8db69d46.jpg) Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a conversion is in progress) When the trigger signal occurs before the first M scans of data are con-verted, the amount of stored data could be fewer than the originally speci-fied amount M\_counter, as illustrated in Figure 4- 6. This situation can be avoided by setting M\_enable. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7. However, if M\_enable is set to 0, the trigger signal will be accepted any time, as illustrated in Figure 13. Note that the total amount of stored data will always be equal to the number in the M\_counter because the data acquisition won’t stop until a scan is completed. ![The image displays a timing diagram with the header **(M_Counter = M = 3, PSC_Counter=0)**. It depicts four signal waveforms labeled **Trigger**, **Scan_start**, **AD_conversion**, and **Acquisition_in_progress**. A vertical dashed line labeled **Operation start** marks the initial point of the sequence.\n\nThe connections and timing relationships are as follows:\n\n* **Trigger:** Shows two positive pulses. The first pulse aligns vertically with the **Operation start** line.\n* **Scan_start:** Shows two positive pulses. The first pulse occurs immediately after the **Operation start** line, and the second pulse aligns with the second **Trigger** pulse.\n* **AD_conversion:** Shows two negative pulses (low signals). The first pulse follows the first **Scan_start**, and the second pulse aligns with the second **Scan_start**.\n* **Acquisition_in_progress:** A high signal that goes active (high) at the **Operation start** line and remains active through both scan cycles, deactivating shortly after the second **AD_conversion** pulse ends.\n\nA horizontal bracket labeled **Acquired &stored data (2 scans)** spans the duration from the **Operation start** line to the end of the second **AD_conversion** pulse, indicating the total time the acquisition signal was active.](.daq-daqe-pxi-20xx-50m-12257-1000-10/f3bf150fb4bb976ac4e7307eb5e96287a3eb817db295b2d29a0cf571dbcc82f4.jpg) Figure 4-6: Pre-trigger with M\_enable = 0 (Trigger occurs before M scans) ![(M_counter = M = 3, PSC_counter=0)\nThe first M scans\nTrigger signals which occur in the shadow region (the first M scans) will be ignored\nTrigger\nScan_start\nADCO NV\nAcquisition_In_progress\nAcquired data\nAcquired & stored data (M scans)\nOperation start](.daq-daqe-pxi-20xx-50m-12257-1000-10/0f516f666960c653adfbb46f5755855d442f07a455442f5a22578ae704d9c1f6.jpg) Figure 4-7: Pre-trigger with M\_enable = 1 ![The image displays a graphic icon of a white document with a folded top-left corner and faint horizontal grey lines representing text. A large, red checkmark is superimposed diagonally across the center of the document.](.daq-daqe-pxi-20xx-50m-12257-1000-10/17296aef19d1b5d6dc3cbae42e460e3e7955dabe491fdefd23024270fdbf8f3a.jpg) NOTE: The PSC\_counter is set to 0 in pre-trigger acquisition mode. # Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M\_counter, while the number of scans (N) after the trigger is specified in PSC\_counter. Like pre-trigger mode, the number of stored data could be less than the specified amount of data (M+N), if an external trigger occurs before M scans of data are converted. The M\_enable bit in middle-trigger mode takes the same effect as in pre-trigger mode. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user with (M+N) scans of data under middle-trigger mode. However, if M\_enable is set to 0, the trigger signal will be accepted at any time. Figure 4-8 shows the acquisition timing with M\_enable=1. ![(M Counter=M=3, PSC Counter=N=1)\nThe first M scans\nTrigger signals which occur in the shadow\nreg (the first M scans) will be ignored\nTrigger\nScan_start\nADCONV\nAcquisition_in_progress\nPost Scan Count 1\n0\nAcquired data\nM scans before\ntrigger\nN scans\nafter trigger\nOperation start\nAcquired & stored data\n(M+N scans)](.daq-daqe-pxi-20xx-50m-12257-1000-10/55afce0546421093ecdfa45430a16b23f8ed10bffd95d68b0c2f2e2062cce83e.jpg) Figure 4-8: Middle trigger with M\_enable = 1 If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9. ![(M Counter=M=2, PSC Counter=N=2)\nTrigger occurs when a scan is in progress\nTrigger\nScan start\nADC0 N V\nAcquisition_In_progress\nPost Scan Count 2\n1 0\nAcquired data\nM scans before\nligger\nN scans at and\nafter ligger\nOperation start\nAcquired & stored data\n(M+N scans)](.daq-daqe-pxi-20xx-50m-12257-1000-10/a2bfa465dc121ff507d660bc17c20340d017d361b6e55bd8037be0121c7ced4f.jpg) Figure 4-9: Middle trigger (trigger when scan in progress) ![The image displays a white icon resembling a piece of paper with a folded top-right corner. Faint horizontal lines run across the lower portion of the document. A large, bold red checkmark is superimposed over the center, slanting upward from left to right.](.daq-daqe-pxi-20xx-50m-12257-1000-10/085ee1b39d855faaf711e01902e69ae94966c6429eaf4bee310b8d6ab1db07a4.jpg) NOTE: M\_counter defined in Middle-Trigger is different from that of Pre-Trigger. In Middle-trigger, M\_Counter ends counting before the trigger event while in Pre-Trigger, M\_Counter ends counting right at or before trigger event. Please refer to Figure 4-6 and Figure 4-9. # Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC\_counter, as illustrated in Figure 4-10. The total acquired data length = number of enable-channel \* PSC\_counter. ![(PSC_Counter=3)\nTrigger\nScan_start\nADCO NV\nAcquisitb_in_progress\nPost Scan Count 3\nOperation start\n2 | 1 0\nAcquired & stored data\n(3 scans)](.daq-daqe-pxi-20xx-50m-12257-1000-10/ad3e0e96b91c76678e2b0fd5514f8634bd941a9aa5cba6a532ccb76fff6724f3.jpg) Figure 4-10: Post trigger # Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay\_counter (16bit). The counter counts down on the rising edge of the Delay\_counter clock source after the trigger condition is met. The clock source can be software programmed either by the TIMEBASE clock (40MHz) or A/D sampling clock (TIMEBASE / SI\_counter). When the count reaches 0, the counter stops and the card starts to acquire data. The total acquired data length = number of enable-channel \* PSC\_counter. ![(PSC_Counter=3\nTrigger\nScan_start\nADCONV\nAcquisition_in_progress\nPost Scan Count 3\n2 1 0\nDelay until\nDelay_ Counter\nreaches 0 Acquired & stored data\n(3 scans)\nOperation start](.daq-daqe-pxi-20xx-50m-12257-1000-10/49890dccfd004a3f43609ec5d4c3cd31aa2dd37fc35b08a332faf62178561e3c.jpg) Figure 4-11: Delay trigger ![The image displays a white document icon with a folded top-right corner and faint horizontal grey lines. A large, bold red checkmark is superimposed over the document.](.daq-daqe-pxi-20xx-50m-12257-1000-10/d3182c6f6008d574488a0430e1cc31a15a00aac8025faaca5140a8126166cc94.jpg) NOTE: When the Delay\_counter clock source is set to TIMEBASE, the maximum delay time = 216/40M s = 1.638ms, and when the source is set to A/D sampling clock, the maximum delay time can be as higher as $( 2 ^ { 1 6 \mathrm { \star } } \mathsf { S } \mathsf { I } _ { - }$ \_counter / 40M ). # Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger function in ap-plications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC\_counter, and users could program Retrig\_no to specify the re-trigger numbers. Figure 4-12 il-lustrates an example. In this example, 2 scans of data is acquired after the first trigger signal, then the card waits for the re-trigger signal (re-trigger signals which occur before the first 2 scans is completed will be ignored). When the re-trigger signal occurs, 2 more scan is performed. The process repeats until specified amount of re-trigger signals are detected. The total acquired data length = number of enable-channel \* PSC\_counter \* Retrig\_no. ![(PSC_Counter=2, retrig_no=3)\nTrigger\nScan_start\nADCONV\nAcquisition_In_progress\nPost Scan Count 2 1 0 2 1 0 2 1 0 .\nAcquired & stored data\n(5 scans)\nOperation start](.daq-daqe-pxi-20xx-50m-12257-1000-10/9c32f2b33c65344391e75a93de8381f35e8f1c79e4dc21e1c6d7fbdc0eb88f06.jpg) Figure 4-12: Post trigger with re-trigger # Bus-mastering DMA Data Transfer In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention. Bus-mastering DMA provides the fastest data transfer rate on a PCI bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a user-defined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA. The DMA transfer mode is very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a highlevel programming library for high speed DMA data acquisition, you convert through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA. The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list. In a multi-user or multitasking OS, like Windows or Linux, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the noncontinuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-6 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address cycle support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs. ![Based on the provided image, here is the description of the flowchart:\n\n**Blocks:**\n* **Local Memory (FIFO)**\n* **PCI Bus**\n* **Left Block:** Contains 'First PCI Address', 'First Dual Address', 'Transfer Size', and 'Next Descriptor'.\n* **Middle Block:** Contains 'PCI Address', 'Dual Address', 'Transfer Size', and 'Next Descriptor'.\n* **Right Block:** Contains 'PCI Address', 'Dual Address', 'Transfer Size', and 'Next Descriptor'.\n\n**Connections:**\n* An arrow points upward from **Local Memory (FIFO)** to **PCI Bus**.\n* An arrow points upward from **PCI Bus** to the **Middle Block**.\n* An arrow points from the **Left Block** to the **Middle Block**.\n* An arrow points from the **Middle Block** to the **Right Block**.](.daq-daqe-pxi-20xx-50m-12257-1000-10/8da6d12c51ef06fee43851db37028c85c37fa113252123b663ab55f5017d94e9.jpg) Figure 4-13: Linked List of PCI Address DMA Descriptors In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multibuffered mode DMA. # 4.2 D/A Conversion There are 2 channels of 12-bit D/A output available in the DAQ/ DAQe/PXI-20xx. When using D/A converters, users should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. Users could also select the output polarity: unipolar or bipolar. The reference selection control lets users fully utilize the multiplying characteristics of the D/A converters. Internal 10V reference and external reference inputs are available in the DAQ/DAQe/PXI-20xx. The range of the D/A output is directly related to the reference. The digital codes that are up-dated to the D/A converters will multiply with the reference to generate the analog output. While using internal 10V reference, the full range would be –10V \~ +9.9951V in the bipolar output mode, and 0V \~ 9.9976V in the unipolar output mode. While using an external reference, users can reach different output ranges by connecting different references. For example, if connecting a DC –5V with the external reference, then the users can get a full range from –4.9976V to +5V in the bipolar output with inverting char-acteristics due to the negative reference voltage. Users could also have an amplitude modulated (AM) output by feeding a sinusoidal signal into the reference input. The range of the external reference should be within ±10V. Table 4-5 and 4-6 illustrates the relationship between digital code and output voltages.
Digital CodeAnalog Output
111111111111Vref * (2047/2048)
100000000001Vref * (1/2048)
1000000000000V
01111111111-Vref * (1/2048)
000000000000-Vref
Table 4-5: Bipolar output code table (Vref=10V if internal reference is selected)
Digital CodeAnalog Output
11111111111Vref * (4095/4096)
100000000000Vref * (2048/4096)
000000000001Vref * (1/4096)
0000000000000V
Table 4-6: Unipolar output code table (Vref=10V if internal reference is selected) The D/A conversion is initiated by a trigger source. Users must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from PC’s main memory to a buffering Data FIFO. There are two modes of the D/A conversion: Software Update and Timed Waveform Generation are described, including timing, trigger source con-trol, trigger modes and data transfer methods. Either mode may be ap-plied to D/A channels independently. You can software update DA CH0 while generate timed waveforms on CH1 at the same time. # 4.2.1 Software Update This is the easiest way to generate D/A output. First, users should specify the D/A output channels, set output polarity: unipolar or bipolar, and ref-erence source: internal 10V or external AOEX-TREF. Then update the digital values into D/A data registers through a software output command. # 4.2.2 Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters. The D/A output timing is provided through a combination of counters in the FPGA on board. There are totally 5 counters to be specified. # These counters are: ```txt UI_counter (24 bits): specify the DA Update Interval = CHUI_counter/TIMEBASE. UC_counter (24 bits): specify the total Update Counts in a single waveform IC_counter (24 bits): specify the Iteration Counts of waveform. DA_DLY1_counter (16 bits): specify the Delay from the trigger to the first update start. DA_DLY2_counter (16 bits): specify the Delay between two consecutive waveform generations. ``` Figure 21 shows a typical D/A timing diagram. D/A updates its output on each rising edge of DAWR. The meaning of the counters above is dis-cussed more in the following sections. ![4 update counts, 3 iterations\n(UC Counter=4, IC Counter=3)\nTrigger\nDAWR\nWFG_in_progress\nDelay until\nDLY1 Counter\nreaches 0\nDelay until\nDLY2 Counter\nreaches 0\nDelay until\nDLY2 Counter\nreaches 0\nDA update_interval=\nUI Counter/Timebase\nOutput Waveform\nOperation start\nA single waveform](.daq-daqe-pxi-20xx-50m-12257-1000-10/5e8bf38cc9a96ea448dc1aa279abe664ae613cf1d19361505c9be73d1e2ffcce.jpg) Figure 4-14: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) ![A white document icon featuring horizontal black lines and a large red checkmark.](.daq-daqe-pxi-20xx-50m-12257-1000-10/6438e7c35452364fb7c5ac1593dd90a034fffe3cc40171c29a03e31023d172ba.jpg) NOTE: The maximum D/A update rate is 1MHz. Therefore, the minimum setting of the UI\_counter is 40 while using an internal TIMEBASE(40MHz). # 4.2.3 Trigger Modes # Post-Trigger Generation Use post trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1\_Counter is not used and you don’t need to specify it. Figure 4-15 shows a single waveform generated right after a trigger signal is detected. The trigger signal could come from a software command, an analog trigger or a digital trigger. Please refer to section 4.5 for detailed information. ![| Signal Type | Value |\n|----------------------|-------|\n| Trigger | 8 |\n| DAMR | 8 |\n| WFG_in_progress | 8 |\n| Output Waveform | 8 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/55b0d0a493422087bcd338c04f649b3b9b2198ab7373ca5ba177c8bd79039487.jpg) Figure 4-15: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) # Delay-Trigger Generation Use delay trigger when you want to delay the waveform generation after a trigger event. In Figure 4-16, DA\_DLY1\_counter determines the delay time from the trigger signal to the start of the waveform generation. DLY1\_counter counts down on the rising edge of its clock source after the trigger condition is met. When the count reaches 0, the counter stops and the DAQ/ DAQe/PXI-20xx starts the waveform generation. This DLY1\_Counter is 16-bit’s wide and users can set the delay time in units of TIMEBASE (delay time = DLY1\_Counter/TIME-BASE) or in units of update period (delay time = DLY1\_Counter \* UI\_counter/TIMEBASE), such that the delay time can reach a wider range. ![8 update counts, 1 iterations\n(UC Counter=8, IC Counter=1)\nTrigger\nDAWR\nWFG_in_progress\nOutput Waveform\nDelay until\nDLY1_counter\nreaches 0\nOperation start](.daq-daqe-pxi-20xx-50m-12257-1000-10/0e33b2dd96b9ed7f389251183ef8e0554072922930f1e887e1bc2621b08bf484.jpg) Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) # Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation. However, the trigger event would be ignored while the waveform generation is ongoing. ![4 update count, 2 iterations\n(UC_Counter=4, IC_Counter=2)\nIgnored\nTrigger\nDAWR\nWFG_h_progress\nOutput Waveform\nOperator start\nCall software stop\nfunction to terminate\nretrigger mode\nwave form generation](.daq-daqe-pxi-20xx-50m-12257-1000-10/be3dc1c7bd49c34473c5c3b0c94c7b4bca5daac5669512ff56e087006056fc6a.jpg) Figure 4-17: Re-triggered waveform generation (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) # Iterative Waveform Generation Set IC\_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number, and the itera-tions can be finite (Figure 4-12) or infinite (Figure 4-13). A data FIFO on board is used to buffer the digital data for DA output. If the data size of a single waveform you specified (That is, Update Counts in UC\_counter) is less than the FIFO size, after initially transferring the data from the host PC memory to the FIFO on board, the data in the FIFO will be automatically re-transmitted whenever a single waveform is completed. Therefore, it won’t occupy the PCI bandwidth when repetitive waveforms are performed. However, if the size of a single waveform were larger than that of the FIFO, it needs to be intermittently loaded from the host PC’s memory via DMA, when a repetitive waveforms is performed thus PCI bandwidth would be occupied. The data FIFO size on DAQ/DAQe/PXI-2010 is 2k samples and on DAQ/DAQe/PXI-2005/2006 it is 512 samples. ![| Signal Type | Value |\n|---------------------|-------|\n| Trigger | 4 |\n| DAWR | 4 |\n| WFG_in_progress | 4 |\n| Output Waveform | 1 |\n| A single waveform | n |](.daq-daqe-pxi-20xx-50m-12257-1000-10/01421d7632c5afd899b2d59fda8286b7aa44203500fe2d5d21c9806b4e19ffbf.jpg) Figure 4-18: Finite iterative waveform generation with Post-trigger and DLY2\_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) ![4 update count, infinite iterations\n(UC Counter=4, IC Counter=4)\nTrigger\nDAWR\nWFG_h_progress\nOutput Waveform\nOperati start\nwave form generation\nwon't stop until software\nstop function is\nexecuted](.daq-daqe-pxi-20xx-50m-12257-1000-10/59e7933b67bda7677a24351301e31446874809d6d6077c3d5b66aa29b0d88329.jpg) Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2\_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) ![The image features a white document icon with a folded top-right corner and faint grey horizontal lines representing text. A large, red checkmark is superimposed over the center.](.daq-daqe-pxi-20xx-50m-12257-1000-10/4e056330057f4c84ef029d502234cb8ca8750f9fe903a73b35b9f0f851ad0af4.jpg) NOTE: When running infinite iterative waveform generation, setting IC\_Counter is ineffective to the waveform generation. It only makes a difference when setting stop mode III. How to set finite and infinite iterative waveform generation is not in-cluded in this manual. Please refer to software manual for further in-formation. # Delay2 in Repetitive Waveform Generation To diversify the D/A waveform generation, we add a DLY2 Counter to separate 2 consecutive waveforms in repetitive waveform generation. The time between two waveforms is set by the value of DLY2 Counter. The Delay2 counter starts to count down after a waveform generation finishes, and the next waveform generation starts right after it counts down to zero, just as shown in Figure 21. This DLY2\_Counter is 16-bits wide and users can set the delay time in units of TIMEBASE (delay time = DLY2\_Counter/TIMEBASE) or in units of update period (delay time = DLY2\_Counter \* UI\_counter/TIMEBASE), such that the delay time can reach a wider range # Stop Modes of Scan Update You can call software stop function to stop waveform generation when it is still in progress. Three stop modes are provided for timed waveform gen-eration, which means when it is to stop the waveform generation. You can apply these 3 modes to stop waveform generation no matter infinite or finite waveform generation mode is selected. Figure 4-20 illustrates an example for stop mode I, in this mode the waveform stops immediately when software command is asserted. In stop mode II, after a software stop command is given, the waveform generation won’t stop until a complete single waveform is finished. Take Figure 4-21 for an example, since UC\_counter is set to 4, the total DA update counts (that is, number of pulses of DAWR signal) must be a multiple of 4.(update counts = 20 in this example) In stop mode III, after a software stop command is given, the waveform generation won’t stop until the performed number of waveforms is a mul-tiple of IC\_Counter. Take Figure 4-22 for an example, since IC\_Counter is set to 3, the total generated waveforms must be a multiple of 3(waveforms = 6 in this example), and the total DA update counts must be a multiple of 12(UC\_counter \* IC\_Counter). You can compare these three figures to see their differences. ![4 update count, infinite iterations\n(UC Counter=1, IC Counter=3)\nTrigger\nDAWR\nWFG_In_progress\nOutput Waveform\nOper at start\n0\nSoftware stop command](.daq-daqe-pxi-20xx-50m-12257-1000-10/67015e6fae05ef49a9cbd73a184dff010a5aba132e9be667cd7100fb5a330ff6.jpg) Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) ![Update counts, infinite iterations\n(UC Counter=1, IC Counter=3)\nTrigger\nDAWR\nWFG_In_progress\nOutput Waveform\nOper at start\nSoftware stop command](.daq-daqe-pxi-20xx-50m-12257-1000-10/f07ec0260a024271ff33eb551cb7f0572c739a47c68f89040f0cfd88d942c28d.jpg) Figure 4-21: Stop mode II ![↓ update count, infinite iterations\n(UC Counter=4, IC Counter=3)\nTrigger\nDAWR\nWFG_h_progress\nOutput Waveform\nOperatu start\nSoftware stop command](.daq-daqe-pxi-20xx-50m-12257-1000-10/7530982d1219a5e2ad654d63c768d68c382789aa5fec86d8cba2a66cc58f5db5.jpg) Figure 4-22: Stop mode III # 4.3 Digital I/O The DAQ/DAQe/PXI-20xx contains 24-lines of general-purpose digital I/O (GPIO), which is provided through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi-vidually programmed to be either inputs or outputs. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs. DAQ/DAQe/PXI-2010 also provides 2 digital inputs per channel (SDI from J5), which are sampled simultaneously with an analog signal input and is stored with the 14-bit AD data. Please refer to section 4.1 for the more details. # 4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following features:  Count up/down controlled by hardware or software  Programmable counter clock source (internal or external clock up to 10MHz)  Programmable gate selection (hardware or software control)  Programmable input and output signal polarities (high active or low active)  Initial Count can be loaded from software  Current count value can be read-back by software without affecting circuit operation # 4.4.1 Timer/Counter functions basics Each timer/counter has three inputs that can be controlled via hardware or software. They are clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UPDOWN). The GPTC\_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UPDOWN input controls whether the counter counts up or down. The GPTC\_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications. The output of timer/counter is GPTC\_OUT. After power-up, GPTC\_OUT is pulled high by a pulled-up resister about 10K ohms. Then GPTC\_OUT goes low after the DAQ/DAQe/PXI-20xx is initialized. All the polarities of input/output signals can be programmed by software. In this chapter, for easy explanation, all GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT are assumed to be active high or rising-edge triggered in the figures. # 4.4.2 General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the soft-ware-start is re-executed. The operating theories under different modes are described as below. # Mode 1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC\_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software any time without affecting the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-23 illustrates the operation with initial count = 5, count-down mode. ![| Signal | Value |\n|--------|-------|\n| Gate | 5 |\n| CLK | 5 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/cda307d85f4d429631e99428024e04274a08d08c60b93c55476075002ee25f9d.jpg) Figure 4-23: Mode 1 Operation # Mode 2: Single Period Measurement In this mode, the counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the com-pletion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by software. Figure 4-24 il-lustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-20xx-50m-12257-1000-10/2b0c6db765ee71139ee088090035a1bb6f1cdd7eecf238e164e4069045af0e9b.jpg) Figure 4-24: Mode 2 Operation # Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT out-puts high and then current count value can be read-back by software. Figure 4-25 illustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-20xx-50m-12257-1000-10/c7e401d02f2ee0ff45af22fa54044f9e939998b2b5ffa5001560d55caadf0e24.jpg) Figure 4-25: Mode 3 Operation # Mode 4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and pro-grammable pulse-width following the software-start. The two programma-ble parameters could be specified in terms of periods of the GPTC\_CLK input by software. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|------------|-------|\n| Gate | 2 |\n| CLK | 2 |\n| Count value| 1 |\n| OUT | 0 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/bae17826869202b451671afb856405f75cbb77dd3b224ac4480f708c621a6838.jpg) Figure 4-26: Mode 4 Operation # Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC\_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC\_CLK input. Once the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until the software-start is re-executed. Figure 4-27 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|------------|-------|\n| Gate | 1 |\n| CLK | 2 |\n| Count value| 2 |\n| OUT | 1 |](.daq-daqe-pxi-20xx-50m-12257-1000-10/754e3e62fe5e1bfa6c6704e3c1e5ba14b30307802966566cfc3a6c5a2a5bdc21.jpg) Figure 4-27: Mode 5 Operation # Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After the software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE triggers that occur when the prior pulse is not completed would be ignored. Figure 4-28 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four. ![Software start\nGate\nIgnored\nCLK\nCount value 2 2 1 0 3 2 1 0 2 2 1 0 3 2 1 0 2 2\nOUT](.daq-daqe-pxi-20xx-50m-12257-1000-10/12aa1666110b6b7cd812319498d3a7bf00bb60d6b8c3bf7724e2c860eceda936.jpg) Figure 4-28: Mode 6 Operation # Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to mode5 except that the counter generates con-tinuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. Once the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until the soft-ware-start is re-executed. Figure 4-29 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value\nOUT](.daq-daqe-pxi-20xx-50m-12257-1000-10/e08bb29ddb863625f893171f8354613e9bcffaf9a451ee2fafe3f940ce1e43f8.jpg) Figure 4-29: Mode 7 Operation # Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value 4 4 3 3 2 1 0 2 1 0 3 2 1 0 2 1 1 0 3\nOUT](.daq-daqe-pxi-20xx-50m-12257-1000-10/c595d425a235e6a08a986265f0f5440f42fb5dab14c6d49667f506abdc73d626.jpg) Figure 4-30: Mode 8 Operation # 4.5 Trigger Sources We provide flexible trigger selections in the DAQ/DAQe/PXI-20xxseries products. In addition to the internal software trigger, DAQ/DAQe/PXI-20xx also supports external analog, digital triggers and SSI triggers. Users can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger. # 4.5.1 Software-Trigger This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function calls to begin the operation. A/D and D/A processes can receive an individual software trigger. # 4.5.2 External Analog Trigger The analog trigger circuitry routing is shown in the Figure 4-31. The analog multiplexer can select either a direct analog input from the EXTATRIG pin (SRC1 in Figure 4-31) in the 68-pin connector or the input signal of ADC (SRC2 in Figure 4-31). That is, one of the 4 channel inputs you can select as a trigger source). Both trigger sources can be used for all trigger modes. The range of trigger level for SRC1 is ±10V and the resolution is 78mV (please refer to Table 4-6), while the trigger range of SRC2 is the full-scale range of the selected channel input, and the resolution is the desired range divided by 256. For example, if the channel input selected to be the trigger source is set bipolar and ±5V range, the trigger voltage would be 4.96V when the trigger level code is set to 0xFF while 0V when the code is set to 0x80. ![Based on the provided image, here is the accurate description of the flowchart:\n\n**Labeled Blocks and Components:**\n* **Inputs:** CN1, CN2, CN3, CN4, and EXTA TRIG.\n* **Signal Processing:** Four rectangular blocks labeled **PGA**, four triangle symbols labeled **Instrumentation Amplifier**, four blocks labeled **ADC**, two blocks labeled **MUX**, and one block labeled **Analog Trigger Circuit**.\n* **Signal Labels:** SRC1 and SRC2.\n\n**Connections and Flow:**\n1. **Signal Path 1 (ADCs):** The inputs **CN1**, **CN2**, **CN3**, and **CN4** connect to four **PGA** blocks. The outputs of these **PGA** blocks connect to four **Instrumentation Amplifier** triangles. The outputs of these amplifiers connect to the four **ADC** blocks.\n2. **Signal Path 2 (MUX 1):** Vertical lines drop down from the outputs of the **Instrumentation Amplifier** triangles and feed into the top **MUX** block.\n3. **Signal Path 3 (Trigger Logic):** The output of the top **MUX** (labeled **SRC2**) connects to the top input of the second, larger **MUX** block. The **EXTA TRIG** input connects via a horizontal line (labeled **SRC1**) to the bottom input of this second **MUX** block.\n4. **Final Output:** The output of the second **MUX** connects to the **Analog Trigger Circuit**, which produces a pulse waveform output.](.daq-daqe-pxi-20xx-50m-12257-1000-10/66e0e09caa24d752fd0f2f41181a1a4a47dcbb7bce6644246148f04253c30c6b.jpg) Figure 4-31: Analog trigger block diagram
Trigger Level digital settingTrigger voltage
0xFF9.92V
0xFE9.84V
------
0x810.08V
0x800
0x7F-0.08V
------
0x01-9.92V
Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic The trigger signal is generated when the analog trigger condition is satis-fied. There are five analog trigger conditions in the DAQ/ DAQe/PXI-20xx. The DAQ/DAQe/PXI-20xx uses 2 threshold voltages, Low\_Threshold and High\_Threshold to build the 5 different trigger conditions. Users could configure the trigger conditions easily by software. # Below-Low analog trigger condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low\_Threshold voltage, and the High\_Threshold setting is not used in this trigger condi-tion. ![Low Threshold\nTrigger](.daq-daqe-pxi-20xx-50m-12257-1000-10/fab9d1a050e6f8e96338e1acc2c02b94b218927f65809663b10f93ae3598a09d.jpg) Figure 4-32: Below-Low analog trigger condition # Above-High analog trigger condition Figure 4-33 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than the High\_Threshold voltage, and the Low\_Threshold setting is not used in this trigger condition. ![High_Threshold\nTrigger](.daq-daqe-pxi-20xx-50m-12257-1000-10/22af9f6e1b5421b83e26b84ccc14e1a563269038a72e1d8aba18c7877196322b.jpg) Figure 4-33: Above-High analog trigger condition # Inside-Region analog trigger condition Figure 4-34 shows the inside-region analog trigger condition, the trigger signal is generated when the input analog signal level falls in the range between the High\_Threshold and the Low\_Threshold voltages. Note: the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting. ![| Time Segment | High_Threshold | Low_Threshold |\n| ------------ | -------------- | ------------- |\n| Trigger | Low | High |](.daq-daqe-pxi-20xx-50m-12257-1000-10/d6c290f5aa150f44a7464bd7f187d1f9fd2355d7298e687a4937f9b5d1d5c25e.jpg) Figure 4-34: Inside-Region analog trigger condition # High-Hysteresis analog trigger condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High\_Threshold voltage, and the Low\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting. ![| Signal Level | Description |\n| ------------------ | ------------------- |\n| Low_Threshold | High_Threshold |\n| Trigger | Trigger |](.daq-daqe-pxi-20xx-50m-12257-1000-10/a3a52f3424e51677a27e162dd59b325c5baeea5a0d2d42f529b0eb23665e5706.jpg) Figure 4-35: High-Hysteresis analog trigger condition # Low-Hysteresis analog trigger condition Figure 4-36 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low\_Threshold voltage, and the High\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting. ![| Trigger | High_Threshold | Low_Threshold |\n| ------- | -------------- | ------------- |\n| Start | Low | Low |\n| Mid | High | Low |\n| End | High | Low |](.daq-daqe-pxi-20xx-50m-12257-1000-10/bc4300a4e67ae08d5399e58c911297b95e6c9e6f0e5f76939449d20804a87745.jpg) Figure 4-36: Low-Hysteresis analog trigger condition # External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT-DTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process. Users can program the trigger polarity through ADLINK’s software drivers easily. Note that the signal level of the external digital trigger signals should be TTL-compatible, and the minimum pulse is 20ns. ![The image displays two signal waveforms illustrating digital edge triggering:\n\n1. **Left Diagram:** A signal transitions from a low state to a high state (rises). An arrow points upward along the rising edge. To the left of the transition, the text reads: 'Positive-edge trigger event occurs'.\n2. **Right Diagram:** A signal transitions from a high state to a low state (falls). An arrow points downward along the falling edge. To the right of the transition, the text reads: 'Negative-edge trigger event occurs'.](.daq-daqe-pxi-20xx-50m-12257-1000-10/0182fd4f055e4279d6d4255cfa2a81a04808b3393cde18c084b3095764a12641.jpg) Figure 4-37: External digital trigger # 4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and the re-quirements for synchronizing multiple cards, the DAQ/DAQe/ PXI-20xx Series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/DAQe/PXI-20xx Series is composed of a bunch of counters and trigger signals in the FPGA. These timing signals are related to the A/D, D/A conversions and Timer/Counter applications. These timing signals can be inputs to or outputs from the I/O connectors, the SSI connector and the PXI bus. Therefore the internal timing signals can be used to control external devices or circuitry’s. Note that in different series of DAQ/ DAQe/PXI-20xx, the user-controllable timing signals would be slightly different. However, the SSI/PXI timing signals remain the same for every DAQ/DAQe/PXI-20xx card. We implemented signal multiplexers in the FPGA to individually choose the desired timing signals for the DAQ operations, as shown in the Figure 4-38. ![Based on the provided image, here is the accurate description of the flowchart:\n\n**Labeled Blocks:**\n* Internal timing signals\n* SSI timing Signals\n* AFI timing signals\n* DAQ timing signals\n* SSI timing Signals\n* Trigger_Out timing signals\n\n**Connections:**\n1. The three blocks on the left ('Internal timing signals', 'SSI timing Signals', and 'AFI timing signals') each have three lines connecting to a vertical trapezoidal block.\n2. This first trapezoidal block connects via three lines to the central block, 'DAQ timing signals'.\n3. The 'DAQ timing signals' block connects via three lines to a second vertical trapezoidal block on the right.\n4. This second trapezoidal block splits the output: three lines connect to 'SSI timing Signals' and three lines connect to 'Trigger_Out timing signals'.](.daq-daqe-pxi-20xx-50m-12257-1000-10/44c68e94ad7992457ef649fe88389292a543d9d4d2bce531d6374cfdeabb0c6d.jpg) Figure 4-38: DAQ signals routing Users can utilize the flexible timing signals through our software drivers, and simply and correctly connect the signals with the DAQ/DAQe/PXI-20xx se-ries cards. Here is the summary of the DAQ timing signals and the corre-sponding functionalities for DAQ/DAQe/PXI-20xx Series.
Timing signal categoryCorresponding functionality
SSI/PXI signalsMultiple cards synchronization
AFI signalsControl DAQ-2000 by external timing signals
AI_Trig_Out, AO_Trig_OutControl external circuitry or boards
Table 4-8: Summary of user-controllable timing signals and the corresponding functionalities # 4.6.1 DAQ timing signals The user-controllable internal timing-signals contain: (Please refer to Section 4.1 for the internal timing signal definition) 1. TIMEBASE, providing TIMEBASE for all DAQ operations, which could be from internal 40MHz oscillator, EXTTIMEBASE from I/O connector or the SSI\_TIMEBASE. Note that the frequency range of the EXTTIMEBASE is 1MHz to 40MHz, and the EXTTIME-BASE should be TTL-compatible. 2. AD\_TRIG, the trigger signal for the A/D operation, which could come from external digital trigger, analog trigger, internal software trigger and SSI\_AD\_TRIG. Refer to Section 4.5 for detailed description. 3. SCAN\_START, the signal to start a scan, which would bring the following ADCONV signals for AD conversion, and could come from the internal SI\_counter, AFI[0] and SSI\_AD\_START. This signal is synchronous to the TIMEBASE. Note that the AFI[0] should be TTL-compatible and the minimum pulse width should be the pulse width of the TIMEBASE to guarantee correct functionalities. 4. ADCONV, the conversion signal to initiate a single conversion, which could be derived from internal counter, AFI[0] or SSI\_ADCONV. Note that this signal is edgesensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effective conversion signal. Also note that the AFI[0] signal should be TTL-compatible and the minimum pulse width is 20ns. 5. DA\_TRIG, the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trigger, internal software trigger and SSI\_AD\_TRIG. Refer to Section 4.5 for detailed de-scription. 6. DAWR, the update signal to initiate a single D/A conversion, which could be derived from internal counter, AFI[1] or SSI\_DAWR. Note that this signal is edge-sensitive. When using AFI[1] as the external DAWR source, each rising edge of AFI[1] would bring an effective update signal. Also note that the AFI[1] signal should be TTL-compatible and the minimum pulse width is 20ns. # 4.6.2 Auxiliary Function Inputs (AFI) Users could use the AFI in applications that take advantage of external circuitry to directly control the DAQ/DAQe/PXI-2000 series cards. The AFI in-cludes 2 categories of timing signals: one group is the dedicated input, and the other is the multi-function input. Table 4-9 illustrates this categorization. Table 4-9 summarizes the auxiliary function input signals and the corre-sponding functionalities
CategoryTiming signalFunctionalityConstraints
Dedicated inputEXTTIMEBASEReplace the internal TIMEBASE1. TTL-compatible
2. 1MHz to 40MHz
3. Affects on both A/D and D/A operations
EXTDTRIGExternal digi-tal trigger input for A/D operation1. TTL-compatible
2. Minimum pulse width = 20ns
3. Rising edge or fall-ing edge
EXTWFTRGExternal digi-tal trigger input for D/A operation1. TTL-compatible
2. Minimum pulse width = 20ns
3. Rising edge or fall-ing edge
Multi-function inputAFI[0] (Dual functions)Replace the internal ADCONV1. TTL-compatible
2. Minimum pulse width = 20ns
3. Rising-edge sensi-tive only
Replace the internal SCAN_START1. TTL-compatible
2. Minimum Pulse width > 2/TIMEBASE
AFI[1]Replace the internal DAWR1. TTL-compatible
2. Minimum pulse width = 20ns
3.Rising-edge sensi-tive only
Table 4-9: Auxiliary function input signals and the corresponding functionalities # EXTDTRIG and EXTWFTRIG EXTDTRIG and EXTWFTRIG are dedicated digital trigger input signals for A/D and D/A operations respectively. Please refer to section 4.5 for detailed descriptions. # EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXTTIME-BASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIME-BASE. # AFI[0] Alternatively, users can also directly apply an external A/D conversion signal to replace the internal ADCONV signal. This is another way to achieve customized sampling frequencies. The external ADCONV signal can only be inputted from the AFI[0]. As section 4.1 describes, the SI\_counter triggers the generation of the A/D conversion signal, ADCONV, but when using the AFI[0] to replace the internal ADCONV signal, then the SI\_counter and the internally generated SCAN\_START will not be effective. By controlling the ADCONV externally, users can sample the data ac-cording to external events. In this mode, the Trigger signal and trigger mode settings will are not available. AFI[0] could also be used as SCAN\_START signal for A/D operations. Please refer to sections 4.1 and 4.6.1 for detailed descriptions of the SCAN\_START signal. When using external signal (AFI[0]) to replace the internal SCAN\_START signal, the pulse width of the AFI[0] must be greater than two time of the period of Timebase. This feature is suitable for the DAQ-2200/ PXI-2200 series, which can scan multiple channels data controlled by an external event. Note that the AFI[0] is a multi-purpose input, and it can only be utilized for one function at any one time. # AFI[1] Regarding the D/A operations, users could directly input the external D/A update signal to replace the internal DAWR signal. This is another way to achieve customized D/A update rates. The external DAWR signal can only be inputted from the AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. AFI[1] currently only has one function. ADLINK reserves it for future development. # 4.6.3 System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing syn-chronization between multiple cards. In DAQ/DAQe/PXI-20xx Series, we de-signed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI signals are designed for card synchronization only, not for external devices.
SSI timing signalFunctionality
SSI_TIMEBASESSI master: send the TIMEBASE out
SSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.
Note: Affects on both A/D and D/A operations
SSI_AD_TRIGSSI master: send the internal AD_TRIG out
SSI slave: accept the SSI_AD_TRIG as the digital trigger signal.
SSI_ADCONVSSI master: send the ADCONV out
SSI slave: accept the SSI_ADCONV to replace the internal ADCONV signal.
SSI_SCAN_STARTSSI master: send the SCAN_START out
SSI slave: accept the SSI_SCAN_START to replace the internal SCAN_START signal.
SSI_DA_TRIGSSI master: send the DA_TRIG out.
SSI slave: accept the SSI_DA_TRIG as the digital trigger signal.
SSI_DAWRSSI master: send the DAWR out.
SSI slave: accept the SSI_DAWR to replace the internal DAWR signal.
Table 4-10: Summary of SSI timing signals and the corresponding functionalities as the master or slave In PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector position. All the SSI signals are routed to the 20-pin connector from the FPGA. To synchronize multiple cards, users can connect a special ribbon cable (ACL-SSI) to all the cards in a daisy-chain configuration In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections. All the SSI signals are routed to the P2 connector. No additional cable is needed. For detailed information of the PXI specifications, please refer to PXI specification Re-vision 2.0 from PXI System Alliance (www.pxisa.org). The 6 internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers. Please refer to section 4.6.1 for detailed in-formation of the 6 internal timing signals. Physically the signal routings are accomplished in the FPGA. Cards that are connected together through the SSI or the PXI trigger bus, will still achieve synchronization on the 6 timing signals. # The mechanism of the SSI/PXI 1. We adopt master-slave configuration for SSI/PXI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with the SSI function disabled. 2. For each timing signal, the SSI master doesn’t have to be in a single card. # For example: We want to synchronize the A/D operation through the ADCONV signal for 4 DAQ/DAQe/PXI-20xx cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisition. The SSI setting could be: 1. Set the SSI\_ADCONV signal of Card 1 to be the master. 2. Set the SSI\_ADCONV signals of Card 2, 3, 4 to be the slaves. 3. Set external digital trigger for Card 1’s A/D operation. 4. Set the SI\_counter and the post scan counter (PSC) of all other cards. 5. Start DMA operations for all cards, thus all the cards are waiting for the trigger event. When the digital trigger condition of Card 1 occurs, Card 1 will internally generate the ADCONV signal and output this ADCONV signal to SSI\_ADCONV signal of Card 2, 3 and 4 through the SSI/ PXI connectors. Thus we can achieve 16-channel acquisition simultaneously. You could arbitrarily choose each of the 6 timing signals as the SSI master from any one of the cards. The SSI master can output the internal timing signals to the SSI slaves. With the SSI, users could achieve better card-to-card synchronization. Note that when power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals. # 4.6.4 AI\_Trig\_Out and AO\_Trig\_Out AI\_Trig\_Out (or AO\_Trig\_Out) is the signal output following one of the four trigger sources (software trigger, analog trigger, digital trigger and SSI trigger) selected by the user. That is, AI\_Trig\_Out follows the A/D trigger source, and AO\_Trig\_Out follows the D/A trigger source. These two sig-nals can be used to control external peripheral circuits or boards, or can be used as synchronization control signals. The signal level of the AI\_Trig\_Out and AO\_Trig\_Out are TTL-compatible. ![The image displays a white sheet of paper featuring faint horizontal grey lines, resembling a document or a checklist. A large, bold red checkmark is superimposed over the center of the page.](.daq-daqe-pxi-20xx-50m-12257-1000-10/a1f669fabe5c80b4a47f8cb6f70f695b5ddb102123ab0308cff73e0f016b1451.jpg) NOTE: AI\_Trig\_Out and AO\_Trig\_Out are output pins on J5 (68-pin VHDCI). Connecting them to any signal source may cause permanent damage. # 5 Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. # 5.1 Loading Calibration Constants The DAQ/DAQe/PXI-20xx is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the Onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability. That means the calibration constants do not retain their values after the system power is turned off. Loading calibration constants is the process of loading the values of TrimDACs stored in the Onboard EEPROM. ADLINK provides software to make it easy to read the calibration constants automatically when necessary. There is a dedicated space for calibration constants In the EEPROM. In addition to the default bank of factory calibration constants, there are three extra user-modifiable banks. This means users can load the TrimDACs values either from the original factory calibration or from a calibration that is subsequently performed. Because of the fact that errors in measurements and outputs will vary with time and temperature, it is recommended re-calibratation when the card is installed in the users environment. The auto-calibration function used to minimize errors will be introduced in the next sub-section. # 5.2 Auto-calibration By using the auto-calibration feature of the DAQ/DAQe/PXI-20xx, the calibration software can measure and correct almost all the calibration errors without any external signal connections, reference voltages, or measurement de-vices. The DAQ/DAQe/PXI-20xx has an Onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured at the factory and adjusted through a digital potentiometer by using an ul-tra-precision calibrator. The impedance of the digital potentiometer is memorized after this adjustment. It is not recommended for users to adjust the Onboard calibration reference except when an ultra-precision cali-brator is available. # Note: 1. Before auto-calibration procedure starts, it is recommended to warn up the card for at least 15 minutes. 2. Please remove the cable before an auto-calibration procedure is initiated because the DA outputs would be changed in the process of calibration. # 5.3 Saving Calibration Constants After an auto-calibration is completed, users can save the new calibration constants into one of the three user-modifiable banks in the EEPROM. The date and the temperature when you ran the auto-calibration will be saved accompanied with the calibration constants. This means users can store three sets of calibration constants according to three different environ-ments and re-load the calibration constants later. # Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.  Read these safety instructions carefully.  Keep the User’s Manual for future reference.  Read the Specifications section of this manual for detailed information on the recommended operating environment.  The device can be operated at an ambient temperature of 50ºC. When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing:  Turn off power and unplug any power cords/cables.  Reinstall all chassis covers before restoring power.  To avoid electrical shock and/or damage to device:  Keep device away from water or liquid sources.  Keep device away from high heat or humidity.  Keep device properly ventilated (do not block or cover ventilation openings).  Always use recommended voltage and power source settings.  Always install and operate device near an easily accessible electrical outlet.  Secure the power cord (do not place any object on/over the power cord).  Only install/attach and operate device on stable surfaces and/or recommended mountings.  If the device will not be used for long periods of time, turn off and unplug it from its power source  Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools  A Lithium-type battery may be provided for uninterrupted backup or emergency power. ![The image displays a standard safety sign featuring a yellow triangle with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the word 'CAUTION.' is written in black capital letters.](.daq-daqe-pxi-20xx-50m-12257-1000-10/285c90fb2d90c0a68ef0b04fe4f1461f83d2babe7c2cf56f14fa2f80d88666a4.jpg) Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately. Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.  The device must be serviced by authorized technicians when:  The power cord or plug is damaged.  Liquid has entered the device interior.  The device has been exposed to high humidity and/or moisture.  The device is not functioning or does not function according to the User’s Manual.  The device has been dropped and/or damaged and/or shows obvious signs of breakage. Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.  It is recommended that the device be installed only in a server room or computer room where access is:  Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.  Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location. ![Yellow triangular warning sign with black smoke symbol indicating hot weather](.daq-daqe-pxi-20xx-50m-12257-1000-10/274537bced44f629cb07403d9681876b0975485d0b89b6a7b3a0db80a967f0f3.jpg) # BURN HAZARD Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching. # RISQUE DE BRÛLURES Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher. # Getting Service Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5723 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Straße 11 D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. 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