# DAQ/DAQe/PXI-2204/2205/2206/2208

64-/96-ch High Performance Multi-Function Data Acquisition Card User’s Manual

Manual Rev. 1.0

Revision Date: Dec. 28, 2023

Part No: 50M-12258-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.01</td><td>2007-12-04</td><td>Previous release PN: 50-11220-2010</td></tr><tr><td>1.0</td><td>2023-12-28</td><td>Initial release under new part number.Added 1.4 Software Support.Added 2.4 Switch and Jumper Settings.Added Board ID Configuration note and figure to 2.4.1.Added SSI connector pin assignment on PXI J2.Added 4.1.7 Bus-mastering DMA Data Transfer.</td></tr></table>

# Preface

# Copyright © 2023 ADLINK Technology Inc.

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# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

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NOTE:

Additional information, aids, and tips that help users perform tasks.

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CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

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WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface ........ iii

# List of Tables......... . vii

# List of Figures ....... ix

# 1 Introduction .........

1.1 Features.... 2
1.2 Applications .. 3
1.3 Specifications.... 4
1.4 Software Support .. 1 4

# 2 Installation ....... 1 9

2.1 Contents of Package ..... 1 9
2.2 Unpacking.... . 20
2.3 Card Layout .. 2 1
2.4 Switch and Jumper Settings . 2 3
2.5 PCI Configuration . 27

# 3 Signal Connections....... . 29

3.1 Connectors Pin Assignment . 2 9
3.2 Analog Input Signal Connection ..... 37

# 4 Operation Theory ........ . 41

4.1 A/D Conversion... . 41
4.2 D/A Conversion... 61
4.3 Digital I/O ..... . 71
4.4 General Purpose Timer/Counter Operation.. 71
4.5 Trigger Sources .. 7 9
4.6 User-controllable Timing Signals .... 86

# 5 Calibration ........ ... 95

5.1 Loading Calibration Constants... . 95
5.2 Auto-calibration .... 96
5.3 Saving Calibration Constants.... 96

# Important Safety Instructions....... .. 97

# Getting Service ....... ... 99

# List of Tables

Table 1-1: Programmabel Input Range.. 5

Table 1-2: Bandwidth. . 6

Table 1-3: System Noise... 7

Table 1-4: CMRR (DC to 60 Hz) ..... 7

Table 1-5: Settling Time to Full Scale Step.. 8

Table 2-1: Board ID SW1 DIP Switch Pin Definitions . . 24

Table 3-1: CN1 Pin Assignment for DAQ/DAQe/PXI-2204/2205/2206 . . 30

Table 3-2: CN1 Pin Assignment for DAQ/DAQe/PXI-2208............. 31

Table 3-3: CN2 Pin Assignment for DAQ/DAQe/PXI-2204/2205/2206 . . 32

Table 3-4: CN2 Pin Assignment for DAQ/DAQe/PXI-2208............. 33

Table 3-5: CN1/CN2 Signal Description . . 34

Table 3-6: SSI Connector Pin Assignment . . 35

Table 3-7: SSI Connector Pin Assignment on PXI J2. . 36

Table 3-8: SSI Connector Legend . . 36

Table 4-1: Bipolar Analog Input Range and Output Digital Code on DAQ/DAQe/PXI-2204/2208 . .. 43

Table 4-2: Unipolar Analog Input Range and Output Digital Code on DAQ/DAQe/PXI-2204/2208 . .. 43

Table 4-3: Bipolar Analog Input Range and Output Digital Code for DAQ/DAQe/PXI-2205/2206... .. 44

Table 4-4: Unipolar Analog Input Range and Output Digital Code for DAQ/DAQe/PXI-2205/2206. .. 44

Table 4-5: Bipolar Output Code Table .. .. 61

Table 4-6: Unipolar Output Code Table.. . 62

Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic.. .. 80

Table 4-8: User-controllable Timing Signals and Functionalities .... 87

Table 4-9: Auxiliary Function Input Signals and Functionalities...... 89

Table 4-10: SSI Timing Signal and Functions... . 91

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# List of Figures

Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout... .... 21

Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout .. .. 22

Figure 2-3: PXI-2204/2205/2206/2208 Card Layout .. .. 22

Figure 2-4: Board ID SW1 DIP Switch ... .. 23

Figure 2-5: Enable Board ID Configuration... .. 25

Figure 2-6: DIO Initial Status (JP4) . .. 26

Figure 3-1: Floating Source and RSE Input Connections ........... 38

Figure 3-2: Ground-referenced Sources and NRSE Input Connections.... .. 39

Figure 3-3: Ground-referenced Source and Differential Input..... 39

Figure 3-4: Floating Source and Differential Input . .. 40

Figure 4-1: Synchronous Digital Inputs Block Diagram ..... ..... 42

Figure 4-2: Synchronous Digital Inputs Timing . .. 42

Figure 4-3: Scan Timing.... .. 47

Figure 4-4: Pre-trigger (Trigger occurs after M scans).... .. 50

Figure 4-5: Pre-trigger (Trigger with scan in progress) ............... 51

Figure 4-6: Pre-trigger with M\_enable=0 (Trigger occurs before M scans)... . 52

Figure 4-7: Pre-trigger with M\_enable=1 . 53

Figure 4-8: Middle-Trigger with M\_enable = 1 . .. 54

Figure 4-9: Middle-Trigger (Trigger occurs when a scan is in progress)............. 55

Figure 4-10: Post-trigger .. .. 56

Figure 4-11: Delay trigger . .. 57

Figure 4-12: Post trigger with Re-trigger.. .. 58

Figure 4-13: Linked List of PCI Address DMA Descriptors ........... 60

Figure 4-14: Typical D/A Timing of Waveform Generation ........... 64

Figure 4-15: Post Trigger Waveform Generation.. .. 65

Figure 4-16: Delay Trigger Waveform Generation... .. 66

Figure 4-17: Re-triggered Waveform Generation with Post-Trigger (DLY2\_Counter=0).. .. 66

Figure 4-18: Finite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0).. . 67

Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0).. . 68

Figure 4-20: Stop Mode I .. .. 69

Figure 4-21: Stop Mode II . .. 70

Figure 4-22: Stop Mode III . .. 70

Figure 4-23: Mode1 Operation.. . 73

Figure 4-24: Mode2 Operation.... . 73

Figure 4-25: Mode3 Operation.. . 74

Figure 4-26: Mode4 Operation.. . 75

Figure 4-27: Mode5 Operation.. . 76

Figure 4-28: Mode6 Operation... . 77

Figure 4-29: Mode7 Operation.. . 77

Figure 4-30: Mode8 Operation.... . 78

Figure 4-31: Analog Trigger Block Diagram. . 80

Figure 4-32: Below-Low Analog Trigger Condition . .81

Figure 4-33: Above-High Analog Trigger Condition ..... .. 81

Figure 4-34: Inside-Region Analog Trigger Condition.. . 82

Figure 4-35: High-Hysteresis Analog Trigger Condition..... . 83

Figure 4-36: Low-Hysteresis Analog Trigger Condition ...... . 84

Figure 4-37: External Digital Trigger . . 85

Figure 4-38: DAQ signals routing.. . 86

# 1 Introduction

The DAQ/DAQe/PXI-2204/2205/2206/2208 card is an advanced data acquisition card based on the 32-bit PCI or PCI Express® architecture. High performance designs and state-of-the-art technology make these cards ideal for data logging and signal analysis applications in medical, process control, etc.

# 1.1 Features

The DAQ/DAQe/PXI-2204/2205/2206/2208 advanced data acquisition card has the following features:

 32-bit PCI bus (DAQ/PXI models) or PCI Express (DAQe model), plug and play
 Up to 96 single-ended inputs or 48 differential inputs supporting combinations of SE and DI analog input signals
 Up to 1024 words analog input Channel Gain Queue configuration size
 Analog input resolution and sampling rate:

 DAQ/DAQe/PXI-2204/2208: 12-bit and up to 3 MHz
 DAQ/DAQe/PXI-2205: 16-bit and up to 500 KHz
 DAQ/DAQe/PXI-2206: 16-bit and up to 250 KHz

 Programmable bipolar/unipolar analog input

 Programmable gain:

 DAQ/DAQe/PXI-2204/2208: x1, x2, x4, x5, x8, x10, x20, x40, x50, x200
 DAQ/DAQe/PXI-2205/2206: x1, x2, x4, x8

 A/D FIFO size: 1024 samples

Versatile trigger sources: software trigger, external digital trigger, analog trigger and trigger from System Synchronization Interface (SSI)

 A/D data transfer: software polling and bus-mastering DMA with scatter/gather functionality

 Four A/D trigger modes including post-trigger, delay-trigger, pre-trigger and middle-trigger

Two-channel D/A outputs with waveform generation capability (except DAQ/DAQe/PXI-2208)

 1024 word length output data FIFO for D/A channels

 D/A data transfer: Software update and bus-mastering DMA with scatter/gather functionality

 Support System Synchronization Interface (SSI)

 Full A/D and D/A auto-calibration

 Jumper-free and software-configurable

# 1.2 Applications

 Automotive Testing
 Cable Testing
 Transient signal measurement
 ATE
 Laboratory Automation
 Biotech measurement

# 1.3 Specifications

# Analog Input (AI)

 Programmable channels:

 DAQ/DAQe/PXI-2204/2205/2206: 64 single-ended (SE) or 32 differential input (DI)
 DAQ/DAQe/PXI-2208: 96 single-ended (SE) or 48 differential input (DI)
 Mixing of SE and DI analog signal sources (Software selectable per channel)

 A/D converter:

 DAQ/DAQe/PXI-2204/2008: LT1412 or equivalent
 DAQ/DAQe/PXI-2205: A/D7665 or equivalent
 DAQ/DAQe/PXI-2206: A/D7663 or equivalent

 Max sampling rate:

 DAQ/DAQe/PXI-2204/2008: 3 MS/s (single-channel) 1 MS/s (multi-channel)
 DAQ/DAQe/PXI-2205: 500 kS/s
 DAQ/DAQe/PXI-2206: 250 kS/s

 Resolution:

 DAQ/DAQe/PXI-2204/2208: 12-bit, no missing code
 DAQ/DAQe/PXI-2205/2206: 16-bit, no missing code

 Input coupling: DC

 FIFO buffer size:

 DAQ/DAQe/PXI-2010: 8K samples
 DAQ/DAQe/PXI-2005/2006/2016: 512 samples

 Programmable input range:

<table><tr><td>Device</td><td>Bipolar input range</td><td>Unipolar input range</td></tr><tr><td rowspan="10">2204/2208</td><td>±10 V</td><td>—</td></tr><tr><td>±5 V</td><td>0 to 10 V</td></tr><tr><td>±2.5 V</td><td>0 to 5 V</td></tr><tr><td>±2 V</td><td>0 to 4 V</td></tr><tr><td>±1.25 V</td><td>0 to 2.5 V</td></tr><tr><td>±1 V</td><td>0 to 2 V</td></tr><tr><td>±0.5 V</td><td>0 to 1 V</td></tr><tr><td>±0.25 V</td><td>0 to 0.5 V</td></tr><tr><td>±0.2 V</td><td>0 to 0.4 V</td></tr><tr><td>±0.05 V</td><td>0 to 0.1 V</td></tr><tr><td rowspan="4">2205/2206</td><td>±10 V</td><td>0 to 10 V</td></tr><tr><td>±5 V</td><td>0 to 5 V</td></tr><tr><td>±2.5 V</td><td>0 to 2.5 V</td></tr><tr><td>±1.25 V</td><td>0 to 1.25 V</td></tr></table>

Table 1-1: Programmabel Input Range

 Operational common mode voltage range: ±11V
 Over-voltage protection:

 Power on: Continuous ±30V
 Power off: Continuous ±15V

 FIFO buffer size: 1024 samples
 Data transfers:

 Programmed I/O
 Bus-mastering DMA with scatter/gather

 Channel Gain Queue configuration size:

 DAQ/DAQe/PXI-2204/2205/2206: 512 words
 DAQ/DAQe/PXI-2208: 1024 words

 Bandwidth (Typical $2 5 ^ { \circ } \mathrm { C } )$ :

<table><tr><td>Device</td><td colspan="2">Input range</td><td>Small signal bandwidth (-3dB)</td><td>Large signal bandwidth (1% THD)</td></tr><tr><td rowspan="10">2204/2208</td><td>±10 V</td><td>—</td><td rowspan="4">2000 kHz</td><td rowspan="4">—</td></tr><tr><td>±5 V</td><td>0 V to 10 V</td></tr><tr><td>±2.5 V</td><td>0 V to 5 V</td></tr><tr><td>±1.25 V</td><td>0 V to 2.5 V</td></tr><tr><td>±2 V</td><td>0 V to 4 V</td><td rowspan="2">1450 kHz</td><td rowspan="2">—</td></tr><tr><td>±0.5 V</td><td>0 V to 1 V</td></tr><tr><td>±1 V</td><td>0 V to 2 V</td><td rowspan="2">990 kHz</td><td rowspan="2">—</td></tr><tr><td>±0.25 V</td><td>0 V to 0.5 V</td></tr><tr><td>±0.2 V</td><td>0 V to 0.4 V</td><td rowspan="2">240 kHz</td><td rowspan="2">—</td></tr><tr><td>±0.05 V</td><td>0 V to 0.1 V</td></tr><tr><td rowspan="4">2205</td><td>±10 V</td><td>0 V to 0 V</td><td>1600 kHz</td><td>300 kHz</td></tr><tr><td>±5 V</td><td>0 V to 5 V</td><td>1400 kHz</td><td>310 kHz</td></tr><tr><td>±2.5 V</td><td>0 V to 2.5 V</td><td>1000 kHz</td><td>310 kHz</td></tr><tr><td>±1.25 V</td><td>0 V to 1.25 V</td><td>600 kHz</td><td>330 kHz</td></tr><tr><td rowspan="4">2206</td><td>±10 V</td><td>0 V to 10 V</td><td>760 kHz</td><td>300 kHz</td></tr><tr><td>±5 V</td><td>0 V to 5 V</td><td>720 kHz</td><td>310 kHz</td></tr><tr><td>±2.5 V</td><td>0 V to 2.5 V</td><td>610 kHz</td><td>310 kHz</td></tr><tr><td>±1.25 V</td><td>0 V to 1.25 V</td><td>450 kHz</td><td>330 kHz</td></tr></table>

Table 1-2: Bandwidth

 System Noise (LSBrms, including Quantization, Typical, $2 5 ^ { \circ } \mathrm { C } )$

<table><tr><td>Device</td><td>Input Range</td><td>System Noise</td><td>Input Range</td><td>System Noise</td></tr><tr><td rowspan="4">2205</td><td>±10 V</td><td>0.95 LSBrms</td><td>0 V to 10 V</td><td>1.5 LSBrms</td></tr><tr><td>±5 V</td><td>1.0 LSBrms</td><td>0 V to 5 V</td><td>1.6 LSBrms</td></tr><tr><td>±2.5 V</td><td>1.1 LSBrms</td><td>0 V to 2.5 V</td><td>1.7 LSBrms</td></tr><tr><td>±1.25 V</td><td>1.3 LSBrms</td><td>0 V to 1.25 V</td><td>1.9 LSBrms</td></tr><tr><td rowspan="4">2206</td><td>±10 V</td><td>0.8 LSBrms</td><td>0 V to 10 V</td><td>0.9 LSBrms</td></tr><tr><td>±5 V</td><td>0.85 LSBrms</td><td>0 V to 5 V</td><td>1.0 LSBrms</td></tr><tr><td>±2.5 V</td><td>0.85 LSBrms</td><td>0 V to 2.5 V</td><td>1.0 LSBrms</td></tr><tr><td>±1.25 V</td><td>0.9 LSBrms</td><td>0 V to 1.25 V</td><td>1.2 LSBrms</td></tr></table>

Table 1-3: System Noise

 Input impedance:

 Normal power on: 1 G/100 pF

 Power off: 820 

 Overload: 820 

 CMRR (DC to 60 Hz, Typical)

<table><tr><td>Device</td><td>Input Range</td><td>CMRR</td><td>Input Range</td><td>CMRR</td></tr><tr><td>2204/2208</td><td>All ranges</td><td>90 dB</td><td>—</td><td>—</td></tr><tr><td rowspan="4">2205/2206</td><td>±10 V</td><td>83 dB</td><td>0 V to 10 V</td><td>87 dB</td></tr><tr><td>±5 V</td><td>87 dB</td><td>0 V to 5 V</td><td>90 dB</td></tr><tr><td>±2.5 V</td><td>90 dB</td><td>0 V to 2.5 V</td><td>92 dB</td></tr><tr><td>±1.25 V</td><td>92 dB</td><td>0 V to 1.25 V</td><td>93 dB</td></tr></table>

Table 1-4: CMRR (DC to 60 Hz)

 Settling time to full-scale step (Typical, $2 5 ^ { \circ } \mathrm { C } )$ :

<table><tr><td>Device</td><td colspan="2">Input Range</td><td>Condition</td><td>Settling time</td></tr><tr><td rowspan="16">2204/2208</td><td colspan="2">±10 V</td><td rowspan="6">Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td rowspan="6">1 μs to 0.1% error</td></tr><tr><td>±5 V</td><td>0 to 10 V</td></tr><tr><td>±2.5 V</td><td>0 to 5 V</td></tr><tr><td>±2 V</td><td>0 to 4 V</td></tr><tr><td>±1.25 V</td><td>0 to 2.5 V</td></tr><tr><td>±0.5 V</td><td>0 to 1 V</td></tr><tr><td colspan="2">±10 V</td><td rowspan="6">Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td rowspan="6">1.25 μs to 0.1% error</td></tr><tr><td>±5 V</td><td>0 to 10 V</td></tr><tr><td>±2.5 V</td><td>0 to 5 V</td></tr><tr><td>v2 V</td><td>0 to 4 V</td></tr><tr><td>±1.25 V</td><td>0 to 2.5 V</td></tr><tr><td>±0.5 V</td><td>0 to 1 V</td></tr><tr><td>±1 V</td><td>0 to 2 V</td><td rowspan="2">Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td rowspan="2">2 μs to 0.1% error</td></tr><tr><td>±0.25 V</td><td>0 to 0.5 V</td></tr><tr><td>±0.2 V</td><td>0 to 0.4 V</td><td rowspan="2">Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td rowspan="2">5 μs to 0.1% error</td></tr><tr><td>±0.05 V</td><td>0 to 0.1 V</td></tr><tr><td rowspan="2">2205/2206</td><td colspan="2">All Ranges</td><td>Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td>2 μs to 0.1% error,4 μs to 0.01% error</td></tr><tr><td colspan="2">All Ranges</td><td>Multiple channels,multiple ranges.All samples in unipolar/bipolar mode.</td><td>2 μs to 0.2% error,4 μs to 0.01% error</td></tr></table>

Table 1-5: Settling Time to Full Scale Step

 Time-base source:

 Internal 40 MHz or external clock Input $( \mathfrak { f } _ { \mathrm { m a x } } )$ 40 MHz, $\mathsf { f } _ { \mathsf { m i n } } .$ 1 MHz, 50% duty cycle)

 Trigger modes: Post-trigger, delay-trigger, pre-trigger and middle-trigger

 Offset error:

 ±50mV max. for DAQ/DAQe/PXI-2204/2208

 ±1mV max. for DAQ/DAQe/PXI-2205/2206

 Gain error (relative to calibration reference):

 0.6% of reading max. for DAQ/DAQe/PXI-2204/2208

 0.05% of reading max. for DAQ/DAQe/PXI-2205/2206

# Analog Output (AO)

NOTEThe DAQ/DAQe/PXI-2208 card does not support this function.

 Channels: Two-channel analog voltage output
 DA converter: LTC7545 or equivalent
 Max update rate: 1 MS/s
 Resolution: 12-bit
 FIFO buffer size:

 512 samples per channel when both channels are enabled for timed DA output
 1024 samples when only one channel is used for timed DA output

 Data transfers:

 Programmed I/O
 Bus-mastering DMA with scatter/gather

 Output range: ±10 V, 0 V to 10 V, ±AOEXTREF, 0 to AOEX-TREF

 Settling time: 3 S to 0.5 LSB accuracy

 Slew rate: 20 V/µS

 Output coupling: DC

 Protection: Short-circuit to ground

 Output impedance: 0.01 typical

 Output driving current: ±5 mA max

 Stability: Any passive load, up to 1500 pF

 Power-on state: 0V steady-state

 Power-on glitch: ±1.5 V/500 µS

 Relative accuracy: ±0.5 LSB typical, ±1 LSB max

 DNL: ±0.5 LSB typical, ±1.2 LSB max

 Offset error: ±1 mV max

 Gain error: ±0.05% of output max

# General Purpose Digital I/O (G.P. DIO, 82C55A)

 Channels: 24 programmable input/output
 Compatibility: TTL
 Input voltage:

 Logic Low: VIL=0.8 V max; IIL=0.2 mA max

 High: VIH=2.0 V max; IIH=0.02 mA max

 Output voltage:

 Low: VOL=0.5 V max; IOL=8 mA max
 High: VOH=2.7 V min; IOH=400 µA

 Synchronous Digital Inputs (SDI): On DAQ/DAQe/PXI-2204 model only.

 Channels: 8 digital inputs sampled simultaneously with the analog signal input
 Compatibility: TTL/CMOS
 Input voltage:

Logic Low: VIL=0.8 V max; IIL=0.2mA max

Logic High: VIH=2.7 V min; IIL=0.02mA max

# General Purpose Timer/Counter (GPTC)

NOTEThe DAQ/DAQe/PXI-2208 does not support this function.

 Channels: 2 independent up/down timer/counters
 Resolution: 16-bit
 Compatibility: TTL
 Clock source: Internal or external
 Max source frequency: 10 MHz

# Analog Trigger (A.Trig)

 Source:
 All analog input channels  External analog trigger (EXTATRIG)
 Level: ±Full-scale, internal; ±10 V external
 Resolution: 8-bit
 Slope: Positive or negative (software-selectable)
 Hysteresis: Programmable
 Bandwidth: 400 kHz

# External Analog Trigger Input (EXTATRIG)

 Input Impedance:
 40 k for DAQ/DAQe/PXI-2204/2208
 20 k for DAQ/DAQe/PXI-2205/2206

 Coupling: DC

 Protection: Continuous ±35 V maximum

# Digital Trigger (D.Trig)

 Compatibility: TTL/CMOS
 Response: Rising or falling edge
 Pulse Width: 10 ns min

# System Synchronous Interface (SSI)

 Trigger lines: 7

# Stability

 Recommended warm-up time: 15 minutes
 On-board calibration reference:
 Level: 5.000 V
 Temperature coefficient: ±2 ppm/C
 Long-term stability: 6 ppm/1000 Hr

# Physical

 Dimensions:
 175mm by 107mm for DAQ-/DAQe-2204/2205/2206/ 2208
 Standard CompactPCI form factor for PXI-2204/2205/ 2206/2208
 I/O connector: 68-pin female VHDCI type (e.g. AMP-787254-1)

# Power Requirement (typical)

 +5 VDC
 1.3 A for DAQ/DAQe/PXI-2204
 1.2 A for DAQ/DAQe/PXI-2205/2206
 950 mA for DAQ/DAQe/PXI-2208

 +12 VDC
 358 mA for DAQe-2204
 344 mA for DAQe-2205
 390 mA for DAQe-2206
 258 mA for DAQe-2208

 +3.3 VDC
 815 mA for DAQe-2204
 735 mA for DAQe-2205
 710 mA for DAQe-2206
 815 mA for DAQe-2208

# Operating Environment

 Ambient temperature: 0C to $5 5 ^ { \circ } \mathrm { C }$
 Relative humidity: 10% to 90% non-condensing

# Storage Environment

 Ambient temperature: -20C to ${ } ^ { 8 0 ^ { \circ } \mathsf { C } }$
 Relative humidity: 5% to 95% non-condensing

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platforms.

By leveraging low-level kernel management and a user friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![The diagram is organized into four main horizontal sections, arranged from top to bottom:\n\n**1. Top Section (Split Layout)**\n*   **Left Column (Red Background):** Titled 'MAPS Core Device Management,' containing four stacked grey blocks:\n    *   'Device Manager (ACE)'\n    *   'PXI Platform Resource Mgmt. Utility'\n    *   'PXI Platform ChassisWatch Utility'\n    *   'DAQ/IO Module Function Test Utility'\n*   **Right Columns (Three Vertical Stacks):**\n    *   **Stack 1:** White block 'User APPs in C/C++' sits above an orange block labeled 'MAPS/C', 'C/C++ SDK', 'for DAQ/IO module'.\n    *   **Stack 2:** White block 'User APPs in LabVIEW' sits above a green block labeled 'MAPS/LV', 'LabVIEW SDK', 'for DAQ/IO module'.\n    *   **Stack 3:** White block 'User APPs in C#' sits above a purple block labeled 'MAPS/C#', 'C# SDK', 'for DAQ/IO module', 'Coming soon'.\n\n**2. Middle Section (Red Background)**\n*   Left side text: 'MAPS Core -Device Runtime'\n*   Right side text (stacked vertically):\n    *   'PXI Platform Service'\n    *   'DAQ/IO Module Device Driver'\n    *   'DAQ/IO Module Runtime Library'\n\n**3. Bottom Section (Blue Background)**\n*   Displays five hardware categories horizontally with images:\n    *   'Digitizers'\n    *   'DAQ'\n    *   'Edge Platform'\n    *   'PXle Controllers'\n    *   'PXle/PXI Chassis'](.daq-daqe-pxi-220x-50m-12258-1000-10/2b401f802e2911517ed96acff415fa88b77b2d1a1a72445d9e04f5d44559c338.jpg)

# 1.4.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCI9112 Device 'PCI-9'\nUSB\nGeneral\nSettings\nAlias Name PCI-9112-0\nVendor ADLINK Technology Inc.\nModel PCI9112 Device\nPCI Bus 2\nPCI Device 11\nPCI Function 0\nDMA Buffer\nAI 1024 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch\nCorelib](.daq-daqe-pxi-220x-50m-12258-1000-10/b6c5c403e6b3cdfdb7d65e0b0434ce4f387b76e9a0e2873fda5b595f09de5538.jpg)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen.

![| Time (Sec) | Voltage (Vpp) |\n| ---------- | ------------- |\n| 0.00       | 5             |\n| 0.02       | 10            |\n| 0.03       | 5             |\n| 0.04       | 0             |\n| 0.05       | -5            |\n| 0.06       | -10           |\n| 0.07       | -10           |\n| 0.08       | -5            |\n| 0.09       | 5             |\n| 0.10       | 5             |](.daq-daqe-pxi-220x-50m-12258-1000-10/1a95f568ab8df565ce8a019ad49372d81899526557edfbb1e51aa439f499835f.jpg)

# 1.4.2 MAPS/LV, LabVIEW Support

Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual:

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_LV

# 1.4.3 MAPS/C, C & C++ Support

Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_C

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# 2 Installation

This chapter describes how to install the DAQ/DAQe/PXI-2204/ 2205/2206/2208 card. The contents of the package and unpacking information that you should be aware of are outlined first.

# 2.1 Contents of Package

In addition to this User's Manual, the package includes the following items:

 DAQ/DAQe/PXI-2204/2205/2206/2208 multi-function data acquisition card
 Software Installation Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

# 2.2 Unpacking

Your DAQ/DAQe/PXI-2204/2205/2206/2208 card contains electro-static sensitive components that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card package for obvious damages. Shipping and handling may cause damage to the card. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

You are now ready to install your DAQ/DAQe/PXI-2204/2205/ 2206/2208 card.

![The image displays a white document icon with a folded top-right corner and faint horizontal lines representing text. Overlaid on the document is a large, bold, red checkmark.](.daq-daqe-pxi-220x-50m-12258-1000-10/5ad3365b25a1757a117954b0c11e6f815606b78dd9bb76a94535c1ec19a2369d.jpg)
NOTE:

DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

# 2.3 Card Layout

# 2.3.1 DAQe-2204/2205/2206/2208

![Board to Board Connector\n68-Pin Connector\nDaughter Board\nBoard to Board Connector\nCarrier Board](.daq-daqe-pxi-220x-50m-12258-1000-10/6ff84e23872818188261d0869ed4c3faf8058c827b453412194eb6252befd0c3.jpg)

Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout

2.3.2 DAQ-2204/2205/2206/2208
![CN1\n68 PIN Connector\nBoard to Board connector\nDaughter Board\nCN2\nBoard to Board connector\nSSI connector\nCarrier Board](.daq-daqe-pxi-220x-50m-12258-1000-10/93c53847aed2fb443ec1dc3701d4c7d6d34cb7e4a3f96b086741cb92f0baa03f.jpg)

Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout

2.3.3 PXI-2204/2205/2206/2208
![CN1\n68 PIN Connector\nBoard to Board connector\nDaughter Board\nCN2\nBoard to Board connector\nCarrier Board](.daq-daqe-pxi-220x-50m-12258-1000-10/1ea0bed85b35510c1102166e1cc638dcc26c333ec8fdb9541407e0bc656b222b.jpg)

Figure 2-3: PXI-2204/2205/2206/2208 Card Layout

# 2.4 Switch and Jumper Settings

# 2.4.1 Board ID (SW1)

The DAQ/DAQe-2000 Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for identifying each card’s device number. After setting each DAQ/ DAQe-2000 Series card, you can identify each card in the system with different device numbers. The default value of the Board ID is 0 and if you need to adjust it to another value, set the SW1 switch as shown in the table below.

![ON\nDIP\n1 2 3 4](.daq-daqe-pxi-220x-50m-12258-1000-10/536c6634bb18c961be106ae39508c11e32481c7a65d48b5b55694feae6150e0b.jpg)

Figure 2-4: Board ID SW1 DIP Switch

<table><tr><td>SW1</td><td>Pin 1</td><td>Pin 2</td><td>Pin 3</td><td>Pin 4</td></tr><tr><td>Board ID</td><td>ID0</td><td>ID1</td><td>ID2</td><td>ID3</td></tr><tr><td>0</td><td>Off</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>1</td><td>On</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>2</td><td>Off</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>3</td><td>On</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>4</td><td>Off</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>5</td><td>On</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>6</td><td>Off</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>7</td><td>On</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>8</td><td>Off</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>9</td><td>On</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>10</td><td>Off</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>11</td><td>On</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>12</td><td>Off</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>13</td><td>On</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>14</td><td>Off</td><td>On</td><td>On</td><td>On</td></tr><tr><td>15</td><td>On</td><td>On</td><td>On</td><td>On</td></tr></table>

Table 2-1: Board ID SW1 DIP Switch Pin Definitions

![The image displays a graphic icon of a white document with faint horizontal lines and a folded top-right corner. Overlaid on the document is a large, bold red checkmark.](.daq-daqe-pxi-220x-50m-12258-1000-10/6e60b5166374f11bd3d1e5b742b272995b4016d01e5854ddd926203f093b2c0c.jpg)
NOTE:

Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K\_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select your Card Type and uncheck Ignore Board ID. See figure below.

![DAQ2000 Device Driver Configuration\nThis utility is used for the cards that will perform continuous AI, DI or DO operation\nCard Type: Daq2016\nDaq2010\nDaq2205\nDaq2206\nAI : Daq2005\nDaq2204\nAO : Daq2006\nDaq2501\nDaq2502\nDI : Daq2208\nDaq2213\nDO : Daq2214\nIgnore Board ID No Reset\nOK Apply Cancel](.daq-daqe-pxi-220x-50m-12258-1000-10/8260f4e58cde0a48caa4525c707d4d0c544cb7aae117201f08676e86b9c4fcc2.jpg)

Figure 2-5: Enable Board ID Configuration

# 2.4.2 DIO Initial Status (JP4)

The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below.

![Disabled\nJP4\nEnabled\nJP4](.daq-daqe-pxi-220x-50m-12258-1000-10/ffe91e7f9506e76af701421a19bf400e6ad5fd9c963d966815e9de2bf312cda0.jpg)

Figure 2-6: DIO Initial Status (JP4)

# 2.5 PCI Configuration

# 2.5.1 Plug and Play

With support for plug and play, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system.

# 2.5.2 Configuration

The board configuration is done on a board-by-board basis for all PCI boards in the system. Because configuration is controlled by the system and software, there is no jumper setting required for base address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the system as new boards are added or removed.

# 2.5.3 Troubleshooting

If your system doesn’t boot or if you experience erratic operation with your PCI board in place, it is likely caused by an interrupt conflict. The BIOS Setup may be incorrectly configured. Consult the BIOS documentation that comes with your system to solve this problem.

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# 3 Signal Connections

This chapter describes DAQ/DAQe/PXI-2204/2205/2206/2208 card connectors and the signal connection between the DAQ/ DAQe/PXI-2204/2205/2206/2208 card and external devices.

# 3.1 Connectors Pin Assignment

The DAQ/DAQe/PXI-2204/2205/2206/2208 card is equipped with two 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input/output, timer/counter signals, etc. One 20-pin ribbon male connector is used for SSI (System Synchronous Interface) in DAQ-/DAQe-2204/2205/2206/2208 card. The pin assignments of the connectors are defined in Table 3-1, Table 3-2, Table 3-3, and Table 3-4.

# 3.1.1 CN1 Connector

<table><tr><td>AI0 (AIH0)</td><td>1</td><td>35</td><td>(AIL0) AI32</td></tr><tr><td>AI1 (AIH1)</td><td>2</td><td>36</td><td>(AIL1) AI33</td></tr><tr><td>AI2 (AIH2)</td><td>3</td><td>37</td><td>(AIL2) AI34</td></tr><tr><td>AI3 (AIH3)</td><td>4</td><td>38</td><td>(AIL3) AI35</td></tr><tr><td>AI4 (AIH4)</td><td>5</td><td>39</td><td>(AIL4) AI36</td></tr><tr><td>AI5 (AIH5)</td><td>6</td><td>40</td><td>(AIL5) AI37</td></tr><tr><td>AI6 (AIH6)</td><td>7</td><td>41</td><td>(AIL6) AI38</td></tr><tr><td>AI7 (AIH7)</td><td>8</td><td>42</td><td>(AIL7) AI39</td></tr><tr><td>AI8 (AIH8)</td><td>9</td><td>43</td><td>(AIL8) AI40</td></tr><tr><td>AI9 (AIH9)</td><td>10</td><td>44</td><td>(AIL9) AI41</td></tr><tr><td>AI10 (AIH10)</td><td>11</td><td>45</td><td>(AIL10) AI42</td></tr><tr><td>AI11 (AIH11)</td><td>12</td><td>46</td><td>(AIL11) AI43</td></tr><tr><td>AI12 (AIH12)</td><td>13</td><td>47</td><td>(AIL12) AI44</td></tr><tr><td>AI13 (AIH13)</td><td>14</td><td>48</td><td>(AIL13) AI45</td></tr><tr><td>AI14 (AIH14)</td><td>15</td><td>49</td><td>(AIL14) AI46</td></tr><tr><td>AI15 (AIH15)</td><td>16</td><td>50</td><td>(AIL15) AI47</td></tr><tr><td>AISENSE</td><td>17</td><td>51</td><td>AIGND</td></tr><tr><td>AI16 (AIH16)</td><td>18</td><td>52</td><td>(AIL16) AI48</td></tr><tr><td>AI17 (AIH17)</td><td>19</td><td>53</td><td>(AIL17) AI49</td></tr><tr><td>AI18 (AIH18)</td><td>20</td><td>54</td><td>(AIL18) AI50</td></tr><tr><td>AI19 (AIH19)</td><td>21</td><td>55</td><td>(AIL19) AI51</td></tr><tr><td>AI20 (AIH20)</td><td>22</td><td>56</td><td>(AIL20) AI52</td></tr><tr><td>AI21 (AIH21)</td><td>23</td><td>57</td><td>(AIL21) AI53</td></tr><tr><td>AI22 (AIH22)</td><td>24</td><td>58</td><td>(AIL22) AI54</td></tr><tr><td>AI23 (AIH23)</td><td>25</td><td>59</td><td>(AIL23) AI55</td></tr><tr><td>AI24 (AIH24)</td><td>26</td><td>60</td><td>(AIL24) AI56</td></tr><tr><td>AI25 (AIH25)</td><td>27</td><td>61</td><td>(AIL25) AI57</td></tr><tr><td>AI26 (AIH26)</td><td>28</td><td>62</td><td>(AIL26) AI58</td></tr><tr><td>AI27 (AIH27)</td><td>29</td><td>63</td><td>(AIL27) AI59</td></tr><tr><td>AI28 (AIH28)</td><td>30</td><td>64</td><td>(AIL28) AI60</td></tr><tr><td>AI29 (AIH29)</td><td>31</td><td>65</td><td>(AIL29) AI61</td></tr><tr><td>AI30 (AIH30)</td><td>32</td><td>66</td><td>(AIL30) AI62</td></tr><tr><td>AI31 (AIH31)</td><td>33</td><td>67</td><td>(AIL31) AI63</td></tr><tr><td>EXTATRIG</td><td>34</td><td>68</td><td>AIGND</td></tr></table>

Table 3-1: CN1 Pin Assignment for DAQ/DAQe/PXI-2204/2205/2206
\* Symbols in $" ( ) "$ are for differential mode connection.

<table><tr><td>AI0 (AIH0)</td><td>1</td><td>35</td><td>(AIL0) AI48</td></tr><tr><td>AI1 (AIH1)</td><td>2</td><td>36</td><td>(AIL1) AI49</td></tr><tr><td>AI2 (AIH2)</td><td>3</td><td>37</td><td>(AIL2) AI50</td></tr><tr><td>AI3 (AIH3)</td><td>4</td><td>38</td><td>(AIL3) AI51</td></tr><tr><td>AI4 (AIH4)</td><td>5</td><td>39</td><td>(AIL4) AI52</td></tr><tr><td>AI5 (AIH5)</td><td>6</td><td>40</td><td>(AIL5) AI53</td></tr><tr><td>AI6 (AIH6)</td><td>7</td><td>41</td><td>(AIL6) AI54</td></tr><tr><td>AI7 (AIH7)</td><td>8</td><td>42</td><td>(AIL7) AI55</td></tr><tr><td>AISENSE</td><td>9</td><td>43</td><td>AIGND</td></tr><tr><td>AI8 (AIH8)</td><td>10</td><td>44</td><td>(AIL8) AI56</td></tr><tr><td>AI9 (AIH9)</td><td>11</td><td>45</td><td>(AIL9) AI57</td></tr><tr><td>AI10 (AIH10)</td><td>12</td><td>46</td><td>(AIL10) AI58</td></tr><tr><td>AI11 (AIH11)</td><td>13</td><td>47</td><td>(AIL11) AI59</td></tr><tr><td>AI12 (AIH12)</td><td>14</td><td>48</td><td>(AIL12) AI60</td></tr><tr><td>AI13 (AIH13)</td><td>15</td><td>49</td><td>(AIL13) AI61</td></tr><tr><td>AI14 (AIH14)</td><td>16</td><td>50</td><td>(AIL14) AI62</td></tr><tr><td>AI15 (AIH15)</td><td>17</td><td>51</td><td>(AIL15) AI63</td></tr><tr><td>AI16 (AIH16)</td><td>18</td><td>52</td><td>(AIL16) AI64</td></tr><tr><td>AI17 (AIH17)</td><td>19</td><td>53</td><td>(AIL17) AI65</td></tr><tr><td>AI18 (AIH18)</td><td>20</td><td>54</td><td>(AIL18) AI66</td></tr><tr><td>AI19 (AIH19)</td><td>21</td><td>55</td><td>(AIL19) AI67</td></tr><tr><td>AI20 (AIH20)</td><td>22</td><td>56</td><td>(AIL20) AI68</td></tr><tr><td>AI21 (AIH21)</td><td>23</td><td>57</td><td>(AIL21) AI69</td></tr><tr><td>AI22 (AIH22)</td><td>24</td><td>58</td><td>(AIL22) AI70</td></tr><tr><td>AI23 (AIH23)</td><td>25</td><td>59</td><td>(AIL23) AI71</td></tr><tr><td>AIGND</td><td>26</td><td>60</td><td>AIGND</td></tr><tr><td>AI24 (AIH24)</td><td>27</td><td>61</td><td>(AIL24) AI72</td></tr><tr><td>AI25 (AIH25)</td><td>28</td><td>62</td><td>(AIL25) AI73</td></tr><tr><td>AI26 (AIH26)</td><td>29</td><td>63</td><td>(AIL26) AI74</td></tr><tr><td>AI27 (AIH27)</td><td>30</td><td>64</td><td>(AIL27) AI75</td></tr><tr><td>AI28 (AIH28)</td><td>31</td><td>65</td><td>(AIL28) AI76</td></tr><tr><td>AI29 (AIH29)</td><td>32</td><td>66</td><td>(AIL29) AI77</td></tr><tr><td>AI30 (AIH30)</td><td>33</td><td>67</td><td>(AIL30) AI78</td></tr><tr><td>AI31 (AIH31)</td><td>34</td><td>68</td><td>(AIL31) AI79</td></tr></table>

Table 3-2: CN1 Pin Assignment for DAQ/DAQe/PXI-2208
\* Symbols in $^ { * } ( ) ^ { * }$ are for differential mode connection.

# 3.1.2 CN2 Connector

<table><tr><td>DA0OUT</td><td>1</td><td>35</td><td>AOGND</td></tr><tr><td>DA1OUT</td><td>2</td><td>36</td><td>AOGND</td></tr><tr><td>AOEXTREF</td><td>3</td><td>37</td><td>AOGND</td></tr><tr><td>NC</td><td>4</td><td>38</td><td>NC</td></tr><tr><td>DGND</td><td>5</td><td>39</td><td>DGND</td></tr><tr><td>EXTWFTRIG</td><td>6</td><td>40</td><td>DGND</td></tr><tr><td>EXTDTRIG</td><td>7</td><td>41</td><td>DGND</td></tr><tr><td>SSHOUT</td><td>8</td><td>42</td><td>SDI0 / DGND*</td></tr><tr><td>RESERVED</td><td>9</td><td>43</td><td>SDI1 / DGND*</td></tr><tr><td>RESERVED</td><td>10</td><td>44</td><td>SDI2 / DGND*</td></tr><tr><td>AFI1</td><td>11</td><td>45</td><td>SDI3 / DGND*</td></tr><tr><td>AFI0</td><td>12</td><td>46</td><td>DGND</td></tr><tr><td>GPTC0_SRC</td><td>13</td><td>47</td><td>DGND</td></tr><tr><td>GPTC0_GATE</td><td>14</td><td>48</td><td>DGND</td></tr><tr><td>GPTC0_UPDOWN</td><td>15</td><td>49</td><td>DGND</td></tr><tr><td>GPTC0_OUT</td><td>16</td><td>50</td><td>DGND</td></tr><tr><td>GPTC1_SRC</td><td>17</td><td>51</td><td>DGND</td></tr><tr><td>GPTC1_GATE</td><td>18</td><td>52</td><td>DGND</td></tr><tr><td>GPTC1_UPDOWN</td><td>19</td><td>53</td><td>DGND</td></tr><tr><td>GPTC1_OUT</td><td>20</td><td>54</td><td>DGND</td></tr><tr><td>EXTTIMEBASE</td><td>21</td><td>55</td><td>DGND</td></tr><tr><td>PB7</td><td>22</td><td>56</td><td>PB6</td></tr><tr><td>PB5</td><td>23</td><td>57</td><td>PB4</td></tr><tr><td>PB3</td><td>24</td><td>58</td><td>PB2</td></tr><tr><td>PB1</td><td>25</td><td>59</td><td>PB0</td></tr><tr><td>PC7</td><td>26</td><td>60</td><td>PC6</td></tr><tr><td>PC5</td><td>27</td><td>61</td><td>PC4</td></tr><tr><td>DGND</td><td>28</td><td>62</td><td>DGND</td></tr><tr><td>PC3</td><td>29</td><td>63</td><td>PC2</td></tr><tr><td>PC1</td><td>30</td><td>64</td><td>PC0</td></tr><tr><td>PA7</td><td>31</td><td>65</td><td>PA6</td></tr><tr><td>PA5</td><td>32</td><td>66</td><td>PA4</td></tr><tr><td>PA3</td><td>33</td><td>67</td><td>PA2</td></tr><tr><td>PA1</td><td>34</td><td>68</td><td>PA0</td></tr></table>

Table 3-3: CN2 Pin Assignment for DAQ/DAQe/PXI-2204/2205/2206

\*Pin 42\~45 are SDI&lt;0.3&gt; for DAQ/DAQe/PXI-2204; DGND for DAQ/DAQe/PXI-2205/2206

<table><tr><td>AI32 (AIH32)</td><td>1</td><td>35</td><td>(AIL32) AI80</td></tr><tr><td>AI33 (AIH33)</td><td>2</td><td>36</td><td>(AIL33) AI81</td></tr><tr><td>AI34 (AIH34)</td><td>3</td><td>37</td><td>(AIL34) AI82</td></tr><tr><td>AI35 (AIH35)</td><td>4</td><td>38</td><td>(AIL35) AI83</td></tr><tr><td>AI36 (AIH36)</td><td>5</td><td>39</td><td>(AIL36) AI84</td></tr><tr><td>AI37 (AIH37)</td><td>6</td><td>40</td><td>(AIL37) AI85</td></tr><tr><td>AI38 (AIH38)</td><td>7</td><td>41</td><td>(AIL38) AI86</td></tr><tr><td>AI39 (AIH39)</td><td>8</td><td>42</td><td>(AIL39) AI87</td></tr><tr><td>EXTATRIG</td><td>9</td><td>43</td><td>AIGND</td></tr><tr><td>AI40 (AIH40)</td><td>10</td><td>44</td><td>(AIL40) AI88</td></tr><tr><td>AI41 (AIH41)</td><td>11</td><td>45</td><td>(AIL41) AI89</td></tr><tr><td>AI42 (AIH42)</td><td>12</td><td>46</td><td>(AIL42) AI90</td></tr><tr><td>AI43 (AIH43)</td><td>13</td><td>47</td><td>(AIL43) AI91</td></tr><tr><td>AI44 (AIH44)</td><td>14</td><td>48</td><td>(AIL44) AI92</td></tr><tr><td>AI45 (AIH45)</td><td>15</td><td>49</td><td>(AIL45) AI93</td></tr><tr><td>AI46 (AIH46)</td><td>16</td><td>50</td><td>(AIL46) AI94</td></tr><tr><td>AI47 (AIH47)</td><td>17</td><td>51</td><td>(AIL47) AI95</td></tr><tr><td>AIGND</td><td>18</td><td>52</td><td>AIGND</td></tr><tr><td>NC</td><td>19</td><td>53</td><td>NC</td></tr><tr><td>EXTDTRIG</td><td>20</td><td>54</td><td>AFI0</td></tr><tr><td>EXTTIMEBASE</td><td>21</td><td>55</td><td>DGND</td></tr><tr><td>PB7</td><td>22</td><td>56</td><td>PB6</td></tr><tr><td>PB5</td><td>23</td><td>57</td><td>PB4</td></tr><tr><td>PB3</td><td>24</td><td>58</td><td>PB2</td></tr><tr><td>PB1</td><td>25</td><td>59</td><td>PB0</td></tr><tr><td>PC7</td><td>26</td><td>60</td><td>PC6</td></tr><tr><td>PC5</td><td>27</td><td>61</td><td>PC4</td></tr><tr><td>DGND</td><td>28</td><td>62</td><td>DGND</td></tr><tr><td>PC3</td><td>29</td><td>63</td><td>PC2</td></tr><tr><td>PC1</td><td>30</td><td>64</td><td>PC0</td></tr><tr><td>PA7</td><td>31</td><td>65</td><td>PA6</td></tr><tr><td>PA5</td><td>32</td><td>66</td><td>PA4</td></tr><tr><td>PA3</td><td>33</td><td>67</td><td>PA2</td></tr><tr><td>PA1</td><td>34</td><td>68</td><td>PA0</td></tr></table>

Table 3-4: CN2 Pin Assignment for DAQ/DAQe/PXI-2208

CN1/CN2 Connector Signal Description

<table><tr><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>AIGND</td><td>—</td><td>—</td><td>Analog ground for AI. All three ground references (AIGND, AOGND, and DGND) are connected together on board.</td></tr><tr><td>AI&lt;0..63/95&gt;</td><td>AIGND</td><td>Input</td><td>For DAQ/DAQe/PXI-2204/2205/2206: Analog Input Channels 0~63. Each channel pair, AI(i=0..31) can be configured either two single-ended inputs or one differential input pair(marked as AIH&lt;0..31&gt; and AIL&lt;0..31&gt;). For DAQ/DAQe/PXI-2208: Analog Input Channels 0~95. Each channel pair, AI(i=0..37) can be configured either two single-ended inputs or one differential input pair(marked as AIH&lt;0..47&gt; and AIL&lt;0..47&gt;).</td></tr><tr><td>AISENSE</td><td>AIGND</td><td>Input</td><td>Analog Input Sense. This pin is the reference for any channels AI&lt;0..63&gt; in NRSE input configuration.</td></tr><tr><td>EXTATRIG</td><td>AIGND</td><td>Input</td><td>External AI analog trigger</td></tr><tr><td>DA0OUT</td><td>AOGND</td><td>Output</td><td>AO channel 0</td></tr><tr><td>DA1OUT</td><td>AOGND</td><td>Output</td><td>AO channel 1</td></tr><tr><td>AOEXTREF</td><td>AOGND</td><td>Input</td><td>External reference for AO channels</td></tr><tr><td>AOGND</td><td>—</td><td>—</td><td>Analog ground for AO</td></tr><tr><td>EXTWFTRIG</td><td>DGND</td><td>Input</td><td>External AO waveform trigger</td></tr><tr><td>EXTDTRIG</td><td>DGND</td><td>Input</td><td>External AI digital trigger</td></tr><tr><td>RESERVED</td><td>—</td><td>Output</td><td>Reserved. Please leave it open</td></tr></table>

Table 3-5: CN1/CN2 Signal Description

<table><tr><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>SDI&lt;0..3&gt;(for 2204 only)</td><td>DGND</td><td>Input</td><td>Synchronous digital inputs. These 4 digital inputs are sampled simultaneously with the analog signal input.</td></tr><tr><td>GPTC&lt;0,1&gt;_SRC</td><td>DGND</td><td>Input</td><td>Source of GPTC&lt;0,1&gt;</td></tr><tr><td>GPTC&lt;0,1&gt;_GATE</td><td>DGND</td><td>Input</td><td>Gate of GPTC&lt;0,1&gt;</td></tr><tr><td>GPTC&lt;0,1&gt;_OUT</td><td>DGND</td><td>Input</td><td>Output of GPTC&lt;0,1&gt;</td></tr><tr><td>GPTC&lt;0,1&gt;_UPDOWN</td><td>DGND</td><td>Input</td><td>Up/Down of GPTC&lt;0,1&gt;</td></tr><tr><td>EXTTIMEBASE</td><td>DGND</td><td>Input</td><td>External Timebase</td></tr><tr><td>DGND</td><td>—</td><td>—</td><td>Digital ground</td></tr><tr><td>PB&lt;7,0&gt;</td><td>DGND</td><td>PIO*</td><td>Programmable DIO of 8255 Port B</td></tr><tr><td>PC&lt;7,0&gt;</td><td>DGND</td><td>PIO*</td><td>Programmable DIO of 8255 Port C</td></tr><tr><td>PA&lt;7,0&gt;</td><td>DGND</td><td>PIO*</td><td>Programmable DIO of 8255 Port A</td></tr><tr><td>AFI0</td><td>DGND</td><td>Input</td><td>Auxiliary Function Input 0 (ADCONV, AD_START)</td></tr><tr><td>AFI1</td><td>DGND</td><td>Input</td><td>Auxiliary Function Input 1 (DAWR, DA_START)</td></tr></table>

Table 3-5: CN1/CN2 Signal Description

# 3.1.3 SSI Connector

<table><tr><td>SSI_TIMEBASE</td><td>1</td><td>2</td><td>DGND</td></tr><tr><td>SSI_ADCONV</td><td>3</td><td>4</td><td>DGND</td></tr><tr><td>SSI_DAWR / RESERVED*</td><td>5</td><td>6</td><td>DGND</td></tr><tr><td>SSI_SCAN_START</td><td>7</td><td>8</td><td>DGND</td></tr><tr><td>RESERVED</td><td>9</td><td>10</td><td>DGND</td></tr><tr><td>SSI_AD_TRIG</td><td>11</td><td>12</td><td>DGND</td></tr><tr><td>SSI_DA_TRIG / RESERVED*</td><td>13</td><td>14</td><td>DGND</td></tr><tr><td>RESERVED</td><td>15</td><td>16</td><td>DGND</td></tr><tr><td>RESERVED</td><td>17</td><td>18</td><td>DGND</td></tr><tr><td>RESERVED</td><td>19</td><td>20</td><td>DGND</td></tr></table>

Table 3-6: SSI Connector Pin Assignment
\*Pin 5 and 13 are reserved for DAQ/PXI-2208.

SSI Connector Signal Description on PXI J2:

<table><tr><td>Sync. Signal</td><td>PXI J2 location</td><td>PXI Trigger Bus</td></tr><tr><td>SSI_TIMEBASE</td><td>B18</td><td>PXI_TRIG4</td></tr><tr><td>SSI_ADCONV</td><td>A16</td><td>PXI_TRIG1</td></tr><tr><td>SSI_SCAN_START</td><td>A18</td><td>PXI_TRIG3</td></tr><tr><td>SSI_AD_TRIG</td><td>C18</td><td>PXI_TRIG5</td></tr><tr><td>SSI_DAWR</td><td>A17</td><td>PXI_TRIG2</td></tr><tr><td>SSI_DA_START</td><td>B16</td><td>PXI_TRIG0</td></tr><tr><td>SSI_DA_TRIG</td><td>E18</td><td>PXI_TRIG6</td></tr></table>

Table 3-7: SSI Connector Pin Assignment on PXI J2

SSI Connector Signal Description:

<table><tr><td>SSI Timing Signal</td><td>Setting</td><td>Function</td></tr><tr><td rowspan="2">SSI_TIMEBASE</td><td>Master</td><td>Send the TIMEBASE out</td></tr><tr><td>Slave</td><td>Accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.</td></tr><tr><td rowspan="2">SSI_ADCONV</td><td>Master</td><td>Send the ADCONV out</td></tr><tr><td>Slave</td><td>Accept the SSI_ADCONV to replace the internal ADCONV signal.</td></tr><tr><td rowspan="2">SSI_SCAN_START</td><td>Master</td><td>Send the SCAN_START out</td></tr><tr><td>Slave</td><td>Accept the SSI_SCAN_START to replace the internal SCAN_START signal.</td></tr><tr><td rowspan="2">SSI_AD_TRIG</td><td>Master</td><td>Send the internal AD_TRIG out</td></tr><tr><td>Slave</td><td>Accept the SSI_AD_TRIG as the digital trigger signal.</td></tr><tr><td rowspan="2">SSI_DAWR</td><td>Master</td><td>Send the DAWR out.</td></tr><tr><td>Slave</td><td>Accept the SSI_DAWR to replace the internal DAWR signal.</td></tr><tr><td rowspan="2">SSI_DA_TRIG</td><td>Master</td><td>Send the DA_TRIG out.</td></tr><tr><td>Slave</td><td>Accept the SSI_DA_TRIG as the digital trigger signal.</td></tr></table>

Table 3-8: SSI Connector Legend

# 3.2 Analog Input Signal Connection

The DAQ/DAQe/PXI-2204/2205/2206/2208 card provides up to 64 single-ended or 32 differential analog input channels. You can fill the Channel Gain Queue to get desired combination of the input signal types. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is important to understand the signal source type and how to connect the analog input signals.

# 3.2.1 Types of signal sources Floating Signal Sources

A floating signal source means it is not connected in any way to the buildings ground system. A device with an isolated output is a floating signal source, such as optical isolator outputs, transformer outputs, and thermocouples.

# Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way to the building system. That is, the signal source is already connected to a common ground point with respect to the DAQ/ DAQe/PXI-2204/2205/2206/2208 card, assuming that the computer is plugged into the same power system. Non-isolated outputs of instruments and devices that plug into the buildings power system are ground-referenced signal sources.

# 3.2.2 Input Configurations Single-Ended Connections

A single-ended connection is used when the analog input signal is referenced to a ground that can be shared with other analog input signals. There are two types of single-ended connections: RSE and NRSE. In RSE configuration, the DAQ/ DAQe/PXI-2204/2205/2206/2208 card provides the grounding point for the external analog input signals and is suitable for floating signal sources. In the NRSE configuration the board does not provide the grounding point, the external analog input signal provides its own reference grounding point and is suitable for ground-referenced signals.

Referenced Single-ended (RSE) Mode

In referenced single-ended mode, all input signals are connected to the ground provided by the DAQ/DAQe/PXI-2204/ 2205/2206/2208 card. This is suitable for connections with floating signal sources. Figure 3-1 shows an illustration. Note that when more than two floating sources are connected, these sources will be referenced to the same common ground.

![This block diagram illustrates a signal acquisition and conditioning circuit.\n\n**Labeled Blocks and Components:**\n*   **Floating Signal Source**: Located on the left, containing two AC voltage sources labeled **V1** and **V2**.\n*   **CN1 Input Multiplexer**: A central rectangular block.\n*   **Instrumentation Amplifier**: A triangular symbol on the right.\n*   **To A/D Converter**: The output destination on the far right.\n*   **n = 0, ..., 63**: Text indicating the channel range at the bottom left.\n\n**Connections:**\n*   **Floating Signal Source** connections:\n    *   The top terminal of **V1** connects to the top input pin labeled **AIn**.\n    *   The top terminal of **V2** connects to the second input pin of the multiplexer.\n    *   The bottom terminals of **V1** and **V2** are joined and connect to the bottom input pin labeled **AIGND**.\n*   **CN1 Input Multiplexer** connections:\n    *   Two additional input lines enter the block between the **V2** connection and **AIGND**, representing other channels.\n    *   A single output line exits the right side of the block.\n*   **Instrumentation Amplifier** connections:\n    *   The output of the multiplexer connects to the non-inverting input (**+**) of the amplifier.\n    *   The inverting input (**-**) of the amplifier connects to the common bottom rail (connected to **AIGND**) and a ground symbol.\n*   **Output connections**:\n    *   The output of the **Instrumentation Amplifier** connects to a wire labeled **+** leading to **To A/D Converter**.\n    *   The common bottom rail extends to the right and connects to a wire labeled **-** leading to **To A/D Converter**.](.daq-daqe-pxi-220x-50m-12258-1000-10/0a0648ddfe4eec9a03b560a9d343f56cc1f20f45b067f0e3ca3e86db37665151.jpg)

Figure 3-1: Floating Source and RSE Input Connections

Non-Referenced Single-ended (NRSE) Mode

To measure ground-referenced signal sources, which are connected to the same ground point, you can connect the signals in NRSE mode. Figure 3-2 illustrates the connection. The signals local ground reference is connected to the negative input of the instrumentation Amplifier (AISENSE pin on CN1 connector), and the common-mode ground potential between signal ground and the ground on board will be rejected by the instrumentation amplifier.

![Based on the provided image, here is an accurate and concise description of the block diagram:\n\n**Labeled Blocks and Text:**\n*   **Ground-Referenced Signal Source**\n*   **Common-mode noise & Ground potential**\n*   **n = 0, ..., 63**\n*   **V1**\n*   **V2**\n*   **Vcm**\n*   **AIn**\n*   **Input Multiplexer**\n*   **AISENSE**\n*   **Instrumentation Amplifier**\n*   **+**\n*   **-**\n*   **To A/D Converter**\n\n**Connections:**\n*   **V1** connects to the topmost input pin of the Input Multiplexer.\n*   **V2** connects to the second input pin of the Input Multiplexer.\n*   The common node of **V1** and **V2** (labeled **Vcm**) connects to the bottom input pin labeled **AISENSE**.\n*   The output of the Input Multiplexer connects to the positive (+) input of the Instrumentation Amplifier.\n*   The negative (-) input of the Instrumentation Amplifier connects to the **AISENSE** line.\n*   The output of the Instrumentation Amplifier connects to the **To A/D Converter**.](.daq-daqe-pxi-220x-50m-12258-1000-10/240cf5b1bde47d93853634ddaa9e8f48502077d43db3addc6567148b0f5cfcaf.jpg)

Figure 3-2: Ground-referenced Sources and NRSE Input Connections

# 3.2.3 Differential Input Mode

The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the com-- mon-mode noise rejection. Figure 3-3 shows the connection of ground-referenced signal sources under differential input mode.

![The diagram illustrates a signal acquisition path involving a multiplexer and an instrumentation amplifier.\n\n**Labeled Blocks and Components:**\n*   **Left Side:**\n    *   'Ground Referenced Signal Source' (AC source symbol).\n    *   'Common-mode noise & Ground potential' (DC source symbol labeled \$V_{cm}\$, connected to ground).\n*   **Middle:**\n    *   A vertical bar with connection dots, labeled 'Input Multiplexer' at the top and 'AIGND' at the bottom (connected to ground).\n    *   Two rectangular blocks positioned next to the vertical bar.\n*   **Right:**\n    *   'Instrumentation Amplifier' (triangle symbol).\n    *   Text 'To A/D Converter'.\n\n**Connections and Flow:**\n*   **Signal Generation:** The 'Ground Referenced Signal Source' connects to the '\$V_{cm}\$' source. The top wire of the signal source is labeled '\$AIxH\$' (with text '\$x = 0, ..., 31\$' above it), and the wire connecting the source to the '\$V_{cm}\$' source is labeled '\$AIxL\$'.\n*   **Multiplexer Input:** The '\$AIxH\$' line connects to the top-most dot on the 'Input Multiplexer' vertical bar. The '\$AIxL\$' line connects to a lower dot on the same bar.\n*   **Multiplexer Routing:** The vertical bar connects into the two rectangular blocks.\n    *   The **top rectangular block** receives inputs from the upper section of the bar and outputs to the non-inverting ('+') input of the amplifier.\n    *   The **bottom rectangular block** receives inputs from the lower section of the bar and outputs to the inverting ('-') input of the amplifier.\n*   **Amplification and Output:** The 'Instrumentation Amplifier' takes these differential inputs. Its output line extends to the right, labeled 'To A/D Converter'. A ground symbol is connected to the negative terminal of the amplifier's output path.](.daq-daqe-pxi-220x-50m-12258-1000-10/fb17895c3522c4d8d11aa3553e42fda1f8d313f44946957f0e816712b2ba2c1d.jpg)

Figure 3-3: Ground-referenced Source and Differential Input

# Ground-referenced Source and Differential Input

Figure 3-4 shows how to connect a floating signal source to the DAQ/DAQe/PXI-2204/2205/2206/2208 card in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. If the source impedance is less than 100ohms, you can simply connect the negative side of the signal to AIGND as well as the negative input of the Instrumentation Amplifier without any resistors. In differential input mode, less noise couples into the signal connections than in single-ended mode.

![Ground\nReferenced\nSignal\nSource\nx = 0, ..., 31\nInput Multiplexer\nInstrumentation\nAmplifier\nTo A/D\nConverter\nAlxH\nAlxL\nAIGND](.daq-daqe-pxi-220x-50m-12258-1000-10/016fc9e038bea7057886bec315d12b4f53a6e5f5be1555148c20cb98ac86c52b.jpg)

Figure 3-4: Floating Source and Differential Input

# 4 Operation Theory

The operation theory of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card functions are described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O, and general purpose counter/timer. The operation theory can help you understand how to configure and program the DAQ/DAQe/PXI-2204/2205/2206/2208 card.

# 4.1 A/D Conversion

When using an A/D converter, you must know about the properties of the signal to be measured. You may decide which channel to use and how to connect the signals to the card. In addition, users should define and control the A/D signal configurations, including channels, gains, and polarities (unipolar/bipolar).

The A/D acquisition is initiated by a trigger source and you must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched.

After the end of an A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data can now be transferred into the system memory for further processing.

# 4.1.1 DAQ/DAQe/PXI-2204/2208 AI Data Format Synchronous Digital Inputs (DAQ/DAQe/PXI-2204 only)

When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI&lt;1..0&gt;\_X per channel from J5 will be latched into the 16-bit register and data FIFO as shown in Figure 4-1 and Figure 4-2. Therefore, you can simultaneously sample one analog signal with four digital signals. The data format of every acquired 16-bit data is as follows:

```txt
D11, D10, D9 ..... D1, D0, b3, b2, b1, b0
Where
D11, D10, D9 ..... D1, D0: 2's complement A/D
12-bit data
b3, b2, b1, b0: Synchronous Digital Inputs
SDI&lt;3..0&gt;
```

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **ADC**: Contains labels for inputs/outputs including 'Ain', 'nADBUSY', and 'nADCONV'.\n*   **16-bit Register**: Contains a label for an input 'CLK'.\n*   **AD Data FIFO**.\n\n**Connections and Signals:**\n*   **SDI(3..0)**: A 4-bit bus labeled 'SDI(3..0) from CN2' connects to the **16-bit Register**.\n*   **From Instrumentation Amplifier**: Connects to the 'Ain' input of the **ADC**.\n*   **AD_conversion**: Connects to the 'nADCONV' input of the **ADC**.\n*   **AD(11..0)**: A 12-bit bus connecting the output of the **ADC** to the **16-bit Register**.\n*   **nADBUSY**: A signal line connecting the **ADC** to the **16-bit Register**.\n*   **CLK**: An input signal connecting to the **16-bit Register**.\n*   **Data Output**: A thick arrow representing a 16-bit bus connects the **16-bit Register** to the **AD Data FIFO**.](.daq-daqe-pxi-220x-50m-12258-1000-10/d2ad6800b8ebb9b6bfe1e8f6e6fdc8fad4b878b09d60a99cb5040ff7518ff8f8.jpg)

Figure 4-1: Synchronous Digital Inputs Block Diagram

![AD_conversion\nnADBUSY\n16 bits data(including AD(11..0) and SDI(3..0)\nlatched into AD Data FIFO](.daq-daqe-pxi-220x-50m-12258-1000-10/35e3290be502e093a8211f05ba7c0e332d0144572ba9c1f4d65c5d416ed2ece0.jpg)

Figure 4-2: Synchronous Digital Inputs Timing

![A graphic icon featuring a white document with faint horizontal lines and a large red checkmark overlaid on it. Below the icon is the text 'NOTE:' in black capital letters.](.daq-daqe-pxi-220x-50m-12258-1000-10/df1ab2bce56050888483fc493852236bbcf2491f8de25e1e0df87746c33426ee.jpg)

Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D\_conversion signal), while $\mathsf { S D } | { &lt; } 3 . . 0 &gt;$ are sampled right after an A/D conversion completes (rising edge of nADBUSY signal). Precisely SDI&lt;3..0&gt; are sampled with 280ns lag to the analog signal.

Table 4-1and Table 4-2 illustrate the ideal transfer characteristics of various input ranges of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card.

<table><tr><td>Description</td><td colspan="4">Bipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>—</td></tr><tr><td>Least significant bit</td><td>4.88mV</td><td>2.44mV</td><td>1.22mV</td><td>0.61mV</td><td>—</td></tr><tr><td>FSR-1LSB</td><td>9.9951V</td><td>4.9976V</td><td>2.4988V</td><td>1.2494V</td><td>7FFX</td></tr><tr><td>Midscale +1LSB</td><td>4.88mV</td><td>2.44mV</td><td>1.22mV</td><td>0.61mV</td><td>001X</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>000X</td></tr><tr><td>Midscale -1LSB</td><td>-4.88mV</td><td>-2.44mV</td><td>-1.22mV</td><td>-0.61mV</td><td>FFFX</td></tr><tr><td>-FSR</td><td>-10V</td><td>-5V</td><td>-2.5V</td><td>-1.25V</td><td>800X</td></tr></table>

Table 4-1: Bipolar Analog Input Range and Output Digital Code on DAQ/ DAQe/PXI-2204/2208

Note that the last 4 digital codes are SDI&lt;3..0&gt; and is supported only on DAQ/DAQe/PXI-2204)

<table><tr><td>Description</td><td colspan="3">Unipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>0V to 10V</td><td>0 to +5V</td><td>0 to +2.5V</td><td>—</td></tr><tr><td>Least significant bit</td><td>2.44mV</td><td>1.22mV</td><td>0.61mV</td><td>—</td></tr><tr><td>FSR-1LSB</td><td>9.9976V</td><td>4.9988V</td><td>2.9994V</td><td>7FFX</td></tr><tr><td>Midscale +1LSB</td><td>5.00244V</td><td>2.50122V</td><td>1.25061V</td><td>001X</td></tr><tr><td>Midscale</td><td>5V</td><td>2.5V</td><td>1.25V</td><td>000X</td></tr><tr><td>Midscale –1LSB</td><td>4.9976V</td><td>2.4988V</td><td>1.2494V</td><td>FFFX</td></tr><tr><td>-FSR</td><td>0V</td><td>0V</td><td>0V</td><td>800X</td></tr></table>

Table 4-2: Unipolar Analog Input Range and Output Digital Code on DAQ/ DAQe/PXI-2204/2208
Note that the last 4 digital codes are SDI&lt;3..0&gt; and is supported only on DAQ/DAQe/PXI-2204.

# 4.1.2 DAQ/DAQe/PXI-2005/2006/2016 AI Data Format

The data format of the acquired 16-bit A/D data is 2's Complement coding. Table 4-3 and Table 4-4 illustrate the valid input ranges and the ideal transfer characteristics.

<table><tr><td>Description</td><td colspan="4">Bipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>—</td></tr><tr><td>Least significant bit</td><td>305.2 μV</td><td>152.6 μV</td><td>76.3 μV</td><td>38.15 μV</td><td>—</td></tr><tr><td>FSR-1LSB</td><td>9.999695V</td><td>4.999847V</td><td>2.499924V</td><td>1.249962V</td><td>7FFF</td></tr><tr><td>Midscale +1LSB</td><td>305.2 μV</td><td>152.6 μV</td><td>76.3 μV</td><td>38.15 μV</td><td>0001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0000</td></tr><tr><td>Midscale -1LSB</td><td>-305.2 μV</td><td>-152.6 μV</td><td>-76.3 μV</td><td>-38.15 μV</td><td>FFFF</td></tr><tr><td>-FSR</td><td>-10V</td><td>-5V</td><td>-2.5V</td><td>-1.25V</td><td>8000</td></tr></table>

Table 4-3: Bipolar Analog Input Range and Output Digital Code for DAQ/DAQe/ PXI-2205/2206

<table><tr><td>Description</td><td colspan="4">Unipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>0V to 10V</td><td>0 to +5V</td><td>0 to +2.5V</td><td>0 to +1.25V</td><td>—</td></tr><tr><td>Least significant bit</td><td>152.6 μV</td><td>76.3 μV</td><td>38.15 μV</td><td>19.07 μV</td><td>—</td></tr><tr><td>FSR-1LSB</td><td>9.999847V</td><td>4.999924V</td><td>2.499962V</td><td>1.249981V</td><td>7FFF</td></tr><tr><td>Midscale +1LSB</td><td>5.000153V</td><td>2.500076V</td><td>1.250038V</td><td>0.625019V</td><td>0001</td></tr><tr><td>Midscale</td><td>5V</td><td>2.5V</td><td>1.25V</td><td>0.625V</td><td>0000</td></tr><tr><td>Midscale -1LSB</td><td>4.999847V</td><td>2.499924V</td><td>1.249962V</td><td>0.624981V</td><td>FFFF</td></tr></table>

Table 4-4: Unipolar Analog Input Range and Output Digital Code for DAQ/DAQe/ PXI-2205/2206

# 4.1.3 Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available.

This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled by the software. However, it is difficult to control the A/D conversion rate.

# Specifying Channel, Gain, and Input Configurations in the Channel Gain Queue

In Software Polling and Programmable Scan Acquisition mode, the channel, gain, polarity, and input configuration (RSE, NRSE, or DIFF) can be specified in the Channel Gain Queue. You can fill the channel number in the Channel Gain Queue in any order. The channel order of acquisition will be the same as the order you set in the Channel Gain Queue. Therefore, you can acquire data with user-defined channel orders and with different settings on each channel.

When the specified channels have been sampled from the first data to the last data in the Channel Gain Queue, the settings in Channel Gain Queue are maintained. You do not need to reconfigure the Channel Gain Queue if you want to keep on sampling data in the same order. The maximum number of entries you can set in the Channel Gain Queue is 512.

# Example:

First you can set entries in Channel Gain Queue:

 Ch3 with bipolar ±10V, RSE connection
 Ch1 with bipolar ±2.5V, DIFF connection
 Ch2 with unipolar 5V, NRSE connection
 Ch1 with bipolar ±2.5V, DIFF connection

If you read 10 data by software polling method, then the acquisition sequence of channels is 3, 1, 2, 1, 3, 1, 2, 1, 3, 1.

# 4.1.4 Programmable Scan Acquisition Mode Scan Timing and Procedure

It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least four counters which need to be specified:

 SI\_counter (24-bit): Specify the Scan Interval = SI\_counter / Timebase
 SI2\_counter (16-bit): Specify the data Sampling Interval = SI2\_counter/Timebase
 PSC\_counter (24-bit): Specify Post Scan Counts after a trigger event
 NumChan\_counter (9-bit): Specify the number of samples per scan

The acquisition timing and the meanings of the 2 counters are illustrated in Figure 4-3.

# TIMEBASE Clock Source

In scan acquisition mode, all the A/D conversions start on the output of counters, which use TIMEBASE as the clock source. By software you can specify the TIMEBASE to be either an internal clock source (onboard 40 MHz clock) or an external clock input (EXTTIMEBASE) on CN2 connector. The external TIMEBASE is useful when you want to acquire data at rates not available with the internal A/D sample clock. The external clock source should generate TTL-compatible continuous clocks and with a maximum frequency of 40 MHz while the minimum should be 1 MHz. Refer to section 4.6 for information on user-controllable timing signals.

![| Scan | Channel Sequence | Annotation |\n|------|------------------|----------|\n| 1    | Ch2              | Sampling Interval t= SI2_COUNTER/TimeBase |\n| 2    | Ch3              | Sampling Interval t= SI2_COUNTER/TimeBase |\n| 3    | Ch0              | Sampling Interval t= SI2_COUNTER/TimeBase |\n| 4    | Ch1              | Sampling Interval t= SI2_COUNTER/TimeBase |\n| 5    | Ch0              | Sampling Interval t= SI2_COUNTER/TimeBase |\n| 6    | Ch2              | Channel Sequence 1: PSC_Counter=3, NumChan_Counter=4 |\n| 7    | Ch3              | Channel Sequence 1: PSC_Counter=3, NumChan_Counter=4 |\n| 8    | Ch0              | Channel Sequence 1: PSC_Counter=3, NumChan_Counter=4 |\n| 9    | Ch2              | Channel Sequence 2: PSC_Counter=3, NumChan_Counter=4 |\n| 10   | Ch3              | Channel Sequence 2: PSC_Counter=3, NumChan_Counter=4 |\n| 11   | Ch0              | Channel Sequence 2: PSC_Counter=3, NumChan_Counter=4 |\n| 12   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 13   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 14   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 15   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 16   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 17   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 18   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 19   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 20   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 21   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 22   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 23   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 24   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 25   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 26   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 27   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 28   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 29   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 30   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 31   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 32   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 33   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 34   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 35   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 36   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 37   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 38   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 39   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 40   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 41   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 42   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 43   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 44   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 45   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 46   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 47   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 48   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 49   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 50   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 51   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 52   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 53   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 54   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 55   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 56   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 57   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 58   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 59   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 60   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 61   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 62   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 63   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 64   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 65   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 66   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 67   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 68   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 69   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 70   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 71   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 72   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 73   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 74   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 75   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 76   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 77   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 78   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 79   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 80   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 81   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 82   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 83   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 84   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 85   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 86   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 87   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 88   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 89   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 90   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 91   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 92   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 93   | Ch2              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 94   | Ch3              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| 95   | Ch0              | Channel Sequence 3: PSC_Counter=3, NumChan_Counter=4 |\n| Note: The chart displays the scan intervals for each scan type. The scan intervals are labeled as 'SNHOUT' and 'CN2'. The values in the table represent the sample count of the scan intervals. The labels above the scan intervals are 'Sampling Interval t': SI2_COUNTER/TimeBase; SI_COUNTER/TimeBase. The values below the scan intervals are 'Scan Interval T': SI_PCounter/TimeBase. The labels above the scan intervals are 'SNHOUT' and 'CN2'.](.daq-daqe-pxi-220x-50m-12258-1000-10/a0b42039afd6b9a0924ec15f817150d0744ba86a2027ae0415dbf8e56e3a3e20.jpg)

Figure 4-3: Scan Timing

There are four trigger modes to start the scan acquisition. Refer to section 4.1 for details. The data transfer mode is discussed in the following section.

![The image displays an icon of a white document with a folded top-right corner and faint horizontal gray lines, overlaid with a large, bold red checkmark.](.daq-daqe-pxi-220x-50m-12258-1000-10/8889e736afccf6f9ea26dd31ff19a6705fb729cec2cbdc58260f978c6822f5a1.jpg)
NOTE:

The maximum A/D sampling rate is 3 MHz for DAQ/DAQe/PXI-2204/2208, 500 kHz for DAQ/DAQe/PXI-2205, and 250 kHz for DAQ/DAQe/PXI-2206. Therefore, the minimum setting of SI2\_counter is 14 for DAQ/DAQe/PXI-2204/2208, 80 for DAQ/ DAQe/PXI-2205, and 160 for DAQ/DAQe/PXI-2206 while using the internal TIMEBASE.

The SI\_counter is a 24-bit counter and the SI2\_counter is a 16- bit counter. The maximum scan interval using the internal Timebase = 224/40 Ms = 0.419 s, and the maximum sampling interval between two channels using the internal Timebase = 216/40 Ms = 1.638 ms.

The scan interval may not be smaller than the product of the data sampling interval and the NumChan\_counter value. The relationship can be represented as: SI\_counter>=SI2\_counter \* NumChan\_counter.

# Scan with SSH

You can send the SSHOUT signal on CN2 to external S&H circuits to sample and hold all signals if you want to simultaneously sample all channels in a scan, as illustrated in Figure 4-3.

![The image displays a white document icon with a folded top-right corner. Faint blue horizontal lines run across the paper, resembling lined notebook paper or a form. A large, bold red checkmark is superimposed diagonally over the center of the document.](.daq-daqe-pxi-220x-50m-12258-1000-10/2c608090183de2b70c2edbe4081d40214695bb59d7e6025fff79c991dbc6f5dc.jpg)
NOTE:

The DAQ/DAQe/PXI-2208 does not support this function.

The SSHOUT signal is sent to external S&H circuits to hold the analog signal. You must implement external S&H circuits on their own to carry out the S&H function. There are no onboard S&H circuits.

# 4.1.5 Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue

Like software polling acquisition mode, the channel, gain, and input configurations can be specified in the Channel Gain Queue under the scan acquisition mode. Note that in scan acquisition mode, the number of entries in the Channel Gain Queue is normally equivalent to the value of NumChan\_counter (that is, the number of samples per scan).

# Example: Set

 SI2\_counter = 160
 SI\_counter = 640
 PSC\_counter = 3
 NumChan\_counter = 4
 Timebase = Internal clock source
 Channel entries in the Channel Gain Queue: ch1, ch2, ch0, ch2

# Then

 Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2
 Sampling interval: 160/40 Ms = 4 µs
 Scan interval: 640/40 Ms = 16 µs
 Equivalent sampling rate of ch0, ch1: 62.5 kHz
 Equivalent sampling rate of ch2: 125 kHz

# 4.1.6 Trigger Modes

The DAQ/DAQe/PXI-2204/2205/2206/2208 card provides four trigger sources (internal software trigger, external analog trigger, and digital trigger sources, and SSI trigger signals). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source. For example, a rising edge on the external digital trigger input. Refer to section 4.6 for more information on SSI signals.

There are four trigger modes (pre-trigger, post-trigger, middle-trigger, and delay-trigger) working with the four trigger sources to initiate different scan data acquisition timing when a trigger event occurs. They are described in the following sections. For information on trigger sources, refer to section 4.5.

# Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to collect data before a trigger event. The A/D starts to sample when you execute the specified function calls to begin the pretrigger operation, and it stops when the trigger event occurs. Users must program the value M in M\_counter (16 bits) to specify the amount of the stored scans before the trigger event. If an external trigger occurs, the program only stores the last M scans of data converted before the trigger event, as illustrated in Figure 4-4, where M\_counter = M =3, PSC\_counter = 0. The post scan count is 0 because there is no sampling after the trigger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels \* M\_counter.

![(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nAquired data\nAcquired & stored data\n(M scans)](.daq-daqe-pxi-220x-50m-12258-1000-10/dfe9aec57e34ffcf369ded9eefe0c534e2dc11ba8a0f0d566c2d3f213fe8e1b9.jpg)

Figure 4-4: Pre-trigger (Trigger occurs after M scans)

Note that if a trigger event occurs when a scan is in progress, the data acquisition won't stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan\_counter), no matter when a trigger signal occurs, as illustrated in Figure 16, where M\_counter = M =3, NumChan\_counter = 4, PSC\_counter = 0.

![(M_counter = M = 3, NumChan_counter =4, PSC_counter=0)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nTrigger occurs\nData acquisition\nwon't stop until a\nscan completes\nAquired data\nAcquired & stored data\n(M scans)](.daq-daqe-pxi-220x-50m-12258-1000-10/57131b0430bc942b327f074b1dad346547c18b5440f5b8254cfa30bd76061150.jpg)

Figure 4-5: Pre-trigger (Trigger with scan in progress)

When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the originally specified amount M\_counter, as illustrated in Figure 4-6. This situation can be avoided by setting M\_enable. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7. However, if M\_enable is set to 0, the trigger signal will be accepted any time, as shown in Figure 4-6. Note that the total amount of stored data will always be equal to the number in the M\_counter because data acquisition does not stop until a scan is completed.

![| Operation Start | Trigger | Scan_start | AD_conversion | Scan_in_progress (SSHOUT)(pin8 on CN2) | Acquisition_in_progress |\n| --------------- | ------- | ---------- | ------------- | -------------------------------------- | ----------------------- |\n| Operation start | -       | -          | -             | -                                      | -                       |](.daq-daqe-pxi-220x-50m-12258-1000-10/9d0b45035f7b2395e7e80cff060ef994bfd627625de18ebc36226adc989c403b.jpg)

Figure 4-6: Pre-trigger with M\_enable=0 (Trigger occurs before M scans)

![(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)\nThe first M scans\nTrigger signals which occur in the shadow region(the first M scans) will be ignored\nTrigger\nScan_start\nAD_conversion\nScan_in_progress (SSHOUT)(pin2 on CN2)\nAcquisition_in_progress\nAquired data\nAcquired & stored data (M scans)\nOperation start](.daq-daqe-pxi-220x-50m-12258-1000-10/e397a9c294a9cf2efc8e21de737f3df42646bfe6ea785cd3fb8101c8abb55e91.jpg)

Figure 4-7: Pre-trigger with M\_enable=1

![The image shows an icon of a white document with a folded top-right corner and several horizontal lines running down the page. A large, red checkmark is superimposed over the document, spanning from the bottom left to the top right.](.daq-daqe-pxi-220x-50m-12258-1000-10/ba53dd26b743e140351ad5bd3676fa9f5a3eab5c79246712909271262dae6186.jpg)
NOTE:

The PSC\_counter is set to 0 in pre-trigger acquisition mode.

# Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M\_counter, while the number of scans (N) after the trigger is specified in PSC\_counter.

Like pre-trigger mode, the number of stored data could be less than the specified amount of data (M+N), if an external trigger occurs before M scans of data are converted. The M\_enable bit in middle-trigger mode takes the same effect as in pre-trigger mode. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user with (M+N) scans of data under middle-trigger mode. However, if M\_enable is set to 0, the trigger signal will be accepted at any time. Figure 4-8 shows the acquisition timing with M\_enable=1.

![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks and Text:**\n*   **Header:** `(M_Counter=M=3, P SC_Counter=N=1)`\n*   **Signal Labels (Left):** `Trigger`, `Scan_start`, `ADCONV`, `Acquisition_in_progress`, `Post Scan Count`\n*   **Annotations & Timers:**\n    *   `The first M scans`\n    *   `Trigger signals which occur in the shadow region the first M scans) will be ignored`\n    *   `1` (under Post Scan Count)\n    *   `0` (under Post Scan Count)\n    *   `Acquired data`\n    *   `M scans before trigger`\n    *   `N scans after trigger`\n    *   `Operation start`\n    *   `Acquired & stored data (M+N scans)`\n\n**Connections and Flow:**\n*   **Trigger Signal:** A hatched region covers the initial pulses, labeled `The first M scans`. An arrow points to a specific pulse within this region with the text: `Trigger signals which occur in the shadow region the first M scans) will be ignored`.\n*   **Timing Correlations:** Dashed vertical lines connect events across the signal rows.\n    *   One set of dashed lines connects the first valid `Scan_start` pulse (after the hatched region) to the rising edge of `Acquisition_in_progress`.\n    *   Another set of dashed lines connects the end of the `Acquisition_in_progress` signal to the point where `Post Scan Count` drops from `1` to `0`.\n    *   Dashed lines mark the boundaries for `Acquired data`, `M scans before trigger`, `N scans after trigger`, and the total `Acquired & stored data (M+N scans)`.\n*   **Logic:** The diagram illustrates that acquisition starts (`Acquisition_in_progress` goes high) after the first valid trigger pulse. It continues through subsequent scans and stops when the `Post Scan Count` reaches `0`.](.daq-daqe-pxi-220x-50m-12258-1000-10/485db9a06b5788e42a6e65b83b31df01be370b04bad7fd9ce4246502785e2153.jpg)

Figure 4-8: Middle-Trigger with M\_enable = 1

If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9.

![(M Counter=M=2, PSC Counter=N=2)\nTrigger occurs when a scan is in progress\nTrigger\nScan_sla1\nADCO N V\nAcquisition_In_progress\nPost Scan Count 2\n1 0\nAcquired data\nM scans before\ntrigger\nN scans at and\nafter trigger\nOperation start\nAcquired & stored data\n(M+N scans)](.daq-daqe-pxi-220x-50m-12258-1000-10/ea9ce5962c4289c0d3244efe1d894d6089168335dadea1f4557c6598f2d81db3.jpg)

Figure 4-9: Middle-Trigger (Trigger occurs when a scan is in progress)

# Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC\_counter, as illustrated in Figure 4- 10. The total acquired data length = NumChan\_counter \* PSC\_counter.

![(NumChan_Counter=4, PSC_Counter=3)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(3 scans)](.daq-daqe-pxi-220x-50m-12258-1000-10/56324611fe4ace9c07a3ae1939fb64dbcc9e084bcd8c4bfda920c1449b16600a.jpg)

Figure 4-10: Post-trigger

# Delay Trigger Acquisition

Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay\_counter (16-bit). The counter counts down on the rising edge of the Delay\_counter clock source after the trigger condition is met. The clock source can be software-programmed either by the TIMEBASE clock (40 MHz) or A/D sampling clock (TIMEBASE / SI2\_counter). When the count reaches 0, the counter stops and the card starts to acquire data. The total acquired data length = NumChan\_counter \* PSC\_counter.

![| Operation Start | Trigger | Scan_start | AD_conversion | Scan_in_progress (SSHOUT)(pin8 on CN2) | Acquisition_in_progress |\n| --------------- | ------- | ---------- | ------------- | ------------------------------------- | ----------------------- |\n| Operation start | -       | -          | -             | -                                     | -                       |\n| Delay until Delay_Counter reaches 0   | -       | -          | -             | -                                     | -                       |\n| Acquired & stored data (3 scans)    | -       | -          | -             | -                                     | -                       |](.daq-daqe-pxi-220x-50m-12258-1000-10/b4294034fa7566f9c9234ede6f7c666e4c3871c9c927d3811695bd3dc8f50675.jpg)

Figure 4-11: Delay trigger

![The image features a white document icon with a folded top-left corner and faint horizontal lines indicating text. A large, bold red checkmark is superimposed diagonally over the center of the document.](.daq-daqe-pxi-220x-50m-12258-1000-10/136d51b489c3c2847943ff97fffab530f2e113e4a604e2f75aa996f8adfbd5f9.jpg)
NOTE:

When the Delay\_counter clock source is set to TIMEBASE, the maximum delay time is 216/40 Ms or 1.638 ms. When the source is set to A/D sampling clock, the maximum delay time may be higher than 216 \* SI2\_counter / 40M.

Use post-trigger or delay-trigger acquisition with re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC\_counter, and users could program Retrig\_no to specify the re-trigger numbers. Figure 4-12 illustrates an example. In this example, two scans of data is acquired after the first trigger signal, then the card waits for the re-trigger signal (re-trigger signals which occur before the first two scans is completed will be ignored). When the re-trigger signal occurs, two more scans are performed. The process repeats until specified amount of re-trigger signals are detected. The total acquired data length = NumChan\_counter \* PSC\_counter \* Re-trig\_no.

![(NumChan Counter=4, PSC Counter=2, retrig_no=3)\nTrigger\nScan_start\nAD_conversion\nScan_in_progress\n(SSHOUT)(pin8 on CN2)\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(6 scans)](.daq-daqe-pxi-220x-50m-12258-1000-10/c43e80975237171233f37bc9a8b6212e1aa9cc2203b02226b191a4a0732ba4dd.jpg)

Figure 4-12: Post trigger with Re-trigger

# 4.1.7 Bus-mastering DMA Data Transfer

In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI busmastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on a PCI bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a userdefined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA.

The DMA transfer mode is very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a high-level programming library for high speed DMA data acquisition, you convert through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA.

The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list.

In a multi-user or multitasking OS, like Windows or Linux, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the non-continuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-13 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address cycle support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs.

![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Blocks:**\n*   **Bottom:** A block labeled 'Local Memory (FIFO)'.\n*   **Middle:** A wide block labeled 'PCI Bus'.\n*   **Top Row (Left):** A block containing the text:\n    *   'First PCI Address'\n    *   'First Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n*   **Top Row (Center):** A block containing the text:\n    *   'PCI Address'\n    *   'Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n*   **Top Row (Right):** A block containing the text:\n    *   'PCI Address'\n    *   'Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n\n**Connections:**\n*   An arrow points upward from 'Local Memory (FIFO)' to 'PCI Bus'.\n*   An arrow points upward from 'PCI Bus' to the center block of the top row.\n*   An arrow points from the left block of the top row to the center block of the top row.\n*   An arrow points from the center block of the top row to the right block of the top row.](.daq-daqe-pxi-220x-50m-12258-1000-10/c0c0808dc7f544fd0b238e83bad28c48854b1932ac9ee73e7977b67a792cd915.jpg)

Figure 4-13: Linked List of PCI Address DMA Descriptors

In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multibuffered mode DMA.

# 4.2 D/A Conversion

NOTEThe DAQ/DAQe/PXI-2208 card does not support this function.

There are two 12-bit D/A output channels available in the DAQ/ DAQe/PXI-2204/2205/2206 card. When using D/A converters, you should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. You could also set the output polarity to unipolar or bipolar.

The reference selection control lets you utilize in full the multiplying characteristics of the D/A converters. Internal 10V reference and external reference inputs are available in the DAQ/DAQe/PXI-2204/2205/2206 card. The range of the D/A output is directly related to the reference. The digital codes that are updated to the D/A converters will multiply with the reference to generate the analog output. While using internal 10V reference, the full range would be –10V to +9.9951V in the bipolar output mode, and 0V to 9.9976V in the unipolar output mode. While using an external reference, you can reach different output ranges by connecting different references. For example, if connecting a DC –5V with the external reference, then you can get a full range from –4.9976V to +5V in the bipolar output with inverting characteristics due to the negative reference voltage. You could also have an amplitude modulated (AM) output by feeding a sinusoidal signal into the reference input. The range of the external reference should be within ±10V. Table 4-5 and Table 4-6 illustrates the relationship between digital code and output voltages with Vref=10V and if internal reference is selected.

<table><tr><td>Digital Code</td><td>Analog Output</td></tr><tr><td>111111111111</td><td>Vref * (2047/2048)</td></tr><tr><td>100000000001</td><td>Vref * (1/2048)</td></tr><tr><td>100000000000</td><td>0V</td></tr><tr><td>01111111111</td><td>-Vref * (1/2048)</td></tr><tr><td>000000000000</td><td>-Vref</td></tr></table>

Table 4-5: Bipolar Output Code Table

<table><tr><td>Digital Code</td><td>Analog Output</td></tr><tr><td>11111111111</td><td>Vref * (4095/4096)</td></tr><tr><td>100000000000</td><td>Vref * (2048/4096)</td></tr><tr><td>000000000001</td><td>Vref * (1/4096)</td></tr><tr><td>000000000000</td><td>0V</td></tr></table>

Table 4-6: Unipolar Output Code Table

The D/A conversion is initiated by a trigger source. You must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from the computer’s main memory to a buffering Data FIFO.

Two D/A conversion modes are available: Software Update and Timed Waveform Generation. These are described below, including the timing, trigger source control, trigger modes, and data transfer methods. Either mode may be applied to D/A channels independently. You can simultaneously software update DA CH0 while generating timed waveforms on CH1.

# 4.2.1 Software Update

This is the easiest way to generate D/A output. To do this:

1. Specify the D/A output channels.
2. Set output polarity (unipolar or bipolar) and reference source (internal 10V or external AOEXTREF).
3. Update the digital values into D/A data registers through a software output command.

# 4.2.2 Timed Waveform Generation

This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters.

The D/A output timing is provided through a combination of counters in the FPGA on board. There are a total of five counters to be specified. These counters include:

 UI\_counter (24 bits): specify the DA update interval is equal to CHUI\_counter/TIMEBASE
 UC\_counter (24 bits): specify the total update counts in a single waveform
 IC\_counter (24 bits): specify the iteration counts of waveform
 DA\_DLY1\_counter (16 bits): specify the delay from the trigger to the first update start
 DA\_DLY2\_counter (16 bits): specify the delay between two consecutive waveform generations

Figure 4-14 shows a typical D/A timing diagram assuming the data in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on each rising edge of DAWR. The meaning of the counters enumerated above are discussed in the following sections.

![| Signal Event | Description |\n| ------------ | ----------- |\n| Trigger      | High pulse width |\n| DAWR         | Delay until DLY1 Counter reaches 0 |\n| WFG_in_progress | Delay until DLY1 Counter reaches 0 |\n| Output Waveform | DA update_interval t= UI Counter/Timebase |\n| Operation start | -4 to +4 pulse width |\n| IC Counter = 3 | Single waveform |\n| UC Counter = 4 | Delay until DLY2 Counter reaches 0 |\n| DA Update Interval | DA update_interval t= UI Counter/Timebase |\n| IC Counter = 3 | Single waveform |](.daq-daqe-pxi-220x-50m-12258-1000-10/e7557e259e2c8f54d05cef078d79940337b1a4ff19e9e0910babe66b9fe4c7ee.jpg)

Figure 4-14: Typical D/A Timing of Waveform Generation

![A white icon of a document featuring a folded top-right corner, horizontal lines, and a large red checkmark superimposed over it.](.daq-daqe-pxi-220x-50m-12258-1000-10/dd07ddb73c7f2113acfd126238d464867dd0292d5dc64f2428da09b880bb723a.jpg)
NOTE:

The maximum D/A update rate is 1 MHz. Therefore, the minimum setting of the UI\_counter is 40 while using an internal TIMEBASE (40 MHz).

# 4.2.3 Trigger ModesPost-Trigger Generation

Use post-trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1\_Counter is ignored and not be specified. Figure 4-15 shows a single waveform generated right after a trigger signal is detected and assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. The trigger signal could come from a software command, an analog trigger or a digital trigger. Refer to section 4.5 for detailed information.

![| Operation start | Trigger | DAWR | WFG_in_progress | Output Waveform |\n| --------------- | ------- | ---- | --------------- | ---------------- |\n| Value           | 2       | 4    | 6               | 3                |\n| Value           | 0       | 3    | 4               | -2               |\n| Value           | -4      | -2   | 0               | 0                |](.daq-daqe-pxi-220x-50m-12258-1000-10/6b17695785c9f02fd83ae70c48b8ef62163f1a606d6f25eeb5eb66a3911810bd.jpg)

Figure 4-15: Post Trigger Waveform Generation

# Delay-Trigger Generation

Use delay trigger when you want to delay the waveform generation after a trigger event. In Table 4-16, DA\_DLY1\_counter determines the delay time from the trigger signal to the start of the waveform generation, assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. DLY1\_counter counts down on the rising edge of its clock source after the trigger condition is met. When the count reaches 0, the counter stops and the DAQ/DAQe/PXI-2204/2205/2206/2208 card starts the waveform generation. This DLY1\_Counter is 16-bit wide and you can set the delay time in units of TIMEBASE (delay time = DLY1\_Counter/TIMEBASE) or in units of update period (delay time = DLY1\_Counter \* UI\_counter/TIMEBASE), so the delay time can reach a wider range.

![8 update counts, 1 iterations\nTrigger\n(UC Counter=8, IC Counter=1)\nDAWR\nWFG_in_progress\nOutput Waveform\nOperation start\nDelay until\nDLY1 counter\nreaches 0](.daq-daqe-pxi-220x-50m-12258-1000-10/9eaf196630c1e95a91e6ec1816e57936d645b694a369314f37b2c2131fce3b5b.jpg)

Figure 4-16: Delay Trigger Waveform Generation

# Post-Trigger or Delay-Trigger with Re-trigger

Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation assuming the data in the data buffer are 2V, 4V, 2V, and 0V. However, the trigger event would be ignored while the waveform generation is ongoing.

![4 update counts, 2 iterations\n(UC_Co#nter=4, IC_Co#nter=2)    Ignored\nTrigger\nDAWR\nWFG_in_progress\nOutput Wave tom\nOper atb start\nCall software stop\nfunction to terminate\nretrigger rmode\nwave tom generation](.daq-daqe-pxi-220x-50m-12258-1000-10/f0814200a8a295fd2c975a62a08f82f544650fb1329bfc35c1867cc1e2daa71c.jpg)

Figure 4-17: Re-triggered Waveform Generation with Post-Trigger (DLY2\_Counter=0)

# Iterative Waveform Generation

Set IC\_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number and the iterations may be finite (Figure 4-18) or infinite (Figure 4-19). Take note that in infinite mode the waveform generation does not stop until software stop function is executed and IC\_Counter is still valid when stop mode III is selected. Both figures assume that the data in the data buffer are 2V, 4V, 2V, and 0V.

An onboard data FIFO is used to buffer the digital data for DA output. If the data size of a single waveform you specified (That is, Update Counts in UC\_counter) is less than the FIFO size, after initially transferring the data from the host PC memory to the FIFO on board, the data in the FIFO will be automatically re-transmitted whenever a single waveform is completed. Therefore, it does not occupy the PCI bandwidth when repetitive waveforms are performed. However, if the size of a single waveform were larger than that of the FIFO, it needs to be intermittently loaded from the host PC’s memory via DMA, when a repetitive waveforms is performed thus PCI bandwidth would be occupied.

The data FIFO size on the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card is 1024 (words) when one DA channel is enabled, or 512 (words) when both DA channels are enabled.

![| Signal          | Event Description                     |\n|-----------------|----------------------------------------|\n| Trigger         | 4 update counts, 3 iterations (UC_Counter=4, IC_Counter=3) |\n| DAWR            | (Waveform pulses)                       |\n| WFG_in_progress | (Waveform pulses)                       |\n| Output Waveform | (Waveform pulses)                       |\n| Operation start | (Line segment labeled 'n')                 |](.daq-daqe-pxi-220x-50m-12258-1000-10/0bdfd0d770a3ff5d065230bfb63bcf86ab8e4ed50ec059814dfc178274d3e170.jpg)

Figure 4-18: Finite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0)

![4 update counts, infinite iterations\n(UC Counter=4, IC Counter=4)\nTrigger\nDAWR\nWFG_h_progress\nOutput Waveform\n? 1\nn\nOperatb start\nwave form generation\nwon't stop until software\nstop function is\nexecited](.daq-daqe-pxi-220x-50m-12258-1000-10/fee88a8db64213934a57592e096945d6e5ba079c57f86f25d44b394049c8f303.jpg)

Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger (DLY2\_Counter = 0)

# Delay2 in Iterative Waveform Generation

To stretch out the flexibility of the D/A waveform generation, we add a DLY2\_Counter to separate two consecutive waveforms in iterative waveform generation. The time between two waveforms is assigned by setting the value of the DLY2\_Counter. The DLY2\_Counter starts to count down after a waveform generation finishes and the next waveform generation starts right after it counts down to zero, as shown in Figure 4-20. This DLY2\_Counter is 16-bit wide and you may set the delay time in unit of TIMEBASE (delay time = DLY2\_Counter/TIMEBASE) or in unit of update period (delay time = DLY2\_Counter \* UI\_Counter/TIMEBASE), so the delay time can reach a wider range.

# Stop Modes of Scan Update

You can call software stop function to stop waveform generation when it is still in progress. Three stop modes are provided for timed waveform generation meant to stop the waveform generation. You can apply these three modes to stop waveform generation no matter infinite or finite waveform generation mode is selected.

Figure 4-20 illustrates an example for stop mode I, assuming the data in the data buffer are 2V, 4V, 2V, and 0V. In this mode, the waveform stops immediately when software command is asserted.

![| Signal             | Value |\n| ------------------ | ----- |\n| Trigger            | High  |\n| DAWR               | Low   |\n| WFG_In_progress    | Low   |\n| Output Waveform    | Low   |\n| Operation start    | Start |\n| Software stop command | Stop  |](.daq-daqe-pxi-220x-50m-12258-1000-10/85c866f6896a81690a1b916842ee6916c94c0ed8f2f5b2f900efb9b8021dacbd.jpg)

Figure 4-20: Stop Mode I

In stop mode II, after a software stop command is given, the waveform generation does not stop until a complete single waveform is finished. See Figure 4-21. Since the UC\_counter is set to four, the total DA update counts (number of pulses of DAWR signal) must be a multiple of four (update counts = 20 in this example).

![| Signal Event             | Value |\n| ------------------------ | ----- |\n| Trigger                   | 4     |\n| DAWR                     | 0     |\n| WFG_In_progress          | 0     |\n| Output Waveform          | 0     |](.daq-daqe-pxi-220x-50m-12258-1000-10/20f4339f2b2356061e3a1d36851e94e62b727492211fffeaa9d5dbd57ead30fc.jpg)

Figure 4-21: Stop Mode II

In stop mode III, after a software stop command is given, the waveform generation does not stop until the performed number of waveforms is a multiple of the IC\_Counter. See Figure 4-22. Since the IC\_Counter is set to three, the total generated waveforms must be a multiple of three (waveforms = 6 in this example), and the total DA update counts must be a multiple of 12 (UC\_counter \* IC\_Counter). You can compare these three figures to see the differences.

![| Signal Type           | Value |\n|-----------------------|-------|\n| Trigger               | 1     |\n| DAWR                  | 0     |\n| WFG_In_progress       | 0     |\n| Output Waveform       | 0     |](.daq-daqe-pxi-220x-50m-12258-1000-10/9bb03cbde30fc3d9ce2e5147bb0977c23cabfb2591997ad1fbc6fb6c73700754.jpg)

Figure 4-22: Stop Mode III

# 4.3 Digital I/O

The DAQ/DAQe/PXI-2204/2205/2206/2208 card contains 24 lines of general-purpose digital I/O (GPIO) which is provided through the 82C55A chip.

The 24-line GPIO are separated into three ports: Port A, Port B and Port C. Port A and Port B can be programmed to be either input or output ports. Port C can be separated into high bit (PC4- PC7) and low bit (PC0-PC3), and both high bit and low bit ports can be programmed for input or output. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs.

The DAQ/DAQe/PXI-2010 also provides two digital inputs per channel (SDI from CN2), which are sampled simultaneously with an analog signal input and is stored with the 12-bit AD data. Refer to Figure 4.1 for the more details.

# 4.4 General Purpose Timer/Counter Operation

NOTEThe DAQ/DAQe/PXI-2208 card does not support this function.

Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following features:

 Count up/down controlled by hardware or software
 Programmable counter clock source (internal or external clock up to 10 MHz)
 Programmable gate selection (hardware or software control)
 Programmable input and output signal polarities (high active or low active)
 Initial count can be loaded from software
 Current count value can be read-back by software without affecting circuit operation

# 4.4.1 The Basics of Timer/Counter Functions

Each timer/counter has three inputs that can be controlled via hardware or software. These are clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UPDOWN). The GPTC\_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UPDOWN input controls whether the counter counts up or down. The GPTC\_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications.

The output of timer/counter is GPTC\_OUT. After power-up, GPTC\_OUT is pulled high by a pulled-up resister about 10K ohms. Then GPTC\_OUT goes low after the DAQ/DAQe/PXI-2204/ 2205/2206/2208 card is initialized.

All the polarities of input/output signals can be programmed by software. In this chapter, for easy explanation, all GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT are assumed to be active high or rising-edge triggered in the figures.

# 4.4.2 General Purpose Timer/Counter modes

Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the software-start is re-executed. The operating theories under different modes are described in the following sections.

# Mode1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the GPTC\_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software any time without affecting the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-23 illustrates the operation with initial count = 5, countdown mode.

![| Signal | Value |\n|--------|-------|\n| Gate   | 5     |\n| CLK    | 5     |\n| Count value | 5    |\n| Count value | 4     |\n| Count value | 3     |\n| Count value | 2     |\n| Count value | 1     |\n| Count value | 1     |\n| Count value | 0     |\n| ffff   | 0     |](.daq-daqe-pxi-220x-50m-12258-1000-10/4b703ea532f5201b2d633f2ef50c56ba31ce207e89003f21ec99698c6c27022e.jpg)

Figure 4-23: Mode1 Operation

# Mode2: Single Period Measurement

In this mode, the counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by software. Figure 4-24 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-220x-50m-12258-1000-10/ac75e15e6bb7be75969166305c7de6407dc4afd613b67d75f120ab8c977e1f51.jpg)

Figure 4-24: Mode2 Operation

# Mode3: Single Pulse-width Measurement

In this mode, the counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT outputs high, then current count value can be read-back by software. Figure 4-25 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-220x-50m-12258-1000-10/27ae39c87ba6cb678225b795bea13ccce219446286ec928ec427829e4f588009.jpg)

Figure 4-25: Mode3 Operation

# Mode4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC\_CLK input by software. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 2     |\n| CLK        | 2     |\n| Count value| 1     |\n| OUT        | 0     |](.daq-daqe-pxi-220x-50m-12258-1000-10/3d5bac6f3e6f252328f5d649caa67926212e2ea2b74dd5ea68379517f2c498b0.jpg)

Figure 4-26: Mode4 Operation

# Mode5: Single Triggered Pulse Generation

This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC\_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC\_CLK input. Once the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until the software-start is re-executed. Figure 4-27 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 2     |\n| CLK        | 2     |\n| Count value| 2     |\n| OUT        | 2     |](.daq-daqe-pxi-220x-50m-12258-1000-10/8fbac9df2237dfd28f6be475c726b5234586533871318c26ea13c3f3ae0dd40d.jpg)

Figure 4-27: Mode5 Operation

# Mode6: Re-triggered Single Pulse Generation

This mode is similar to Mode5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After the software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE triggers that occur when the prior pulse is not completed would be ignored. Figure 4-28 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four.

![| Signal | Value |\n|--------|-------|\n| Gate   | 0     |\n| CLK    | 0     |\n| Count  | 0     |\n| OUT    | 0     |](.daq-daqe-pxi-220x-50m-12258-1000-10/63d2918578b52b961962dd296ba7e474cff58ddae5499dc7bdf26d61c5e81770.jpg)

Figure 4-28: Mode6 Operation

# Mode7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. Once the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until the software-start is re-executed. Figure 4-29 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![| Signal | Value |\n|--------|-------|\n| Gate   | High  |\n| CLK    | Low   |\n| Count value | 4, 4, 3, 2, 1, 0, 2, 1, 0, 3, 2, 1, 0, 2, 1, 0, 3, 2 |](.daq-daqe-pxi-220x-50m-12258-1000-10/1475883b864a602a1c4283a8d0a740b4340c1b6923af3134084e3551431cbd31.jpg)

Figure 4-29: Mode7 Operation

# Mode8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![Software start\nGate\nCLK\nCount value + + 3 3 2 1 0 2 1 0 3 2 1 0 2 1 1 0 3\nOUT](.daq-daqe-pxi-220x-50m-12258-1000-10/7921ce458d90ae558fcbf7c8a5d95a307798735eda04c163b4344d1c915c5596.jpg)

Figure 4-30: Mode8 Operation

# 4.5 Trigger Sources

ADLINK provides flexible trigger selections in the DAQ/DAQe/PXI-2204/2205/2206/2208 card. In addition to the internal software trigger, the DAQ/DAQe/PXI-2204/2205/2206/2208 card also supports external analog, digital triggers, and SSI triggers. You can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger.

# 4.5.1 Software-Trigger

This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function calls to begin the operation. A/D and D/A processes can receive an individual software trigger.

# 4.5.2 External Analog Trigger

The analog trigger circuitry routing is shown in the Figure 4-31. The analog multiplexer can select either a direct analog input from the EXTATRIG pin (SRC1 in Figure 4-31) in the 68-pin connector or the input signal of ADC (SRC2 in Figure 4-31). That is, one of the four channel inputs you can select as a trigger source. Both trigger sources can be used for all trigger modes. The range of trigger level for SRC1 is ±10V and the resolution is 78mV (refer to Table 4-6), while the trigger range of SRC2 is the full-scale range of the selected channel input and the resolution is the desired range divided by 256. For example, if the channel input selected to be the trigger source is set bipolar and ±5V range, the trigger voltage would be 4.96V when the trigger level code is set to 0xFF while -4.96V when the code is set to 0x01.

![Based on the provided block diagram, here is an accurate and concise description:\n\n**Labeled Blocks:**\n*   **CN1, CN2, CN3, CN4:** Input labels on the left.\n*   **PGA:** Label above the first column of rectangular blocks.\n*   **Instrumentation Amplifier:** Label above the first column of triangular amplifier symbols.\n*   **ADC:** Label inside four rectangular blocks.\n*   **MUX:** Label inside two rectangular blocks (one small, one large).\n*   **EXTA TRIG:** Label pointing to the bottom of the vertical input bar.\n*   **Analog Trigger Circuit:** Label inside the final rectangular block.\n\n**Connections:**\n*   **Inputs:** A vertical bus bar on the left receives inputs labeled **CN1**, **CN2**, **CN3**, and **CN4**, as well as **EXTA TRIG**.\n*   **Signal Path:** The bus bar connects to four blocks labeled **PGA**. These connect to four triangular symbols labeled **Instrumentation Amplifier**.\n*   **ADCs:** The outputs of the Instrumentation Amplifiers connect directly to four blocks labeled **ADC**.\n*   **Multiplexing:** The outputs of the Instrumentation Amplifiers also connect to a small block labeled **MUX**.\n*   **SRC Lines:** Two lines labeled **SRC2** and **SRC1** emerge from the first **MUX** and connect to a larger **MUX** block.\n*   **Trigger Circuit:** The output of the second **MUX** connects to the **Analog Trigger Circuit**.\n*   **Final Output:** The **Analog Trigger Circuit** outputs a signal to the right (indicated by an arrow), with a pulse waveform shown above it.](.daq-daqe-pxi-220x-50m-12258-1000-10/50b5fbb0ddbf2b972877449c9de10fdf2339198215558cce9d45cd49af33c13e.jpg)

Figure 4-31: Analog Trigger Block Diagram

<table><tr><td>Trigger level digital setting</td><td>Trigger voltage</td></tr><tr><td>0xFF</td><td>9.92V</td></tr><tr><td>0xFE</td><td>9.84V</td></tr><tr><td>0x81</td><td>0.08V</td></tr><tr><td>0x80</td><td>0</td></tr><tr><td>0x7F</td><td>-0.08V</td></tr><tr><td>0x01</td><td>-9.92V</td></tr></table>

# Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic

The trigger signal is generated when the analog trigger condition is satisfied. There are five analog trigger conditions in the DAQ/ DAQe/PXI-2204/2205/2206/2208 card. The DAQ/DAQe/PXI-2204/2205/2206/2208 card uses two threshold voltages, Low\_Threshold and High\_Threshold to build the five different trigger conditions. You can configure the trigger conditions easily by software.

# Below-Low Analog Trigger Condition

Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low\_Threshold voltage, and the High\_Threshold setting is not used in this trigger condition.

![Low_Threshold\nTrigger](.daq-daqe-pxi-220x-50m-12258-1000-10/1b43fff5e940f2ae39fb57446ba944ff18407876e92968084aff148596d2c37d.jpg)

Figure 4-32: Below-Low Analog Trigger Condition

# Above-High Analog Trigger Condition

Figure 4-33 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than the High\_Threshold voltage, and the Low\_Threshold setting is not used in this trigger condition.

![High_Threshold\nTrigger](.daq-daqe-pxi-220x-50m-12258-1000-10/9ced81221c23228f50fa26079d0651a60fd3a1667cc8b8ddfaced1049222e948.jpg)

Figure 4-33: Above-High Analog Trigger Condition

# Inside-Region Analog Trigger Condition

Figure 4-34 shows the inside-region analog trigger condition, the trigger signal is generated when the input analog signal level falls in the range between the High\_Threshold and the Low\_Threshold voltages.

![The image features a white document icon with a folded top-left corner and faint horizontal lines. A large, bold red checkmark is superimposed over the document.](.daq-daqe-pxi-220x-50m-12258-1000-10/e41ad44d5205aa338a7b5170722e8e8e5959c924035b9de22b5652c54d7bbfbe.jpg)
NOTE:

The High\_Threshold setting should be always higher than the Low\_Threshold voltage setting.

![| Trigger | High_Threshold | Low_Threshold |\n| ------- | ------------- | ------------ |\n| Start   | Low           | Low          |\n| Mid     | High          | Low          |\n| End     | High          | Low          |](.daq-daqe-pxi-220x-50m-12258-1000-10/fa571dafa1e8cc97189f9a79655329c8900ebaa65ff8f844d6d6f7fd319dbcfa.jpg)

Figure 4-34: Inside-Region Analog Trigger Condition

# High-Hysteresis Analog Trigger Condition

Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High\_Threshold voltage, and the Low\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting.

![| Time Segment | Value |\n| ------------ | ----- |\n| Trigger      | Low_Threshold |\n| High_Threshold | High_Threshold |](.daq-daqe-pxi-220x-50m-12258-1000-10/4bc75c9f606b7f120ca7c4e0656f5b0797db982e7e6e4089b0cdbad1061c1651.jpg)

Figure 4-35: High-Hysteresis Analog Trigger Condition

# Low-Hysteresis Analog Trigger Condition

Figure 4-36 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low\_Threshold voltage, and the High\_Threshold voltage determines the hysteresis duration. Note the High\_Threshold setting should be always higher then the Low\_Threshold voltage setting.

![| Trigger | High_Threshold | Low_Threshold |\n| ------- | -------------- | ------------- |\n| Low     | Peak           | Low           |\n| High    | Peak           | Peak          |](.daq-daqe-pxi-220x-50m-12258-1000-10/bb5c850cfed14834e7a455496f86173d3748465237e101b42db90eefb255a762.jpg)

Figure 4-36: Low-Hysteresis Analog Trigger Condition

# External Digital Trigger

An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT-DTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process. You can program the trigger polarity using the software drivers. Note that the signal level of the external digital trigger signals should be TTLcompatible and the minimum pulse is 20 ns.

![Based on the image provided, here is the description:\n\n**Labeled Blocks/Text:**\n*   'Positive-edge trigger event occurs'\n*   'Negative-edge trigger event occurs'\n\n**Visual Elements and Connections:**\nThe image displays two separate signal waveforms side-by-side with no interconnecting lines between them:\n1.  **Left Diagram:** Shows a rising edge of a signal line with a black arrow pointing upwards. The text 'Positive-edge trigger event occurs' is positioned to the left of the rising edge.\n2.  **Right Diagram:** Shows a falling edge of a signal line with a black arrow pointing downwards. The text 'Negative-edge trigger event occurs' is positioned to the right of the falling edge.](.daq-daqe-pxi-220x-50m-12258-1000-10/7f037add143d0c87135ec6307ac36b2b3ab0a51e700a4eb3f500a758883c6141.jpg)

Figure 4-37: External Digital Trigger

# 4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and requirements for synchronizing multiple cards, the DAQ/DAQe/ PXI-2204/2205/2206/2208 card provides flexible user-controllable timing signals to connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card is composed of a bunch of counters and trigger signals in the FPGA. These timing signals are related to the A/D, D/A conversions, and Timer/Counter applications. These timing signals can be input to or output from the I/O connectors, SSI connector, and the PXI bus. Therefore, the internal timing signals can be used to control external devices or circuitry. Note that in other models of DAQ/DAQe/PXI-2204/2205/2206/2208 card, the usercontrollable timing signals may vary. However, the SSI/PXI timing signals remain the same for every DAQ/DAQe/PXI-2204/2205/ 2206/2208 card.

We implemented signal multiplexers in the FPGA to individually choose the desired timing signals for the DAQ operations, as shown in the Figure 4-38.

![This flowchart depicts a signal distribution system flowing from left to right, consisting of input blocks, a central processing block, and output blocks connected by vertical switching elements.\n\n**Labeled Blocks:**\n*   **Internal timing signals**\n*   **SSI timing Signals**\n*   **AFI timing signals**\n*   **DAQ timing signals**\n*   **SSI timing Signals**\n*   **Trigger_Out timing signals**\n\n**Connections:**\n*   Three input blocks on the left ('Internal timing signals', 'SSI timing Signals', and 'AFI timing signals') each connect via three lines to a vertical trapezoid.\n*   The output of that first trapezoid connects via three lines to the central block, 'DAQ timing signals'.\n*   The output of 'DAQ timing signals' connects via three lines to a second vertical trapezoid on the right.\n*   The output of the second trapezoid splits to connect to two final blocks on the right: 'SSI timing Signals' (top) and 'Trigger_Out timing signals' (bottom).](.daq-daqe-pxi-220x-50m-12258-1000-10/bcedb8d13c1d4fea74f5d1fe009114463a30cf74f77e1eced09eed23231b05a5.jpg)

Figure 4-38: DAQ signals routing

You can utilize the flexible timing signals through our software drivers, then simply and correctly connect the signals with the DAQ/DAQe/PXI-2204/2205/2206/2208 card. Here is the summary of the DAQ timing signals and the corresponding functionalities for DAQ/DAQe/PXI-2204/2205/2206/2208 card.

<table><tr><td>Timing signal category</td><td>Corresponding functionality</td></tr><tr><td>SSI/PXI signals</td><td>Multiple cards synchronization</td></tr><tr><td>AFI signals</td><td>Control DAQ/DAQe/PXI-2204/2205/2206/2208 by external timing signals</td></tr></table>

Table 4-8: User-controllable Timing Signals and Functionalities

# 4.6.1 DAQ timing signals

![The image displays a square icon featuring a white document with a folded upper-right corner. Faint, horizontal grey lines run across the document, and a large, bold red checkmark is superimposed over the center.](.daq-daqe-pxi-220x-50m-12258-1000-10/f696962eebed2dd643fbc5ad622dbc5456b70a0dcafa90c77fcb5e93e3b49ef5.jpg)
NOTE:

Refer to section 4.1 for the internal timing signal definition.

The DAQ/DAQe/PXI-2208 card supports SCAN\_START, ADCONV and DA\_TRIG, DAWR.

The user-controllable DAQ timing-signals contain:

1. TIMEBASE, providing TIMEBASE for all DAQ operations, which could be from internal 40 MHz oscillator, EXTTIMEBASE from I/O connector or the SSI\_TIMEBASE. Note that the frequency range of the EXTTIMEBASE is 1 MHz to 40 MHz, and the EXTTIME-BASE must be TTL-compatible.
2. AD\_TRIG, the trigger signal for the A/D operation, which could come from external digital trigger, analog trigger, internal software trigger, and SSI\_AD\_TRIG. Refer to section 4.5 for detailed description.
3. SCAN\_START, the signal to start a scan, which would bring the following ADCONV signals for AD conversion, and could come from the internal SI\_counter, AFI[0] and SSI\_AD\_START. This signal is synchronous to the TIMEBASE. Note that the AFI[0] should be TTL-compatible and the minimum pulse width should be the pulse width of the TIMEBASE to guarantee correct functionalities.

4. ADCONV, the conversion signal to initiate a single conversion, which could be derived from internal counter, AFI[0] or SSI\_ADCONV. Note that this signal is edgesensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effective conversion signal. Also note that the AFI[0] signal should be TTL-compatible and the minimum pulse width is 20 ns.
5. DA\_TRIG, the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trigger, internal software trigger, and SSI\_AD\_TRIG. Refer to section 4.5 for detailed description.
6. DAWR, the update signal to initiate a single D/A conversion, which could be derived from internal counter, AFI[1] or SSI\_DAWR. Note that this signal is edge-sensitive. When using AFI[1] as the external DAWR source, each rising edge of AFI[1] would bring an effective update signal. Also note that the AFI[1] signal should be TTL-compatible and the minimum pulse width is 20 ns.

# 4.6.2 Auxiliary Function Inputs (AFI)

You can use the AFI in applications that take advantage of external circuitry to directly control the DAQ/DAQe/PXI-2204/2205/ 2206/2208 card. The AFI includes two categories of timing signals: one group is the dedicated input, and the other is the multi-function input. Table 4-9 illustrates this categorization.

<table><tr><td>Category</td><td>Timing signal</td><td>Functionality</td><td>Constraints</td></tr><tr><td rowspan="3">Dedicated input</td><td>EXTTIMEBASE</td><td>Replace the internal TIME-BASE</td><td>TTL-compatible1 MHz to 40 MHzAffects on both A/D and D/A operations.</td></tr><tr><td>EXTDTRIG</td><td>External digital trigger input for A/D operation</td><td>TTL-compatibleMinimum pulse width = 20nsRising edge or falling edge</td></tr><tr><td>EXTWFTRG</td><td>External digital trigger input for D/A operation</td><td>TTL-compatibleMinimum pulse width = 20nsRising edge or falling edge</td></tr><tr><td rowspan="3">Multi-function input</td><td rowspan="2">AFI[0](Dual-functions)</td><td>Replace the internal ADCONV</td><td>TTL-compatibleMinimum pulse width = 20nsRising-edge sensitive only</td></tr><tr><td>Replace the internal SCAN_START</td><td>TTL-compatibleMinimum Pulse width &gt; 2/TIMEBASE</td></tr><tr><td>AFI[1]</td><td>Replace the internal DAWR</td><td>TTL-compatibleMinimum pulse width = 20nsRising-edge sensitive only</td></tr></table>

Table 4-9: Auxiliary Function Input Signals and Functionalities

# EXTDTRIG and EXTWFTRIG

EXTDTRIG and EXTWFTRIG are dedicated digital trigger input signals for A/D and D/A operations respectively. Refer to section 4.5 for details.

# EXTTIMEBASE

When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE — the 40 MHz clock — you could utilize the EXT-TIMEBASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE.

# AFI[0]

Alternatively, you can also directly apply an external A/D conversion signal to replace the internal ADCONV signal. This is another way to achieve customized sampling frequencies. The external ADCONV signal can only be inputted from the AFI[0]. As section 4.1 describes, the SI\_counter triggers the generation of the A/D conversion signal, ADCONV, but when using the AFI[0] to replace the internal ADCONV signal, the SI\_counter and the internally generated SCAN\_START is not effective. By controlling the ADCONV externally, you can sample the data according to external events. In this mode, the Trigger signal and trigger mode settings are not available.

AFI[0] could also be used as SCAN\_START signal for A/D operations. Refer to section 4.1 and section 4.6 for detailed descriptions of the SCAN\_START signal. When using external signal (AFI[0]) to replace the internal SCAN\_START signal, the pulse width of the AFI[0] must be greater than two time of the period of Timebase. This feature is suitable for the DAQ-2200/ DAQe-2200/PXI-2200 Series, which can scan multiple channels data controlled by an external event. Note that the AFI[0] is a multi-purpose input, and it can only be utilized for one function at any one time.

# AFI[1]

Regarding the D/A operations, users could directly input the external D/A update signal to replace the internal DAWR signal. This is another way to achieve customized D/A update rates. The external DAWR signal can only be inputted from the AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. AFI[1] currently only has one function. ADLINK reserves it for future development.

# 4.6.3 System Synchronization Interface

SSI (System Synchronization Interface) provides the DAQ timing synchronization between multiple cards. In DAQ/DAQe/PXI-2204/ 2205/2206/2208 card, we designed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI signals are designed for card synchronization only and not for external devices.

<table><tr><td>SSI Timing Signal</td><td>Setting</td><td>Function</td></tr><tr><td rowspan="2">SSI_TIMEBASE</td><td>Master</td><td>Send the TIMEBASE out</td></tr><tr><td>Slave</td><td>Accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.</td></tr><tr><td rowspan="2">SSI_ADCONV</td><td>Master</td><td>Send the ADCONV out</td></tr><tr><td>Slave</td><td>Accept the SSI_ADCONV to replace the internal ADCONV signal.</td></tr><tr><td rowspan="2">SSI_SCAN_START</td><td>Master</td><td>Send the SCAN_START out</td></tr><tr><td>Slave</td><td>Accept the SSI_SCAN_START to replace the internal SCAN_START signal.</td></tr><tr><td rowspan="2">SSI_AD_TRIG</td><td>Master</td><td>Send the internal AD_TRIG out</td></tr><tr><td>Slave</td><td>Accept the SSI_AD_TRIG as the digital trigger signal.</td></tr><tr><td rowspan="2">SSI_DAWR</td><td>Master</td><td>Send the DAWR out.</td></tr><tr><td>Slave</td><td>Accept the SSI_DAWR to replace the internal DAWR signal.</td></tr><tr><td rowspan="2">SSI_DA_TRIG</td><td>Master</td><td>Send the DA_TRIG out.</td></tr><tr><td>Slave</td><td>Accept the SSI_DA_TRIG as the digital trigger signal.</td></tr></table>

Table 4-10: SSI Timing Signal and Functions

In PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector position. All the SSI signals are routed to the 20-pin connector from the FPGA. To synchronize multiple cards, users can connect a special ribbon cable (ACL-SSI) to all the cards in a daisy-chain configuration.

In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections. All the SSI signals are routed to the P2 connector. No additional cable is needed. For detailed information of the PXI specifications, refer to the PXI Specification Revision 2.0 from PXI System Alliance (www.pxisa.org).

The six internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers. Refer to section 4.6 for detailed information on the six internal timing signals. Physically, the signal routings are accomplished in the FPGA. Cards that are connected together through the SSI or the PXI trigger bus, will still achieve synchronization on the six timing signals.

# The SSI/PXI Mechanism

We adopt master-slave configuration for SSI/PXI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with SSI function disabled.

For each timing signal, the SSI master does not have to be in a single card. For example:

We want to synchronize the A/D operation through the ADCONV signal for four DAQ/DAQe/PXI-2204/2205/2206/ 2208 cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisition. The SSI setting could be:

 Set the SSI\_ADCONV signal of Card 1 to be the master.
 Set the SSI\_ADCONV signals of Card 2, 3, 4 to be the slaves.
 Set external digital trigger for Card 1’s A/D operation.
 Set the SI\_counter and the post scan counter (PSC) of all other cards.
Start DMA operations for all cards, so all the cards are waiting for the trigger event.

When the digital trigger condition of Card 1 occurs, Card 1 will internally generate the ADCONV signal and output this ADCONV signal to SSI\_ADCONV signal of Card 2, 3 and 4 through the SSI/PXI connectors. Thus we can achieve 16- channel acquisition simultaneously.

You could arbitrarily choose each of the six timing signals as the SSI master from any one of the cards. The SSI master can output the internal timing signals to the SSI slaves. With the SSI, users could achieve better card-to-card synchronization.

Note that when power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals.

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# 5 Calibration

This chapter introduces the calibration process to minimize AD measurement errors and DA output errors.

# 5.1 Loading Calibration Constants

The DAQ/DAQe/PXI-2204/2205/2206/2208 card is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. Trim-DACs do not have memory capability. That means the calibration constants do not retain their values after the system power is turned off. Loading calibration constants is the process of loading the values of TrimDACs firmware stored in the onboard EEPROM. ADLINK provides a software utility that automatically reads the calibration constants automatically, if necessary.

There is a dedicated space for storing calibration constants in the EEPROM. In addition to the default bank of factory calibration constants, there is one user-utilization bank. This bank allows you to load the TrimDACs firmware values either from the original factory calibration or from a subsequently-performed calibration.

Because of the fact that measurements and outputs errors may vary depending on time and temperature, it is recommended that you calibrate the card when it is integrated in your computing environment. The auto-calibration function is presented in the following sections.

# 5.2 Auto-calibration

Through the DAQ/DAQe/PXI-2204/2205/2206/2208 card auto-calibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices.

The DAQ/DAQe/PXI-2204/2205/2206/2208 card comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software. The calibration constant is memorized after this measurement. We do not recommended adjustment of the onboard calibration reference except when an ultra-precision calibrator is available.

![The image displays a white document icon featuring horizontal lines, overlaid with a large red checkmark. Below this graphic is the text 'NOTE:' in bold, black capital letters.](.daq-daqe-pxi-220x-50m-12258-1000-10/cfc6c96877b5f3eebce11827a287041de7d00e26033faa9100bc002431b2feb3.jpg)

 Warm the card up for at least 15 minutes before initiating auto-calibration.
 Remove the cable before auto-calibrating the card since the DA outputs are changed during the process.

# 5.3 Saving Calibration Constants

When auto-calibration is completed, you can save the new calibration constants to the user-configurable banks in the EEPROM. The date and the temperature when you ran auto-calibration is saved with the calibration constants. You can store three sets of calibration constants according to three different environments and re-load the calibration constants later.

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

 Read these safety instructions carefully.
 Keep the User’s Manual for future reference.
 Read the Specifications section of this manual for detailed information on the recommended operating environment.
 The device can be operated at an ambient temperature of 50ºC.
When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing:
 Turn off power and unplug any power cords/cables.
 Reinstall all chassis covers before restoring power.

 To avoid electrical shock and/or damage to device:

 Keep device away from water or liquid sources.
 Keep device away from high heat or humidity.
 Keep device properly ventilated (do not block or cover ventilation openings).
 Always use recommended voltage and power source settings.
 Always install and operate device near an easily accessible electrical outlet.
 Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate device on stable surfaces and/or recommended mountings.

 If the device will not be used for long periods of time, turn off and unplug it from its power source
 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a standard warning sign consisting of a yellow equilateral triangle with a thick black border. Centered inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is written in black capital letters.](.daq-daqe-pxi-220x-50m-12258-1000-10/35162ce134f22663a7ebdb5b0ffcd4ddf448fac89e5f74bdca28cea4d34e2d6a.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged.
 Liquid has entered the device interior.
 The device has been exposed to high humidity and/or moisture.
 The device is not functioning or does not function according to the User’s Manual.
 The device has been dropped and/or damaged and/or shows obvious signs of breakage.

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.

 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.daq-daqe-pxi-220x-50m-12258-1000-10/bbc20af53f7c12cf65b8d5fd0478bf9ea7f8a526f54de9d6563bbdd9ea733fde.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Road, Guishan District

Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose,

CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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