# DAQ/DAQe/PXI-250x Series

High Performance

Analog Output Multi-function Cards

User’s Manual

Manual Rev. 1.0

Revision Date: Dec. 29, 2023

Part No: 50M-12264-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.01</td><td>2006-12-21</td><td>Previous release PN: 50-12265-100</td></tr><tr><td>1.0</td><td>2023-12-29</td><td>Initial release under new part number.Added 1.4 Software Support.Added 2.4 Switch and Jumper Settings.Added SSI connector pin assignment on PXI J2.Added 4.1.6 Bus-mastering DMA Data Transfer.</td></tr></table>

# Preface

# Copyright © 2023 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.daq-daqe-pxi-250x-50m-12264-1000-10/335ac068ddcd9902e58a81971afffc530dcdcbd744675ea126151b9413f7e5bd.jpg)

Battery Labels (for products with battery)
![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.daq-daqe-pxi-250x-50m-12264-1000-10/0252b5b0deb533317bce1a0b1fd619465fe7271265c1b6fbc184363f9c1b465d.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.daq-daqe-pxi-250x-50m-12264-1000-10/c4de9a8549569e5d85fcc5d288361820ddec568d6811f3f1fc30c56ea57a0581.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.daq-daqe-pxi-250x-50m-12264-1000-10/a2e87f274a3c6d2c5f8fec8e5a806fd76c75e2f341b288fdae834cb6c14f93f0.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.daq-daqe-pxi-250x-50m-12264-1000-10/5b5ffe2981eb0f644754597cb29c6e75661ae3ba1ef8c7528c20e43648dbacb9.jpg)

ᘄ㟁ụㄳᅇᨲ

# California Proposition 65 Warning

![The image displays a standard yellow warning sign. It is an equilateral triangle with a thick black border, featuring a single black exclamation point centered inside.](.daq-daqe-pxi-250x-50m-12264-1000-10/769f23644f26e03b0446e343f606895bd028d0bdfcbe1421029238d04a60f926.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon featuring a folded upper-right corner and faint horizontal lines. A large red checkmark is overlaid diagonally across the center of the document.](.daq-daqe-pxi-250x-50m-12264-1000-10/d64b16ee0355065ffdcc18ef302dd72f4576a96bbe5c5bbc96206fae898bf20c.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image shows a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation mark. The sign is set against a white background, and a thin black horizontal line is visible at the very top edge.](.daq-daqe-pxi-250x-50m-12264-1000-10/1e1962672431583297cf18d02bf7352ca946d276a349933e9c033ed2530e26b6.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a triangular warning symbol. It consists of a dark red triangle with a thin white border. Centered inside the triangle is a large, white exclamation mark.](.daq-daqe-pxi-250x-50m-12264-1000-10/1e93373071b9edc4b06c9a473072fbb05a7ba3cfa35703a59b8fae7e7969d302.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface ......... iii

# List of Tables......... . vii

# List of Figures ........ ix

# 1 Introduction .........

1.1 Features.... 2
1.2 Applications .. 3
1.3 Specifications.... 3
1.4 Software Support .. 7

# 2 Installation ........ . 11

2.1 Contents of Package ..... 11
2.2 Unpacking.... . 12
2.3 DAQ/DAQe/PXI-250x Series Layout . 1 3
2.4 Switch and Jumper Settings . 1 4
2.5 PCI Configuration . 1 8

# 3 Signal Connections....... . 19

3.1 Connectors Pin Assignment . 1 9

# 4 Operation Theory ......... 2 5

4.1 A/D Conversion... 27
4.2 D/A Conversion... 3 5
4.3 General Purpose Digital I/O... 4 9
4.4 General Purpose Timer/Counter Operation.. 4 9
4.5 Trigger Sources .. 5 5
4.6 Timing Signals ..... 59

# 5 Calibration ........ ...... 61

5.1 Auto-calibration ..... . 61
5.2 Saving Calibration Constants.... 62
5.3 Loading Calibration Constants.... 62

# Important Safety Instructions....... ... 65

# Getting Service ....... .... 67

# List of Tables

Table 2-1: Board ID SW1 DIP Switch Settings 15

Table 3-1: Connector CN1 pin assignment . 19

Table 3-2: Connector CN2 pin assignment . 2 0

Table 3-3: SSI connector pin assignment . 2 2

Table 3-4: SSI Connector Pin Assignment on PXI J2 .............. 22

Table 3-5: Legend of SSI connector . 23

Table 4-1: Bipolar Input Range and Converted Digital Codes . 27

Table 4-2: Unipolar Input Range and Converted Digital Codes 28

Table 4-3: Trigger Modes and Corresponding Trigger Sources 29

Table 4-4: Summary of Counters for Programmable Scan ...... 29

Table 4-5: D/A Output Versus Digital Codes ..... 3 8

Table 4-6: Trigger Signals and Corresponding Signal Sources 39

Table 4-7: Summary of Counters for Waveform Generation ... 39

Table 4-8: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic 56

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# List of Figures

Figure 2-1: PCB Layout of the DAQ-2502/2501 13

Figure 2-2: PCB Layout of the PXI-DAQ-2502/2501 .... 1 3

Figure 2-3: Board ID SW1 DIP Switch . 1 4

Figure 2-4: Enable Board ID Configuration...... 1 6

Figure 4-1: DAQ/DAQe/PXI-250x Series Block Diagram........... 26

Figure 4-2: Timing for Scan ... 30

Figure 4-3: Post Trigger ... 3 1

Figure 4-4: Delay Trigger .... 3 2

Figure 4-5: Post Trigger with Retrigger.. 3 2

Figure 4-6: Linked List of PCI Address DMA Descriptors .......... 34

Figure 4-7: Block Diagram of D/A Group ... . 35

Figure 4-8: Data Format in FIFO and Mapping.. 36

Figure 4-9: Typical D/A timing of waveform generation ............. 41

Figure 4-10: Post-Trigger Generation ... 4 2

Figure 4-11: Delay-Trigger Generation .. 4 3

Figure 4-12: Post-Trigger with Retrigger Generation..... 4 3

Figure 4-13: Finite iterative waveform generation w/Post-trigger 45

Figure 4-14: Infinite iterative waveform generation w/Post-trigger 45

Figure 4-15: Stop mode I .. 4 7

Figure 4-16: Stop mode II . 4 7

Figure 4-17: Stop mode III .. 4 8

Figure 4-18: Mode 1 Operation.. 5 0

Figure 4-19: Mode 2 Operation.. 5 1

Figure 4-20: Mode 3 Operation.. 51

Figure 4-21: Mode 4 Operation.. 5 2

Figure 4-22: Mode 5 Operation.. 5 3

Figure 4-23: Mode 6 Operation.. 5 3

Figure 4-24: Mode 7 Operation.. 5 4

Figure 4-25: Mode 8 Operation.. 54

Figure 4-26: Analog trigger block diagram.. 56

Figure 4-27: Below-Low analog trigger condition.. 56

Figure 4-28: Above-High analog trigger condition . 57

Figure 4-29: Inside-Region analog trigger condition ..... 57

Figure 4-30: High-Hysteresis analog trigger condition ........... 5 8

Figure 4-31: Low-Hysteresis analog trigger condition........ 58

Figure 4-32: DAQ signals routing.... 59

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# 1 Introduction

The DAQ/DAQe/PXI-250x Series is an advanced analog output card based on the 32-bit PCI/PXI architecture. High performance designs and state-of-the-art technology make this card ideal for waveform generation, industrial process control, and signal analysis applications in medical, process control, etc.

# 1.1 Features

DAQ/DAQe/PXI-250x Series advanced analog output cards provide the following advanced features:

 32-bit PCI/PXI-Bus, plug and play
 Up to 1MS/s analog output rate
 Up to 400KS/s analog input rate
 Up to 8 analog output channels for DAQ/DAQe/PXI-2502, and 4 analog output channels for DAQ/DAQe/PXI-2501
 Up to 4 analog input channels for DAQ/DAQe/PXI-2502, and 8 analog input channels for DAQ/DAQe/PXI-2501
 Programmable bipolar/unipolar range for analog input channels and individual analog output channels
 Programmable internal/external reference for individual analog output channels
D/A FIFO size: 8K samples for DAQ/DAQe/PXI-2501, and 16K samples for DAQ/DAQe/PXI-2502
 A/D FIFO size: 2K samples
Versatile trigger sources: software trigger, external digital trigger, ana-log trigger and trigger from System Synchronization Interface (SSI)
 A/D Data transfer: software polling & bus-mastering DMA with Scat-ter/Gather
 D/A Data transfer: software update and bus-mastering DMA with Scatter/Gather
 A/D trigger modes: post-trigger, delay-trigger with re-trigger functionality
 D/A outputs with waveform generation capability
 System Synchronization Interface (SSI)
 A/D and D/A fully auto-calibration
 Built-in programmable D/A external reference voltage compensator
 Completely jumper-less and software configurable

# 1.2 Applications

 Automotive Testing
 Arbitrary Waveform Generator
 Transient signal measurement
 ATE
 Laboratory Automation
 Biotech measurement

# 1.3 Specifications

# Analog Input (AI)

 Number of channels:
 4 single-ended for DAQ/DAQe/PXI-2502
 8 single-ended for DAQ/DAQe/PXI-2501
 AD converter: LTC1416
 Max sampling rate: 400KS/s
 Resolution: 14 bits
 FIFO buffer size: 2K samples
 Input range: Bipolar: ±10V, unipolar: 0\~10V
 Over voltage protection: Continuous ±35V maximum
 Input impedance: 1G | 6pF
 Trigger modes: Pre-trigger, post-trigger, middle-trigger, and delay trigger
 Data transfers: Programmed I/O, and bus-mastering DMA with scatter/gather
 Input coupling: DC
 Offset error: ±4mV max
 Gain error: ±0.3 % of output max

# Analog Output (AO)

 Number of channels: 4-ch for DAQ/DAQe/PXI-2501, 8-ch for DAQ/DAQe/PXI-2502
 DA converter: AD7945
 Max update rate: 1MS/s
 Resolution: 12 bits
 FIFO buffer size: 8K for DAQ/DAQe/PXI-2501, 16K for DAQ/PXI- 2502
 Data transfer: Programmed I/O, and bus-mastering DMA with scat-ter/gather
 Voltage reference: internal 10V or external up to ±510V
 Output range:
 Bipolar: ±10V or ±external reference
 Unipolar: 0\~10V or 0\~ external reference
 Settling time for –10\~+10V step: 2μs
 Slew rate: 20V/μs
 Output coupling: DC
 Protection: Short-circuit to ground
 Output impedance: 0.1. max.
 Output current: ±5mA max.
 Power-on state: 0V steady-state
 Power-on glitch: ±600mV/500μs
 Offset error: ±2mV max
 Gain error: ±0.05% of output max

# General Purpose Digital I/O (G.P. DIO)

 Number of channels: 24 programmable Input/Output
 Compatibility: TTL/CMOS
 Input voltage:

 C> Logic Low: VIL=0.8V max.; IIL=0.2mA max.

 C> High: VIH=2.0V max.; IIH=0.02mA max

 Output voltage:

 C> Low: VOL=0.5 V max.; IOL=8mA max.
 C> High: VOH=2.7V min; IOH=400?A

# General Purpose Timer/Counter (GPTC)

 Number of channel: 2 Up/Down Timer/Counters
 Resolution: 16 bits
 Compatibility: TTL/CMOS
 Clock source: Internal or external
 Max source frequency: 10MHz

# Analog Trigger (A.Trig)

 Source: external analog trigger (EXTATRIG)
 Level: ±10V external
 Resolution: 8 bits
 Slope: Positive or negative (software selectable)
 Hysteresis: Programmable
 Bandwidth: 400khz
 External Analog Trigger Input (EXTATRIG)
 Input Impedance: 40k
 Coupling: DC
 Protection: Continuous ±35V maximum

# System Synchronous Interface (SSI)

 Trigger lines: 7

# Calibration

 Recommended warm-up time: 15 minutes
 Onboard reference: 5.0V
 Temperature coefficient: ±2ppm/C
 Long-term stability: 6ppm/1000Hr

# Physical

 Dimensions: 175mm by 107mm
 I/O connector: 68-pin female mini-SCSI type
 Power Requirement: +5VDC: 1.6A typical

# Operating Environment

 Ambient temperature: 0 to $5 5 ^ { \circ } \mathrm { C }$
 Relative humidity: 10% to 90% non-condensing

# Storage Environment

 Ambient temperature: -20 to $70 \textdegree$
 Relative humidity: 5% to 95% non-condensing

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platforms.

By leveraging low-level kernel management and a user friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![Based on the provided image, here is an accurate and concise description of the block diagram, organized by its layered structure:\n\n**Top Layer: Management and SDKs**\n*   **Left Block:** A red vertical block labeled **'MAPS Core Device Management'** containing four gray sub-blocks stacked vertically:\n    *   'Device Manager (ACE)'\n    *   'PXI Platform Resource Mgmt. Utility'\n    *   'PXI Platform ChassisWatch Utility'\n    *   'DAQ/IO Module Function Test Utility'\n*   **Right Columns:** Three vertical columns representing different programming environments, each consisting of a top white block and a colored block underneath:\n    *   **Column 1:** Top block reads **'User APPs in C/C++'**. Below it is an orange block labeled **'MAPS/C C/C++ SDK for DAQ/IO module'**.\n    *   **Column 2:** Top block reads **'User APPs in LabVIEW'**. Below it is a green block labeled **'MAPS/LV LabVIEW SDK for DAQ/IO module'**.\n    *   **Column 3:** Top block reads **'User APPs in C#'**. Below it is a purple block labeled **'MAPS/C# C# SDK for DAQ/IO module Coming soon'**.\n\n**Middle Layer: Runtime Services**\n*   A wide red horizontal bar spanning the width of the upper section.\n*   Text on the left reads: **'MAPS Core -Device Runtime'**.\n*   Text on the right lists three services:\n    *   'PXI Platform Service'\n    *   'DAQ/IO Module Device Driver'\n    *   'DAQ/IO Module Runtime Library'\n\n**Bottom Layer: Hardware**\n*   A blue horizontal bar at the bottom containing images of hardware devices, each with a label underneath:\n    *   'Digitizers'\n    *   'DAQ'\n    *   'Edge Platform'\n    *   'PXle Controllers'\n    *   'PXle/PXI Chassis'](.daq-daqe-pxi-250x-50m-12264-1000-10/0306bc8f8fbb52b4461e7d25abfd37e4aa4d4459698ff07b4a06927bb23c16ad.jpg)

# 1.4.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\nGeneral\n0: PCI9112 Device 'PCI-9'\nUSB\nSettings\nAlias Name PCI-9112-0\nVendor ADLINK Technology Inc.\nModel PCI9112 Device\nPCI Bus 2\nPCI Device 11\nPCI Function 0\nDMA Buffer\nAI 1024 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch\nCorelib](.daq-daqe-pxi-250x-50m-12264-1000-10/f8c980c5c48ab0d74879600df0022216f8f20f7f717c9ae8fc1c0ff71725452f.jpg)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen.

![| Time (Sec) | Voltage (Vpp) |\n| ---------- | ------------- |\n| 0.00       | 5             |\n| 0.03       | 5             |\n| 0.06       | -10           |\n| 0.08       | -5            |\n| 0.10       | 5             |](.daq-daqe-pxi-250x-50m-12264-1000-10/1a6fb56df65204b0d7231c4d9ffbc60e0f439098f86bf9cb77d0b78fc2546cc4.jpg)

# 1.4.2 MAPS/LV, LabVIEW Support

Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual:

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_LV

# 1.4.3 MAPS/C, C & C++ Support

Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_C

# 2 Installation

This chapter describes how to install DAQ/DAQe/PXI-250x Series cards. The contents of the package and unpacking information that you should be aware of are outlined first.

# 2.1 Contents of Package

In addition to this User's Guide, the package should include the following items:

 DAQ/DAQe/PXI-250x Series Multi-function Data Acquisition Card
 Software Installation Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

# 2.2 Unpacking

Your DAQ/DAQe/PXI-250x Series card contains electro-static sensitive components that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damages. Shipping and han-dling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

You are now ready to install your DAQ/DAQe/PXI-250x Series.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

# 2.3 DAQ/DAQe/PXI-250x Series Layout

![Board to Board Connector\nSSI Connector\n68\nPIN Connector\n2501/2502\nDaughter Board\nDAQ-2000\nCarrier Board\nBoard to Board Connector](.daq-daqe-pxi-250x-50m-12264-1000-10/8daef6d249ae378b54022acc94970ab45444115fbfcc3d08a1872162dc17d748.jpg)

Figure 2-1: PCB Layout of the DAQ-2502/2501

![68 PIN Connector\n2501/2502\nDaughter Board\nBoard to Board Connector\nPXI-2000 Carrier Board](.daq-daqe-pxi-250x-50m-12264-1000-10/fd31c695b61cb1bd7fb2d5823a2783c85e391b9a412c5db451b8ed11e54b6fc1.jpg)

Figure 2-2: PCB Layout of the PXI-DAQ-2502/2501

# 2.4 Switch and Jumper Settings

# 2.4.1 Board ID (SW1)

The DAQ/DAQe/PXI-250x Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for identifying each card’s device number. After setting each DAQ/ DAQe/PXI-250x Series card, you can identify each card in the system with different device numbers. The default value of the Board ID is 0 and if you need to adjust it to another value, set the SW1 switch as shown in the table below.

![ON\nDIP\n1 2 3 4](.daq-daqe-pxi-250x-50m-12264-1000-10/e991a91065b129b850a7cf9d6c0ff94d7b7b3dd7f7773687de87365a09572258.jpg)

Figure 2-3: Board ID SW1 DIP Switch

<table><tr><td>SW1</td><td>Pin 1</td><td>Pin 2</td><td>Pin 3</td><td>Pin 4</td></tr><tr><td>Board ID</td><td>ID0</td><td>ID1</td><td>ID2</td><td>ID3</td></tr><tr><td>0</td><td>Off</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>1</td><td>On</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>2</td><td>Off</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>3</td><td>On</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>4</td><td>Off</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>5</td><td>On</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>6</td><td>Off</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>7</td><td>On</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>8</td><td>Off</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>9</td><td>On</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>10</td><td>Off</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>11</td><td>On</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>12</td><td>Off</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>13</td><td>On</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>14</td><td>Off</td><td>On</td><td>On</td><td>On</td></tr><tr><td>15</td><td>On</td><td>On</td><td>On</td><td>On</td></tr></table>

Table 2-1: Board ID SW1 DIP Switch Settings

![The image displays a white document icon with a folded top-right corner. Faint horizontal gray lines run across the lower portion of the document. A large, bold red checkmark is centered on the document.](.daq-daqe-pxi-250x-50m-12264-1000-10/5100af8fb0f495fb5586df3ade7898dd978ab914379d702646f936bacdb37a38.jpg)
NOTE:

Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K\_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select your Card Type and uncheck Ignore Board ID. See figure below.

![DAQ2000 Device Driver Configuration\nThis utility is used for the cards that will perform continuous AI, DI or DO operation\nCard Type: Daq2016\nDaq2010\nDaq2205\nDaq2206\nAI : Daq2005\nDaq2204\nAO : Daq2006\nDaq2501\nDaq2502\nDI : Daq2208\nDaq2213\nDO : Daq2214\nIgnore Board ID No Reset\nOK Apply Cancel](.daq-daqe-pxi-250x-50m-12264-1000-10/083189d442d7416c477cb94772475a8e53827c3fbd920326373d7dfd62023ea4.jpg)

Figure 2-4: Enable Board ID Configuration

# 2.4.2 DIO Initial Status (JP4)

The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below.

![Disabled\nJP4\nEnabled\nJP4](.daq-daqe-pxi-250x-50m-12264-1000-10/f9b4877a8192de40f51758dc312c66475966694d8a5ac3bc657ca34c0112e673.jpg)

# 2.5 PCI Configuration

# 1. Plug and Play:

As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system.

# 2. Configuration:

The board configuration is done on a board-by-board basis for all PCI boards on your system. Because configuration is controlled by the system and software, there is no jumper setting required for base-address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the sys-tem as new boards are added or removed.

# 3. Troubleshooting:

If your system doesn’t boot or if you experience erratic operation with your PCI board in place, it’s likely caused by an interrupt con-flict (perhaps the BIOS Setup is incorrectly configured). In general, the solution, once you determine it is not a simple oversight, is to consult the BIOS documentation that comes with your system.

# 3 Signal Connections

This chapter describes the connectors of the DAQ/DAQe/PXI-250x Series, and the signal connection between the DAQ/DAQe/ PXI-250x Series and external devices.

# 3.1 Connectors Pin Assignment

DAQ/DAQe/PXI-250x Series is equipped with two 68-pin VHDCItype connectors (AMP-787254-1). It is used for digital input / output, analog input / output, and timer/counter signals, etc. The pin assignments of the connectors are defined in the figures below.

<table><tr><td>AO_0</td><td>1</td><td>35</td><td>AGND</td></tr><tr><td>AO_1</td><td>2</td><td>36</td><td>AGND</td></tr><tr><td>AO_2</td><td>3</td><td>37</td><td>AGND</td></tr><tr><td>AO_3</td><td>4</td><td>38</td><td>AGND</td></tr><tr><td>AOEXTREF_A/AI_0</td><td>5</td><td>39</td><td>AGND</td></tr><tr><td>AI_1</td><td>6</td><td>40</td><td>AGND</td></tr><tr><td>EXTATRIG/AI_2</td><td>7</td><td>41</td><td>AGND</td></tr><tr><td>AOEXTREF_B/AI_3</td><td>8</td><td>42</td><td>AGND</td></tr><tr><td>AO_4/AI_4</td><td>9</td><td>43</td><td>AGND</td></tr><tr><td>AO_5/AI_5</td><td>10</td><td>44</td><td>AGND</td></tr><tr><td>AO_6/AI_6</td><td>11</td><td>45</td><td>AGND</td></tr><tr><td>AO_7/AI_7</td><td>12</td><td>46</td><td>AGND</td></tr><tr><td>AO_TRIG_OUTA</td><td>13</td><td>47</td><td>EXTWFTRG_A</td></tr><tr><td>AO_TRIG_OUTB</td><td>14</td><td>48</td><td>EXTWFTRG_B</td></tr><tr><td>GPTC1_SRC</td><td>15</td><td>49</td><td>VCC</td></tr><tr><td>GPTC0_SRC</td><td>16</td><td>50</td><td>DGND</td></tr><tr><td>GPTC0_GATE</td><td>17</td><td>51</td><td>GPTC1_GATE</td></tr><tr><td>GPTC0_OUT</td><td>18</td><td>52</td><td>GPTC1_OUT</td></tr><tr><td>GPTC0_UPDOWN</td><td>19</td><td>53</td><td>GPTC1_UPDOWN</td></tr><tr><td>RESERVED</td><td>20</td><td>54</td><td>DGND</td></tr><tr><td>AFI1</td><td>21</td><td>55</td><td>AFI0</td></tr></table>

Table 3-1: Connector CN1 pin assignment

<table><tr><td>PB7</td><td>22</td><td>56</td><td>PB6</td></tr><tr><td>PB5</td><td>23</td><td>57</td><td>PB4</td></tr><tr><td>PB3</td><td>24</td><td>58</td><td>PB2</td></tr><tr><td>PB1</td><td>25</td><td>59</td><td>PB0</td></tr><tr><td>PC7</td><td>26</td><td>60</td><td>PC6</td></tr><tr><td>PC5</td><td>27</td><td>61</td><td>PC4</td></tr><tr><td>DGND</td><td>28</td><td>62</td><td>DGND</td></tr><tr><td>PC3</td><td>29</td><td>63</td><td>PC2</td></tr><tr><td>PC1</td><td>30</td><td>64</td><td>PC0</td></tr><tr><td>PA7</td><td>31</td><td>65</td><td>PA6</td></tr><tr><td>PA5</td><td>32</td><td>66</td><td>PA4</td></tr><tr><td>PA3</td><td>33</td><td>67</td><td>PA2</td></tr><tr><td>PA1</td><td>34</td><td>68</td><td>PA0</td></tr></table>

Table 3-1: Connector CN1 pin assignment

Legend:

<table><tr><td>Pin #</td><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>1~4</td><td>AO_&lt;0..3&gt;</td><td>AGND</td><td>Output</td><td>Voltage output of DA channel&lt;0..3&gt;</td></tr><tr><td>5</td><td>AOEXTREF_A/AI_0</td><td>AGND</td><td>Input</td><td>External reference for AO channel&lt;0..3&gt; / AI input 2</td></tr><tr><td>6</td><td>AI_1</td><td>AGND</td><td>Input</td><td>AI input 0</td></tr><tr><td>7</td><td>EXTATRIG/AI_2</td><td>AGND</td><td>Input</td><td>External analog trigger / AI input 1</td></tr><tr><td>8</td><td>AOEXTREF_B/AI_3</td><td>AGND</td><td>Input</td><td>External reference for AO channel&lt;4..7&gt; / AI input 3</td></tr></table>

Table 3-2: Connector CN2 pin assignment

<table><tr><td>Pin #</td><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>9~12</td><td>AO_&lt;4..7&gt;/AI_&lt;4..7&gt;</td><td>AGND</td><td>Output/Input</td><td>Voltage output of DA channel &lt;4..7&gt; / AI channel &lt;4..7&gt;(only for DAQ-2501)</td></tr><tr><td>13,14</td><td>AO_TRIG_OUT_&lt;A,B&gt;</td><td>DGND</td><td>Output</td><td>AO trigger signal for channel &lt;0..3&gt;&lt;4..7&gt;</td></tr><tr><td>15,16</td><td>GPTC&lt;0,1&gt;_SRC</td><td>DGND</td><td>Input</td><td>Source of GPTC&lt;0,1&gt;</td></tr><tr><td>17,51</td><td>GPTC&lt;0,1&gt;_GATE</td><td>DGND</td><td>Input</td><td>Gate of GPTC&lt;0,1&gt;</td></tr><tr><td>18,52</td><td>GPTC&lt;0,1&gt;_OUT</td><td>DGND</td><td>Input</td><td>Output of GPTC&lt;0,1&gt;</td></tr><tr><td>19,53</td><td>GPTC&lt;0,1&gt;_UPDOWN</td><td>DGND</td><td>Input</td><td>Up/Down of GPTC&lt;0,1&gt;</td></tr><tr><td>20</td><td>RESERVED</td><td>----</td><td>----</td><td>Reserved Pin</td></tr><tr><td>21,55</td><td>AFI&lt;1,0&gt;</td><td>DGND</td><td>Input</td><td>Auxiliary Function Input</td></tr><tr><td>22,56,23,57,24,58,25,59</td><td>PB&lt;7,0&gt;</td><td>DGND</td><td>PIO</td><td>Programmable DIO of 8255 Port B</td></tr><tr><td>26,60,27,61,29,63,30,64</td><td>PC&lt;7,0&gt;</td><td>DGND</td><td>PIO</td><td>Programmable DIO of 8255 Port C</td></tr><tr><td>31,65,32,66,33,67,34,68</td><td>PA&lt;7,0&gt;</td><td>DGND</td><td>PIO</td><td>Programmable DIO of 8255 Port A</td></tr><tr><td>35~46</td><td>AGND</td><td>----</td><td>----</td><td>Analog ground</td></tr><tr><td>47,48</td><td>EXTWFTRIG_&lt;A,B&gt;</td><td>DGND</td><td>Input</td><td>External waveform trigger for AO channel &lt;0..3&gt; &lt;4..7&gt;</td></tr></table>

Table 3-2: Connector CN2 pin assignment

<table><tr><td>Pin #</td><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>49</td><td>VCC</td><td>DGND</td><td>Power (Output)</td><td>+5V Power Source</td></tr><tr><td>28,50,54,62</td><td>DGND</td><td>----</td><td>----</td><td>Digital ground</td></tr></table>

Table 3-2: Connector CN2 pin assignment

\*PIO means programmable I/O

<table><tr><td>SSI_TIMEBASE</td><td>1</td><td>2</td><td>DGND</td></tr><tr><td>SSI_ADCONV</td><td>3</td><td>4</td><td>DGND</td></tr><tr><td>SSI_DAWR</td><td>5</td><td>6</td><td>DGND</td></tr><tr><td>SSI_SCAN_START</td><td>7</td><td>8</td><td>DGND</td></tr><tr><td>RESERVED</td><td>9</td><td>10</td><td>DGND</td></tr><tr><td>SSI_AD_TRIG</td><td>11</td><td>12</td><td>DGND</td></tr><tr><td>SSI_DA_TRIG</td><td>13</td><td>14</td><td>DGND</td></tr><tr><td>RESERVED</td><td>15</td><td>16</td><td>DGND</td></tr><tr><td>RESERVED</td><td>17</td><td>18</td><td>DGND</td></tr><tr><td>RESERVED</td><td>19</td><td>20</td><td>DGND</td></tr></table>

Table 3-3: SSI connector pin assignment

SSI Connector Signal Description on PXI J2:

<table><tr><td>Sync. Signal</td><td>PXI J2 location</td><td>PXI Trigger Bus</td></tr><tr><td>SSI_TIMEBASE</td><td>B18</td><td>PXI_TRIG4</td></tr><tr><td>SSI_ADCONV</td><td>A16</td><td>PXI_TRIG1</td></tr><tr><td>SSI_SCAN_START</td><td>A18</td><td>PXI_TRIG3</td></tr><tr><td>SSI_AD_TRIG</td><td>C18</td><td>PXI_TRIG5</td></tr><tr><td>SSI_DAWR</td><td>A17</td><td>PXI_TRIG2</td></tr><tr><td>SSI_DA_START</td><td>B16</td><td>PXI_TRIG0</td></tr><tr><td>SSI_DA_TRIG</td><td>E18</td><td>PXI_TRIG6</td></tr></table>

Table 3-4: SSI Connector Pin Assignment on PXI J2

Legend:

<table><tr><td>SSI timing signal</td><td>Functionality</td></tr><tr><td>SSI_TIMEBASE</td><td>SSI master: send the TIMEBASE out SSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal.</td></tr><tr><td>SSI_ADCONV</td><td>SSI master: send the ADCONV out SSI slave: accept the SSI_ADCONV to replace the internal ADCONV signal.</td></tr><tr><td>SSI_SCAN_START</td><td>SSI master: send the SCAN_START out SSI slave: accept the SSI_SCAN_START to replace the internal SCAN_START signal.</td></tr><tr><td>SSI_AD_TRIG</td><td>SSI master: send the internal AD_TRIG out SSI slave: accept the SSI_AD_TRIG as the digital trigger signal.</td></tr><tr><td>SSI_DAWR</td><td>SSI master: send the DAWR out. SSI slave: accept the SSI_DAWR to replace the internal DAWR signal.</td></tr><tr><td>SSI_DA_TRIG</td><td>SSI master: send the DA_TRIG out. SSI slave: accept the SSI_DA_TRIG as the digital trigger signal.</td></tr></table>

Table 3-5: Legend of SSI connector

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# 4 Operation Theory

The operation theories of the DAQ/DAQe/PXI-250x Series are described in this chapter. The functions include A/D conversion, D/ A conversion, Digital I/O, and General Purpose Counter / Timer. This operation theory will help you understand how to configure and program the DAQ/DAQe/PXI-250x Series.

![Based on the provided image, here is an accurate and concise description of the block diagram:\n\n**Top Section**\n*   **Connector:** A horizontal arrow at the very top is labeled '68 pin Mini-SCSI Connector'.\n*   **DA Group:** Below the connector is a large block labeled vertically as 'DA Group A' and 'DA Group B'. Inside this block:\n    *   Four columns of stacked blocks are labeled 'OPA', '12-bit DAC', and 'LATCH'.\n    *   Below these columns are blocks labeled 'FIFO' and 'CPLD'.\n    *   To the left/bottom of the main DA columns are blocks labeled 'MUX', '14-bit ADC', 'Calibration', 'Analog Trigger', and 'EEPROM'.\n    *   Vertical arrows on the far left connect to this section, labeled 'EXT-WF/3155-EXC/EXC/External', '8255-24-Bit DID', and '24-Bit DIO / GTRIG2 / External Triggers'.\n\n**Middle Section**\n*   **Interface:** A horizontal arrow labeled 'Board to Board Interface' connects the top and bottom sections.\n*   **Central Logic Block:** A large square contains the following blocks:\n    *   **Top Row:** 'AD Control and Timing Logic', 'DAQ Bus Interface', 'DA Control and Trigger Logic', 'DA Interface FIFO'.\n    *   **Middle Row:** 'AD Control FIFO (for Data & Configuration)', 'DAQ 2000 Control and Trigger Logic', 'GEMIC0', 'GEMIC1'.\n    *   **Bottom Row:** 'Analog Trigger Logic', 'Daughter Board FIFO Interface', 'Local Bus Interface and DMA Logic', 'SSI 84/86 PFI'.\n*   **Peripheral Blocks & Connections:**\n    *   **Left:** Arrows point up labeled 'Daughter Board FIFO Interface', 'AD Control and Timing Logic', and 'Analog Trigger Logic'.\n    *   **Right:** Arrows point up labeled 'General Purpose Timer/Counter Signals', 'Programmable Function Inputs', 'DIO Bus PC', and 'Power'.\n    *   **Far Right:** A column of blocks includes '8SC65A', 'Power Circuit', 'SDC65A Power Control Logic Logic', and 'Logic Bus Interface'.\n\n**Bottom Section**\n*   **PCI Interface:** Below the central logic block are blocks labeled 'Local Bus Interface', 'PCI Bus Controller', and 'Universal PCI Interface'. A block labeled 'Configuration and Calibration EEPROM' is connected to the PCI Bus Controller.\n*   **Connections:** Arrows labeled 'DMA' and 'Local Bus Signals' connect the lower blocks to the rest of the diagram.\n*   **Bus:** A horizontal arrow at the bottom is labeled 'Universal 32-bit PCI Bus'.\n*   **System Sync:** A vertical arrow on the far right is labeled 'System Synchronization Interface'.](.daq-daqe-pxi-250x-50m-12264-1000-10/aa5eaf43551f9bbc339b97c4ea9fc675d92c32f2044386e577e2af55184fc18b.jpg)

Figure 4-1: DAQ/DAQe/PXI-250x Series Block Diagram

# 4.1 A/D Conversion

When using an A/D converter, users should know the properties of the signal to be measured. In addition, users should setup the A/D configurations, including scan channels, input range, and polarities.

The A/D acquisition is initiated by a trigger signal. The data acquisition will start once the trigger signal matches the trigger conditions. Converted data are queued into the FIFO buffer, and then transferred to the host PC's memory for further processing.

Two acquisition modes: Software Polling and Programmable Scan are described in the following sections, including the timing, trigger modes, trigger sources, and transfer methods.

# 4.1.1 DAQ/DAQe/PXI-250x Series AD Data Format

The data format of the acquired 14-bit A/D data is 2’s Complement coding. Table 4-1 and 4-2 lists the valid input ranges and the ideal transfer characteristics.

<table><tr><td>Description</td><td colspan="4">Bipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td></td></tr><tr><td>Least significant bit</td><td>1120.78uV</td><td>610.39uV</td><td>305.19uV</td><td>152.60uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>9.998779V</td><td>4.999389V</td><td>2.499694V</td><td>1.249847V</td><td>1FFF</td></tr><tr><td>Midscale +1LSB</td><td>1120.78uV</td><td>610.39uV</td><td>305.19uV</td><td>152.60uV</td><td>0001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0000</td></tr><tr><td>Midscale -1LSB</td><td>-1120.78uV</td><td>-610.39uV</td><td>-305.19uV</td><td>-152.60uV</td><td>3FFF</td></tr><tr><td>-FSR</td><td>-10V</td><td>-5V</td><td>-2.5V</td><td>-1.25V</td><td>2000</td></tr></table>

Table 4-1: Bipolar Input Range and Converted Digital Codes

<table><tr><td>Description</td><td colspan="4">Unipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>0V to 10V</td><td>0 to +5V</td><td>0 to +2.5V</td><td>0 to +1.25V</td><td></td></tr><tr><td>Least significant bit</td><td>610.39uV</td><td>305.19uV</td><td>152.60uV</td><td>76.3uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>4.999389V</td><td>2.499694V</td><td>1.249847V</td><td>1.249923V</td><td>1FFF</td></tr><tr><td>Midscale +1LSB</td><td>5.000611V</td><td>2.500306V</td><td>1.250153V</td><td>0.625076V</td><td>0001</td></tr><tr><td>Midscale</td><td>5V</td><td>2.5V</td><td>1.25V</td><td>625mV</td><td>0000</td></tr><tr><td>Midscale -1LSB</td><td>4.999389V</td><td>2.499694V</td><td>1.249847V</td><td>1.249923V</td><td>3FFF</td></tr><tr><td>-FSR</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>2000</td></tr></table>

Table 4-2: Unipolar Input Range and Converted Digital Codes

# 4.1.2 Software Polling

This is the easiest way to acquire a single A/D data. The A/D converter performs one conversion whenever the dedicated software command is executed. The software would poll the conversion status and read the A/D data back when it is available.

This method is suitable for applications that need to acquire A/D data in real time. In this mode, the timing of the A/D conversion is fully controlled by software. However, it would be difficult to maintain a fixed A/D sampling rate.

# 4.1.3 Programmable Scan

This method is suitable for applications that need to acquire A/D data at a precise and fixed rate. A scan is a group of multiple channel samples and the scan interval is defined by the SI\_counter. Likewise, the sample interval of the multiple channels is defined by the SI2\_counter. Please refer to Table 4-4 for more information.

DAQ/DAQe/PXI-250x Series can sample multiple channels in continuous/discontinuous ascending sequence. For example, users may program DAQ/DAQe/PXI-250x Series to perform a scan in the channel sequence of 1-2-4-1-2-4…

There are 3 Trigger Modes available in Programmable Scan. They are Post-Trigger, Delay-Trigger, Post/Delay-Trigger with Retrigger.

Please refer to Table 4-3 for a brief summary on Trigger Modes and their Trigger Sources.

<table><tr><td>Trigger Mode</td><td>Description</td><td>Trigger Sources</td></tr><tr><td>Post-Trigger</td><td>Perform a scan right after the trigger occurs.</td><td rowspan="3">Software Trigger Digital Trigger Analog Trigger SSI AD Trigger</td></tr><tr><td>Delay-Trigger</td><td>Scan delayed by the amount of time programmed after the trigger</td></tr><tr><td>Post/Delay-Trigger with Retrigger</td><td>Perform repeated scan while trigger occurs and it could be under Post-Trigger or De-lay-Trigger mode.</td></tr></table>

Table 4-3: Trigger Modes and Corresponding Trigger Sources

# 4.1.4 Scan Timing and Procedure

There are 4 counters that need to be specified prior to programmable scans:

<table><tr><td>Counter Name</td><td>Width</td><td>Description</td><td>Notes</td></tr><tr><td>SI_counter</td><td>24-bit</td><td>Scan Interval, which defines the interval between each scan.</td><td>Scan Interval = SI_counter / Time-base*</td></tr><tr><td>SI2_counter</td><td>24-bit</td><td>Sampling Interval, which defines the interval between each sampled channel.</td><td>Sampling Interval = SI2_counter / Timebase*</td></tr><tr><td>PSC_counter</td><td>24-bit</td><td>Post Scan Counts, which defines how many scans to be performed with re-spect to each trigger.</td><td></td></tr><tr><td>Delay_counter</td><td>16-bit</td><td>Define the delay time for scan after trigger.</td><td>Delay Time = (Delay_counter / Time-base*),Timebase*=40Mfor DAQ/DAQe/PXI-250x Series</td></tr></table>

Table 4-4: Summary of Counters for Programmable Scan

The relationship between counters and acquisition timing is illustrated in Figure 4-2.

3 Scans.4 Samples per scan

(PSC\_Counter=3)

(Scan acquisition is performed in ascending sequence for enabled channels)

![Trigger\nScan_start\nAD_conversion\nScan_in_progress\nAcquisition_in_progress\nCh0\nCh1\nCh2\nCh3\nCh0\nCh1\nCh2\nCh3\nCh0\nCh1\nCh2\nCh3\nSampling Interval t=\nSI2_COUNTER/TimeBase\nScan Interval T=\nSI_COUNTER/TimeBase](.daq-daqe-pxi-250x-50m-12264-1000-10/e50264750c933a1d70dce6d2fd710a7f707a51444faf8f294bd9fc04cd5554c3.jpg)

Figure 4-2: Timing for Scan

# Note:

1. The maximum A/D sampling rate is 400KHz for DAQ/DAQe/ PXI-250x Series therefore the minimum setting of SI2\_counter is 100.
2. The Scan Interval can not be smaller than the interval of data Sampling Interval multiple by the Number of channels per Scan, i.e.: SI\_counter >= SI2\_counter \* NumChan\_Counter.

# 4.1.5 Trigger Modes

# Post-Trigger Acquisition

Use post-trigger acquisition when users want to perform scans right after a trigger signal. The number of scans to be performed after the trigger signal is specified by the PSC\_counter, as illustrated in Figure 4.3. The total acquired data length = (number\_of\_channels\_enabled\_for\_scan\_acquisition) \* PSC\_counter.

# Delay Trigger Acquisition

Use delay trigger when users want to delay the scan after a trigger signal. The delay time is determined by the Delay\_counter, as shown in Figure 4-4.

The counter counts down on the rising edges of Delay\_counter clock source after the trigger signal. When the count reaches 0, DAQ/DAQE/PXI-250X SERIES starts to perform the scan. The acquired data length = (number\_of\_channels\_enabled\_for\_scan\_acquisition) \* PSC\_counter. The Delay\_counter clock source can be software selected from Internal 40MHz Timebase, external input (AFI-1), or General Purpose Timer/Counter Output 0/1.

# Post-Trigger or Delay-trigger Acquisition with Retrigger

Use post-trigger or delay-trigger acquisition with retrigger when users want to perform repeated scans with respect to the repeated triggers. Figure 4-5 illustrates an example. Two scans are performed after the first trigger signal, and then wait for the next trigger signal. When the trigger signal occurs, it performs 2 more scans.

When retrigger function is disabled, only one trigger signal would be accepted after retrigger.

Note: Retrigger signals asserted during scan process will be ignored.

![| Event               | Value |\n| ------------------- | ----- |\n| Trigger             | 4     |\n| Scan_start          | 3     |\n| AD_conversion       | 2     |\n| Scan_in_progress    | 1     |\n| Acquisition_in_progress | 0.5   |](.daq-daqe-pxi-250x-50m-12264-1000-10/9178c17e0c2e1689e0d3404c8957b321919336c45216c69de9095fbe1d279f81.jpg)

Figure 4-3: Post Trigger

(NumChan\_Counter=4.PSC\_Counter=3)
![Trigger\nScan_start\nAD_conversion\nScan in progress\nAcquisition_in_progress\nOperation start\nDelay until\nDelay_Counter\nreaches 0\nAcquired & stored data\n(3 scans)](.daq-daqe-pxi-250x-50m-12264-1000-10/0fe2c1f9df8d91cfba18456e9886f3acbd3e7e0e02e15359226449582ac58540.jpg)

Figure 4-4: Delay Trigger

![| Signal Type             | Value |\n| ----------------------- | ----- |\n| Trigger                 | 4     |\n| Scan_start              | 2     |\n| AD_conversion           | 3     |\n| Scan_in_progress        | 1     |\n| Acquisition_in_progress | 2     |](.daq-daqe-pxi-250x-50m-12264-1000-10/0613c0b4a6114e1db61c13739ba68813a09eaf8a514175e91c511b0a88d5e5bf.jpg)

Figure 4-5: Post Trigger with Retrigger

# 4.1.6 Bus-mastering DMA Data Transfer

In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on a PCI bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a user-defined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA.

The DMA transfer mode is very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a highlevel programming library for high speed DMA data acquisition, you convert through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA.

The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list.

In a multi-user or multitasking OS, like Windows or Linux, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the noncontinuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-6 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address cycle support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs.

![Based on the provided image, here is the description of the blocks and connections:\n\n**Labeled Blocks:**\n\n*   **Left Block:** Contains four rows: 'First PCI Address', 'First Dual Address', 'Transfer Size', 'Next Descriptor'.\n*   **Center Top Block:** Contains four rows: 'PCI Address', 'Dual Address', 'Transfer Size', 'Next Descriptor'.\n*   **Right Block:** Contains four rows: 'PCI Address', 'Dual Address', 'Transfer Size', 'Next Descriptor'.\n*   **Center Bottom Block:** Contains the text 'PCI Bus'.\n*   **Bottom Block:** Contains the text 'Local Memory (FIFO)'.\n\n**Connections:**\n\n*   An arrow points from the **Left Block** to the **Center Top Block**.\n*   An arrow points from the **Center Top Block** to the **Right Block**.\n*   A thick arrow points upward from the **Bottom Block** ('Local Memory (FIFO)') to the **Center Bottom Block** ('PCI Bus').\n*   A thick arrow points upward from the **Center Bottom Block** ('PCI Bus') to the **Center Top Block**.](.daq-daqe-pxi-250x-50m-12264-1000-10/395b3d95029611b67a98dda8258ff45a003740d7c879bce9950cc515d1b64000.jpg)

Figure 4-6: Linked List of PCI Address DMA Descriptors

In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multibuffered mode DMA.

# 4.2 D/A Conversion

DAQ/DAQe/PXI-250x Series offers flexible and versatile analog output scheme to fit users’ complex field applications. In order to take full advantages of DAQ/DAQe/PXI-250x Series, we suggest users carefully read the following con-tents.

# Architecture

There are up to 8-channel of 12-bit Digital-to-Analog Converter (DAC) available in the DAQ/DAQe/PXI-2502. Four D/A channels are packed into one D/A group, i.e., DAQ/DAQe/PXI-2502 contains two D/ A groups, and DAQ/DAQe/PXI-2501 has only one D/ A group.

![**Title:** D/A Group A\n\n**Labeled Blocks:**\n*   CPLD\n*   FIFO\n*   Latch (repeated four times)\n*   12 Bit DAC (repeated four times)\n*   OPA (repeated four times)\n*   Group A Ext. Ref. / Internal 10V Ref. (contained in one box)\n\n**External Labels/Inputs:**\n*   Carrier-to-daughter Interface\n*   Trigger Signal\n*   AOEXTREF_A (Pin# 5 on CN2)\n\n**Connections:**\n*   **Inputs:** Large grey arrows labeled 'Carrier-to-daughter Interface' point into the CPLD and FIFO blocks. An arrow labeled 'Trigger Signal' points into the CPLD.\n*   **Internal Flow:**\n    *   A vertical arrow points down from the **CPLD** to the **FIFO**.\n    *   A black line extends from the **CPLD** to the first (top) **Latch**.\n    *   Four thick grey arrows extend from the **FIFO** area to the four **Latch** blocks.\n*   **Signal Path:**\n    *   Horizontal arrows connect each **Latch** to its corresponding **12 Bit DAC**.\n    *   Horizontal arrows connect each **12 Bit DAC** to its corresponding **OPA**.\n    *   Dotted lines extend to the right from each **OPA**.\n*   **Reference:** A black line connects the bottom box (labeled 'Group A Ext. Ref.' and 'Internal 10V Ref.') upwards to the signal chain (likely connecting to the DACs or OPAs). The label 'AOEXTREF_A (Pin# 5 on CN2)' is positioned at the bottom right.](.daq-daqe-pxi-250x-50m-12264-1000-10/9ee4e13db4a0878daacc23aaabf145b8c34c920a5f5dc33ab91bb052b1c4e658.jpg)

Figure 4-7: Block Diagram of D/A Group

(Group B of DAQ/DAQE/PXI-2502 is identical to Group A shown above)

Figure 4-7 shows the D/A block diagram. DAC are controlled implicitly by CPLD and have their outputs updated only when digital codes for all enabled DA channels are ready and latched. This ensures D/A conversions to be synchronized for each channel in the same D/A group. Users can utilize this property to perform multi-channel waveform generation without any phase-lag.

# Hardware controlled Waveform Generation

FIFO is a hardware first-in first-out data queue, which holds temporary digital codes for D/A conversion. When DAQ/DAQe/PXI-250x Series operates in Waveform Generation mode, the waveform patterns are stored in FIFO, with 8K maximum samples. Waveform patterns larger than 8K are also supported by utilizing bus-mastering DMA transfer supported by PCI controller. Data format in FIFO is shown in Figure 4-8.

![This diagram depicts a data processing flow involving a FIFO buffer and channel assignment.\n\n**Main Block:**\nA large rectangular block is labeled **8K Samples Data FIFO**. Inside the top left of this block is the text **12-Bit DA Data in HEX Format**.\n\n**Data Sequence (Inside FIFO):**\nInside the FIFO block, there is a sequence of hex value boxes.\n*   **Left Sequence:** From left to right, the boxes contain **0FFF**, **0000**, **0100**, **0FFE**, **0001**, **0101**, **0FFD**, **0002**, **0102**.\n*   **Right Sequence:** After a dotted line, the boxes on the far right contain **0F00**, **00FF**, **01FF**.\n\n**Data Flow:**\n*   An arrow labeled **Data In** points into the rightmost box (**01FF**).\n*   An arrow labeled **Data Out** points left away from the leftmost box (**0FFF**).\n\n**Destination Channels:**\nBelow the FIFO block is a row of boxes labeled **Destination Channel**. Dashed arrows connect each hex data box to a channel box directly below it.\n*   **Left Sequence Channels:** Corresponding to the first set of data, the boxes contain **CH0**, **CH1**, **CH3**, **CH0**, **CH1**, **CH3**, **CH0**, **CH1**, **CH3**.\n*   **Right Sequence Channels:** After a dotted line, the boxes corresponding to the rightmost data contain **CH0**, **CH1**, **CH3**.](.daq-daqe-pxi-250x-50m-12264-1000-10/ef480a630f4bdf18a650f79645182b79679c1bd056809877b5f16eb41ef4d29a.jpg)

Note: 1) CH0, CH1, CH3 are used for Waveform Generation.
2) CH2 is disabled in this case.
3) FIFO Data are assigned to DAC in sequence: CH0,CH1,CH3.

Result

<table><tr><td>DA Channel</td><td>0</td></tr><tr><td>DA Channel</td><td>1</td></tr><tr><td>DA Channel</td><td>2</td></tr><tr><td>DA Channel</td><td>3</td></tr></table>

<table><tr><td>0FFF</td><td>0FFE</td><td>0FFD</td><td></td><td></td><td></td><td>...... Monotonically decreasing waveform ......</td><td></td><td></td><td></td><td>0F00</td></tr><tr><td>0000</td><td>0001</td><td>0002</td><td></td><td></td><td></td><td>...... Monotonically increasing waveform ......</td><td></td><td></td><td></td><td>00FF</td></tr><tr><td>X</td><td>X</td><td>X</td><td></td><td></td><td></td><td>...... Disabled ......</td><td></td><td></td><td></td><td>X</td></tr><tr><td>0100</td><td>0101</td><td>0102</td><td></td><td></td><td></td><td>...... Monotonically increasing waveform ......</td><td></td><td></td><td></td><td>01FF</td></tr></table>

Figure 4-8: Data Format in FIFO and Mapping

With hardware-based Waveform Generation, D/A conversions are updated automatically by CPLD rather than application software. Unlike the conventional Software-based Waveform Generation, the precise hardware timing control guarantees non-distorted waveform generation even when host CPU is under heavy loading. Detailed function setup will be explained in Section 4.2.2.

![A white document icon featuring faint horizontal lines, overlaid with a large, bold red checkmark.](.daq-daqe-pxi-250x-50m-12264-1000-10/72da45fc7479de4450b5636d1b0523bac7b045f28f6ef5c7c2a029a2afc3948b.jpg)
NOTE:

When using waveform generation mode, all the four DACs in the same D/A group must be configured for the same mode. However, any one of the DAC can be disabled. If users need to use the software update mode, they can use another D/A group on the DAQ/DAQe/PXI-2502.

# Setting up the DACs

Before using the DACs, users should setup the reference source and its polarity. Each DAC has its own reference and polarity settings. For example; the internal voltage reference of D/A Group A is tied to internal +10V, however, users can still connect external reference thru AOEXTREF (pin 5 on CN2), for example to a +3.3V voltage source. Therefore, each DAC in D/ A Group A has two reference options: 10V or 3.3V. However, DA update timing, trigger Source, and trigger/stop mode are all the same throughout that D/ A Group.

DAQ/DAQe/PXI-250x Series provides the capability to fine tune the voltage reference from the external source. The external reference is fed thru an on board calibrated circuit, with programmable offset. Users can utilize this capability to generate precise D/A outputs.

![The image displays a graphic icon of a document or checklist. It features a white sheet of paper with a folded top-right corner and horizontal lines suggesting text. A large, red checkmark is prominently displayed over the left side of the document.](.daq-daqe-pxi-250x-50m-12264-1000-10/a998080afe0af2323964939b77be37c85917e20506bba702206b2d830d7f1362.jpg)
NOTE:

The range of external voltage reference should be within ±10V.

# Utilizing Multiplying Characteristic of DACs

The D/A reference selection let users fully utilize the multiplying characteristics of the DACs. Digital codes sent to the D/A converters will be multiplied by the reference to generate output.

<table><tr><td rowspan="2">Magnitude</td><td>Bipolar</td><td colspan="2">Unipolar</td></tr><tr><td>Output</td><td>Output</td><td>Digital Code</td></tr><tr><td>FSR – LSB</td><td>+Vref * (2046 / 2048)</td><td>Vref * (4095 / 4096)</td><td>0FFF</td></tr><tr><td>Midscale + LSB</td><td>+Vref * (1 / 2048)</td><td>Vref * (2049 4096)</td><td>0801</td></tr><tr><td>Midscale</td><td>0</td><td>Vref * (2048 / 4096)</td><td>0800</td></tr><tr><td>Midscale – LSB</td><td>-Vref * (1 / 2048)</td><td>Vref * (2047 / 4096)</td><td>07FF</td></tr><tr><td>FSR + LSB</td><td>-Vref * (2046 / 2048)</td><td>Vref * (1 / 4096)</td><td>0001</td></tr><tr><td>-FSR</td><td>-Vref</td><td>0</td><td>0000</td></tr></table>

# Table 4-5: D/A Output Versus Digital Codes

The DAQ/DAQe/PXI-250x Series can generate standard and arbitrary functions, continuously or piece-wise. Appendix A demonstrates possible wave-form patterns generated by the DAQ/DAQe/ PXI-250x Series in combination with various counters, clock sources, and voltage references.

# Software Update

This method is suitable for applications that need to generate D/A output controlled by user programs. In this mode, the D/A converter generates one output once the software command is issued. However, it would be difficult to determine the software update rate under a multi-task OS like Windows.

# Waveform Generation

This method is suitable for applications that need to generate waveforms at a precise and fixed rate. Various programmable counters will facilitate users to generate complex waveforms with great flexibility.

There are three event signals involved in Waveform Generation: Start, DAWR (DA WRite), and Stop. Please refer to Table 4.2.2 for a brief summary on Waveform Generation Events and their corresponding Trigger Sources.

For more information on Trigger Mode, Stop Mode, Time-base, and Trigger Sources, please refer to sections 4.2, 4.1, and 4.5, respectively.

<table><tr><td>Signal</td><td>Descriptions</td><td>Valid Sources</td></tr><tr><td>Start</td><td>Start Waveform Generation process.</td><td>Software Trigger Ext. Digital Trigger Analog Trigger SSI Trigger</td></tr><tr><td>DAWR</td><td>Write data to the DAC on the fal-ling edges of DAWR.</td><td>Internal Update External Update SSI Update</td></tr><tr><td>Stop</td><td>Stop Waveform Generation</td><td>Software Trigger Ext. Digital Trigger Analog Trigger</td></tr></table>

Table 4-6: Trigger Signals and Corresponding Signal Sources

# Waveform Generation Timing

Six counters interact with the waveform to generate different DAWR timing, thus forming different waveforms. They are described in Table 4-7.

<table><tr><td>Counter Name</td><td>Width</td><td>Description</td><td>Note</td></tr><tr><td>UI_counter</td><td>24-bit</td><td>Update Interval, which defines the update interval between each data output.</td><td>Update Interval = UI_counter / Time-base*.</td></tr><tr><td>UC_counter</td><td>24-bit</td><td>Update Counts, which defines the number of data in a waveform.</td><td>When value in UC_counter is smaller than the size of waveform patterns, the waveform is generated piece-wisely.</td></tr><tr><td>IC_counter</td><td>16-bit</td><td>Iteration Counts, which defines how many times the waveform is generated.</td><td></td></tr></table>

Table 4-7: Summary of Counters for Waveform Generation

<table><tr><td>DLY1_counter</td><td>16-bit</td><td>Define the delay time for waveform generation after the trigger signal.</td><td>Delay Time = (DLY1_counter / Clock Timebase)</td></tr><tr><td>DLY2_counter</td><td>16-bit</td><td>Define the delay time to separate consecutive waveform generation. Effective only in Iterative Waveform Generation mode.</td><td>Delay Time = (DLY2_counter / Clock Timebase)</td></tr><tr><td>Trig_counter</td><td>16-bit</td><td>Define the acceptable start trigger count when re-trigger function is enabled</td><td>Timebase*= 40M for DAQ/DAQe/PXI-250x Series</td></tr></table>

Table 4-7: Summary of Counters for Waveform Generation

![The image displays a white document icon with a folded upper-right corner. A large red checkmark is superimposed diagonally across the center of the document. Faint horizontal lines representing text are visible on the white background of the paper.](.daq-daqe-pxi-250x-50m-12264-1000-10/439f4322d8185b386f733cb7a5cae51a927d1b98ce180353cde6d7a52b0076b6.jpg)
NOTE:

The maximum D/A update rate is 1MHz. Therefore the minimum setting of UI\_counter is 40.

![4 update counts, 3 iterations\n(UC Counter=4, IC Counter=3)\nTrigger\nUC Counter=4\nDAWR\nWFG_in_progress\nDelay until\nDLY1 Counter\nreaches 0\nDelay until\nDLY2 Counter\nreaches 0\nDelay until\nDLY2 Counter\nreaches 0\nDA update_interval t=\nUI Counter/Timebase\nOutput Waveform\nOperation start\nn\n-4\nA single waveform\nIC Counter = 3](.daq-daqe-pxi-250x-50m-12264-1000-10/9b6222199392f50b79cae43c7d3b0bd80a3b935a0e8ce6edfddbfefedb887637.jpg)

Figure 4-9: Typical D/A timing of waveform generation

(Assuming the data in the data buffer are 2V, 4V, -4V, 0V)

# Trigger Modes

Post-Trigger Generation

Use post-trigger generation when users want to generate waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC\_counter\* IC\_counter, as illustrated in Figure 4-9

# Delay-Trigger Generation

Use delay-trigger when users want to delay the waveform generation after the trigger signal. The delay time is determined by DLY1\_counter, as shown in Figure 4-10.

The counter counts down on the rising edges of DLY1\_counter clock source after the start trigger signal. When the count reaches zero, DAQ/DAQe/PXI-250x Series starts to generate the waveform. The DLY1\_counter clock source can be software selected from the Internal 40MHz Timebase, external clock input (AFI-0), or GPTC output 0/1.

# Post-Trigger or Delay-Trigger with Retrigger

Use post-trigger or delay-trigger with retrigger when users want to generate multiple waveforms with respect to multiple incoming trigger signals. Users can set Trig\_counter to specify the number of acceptable trigger signals.

Figure 4-11 illustrates an example. Two waveforms are generated after the first trigger signal (Iterative Waveform Generation is used in this example, please refer to Section 4.2 for details). The board then waits for another trigger signal. When the next trigger signal is asserted, the board generates two more waveforms. After three trigger signals, as specified in Trig\_Counter, no more triggers signals will be accepted unless software trig- ger reset command is executed.

![This image features a digital icon representing a document or file. It depicts a white rectangular sheet of paper with a folded upper-right corner. Faint grey horizontal lines run across the page, simulating text. Superimposed over the center of the document is a large, bold red checkmark (or tick mark).](.daq-daqe-pxi-250x-50m-12264-1000-10/70e6e06c94dcaa3e856165230e068d53db1a43fc89fb945e889673b871f3e015.jpg)
NOTE:

Start Trigger signals asserted during waveform generation process will be ignored.

![| Signal             | Value |\n| ------------------ | ----- |\n| Trigger            | 8     |\n| DAWR               | 8     |\n| WFG_in_progress    | 8     |\n| Output Waveform    | 4     |](.daq-daqe-pxi-250x-50m-12264-1000-10/d4b414b0044d157b41c1b814ed8f30590ee458a1b8ddfea4c65f6962461d4ff7.jpg)

Figure 4-10: Post-Trigger Generation

![| Signal             | Value |\n| ------------------ | ----- |\n| Trigger            | High  |\n| DAWR               | Low   |\n| WFG_in_progress    | Low   |\n| Output Waveform    | Low   |\n| Delay until DLY1_counter reaches 0 | 0     |](.daq-daqe-pxi-250x-50m-12264-1000-10/8dee2f6feee3e9a3b99220960bd3d70cb5bf1973a946e3c49fc4234afba6af72.jpg)

Figure 4-11: Delay-Trigger Generation

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 1     |\n| WFG_in_progress | 4     |\n| Output Waveform | 2     |](.daq-daqe-pxi-250x-50m-12264-1000-10/cccaa1f47dea57685649f1b9af356a163fbd7fc523c488d02f65dafb991b8a33.jpg)

Figure 4-12: Post-Trigger with Retrigger Generation

# Iterative Waveform Generation

Users can set IC\_counter to generate iterative waveforms, no matter which Trigger Mode is used. The IC\_counter stores the iteration number. Examples are shown in Figure 4-13 and 4-14.

When IC\_counter is disabled, the waveform generation will not stop until a stop trigger is asserted. For Stop Mode, please refer to Section 4.2 for details.

An on-board data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host PC’s memory, the data in FIFO will be re-used when a single waveform generation is completed. In other words, it won’t occupy the PCI bandwidth afterwards. How- ever, if the size of a single waveform were larger than that of the FIFO, it needs to be intermittently loaded from the host PC’s memory via DMA, thus PCI bandwidth would be occupied.

If the value specified in UC\_counter is smaller than the sample size of the waveform patterns, the waveform will be generated piece-wisely. For example, if users defined a 16-sample sine wave and set the UC\_counter to 2, the generated waveform will be a 1/ 8-cycle sine wave for every waveform period. In other words, a complete sine wave will be generated for every 8-iterations. If value specified in UC\_counter is larger than the sample size of waveform LUT, say, 32; the generated waveform will be a 2-cycle sine wave for every waveform period.

In conjunction with different trigger modes and counter setups, users can manipulate a single waveform to generate different, more complex waveforms. For more information, please refer to Appendix A.

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WFG_in_progress | 2     |\n| Output Waveform | 2     |](.daq-daqe-pxi-250x-50m-12264-1000-10/e6be287910ded66fc43e2a1f380b119e2959b40cb21c723f943ed1a124a81ce2.jpg)

Figure 4-13: Finite iterative waveform generation w/Post-trigger

(Assuming the digital codes in the FIFO are 2V, 4V, 2V, 0V)

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WFG_in_progress | 4     |\n| Output Waveform | 2     |\n| Operation start | n     |](.daq-daqe-pxi-250x-50m-12264-1000-10/c99f46da8fc5cb61886bf96b0b7889b70d6f9c3649e1b5def8465550793a4fad.jpg)

Figure 4-14: Infinite iterative waveform generation w/Post-trigger

(Assuming the digital codes in the FIFO are 2V, 4V, 2V, 0V)

DLY2\_Counter in iterative Waveform Generation

To expand the flexibility of Iterative Waveform Generation, DLY2\_counter was implemented to separate consecutive waveform generations.

The DLY2\_counter starts counting down right after a single waveform generation is completed. When it reaches zero, the next iteration of waveform generation will start as shown in Figure 4.2.3. If users are generating waveform piece-wisely, the next piece of waveform will be generated. The DLY2\_counter clock source can be software selected from Internal 40MHz Timebase, external clock input (AFI-0), or GPTC output 0/1.

# Stop Modes

Users can stop waveform generation while it is still in progress, either by hardware or software trigger. The stop trigger sources can be software selected from Internal software trigger, external digital trigger (AFI-0/1), or analog trigger. Three stop modes are provided to stop finite or infinite waveform generation.

Stop Mode I

After a mode I stop trigger is asserted, the waveform generation stops immediately. Figure 4-15 illustrates an example.

Stop Mode II

After a mode II stop trigger is asserted, the waveform generation continues to generate a complete waveform then stops the operation. Take Figure 4-16 as an example. Since UC\_counter is set to 4, the total generated data points must be a multiple of 4.

Users can check WFG\_in\_progress (waveform generation in progress) status by software read-back to confirm the stop of a waveform generation.

Stop Mode III

After a mode III stop trigger is asserted, the waveform generation continues until the iterative number of waveforms specified in IC\_Counter is completed. Take Figure 4-17 for example. Since IC\_Counter is set to 3, the total generated waveforms must be a multiple of 3.

Users can check WFG\_in\_progress (waveform generation in progress) status by software read-back to confirm the stop of a waveform generation.

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WFG_in_progress | 4     |\n| Output Waveform | 4     |](.daq-daqe-pxi-250x-50m-12264-1000-10/b66d57d2dfd534f3f597b0cd521f6d2e8d5ebf725a3bae35e3c49b79d75e238b.jpg)

Figure 4-15: Stop mode I

(Assuming the data in the data buffer are 2V, 4V, 2V, 0V)

![| Event               | Value |\n| ------------------- | ----- |\n| Trigger             | 4     |\n| DAWR                | 4     |\n| WFG_in_progress     | 4     |\n| Output Waveform     | 4     |](.daq-daqe-pxi-250x-50m-12264-1000-10/dda9841d9bf2561179b9c1802617e0fccde400deb803293db21a6e6ffe4cbbc6.jpg)

Figure 4-16: Stop mode II

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WFG_in_progress | 4     |\n| Output Waveform | 4     |](.daq-daqe-pxi-250x-50m-12264-1000-10/c59534bc2354550d2a5db9ba8db7ff7410ec35d3b17003883021cd3a431403af.jpg)

Figure 4-17: Stop mode III

# 4.3 General Purpose Digital I/O

DAQ/DAQE/PXI-250x Series provides 24-line general-purpose digital I/ O (GPIO) through a 82C55A chip.

The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be individually programmed to be either inputs or outputs. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs.

For more information on programmable I/O chip 82C55A, please refer to http://www.intel.com.

# 4.4 General Purpose Timer/Counter Operation

Two independent 16-bit up/down timer/counter are embedded in FPGA firmware for users applications. They have the following features:

 Direction of counting can be controlled via hardware or software.
 Selectable counter clock source from either internal or external clock up to 10MHz.
 Programmable gate selection.
 Programmable input and output signal polarities, either active-high or active-low.
 Initial Count can be loaded via software
 Current count value can be read-back by software without affecting circuit operation

# 4.4.1 Timer/Counter functions basics

Each timer/counter has three inputs that can be controlled via hardware or software. They are clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UPDOWN).

The GPTC\_CLK input acts as a clock source to the timer/counter. Active edges on the GPTC\_CLK input increment or decrement the counter. The GPTC\_UPDOWN input determines whether the counter’s counting-up or counting-down. The GPTC\_GATE input is a control line, which acts as a counter enable or a counter trigger signal in different modes.

The output of timer/counter is GPTC\_OUT. After power-up, GPTC\_OUT is pulled high by a 10K resistor. GPTC\_OUT goes low after the DAQ board is initialized.

All the polarities of input/output signals can be programmed via software. In this chapter, all timing figures assume that GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT are set to be positive-logic. (i.e. they’re triggered on the rising-edge)

# 4.4.2 General Purpose Timer/Counter modes

Eight programmable timer/counter modes are provided. All modes start operations following the software start command. The GPTC software reset command initializes the status of the counter and re-loads the initial value to the counter.

# Mode 1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the GPTC\_CLK after the software start. Initial count value can be loaded via software. Current count value can be read-back by software at any time. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-18 illustrates the operation with initial count = 5 in down-counting mode.

![| Signal | Value |\n|--------|-------|\n| Gate   | 5     |\n| CLK    | 5     |\n| Count value | 5    |\n| Count value | 4     |\n| Count value | 3     |\n| Count value | 2     |\n| Count value | 1     |\n| Count value | 0     |](.daq-daqe-pxi-250x-50m-12264-1000-10/31dc9ce2c737b5edfeacc09c0eb96eec2038eda88b7db4e241586dc4b1c880d4.jpg)

Figure 4-18: Mode 1 Operation

# Mode 2: Single Period Measurement

In this mode, the counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded via software. After the software start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period measurement, GPTC\_OUT outputs high and current count value can be read-back by software. Figure 4-19 illustrates the operation where initial count = 0, up-counting mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-250x-50m-12264-1000-10/aa0036c47be5afd3691dd7e6e9a801bb1c8b11fd2d42d1be1b3f8d1a3486c474.jpg)

Figure 4-19: Mode 2 Operation

# Mode 3: Single Pulse-width Measurement

In this mode, the counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded via software. After the software start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is active. GPTC\_OUT outputs high, and current count value can be read-back via software after the completion of the pulse-width measurement. Figure 4-20 illustrates the operation where initial count = 0 in up-counting mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.daq-daqe-pxi-250x-50m-12264-1000-10/3bd02ac3bf1ff2e7f62f77abe5dfda9aa5044974b8678ff56bb7d0fdea40f1f1.jpg)

Figure 4-20: Mode 3 Operation

# Mode 4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay and programmable pulse-width following the software start. These software programmable parameters could be specified in terms of periods of the GPTC\_CLK. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the counting. Figure 4-20 il-lustrates the generation of a single pulse with pulse-delay of two and pulse-width of four

![The image displays a digital timing diagram with four signal traces labeled on the left: 'Gate', 'CLK', 'Count value', and 'OUT'.\n\nAt the top, the text '**Software start**' is centered above a vertical dashed line.\n\nThe signals are depicted as follows:\n*   **Gate:** A signal line that is high, briefly pulses low, and then returns high.\n*   **CLK:** A continuous square wave clock signal.\n*   **Count value:** A sequence of numbers displayed below the clock line: **2**, **3**, **1**, **0**, **3**, **2**, **2**, **1**, **0**. The vertical dashed line intersects the second clock pulse and aligns with the number **3**.\n*   **OUT:** A signal that starts low, goes high when the count value reaches the first **0**, remains high through the subsequent counts, and goes low when the count value reaches the final **0**.](.daq-daqe-pxi-250x-50m-12264-1000-10/077674d46111b7e3944c595d59c08427c36dbc9f594a605ba9d82004be97472f.jpg)
Figure 4-21: Mode 4 Operation

# Mode 5: Single Triggered Pulse Generation

This function generates a single pulse with programmable delay and programmable pulse-width following an active GPTC\_GATE edge. These software programmable parameters can be specified in terms of periods of the GPTC\_CLK input. Once the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until the software start is re-executed. Figure 4-22 illustrates the generation of a single pulse with pulse delay of two and pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 1     |\n| CLK        | 2     |\n| Count value| 2     |\n| OUT        | 1     |](.daq-daqe-pxi-250x-50m-12264-1000-10/9d8f20323900f4e0c73571af68224e908fafe6b92852d16a2532a98d613a9cc9.jpg)

Figure 4-22: Mode 5 Operation

# Mode 6: Re-triggered Single Pulse Generation

This mode is similar to mode 5 except that the counter generates a pulse following every active edge on GPTC\_GATE. After the software start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE trigger that occurs during the pulse generation would be ignored. Figure 4-23 illustrates the generation of two pulses with pulse delay of two and pulse-width of four.

![Software start\nGate\nClosed\nCount value 2 2 1 0 3 2 1 0 2 2 1 0 3 2 1 0 2 2\nOUT\nIgnored](.daq-daqe-pxi-250x-50m-12264-1000-10/7b4f46dfe791b89b2187685e78adf0db6ba36998f8cfce3b353606fce387fbf7.jpg)

Figure 4-23: Mode 6 Operation

# Mode 7: Single Triggered Continuous Pulse Generation

This mode is similar to mode 5, except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. Once the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until the software start is re-executed. Figure 4-24 illustrates the generation of two pulses with pulse delay of four and pulse-width of three.

![Software start\nGate\nCLK\nCount value 4 + + 3 2 1 0 2 1 0 3 2 1 0 2 1 0 3 2\nOUT](.daq-daqe-pxi-250x-50m-12264-1000-10/e59aa8f992f4820379be17d704f5cc0c66b9d7fd89adf78d81009c4a40dc853f.jpg)

Figure 4-24: Mode 7 Operation

# Mode 8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse interval and pulse-width following the software start. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-25 illustrates the generation of two pulses with pulse delay of four and pulse-width of three

![Software start\nGate\nCLK\nCount value 4 + 3 3 2 1 0 2 1 0 3 2 1 0 2 1 1 0 3\nOUT](.daq-daqe-pxi-250x-50m-12264-1000-10/cd4bb15dcb42e607c0d52a63301aeec8d112ef1dc64c38fffa1aef372ba4012d.jpg)

Figure 4-25: Mode 8 Operation

# 4.5 Trigger Sources

We provide flexible trigger selections in DAQ/DAQE/PXI-250x Series. In addition to software trigger, DAQ/DAQE/PXI-250x Series also supports external analog and digital triggers. Users can configure the trigger source for A/D and D/A processes individually via software. Note that the A/D and the D/A conversion share the same analog trigger.

# 4.5.1 Software-Trigger

This trigger mode does not need any external trigger source. The trigger asserts right after users execute the specified function call. A/D and D/A processes can receive an individual software trigger.

# 4.5.2 External Analog Trigger

The analog trigger circuitry routing is shown in the Figure 4.5.1. The analog multiplexer selects either a direct analog input from the EXTATRIG pin (SRC1 in Figure 4-25) on the 68-pin connector CN1 or the input signal of ADC (SRC2 in Figure 4-25). The range of trigger level for SRC1 is ±10V and the resolution is 78mV (please refer to Table 4-8), while the trigger range of SRC2 is the full-scale range of AD input, and the resolution is the desired range divided by 256.

![Based on the provided block diagram, here is an accurate and concise description:\n\n**Labeled Blocks:**\n*   **Input Multiplexer**\n*   **Instrumentation Amplifier** (represented by a triangle)\n*   **A/D Converter**\n*   **MUX**\n*   **Analog Trigger Circuit**\n\n**Connections and Signal Flow:**\n*   **CN1**: A vertical bar labeled **CN1** at the top.\n*   **Aln**: Five arrows labeled **Aln** point from the left into the **Input Multiplexer**.\n*   **Input Multiplexer** connects to the **Instrumentation Amplifier**.\n*   **Instrumentation Amplifier** connects to the **A/D Converter**.\n*   A line drops down from the **Instrumentation Amplifier**, labeled **SRC2**, and connects to the **MUX**.\n*   A line labeled **EXT TRIG** at the bottom left runs horizontally to the right, labeled **SRC1** as it connects to the **MUX**.\n*   The **MUX** connects to the **Analog Trigger Circuit**.\n*   The **Analog Trigger Circuit** outputs a pulse signal (depicted as a square wave) and an arrow pointing to the right.](.daq-daqe-pxi-250x-50m-12264-1000-10/761d3108ad8d2f5a66e1611838fe526162c64a15fa446461cd49fa4e7f1b1d19.jpg)

Figure 4-26: Analog trigger block diagram

<table><tr><td>Trigger Level digital setting</td><td>Trigger voltage</td></tr><tr><td>0xFF</td><td>9.92V</td></tr><tr><td>0xFE</td><td>9.84V</td></tr><tr><td>---</td><td>---</td></tr><tr><td>0x81</td><td>0.08V</td></tr><tr><td>0x80</td><td>0</td></tr><tr><td>0x7F</td><td>-0.08V</td></tr><tr><td>---</td><td>---</td></tr><tr><td>0x01</td><td>-9.92V</td></tr><tr><td>0x00</td><td>-10V</td></tr></table>

Table 4-8: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic

The trigger signal asserts when an analog trigger condition is meet. There are five analog trigger conditions in DAQ/DAQE/PXI-250x Series. DAQ/DAQE/PXI-250x Series uses 2 threshold voltages: Low\_Threshold and High\_Threshold to compose 5 different trigger conditions. Users can con-figure the trigger conditions easily via software.

# Below-Low analog trigger condition

Figure 4-27 shows the below-low analog trigger condition, the trigger signal asserts when the input analog signal is lower than the Low\_Threshold voltage. High\_Threshold setting is not used in this trigger condition.

![Low Threshold\nTrigger](.daq-daqe-pxi-250x-50m-12264-1000-10/6b05f56fc987f1c5ebacc0cbd612a3d6a3a4ea13d9fc3d68099ba93513436a92.jpg)

Figure 4-27: Below-Low analog trigger condition

# Above-High analog trigger condition

Figure 4-28 shows the above-high analog trigger condition, the trigger signal asserts when the input analog signal is higher than the High\_Threshold voltage. The Low\_Threshold setting is not used in this trigger condition.

![| Time Segment | Value |\n| ------------ | ----- |\n| High_Threshold | High_Threshold |\n| Trigger      | Trigger (labeled) |](.daq-daqe-pxi-250x-50m-12264-1000-10/44e03032af8d6d10cd5d9815a5e3da7ebc568c20b31f161c11b8988fd6cae024.jpg)

Figure 4-28: Above-High analog trigger condition

Figure 4-29 shows the inside-region analog trigger condition, the trigger signal asserts when the input analog signal level falls in the range between the High\_Threshold and the Low\_Threshold voltages.

![| Time Segment | High_Threshold | Low_Threshold |\n| ------------ | ------------- | ------------ |\n| Trigger      | Low           | High         |](.daq-daqe-pxi-250x-50m-12264-1000-10/a28f7b83c302106ba80ced46688c60b4bedf45fc91dd154e55935d92e8363c28.jpg)

Figure 4-29: Inside-Region analog trigger condition

# High-Hysteresis analog trigger condition

Figure 4-30 shows the high-hysteresis analog trigger condition, the trigger signal asserts when the input analog signal level is higher than the High\_Threshold voltage, where the hysteresis region is determined by the Low\_Threshold voltage.

![| Level          | Value |\n| -------------- | ----- |\n| Trigger        | Low   |\n| High_Threshold | High  |](.daq-daqe-pxi-250x-50m-12264-1000-10/0082976858e4f0efe95ffd58301320a90bc27a51726c941cccb2a3429315be2c.jpg)

Figure 4-30: High-Hysteresis analog trigger condition

# Low-Hysteresis analog trigger condition

Figure 4-30 shows the low-hysteresis analog trigger condition, the trigger signal asserts when the input analog signal level is lower than the Low\_Threshold voltage, where the hysteresis region is determined by the High\_Threshold voltage.

![| Trigger | High_Threshold | Low_Threshold |\n| ------- | -------------- | ------------- |\n| Low     | Peak           | Low           |\n| High    | Peak           | Peak          |](.daq-daqe-pxi-250x-50m-12264-1000-10/6cfd2ce3023d5f18e6f886b59207804216493cd428d053c3aa0fb4fd06d45f88.jpg)

Figure 4-31: Low-Hysteresis analog trigger condition

# 4.6 Timing Signals

In order to meet the requirements for user-specific timing or synchronizing multiple boards, DAQ/DAQE/PXI-250x Series provides a flexible interface for connecting timing signals with external circuitry or other boards. The DAQ timing of the DAQ/DAQE/PXI-250x Series is composed of a bunch of counters and trigger signals in the FPGA on board.

There are 7 timing signals related to the DAQ timing, which in turn influence the A/D, D/A process, and GPTC operation. These signals are fed through the Auxiliary Function Inputs pins (AFI) or the System Synchronization Interface bus (SSI). We implemented a multiplexer in the FPGA to select the desired timing signal from these inputs, as shown in the Figure 4-32.

Users can use the SSI to achieve synchronization between multiple boards, or use the AFI to derive timing signals from an external timing circuit.

![The diagram illustrates a signal routing process involving four labeled blocks and a central switching component.\n\n**Labeled Blocks:**\n*   **Top Left:** A block containing the text 'Internal tim ing' on the first line and 'signals' on the second line.\n*   **Middle Left:** A block containing the text 'SSI tim ing signals'.\n*   **Bottom Left:** A block containing the text 'AFI tim ing signals'.\n*   **Right:** A block containing the text 'DA Q tim ing signals'.\n\n**Connections:**\n*   **Inputs:** Multiple parallel horizontal lines connect each of the three left-hand blocks ('Internal tim ing signals', 'SSI tim ing signals', and 'AFI tim ing signals') to the left side of a large, vertical trapezoidal shape in the center.\n*   **Output:** Multiple parallel horizontal lines connect the right side of the central trapezoidal shape to the single block on the right ('DA Q tim ing signals').](.daq-daqe-pxi-250x-50m-12264-1000-10/fc3ab0f5aaf043035c396ec41831048cd27cb0ca132714dc2b93abe4b0c33172.jpg)

Figure 4-32: DAQ signals routing

# 4.6.1 System Synchronization Interface

SSI uses bi-directional I/O to provide flexible connections between boards. You can choose each of the 7 timing signals and which board to be the SSI master. The SSI master can drive the timing signals of the slaves. Users can thus achieve better synchronization between boards.

Note that when power-up or reset, the DAQ board is reset to using its internal timing signals.

# 5 Calibration

This chapter introduces the calibration process to minimize AD measurement errors and DA output errors.

DAQ/DAQE/PXI-250x Series is factory calibrated before shipment. The onboard high precision band-gap voltage reference together with TrimDAC compensates for unwanted offsets and gain errors, caused by environment variation or component aging.

# 5.1 Auto-calibration

The auto-calibration feature of DAQ/DAQE/PXI-250x Series facilitates users completing a calibration process, without the necessities for any external voltage references or measurement devices.

The onboard auto-calibration circuitry is composed of a precision band-gap voltage reference, an ADC and a TrimDAC. TrimDAC is a multi-channel DAC that generates DC offsets that counteract the offsets from the main DACs. Digital codes for the TrimDAC, as well as the temperature and the date of the calibration, are stored in the onboard EEPROM. We do not recommend end-users to adjust the onboard band-gap voltage reference in anyway, unless an ultra-precision calibrator is available.

Due to temperature, humidity variations, and component aging, the precision of DAQ board may degrade over time. It is suggested that users periodically calibrate the DAQ board. The user calibration constants can also be stored in the onboard EEPROM.

# Note:

1. Before auto-calibration procedure starts, it is recommended to warn up the card for at least 15 minutes.

2. Please remove the cable before an auto-calibration procedure is initiated because the DA outputs would be changed in the process of calibration.

# 5.2 Saving Calibration Constants

An onboard EEPROM is used to store calibration constants. In addition to a default bank that stores factory calibration constants, there are three user banks. Users can save the subsequently performed calibration constants in anyone of these user banks. ADLINK provides software for users to save calibration constants in an easy manner.

# 5.3 Loading Calibration Constants

Users can calibrate DAQ board in three sites and store the calibration constants into different user banks. When moving DAQ board from one site to another, users can load the calibration constants without re-calibration. ADLINK provides software for users to load calibration constants in an easy manner.

# Appendix A Waveform Generation Demonstration

Combined with 6 counters, selectable trigger sources, external reference sources, and time base, DAQ/DAQE/PXI-250x Series provides the capabilities to generate complex waveforms. Various modes shown below can be mixed together to generate waveforms that are even more complex.

Although users can always load a new waveform to generate any desired waveform, we suggest using hardware capabilities to maximize both efficiency and flexibility.

<table><tr><td colspan="2">Standard Function</td></tr><tr><td>&lt;img src="images/c82d5344b66e0798d43a76d28a7804c4323bccccc8d901ea27a134604d820871.jpg"/&gt;</td><td>Waveforms including sine wave, triangular wave, saw wave, ramp, etc., can be converted to Waveform LUT. Using larger waveform means trading maxi-mum output rate for lower harmonic distortion.</td></tr><tr><td colspan="2">Arbitrary Function</td></tr><tr><td>&lt;img src="images/3d13588d2689261b44547bb66f5284e32f9bb30383ff684fcaa4f47b69e773f8.jpg"/&gt;</td><td>User defined arbitrary function without size limit can be generated. Users can also concatenate various standard functions of same length into one arbitrary function and setup piece-wise generation, so each standard function can be generated in sequence, with a user definable intermediate space.</td></tr><tr><td colspan="2">Standard Function w. Frequency Variant</td></tr><tr><td>&lt;img src="images/f5bb5b76d8e8504837e9f956e5c436feff61f55d7cd5e9d9979138b1274ac228.jpg"/&gt;</td><td>Users can alter the frequency of generated waveforms by driving DAWR from external signal via AF0/AF1/SSI. The resultant updating rate should be kept within1MHz. In this demo, iterative generation is used.</td></tr><tr><td colspan="2">Iterative Generation w. Intermediate Space</td></tr><tr><td>&lt;img src="images/e9929b04c61830b72d0ef7c920c7da8186c096bd4cfe24aa0c21ba9ad6e92ac4.jpg"/&gt;</td><td>Utilize DLY2_counter to separate consecutive waveform generations in iterative generation mode. In this demo, the original standard sine wave is repeated several times as specified in IC_counter, with intermediate space determined by DLY2_counter.</td></tr><tr><td colspan="2">Piece-wise Generation</td></tr><tr><td>&lt;img src="images/9ccdd2f2b0d481ec673a1100182e20bb8129034b22362ecc014a0cc76f804f59.jpg"/&gt;</td><td>When the value specified in UC_counter is smaller than the sample size of waveform, the waveform is generated piece-wisely. The intermediate space between each piece is determined by DLY2_counter. In this demo, the UC_counter is set to 1/8 of the sample size of waveform.</td></tr><tr><td colspan="2">Amplitude Modulated</td></tr><tr><td>&lt;img src="images/7b49c29284d230cdfc311aee6a75a18ce7fc0cde21abd59d98bf2538e28e4c92.jpg"/&gt;</td><td>When external D/A reference is used, applying sinusoidal voltage reference will result in an amplitude modulated (AM) waveform generation. Users can use one D/A channel to generate sine wave, loop it back to AOEXTREF_A/ B pin, and generate AM waveform by another D/A channel using external reference. All can be done in a single D/A group.</td></tr><tr><td colspan="2">Frequency Modulated</td></tr><tr><td>&lt;img src="images/49bfbaf0effeadc43aae94859f16d1e86a90c01699a75363ee42554c9717ace0.jpg"/&gt;</td><td>By feeding AFI0/AFI1 with PWM source, pulse train from VCO, or any time-varying digital signal, DAQ/DAQE/PXI-250x Series is capable of generating frequency modulated (FM) waveform. Since all four channels are synchronized in a D/A group, precise quadrature waveform generation is guaranteed, provided the waveform are shifted 90-degree for the other channel. Phase difference of any degree can also be setup. Combined with external High-speed programmable Digital I/O card, Phase-Shift-Keying or Phase-Reversal-Keying can also be achieved.</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

 Read these safety instructions carefully.
 Keep the User’s Manual for future reference.
 Read the Specifications section of this manual for detailed information on the recommended operating environment.
 The device can be operated at an ambient temperature of 50ºC.
When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing:
 Turn off power and unplug any power cords/cables.
 Reinstall all chassis covers before restoring power.

 To avoid electrical shock and/or damage to device:

 Keep device away from water or liquid sources.
 Keep device away from high heat or humidity.
 Keep device properly ventilated (do not block or cover ventilation openings).
 Always use recommended voltage and power source settings.
 Always install and operate device near an easily accessible electrical outlet.
 Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate device on stable surfaces and/or recommended mountings.

 If the device will not be used for long periods of time, turn off and unplug it from its power source
 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image shows a standard warning sign featuring a yellow triangle with a thick black border and a black exclamation point in the center. Below the triangle, the word 'CAUTION:' is printed in black capital letters on a white background.](.daq-daqe-pxi-250x-50m-12264-1000-10/f3a531bac711ec90aba1d810905318ce1af8992bbef006c15a416c71f43d2d9d.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged.
 Liquid has entered the device interior.
 The device has been exposed to high humidity and/or moisture.
 The device is not functioning or does not function according to the User’s Manual.
 The device has been dropped and/or damaged and/or shows obvious signs of breakage.

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.

 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.daq-daqe-pxi-250x-50m-12264-1000-10/2541813273f7835235a82a80da42ac763c5d8208fb0c19d25418e8810e8dc92c.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Road, Guishan District

Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose,

CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.daq-daqe-pxi-250x-50m-12264-1000-10/daq-daqe-pxi-250x-50m-12264-1000-10.pdf)
