# DLAP-3200-CF Series

Embedded System supporting MXM Graphics Module with 8th/9th Generation Intel® Core™ i7/i5/i3 in LGA1151 Socket

User’s Manual

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Manual Rev.: 1.0

Revision Date: August 13, 2021

Part No: 50M-00004-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2021-08-13</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2021 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

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Battery Labels (for products with battery)

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Li-ion

![RECYCLE\nRBRC\nLi-ion\n1.800.822.8837](.dlap-3200-cf-50m-00004-1000-10/908988980e5ba9151738cddc7ece73b13d902ad5ee5665c0367feadb25c2520d.jpg)

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# California Proposition 65 Warning

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WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4- Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

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NOTE:

Additional information, aids, and tips that help users perform tasks.

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CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

ATTENTION: Informations destinées à prévenir les blessures corporelles mineures, les dommages aux composants, la perte de données et/ou la corruption de programme lors de l'exécution d'une tâche.

![The image displays a red equilateral triangle pointing upwards with a white exclamation point centered within it. The background is white, and a black horizontal line runs along the top edge.](.dlap-3200-cf-50m-00004-1000-10/0812e97a6f642ebd13240084ea7cf03e2259ad9590ff3f847014d475fa21dc56.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

AVERTISSEMENT: Informations destinées à prévenir les blessures corporelles graves, les dommages aux composants, la perte de données et/ou la corruption de programme lors de l'exécution d'une tâche spécifique.

# Table of Contents

# Preface ......... iii

# List of Tables ......... .... vii

# List of Figures ........ ix

# 1 Introduction ........

1.1 Overview... 1
1.2 Features... 1
1.3 Packing List ..... 2
1.4 Optional Accessories ..... 3

# 2 Specifications ........ 5

2.1 DLAP-3200-CF . 5
2.2 DLAP-3200-CF Functional Block Diagram . 8
2.3 Display Options... 9
2.4 Mechanical Dimensions.. 10

# 3 System Layout......... . 15

3.1 Front Panel .. 15
3.2 Internal I/O Connectors.. 23

# 4 Getting Started ........ 4 5

4.1 Installing 2.5” Storage .. 46
4.2 Installing an M.2 Module.. 48
4.3 Installing MXM P1000/P2000/T1000 Module ............ 63
4.4 Installing MXM P3000/P5000/RTX3000/RTX5000 Module 67
4.5 Installing a PCIe x4 Add-on Card .. 73
4.6 Mounting ..... 81
4.7 Driver Installation .... 83

# A Appendix: Power Consumption ........ ......85

A.1 Power Consumption Reference... 8 5

# B Appendix: Resource Mapping ............. .....87

B.1 BIOS Mapping in SPI ROM.. 87

B.2 PCI/PCIe Devices .. 88

B.3 IRQ Lines (APIC Mode) . 89

B.4 IRQ Lines (PIC Mode)..... 90

B.5 System Memory Mapping . 91

B.6 System I/O Mapping .. 92

B.7 PCI/PCIe Interrupt Routing Mapping . 93

B.8 SMBus Slave Address Mapping .. 94

# C Appendix: BIOS Setup........... .....95

C.1 BIOS Setup Menu... 95

C.2 Menu Structure . 97

C.3 Main Menu ..... 99

C.4 Advanced Menu.. . 102

C.5 Chipset.. .. 120

C.6 Security ..... . 127

C.7 Boot ... . 128

C.8 Save & Exit ... . 129

# D Appendix: DisplayPort BIOS Settings ................ ......131

D.1 MXM P1000/P2000/T1000/RTX3000/RTX5000 .............. 131

D.2 MXM P3000/P5000... . 132

# E Appendix: Digital Input/Output Function Library .........133

# Important Safety Instructions........ .... 135

# Consignes de Sécurité Importante .......... ... 137

# Getting Service ...... .... 141

# List of Tables

Table 2-1: Maximum Display Resolution .. 9

Table 3-1: I/O Legend... . 17

Table 3-2: Digital Input/Output Connector Pin Definition ........... 19

Table 3-3: Active/Link LED Indicators... . 21

Table 3-4: Speed LED Indicators... .. 21

Table 3-5: D-Sub 9-pin Signal Function of COM Ports .............. 22

Table 3-6: Mainboard Connector Legend .. . 25

Table 3-7: USB 2.0 Connector Pin Definition .. . 27

Table 3-8: USB 3.2 Connector Pin Definition .. . 28

Table 3-9: PCIe Power Connector Pin Definition........... . 29

Table 3-10: SATA Connector Pin Definition . . 29

Table 3-11: COM Connector Pin Definition .. .. 30

Table 3-12: CPU/System Fan Connector Pin Definition .............. 31

Table 3-13: GPU Fan Connector Pin Definition... . 32

Table 3-14: Audio Connector Pin Definition... . 33

Table 3-15: COM1 RS-232/CCtalk Selection Jumper .... . 34

Table 3-16: Case Open Jumper . . 34

Table 3-17: ME Lock Jumper... . 34

Table 3-18: Clear CMOS Jumper .. . 35

Table 3-19: BIOS WP Jumper .. . 35

Table 3-20: Power-on Module Connector Pin Definition.............. 36

Table 3-21: DIO Connector Pin Definition ... . 37

Table 3-22: 12V DC-in Connector Pin Definition .... .. 38

Table 3-23: PCB Edge Connector Pin Definition .. .. 42

Table 3-24: DB40 Connector Pin Definition.. .. 43

Table A-1: DLAP-3200 Power Consumption... . 86

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# List of Figures

Figure 2-1: DLAP-3200-CF Functional Block Diagram . . 8

Figure 2-2: DLAP-3200-CF Front View.. . 10

Figure 2-3: DLAP-3200-CF Left Side View . . 11

Figure 2-4: DLAP-3200-CF Right Side View... . 12

Figure 2-5: DLAP-3200-CF Rear View.... .. 13

Figure 2-6: DLAP-3200-CF Top View .. . 14

Figure 3-1: DLAP-3200-CF Front Panel I/O... .. 15

Figure 3-2: DLAP-3200-CF Rear Panel I/O . . 16

Figure 3-3: Power-on Module.. . 17

Figure 3-4: Digital I/O Connector Pin Definition ... . 19

Figure 3-5: Digital Input Circuit.. .. 20

Figure 3-6: Digital Output Circuit. .. 20

Figure 3-7: COM Port Pin Definition.. . 22

Figure 3-8: Mainboard Connectors (Top).. . 23

Figure 3-9: Mainboard Connectors (Rear) . . 24

Figure 3-10: USB 2.0 Connector Pin Definition.. . 27

Figure 3-11: USB 3.2 Connector Pin Definition... .. 28

Figure 3-12: PCIe Power Connector Pin Definition.. .. 29

Figure 3-13: SATAConnector Pin Definition... .. 29

Figure 3-14: COM Connector Pin Definition.. .. 30

Figure 3-15: CPU/System Fan Connector Pin Definition ..... .. 31

Figure 3-16: GPU Fan Connector Pin Definition.. . 32

Figure 3-17: Audio Connector Pin Definition.. .. 33

Figure 3-18: Multiple I/O Connector Pin Definition.. . 34

Figure 3-19: Power-on Module Connector Pin Definition... .. 36

Figure 3-20: DIO Connector Pin Definition... . 37

Figure 3-21: 12V DC-in Connector Pin Definition ... .. 38

Figure 3-22: PCB Edge Connector Pin Definition .... .. 39

Figure 3-23: DB40 Connector Pin Definition. .. 42

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# 1 Introduction

# 1.1 Overview

The DLAP-3200-CF series is an optimized computing platform supporting performance-hungry workloads, such as deep learning, with expandability options and active cooling for applications requiring very high levels of computing in a limited space. The DLAP-3200-CF series is one of the smallest embedded GPU platforms (5.5 liters) with a low TDP reliable MXM GPU design, scalable graphics processing ranging from Pascal to Turing GPUs, and two PCIe Gen3 x4 expansion slots for full height, half length add-on card support.

# 1.2 Features

X ADLINK MXM Graphics module support (Type A/B/B+, up to 120W)
X 8th/9th Gen Intel® Core™ i7/i5/i3, Celeron® processors
X Dual SODIMMs for up to 64GB DDR4 non-ECC memory (CPU dependent)
X 6x DisplayPort (2 from CPU, 4 from MXM)
X 1x M.2 E key supporting 1630 or 2230 for Wi-Fi/Bluetooth module
X 1x M.2 B key supporting 2242 or 2280 for SATA storage module
X 1x M.2 M key supporting 2242 or 2280 for SATA/PCIe x4 storage module
X Reliable Molex type 12V DC-in connector
X 1x Intel® i219-LM and 3x Intel® i210-AT
X 2x PCIe Gen3 x4 expansion slot for full height, half length add on card. Each slot supports 25W power with an additional Molex 4-pin power cable (12V/1.5A and 5V/2A)

# 1.3 Packing List

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

X 1x DLAP-3200-CF Embedded Computer
X Fasteners:

Z 3x M3 screws, P-head, L4, Ni for M.2 (P/N: 33-03013-0040)
Z 8x M3 screws, F-head, L4, Nylok for 2.5” storage bay (P/N: 33-03103-1040)
Z 2x M3 screws, I-head, L4, Nylok for MXM (P/N: 33-03306-0040)

![The image displays a simple icon representing a document with a large red checkmark superimposed over it. The document is depicted as a white piece of paper with a folded top-left corner and several horizontal gray lines running across the bottom, suggesting text or a checklist. The red checkmark is drawn thickly, spanning from the bottom left to the top right of the document area.](.dlap-3200-cf-50m-00004-1000-10/8fb719390f8c06636f60fbec084862b6ee4c4c9cf04e6817c4f224e2f916ccd6.jpg)
NOTE:

If the DLAP-3200-CF does not have a pre-installed MXM P3000/P5000/RTX3000/RTX5000, the following additional installation items have been included.

X 4x M3 Screw, I-head, L5, Ni (PN: 33-03320-0050)
X 4x Washer 5.3 x 10 x 1.0, SUS (PN:33-90086-0000-A0)
X 4x Rubber footpad (PN:39-00039-0000)

# 1.4 Optional Accessories

X CPU cooler (P/N: 32-20495-0000)
X CPU cooler bracket (P/N: 32-50015-0100-A0)
X MXM cooler for P1000/P2000 (P/N: 32-20797-0200-A0)
X MXM cooler for P3000/P5000 (P/N: 32-20823-0020-A0)
X MXM cooler for T1000 (P/N: 32-20830-0200-A0)
X MXM cooler for RTX3000 (P/N: 32-20823-1100-A0)
X MXM cooler for RTX5000 (P/N: 32-20839-1000-A0)
X 12V/240W power adaptor (P/N: 31-62164-0010-A0)
X DLAP-3000 AC/DC power supply kit, 500W (12V/41.7A) (P/N: 91-95296-002E)
X Wall mount bracket set (P/N: 34-34546-0000-A0) (2 required)
? Wi-Fi Kit Intel® Wireless-AC 9260 non-vPRO (P/N: 91-95266-0020)

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# 2 Specifications

2.1 DLAP-3200-CF

<table><tr><td rowspan="2">Model</td><td>DLAP-3200-CFP1</td><td>DLAP-3200-CFP2</td><td>DLAP-3200-CFT1</td><td>DLAP-3200-CFT3</td><td>DLAP-3200-CFT5</td><td>DLAP-3200-CFP3</td><td>DLAP-3200-CFP5</td></tr><tr><td colspan="5">DLAP-3200-CFP12*</td><td colspan="2">DLAP-3200-CFP35*</td></tr><tr><td>MXM Support</td><td>EGX-MXM-P1000</td><td>EGX-MXM-P2000</td><td>EGX-MXM-T1000</td><td>EGX-MXM-RTX3000</td><td>EGX-MXM-RTX5000</td><td>EGX-MXM-P3000</td><td>EGX-MXM-P5000</td></tr><tr><td>Processor</td><td colspan="7">Intel® CoreTM i7-9700E, 2.6GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (8C/8T) Intel® CoreTM i7-9700TE, 1.8GHz, 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (8C/8T) Intel® CoreTM i5-9500E, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T) Intel® CoreTM i5-9500TE, 2.2GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T) Intel® CoreTM i3-9100E, 3.1GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support (4C/4T) Intel® CoreTM i3-9100TE, 2.2GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2400MHz support (4C/4T) Intel® CoreTM i7-8700, 3.2GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/12T) Intel® CoreTM i7-8700T, 2.4GHz 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/12T) Intel® CoreTM i5-8500, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T) Intel® CoreTM i5-8500T, 2.1GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T) Intel® CoreTM i3-8100, 3.6GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support (4C/4T) Intel® Celeron® G4900, 3.1GHz, 2M Cache, 54W TDP, LGA1151, DDR4 2400MHz support (2C/2T) Intel® Celeron® G4900T, 2.9GHz, 2M Cache, 35W TDP, LGA1151, DDR4 2400MHz support (2C/2T)</td></tr><tr><td>Chipset</td><td colspan="7">Intel® Q370 Chipset</td></tr><tr><td>Memory</td><td colspan="7">Non-ECC DDR4 2666/2400MHz, 2x SODIMM, up to 64GB (CPU dependent)</td></tr><tr><td colspan="8">I/O Interface</td></tr><tr><td>Display</td><td colspan="7">6x DisplayPort (2 from CPU, 4 from MXM)</td></tr><tr><td>Ethernet</td><td colspan="7">1x GbE (Intel® i219-LM), 3x GbE (Intel® i210-AT)</td></tr><tr><td>Serial Ports</td><td colspan="7">1x RS-232/422/485, 1x RS-232</td></tr><tr><td>USB</td><td colspan="7">6x USB 3.2 Gen1 x1 ports, 2x USB 2.0 ports</td></tr><tr><td>Audio</td><td colspan="7">Mic-in, L/R speaker-out (6W + 6W) (Optional)</td></tr><tr><td>M.2</td><td colspan="7">► 1x M.2 E key for 1630 or 2230 Wi-Fi/BT module► 1x M.2 B key for 2242 or 2280 SATA storage module► 1x M.2 M key for 2242 or 2280 SATA/PCIe x4 storage module</td></tr><tr><td>eSIM</td><td colspan="7">Optional</td></tr><tr><td>DI/O</td><td colspan="7">1x DI/DO with 4 in, 4 out</td></tr><tr><td>TPM 2.0</td><td colspan="7">Yes</td></tr><tr><td>Expansion</td><td colspan="7">2x PCIe Gen3 x4 expansion slots for full height, half length add-on card.Each slot supports 25W power and additional Molex 4-pin power cable (12V/1.5A and 5V/2A).</td></tr><tr><td colspan="8">Storage</td></tr><tr><td>SATA</td><td colspan="7">► 2x 2.5" SATA 6Gb/s external drive bays► 2x SATA 6Gb/s signals via M.2 M &amp; B key connectors► Intel® RST RAID Support</td></tr><tr><td colspan="8">Physical</td></tr><tr><td>Dimensions</td><td colspan="7">235 x 182 x 129mm (W x D x H, without foot pads)</td></tr><tr><td>Mounting</td><td colspan="7">Optional wall-mount bracket</td></tr><tr><td colspan="8">Power Supply</td></tr><tr><td>DC Input</td><td colspan="7">DC 12V input (Molex DC-in jack)</td></tr><tr><td>AC Input</td><td colspan="7">► Optional: 240W (12V/20A) AC/DC adapter► Optional: 500W (12V/41.7A) AC/DC power supply unit</td></tr><tr><td colspan="8">Environmental</td></tr><tr><td>Operating Temperature</td><td colspan="7">0°C to 50°C (W/MXM module except RTX-5000, W/SSD; w/add on card supported operating temperature is 0°C to 70°C)0°C to 40°C (W/MXM RTX-5000, W/SSD, w/add on card supported operating temperature is 0°C to 70°C)</td></tr><tr><td>Storage Temperature</td><td colspan="7">-20°C to 70°C</td></tr><tr><td>Humidity</td><td colspan="7">5% to 95%, non-condensing</td></tr><tr><td>Vibration</td><td colspan="7">Operating: 2Grms, 5-500Hz, 3 axesPackage (non operating): 3.44Grms, 10-1000Hz, 3 axes (w/MXM, w/SSD)</td></tr><tr><td>Shock</td><td colspan="7">Operating and Package (non operating): 30G, 11ms duration,half-sine (w/MXM, w/SSD)</td></tr><tr><td>EMC</td><td colspan="7">EN55032/35, EN61000-6-2/-4, CE, FCC Part 15B Class B (w/ 240W adaptor),Class A (w/ 500W PSU)</td></tr><tr><td>Safety</td><td colspan="7">UL/cUL and CB</td></tr></table>

![The image displays a graphic of a document icon featuring horizontal lines and a large red checkmark overlaid on it. Below the icon is the text 'NOTE:' in black, uppercase letters.](.dlap-3200-cf-50m-00004-1000-10/8655e0e9c2644808b1504bc085fe10d20a5ad648e469deccbea3a961e69d4b13.jpg)

Models marked with “\*” do not include an MXM graphics module.
X Contact your local ADLINK sales representative for MXM module and related DLAP model longevity.

2.2 DLAP-3200-CF Functional Block Diagram
![Here is an accurate description of the flowchart blocks and connections:\n\n**Central Processors**\n*   **8th/9th Gen Intel® Core™ Processor** connects to:\n    *   **SODIMM 1** (DDR4 non-ECC Socket) via **Channel A**.\n    *   **SODIMM 2** (DDR4 non-ECC Socket) via **Channel B**.\n    *   **DP to LVDS** (FTX34608BS_NXP) via **4DP-Lanes**.\n    *   **LVDS CN** via **DDAL 24/18x00** (indicated by blue dashed lines).\n    *   Three **DP CN** blocks via **DD 1 (PORT B), DP**, **DD 2 (PORT C), DP**, and **DD 3 (PORT D), HDMI**.\n    *   **HDMI CN**.\n    *   **MXM3.1 slot** via **PCI Express x16 (GEN3)**.\n    *   **Intel PCH Q370 Chipset** via **DMI**.\n\n*   **Intel PCH Q370 Chipset** connects to:\n    *   **USB3.2 Gen1x1 * 4 + RJ45 x1 CN * 2** via **USB3.2 Gen1x1**, **USB2.0**.\n    *   **GbE LAN1** (QTELM_Intel) via **LAN**.\n    *   **LAN4** (QTE_Intel) via **PCIe1**.\n    *   **USB3.2 Gen1x12** via **USB3.2 Gen1x1**, **USB2.0**.\n    *   **SW** (PID68512212A_Diodes) via **USB3.2 Gen1x1**.\n    *   **M.2_B_key CNx1** (2280 size (default)) via **USB2.0**.\n    *   **M.2_M_key CNx1** (2280 size (default)) via **PCIe1 or SATA**.\n    *   **M.2_E_key CNx1** (2230 size (default)) via **PCIe1 * 2**, **USB2.0**.\n    *   **USB2.0x2** via **USB2.0**.\n    *   **Audio Codec** (Optional) via **HDA**.\n    *   **AMP** (Optional) via **SPI**.\n    *   **SATA Storage x2** via **SATA**.\n    *   **BIOS** via **SPI**.\n    *   **SUPER I/O** (F81864AD_1_FUNTEK) via **UART**, **UART**.\n    *   **TPM 2.0** (SLB9666_IFINEON) via **SPI**.\n    *   **D640** via **JTAG**.\n    *   **Lite BMC** (BTM32L071RB16_ST) via **SMBus**.\n    *   **DIO 4 bit in 4 bit out** via **GPIO**.\n    *   **2nd Gen3 PCIe x4** (bidirectional connection).\n\n**Peripheral Connections**\n*   **MXM3.1 slot** connects to four **DP CN** blocks via **Port A**, **Port E**, **Port C**, and **Port D**.\n*   **SW** (PID68512212A_Diodes) connects to **USB3.2 Gen1x12** via **USB3.2 Gen1x1**, **USB2.0**.\n*   **SW** (PID68512212A_Diodes) connects to **M.2_B_key CNx1** via **USB2.0**.\n*   **Audio Codec** (Optional) connects to **MIC IN x1 or LINE IN x1** (Speakers out (6W x2)) (Optional) via **Line In**, **Mic In**.\n*   **MIC IN x1 or LINE IN x1** block connects to **AMP** (Optional) via **Speaker Out**.\n*   **SUPER I/O** connects to **RS232/422/485** via **SP338E_EXAR** and to **RS232** via **ADM2131EA_ADI**.\n*   **M.2_B_key CNx1** connects to **SW** (PID68512212A_Diodes) via **SW**.\n*   **SW** (PID68512212A_Diodes) connects to **RJ45 CN** via **SW**.\n*   **RJ45 CN** connects to **LAN2** (QTE_Intel) via **Default** and **LAN3** (QTE_Intel) via **Default**.\n*   **SW** (PID68512212A_Diodes) connects to **BOM Option** via **PCIe1**.\n*   **BOM Option** connects to another **BOM Option** via **PCIe1**.](.dlap-3200-cf-50m-00004-1000-10/53ba919b440a29720cb6e87003b1f815147a7efd0402a90012bbaa54772ba965.jpg)

Figure 2-1: DLAP-3200-CF Functional Block Diagram

# 2.3 Display Options

The DLAP-3200-CF includes six DisplayPort connectors, two DisplayPort signals from the CPU and four from MXM. All DisplayPorts support DP++. Use DisplayPort1 (DP 1) to connect a monitor when booting the system for the first time to properly access the display settings in the BIOS menu. Refer to Appendix D, Display-Port BIOS Settings for more information.

<table><tr><td></td><td>Port</td><td>Resolution</td></tr><tr><td>Display Port 1 from CPU</td><td>DP 1</td><td>4096x2304@60Hz</td></tr><tr><td>Display Port 2 from CPU</td><td>DP 2</td><td>4096x2304@60Hz</td></tr><tr><td>Display Port A from MXM</td><td>DP A</td><td>Based on MXM module</td></tr><tr><td>Display Port B from MXM</td><td>DP B</td><td>Based on MXM module</td></tr><tr><td>Display Port C from MXM</td><td>DP C</td><td>Based on MXM module</td></tr><tr><td>Display Port D from MXM</td><td>DP D</td><td>Based on MXM module</td></tr></table>

Table 2-1: Maximum Display Resolution

# 2.4 Mechanical Dimensions

![The image displays a white document icon with a folded top-right corner and horizontal lines near the bottom. A large, thick red checkmark is superimposed over the document, slanting upwards from the bottom left to the top right.](.dlap-3200-cf-50m-00004-1000-10/ad19e5758368453147aafe412c310401f974c17d44bbcf8104ffa9a1517ec5e0.jpg)
NOTE:

All dimensions are in millimeters, unless noted.

![235.00\n129.00\n132.96](.dlap-3200-cf-50m-00004-1000-10/a052f14712335f48f6e485f0404fcecbe48b1390b51385f4d87e37235bc86f89.jpg)

![235.00\nCOM 1\nU8 U14 U6 U8\nLAN 3 LAN 4 LAN 1\nDP 1 U3 U1 DP A\nCOM 2\nDP 2 LAN 2 U4 U2 DP B\nBay 1 Bay 2\nADLINK\n129.00\n137.00](.dlap-3200-cf-50m-00004-1000-10/3ad70cc69b615d123e03dbbcc5338867d3a54f5d6c10d009a6390fb0d0ab1dbc.jpg)

Figure 2-2: DLAP-3200-CF Front View (including wall-mount brackets and footpads)

![182.00\n194.50](.dlap-3200-cf-50m-00004-1000-10/7354241b8ef859287d507f71212f8c6f7a19025168d1618d1f89707ff1f8b9f8.jpg)

Figure 2-3: DLAP-3200-CF Left Side View

![182.00\n194.50](.dlap-3200-cf-50m-00004-1000-10/d20ce86d3c36d20b6872736b226973d8aefc89cff03f169dbdcdf48a6fac8ce4.jpg)

Figure 2-4: DLAP-3200-CF Right Side View

![235.00\nDIO\nR\nL](.dlap-3200-cf-50m-00004-1000-10/07c4994f63e4e39cf9199d21516cfe5e89e485290ae4ec3bf3a131c9edb555c0.jpg)

Figure 2-5: DLAP-3200-CF Rear View

![235\n128\n169\n180\n182\n235\n253\n266](.dlap-3200-cf-50m-00004-1000-10/40b400a415dadd9f9281d507d0edaa4e08d147f766ff048f1f9090e06d4d3223.jpg)

![R2.50\nR5\n20\nØS\n5.50\n6.50](.dlap-3200-cf-50m-00004-1000-10/c6a41d58442fdb23f78265a33818a0854cb04e8d109d616dbac4813b2b407d5f.jpg)

Figure 2-6: DLAP-3200-CF Top View

![The image displays a warning sign consisting of a red triangle with a white exclamation point in the center. Below the triangle is a white rectangular label with the word 'WARNING' printed in black, all-caps text.](.dlap-3200-cf-50m-00004-1000-10/6cb3a149261676f08928b1f5d38f90e40504859cbf21e75e0b73726ee594dfa2.jpg)

To prevent damage to the system, ensure there is a minimum 10 cm clearance around the air vents for unrestricted airflow. The air temperature inside the enclosure could rise above the specified operating temperature limits if the airflow through the vents is restricted.

AVERTISSEMENT: Pour éviter d'endommager le système, assurez-vous qu'il y a un dégagement minimum de 10 cm autour des bouches d'aération pour une circulation d'air sans restriction. La température de l'air à l'intérieur du boîtier peut dépasser les limites de température de fonctionnement spécifiées si le flux d'air à travers les évents est restreint.

# 3 System Layout

# 3.1 Front Panel

The DLAP-3200-CF Series provides the following I/O access features.

![A\nF\nG\nB\nH I M\nJ9 U14\nJ5 U6\nCOM 1\nLAN 3\nLAN 4\nU1\nU2\nDP A\nDP B\nDP C\nDC-IN\nADLINK\nC\nCOM 2\nDP 1\nDP 2 LAN 2\nBay 1\nDP D\nBay 2\nD E F G L J\nK](.dlap-3200-cf-50m-00004-1000-10/7b7c97030ac571813ceda40e478b9776eeac55a577b7c3dbdf263eb8b4e56325.jpg)

Figure 3-1: DLAP-3200-CF Front Panel I/O

![N\nO\nDIO\nR\nL\nP](.dlap-3200-cf-50m-00004-1000-10/ab374ca2c7ad501510f523b4e7103bfdaff3ad9a83d79f0ae69df117af4def1d.jpg)

Figure 3-2: DLAP-3200-CF Rear Panel I/O

<table><tr><td>A</td><td>USB 2.0 Type-A x2 (U9, U14)</td><td>I</td><td>DisplayPort from MXM for DP C/DP D</td></tr><tr><td>B</td><td>USB 3.2 Gen1 x1 Type-A x2 for U5/U6</td><td>J</td><td>12V DC Power Input</td></tr><tr><td>C</td><td>RS-232 for COM1, RS-232/422/485 for COM2</td><td>K</td><td>2x PCIe x4 Gen3 slots</td></tr><tr><td>D</td><td>DisplayPort x2 (DP 1/DP 2)</td><td>L</td><td>2x 2.5” hot swappable storage bay (Bay 1/Bay 2)</td></tr><tr><td>E</td><td>i210-AT (LAN 2/ LAN 3)</td><td>M</td><td>Power-on module. (See 3.1.1: Power-on Module )</td></tr><tr><td>F</td><td>i210-AT (LAN 4), USB 3.2 Gen1 x1 Type-A (U3/U4)</td><td>N</td><td>DIO</td></tr><tr><td>G</td><td>i219-LM (LAN 1), USB 3.2 Gen1 x1 Type-A (U1/U2)</td><td>O</td><td>Speaker out Left and Right, Mic in (Optional. Audio hole is sealed when not available.)</td></tr><tr><td>H</td><td>DisplayPort from MXM for DP A/DP B</td><td>P</td><td>Reserved for Wi-Fi/BT antenna</td></tr></table>

Table 3-1: I/O Legend

# 3.1.1 Power-on Module

![M1 M2 M3 M4\nM5 M6 M7](.dlap-3200-cf-50m-00004-1000-10/f80d5cd99ee60f606227cc6f971c3b1b468c1f165a6cf93c675ad8d6322c43f1.jpg)

Figure 3-3: Power-on Module

<table><tr><td>M1</td><td>Alarm Reset Button: When the fan or GPU temperature alarm has been triggered, insert a small, thin object like a paper clip and press the reset button to turn off the alarm. This is to reset the alarm beeper only, not to reset the alarm LED.</td></tr><tr><td>M2</td><td>Reset Switch: Push to reset the system.</td></tr><tr><td>M3</td><td>Power On Button: Lights blue when the system is powered on, blinks when the system suspends to RAM, and is off when the system suspends to disk.</td></tr><tr><td>M4</td><td>Remote Power On Button Connector: Remote power on control.Note: Requires additional cable with an ALEX 9566-02G tin plated connector. The left pin is GND and the right pin is PRWBTN#, short enabled. (MPN: ALEX, 9553-02-PBT, black)</td></tr><tr><td>M5</td><td>Temperature Alarm LED: Blinks white when CPU or GPU overheats.</td></tr><tr><td>M6</td><td>Fan Alarm LED: Blinks amber when CPU, GPU, or system fan is &lt;300 rpm.</td></tr><tr><td>M7</td><td>Storage Status LED: Blinks red when storage is accessed.</td></tr></table>

# 3.1.2 Audio Connectors

The DLAP-3200-CF provides the following defualt audio connectors.

X 3.5 mm mono jack for left channel speaker out (6W)
X 3.5 mm mono jack for right channel speaker out (6W)
X Microphone in

![The image displays a standard icon featuring a white document with horizontal lines. The top right corner is folded over, and a large red checkmark is superimposed on the left side of the document.](.dlap-3200-cf-50m-00004-1000-10/f6e3a41459b18ff64abfe7b65302be3df042164320ab0484ef89b98ed1114000.jpg)
NOTE:

The DLAP-3200-CF series audio connectors are (from top to bottom) speaker out L channel (6W), speaker out R channel (6W), and Mic in. The speaker out connector should be a 3.5mm mono jack plug. If a line out (headphone out) is needed instead of the speaker out (with amplifier 6W+6W), contact your local ADLINK sales representative.

The following audio configurations are also available.

X Mic-in, Line-out, Line-in
X Line-in, L/R speaker-out (6W + 6W)
X Without audio function

# 3.1.3 Digital I/O Connector

The DLAP-3200-CF provides 4 channels of non-isolation digital input and 4 channels of non-isolation digital output circuits, with specificacations and circuits as follows.

# 4-channel Digital Input

X VIH: 1.5 to 5V
X VIL: 0 to 0.5V

# 4-channel Digital Output

X Output type: Open drain N-channel
X MOSFET driver with internal pull high of 200Ω resistance.
X Source/Sink current for all channels: 22mA
X VOH: 4.956 to 5V
X VOL: 0 to 0.085V

![5\n10\n15\n6\n11](.dlap-3200-cf-50m-00004-1000-10/3bdb8c2f7302c8befafec924390aaed4f10a504495873b23b803cef01a987fae.jpg)

Figure 3-4: Digital I/O Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DI0</td><td>6</td><td>VCC(5V standby is always on except when in ACPI S5 )</td><td>11</td><td>DO0</td></tr><tr><td>2</td><td>DI1</td><td>7</td><td>NC</td><td>12</td><td>DO1</td></tr><tr><td>3</td><td>DI2</td><td>8</td><td>NC</td><td>13</td><td>DO2</td></tr><tr><td>4</td><td>DI3</td><td>9</td><td>NC</td><td>14</td><td>DO3</td></tr><tr><td>5</td><td>GND</td><td>10</td><td>GND</td><td>15</td><td>NC</td></tr></table>

Table 3-2: Digital Input/Output Connector Pin Definition

![+3.3V\n2.2kΩ\nDI_IN\nDIn\n100kΩ\nG\nS\nMOS\nDI_GND](.dlap-3200-cf-50m-00004-1000-10/b6db9fd3d1c6bfa8ddb2c2f817b3c5a5804de529fd0defc8667730713383e3e6.jpg)

Figure 3-5: Digital Input Circuit

![+3.3V\n+5.0V\n2.2K\n220\nDO_OUT\nD\nG\nS\nMOS\nDOn](.dlap-3200-cf-50m-00004-1000-10/87fd367e0991a10d1e603994a8d87daa6ec363070bc5051a8d00976358c61b61.jpg)

Figure 3-6: Digital Output Circuit

# 3.1.4 Gigabit Ethernet Ports

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Orange</td><td>Off</td><td>Ethernet port is disconnected.</td></tr><tr><td>On</td><td>Ethernet port is connected with no activity.</td></tr><tr><td>Flashing</td><td>Ethernet port is connected and active.</td></tr></table>

Table 3-3: Active/Link LED Indicators

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Green/Orange</td><td>Off</td><td>10 Mbps</td></tr><tr><td>Green</td><td>100 Mbps</td></tr><tr><td>Orange</td><td>1000 Mbps</td></tr></table>

Table 3-4: Speed LED Indicators

# 3.1.5 COM Port Connectors

The DLAP-3200-CF provides two COM ports through D-sub 9-pin connectors. The COM2 port support RS-232/422/485 modes by BIOS setting, while COM1 supports only RS-232.

![1\n5\n6\n9](.dlap-3200-cf-50m-00004-1000-10/24a1af7c36b3417a05975819e8d43ed78868a1ca9ef82a343d01f1721308d4ce.jpg)

Figure 3-7: COM Port Pin Definition

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal Name</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>TXD422-</td><td>485DATA-</td></tr><tr><td>2</td><td>RXD</td><td>TXD422+</td><td>485DATA+</td></tr><tr><td>3</td><td>TXD</td><td>RXD422+</td><td>N/S</td></tr><tr><td>4</td><td>DTR#</td><td>RXD422-</td><td>N/S</td></tr><tr><td>5</td><td>GND</td><td>N/S</td><td>N/S</td></tr><tr><td>6</td><td>DSR#</td><td>N/S</td><td>N/S</td></tr><tr><td>7</td><td>RTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>8</td><td>CTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>9</td><td>RI#</td><td>N/S</td><td>N/S</td></tr></table>

Table 3-5: D-Sub 9-pin Signal Function of COM Ports

# 3.2 Internal I/O Connectors

![The image displays a standard safety warning symbol consisting of a red equilateral triangle with a white exclamation mark in the center. Below the triangle, the word 'WARNING' is printed in black, uppercase letters.](.dlap-3200-cf-50m-00004-1000-10/96635dddc1f6fe1910f091ec1d6b691869b066890abb708148ba44c2fc319833.jpg)

Installation of add-on devices must be carried out by ADLINK service personnel only. Users must not disassemble the device themselves.

L'installation de périphériques complémentaires doit être effectuée uniquement par le personnel de service ADLINK. Les utilisateurs ne doivent pas démonter l'appareil eux-mêmes.

# 3.2.1 Mainboard Connector Locations

![F G H I J K\nE C\nD B\nAH AI\nA S\nT\nU V\nAC AB AA Z Y X W](.dlap-3200-cf-50m-00004-1000-10/4ec15494b562e6a0f65e5eb22c68b6ad9d9c27772eef1243e907cff94e33faa4.jpg)

Figure 3-8: Mainboard Connectors (Top)

![AD\nAE AF AG](.dlap-3200-cf-50m-00004-1000-10/8df862219aea9c43adb15097f58edfad45fb3d9df134bae38f39f398da3b2862.jpg)

Figure 3-9: Mainboard Connectors (Rear)

<table><tr><td>A</td><td>CPU socket</td></tr><tr><td>B</td><td>DRAM socket for DIMM1</td></tr><tr><td>C</td><td>DRAM socket for DIMM2</td></tr><tr><td>D</td><td>CPU Fan connector</td></tr><tr><td>E</td><td>System Fan connector</td></tr><tr><td>F</td><td>2x USB 2.0 Gen1 x1 pin header for U9/U14</td></tr><tr><td>G</td><td>RS-232 pin header for COM1</td></tr><tr><td>H</td><td>RS-232/422/485 pin header for COM2</td></tr><tr><td>I</td><td>2x USB 3.2 Gen1 x1 pin header for U5/U6</td></tr><tr><td>J</td><td>Multi I/O connector</td></tr><tr><td>K</td><td>Audio pin header</td></tr><tr><td>L</td><td>PCIe power connector</td></tr></table>

<table><tr><td>M</td><td>SATA connector</td></tr><tr><td>N</td><td>SATA connector</td></tr><tr><td>O</td><td>SATA power connector</td></tr><tr><td>P</td><td>Power-on module connector</td></tr><tr><td>Q</td><td>DIO connector</td></tr><tr><td>S</td><td>MXM connector</td></tr><tr><td>T</td><td>PCB edge connector</td></tr><tr><td>U</td><td>RTC battery connector</td></tr><tr><td>V</td><td>GPU fan connector</td></tr><tr><td>W</td><td>12V DC in connector</td></tr><tr><td>X</td><td>DisplayPort C and D from MXM</td></tr><tr><td>Y</td><td>DisplayPort A and B from MXM</td></tr><tr><td>Z</td><td>LAN 1 and USB 3.2 Gen 1 x1 ports 1 and 2</td></tr><tr><td>AA</td><td>LAN 4 and USB 3.2 Gen 1 x1 ports 3 and 4</td></tr><tr><td>AB</td><td>LAN 2 and LAN 3</td></tr><tr><td>AC</td><td>DisplayPort 1 and 2 from CPU</td></tr><tr><td>AD</td><td>DB40 connector</td></tr><tr><td>AE</td><td>M.2_B Key connector</td></tr><tr><td>AF</td><td>M.2_M Key connector (DLAP-3100-CF and DLAP-3200-CF)</td></tr><tr><td>AG</td><td>M.2_E Key connector</td></tr><tr><td>AH</td><td>Blue LED2_BMC status</td></tr><tr><td>AI</td><td>RED LED3_BMC watchdog</td></tr></table>

Table 3-6: Mainboard Connector Legend

# 3.2.2 BMC Status LED and WDT LED

# 3.2.2.1 Status LED (Blue)

The Status LED is controlled by SEMA to signal system state changes and power up failures. The system state changes can be HW-Reset, SW-Reset, Power-Up, Power-Down, Reset-Button and Power-Button activity. The Status LED will light for short time. Power-Up failures can indicate a corrupted BIOS or failure of the onboard power supply. A blink code displays in cases of failure.

When the system is in an S3 state, the Status LED flashes every four seconds.

<table><tr><td>LED Blink Code</td><td>Status</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_RSMRST</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>7</td><td>PLTRST_FAIL</td></tr><tr><td>8</td><td>NO_SYS_PWRGD</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>NO_VIN</td></tr><tr><td>12</td><td>NO_VRTC</td></tr></table>

# 3.2.2.2 WDT LED (Red)

The WDT LED is driven by SEMA and will light when a watchdog timeout occurs. It stays on until it is cleared by software or the reset button.

# 3.2.3 USB 2.0 Connector

One USB 2.0 pin header is provided on the mainboard for an internal USB dongle.

![1\n10](.dlap-3200-cf-50m-00004-1000-10/24c10aae928ffbd84d433fb5b14aec2a0edf0b1efb5a1dd5b0a0cc0fd0ccef40.jpg)

Figure 3-10: USB 2.0 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P5V_USB1</td><td>6</td><td>CN_U2_USB14_P</td></tr><tr><td>2</td><td>P5V_USB1</td><td>7</td><td>GND</td></tr><tr><td>3</td><td>CN_U2_USB9_N</td><td>8</td><td>GND</td></tr><tr><td>4</td><td>CN_U2_USB14_N</td><td>9</td><td>NC</td></tr><tr><td>5</td><td>CN_U2_USB9_P</td><td>10</td><td>GND</td></tr></table>

Table 3-7: USB 2.0 Connector Pin Definition

# 3.2.4 USB 3.2 Connector

One USB 3.2 Gen1 x1pin header is provided on the mainboard for an internal USB dongle.

![Pure electrical circuit lines without any symbols](.dlap-3200-cf-50m-00004-1000-10/bcd14a97a161492ba263ad62cd4a3beaf4cf3fb801485a01415330c93f11b0f1.jpg)

Figure 3-11: USB 3.2 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>11</td><td>P5V_USB56</td></tr><tr><td>2</td><td>CN_U3_USB6_T_P</td><td>12</td><td>CN_U2_USB5_N</td></tr><tr><td>3</td><td>CN_U3_USB6_T_N</td><td>13</td><td>CN_U2_USB5_P</td></tr><tr><td>4</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>5</td><td>CN_U3_USB6_R_P</td><td>15</td><td>CN_U3_USB5_R_N</td></tr><tr><td>6</td><td>CN_U3_USB6_R_N</td><td>16</td><td>CN_U3_USB5_R_P</td></tr><tr><td>7</td><td>GND</td><td>17</td><td>GND</td></tr><tr><td>8</td><td>CN_U2_USB6_P</td><td>18</td><td>CN_U3_USB5_T_N</td></tr><tr><td>9</td><td>CN_U2_USB6_N</td><td>19</td><td>CN_U3_USB5_T_P</td></tr><tr><td>10</td><td>P5V_USB56</td><td>20</td><td>NC</td></tr></table>

Table 3-8: USB 3.2 Connector Pin Definition

# 3.2.5 PCIe Power Connector

![Simple line drawing of a rectangular frame with five square holes, no text or symbols present](.dlap-3200-cf-50m-00004-1000-10/83abe3e96b6975ab8018a686484d0591cfc79e99d4b8e473555e007bf252d742.jpg)

Figure 3-12: PCIe Power Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+12V_S</td></tr><tr><td>2</td><td>P_+12V_S</td></tr><tr><td>3</td><td>P_+5V0_S</td></tr><tr><td>4</td><td>P_+5V0_S</td></tr><tr><td>5</td><td>GND</td></tr></table>

Table 3-9: PCIe Power Connector Pin Definition

# 3.2.6 SATA Power Connector

![The image displays a schematic line drawing of a rectangular electrical connector, resembling a USB or similar plug, featuring a vertical row of connection points along its left edge. To the right of the connector is the number '1'.](.dlap-3200-cf-50m-00004-1000-10/2e3b6f78ab8ac6c4027101710de0de2f84f1d756bf433870207ce61e2ddaa311.jpg)
Figure 3-13: SATAConnector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V0_S</td></tr><tr><td>2</td><td>P_+5V0_S</td></tr><tr><td>3</td><td>P_+5V0_S</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>GND</td></tr></table>

Table 3-10: SATA Connector Pin Definition

# 3.2.7 COM Connector

![1\n2\n9\n10](.dlap-3200-cf-50m-00004-1000-10/9ee47d14de24d3d76c7e652239b28a27a5bf03840b8029c199048a73bd0dbf10.jpg)

Figure 3-14: COM Connector Pin Definition

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal Name</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>Tx-</td><td>Tx/Rx-</td></tr><tr><td>2</td><td>DSR#</td><td>Tx+</td><td>Tx/Rx+</td></tr><tr><td>3</td><td>RxD</td><td>Rx+</td><td>N/A</td></tr><tr><td>4</td><td>RTS#</td><td>Rx-</td><td>N/A</td></tr><tr><td>5</td><td>TxD</td><td>N/A</td><td>N/A</td></tr><tr><td>6</td><td>CTS#</td><td>N/A</td><td>N/A</td></tr><tr><td>7</td><td>DTR#</td><td>N/A</td><td>N/A</td></tr><tr><td>8</td><td>RI#</td><td>N/A</td><td>N/A</td></tr><tr><td>9</td><td>GND</td><td>GND</td><td>GND</td></tr></table>

Table 3-11: COM Connector Pin Definition

# 3.2.8 CPU/System Fan Connectors

Two connectors are provided for CPU and system fan power.

![Simple diagram with four black squares arranged horizontally inside a rectangular frame, labeled '1' at the bottom (no text or symbols within the diagram itself)](.dlap-3200-cf-50m-00004-1000-10/8894c88edf958278e7f79369e79186707cb5b1720b474472d12288a831ef9813.jpg)

Figure 3-15: CPU/System Fan Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>FAN_GND</td></tr><tr><td>2</td><td>P_+12V_FAN</td></tr><tr><td>3</td><td>FAN_IN</td></tr><tr><td>4</td><td>FAN_OUT</td></tr></table>

Table 3-12: CPU/System Fan Connector Pin Definition

# 3.2.9 GPU Fan Connector

![Pure electrical connector pinout diagram without any text or symbols](.dlap-3200-cf-50m-00004-1000-10/3f9f54dc2cf04eba59712cd09202f62c5c736fd657777612dd4abeb128681c12.jpg)

Figure 3-16: GPU Fan Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>FAN_OUT</td></tr><tr><td>2</td><td>FAN_IN</td></tr><tr><td>3</td><td>P_+12V_FAN</td></tr><tr><td>4</td><td>FAN_GND</td></tr></table>

Table 3-13: GPU Fan Connector Pin Definition

# 3.2.10 Audio Connector

![Pure electrical connector diagram without any text or symbols](.dlap-3200-cf-50m-00004-1000-10/9edeb5913b162b38bb09521c7bdfcc325f3d5a59a0ed01dd4f4a0ec7e68ab61f.jpg)

Figure 3-17: Audio Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>AUDIO_Sense</td><td>6</td><td>GND_AUD</td></tr><tr><td>2</td><td>SPK_RP</td><td>7</td><td>A_MIC_IN_L</td></tr><tr><td>3</td><td>A_L_IN_L</td><td>8</td><td>SPK_LP</td></tr><tr><td>4</td><td>SPK_RN</td><td>9</td><td>A_MIC_IN_R</td></tr><tr><td>5</td><td>A_L_IN_R</td><td>10</td><td>SPK_LN</td></tr></table>

Table 3-14: Audio Connector Pin Definition

# 3.2.11 Multiple I/O Connector

![Pure electrical circuit lines without any symbols](.dlap-3200-cf-50m-00004-1000-10/153b42a3fb38a942f86e3ed7a71581751cd8a73e6e27b83ba4ee4b38eea4a3b2.jpg)

Figure 3-18: Multiple I/O Connector Pin Definition

# 3.2.11.1 COM1 RS-232/CCtalk Selection Jumper

<table><tr><td colspan="2">RS-232/CCtalk</td></tr><tr><td>1-3</td><td rowspan="4">RS-232 (default)</td></tr><tr><td>2-4</td></tr><tr><td>7-9</td></tr><tr><td>8-10</td></tr><tr><td>3-5</td><td rowspan="4">CCtalk</td></tr><tr><td>4-6</td></tr><tr><td>9-11</td></tr><tr><td>10-12</td></tr></table>

Table 3-15: COM1 RS-232/CCtalk Selection Jumper

# 3.2.11.2 Case Open Jumper

<table><tr><td colspan="2">Case open</td></tr><tr><td>13-14</td><td>Function ON</td></tr><tr><td>N/A</td><td>Undo (default)</td></tr></table>

Table 3-16: Case Open Jumper

# 3.2.11.3 ME Lock Jumper

<table><tr><td colspan="2">ME Lock</td></tr><tr><td>15-16</td><td>Lock</td></tr><tr><td>N/A</td><td>Undo (default)</td></tr></table>

Table 3-17: ME Lock Jumper

# 3.2.11.4 Clear CMOS Jumper

<table><tr><td colspan="2">Clear CMOS</td></tr><tr><td>17-18</td><td>Clear CMOS</td></tr><tr><td>N/A</td><td>Undo (default)</td></tr></table>

Table 3-18: Clear CMOS Jumper

# 3.2.11.5 BIOS WP Jumper

<table><tr><td colspan="2">BIOS WP</td></tr><tr><td>19-20</td><td>BIOS WP</td></tr><tr><td>N/A</td><td>Undo (default)</td></tr></table>

Table 3-19: BIOS WP Jumper

![The image shows a white document icon with a folded top corner and horizontal lines indicating text. A large, bold red checkmark is overlaid on top of the document.](.dlap-3200-cf-50m-00004-1000-10/1f8fe1e56880b339395ce8a20620079ad0b441371b9cc7ea142f34b7308c6272.jpg)
NOTE:

X S3 and S4 not supported under operating system.
X IAMT is not supported while pairing with Q370.
X BIOS ME version information is shown as “zero”.
X Do not install an operating system when BIOS WP is enabled.
X Intel GbE LAN cannot update the MAC address.
X A special PN/process is needed if the default setting is Write Protect Enabled.

# 3.2.12 Power-on Module Connector

![Pure electrical connector pinout diagram without any text or symbols](.dlap-3200-cf-50m-00004-1000-10/6f0949b090d9d59bf2ffa7b70daffd43f7d851c74bdc38919d0de34c1b685133.jpg)

Figure 3-19: Power-on Module Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V0_A</td><td>9</td><td>LED_TEMP_ALARM</td></tr><tr><td>2</td><td>P_+3V3_A</td><td>10</td><td>GND</td></tr><tr><td>3</td><td>PWR_BTN</td><td>11</td><td>LED_FAN_ALARM</td></tr><tr><td>4</td><td>LED_STANDBY</td><td>12</td><td>GND</td></tr><tr><td>5</td><td>RST_BTN#</td><td>13</td><td>P_+12V_A</td></tr><tr><td>6</td><td>POWER_ON</td><td>14</td><td>GND</td></tr><tr><td>7</td><td>RESET_BUTTON_ALARM#</td><td>15</td><td>BEEP_TEMP_ALARM</td></tr><tr><td>8</td><td>PCH_SATS-L</td><td>16</td><td>GND</td></tr></table>

Table 3-20: Power-on Module Connector Pin Definition

# 3.2.13 DIO Connector

![This is a black-and-white technical line drawing of a vertical rectangular component, likely a connector housing.\n\n*   **Left Edge:** A column of small, semi-circular protrusions or tabs runs along the left vertical edge.\n*   **Main Body:** The central body is a tall rectangle. On its right-facing surface, there are two parallel vertical columns of rectangular slots or holes. Each column contains 14 slots.\n*   **Top and Bottom:** Horizontal lines cap the top and bottom of the rectangular body.\n*   **Label:** To the right of the bottom edge, the number '1' is displayed.](.dlap-3200-cf-50m-00004-1000-10/8b02f5fca6e7e9de098fdd035df71b3f227ddbe5d86a140a1b3018137a2da360.jpg)
Figure 3-20: DIO Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>5V_12V_S</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>DI0</td></tr><tr><td>4</td><td>DI1</td></tr><tr><td>5</td><td>DI2</td></tr><tr><td>6</td><td>DI3</td></tr><tr><td>7</td><td>DO0</td></tr><tr><td>8</td><td>DO1</td></tr><tr><td>9</td><td>DO2</td></tr><tr><td>10</td><td>DO3</td></tr></table>

Table 3-21: DIO Connector Pin Definition

# 3.2.14 12V DC-in Connector

![The image displays a rectangular frame enclosing a grid of six identical robot-like icons arranged in two rows of three. Each icon features a rounded square head containing a smaller square and a central dot, mounted on a rounded rectangular body. To the right of the grid, the number '2' is positioned above the number '1'.](.dlap-3200-cf-50m-00004-1000-10/ea7b3e41e8abac132239e4454c438e2772125da35214a42d374520bb28937267.jpg)
Figure 3-21: 12V DC-in Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>DCIN</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>DCIN</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>DCIN</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>DCIN</td></tr></table>

Table 3-22: 12V DC-in Connector Pin Definition

![The image features a triangular warning sign. It consists of a dark red triangle containing a large white exclamation point. Below the triangle, the text 'WARNING:' is displayed in black capital letters.](.dlap-3200-cf-50m-00004-1000-10/2755246209bbf3717c8e9f43e14f780a1023b419df3e0ccc71d33bd8e5365fc3.jpg)

Before providing DC power, ensure the voltage and polarity provided are compatible with the DC input. Improper input voltage and/or polarity can be responsible for system damage. AVERTISSEMENT: Avant de fournir une alimentation CC, assurez-vous que la tension et la polarité fournies sont compati- bles avec l'entrée CC. Une tension d'entrée et / ou une polarité incorrectes peuvent être responsables de dommages au système.

# 3.2.15 PCB Edge Connector

![Diagram of a vertical spring scale with a coiled spring attached, labeled '1' (no text or symbols on the diagram itself)](.dlap-3200-cf-50m-00004-1000-10/35fef5f92904f4a22a71b28fc76c68b4d5717101b0ae8ca21a3aafbdb9bdb62d.jpg)

Figure 3-22: PCB Edge Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>A1 (Pin 1 on bottom)</td><td>GND</td></tr><tr><td>A2</td><td>P_+12V_S</td></tr><tr><td>A3</td><td>P_+12V_S</td></tr><tr><td>A4</td><td>GND</td></tr><tr><td>A5</td><td>JTAGE_CLK(NC)</td></tr><tr><td>A6</td><td>JTAGE_DI(NC)</td></tr><tr><td>A7</td><td>JTAGE_DO(NC)</td></tr><tr><td>A8</td><td>JTAGE_MS(NC)</td></tr><tr><td>A9</td><td>P_+3V3_S</td></tr><tr><td>A10</td><td>P_+3V3_S</td></tr><tr><td>A11</td><td>PCH_PLTRST-L_BUF</td></tr><tr><td>A12</td><td>GND</td></tr><tr><td>A13</td><td>CLKOUT_PCIE_P7</td></tr><tr><td>A14</td><td>CLKOUT_PCIE_N7</td></tr><tr><td>A15</td><td>GND</td></tr><tr><td>A16</td><td>GF_PCIEX21_RX_P</td></tr><tr><td>A17</td><td>GF_PCIEX21_RX_N</td></tr><tr><td>A18</td><td>GND</td></tr><tr><td>A19</td><td>NC</td></tr><tr><td>A20</td><td>GND</td></tr><tr><td>A21</td><td>GF_PCIEX22_RX_P</td></tr><tr><td>A22</td><td>GF_PCIEX22_RX_N</td></tr><tr><td>A23</td><td>GND</td></tr><tr><td>A24</td><td>GND</td></tr><tr><td>A25</td><td>GF_PCIEX23_RX_P</td></tr><tr><td>A26</td><td>GF_PCIEX23_RX_N</td></tr><tr><td>A27</td><td>GND</td></tr><tr><td>A28</td><td>GND</td></tr><tr><td>A29</td><td>GF_PCIEX24_RX_P</td></tr><tr><td>A30</td><td>GF_PCIEX24_RX_N</td></tr><tr><td>A31</td><td>GND</td></tr><tr><td>A32</td><td>NC</td></tr><tr><td>A33</td><td>NC</td></tr><tr><td>A34</td><td>GND</td></tr><tr><td>A35</td><td>GF_PCIEX1_RX_P</td></tr><tr><td>A36</td><td>GF_PCIEX1_RX_N</td></tr><tr><td>A37</td><td>GND</td></tr><tr><td>A38</td><td>GND</td></tr><tr><td>A39</td><td>GF_PCIEX2_RX_P</td></tr><tr><td>A40</td><td>GF_PCIEX2_RX_N</td></tr><tr><td>A41</td><td>GND</td></tr><tr><td>A42</td><td>GND</td></tr><tr><td>A43</td><td>GF_PCIEX3_RX_P</td></tr><tr><td>A44</td><td>GF_PCIEX3_RX_N</td></tr><tr><td>A45</td><td>GND</td></tr><tr><td>A46</td><td>GND</td></tr><tr><td>A47</td><td>GF_PCIEX4_RX_P</td></tr><tr><td>A48</td><td>GF_PCIEX4_RX_N</td></tr><tr><td>A49</td><td>GND</td></tr><tr><td>B1 (Pin 1 on top)</td><td>P_+12V_S</td></tr><tr><td>B2</td><td>P_+12V_S</td></tr><tr><td>B3</td><td>P_+12V_S</td></tr><tr><td>B4</td><td>GND</td></tr><tr><td>B5</td><td>PCH_SMB_CLK_A</td></tr><tr><td>B6</td><td>PCH_SMB_DAT_A</td></tr><tr><td>B7</td><td>GND</td></tr><tr><td>B8</td><td>P_+3V3_S</td></tr><tr><td>B9</td><td>JTAGE_RST(NC)</td></tr><tr><td>B10</td><td>P_+3V3_S</td></tr><tr><td>B11</td><td>X_PCIE_WAKE-L</td></tr><tr><td>B12</td><td>NC</td></tr><tr><td>B13</td><td>GND</td></tr><tr><td>B14</td><td>GF_PCIEX5_21_TX_P</td></tr><tr><td>B15</td><td>GF_PCIEX5_21_TX_N</td></tr><tr><td>B16</td><td>GND</td></tr><tr><td>B17</td><td>PCH_CLK_REQ7-L</td></tr><tr><td>B18</td><td>GND</td></tr><tr><td>B19</td><td>GF_PCIEX22_TX_P</td></tr><tr><td>B20</td><td>GF_PCIEX22_TX_N</td></tr><tr><td>B21</td><td>GND</td></tr><tr><td>B22</td><td>GND</td></tr><tr><td>B23</td><td>GF_PCIEX23_TX_P</td></tr><tr><td>B24</td><td>GF_PCIEX23_TX_N</td></tr><tr><td>B25</td><td>GND</td></tr><tr><td>B26</td><td>GND</td></tr><tr><td>B27</td><td>GF_PCIEX24_TX_P</td></tr><tr><td>B28</td><td>GF_PCIEX24_TX_N</td></tr><tr><td>B29</td><td>GND</td></tr><tr><td>B30</td><td>NC</td></tr><tr><td>B31</td><td>PCH_CLK_REQ7-L</td></tr><tr><td>B32</td><td>GND</td></tr><tr><td>B33</td><td>GF_PCIEX1_TX_P</td></tr><tr><td>B34</td><td>GF_PCIEX1_TX_N</td></tr><tr><td>B35</td><td>GND</td></tr><tr><td>B36</td><td>GND</td></tr><tr><td>B37</td><td>GF_PCIEX2_TX_P</td></tr><tr><td>B38</td><td>GF_PCIEX2_TX_N</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>B39</td><td>GND</td></tr><tr><td>B40</td><td>GND</td></tr><tr><td>B41</td><td>GF_PCIEX3_TX_P</td></tr><tr><td>B42</td><td>GF_PCIEX3_TX_N</td></tr><tr><td>B43</td><td>GND</td></tr><tr><td>B44</td><td>GND</td></tr><tr><td>B45</td><td>GF_PCIEX4_TX_P</td></tr><tr><td>B46</td><td>GF_PCIEX4_TX_N</td></tr><tr><td>B47</td><td>GND</td></tr><tr><td>B48</td><td>PCH_CLK_REQ7-L</td></tr><tr><td>B49</td><td>GND</td></tr></table>

Table 3-23: PCB Edge Connector Pin Definition

# 3.2.16 DB40 Connector

![Pure electrical connector pinout diagram without any text or symbols](.dlap-3200-cf-50m-00004-1000-10/57b4190bd124c3032eb6dd8fcee62ca0e4d0881c0f3a6f09a2df8a03169d5cec.jpg)

1

Figure 3-23: DB40 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC_SPI_IN</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>SPI_BIOS_CS0#</td></tr><tr><td>4</td><td>SPI_BIOS_CS1#</td></tr><tr><td>5</td><td>SPI_BIOS_MISO</td></tr><tr><td>6</td><td>SPI_BIOS_MOSI</td></tr><tr><td>7</td><td>SPI_BIOS_CLK</td></tr><tr><td>8</td><td>3V3_LPC</td></tr><tr><td>9</td><td>GND</td></tr><tr><td>10</td><td>BIOS_DIS0</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>11</td><td>RST#</td></tr><tr><td>12</td><td>CLK33_LPC</td></tr><tr><td>13</td><td>LPC_FRAME#</td></tr><tr><td>14</td><td>LPC_AD3</td></tr><tr><td>15</td><td>LPC_AD2</td></tr><tr><td>16</td><td>LPC_AD1</td></tr><tr><td>17</td><td>LPC_AD0</td></tr><tr><td>18</td><td>3.3V_SMC</td></tr><tr><td>19</td><td>3.3V_A</td></tr><tr><td>20</td><td>GND</td></tr><tr><td>21</td><td>TXD6</td></tr><tr><td>22</td><td>RXD6</td></tr><tr><td>23</td><td>FUMD0</td></tr><tr><td>24</td><td>RESET_IN#</td></tr><tr><td>25</td><td>DATA</td></tr><tr><td>26</td><td>CLK</td></tr><tr><td>27</td><td>OCD0A</td></tr><tr><td>28</td><td>OCD0B</td></tr><tr><td>29</td><td>PWRBTN#</td></tr><tr><td>30</td><td>SYS_RESET#</td></tr><tr><td>31</td><td>CB_RESET#</td></tr><tr><td>32</td><td>CB_PWROK</td></tr><tr><td>33</td><td>SUS_S3#</td></tr><tr><td>34</td><td>SUS_S4#</td></tr><tr><td>35</td><td>SUS_S5#</td></tr><tr><td>36</td><td>POSTWDT_DIS#</td></tr><tr><td>37</td><td>SEL_BIOS</td></tr><tr><td>38</td><td>BIOS_MODE</td></tr><tr><td>39</td><td>SMC_STATUS</td></tr><tr><td>40</td><td>RESVD</td></tr></table>

Table 3-24: DB40 Connector Pin Definition

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# 4 Getting Started

This chapter outlines the procedures for 2.5" storage, M.2 module, MXM module, wall-mount brackets, and driver installation.

![The image displays a standard warning sign. It features a red triangle with a white exclamation point in the center. Below the triangle, the word 'WARNING' is printed in black capital letters on a white background.](.dlap-3200-cf-50m-00004-1000-10/3bd38767fba8d0fe30c01104c42435e78a7d4890a00e8d79805fa8d4822f536d.jpg)

Installation of an add-on device must be carried out by ADLINK service personnel only. Users must not disassemble the device themselves.

Avertissement! L'installation d'une carte d'extension PCIe doit être effectuée uniquement par le personnel de service ADLINK. Les utilisateurs ne doivent pas démonter l'appareil eux-mêmes

![The image displays a standard yellow triangular warning sign containing a large black exclamation mark in the center. Directly beneath the triangle, the word 'CAUTION:' is printed in black capital letters.](.dlap-3200-cf-50m-00004-1000-10/a374c34893c122d81ced1ded2c3099aeb0b51ff2775f0f110ae88a9997ec4358.jpg)

Disconnect the unit from power before opening the chassis, or installing any internal components. See “Important Safety Instructions” on page 135.

ATTENTION: Débranchez l'unité de l'alimentation avant d'ouvrir le châssis ou d'installer des composants internes.

# 4.1 Installing 2.5” Storage

Before installing a disk drive, the drive bracket must be removed.

1. Remove the thumbscrews and take out the 2.5” drive bay.

![COM 1\nU8\nU14\nUS\nU8\nLAN 4\nLAN 1\nDP 1\nU3\nU1\nDN A\nDP C\nDC-IN\nCOM 2\nDP 2\nLAN 2\nU4\nU2\nDP B\nDP D\nBay 1\nBay 2\nADLINK](.dlap-3200-cf-50m-00004-1000-10/ecf44fce8f89e4fabaa3ad4ad5e6c0b6b132647483d16d3318ae431214e8adcf.jpg)

2. Place a 2.5” SSD up to 9mm thick into the bracket and use the 4 provided M3 screws at 4kgf/cm torque to attach the drive to the bracket.

![Technical line drawing of a mechanical device with multiple wheels and mounting holes (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/7d6473391e45643a79a5b6260120e579fdf96e0e7fb04a3bdca60e4b573a85ba.jpg)

3. Gently slide the bracket back into the drive bay until the SATA connector on the PCB is engaged, and then refasten the thumbscrews.

# 4.2 Installing an M.2 Module

Remove the bottom panel before installing an M.2 Module.

1. Remove 10 screws total to release the bottom panel from the chassis: 4 on the bottom, 2 on the left side, and 4 on the right side.

Bottom screws
![DLAP-320C-CF\nADLINK\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nPLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SM32G/1TB\nSLA-320C-CF/SAV/SM32G/1TB\nSLA-320C-CF/SAV/SM32G/1TB\nSLA-320C-CF/SAV/SM32G/1TB\nSLA-320C-CF/SAV/SM32G/1TB\nSLA-320C-CF/SAV/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nSLA-320S/CF/SM32G/1TB\nALDLINK\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-CFP/SM32G/1TB\nPLA-320C-SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SSOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCC/SSOCCCCSOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSCCCCOSFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFFFSSOCFFCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCSOCFGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGCGTCOGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCGGTCAGTGCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTCTTAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAAGTTAAUGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAAAAGGTAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCAACCATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATGAATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGCATTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGACTGATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA GATA AUC TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUG TUN TGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TGTTTAG TG TTU TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA TA AA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA GA CA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SA SAV CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CC AS SAV CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CCAS CC AS SIV TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCX TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TC x TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx TCx SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SCX SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC X SC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VSC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFC VFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVFCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCVCPCVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCPVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCFVGCM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGM CGN CTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTSG CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CNTGS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCTS CCT SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SOST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUST SUT B U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U UU A B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB(ecel)(nl)](.dlap-3200-cf-50m-00004-1000-10/3893885cce7d00aa47da33bb4ea4e7054dda0722e7bcab719a571be8b07821cd.jpg)

Left side screws
![Close-up of a black electronic device casing with a circular vented pattern and two red circular markers on the side (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/9c5ccd5b94c07479b20927550d8f68fb1d5dddfdc593cb26b457317fb23c69a4.jpg)

Right side screws
![Front view of a server rack with ventilation grilles and two red circular annotations highlighting ports (no text or symbols present)](.dlap-3200-cf-50m-00004-1000-10/1dbf567a59d70c56627b139eed475270ca1141f4710c5359425232359e6d3c98.jpg)

2. Apply the minimum amount of pressure necessary to slide the panels apart in the directions shown to reveal the internal contents of the unit.

![0.47.100 C#P#N5197\nADJLNK\nDVR 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-08\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-03-\n© 2000-04](.dlap-3200-cf-50m-00004-1000-10/e4815830a89d131e9ba9db8a92240467aff6f679cff6f20bde61ee63674a94ef.jpg)

![Interior view of a computer drive bay with exposed circuit board, RAM slots, and power cord (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/2c370ca56bd67bbebe1a372a7000eefd079b350c2616306888adba28694677d2.jpg)

3. Remove the 4 screws attaching the left drive bay to the chassis.

![Interior view of a computer drive bay with visible CPU socket, RAM slots, and cable connections (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/9b390e6aafebb73720eeea4865530d72368dc28bc97b6c9822698555fc0d79b5.jpg)

4. Move the drive bay to reveal the M.2 socket underneath and install an M.2 module with an M3 screw at 4kgf/cm torque. (P/N: 33-03013-0040)

Z M.2 E-key module: Wi-Fi Kit Intel® Wireless-AC 9260 non-vPRO (P/N: 91-95266-0020)
Z M.2 M-key module example: M.2 PCIe Gen3 x4 SSD 128G PS5012-E12 M.2 2280 (P/N: 95-31102-4310)
Z M.2 B-key module example: 4G Module EM06-A Kit (M.2 B Key) with Antenna (P/N: 91-95284-000E). A 4G module needs to be used with the DLAP-3200-CF with an eSIM SKU. Contact an ADLINK sales representative for more information.

![B key\nM key\nE key](.dlap-3200-cf-50m-00004-1000-10/6fd6d65ca98dcd86fbbaec2446d2f2de49baaa39ac91fdcb5997cc37c65a2797.jpg)

5. The antenna cables of the M.2 B-key and E-key modules are installed as shown in the figures below. For improved cable management, route the M.2 B-key cables under the drive bay support plate before making the antenna connections.

![Interior view of an electronic device showing a circuit board with components and wiring (no readable text or symbols)](.dlap-3200-cf-50m-00004-1000-10/f1342b856c8675adbcbf5b4060cff151f232ba8edf199bf21ae384f2c7807f05.jpg)

![B-key line out\nE-key line out](.dlap-3200-cf-50m-00004-1000-10/2b5b8bb420ef604be441364b5782b2bf91a2e2173057e35e74bcfe17a858c7e7.jpg)

Make sure the antenna wires are properly soldered to the M.2 Bkey and E-key modules.

![QURECTEL\nEM06-E\nL1A EM06E1A-512-8S4A\nSD220080600\nCE\nIC4-A-C-OUI-3-NO9-E\nCCAF1940024072\nEN-MAP203E106001715\nW31B566800403512724\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nG\nM](.dlap-3200-cf-50m-00004-1000-10/d14ab48f7f07317d99a3a2b84dd397e6f5850e0ff7ac4a8b8e46990def9f80b9.jpg)

6. The figure below shows the locations of the M.2 B-key and E-key module antenna cable connections.

![B-key E-key B-key E-key](.dlap-3200-cf-50m-00004-1000-10/42bca23807d6600a42bfb037ea0e1b5431471b42797b234200cff4d9beed3b93.jpg)

7. Attach the antenna cable connectors and the drive bay screws at 6kgf/cm torque.

![B-key\nE-key\nB-key\nE-key](.dlap-3200-cf-50m-00004-1000-10/6c1d4d6904476e98cb44c9a97ea0023e1ea261ea8560da35261563448cf22a04.jpg)

![Interior view of a computer drive bay with visible circuitry and connectors (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/bf045304b167b5cc07b1d2952e7986b90b621b41c7642a58e431a1cf04ed60a1.jpg)

8. After reinstalling the left and right side covers, fasten all the screws at 6kgf/cm torque.

![Ours 2000 C#N/19\nQR code: 2000 C#N/19\nADJUNIC\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#N/19\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2000 C#\n© 2](.dlap-3200-cf-50m-00004-1000-10/333bf402c2822be944c2b95991ebdb3e9daae706782d1c8c957fdfae1235af90.jpg)

Right side screws
![Front view of a black server rack with ventilation grilles and two red circular annotations highlighting ports (no text or symbols present)](.dlap-3200-cf-50m-00004-1000-10/683eba8a22136ccb150090ab7492104e0f08a0d36ae2d9af0b6bfbb7cac3dd78.jpg)

Left side screws
![Close-up of a black electronic device casing with a circular patterned panel and two red-circled pins (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/c61455b3ed633a86e0d46b44b7722e20d43b4575ab41352b9e5a6dc9ae0bd8cb.jpg)

Bottom screws
![DLAP-320C-CF\nADLINK\nPLA5 16800000000000000000000000000000000000000000000000000000000000000000000000000000000000\nDLAP-320C-CFP5M32G1TB\nPLA5 1680000000000000000\nCE FC\nPLA5 168000000000000000\nCE FC\nPLA5 16800000000000000\nCE FC\nPLA5 1680000\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16817TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 16824TB TLE\nPLA5 2333333333333333333333333333333333333333333333333333333333333333333333333333333333333333](.dlap-3200-cf-50m-00004-1000-10/f7aedbbe1f7011542033330843a2ca64882d9d1e8f9adf66826c3eadb094b8ae.jpg)

# 9. Install and lock the antennas as shown.

![B key\nE key\nB key\nE key](.dlap-3200-cf-50m-00004-1000-10/165774d238d2e5a7b5167303cfe2db67de33ee15ce08760b30244505427fa36b.jpg)

![Black cylindrical device with label 'SO 10Cr' on white background (no other text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/68c16292b917eb0b32c90c4e94f5806a81664fc5482ab4a915f1ad4775bfd21a.jpg)

B key

![Black cylindrical object with a protruding rod, isolated on white background (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/4831bbfbf48b745ce76f278e709b1d953afbeb16b86ed9ded97290205cef207a.jpg)

E key

# 4.3 Installing MXM P1000/P2000/T1000 Module

1. Remove the protective film from the MXM cooler.

![Close-up of a microchip with blue and gray components, no visible text or symbols](.dlap-3200-cf-50m-00004-1000-10/aa929297fbef693af13086872cbbf0fe08a5034208564fb45717868e8d296d07.jpg)

2. Attach the MXM cooler to the MXM module. Tighten the screws in the order indicated at 4kgf/cm torque.

![1\n3\n4\n2\n5/N:\n51-7C000-0A10\nEGX-MXM-P1000\nADLINK](.dlap-3200-cf-50m-00004-1000-10/6dd9b7855fa3cdc6d59d197f3b487dc2e7c15c416e2541ccad2e8fba23fc7a78.jpg)

3. Remove 2 screws to detach the top panel from the chassis. Remove the top panel to reveal the internal components of the system.

![3D diagram of an open computer chassis showing internal components and ports (no text or labels visible)](.dlap-3200-cf-50m-00004-1000-10/4b32bf1cf5c1b021be529bd8931ed79a0daabaa7399d542829c6a26a496bccac.jpg)

4. Attach the MXM module with 2 M3 screws P/N: 33- 03306-0040 at 4kgf/cm torque and plug the MXM cooling fan connector into the GPU fan connector.

![Technical diagram of an internal computer drive with labeled components and parts](.dlap-3200-cf-50m-00004-1000-10/cd28da9b02282a9426719320b43bc7eb37ffff98e023064aa3b84470b8347c8f.jpg)

5. Screw the top panel back on to complete the installation.

# 4.4 Installing MXM P3000/P5000/RTX3000/RTX5000 Module

1. Remove 2 screws to detach the top panel from the chassis and reveal the internal components of the system.

![3D diagram of an open computer rack with labeled ports and connectors, showing internal components and mounting points (no text or symbols present)](.dlap-3200-cf-50m-00004-1000-10/873aed6cbbcbcffb037b381d70678d4cf71a79e5794274e55cdf1d1a8e69ee9d.jpg)

2. Remove the protective film from the MXM cooler bracket and attach the MXM bracket to the bottom side of the MXM module.

![Technical diagram of an electronic circuit board with red annotations highlighting specific components (no text or symbols present)](.dlap-3200-cf-50m-00004-1000-10/5d208b2e9e581cd6bcbba5390ad82bf876916adab464aee5d0316a168670501c.jpg)

# 3. Attach the MXM module with 2 M3 screws

P/N: 33-03306-0040 at 4kgf/cm torque to the mainboard.

![Technical diagram of an electronic device rear panel with labeled components and highlighted parts](.dlap-3200-cf-50m-00004-1000-10/6820419f02f73c51f3fb6b1b571dfbaf5bab81172611d482305f7ad0395e0439.jpg)

4. Remove the protective film from the MXM cooler and lock the MXM cooler on the MXM module via the four spring screws. Then plug the MXM cooling fan connector into the GPU fan connector.

![1\n2\nFan Connector\n3\n4](.dlap-3200-cf-50m-00004-1000-10/9d09abb33b61b04ae1a5621c42edd60b0e0ec30d87827174e9e9cb27ac73f9e6.jpg)

5. Place 4 washers PN: 33-90086-0000-A0 and 4 rubber spacers PN: 39-00039-0000 over the screw holes on the top of the fan.

![Technical diagram of an AOSLink computer drive showing internal components and labeled ports](.dlap-3200-cf-50m-00004-1000-10/305eec5a116c2468cabf22c50b30ef710c13e35b16ceabd91cae75196ee083ad.jpg)

6. Use 4 screws PN: 33-03320-0050 to secure the rubber spacers to the fan at 4kgf/cm torque.

![Technical diagram of an electronic device rear panel with labeled ports and connectors, showing internal components like CPU, fan, and drive connections.](.dlap-3200-cf-50m-00004-1000-10/b7524a5b4665223e0d6c86eb7d5269fad4ccbbaa4daebf4f2369ce7e4e351849.jpg)

7. Screw the top panel back on at 6kgf/cm torque to complete the installation.

# 4.5 Installing a PCIe x4 Add-on Card

1. Remove 2 screws to detach the top panel from the chassis.

![3D rendering of a computer tower rear panel with labeled ports and connectors (no readable text or symbols)](.dlap-3200-cf-50m-00004-1000-10/a589d17f6ebe7b3541672a562230cfd1cbf926bf721af7f1e1f48be6bee1759b.jpg)

![3D CAD rendering of an electronic device chassis showing internal components and ports (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/a440fdd56476a7367cdeb72ea1c70f3da6712a2a5081931a80cf3dd4fe1a99a9.jpg)

2. Remove the 2 screws attaching the fan bracket to the chassis and disconnect the fan cable.

![Interior view of an electronic device showing internal components including a fan, CPU socket, and drive bays (no text or labels visible)](.dlap-3200-cf-50m-00004-1000-10/2a3a1e8fe9e8d68e78722cb5d5ab9d4b6f44d2fdeb6b7ba5fcf8625955991abe.jpg)

3. Remove the 8 screws attaching the BM cover to the chassis.

![3D CAD model of a computer tower with visible drive bays and ports (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/cf4764902f11b4ac25185d8d6cba81461198e52311b987120ab899aa61c9475b.jpg)

# 4. Remove the BM cover.

![3D CAD rendering of an electronic device chassis showing internal components and a highlighted fan (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/01f6302e2ef6941ee721b909c5c6078bd56b352258b01700abaad36410ec9120.jpg)

# 5. Remove the fan.

![3D technical illustration of a computer tower with fan, drive, and internal components (no text or symbols)](.dlap-3200-cf-50m-00004-1000-10/bef5daa899d738abc2b7de2a3251725b0be88cb7abb595b12c471e6c845e0a14.jpg)

6. Remove the 2 screws connecting the PCIe bracket.

![3D CAD model of an ADLINK computer chassis showing internal components and ports (no readable text or symbols)](.dlap-3200-cf-50m-00004-1000-10/6d72f1710031e09ab3b08ee8b2e513b26fb57e49ac073b87dcdcbd20cbe44ed2.jpg)

7. Remove the PCIe bracket.

![3D CAD model of an electronic device chassis showing internal components and ports (no text or symbols visible)](.dlap-3200-cf-50m-00004-1000-10/257e856a74d7eac9840c6846d29e2a5fc22abe53d5815b697dac7bc617431260.jpg)

8. Install a PCIe x4 add-on card and tighten the lock screw at 6kgf/cm torque.

![3D CAD rendering of an internal electronic device with labeled ports and connectors (no readable text or symbols)](.dlap-3200-cf-50m-00004-1000-10/8ec6471cb1ee0ebd9a656f18d4baefa08231bad4d0ee8a26b7573ebd9ae6f3db.jpg)

9. Reinstall the fan, connect the fan power cable and tighten the screws at 6kgf/cm torque.

![3D rendering of an electronic device chassis with labeled ports and a fan blade (no readable text or symbols)](.dlap-3200-cf-50m-00004-1000-10/823af7c94ba7caf01b6b8fd77db4950b0dac23cf17f84745da294191a2fa4e30.jpg)

10.Attach the bottom cover and tighten the screws at 6kgf/ cm torque.

![check docking\ncheck docking](.dlap-3200-cf-50m-00004-1000-10/2e727ae44516385fbc83625b0e794a78fce1ecfc072e323f6376e6580049527f.jpg)

11.Attach the BM and top covers and tighten the screws at 6kgf/cm torque.

# 4.6 Mounting

# 4.6.1 Install the Wall-mount Brackets

Use the 4 footpad screws to attach the 2 wall-mount brackets to the chassis.

Utilisez les 4 incluses dans la boîte d'accessoires pour fixer les 2 supports de montage mural inclus au châssis.

![Wall-mount Bracket\nWall-mount Bracket](.dlap-3200-cf-50m-00004-1000-10/9fbabdba114528f490c9bebdfa93232092514f9602439962c41233875c7fec34.jpg)

# Mounting the Device / Montage de l'Appareil

Mount the device to a wall using the 4 keyhole openings indicated with M4 6mm screws torqued to 6kgf/cm, or the 6 mounting holes circled, according to the spacing dimensions of the holes in the bracket as shown in Figure 2-6 DLAP-3200-CF Top View.

Montez l'appareil sur un mur à l'aide des 4 ouvertures de trou de serrure en fonction des dimensions d'espacement des trous dans le support, comme indiqué dans Figure 2-6 DLAP-3200-CF Top View.

![Keyhole opening\nKeyhole opening](.dlap-3200-cf-50m-00004-1000-10/3c60e7b44f5432b84db51e3f6bc1c6b08d693cb7097268507d37c170d7f1122a.jpg)

# 4.7 Driver Installation

Download the Windows 10 drivers from the product page at https://www.adlinktech.com/Products/Industrial\_PCs\_Fanless\_ Embedded\_PCs/IPCSystems/DLAP-3200-CF\_Series.

The following drivers must be installed:

X Intel GPU
X Chipset
X ME
X LAN
X Audio (There are two different codec drivers. Check the audio device after driver installation.)
X MXM
X DIO
X RAID

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# Appendix A Power Consumption

![The image displays a document icon featuring a white sheet of paper with faint, horizontal grey lines. Superimposed over the center of the paper is a large, bold, red checkmark.](.dlap-3200-cf-50m-00004-1000-10/eab471025a5b4b6f7abd3ec221036fb3e468547652a7c1be2a3899bae0e6dfa5.jpg)
NOTE:

Information in this Appendix is for power budget planning and design purposes only. Actual power consumption may differ based on final application.

# A.1 Power Consumption Reference

Power consumption as follows is based on lab data in which 12V DC is applied and current is measured by the DC power supply. The power consumption (W) is calculated as the product of applied voltage (V) and the current (A).

Platforms tested for this data have available external I/O interfaces, and are attached to supported devices such as keyboard/ mouse, USB dummy load, COM loopback, LAN port, PCIe add-on card, and with an internal SSD driver installed.

Information is presented for reference only. Actual power consumption will vary with different attached devices and operating system.

<table><tr><td>DLAP-3200</td><td>Power Consumption</td></tr><tr><td>65W CPU/RTX5000 Full loading</td><td>365W</td></tr><tr><td>65W CPU/RTX3000 Full loading</td><td>335W</td></tr><tr><td>65W CPU/T1000 Full loading</td><td>305W</td></tr><tr><td>65W CPU/P5000 Full loading</td><td>355W</td></tr><tr><td>65W CPU/P3000 Full loading</td><td>330W</td></tr><tr><td>65W CPU/P2000 Full loading</td><td>313W</td></tr><tr><td>65W CPU/P1000 Full loading</td><td>302W</td></tr><tr><td>35W CPU/RTX5000 Full loading</td><td>335W</td></tr><tr><td>35W CPU/RTX3000 Full loading</td><td>305W</td></tr><tr><td>35W CPU/T1000 Full loading</td><td>275W</td></tr><tr><td>35W CPU/P5000 Full loading</td><td>325W</td></tr><tr><td>35W CPU/P3000 Full loading</td><td>300W</td></tr><tr><td>35W CPU/P2000 Full loading</td><td>283W</td></tr><tr><td>35W CPU/P1000 Full loading</td><td>272W</td></tr></table>

Table A-1: DLAP-3200 Power Consumption

![The image displays a graphic icon of a white document featuring faint horizontal lines and a folded top-right corner. A large red checkmark is superimposed over the center of the document.](.dlap-3200-cf-50m-00004-1000-10/6fd9a80c7457e371c2cc1d0786aceafe02ef3b24ea926c1b60bd0d469b3e59bc.jpg)
NOTE:

Sufficient power for the entire system is required to meet these specifications. We recommend using a DC source instead of the optional 240W adaptor when power consumption is over 240W in an environmentwhere the temperature is $4 0 ^ { \circ } \mathsf { C }$ .
Heat generated by add-on PCIe adapters affects thermal stability. Additional heat dissipation is required when the system operates at high temperatures or in harsh environments with add-on adapters.

# Appendix B Resource Mapping

# B.1 BIOS Mapping in SPI ROM

The chipset supports up to three SPI ROMs (SPI\_CS0#, SPI\_CS1# and SPI\_CS2#). The motherboard uses SPI flash SPI\_CS0# to select the SPI flash which stores ME firmware and the system BIOS. The size of the SPI ROM is 16MB for H310, and 32MB for Q370 chipsets.

From a software standpoint, the serial peripheral interface (SPI) resides in the memory mapped space. This function contains registers that allow for the setup and programming of devices that reside on the SPI interface. The physical SPI ROM can be accessed by putting an address into the flash address register.

The motherboard SPI ROM mapping is as below.

<table><tr><td>Region</td><td>Size</td></tr><tr><td>Descriptor</td><td>4 KB</td></tr><tr><td>ME</td><td>8 MB - 4 KB</td></tr><tr><td>BIOS</td><td>8 MB</td></tr></table>

# B.2 PCI/PCIe Devices

The following table lists all PCI/PCIe devices in the system.

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>0</td><td>0x00</td><td>0</td><td>N/A</td><td>Intel Host Bridge - 6 Cores/Desktop</td></tr><tr><td>0</td><td>0x02</td><td>0</td><td>Internal</td><td>IGFX - GT2/6 Cores/Desktop</td></tr><tr><td>0</td><td>0x01</td><td>0</td><td>Internal</td><td>PEG Root Port D1F0</td></tr><tr><td>0</td><td>0x12</td><td>0</td><td>Internal</td><td>Thermal Subsystem</td></tr><tr><td>0</td><td>0x14</td><td>0</td><td>Internal</td><td>USB 3.1 xHCI HC</td></tr><tr><td>0</td><td>0x14</td><td>2</td><td>Internal</td><td>Shared SRAM</td></tr><tr><td>0</td><td>0x15</td><td>0</td><td>Internal</td><td> $I^{2}C$  Controller #0</td></tr><tr><td>0</td><td>0x15</td><td>1</td><td>Internal</td><td> $I^{2}C$  Controller #1</td></tr><tr><td>0</td><td>0x16</td><td>0</td><td>Internal</td><td>HECI #1</td></tr><tr><td>0</td><td>0x17</td><td>0</td><td>Internal</td><td>SATA Controller (AHCI)</td></tr><tr><td>0</td><td>0x1C</td><td>0</td><td>Internal</td><td>PCI Express Root Port #1</td></tr><tr><td>0</td><td>0x1D</td><td>0</td><td>Internal</td><td>PCI Express Root Port #9</td></tr><tr><td>0</td><td>0x1D</td><td>3</td><td>Internal</td><td>PCI Express Root Port #12</td></tr><tr><td>0</td><td>0x1E</td><td>0</td><td>Internal</td><td>UART #0</td></tr><tr><td>0</td><td>0x1F</td><td>0</td><td>Internal</td><td>LPC Controller</td></tr><tr><td>0</td><td>0x1F</td><td>3</td><td>Internal</td><td>Intel® High Definition Audio Interface</td></tr><tr><td>0</td><td>0x1F</td><td>4</td><td>Internal</td><td>SMBus Controller</td></tr><tr><td>0</td><td>0x1F</td><td>5</td><td>Internal</td><td>SPI (flash) Controller</td></tr><tr><td>0</td><td>0x1F</td><td>6</td><td>Internal</td><td>GbE Controller</td></tr></table>

![The image displays a white document icon with a folded upper-left corner and distinct horizontal black lines suggesting text. A large red checkmark is superimposed diagonally over the document.](.dlap-3200-cf-50m-00004-1000-10/dc5ec167e2356785e6644351e184f1819b2b21de0943d8ebde9aebb9203ce69e.jpg)
NOTE:

The bus number changes if a PEG/PCIe port has a bridge device attached.

# B.3 IRQ Lines (APIC Mode)

The following table lists the IRQ line mapping when APIC mode is enabled.

<table><tr><td>IRQ #</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard Controller</td><td>N/A</td><td>No</td></tr><tr><td>2</td><td>Cascade Interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>5</td><td>N/A</td><td>IRQ5 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>6</td><td>N/A</td><td>IRQ6 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>7</td><td>N/A</td><td>IRQ7 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>8</td><td>Real-Time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>Generic</td><td>N/A</td><td>No</td></tr><tr><td>10</td><td>N/A</td><td>IRQ10 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>11</td><td>N/A</td><td>IRQ11 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>12</td><td>N/A</td><td>IRQ12 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>No</td></tr><tr><td>14</td><td>Generic</td><td>N/A</td><td>No</td></tr><tr><td>15</td><td>N/A</td><td>N/A</td><td>No</td></tr><tr><td>16-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Yes</td></tr></table>

# B.4 IRQ Lines (PIC Mode)

The following table lists the IRQ line mapping when APIC mode is disabled.

<table><tr><td>IRQ #</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard Controller</td><td>N/A</td><td>No</td></tr><tr><td>2</td><td>Cascade Interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>5</td><td>N/A</td><td>IRQ5 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>6</td><td>N/A</td><td>IRQ6 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>7</td><td>N/A</td><td>IRQ7 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>8</td><td>Real-Time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>Generic</td><td>N/A</td><td>No</td></tr><tr><td>10</td><td>N/A</td><td>IRQ10 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>11</td><td>N/A</td><td>IRQ11 via SERIRQ/PIRQ</td><td>See note.</td></tr><tr><td>12</td><td>N/A</td><td>IRQ12 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>No</td></tr><tr><td>14</td><td>Generic</td><td>N/A</td><td>No</td></tr><tr><td>15</td><td>N/A</td><td>N/A</td><td>See note.</td></tr></table>

![The image displays a digital icon of a document. It features a white sheet of paper with a folded top-right corner and faint horizontal lines running across the lower portion. A large, bold red checkmark is superimposed diagonally over the center of the paper. There is no actual text visible.](.dlap-3200-cf-50m-00004-1000-10/d71c35e9004417325c4a48f68a7ef15bab4507185ada20c0a2ba18e81df78f35.jpg)
NOTE:

The IRQs can be used for PCI devices when the onboard device is disabled.

# B.5 System Memory Mapping

The following table lists the system memory mapping.

<table><tr><td>Address Range (Decimal)</td><td>Address Range (Hex)</td><td>Size</td><td>Description</td></tr><tr><td>(4GB – 2MB)</td><td>FFE00000 – FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB – 18MB) – (4GB –17MB – 1)</td><td>FEE00000 – FEEFFFFFF</td><td>1 MB</td><td>MSI Interrupt</td></tr><tr><td>(4GB – 20MB) – (4GB – 19MB – 1)</td><td>FEC00000 – FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB – 16MB</td><td>F00000 – FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>1MB – 15MB</td><td>100000 – EFFFFF</td><td>14 MB</td><td>Main Memory</td></tr><tr><td>0K – 1MB</td><td>00000 – FFFFF</td><td>1 MB</td><td>DOS Compatibility Memory</td></tr></table>

# B.6 System I/O Mapping

The following table lists the system I/O mapping.

<table><tr><td>I/O Range (Hex)</td><td>Device</td></tr><tr><td>020h – 02Dh &amp; 030h – 03Dh</td><td>Interrupt controller 1, 8259 equivalent</td></tr><tr><td>02Eh – 02Fh</td><td>Motherboard resource</td></tr><tr><td>040h – 043h &amp; 050h – 053h</td><td>System Timer</td></tr><tr><td>04Eh – 04Fh</td><td>Motherboard resource</td></tr><tr><td>060h, 062h, 064h, 066h, 068h – 06Fh</td><td>8042 equivalent (keyboard)</td></tr><tr><td>061h, 063h, 065h, 067h</td><td>NMI control and status</td></tr><tr><td>070h – 077h</td><td>Real Time Clock Controller(bit 7 – NMI mask)</td></tr><tr><td>092h</td><td>Reset(Bit 0)/Fast Gate A20 (Bit 1)</td></tr><tr><td>0A0h – 0B1h &amp; 0B4h – 0BDh</td><td>Interrupt Controller 2, 8259 equivalent</td></tr><tr><td>0B2h and 0B3h</td><td>APM control and status port</td></tr><tr><td>0E0h – 0EFh</td><td>Available</td></tr><tr><td>0F0h</td><td>Co-processor error register</td></tr><tr><td>2F8h – 2FFh</td><td>Serial Port 2</td></tr><tr><td>3F8h – 3FFh</td><td>Serial Port 1</td></tr><tr><td>378h – 37Fh</td><td>Available</td></tr><tr><td>380h – 3AFh</td><td>Available</td></tr><tr><td>4D0h</td><td>Master PIC Edge/Level Trigger register</td></tr><tr><td>4D1h</td><td>Slave PIC Edge/Level Trigger register</td></tr><tr><td>0A00h – 0A2Fh</td><td>Reserved for SIO functions base address (e.g. PME/GPIO etc.)</td></tr><tr><td>0CF8h – 0CFBh</td><td>PCI configuration address register(32-bit I/O only)</td></tr><tr><td>0CF9h</td><td>Reset Controller register (8-bit I/O)</td></tr><tr><td>0CFCh – 0CFFh</td><td>PCI configuration data register</td></tr><tr><td>1800h</td><td>PM (ACPI) Base Address for SB</td></tr></table>

# B.7 PCI/PCIe Interrupt Routing Mapping

# B.7.1 Internal Devices

<table><tr><td>INT Line</td><td>Audio Controller</td><td>xHCI Controller</td><td>TXE Controller #1</td><td>LPC Controller</td><td>SATA Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTA: 16</td><td>INTA: 16</td><td>INTA: 16</td><td>INTA: 16</td><td>INTA: 16</td><td>INTA: 16</td></tr><tr><td>Int1</td><td></td><td>INTB: 17</td><td>INTB: 17</td><td>INTB: 17</td><td></td><td></td></tr><tr><td>Int2</td><td></td><td>INTC: 18</td><td>INTC: 18</td><td>INTC: 18</td><td></td><td></td></tr><tr><td>Int3</td><td></td><td>INTD: 19</td><td>INTD: 19</td><td>INTD: 19</td><td></td><td></td></tr></table>

# B.7.2 PCIe Root Ports

<table><tr><td>INT Line</td><td>PCIe Port 1</td><td>PCIe Port 5</td><td>PCIe Port 6</td><td>PCIe Port 11</td><td>PCIe Port 17</td><td>PCIe Port 21</td></tr><tr><td>Int0</td><td>INTA: 16</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTA: 16</td><td>INTA: 16</td></tr><tr><td>Int1</td><td>INTB: 17</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTB: 17</td><td>INTB: 17</td></tr><tr><td>Int2</td><td>INTC: 18</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTC: 18</td><td>INTC: 18</td></tr><tr><td>Int3</td><td>INTD: 19</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTD: 19</td><td>INTD: 19</td></tr></table>

# B.8 SMBus Slave Address Mapping

The following table lists the SMBus slave address (8-bit addressing) mapping.

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMM A</td><td>0A0h</td></tr><tr><td>DIMM B</td><td>0A4h</td></tr><tr><td>BMC</td><td>050h</td></tr><tr><td>NXP</td><td>0C0h</td></tr></table>

# Appendix C BIOS Setup

BIOS can be configured via the BIOS Setup Utility that is invoked during BIOS boot phase. The BIOS configuration is kept in NVRAM which is the same hardware part where the BIOS is stored. All settings will remain after the system is powered down.

# C.1 BIOS Setup Menu

The BIOS Setup Utility is invoked by pressing &lt;ESC&gt; or &lt;DEL&gt; when the system boots. A system reboot is required when changes are made in the BIOS setup utility.

The BIOS Setup Utility includes the following hotkeys.

X &lt;F1&gt;: General help
X &lt;F8&gt;: Load previous BIOS values
X &lt;F9&gt;: Load BIOS default values
X &lt;F10&gt;: Save & Exit the setup utility

# Menu Selection Bar

The Menu Selection Bar is located at the top of the screen. It displays the top level menus available to the user.

X Main Menu
X Advanced Menu
X Chipset Menu
X Security Menu
X Boot Menu
X Save & Exit Menu

# Menu Conventions

The appearance of the setup menus and items listed in this chapter are based on a VT100 terminal connection via serial console with the following menu conventions.

X Using color
The default BIOS setup fields are in black. The BIOS setup fields currently not used are in grey. The display strings are in black.
X Using brackets

Editable menu options are marketed with square brackets, ‘[‘ and ‘]’.

# C.2 Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following tables as a quick reference for the contents of the BIOS Setup Utility. The remainder of this chapter describe the submenus and options for each menu item. The default settings are presented in bold, and the function of each setting is described in the right hand column of the table.

<table><tr><td>Main</td><td>Advanced</td></tr><tr><td>- BIOS Information- System Information- Processor Information- Memory Information- PCH Information- Board Information▶- System Date- System Time- Access level</td><td>- CPU Configuration ▶- Graphics Configuration ▶- Power Management ▶- System Management ▶- Thermal Management ▶- Watchdog Timer ▶- Super IO Configuration ▶- Serial Console Redirection ▶- Trusted Computing ▶- S5 RTC Wake Settings ▶- NVMe Configuration ▶- Network Stack Configuration ▶- RAM Disk Configuration ▶- Network Configuration ▶</td></tr></table>

<table><tr><td>Chipset</td><td>Security</td></tr><tr><td>- System Agent (SA) Configuration ▶- PCH-IO Configuration ▶</td><td>- Password Description- Administrator Password- User Password- Secure Boot menu ▶</td></tr></table>

<table><tr><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>- Boot Configuration- Setup Prompt Timeout- Bootup NumLock State- Quiet Boot- Fast Boot- Boot Order</td><td>- Save Changes and Exit- Discard Changes and Exit- Save Changes and Reset- Discard Changes and Reset- Save Changes- Discard Changes- Restore Defaults- Save as User Defaults- Restore User Defaults- Boot Override</td></tr></table>

![The image displays an icon of a white document featuring faint horizontal lines and a folded top-left corner. A large, red checkmark is superimposed diagonally across the center of the paper.](.dlap-3200-cf-50m-00004-1000-10/dc0ef2cd6cb335633909ad5b707f4f8d4f919da62dea3e40605655f376657e23.jpg)
NOTE:

- ► indicates a submenu
- Gray text indicates info only
- Bold text indicates a default setting

# C.3 Main Menu

This menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings.

# C.3.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Information</td><td>Info only</td><td></td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>BIOS Vendor</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>BIOS Version.</td></tr><tr><td>Build Date</td><td>Info only</td><td>BIOS build date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>ME FW Version</td></tr></table>

# C.3.2 Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Information</td><td>Info only</td><td></td></tr><tr><td>Project Name</td><td>Info only</td><td>Project Name</td></tr></table>

# C.3.3 Main > Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>CPU Board Version</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>CPU Brand String</td></tr><tr><td>Stepping</td><td>Info only</td><td>CPU Stepping</td></tr><tr><td>GT Info</td><td>Info only</td><td>GT Info</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>CPU Frequency</td></tr></table>

# C.3.4 Main > Memory Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Total Memory</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Memory Frequency</td></tr></table>

# C.3.5 Main > PCH Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>PCH SKU</td></tr><tr><td>Stepping</td><td>Info only</td><td>PCH Stepping</td></tr></table>

# C.3.6 Main > Board Information > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Board Information</td><td>Info only</td><td></td></tr><tr><td>Serial Number</td><td>Info only</td><td>Serial Number</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Manufacturing Date</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Last Repair Date</td></tr><tr><td>MAC ID</td><td>Info only</td><td>MAC ID</td></tr></table>

# C.3.7 Main > Board Information > Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td></td></tr><tr><td>Total Runtime</td><td>Info only</td><td>Total Runtime</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>Current Runtime</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>Power Cycles</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>Boot Cycles</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>Boot Reason</td></tr></table>

# C.3.8 Main > System Date & Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# C.3.9 Main > Access Level

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Access</td><td>Level</td><td>Administrator / User</td></tr></table>

# C.4 Advanced Menu

This menu contains the settings for most of the user interfaces in the system.

C.4.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Configuration</td><td>Info only</td><td></td></tr><tr><td>Type</td><td>Info only</td><td>Displays the Processor Type</td></tr><tr><td>Package</td><td>Info only</td><td>Displays the Processor Package</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays the Processor Stepping.</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Displays number of CPU cores.</td></tr><tr><td>CPUID</td><td>Info only</td><td>Displays the Processor ID.</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>CPU Microcode Revision</td></tr><tr><td>Speed</td><td>Info only</td><td>Displays the Processor Speed.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Displays the Processor L1 Data Cache size.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Displays the Processor L1 Instruction Cache size.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Displays the Processor L2 Cache size.</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Displays the Processor L3 Cache size.</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Displays the Processor L4 eDRAM size.</td></tr><tr><td>VMX</td><td>Info only</td><td>VMX Supported or Not</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>SMX/TXT Supported or Not</td></tr><tr><td>Active Processor Cores</td><td>All (based on CPU SKU)</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>Disabled Enabled</td><td>Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled Enabled</td><td>Enables/Disables Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enables/Disables processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled).</td></tr><tr><td>C states</td><td>Disabled Enabled</td><td>Enables/Disables CPU Power Management. Allows CPU to go to C states when not 100% utilized.</td></tr><tr><td>C-State Auto Demotion</td><td>Disabled C1 C3 C1 and C3</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Un-demotion</td><td>Disabled C1 C3 C1 and C3</td><td>Configure C-State Un-demotion</td></tr><tr><td>Package C-State Demotion</td><td>Disabled Enabled</td><td>Package C-State Demotion</td></tr><tr><td>Package C-State Un-demotion</td><td>Disabled Enabled</td><td>Package C-State Un-demotion</td></tr><tr><td>Package C State Limit</td><td>C0/C1 C2 C3 C6 C7 C7S C8 C9 C10 Cpu Default Auto</td><td>Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit.</td></tr><tr><td>Tcc Activation Offset</td><td>0-63Default: 0</td><td>Offset from factory set Tcc activation temperature at which the Thermal Control Circuit must be activated. Tcc will be activated at: Tcc Activation Temp - Tcc Activation Offset. Tcc Activation Offset range is 0 to 63.</td></tr></table>

C.4.2 Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GraphicsConfiguration</td><td>Info only</td><td></td></tr><tr><td>LVDS</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enables/Disables eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x10501266x7681600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>Spreading depth</td><td>No Spreading0.50%1.00%1.50%2.00%2.50%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>LVDS Backlight Mode</td><td>BMC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td rowspan="2">LVDS Backlight Brightness</td><td>BMC Mode: 0-255Default: 255</td><td rowspan="2">Set LVDS Backlight Brightness Percentage.The change takes effect immediately.</td></tr><tr><td>GTT Mode: 0-100Default 100</td></tr></table>

# C.4.3 Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Management</td><td>Info only</td><td></td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables/Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables/Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>Lock Legacy Resources</td><td>DisabledEnabled</td><td>Enables/Disables Lock of Legacy Resources</td></tr><tr><td>Restore AC Power Loss</td><td>Power OnPower OffLast State</td><td>Select AC power state when power is re-applied after a power failure.</td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>ATX: OS will turn off system power when shutdown.NOTE: AT mode will not support S3 &amp; S4, so it will change Power Loss State to Power On</td></tr><tr><td>PCI Express Wake</td><td>DisabledEnabled</td><td>Enables/Disables PCIExpress Wake ping for PCIe device wake function</td></tr><tr><td>Power Consumption ▶</td><td>Sub-Menu</td><td>Power Consumption</td></tr></table>

C.4.4 Advanced > Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info only</td><td></td></tr><tr><td>Current Input Current</td><td>Info only</td><td>Current Input Current</td></tr><tr><td>Current Input Power</td><td>Info only</td><td>Current Input Power</td></tr><tr><td>VIN</td><td>Info only</td><td>VIN</td></tr><tr><td>VCORE</td><td>Info only</td><td>VCORE</td></tr><tr><td>RTC</td><td>Info only</td><td>RTC</td></tr></table>

C.4.5 Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info only</td><td></td></tr><tr><td>Version</td><td>Info only</td><td></td></tr><tr><td>SEMA Firmware</td><td>Info only</td><td>Version of SEMA Firmware</td></tr><tr><td>Build Date</td><td>Info only</td><td>Build Date of SEMA Firmware</td></tr><tr><td>SEMA Bootloader</td><td>Info only</td><td>Version of SEMA Bootloader</td></tr><tr><td>Build Date</td><td>Info only</td><td>Build Date of SEMA Bootloader</td></tr><tr><td>SEMA Features ▶</td><td>Sub-Menu</td><td>SEMA Features</td></tr><tr><td>Flags ▶</td><td>Sub-Menu</td><td>Flags</td></tr><tr><td>SPI ROM WP ▶</td><td>Sub-Menu</td><td>SPI ROM write protect</td></tr><tr><td>BIOS Post Update Menu</td><td>Sub-Menu</td><td>An update BIOS interface</td></tr></table>

C.4.6 Advanced > System Management > SEMA Features

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Features</td><td>Info only</td><td></td></tr><tr><td>Uptime &amp; Power Cycles Counter</td><td>Info only</td><td>Uptime &amp; Power Cycles Counter</td></tr><tr><td>System Restart Event</td><td>Info only</td><td>System Restart Event</td></tr><tr><td>1024 Bytes User-Flash</td><td>Info only</td><td>1024 Bytes User-Flash</td></tr><tr><td>Watchdog</td><td>Info only</td><td>Watchdog</td></tr><tr><td>Temperatures</td><td>Info only</td><td>Temperatures</td></tr><tr><td>Voltage Monitor</td><td>Info only</td><td>Voltage Monitor</td></tr><tr><td>Display Backlight control</td><td>Info only</td><td>Display Backlight control</td></tr><tr><td>Power-Up Watchdog</td><td>Info only</td><td>Power-Up Watchdog</td></tr><tr><td>Power Monitor (current sense)</td><td>Info only</td><td>Power Monitor (current sense)</td></tr><tr><td>Boot Counter</td><td>Info only</td><td>Boot Counter</td></tr><tr><td>5V Input-Voltage</td><td>Info only</td><td>5V Input-Voltage</td></tr><tr><td>4mR Rsense for Input-Voltage</td><td>Info only</td><td>4mR Rsense for Input-Voltage</td></tr><tr><td>CPU Fan</td><td>Info only</td><td>CPU Fan</td></tr><tr><td>System Fan 1</td><td>Info only</td><td>System Fan 1</td></tr><tr><td>AT/ATX mode</td><td>Info only</td><td>AT/ATX mode</td></tr><tr><td>ACPI Thermal Trigger</td><td>Info only</td><td>ACPI Thermal Trigger</td></tr><tr><td>Backlight restore</td><td>Info only</td><td>Backlight restore</td></tr><tr><td>DTS register available</td><td>Info only</td><td>DTS register available</td></tr><tr><td>System Fan 2</td><td>Info only</td><td>System Fan 2</td></tr><tr><td>TIVA BMC</td><td>Info only</td><td>TIVA BMC</td></tr><tr><td>Board2 Temperature</td><td>Info only</td><td>Board2 Temperature</td></tr><tr><td>SEMA Error Log</td><td>Info only</td><td>SEMA Error Log</td></tr><tr><td>Soft Fan</td><td>Info only</td><td>Soft Fan</td></tr></table>

# C.4.7 Advanced > System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td>Info only</td><td></td></tr><tr><td>BMC Flags</td><td>Info only</td><td>BMC Flags</td></tr><tr><td>BIOS Select</td><td>Info only</td><td>BIOS Select</td></tr><tr><td>ATX/AT-Mode</td><td>Info only</td><td>ATX/AT-Mode</td></tr><tr><td>Exception Code</td><td>Info only</td><td>Exception Code</td></tr></table>

# C.4.8 Advanced > System Management > SPI ROM WP

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SPI ROM Write Protect</td><td>DisabledEnabled</td><td>Enables/Disables SPI ROM Write Protect</td></tr></table>

# C.4.9 Advanced > System Management > BIOS Post Update Menu

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>BIOS Post Update Menu</td><td>An update BIOS interface.</td></tr><tr><td>Choose BIOS Image</td><td>An interface to let users choose a BIOS image in a local storage device.</td></tr><tr><td>Start Flash</td><td>Start to flash BIOS</td></tr></table>

C.4.10 Advanced > Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info only</td><td></td></tr><tr><td>Current</td><td>Info only</td><td>Current CPU temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Startup CPU temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Min. CPU temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Max. CPU temperature</td></tr><tr><td>Board Temperatures</td><td>Info only</td><td></td></tr><tr><td>Current</td><td>Info only</td><td>Current Board temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Startup Board temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Min. Board temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Max. Board temperature</td></tr><tr><td>GPU Temperatures</td><td>Info only</td><td></td></tr><tr><td>Current</td><td>Info only</td><td>Current GPU temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Startup GPU temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Min. GPU temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Max. GPU temperature</td></tr><tr><td>CPU Fan Speed</td><td>Info only</td><td>CPU Fan Speed</td></tr><tr><td>System Fan Speed</td><td>Info only</td><td>System Fan Speed</td></tr><tr><td>GPU Fan Speed</td><td>Info only</td><td>GPU Fan Speed</td></tr><tr><td>Smart Fan ▶</td><td>Sub-Menu</td><td>Smart Fan</td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>This value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C99 C</td><td>This value is the temperature threshold of the Passive Cooling Trip Point.</td></tr></table>

C.4.11 Advanced > Thermal Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info only</td><td></td></tr><tr><td>CPU Smart FanTemperature Source</td><td>CPU Sensor</td><td>CPU Smart FanTemperature Source</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>CPU Fan Mode</td></tr><tr><td>Trigger Point 1</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 0</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 30</td><td>PWM Level</td></tr><tr><td>Trigger Point 2</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 50</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 65</td><td>PWM Level</td></tr><tr><td>Trigger Point 3</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 85</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 80</td><td>PWM Level</td></tr><tr><td>Trigger Point 4</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 92</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 100</td><td>PWM Level</td></tr><tr><td>System Smart FanTemperature Source</td><td>CPU Sensor</td><td>System Smart FanTemperature Source</td></tr><tr><td>System Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>System Fan Mode</td></tr><tr><td>Trigger Point 1</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 0</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 30</td><td>PWM Level</td></tr><tr><td>Trigger Point 2</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 50</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 45</td><td>PWM Level</td></tr><tr><td>Trigger Point 3</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 85</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 65</td><td>PWM Level</td></tr><tr><td>Trigger Point 4</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 92</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 100</td><td>PWM Level</td></tr><tr><td>GPU Smart FanTemperature Source</td><td>GPU Sensor</td><td>GPU Smart FanTemperature Source</td></tr><tr><td>GPU Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>GPU Fan Mode</td></tr><tr><td>Trigger Point 1</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 0</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 25</td><td>PWM Level</td></tr><tr><td>Trigger Point 2</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 45</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 50</td><td>PWM Level</td></tr><tr><td>Trigger Point 3</td><td>Info only</td><td></td></tr></table>

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 60</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 75</td><td>PWM Level</td></tr><tr><td>Trigger Point 4</td><td>Info only</td><td></td></tr><tr><td>Trigger Temperature</td><td>0-100Default: 80</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>0-100Default: 100</td><td>PWM Level</td></tr></table>

C.4.12 Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>DisabledEnabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>0-65535Default: 65535</td><td>The time the Power Up Watchdog should wait until it resets the system.</td></tr><tr><td>ATTENTION:Pressing F12 during start up disables the Power Up Watchdog.</td><td>Info only</td><td></td></tr><tr><td>RunTime Watchdog</td><td>DisabledEnabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>0-65535Default: 24</td><td>The Power Up Watchdog should wait until it resets the system.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Enables/Disables Watchdog ACPI Event Shutdown</td></tr></table>

C.4.13 Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>COM1 Device Settings</td><td>Info only</td><td>IO=3F8h; IRQ=4;</td></tr><tr><td>COM1 Control</td><td>RS232</td><td>Select COM1 mode. RS232 only</td></tr><tr><td>Ring1 Wake</td><td>DisabledEnabled</td><td>Disable/Enable RI ping for Wake On Ring function(PCH PME# signal)</td></tr><tr><td>COM2 Device Settings</td><td>Info only</td><td>IO=2F8; IRQ=3;</td></tr><tr><td>COM2 Control</td><td>RS232RS422RS485</td><td>Select COM2 mode. RS232, RS422 or RS485</td></tr><tr><td>Ring2 Wake</td><td>DisabledEnabled</td><td>Disable/Enable RI ping for Wake On Ring function(PCH PME# signal)</td></tr></table>

C.4.14 Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Console Redirection</td><td>Info only</td><td></td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables Console Redirection</td></tr><tr><td>Console Redirection Settings ▶</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables Console Redirection</td></tr><tr><td>Console Redirection Settings ▶</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

C.4.15 Advanced > Console Redirection Settings [COM1-2]

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM[1-2]Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on both connected systems. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0.Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareRTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow.Hardware flow control uses two wires to send start/stop</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables/Disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

C.4.16 Advanced > Trusted Computing [TPM 2.0 Configuration]

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Configuration</td><td>Info only</td><td></td></tr><tr><td>Security Device Support</td><td>Disabled Enabled</td><td>Enables/Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>TPM 2.0 Configuration</td><td>Info only</td><td></td></tr><tr><td>TPM20 Device Found</td><td>Info only</td><td></td></tr><tr><td>Firmware Version:</td><td>Info only</td><td></td></tr><tr><td>Vendor:</td><td>Info only</td><td></td></tr><tr><td>Security Device Support</td><td>Disabled Enabled</td><td>Enables/Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>Active PCR banks</td><td>Info only</td><td></td></tr><tr><td>Available PCR banks</td><td>Info only</td><td></td></tr><tr><td>SHA-1 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA-1 PCR Bank</td></tr><tr><td>SHA256 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA256 PCR Bank</td></tr><tr><td>Pending operation</td><td>None TPM Clear</td><td>Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Platform Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Platform Hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Storage Hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Endorsement Hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2 TCG_2</td><td>Select the TCG2 Spec Version Support</td></tr><tr><td>Physical Presence Spec Version</td><td>1.2 1.3</td><td>Select to Tell OS to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.</td></tr><tr><td>PH Randomization</td><td>Disabled Enabled</td><td>Enables/Disables Platform Hierarchy randomization. DO NOT ENABLE THIS QUESTION IN PRODUCTION PLATFORMS. THIS IS FOR DEVELOPMENT TESTING. OVERRIDE ChangePlatformAuth ELINK for production platforms supporting TXT.</td></tr></table>

C.4.17 Advanced > RTC Wake Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Wake system from S5</td><td>DisabledFixed TimeDynamic Time</td><td>Enables/Disables System wake on alarm event.FixedTime: system will wake on the hr::min::sec specified.DynamicTime: System will wake on the current time + Increase minute(s)</td></tr><tr><td>Wake up hour</td><td>0-23Default: 0</td><td>Range: 0-23 hrFor example enter 3 for 3am and 15 for 3pm</td></tr><tr><td>Wake up minute</td><td>0-59Default: 0</td><td>Range: 0-59 min</td></tr><tr><td>Wake up second</td><td>0-59Default: 0</td><td>Range: 0-59 sec</td></tr><tr><td>Wake up minute increase</td><td>1-5Default: 1</td><td>Range: 1-5 min</td></tr></table>

C.4.18 Advanced > NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVMe Configuration</td><td>Info only</td><td></td></tr><tr><td>List NVMe Device</td><td>Info only</td><td></td></tr></table>

C.4.19 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Disabled Enabled</td><td>Enables/Disables UEFI Network Stack</td></tr><tr><td>Ipv4 PXE Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>Ipv4 HTTP Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.</td></tr><tr><td>Ipv6 PXE Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>Ipv6 HTTP Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>IPSEC Certificate</td><td>Disabled Enabled</td><td>Enables/Disables IPSEC certificate for Ikev.</td></tr><tr><td>PXE boot wait time</td><td>0-5Default: 0</td><td>Wait time in seconds to press ESC key to abort PXE boot. Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>1-50Default: 1</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

# C.4.20 Advanced > [Network Name] Network Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">This sub-menu is controlled by device firmware, refer to the actual layout.</td></tr></table>

# C.4.21 Advanced > RAM Disk Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Disk Memory Type:</td><td>Boot Service Data Reserved</td><td>Specifies type of memory to use from available memory pool in system to create a disk.</td></tr><tr><td>Create raw ▶</td><td>Sub-Menu</td><td>Create a raw RAM disk.</td></tr><tr><td>Create from file ▶</td><td>Sub-Menu</td><td>Create a RAM disk from a given file.</td></tr><tr><td>Created RAM disk list:</td><td>Info only</td><td></td></tr><tr><td>Remove selected RAM disk(s)</td><td>Remove selected RAM disk(s)</td><td></td></tr></table>

C.4.22 Advanced > RAM Disk Configuration > Create raw

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Size (Hex):</td><td>Number</td><td>The valid RAM disk size should be multiples of the RAM disk block size.</td></tr><tr><td>Create &amp; Exit</td><td>Yes</td><td>Create a new RAM disk with the given starting and ending address.</td></tr><tr><td>Discard &amp; Exit</td><td>Yes</td><td>Discard and exit.</td></tr></table>

C.4.23 Advanced > RAM Disk Configuration > Create from file

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Create from file</td><td>Select file</td><td>Create a RAM disk from a given file.</td></tr></table>

# C.5 Chipset

C.5.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>Info only</td><td></td></tr><tr><td>SA PCIe Code Version</td><td>Info only</td><td>SA PCIe Code Version</td></tr><tr><td>VT-d</td><td>Info only</td><td>Supported or not</td></tr><tr><td>Memory Configuration ▶</td><td>Sub-Menu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration ▶</td><td>Sub-Menu</td><td>Graphics Configuration</td></tr><tr><td>PEG Port Configuration ▶</td><td>Sub-Menu</td><td>PEG Port Options</td></tr><tr><td>VT-d</td><td>Disabled Enabled</td><td>VT-d capability</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Disabled Enabled</td><td>Enables/Disables above 4GB MemoryMappedIO BIOS assignment</td></tr></table>

C.5.2 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>Info only</td><td></td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Memory RC Version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Memory Frequency</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td></tr><tr><td>DIMM 1</td><td>Info only</td><td>DIMM 1 info</td></tr><tr><td>Size</td><td>Info only</td><td>Size of DIMM 1</td></tr><tr><td>Number of Ranks</td><td>Info only</td><td>Number of Ranks of DIMM 1</td></tr><tr><td>Manufacturer</td><td>Info only</td><td>Manufacturer of DIMM 1</td></tr><tr><td>DIMM 2</td><td>Info only</td><td>DIMM 2 info</td></tr><tr><td>Size</td><td>Info only</td><td>Size of DIMM 2</td></tr><tr><td>Number of Ranks</td><td>Info only</td><td>Number of Ranks of DIMM 2</td></tr><tr><td>Manufacturer</td><td>Info only</td><td>Manufacturer of DIMM 2</td></tr></table>

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Remap</td><td>DisabledEnabled</td><td>Enables/Disables Memory Remap above 4GB</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables/Disables fast path through MRC</td></tr></table>

C.5.3 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info only</td><td></td></tr><tr><td>Graphics Turbo IMON Current</td><td>14-31Default: 31</td><td>Graphics turbo IMON current values supported (14-31)</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEG</td><td>Select which of IGFX/PEG Graphics device should be Primary Display.</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>GTT Size</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

C.5.4 Chipset > System Agent (SA) Configuration > PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG Port Configuration</td><td>Info only</td><td></td></tr><tr><td>PEG [Bus, Dev, Fun]</td><td>Info only</td><td>PEG location and info</td></tr><tr><td>Enable Root Port</td><td>Disabled Enabled Auto</td><td>Enables/Disables the Root Port</td></tr><tr><td>Max Link Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Configure PEG [Bus, Dev, Fun] Max Speed</td></tr><tr><td>PCIe Spread Spectrum Clocking</td><td>Disabled Enabled</td><td>Allows disabling Spread Spectrum Clocking for compliance testing</td></tr></table>

C.5.5 Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH-IO Configuration</td><td>Info only</td><td></td></tr><tr><td>PCI Express Configuration ▶</td><td>Sub-Menu</td><td>PCI Express Configuration settings</td></tr><tr><td>SATA Configuration ▶</td><td>Sub-Menu</td><td>SATA Device Settings</td></tr><tr><td>USB Configuration ▶</td><td>Sub-Menu</td><td>USB Configuration settings</td></tr><tr><td>Security Configuration ▶</td><td>Sub-Menu</td><td>Security Configuration settings</td></tr><tr><td>PCH digital I/O device</td><td>Disabled Enabled</td><td>Enables/Disables PCH digital I/O device</td></tr><tr><td>SPD Write Disable</td><td>TRUE FALSE</td><td>Enables/Disables setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr></table>

C.5.6 Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info only</td><td></td></tr><tr><td>PCI Express Clock Gating</td><td>Disabled Enabled</td><td>Enables/Disables PCI ExpressClock Gating for each root port.</td></tr><tr><td>Pcie PII SSC</td><td>Auto0.0%0.1%0.2%0.3%0.4%0.5%0.6%0.7%0.8%0.9%1.0%1.1%1.2%1.3%1.4%1.5%1.6%1.7%1.8%1.9%2.0%</td><td>Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override.Range is 0.0%-2.0%.</td></tr></table>

# C.5.7 Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Configuration</td><td>Info only</td><td></td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST Premium With Intel Optane System Acceleration</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>Serial ATA Port 0</td><td>Info only</td><td>SATA device info</td></tr><tr><td>Serial ATA Port 2</td><td>Info only</td><td>SATA device info</td></tr><tr><td>Serial ATA Port 3</td><td>Info only</td><td>SATA device info</td></tr><tr><td>Serial ATA Port 4</td><td>Info only</td><td>SATA device info</td></tr></table>

# C.5.8 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info only</td><td></td></tr><tr><td>USB Overcurrent</td><td>Disabled Enabled</td><td>Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>Disabled Enabled</td><td>Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Port Disable Override</td><td>Disable Link Select Per-Pin</td><td>Selectively Enables/Disables the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>U3_USB1_TX_P(EXTERNAL USB)</td><td>DisabledEnabled</td><td rowspan="16">Enables/Disables this USB Physical Connector (physical port). Once disabled, any USB devices plugged into the connector will not be detected by BIOS or OS.</td></tr><tr><td>U3_USB2_TX_P(EXTERNAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U3_USB3_TX_P(EXTERNAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U3_USB4_TX_P(EXTERNAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U3_USB5_TX_P (PIN HEADER USB)</td><td>DisabledEnabled</td></tr><tr><td>U3_USB6_TX_P (PIN HEADER USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB1_P(EXTRENAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB2_P(EXTRENAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB3_P(EXTRENAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB4_P(EXTRENAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB5_P (PIN HEADER USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB6_P (PIN HEADER USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB7_P (M.2 Key_B)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB8_P (M.2 Key_E)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB9_P(INTERNAL USB)</td><td>DisabledEnabled</td></tr><tr><td>U2_USB14_P(INTERNAL USB)</td><td>DisabledEnabled</td></tr></table>

# C.5.9 Chipset > PCH-IO Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Configuration</td><td>Info only</td><td></td></tr><tr><td>BIOS Lock</td><td>Disabled Enabled</td><td>Enables/Disables the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr></table>

# C.6 Security

C.6.1 Security > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Sets Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Sets User Password</td></tr><tr><td>Secure Boot menu ▶</td><td>Submenu</td><td>Secure Boot configuration</td></tr></table>

C.6.2 Security > Secure Boot menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>System Mode</td><td>Info only</td><td>Setup / User / Audit / Deployed</td></tr><tr><td>Secure Boot</td><td>Info only</td><td>Active / Not Active</td></tr><tr><td>Vendor Keys</td><td>Info only</td><td>Valid / Modified</td></tr><tr><td>Secure Boot Control</td><td>Disabled Enabled</td><td>Secure Boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. Changing this requires a platform reset.</td></tr><tr><td>Secure Boot Mode</td><td>Standard Custom</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr><tr><td>Key Management ▶</td><td>Sub-Menu</td><td>Enables expert users to modify Secure Boot Policy variables without full authentication.</td></tr></table>

C.6.3 Security > Secure Boot menu > Key Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">This sub-menu is provided by AMI.</td></tr></table>

# C.7 Boot

C.7.1 Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td><td></td></tr><tr><td>Boot Configuration</td><td colspan="3">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td colspan="2">Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td colspan="2">Selects the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td colspan="2">Enables/Disabless Quiet Boot option.</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td colspan="2">Enables/Disabless boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>Boot Configuration</td><td colspan="3">Info only</td></tr><tr><td>Boot Option #1</td><td rowspan="8">Hard Disk CD/DVD USB Hard Disk USB CD/DVD USB Key USB Floppy USB Lan Network Disabled</td><td>Hard Disk</td><td rowspan="8">Sets the system boot order</td></tr><tr><td>Boot Option #2</td><td>CD/DVD</td></tr><tr><td>Boot Option #3</td><td>USB Hard Disk</td></tr><tr><td>Boot Option #4</td><td>USB CD/DVD</td></tr><tr><td>Boot Option #5</td><td>USB Key</td></tr><tr><td>Boot Option #6</td><td>USB Floppy</td></tr><tr><td>Boot Option #7</td><td>USB Lan</td></tr><tr><td>Boot Option #8</td><td>Network</td></tr><tr><td>UEFI [Device] BBS Priorities ▶</td><td>Sub-Menu</td><td colspan="2">Specifies the Boot Device Priority sequence from available UEFI device</td></tr></table>

C.7.2 Boot > Boot Configuration > UEFI [Device] BBS Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option #[Num]</td><td>[Device]Disabled</td><td>Sets the system boot order</td></tr></table>

C.8 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>Yes No</td><td>Exits system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Yes No</td><td>Exits system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Yes No</td><td>Resets the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Yes No</td><td>Resets system setup without saving any changes.</td></tr><tr><td>Save Options</td><td colspan="2">Info only</td></tr><tr><td>Save Changes</td><td>Yes No</td><td>Saves changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Yes No</td><td>Discards changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td>Yes No</td><td>Restores/Loads default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Yes No</td><td>Saves the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Yes No</td><td>Restores the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td colspan="2">Info only</td></tr><tr><td>Boot options</td><td colspan="2">Do one time boot override to boot selected boot option.</td></tr></table>

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# Appendix D DisplayPort BIOS Settings

This appendix describes use of the DisplayPort BIOS settings for MXM modules.

D.1 MXM P1000/P2000/T1000/RTX3000/RTX5000

<table><tr><td colspan="3">BIOS Setting</td><td colspan="4">DisplayPort</td></tr><tr><td rowspan="2">Primary Display</td><td rowspan="2">Internal Graphics</td><td rowspan="2">LVDS</td><td colspan="2">POST Stage</td><td colspan="2">Windows 10</td></tr><tr><td>DP from CPU</td><td>DP from MXM</td><td>DP from CPU</td><td>DP from MXM</td></tr><tr><td>IGFX</td><td>Enabled</td><td>Enabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Enabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Enabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Disabled</td><td>Enabled</td><td>No</td><td>No</td><td>No</td><td>Yes</td></tr><tr><td>PEG</td><td>Disabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Disabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Auto</td><td>Enabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Auto</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Auto</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Enabled</td><td>Disabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Enabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Auto</td><td>Enabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>IGFX</td><td>Disabled</td><td>Disabled</td><td>No</td><td>No</td><td>No</td><td>Yes</td></tr><tr><td>PEG</td><td>Disabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Disabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Auto</td><td>Disabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Auto</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Auto</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr></table>

D.2 MXM P3000/P5000

<table><tr><td colspan="3">BIOS Setting</td><td colspan="4">DisplayPort</td></tr><tr><td rowspan="2">Primary Display</td><td rowspan="2">Internal Graphics</td><td rowspan="2">LVDS</td><td colspan="2">POST Stage</td><td colspan="2">Windows 10</td></tr><tr><td>DP from CPU</td><td>DP from MXM</td><td>DP from CPU</td><td>DP from MXM</td></tr><tr><td>IGFX</td><td>Enabled</td><td>Enabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Enabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Enabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Disabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>PEG</td><td>Disabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Disabled</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Auto</td><td>Enabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Auto</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Auto</td><td>Enabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Enabled</td><td>Disabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Enabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Auto</td><td>Enabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>IGFX</td><td>Disabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>PEG</td><td>Disabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>Auto</td><td>Disabled</td><td>Disabled</td><td>No</td><td>Yes</td><td>No</td><td>Yes</td></tr><tr><td>IGFX</td><td>Auto</td><td>Disabled</td><td>Yes</td><td>No</td><td>Yes</td><td>Yes</td></tr><tr><td>PEG</td><td>Auto</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Auto</td><td>Auto</td><td>Disabled</td><td>No</td><td>Yes</td><td>Yes</td><td>Yes</td></tr></table>

![The image features a white document icon with a folded top-right corner and faint gray horizontal lines running across it. A large red checkmark is superimposed over the center of the document.](.dlap-3200-cf-50m-00004-1000-10/f8bf81a6b92a64dc8797d47974d5e2a762a93ad6ef5a20b84cd010dae61d4bae.jpg)
NOTE:

When using a four DisplayPort configuration, use vBIOS 86.04.70.00.3D with the P3000, and vBIOS 86.04.70.00.3C with the P5000.

# Appendix E Digital Input/Output Function Library

DI/O provides input/output to support inter-device communications. Simple programming guides allow easy transmission of digital signals between the system and attached peripherals.

# DI/O with API/Windows

DLAP-3200 DI/O API library files and a demo program (including source code) can be downloaded from:

https://www.adlinktech.com/Products/Industrial\_PCs\_Fanless\_ Embedded\_PCs/IPCSystems/DLAP-3200-CF\_Series.

To use the DI/O function library for the DLAP-3200 series, include the header file (GpioLib.h) and linkage library (GpioLib.lib) in the C++ project. DI/O functions are as follows.

# GPIO\_Init

This API checks if the GPIO driver handle is valid.

char GPIO\_Init ()

# Return values:

GPIO\_OK on success. GPIO\_ERROR on failure.

# GPI\_Read

This API reads the digital input (DI) pin status:

char GPI\_Read(UCHAR GpioNum, PUCHAR data)

# Arguments:

GpioNum: The number of a digital input pin (0-3)

data: The digital input pin status will be copied to this address reference

# Return values:

GPIO\_OK on success. GPIO\_ERROR on failure.

# GPO\_Write

This API is used to write the new state of a digital output (DO):

char GPO\_Write(UCHAR GpioNum,UCHAR GpioPortVal)

# Arguments:

GpioNum: The number of a digital output pin (4-7).

GpioPortVal: A new output state 0 or 1.

# Return values:

GPIO\_OK on success. GPIO\_ERROR on failure.

# RegisterInterruptEvent

The event passed will be signaled when there is a change in state on a digital input pin. This API is used to register the event.

char RegisterInterruptEvent(HANDLE Event, UCHAR Pin)

# Argument:

Event: Handle of the event that wait for Interrupt notification.

Pin: The number of an input pin.

# Return values:

GPIO\_OK on success. GPIO\_ERROR on failure.

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

X Read these safety instructions carefully.
X Keep the User’s Manual for future reference.
Read the Specifications section of this manual for detailed information on the recommended operating environment.
X The device can be operated at an ambient temperature of $4 5 \%$ with DC input, and $\mathtt { 3 5 ^ { \circ } C }$ with adapter input.
It is recommended that the device be installed in Information Technology Rooms that are in accordance with Article 645 of the National Electrical Code and NFPA 75.

X To avoid electrical shock and/or damage to device:

Z Keep device away from water or liquid sources.
Z Keep device away from high heat or humidity.
Z Keep device properly ventilated (do not block or cover ventilation openings).
Z Always use recommended voltage and power source settings.
Z Always install and operate device near an easily accessible electrical outlet.
Z Secure the power cord (do not place any object on/over the power cord).
Z Only install/attach and operate device on stable surfaces and/or recommended mountings.
Z The power cord must be connected to a socket or outlet with a ground connection.

If the device will not be used for long periods of time, turn off and unplug from its power source.
X Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools.

X A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a centered black exclamation point. Directly below the triangle, the word 'CAUTION:' is printed in black capital letters.](.dlap-3200-cf-50m-00004-1000-10/e47f3715f11a8f0c3d0b25607ac524c03230afcdf2d1a6dac5b7b274fb0f3848.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

X This equipment is not suitable for use in locations where children are likely to be present.
X The device must be serviced by authorized technicians when:

Z The power cord or plug is damaged
Z Liquid has entered the device interior
Z The device has been exposed to high humidity and/or moisture
Z The device is not functioning or does not function according to the User’s Manual
Z The device has been dropped and/or damaged and/or shows obvious signs of breakage

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up
X It is recommended that the device be installed only in a server room or computer room where access is:

Z Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required
Z Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

![Warning sign depicting steam rising inside a yellow triangle, indicating caution or hazard.](.dlap-3200-cf-50m-00004-1000-10/41ffb0754f6dda16c25f72ce84fbdfc198aaf73225c5b5a6d39394c337ea4989.jpg)

# BURN HAZARD

Hot surface! Do not touch! Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# Consignes de Sécurité Importante

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

X Lisez attentivement ces consignes de sécurité.
X Conservez le manuel de l'utilisateur pour pouvoir le consulter ultérieurement.
Lisez la section Spécifications de ce manuel pour des informations détaillées sur l'environnement d'exploitation recommandé.
L'appareil peut être utilisé à une température ambiante de 45°C avec entrée CC pour les série MVP-61; 35ºC avec entrée adaptateur pour la série MVP-61.
Il est recommandé d'installer l'appareil dans des salles de technologie de l'information conformes à l'article 645 du National Electrical Code et à la NFPA 75.

X Pour éviter les chocs électriques et/ou d’endommager l’appareil:

Z Tenez l'appareil à l'écart de toute source d'eau ou de liquide.
Z Tenez l'appareil à l'écart d'une forte chaleur ou d'une humidité élevée.
Z Maintenez l'appareil correctement ventilé (n'obstruer ou ne couvrez pas les ouvertures de ventilation).
Z Utilisez toujours les réglages de tension et de source d'alimentation recommandés.
Z Installez et utilisez toujours l'appareil près d'une prise de courant facilement accessible.
Z Fixez le cordon d'alimentation (ne placez aucun objet sur le cordon d'alimentation).
Z Installez/fixez et utilisez l'appareil uniquement sur des surfaces stables et/ou sur les fixations recommandées.
Z Le cordon d'alimentation doit être connecté à une prise ou à une prise de courant avec mise à la terre.

Si l'appareil ne doit pas être utilisé pendant de longues périodes, éteignez-le et débranchez-le de sa source d'alimentation
N'essayez jamais de réparer l'appareil, qui ne doit être réparé que par un personnel technique qualifié à l'aide d'outils appropriés
X Une batterie de type Lithium peut être fournie pour une alimentation de secours ininterrompue ou d'urgence.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the word 'CAUTION:' is written in black capital letters.](.dlap-3200-cf-50m-00004-1000-10/556c61aa0cbe54a7c3f7257304ad997fcfeff5efda9b524dfda5f31f16d2e60d.jpg)

ATTENTION: Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

Cet équipement ne convient pas à une utilisation dans des lieux pouvant accueillir des enfants.
X L'appareil doit être entretenu par des techniciens agrees lorsque:
X Le cordon d’alimentation ou la prise est endommagé(e)
X Un liquide a pénétré à l'intérieur de l'appareil.
X L'appareil a été exposé à une forte humidité et/ou de la buée.
X L'appareil ne fonctionne pas ou ne fonctionne pas selon le manuel de l'utilisateur.
L'appareil est tombé et/ou a été endommagé et/ou présente des signes évidents de dommage.
Débranchez le cordon d'alimentation avant de desserrer les vis à oreilles et serrez toujours les vis à oreilles avec un tournevis avant de mettre le système en marche.
X Il est recommandé d'installer l'appareil uniquement dans une salle de serveurs ou une salle informatique où l'accès est:

Z Réservé au personnel de service qualifié ou aux utilisateurs familiarisés avec les restrictions appliquées à l'emplacement, aux raisons de ces restrictions et toutes les précautions requises
Z Uniquement autorisé par l'utilisation d'un outil, d'une serrure et d'une clé, ou d'un autre moyen de sécurité, et contrôlé par l'autorité responsable de l'emplacement.

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.dlap-3200-cf-50m-00004-1000-10/2c17c43ccc02d4a0bd53dd3728a7ce66d9b88478084f4c52e4e467c806d28c75.jpg)

# RISQUE DE BRÛLURES

Partie chaude! Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

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# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you:
[🔗 Link to the original document](.dlap-3200-cf-50m-00004-1000-10/dlap-3200-cf-50m-00004-1000-10.pdf)