# EGX-MXM-P2000

NVIDIA® Pascal™ GP107 Quadro® P2000 Embedded Graphics Module

User's Manual

![Close-up of a green printed circuit board with multiple integrated circuits and gold contacts (no visible text or symbols)](.egx-mxm-p2000-50-1z300-1000-10/b3ee7ac85f401f260584c92461e609ef09392707959b40354bce50089396c40a.jpg)

Manual Rev.: 1.0

Revision Date: November 21, 2019

Part No: 50-1Z300-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2019-11-21</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2019 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Simple line drawing of a trash bin with two crossed lines (no text or symbols)](.egx-mxm-p2000-50-1z300-1000-10/f87bd103a2bc132cd266829076751e3f284bc547229091e831a63586c8ede043.jpg)

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Battery Labels (for products with battery)
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![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.egx-mxm-p2000-50-1z300-1000-10/f140adce2c1a8ab42517de03d935b23b9b09d3ccd0679a8b8846295613ed07b1.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.egx-mxm-p2000-50-1z300-1000-10/2a35dac3a9d8cc228cc2e04355625b13de35eb252e37db97cf930486e8fc4365.jpg)

![Abstract geometric pattern with interlocking X and Y shapes (no text or symbols)](.egx-mxm-p2000-50-1z300-1000-10/2fcdf39a7763873a47d320824d6aa9c028df041e440f7bb734cd5b3386aad7a5.jpg)

廢電池請回收

# California Proposition 65 Warning

![The image displays a yellow triangular warning sign with a thick black border. Inside the triangle, centered, is a black exclamation point. The sign is positioned vertically between two black bars, suggesting it is a cropped section of a larger interface or document.](.egx-mxm-p2000-50-1z300-1000-10/841321e634e0f616b9e5547edc1cdcc4d017316e5d8bc7c6084f98c50e04423d.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4- Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows an icon of a white document or piece of paper with a folded top-left corner and faint horizontal lines running across it. A large red checkmark is superimposed over the center of the document.](.egx-mxm-p2000-50-1z300-1000-10/63d63ef6e71b4a2076290ce508c82437cf0cafddd45a3a6e0dacc79b1b99c593.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image shows a standard warning sign: a yellow equilateral triangle with a thick black border. Centered within the triangle is a large, black exclamation mark. The background surrounding the sign is white.](.egx-mxm-p2000-50-1z300-1000-10/0988c3070becba261de117f44532aaef381bab48cbc499abb6319fda8ef15698.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays the bottom portion of a warning sign. It features a red equilateral triangle with a thin black outline, centered with a white exclamation point. Above the triangle is a white area with a horizontal black line running across the very top edge of the frame.](.egx-mxm-p2000-50-1z300-1000-10/73c6393f28a9f3114d34052b51b3ca2dea132788b472a293b3d4fa9542fdc531.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Tables...... vii

# List of Figures ix

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 1
1.3 Specifications.... 2

1.3.1 Board Specifications....2
1.3.2 Memory Configuration 3
1.3.3 Display Support and Options.... 3
1.3.4 OS Support....3
1.3.5 Software Support.... 3
1.3.6 Graphics Options....4

1.4 Functional Block Diagram.... 5
1.5 Layout and I/O 6

1.5.1 MXM Connector Pin Definition 8

1.6 Thermal Policy 13
1.7 Unpacking Checklist 13

# 2 System Requirements.... 15

2.1 Power Sequencing.... 15
2.2 Module Power Up and Down 16
2.3 Reset Requirements 16
2.4 Dual Mode DisplayPort Implementation 17
2.5 DVI/HDMI on DisplayPort Interface 18
2.6 Driver Installation 19

2.7 Certifications & Agencies 19

Important Safety Instructions.... 21

Getting Service 23

# List of Tables

Table 1-1: Board Specifications....2
Table 1-2: Memory Configuration .... 3
Table 1-3: Display Support and Options....3
Table 1-4: Graphics Module Display Options .... 4
Table 1-5: NVIDIA Link Display Types ....4
Table 1-6: MXM Connector Pin Definition 8
Table 1-7: Thermal Policy....13

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# List of Figures

Figure 1-1: Functional Block Diagram....5
Figure 1-2: MXM Module Basic Dimensions....6
Figure 1-3: MXM Module Detailed Dimensions and Layout......7
Figure 2-1: Power Sequencing 15
Figure 2-2: Module Power Down 16
Figure 2-3: Reset Sequencing .... 16
Figure 2-4: Dual Mode DisplayPort Implementation ..... 17
Figure 2-5: DVI/HDMI on DisplayPort Interface 18

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# 1 Introduction

# 1.1 Overview

The EGX-MXM-P2000 module features advanced NVIDIA® Quadro® Pascal™ architecture in the MXM 3.1 Type A form factor. The P2000 brings a new level of performance to visual graphics and computing applications, fully integrating hardware acceleration for both graphics and computing code, enabling hardware acceleration for a wider class of software applications than ever before.

The compact, module supports operability in an extended temperature range of $-40^{\circ}C$ to $85^{\circ}C$ , suitable for mission-critical harsh environments. With its 768 CUDA core Pascal GPU, the EGX-MXM-P2000 supports 4 FHD displays, offering a flexible and easy solution for medical and gaming applications.

# 1.2 Features

▶ MXM 3.1 Type A form factor (82 x 70 mm)
▶ 768 CUDA cores
▶ 2.3 TFLOPS single precision (SP) peak performance
▶ 4 GB GDDR5 memory
▶ 96 GB/s maximal memory bandwidth
▶ Support for up to 4 UHD displays
▶ 58W Total Graphics Power (TGP)
▶ 5 year performance warranty
▶ Nvidia Quadro P2000 GPU

▷ Package 29 x 29 mm
▷ Base Clock @1455 MHz
▶ Boost Clock @1480 MHz

# 1.3 Specifications

# 1.3.1 Board Specifications

<table><tr><td colspan="2">Graphics Core</td></tr><tr><td>Architecture</td><td>NVIDIA® PascalTM GP107</td></tr><tr><td>GPU</td><td>Quadro® P2000</td></tr><tr><td>Display Outputs</td><td>4x DisplayPort 1.4 digital video outputsSupport for High Dynamic Range (HDR) video4K at 98Hz with 10-bit color depth</td></tr><tr><td>Signal Interface</td><td>MXM 3.1, PCI Express Gen3 x16 support</td></tr><tr><td colspan="2">GPGPU Computing</td></tr><tr><td>CUDA Support</td><td>768 CUDA cores, 2.3TFLOPS SP PeakCUDA Toolkit 8.0, CUDA Compute version 6.1OpenCLTM 1.2, DirectX® 12, OpenGL 4.5, Vulcan 1.0</td></tr><tr><td colspan="2">Memory</td></tr><tr><td>GDDR5 Memory</td><td>4GB</td></tr><tr><td>Memory Width</td><td>128-bit</td></tr><tr><td>Bandwidth</td><td>96 GB/s</td></tr><tr><td colspan="2">Physical</td></tr><tr><td>Dimensions</td><td>87 (W) x 70 (D) x 4.8 (H) mm</td></tr><tr><td>Locking Mechanism</td><td>Standard MXM 3.1 Type A</td></tr><tr><td colspan="2">Environmental</td></tr><tr><td>Operating Temp.</td><td>Standard: 0°C to 55°C, ETT: -40°C to 85°C</td></tr><tr><td>Storage Temp.</td><td>-40°C to 85°C</td></tr><tr><td colspan="2">OS</td></tr><tr><td>Supported OS</td><td>Windows 7/10, Linux 64-bit</td></tr></table>

Table 1-1: Board Specifications

# 1.3.2 Memory Configuration

<table><tr><td>Memory</td><td>GDDR5@6Gbps</td></tr><tr><td>Configuration</td><td>256Mx32</td></tr><tr><td rowspan="3">Memory Bandwidth</td><td>128-bit</td></tr><tr><td>82 GB/s data rate</td></tr><tr><td>x32 GDDR5 DRAM device data width</td></tr><tr><td>Capacity</td><td>Total 4GB</td></tr></table>

Table 1-2: Memory Configuration

# 1.3.3 Display Support and Options

<table><tr><td>DisplayPort</td><td>▶ 1.2, 1.3, 1.4▶ Max. pixel clock: 1050 MP/s▶ Max. bandwidth: 25.9 GB/s/connector</td></tr><tr><td>HDMI 2.0</td><td>Max. resolution: 4096 x 2160 at 60 Hz</td></tr><tr><td>HDCP Support</td><td>1.3 (DP), 2.2 (DP, HDMI)</td></tr></table>

Table 1-3: Display Support and Options

# 1.3.4 OS Support

▶ Windows 7/10 (64-bit)
▶ Linux (64-bit)

# 1.3.5 Software Support

Supported software packages include:

▶ CUDA Toolkit 8.0
▶ CUDA Compute version 6.1
▶ OpenCL™ 1.2
▶ DirectX® 12
▶ OpenGL 4.5
▶ Vulcan 1.0

# 1.3.6 Graphics Options

The EGX-MXM-P2000 supports 4x DisplayPort by default. The graphics module display options are as shown.

<table><tr><td>Item</td><td colspan="4">Detail</td></tr><tr><td>MXM Port</td><td>DP_A</td><td>DP_B</td><td>DP_C</td><td>DP_D</td></tr><tr><td>NVIDIA Link</td><td>Link E</td><td>Link F</td><td>Link A</td><td>Link B</td></tr></table>

Table 1-4: Graphics Module Display Options

<table><tr><td>Link</td><td>Display Type</td></tr><tr><td>Link A</td><td>DisplayPort, DVI (Single Link or Dual Link with Link B)</td></tr><tr><td>Link B</td><td>DisplayPort, DVI (Dual Link with A)</td></tr><tr><td>Link C</td><td rowspan="2">Reserved (on GPU chip)</td></tr><tr><td>Link D</td></tr><tr><td>Link E</td><td>DisplayPort, HDMI</td></tr><tr><td>Link F</td><td>DisplayPort</td></tr></table>

Table 1-5: NVIDIA Link Display Types

# 1.4 Functional Block Diagram

![Based on the provided flowchart, here is the accurate description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **MXM 3.1 Connector** (Left vertical block)\n*   **N18P-Q3 50W** (Middle vertical block)\n*   **PCIE**\n*   **IFPA**\n*   **IFPB**\n*   **IFPE**\n*   **IFPF**\n*   **GDDR5 x32 memory down** (Four blocks on the top right)\n*   **I2CS**\n*   **PM**\n*   **JTAG**\n*   **SPI**\n*   **SPI - VBIOS**\n*   **Power Supply NVDD-PH1**\n*   **Power Supply NVDD-PH2**\n*   **Power Supply NVDD-PH3**\n*   **Power Supply NVDD-PH4**\n*   **Power Supply FBVDD_Q**\n*   **Power Supply PEX_VDD**\n*   **Power Supply VDD_AON\MAIN**\n\n**Connections:**\n*   **PCIE x16 Gen3**: Bidirectional arrow connecting **MXM 3.1 Connector** and **PCIE**.\n*   **DP1.4**: Bidirectional arrows connecting **MXM 3.1 Connector** to **IFPA**, **IFPB**, **IFPE**, and **IFPF**.\n*   **GDDR5 Channel A**: Arrows connecting **N18P-Q3 50W** to two **GDDR5 x32 memory down** blocks.\n*   **GDDR5 Channel B**: Arrows connecting **N18P-Q3 50W** to two **GDDR5 x32 memory down** blocks.\n*   **I2CS**: Bidirectional arrow connecting **MXM 3.1 Connector** and **I2CS**.\n*   **(PWR_EN、PWR_GOOD、WAKE#)**: Bidirectional arrow connecting **MXM 3.1 Connector** and **PM**.\n*   **JTAG**: Bidirectional arrow connecting **MXM 3.1 Connector** and **JTAG**.\n*   **SPI**: Arrow connecting **SPI - VBIOS** to **SPI**.\n*   **NVDD-PH1, NVDD-PH2, NVDD-PH3, NVDD-PH4**: Arrows connecting the respective **Power Supply** blocks to **N18P-Q3 50W**.\n*   **FBVDD_Q**: Arrow connecting **Power Supply** to **N18P-Q3 50W**.\n*   **PEX_VDD**: Arrow connecting **Power Supply** to **N18P-Q3 50W**.\n*   **VDD_AON\MAIN**: Arrow connecting **Power Supply** to **N18P-Q3 50W**.\n*   **P +SRC, P +5V, P +3V3**: Arrows pointing away from **MXM 3.1 Connector**.](.egx-mxm-p2000-50-1z300-1000-10/e681ad83e4c6c5631a168bd5897044bca970080310b969fb72ea23b06d932088.jpg)

Figure 1-1: Functional Block Diagram

# 1.5 Layout and I/O

All dimensions shown are in mm.

![Ø3.20x6\nØ6x6\n70\n82](.egx-mxm-p2000-50-1z300-1000-10/c86d9b10f4f60887a79765041383562f46e5563dd27d59b490444a2c986ca339.jpg)

Figure 1-2: MXM Module Basic Dimensions

![3.5 (137.8)\n0 (0)\n-5.5 (216.5)\n18.377 (723.5)\n28.5 (1122)\n38.123 (1500.9)\n51.5 (2027.6)\n75 (2952.8)\n78.5 (3090.6)\n4 (157.5)\n0 (0)\n6.242 (245.7)\n8.25 (324.8)\n21.127 (831.8)\n31.13 (1225.6)\n40.873 (1609.2)\n54.25 (2135.8)\n58.35 (2297.2)\n59.8 (2354.3)\n66 (2598.4)\n3.1±0.1 (122±3.94)\n0.5±0.1 (19.7±3.94)\n134x0.35±0.03 (13.8±1.18)\n0.85±0.03 (33.5±1.18)\n4.82±0.03 (189.8±1.18)\n2 PLACES\nMIN\n45°±10°\n0.3±0.12 ~ 11.8±4.72](.egx-mxm-p2000-50-1z300-1000-10/0215cc32690f64606106d7111dff1cbd56f50f4b244c1d12b00b675cd614b549.jpg)

Figure 1-3: MXM Module Detailed Dimensions and Component Layout

# 1.5.1 MXM Connector Pin Definition

<table><tr><td colspan="3">Primary Side (Underside)</td><td colspan="3">Secondary Side (Top Side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>E1</td><td>PWR_SRC</td><td></td><td>E2</td><td>PWR_SRC</td><td></td></tr><tr><td>E3</td><td>GND</td><td></td><td>E4</td><td>GND</td><td></td></tr><tr><td>1</td><td>5V</td><td></td><td>2</td><td>PRSNT_R#</td><td>0Ω PD</td></tr><tr><td>3</td><td>5V</td><td></td><td>4</td><td>WAKE#</td><td>NI</td></tr><tr><td>5</td><td>5V</td><td></td><td>6</td><td>PWR_GOOD</td><td>NI</td></tr><tr><td>7</td><td>5V</td><td></td><td>8</td><td>PWR_EN</td><td></td></tr><tr><td>9</td><td>5V</td><td></td><td>10</td><td>27MHZ_REF</td><td>NI</td></tr><tr><td>11</td><td>GND</td><td></td><td>12</td><td>GND</td><td></td></tr><tr><td>13</td><td>GND</td><td></td><td>14</td><td>LVDS_U_HPD</td><td>NI</td></tr><tr><td>15</td><td>GND</td><td></td><td>16</td><td>JTAG_TESTEN</td><td></td></tr><tr><td>17</td><td>GND</td><td></td><td>18</td><td>PWR_LEVEL</td><td>100K PU 3.3V</td></tr><tr><td>19</td><td>PEX_STD_SW#</td><td>NI</td><td>20</td><td>TH_OVERT#</td><td>100K PU 3.3V</td></tr><tr><td>21</td><td>VGA_DISABLE#</td><td>NI</td><td>22</td><td>TH_ALERT#</td><td>100K PU 3.3V</td></tr><tr><td>23</td><td>PNL_PWR_EN</td><td></td><td>24</td><td>TH_PWM</td><td>NI</td></tr><tr><td>25</td><td>PNL_BL_EN</td><td></td><td>26</td><td>GPIO0</td><td>NI</td></tr><tr><td>27</td><td>PNL_BL_PWM</td><td></td><td>28</td><td>GPIO1</td><td>NI</td></tr><tr><td>29</td><td>HDMI_CEC</td><td>NI</td><td>30</td><td>GPIO2</td><td>NI</td></tr><tr><td>31</td><td>LVDS_L_HPD</td><td>NI</td><td>32</td><td>SMB_DAT</td><td>10K PU 3.3V</td></tr><tr><td>33</td><td>LVDS_DDC_DAT</td><td>NI</td><td>34</td><td>SMB_CLK</td><td>10K PU 3.3V</td></tr><tr><td>35</td><td>LVDS_DDC_CLK</td><td>NI</td><td>36</td><td>GND</td><td></td></tr><tr><td>37</td><td>GND</td><td></td><td>38</td><td>OEM0</td><td>NI</td></tr><tr><td>39</td><td>OEM1</td><td>NI</td><td>40</td><td>OEM2</td><td>NI</td></tr><tr><td>41</td><td>OEM3</td><td>NI</td><td>42</td><td>OEM4</td><td>NI</td></tr><tr><td>43</td><td>OEM5</td><td>NI</td><td>44</td><td>OEM6</td><td>NI</td></tr><tr><td>45</td><td>OEM7</td><td>NI</td><td>46</td><td>GND</td><td></td></tr></table>

Table 1-6: MXM Connector Pin Definition

<table><tr><td colspan="3">Primary Side (Underside)</td><td colspan="3">Secondary Side (Top Side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>47</td><td>GND</td><td></td><td>48</td><td>PEX_TX15#</td><td></td></tr><tr><td>49</td><td>PEX_RX15#</td><td></td><td>50</td><td>PEX_TX15</td><td></td></tr><tr><td>51</td><td>PEX_RX15</td><td></td><td>52</td><td>GND</td><td></td></tr><tr><td>53</td><td>GND</td><td></td><td>54</td><td>PEX_TX14#</td><td></td></tr><tr><td>55</td><td>PEX_RX14#</td><td></td><td>56</td><td>PEX_TX14</td><td></td></tr><tr><td>57</td><td>PEX_RX14</td><td></td><td>58</td><td>GND</td><td></td></tr><tr><td>59</td><td>GND</td><td></td><td>60</td><td>PEX_TX13#</td><td></td></tr><tr><td>61</td><td>PEX_RX13#</td><td></td><td>62</td><td>PEX_TX13</td><td></td></tr><tr><td>63</td><td>PEX_RX13</td><td></td><td>64</td><td>GND</td><td></td></tr><tr><td>65</td><td>GND</td><td></td><td>66</td><td>PEX_TX12#</td><td></td></tr><tr><td>67</td><td>PEX_RX12#</td><td></td><td>68</td><td>PEX_TX12</td><td></td></tr><tr><td>69</td><td>PEX_RX12</td><td></td><td>70</td><td>GND</td><td></td></tr><tr><td>71</td><td>GND</td><td></td><td>72</td><td>PEX_TX11#</td><td></td></tr><tr><td>73</td><td>PEX_RX11#</td><td></td><td>74</td><td>PEX_TX11</td><td></td></tr><tr><td>75</td><td>PEX_RX11</td><td></td><td>76</td><td>GND</td><td></td></tr><tr><td>77</td><td>GND</td><td></td><td>78</td><td>PEX_TX10#</td><td></td></tr><tr><td>79</td><td>PEX_RX10#</td><td></td><td>80</td><td>PEX_TX10</td><td></td></tr><tr><td>81</td><td>PEX_RX10</td><td></td><td>82</td><td>GND</td><td></td></tr><tr><td>83</td><td>GND</td><td></td><td>84</td><td>PEX_TX9#</td><td></td></tr><tr><td>85</td><td>PEX_RX9#</td><td></td><td>86</td><td>PEX_TX9</td><td></td></tr><tr><td>87</td><td>PEX_RX9</td><td></td><td>88</td><td>GND</td><td></td></tr><tr><td>89</td><td>GND</td><td></td><td>90</td><td>PEX_TX8#</td><td></td></tr><tr><td>91</td><td>PEX_RX8#</td><td></td><td>92</td><td>PEX_TX8</td><td></td></tr><tr><td>93</td><td>PEX_RX8</td><td></td><td>94</td><td>GND</td><td></td></tr><tr><td>95</td><td>GND</td><td></td><td>96</td><td>PEX_TX7#</td><td></td></tr><tr><td>97</td><td>PEX_RX7#</td><td></td><td>98</td><td>PEX_TX7</td><td></td></tr><tr><td>99</td><td>PEX_RX7</td><td></td><td>100</td><td>GND</td><td></td></tr><tr><td>101</td><td>GND</td><td></td><td>102</td><td>PEX_TX6#</td><td></td></tr><tr><td>103</td><td>PEX_RX6#</td><td></td><td>104</td><td>PEX_TX6</td><td></td></tr><tr><td>105</td><td>PEX_RX6</td><td></td><td>106</td><td>GND</td><td></td></tr></table>

Table 1-6: MXM Connector Pin Definition

<table><tr><td colspan="3">Primary Side (Underside)</td><td colspan="3">Secondary Side (Top Side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>107</td><td>GND</td><td></td><td>108</td><td>PEX_TX5#</td><td></td></tr><tr><td>109</td><td>PEX_RX5#</td><td></td><td>110</td><td>PEX_TX5</td><td></td></tr><tr><td>111</td><td>PEX_RX5</td><td></td><td>112</td><td>GND</td><td></td></tr><tr><td>113</td><td>GND</td><td></td><td>114</td><td>PEX_TX4#</td><td></td></tr><tr><td>115</td><td>PEX_RX4#</td><td></td><td>116</td><td>PEX_TX4</td><td></td></tr><tr><td>117</td><td>PEX_RX4</td><td></td><td>118</td><td>GND</td><td></td></tr><tr><td>119</td><td>GND</td><td></td><td>120</td><td>PEX_TX3#</td><td></td></tr><tr><td>121</td><td>PEX_RX3#</td><td></td><td>122</td><td>PEX_TX3</td><td></td></tr><tr><td>123</td><td>PEX_RX3</td><td></td><td>124</td><td>GND</td><td></td></tr><tr><td>125</td><td>GND</td><td></td><td>126</td><td>KEY</td><td></td></tr><tr><td>127</td><td>KEY</td><td></td><td>128</td><td>KEY</td><td></td></tr><tr><td>129</td><td>KEY</td><td></td><td>130</td><td>KEY</td><td></td></tr><tr><td>131</td><td>KEY</td><td></td><td>132</td><td>KEY</td><td></td></tr><tr><td>133</td><td>GND</td><td></td><td>134</td><td>GND</td><td></td></tr><tr><td>135</td><td>PEX_RX2#</td><td></td><td>136</td><td>PEX_TX2#</td><td></td></tr><tr><td>137</td><td>PEX_RX2</td><td></td><td>138</td><td>PEX_TX2</td><td></td></tr><tr><td>139</td><td>GND</td><td></td><td>140</td><td>GND</td><td></td></tr><tr><td>141</td><td>PEX_RX1#</td><td></td><td>142</td><td>PEX_TX1#</td><td></td></tr><tr><td>143</td><td>PEX_RX1</td><td></td><td>144</td><td>PEX_TX1</td><td></td></tr><tr><td>145</td><td>GND</td><td></td><td>146</td><td>GND</td><td></td></tr><tr><td>147</td><td>PEX_RX0#</td><td></td><td>148</td><td>PEX_TX0#</td><td></td></tr><tr><td>149</td><td>PEX_RX0</td><td></td><td>150</td><td>PEX_TX0</td><td></td></tr><tr><td>151</td><td>GND</td><td></td><td>152</td><td>GND</td><td></td></tr><tr><td>153</td><td>PEX_REFCLK#</td><td></td><td>154</td><td>PEX_CLK_REQ#</td><td></td></tr><tr><td>155</td><td>PEX_REFCLK</td><td></td><td>156</td><td>PEX_RST#</td><td></td></tr><tr><td>157</td><td>GND</td><td></td><td>158</td><td>VGA_DDC_DAT</td><td>NI</td></tr><tr><td>159</td><td>JTAG_TDO</td><td></td><td>160</td><td>VGA_DDC_CLK</td><td>NI</td></tr><tr><td>161</td><td>JTAG_TDI</td><td></td><td>162</td><td>VGA_VSYNC</td><td>NI</td></tr><tr><td>163</td><td>JTAG_TCLK</td><td></td><td>164</td><td>VGA_HSYNC</td><td>NI</td></tr><tr><td>165</td><td>JTAG_TMS</td><td></td><td>166</td><td>GND</td><td></td></tr></table>

Table 1-6: MXM Connector Pin Definition

<table><tr><td colspan="3">Primary Side (Underside)</td><td colspan="3">Secondary Side (Top Side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>167</td><td>JTAG_TRST#</td><td></td><td>168</td><td>VGA_RED</td><td>NI</td></tr><tr><td>169</td><td>LVDS_UCLK#</td><td>NI</td><td>170</td><td>VGA_GREEN</td><td>NI</td></tr><tr><td>171</td><td>LVDS_UCLK</td><td>NI</td><td>172</td><td>VGA_BLUE</td><td>NI</td></tr><tr><td>173</td><td>GND</td><td></td><td>174</td><td>GND</td><td></td></tr><tr><td>175</td><td>LVDS_UTX3#</td><td>NI</td><td>176</td><td>LVDS_LCLK#</td><td>NI</td></tr><tr><td>177</td><td>LVDS_UTX3</td><td>NI</td><td>178</td><td>LVDS_LCLK</td><td>NI</td></tr><tr><td>179</td><td>GND</td><td></td><td>180</td><td>GND</td><td></td></tr><tr><td>181</td><td>LVDS_UTX2#</td><td>NI</td><td>182</td><td>LVDS_LTX3#</td><td>NI</td></tr><tr><td>183</td><td>LVDS_UTX2</td><td>NI</td><td>184</td><td>LVDS_LTX3</td><td>NI</td></tr><tr><td>185</td><td>GND</td><td></td><td>186</td><td>GND</td><td></td></tr><tr><td>187</td><td>LVDS_UTX1#</td><td>NI</td><td>188</td><td>LVDS_LTX2#</td><td>NI</td></tr><tr><td>189</td><td>LVDS_UTX1</td><td>NI</td><td>190</td><td>LVDS_LTX2</td><td>NI</td></tr><tr><td>191</td><td>GND</td><td></td><td>192</td><td>GND</td><td></td></tr><tr><td>193</td><td>LVDS_UTX0#</td><td>NI</td><td>194</td><td>LVDS_LTX1#</td><td>NI</td></tr><tr><td>195</td><td>LVDS_UTX0</td><td>NI</td><td>196</td><td>LVDS_LTX1</td><td>NI</td></tr><tr><td>197</td><td>GND</td><td></td><td>198</td><td>GND</td><td></td></tr><tr><td>199</td><td>DP_C_L0#</td><td></td><td>200</td><td>LVDS_LTX0#</td><td>NI</td></tr><tr><td>201</td><td>DP_C_L0</td><td></td><td>202</td><td>LVDS_LTX0</td><td>NI</td></tr><tr><td>203</td><td>GND</td><td></td><td>204</td><td>GND</td><td></td></tr><tr><td>205</td><td>DP_C_L1#</td><td></td><td>206</td><td>DP_D_L0#</td><td></td></tr><tr><td>207</td><td>DP_C_L1</td><td></td><td>208</td><td>DP_D_L0</td><td></td></tr><tr><td>209</td><td>GND</td><td></td><td>210</td><td>GND</td><td></td></tr><tr><td>211</td><td>DP_C_L2#</td><td></td><td>212</td><td>DP_D_L1#</td><td></td></tr><tr><td>213</td><td>DP_C_L2</td><td></td><td>214</td><td>DP_D_L1</td><td></td></tr><tr><td>215</td><td>GND</td><td></td><td>216</td><td>GND</td><td></td></tr><tr><td>217</td><td>DP_C_L3#</td><td></td><td>218</td><td>DP_D_L2#</td><td></td></tr><tr><td>219</td><td>DP_C_L3</td><td></td><td>220</td><td>DP_D_L2</td><td></td></tr><tr><td>221</td><td>GND</td><td></td><td>222</td><td>GND</td><td></td></tr><tr><td>223</td><td>DP_C_AUX#</td><td></td><td>224</td><td>DP_D_L3#</td><td></td></tr><tr><td>225</td><td>DP_C_AUX</td><td></td><td>226</td><td>DP_D_L3</td><td></td></tr></table>

Table 1-6: MXM Connector Pin Definition

<table><tr><td colspan="3">Primary Side (Underside)</td><td colspan="3">Secondary Side (Top Side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>227</td><td>RSVD</td><td></td><td>228</td><td>GND</td><td></td></tr><tr><td>229</td><td>RSVD</td><td></td><td>230</td><td>DP_D_AUX#</td><td></td></tr><tr><td>231</td><td>RSVD</td><td></td><td>232</td><td>DP_D_AUX</td><td></td></tr><tr><td>233</td><td>RSVD</td><td></td><td>234</td><td>DP_C_HPD</td><td></td></tr><tr><td>235</td><td>RSVD</td><td></td><td>236</td><td>DP_D_HPD</td><td></td></tr><tr><td>237</td><td>RSVD</td><td></td><td>238</td><td>RSVD</td><td></td></tr><tr><td>239</td><td>RSVD</td><td></td><td>240</td><td>3V3</td><td></td></tr><tr><td>241</td><td>RSVD</td><td></td><td>242</td><td>3V3</td><td></td></tr><tr><td>243</td><td>RSVD</td><td></td><td>244</td><td>GND</td><td></td></tr><tr><td>245</td><td>RSVD</td><td></td><td>246</td><td>DP_B_L0#</td><td></td></tr><tr><td>247</td><td>RSVD</td><td></td><td>248</td><td>DP_B_L0</td><td></td></tr><tr><td>249</td><td>RSVD</td><td></td><td>250</td><td>GND</td><td></td></tr><tr><td>251</td><td>GND</td><td></td><td>252</td><td>DP_B_L1#</td><td></td></tr><tr><td>253</td><td>DP_A_L0#</td><td></td><td>254</td><td>DP_B_L1</td><td></td></tr><tr><td>255</td><td>DP_A_L0</td><td></td><td>256</td><td>GND</td><td></td></tr><tr><td>257</td><td>GND</td><td></td><td>258</td><td>DP_B_L2#</td><td></td></tr><tr><td>259</td><td>DP_A_L1#</td><td></td><td>260</td><td>DP_B_L2</td><td></td></tr><tr><td>261</td><td>DP_A_L1</td><td></td><td>262</td><td>GND</td><td></td></tr><tr><td>263</td><td>GND</td><td></td><td>264</td><td>DP_B_L3#</td><td></td></tr><tr><td>265</td><td>DP_A_L2#</td><td></td><td>266</td><td>DP_B_L3</td><td></td></tr><tr><td>267</td><td>DP_A_L2</td><td></td><td>268</td><td>GND</td><td></td></tr><tr><td>269</td><td>GND</td><td></td><td>270</td><td>DP_B_AUX#</td><td></td></tr><tr><td>271</td><td>DP_A_L3#</td><td></td><td>272</td><td>DP_B_AUX</td><td></td></tr><tr><td>273</td><td>DP_A_L3</td><td></td><td>274</td><td>DP_B_HPD</td><td></td></tr><tr><td>275</td><td>GND</td><td></td><td>276</td><td>DP_A_HPD</td><td></td></tr><tr><td>277</td><td>DP_A_AUX#</td><td></td><td>278</td><td>3V3</td><td></td></tr><tr><td>279</td><td>DP_A_AUX</td><td></td><td>280</td><td>3V3</td><td></td></tr></table>

Table 1-6: MXM Connector Pin Definition

# 1.6 Thermal Policy

The GPU core clock throttles at temperatures ( $T_{J}$ ) past the thresholds shown with the behaviors as listed. Thermal throttling ensures that the highest temperature on the die does not exceed the sense temperature for prolonged periods of time.

<table><tr><td>Parameter</td><td>Value</td><td>Units</td></tr><tr><td>Thermal Resistance (Junction to Case,  $R_{JC}$ )</td><td>0.03</td><td>°C/W</td></tr><tr><td>Thermal Resistance (Junction to PCB Board,  $R_{JB}$ )</td><td>3.0</td><td>°C/W</td></tr><tr><td>GPU Maximum Operating Temperature $^{1}$ </td><td>94</td><td>°C</td></tr><tr><td>GPU Slowdown Temperature (THERM_ALERT) $^{2}$ </td><td>97</td><td>°C</td></tr><tr><td>GPU Shutdown Temperature (OVERT) $^{3}$ </td><td>102</td><td>°C</td></tr></table>

Table 1-7: Thermal Policy

![The image displays a digital icon of a white document with a folded top-right corner and horizontal lines, overlaid with a large red checkmark.](.egx-mxm-p2000-50-1z300-1000-10/b0c81dadc32ebb9f0d35967b7fd4e7b0ea795ddc1b0759c19df82b8d18162df1.jpg)
NOTE:

1. Max.GPU operating temperature is the maximum at which the GPU is guaranteed to operate at target performance (base clock) under total board power level
2. THERM\_ALERT generates a 50% (÷2) hardware clock slowdown.
3. OVERT generates a 87.5% (÷8) hardware clock slowdown

# 1.7 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

▶ EGX-MXM-P2000 GPU module

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# 2 System Requirements

# 2.1 Power Sequencing

For initial power on, or to resume from S3 and S4, this sequence must be followed.

![| Signal          | Duration (ms) |\n| --------------- | ------------- |\n| PWR_SRC         | ≥0            |\n| 5V              | ≥0            |\n| 3V3             | ≥0            |\n| PWR_EN          | ≥0            |\n| Module Internal Power | ≤90         |\n| PWR_GOOD        | ≤90           |](.egx-mxm-p2000-50-1z300-1000-10/03a87bcc1b4be191cfc7150c7d9b489596e14157ffea3d085e33f5c05cf7579d.jpg)

Figure 2-1: Power Sequencing

# 2.2 Module Power Up and Down

Issuing the PWR\_EN signal powers the MXM module down, and the system designer can decide whether to keep the module input power when the MXM module is powered down.

![| Signal Type           | Value |\n|-----------------------|-------|\n| Module Input Power    | High  |\n| PWR_EN                | Low   |\n| Module Internal Power | Medium|\n| PWR_GOOD              | Low   |](.egx-mxm-p2000-50-1z300-1000-10/9314988a7c4e76a0cfbd11c5eb75ae768576b0446a2b453cc0bd225b473c1289.jpg)

Figure 2-2: Module Power Down

# 2.3 Reset Requirements

![| Signal          | Time Interval        |\n|-----------------|----------------------|\n| Module Input Power | T_PVPERL ≥100 ms    |\n| PWR_EN          | T_PERST-CLK ≥100 μs  |\n| PWR_GOOD        | T_PERST-PG ≥200 μs   |\n| PEX_REFCLK      | T_PERST-CLK ≤500 ns  |\n| PEX_RST#        | T_FAIL ≤500 ns       |](.egx-mxm-p2000-50-1z300-1000-10/293a127ab08ef7e67602ed62d384c952b76e75cb8900ff024cf81488042d6a03.jpg)

Figure 2-3: Reset Sequencing

# 2.4 Dual Mode DisplayPort Implementation

The EGX-MXM-P2000 supports four dual mode DisplayPorts by default. HDMI is supported via dongle (see “Display Support and Options” on page 3.). The system requires a switch circuit to determine whether the AUX or DDC signal is output from the MXM module, and AC coupling capacitors should be placed on the system board.

![Based on the provided block diagram, here is the accurate description of the components and connections:\n\n**Main Blocks:**\n*   **MXM Connector**: A vertical rectangular block on the left side.\n*   **DisplayPort Connector**: A vertical rectangular block on the right side.\n\n**Connections and Components (from top to bottom):**\n\n1.  **AUX Lines:**\n    *   Two lines connect the MXM Connector to the DisplayPort Connector labeled **AUX_P/DDC_CLK** and **AUX_N/DDC_DAT**.\n    *   These lines pass through a large rectangular box containing two switches. Below this box is the text label **CONFIG1 (cable adaptor detect)**.\n    *   A pull-up resistor connects the **AUX_P/DDC_CLK** line to a voltage source labeled **3.3V**.\n    *   A pull-down resistor connects the **AUX_N/DDC_DAT** line to ground.\n\n2.  **Hot Plug Detect:**\n    *   A horizontal line connects the two main connectors. A rectangular box labeled **Hot Plug Detect** is centered on this line.\n\n3.  **DP Data Lines:**\n    *   Two lines at the bottom connect the MXM Connector to the DisplayPort Connector labeled **DP_x_Lx_P** and **DP_x_Lx_N**.\n    *   Near the DisplayPort Connector end, both of these lines pass through series capacitors (represented by parallel vertical lines).](.egx-mxm-p2000-50-1z300-1000-10/b1f80e8fae3e1687058afb179563cc229d068e92aa725ab511e2c0f00f2add6c.jpg)

Figure 2-4: Dual Mode DisplayPort Implementation

# 2.5 DVI/HDMI on DisplayPort Interface

DVI and HDMI connectors can both be implemented through the DisplayPort interface. Circuits required on the system board are as shown. 499Ω with 1% pulldown resistors to the ground on the DP lanes must placed on the DVI/HDMI connector side of the AC coupling, gated by a MOSFET to limit leakage.

![3.3V 3.3V\nHot Plug Detect\nMXM Connector\nAUX P/DDC CLK\nAUX N/DDC DAT\nLevel Shifter\nDVI/HDMI Connector\nDP_x_Lx_P\nDP_x_Lx_N\n499Ω 1%\n499Ω 1%\nPWR_EN](.egx-mxm-p2000-50-1z300-1000-10/ff2283addb686aafb5e7da832f037970d63ae4bb0b7706f95cbb210f40b53711.jpg)

Figure 2-5: DVI/HDMI on DisplayPort Interface

# 2.6 Driver Installation

Drivers can be downloaded from:
https://www.nvidia.com.tw/Download/index.aspx

# 2.7 Certifications & Agencies

▶ Windows Hardware Quality Lab (WHQL) certified Windows 7, and Windows 10
▶ EU Reduction of Hazardous Substances (EU-RoHS)
▶ Conformité Européenne (CE)
▶ Federal Communications Commission (FCC)

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# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing:
▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power
▶ To avoid electrical shock and/or damage to device:
▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▶ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
▶ A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a standard yellow triangular warning sign with a black border and a central black exclamation point. Below the triangle is a white rectangle containing the text 'CAUTION:' in black capital letters.](.egx-mxm-p2000-50-1z300-1000-10/014fe85a3e2c4c8b8c37b7d3c88d9e9cb8dca5ef78c045ec833877901a126331.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d'explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up

It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required

▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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