# COM ![Green five-pointed star shape on white background (no text or symbols)](.express-at-50-1j021-1000-200/15fc3cd0f93ee3d83ebc4a2689d5d5ab59e17137c3a69f485becce48be4c8cdc.jpg) # Express # Express-AT # User’s Manual ![Green printed circuit board with various electronic components and connectors (no visible text or symbols)](.express-at-50-1j021-1000-200/ab74918b3fbd496c46f65163a2e34bdb295cbbc9afa8ca47ea7799ac6680d262.jpg) Manual Revision: 2.00 Revision Date: May 18, 2009 Part Number: 50-1J021-1000 ![The image displays a red logo shaped like a stylized arrow pointing upwards, resembling the letter 'A'. It features three horizontal white stripes across the middle section and a curved bottom edge. In the bottom right corner, a registered trademark symbol (®) is visible.](.express-at-50-1j021-1000-200/c574c208e10eca346fa588bdad67648fd671689e5bbde48d732bc370cb13ac42.jpg) ADLINK TECHNOLOGYINC. Revision History

Release	Date	Change
2.00	May 18, 2009	Initial Release

# Table of Contents # Express-AT . # Preface 5 # 1 Introduction . 1.1 Description . # 2 Specifications . 8 2.1 General . 8 2.2 Integrated Video .. 8 2.3 Audio 9 2.4 LAN . 9 2.5 Multi I/O 9 2.6 Solid State Storage 9 2.7 TPM (Trusted Platform Module) 9 2.8 Super I/O . 9 2.9 Power Specifications . 10 # 3 Functional Diagram . 11 # 4 Mechanical Dimensions 12 # 5 Pinout and Signal Descriptions 13 5.1 COM Express™ Type 2 . 13 5.2 Pin Definitions . 14 5.3 Signal Descriptions . 16 # 6 Embedded Functions . . 25 6.1 Watchdog Timer .. . 25 6.2 GPIO . 26 6.3 Hardware Monitoring .27 # 7 System Resources . 28 7.1 System Memory Map ..... .. 28 7.2 Direct Memory Access Channels . 28 7.3 Legacy I/O Map ....... .. 29 7.4 Interrupt Request (IRQ) Lines . 31 7.5 PCI Configuration Space Map . 32 7.6 PCI Interrupt Routing Map . 33 7.7 SMBus Slave Device Address . 33 # 8 BIOS Setup Utility . . 34 8.1 Starting the BIOS . 34 8.2 Main Setup . 38 8.3 Advanced BIOS Setup . 39 8.4 Power Management . 57 8.5 Boot Setup . . 62 8.6 Security Setup . 66 8.7 Exit Menu . 69 # 9 BIOS Checkpoints, Beep Codes . 71 9.1 Bootblock Initialization Code Checkpoints . 72 9.2 Bootblock Recovery Code Checkpoints . 73 9.3 POST Code Checkpoints .74 9.4 OEM POST Error Checkpoints . 76 9.5 DIM Code Checkpoints . 76 9.6 ACPI Runtime Checkpoints .77 9.7 Boot Block Beep Codes .. 78 9.8 POST BIOS Beep Codes .. 78 9.9 Troubleshooting POST BIOS Beep Codes . 79 # Important Safety Instructions . 80 # Getting Service . 82 # Preface # Copyright 2009 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks AMIBIOS®8 is a registered trademark of American Megatrends, Inc. COM Express™, and PICMG® are registered trademarks of the PCI Industrial Computer Manufacturers Group. Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![An icon featuring a piece of lined paper with a large red checkmark. Below the paper graphic is the text 'NOTE:' in bold, black letters.](.express-at-50-1j021-1000-200/060e308756cf0e021074fdf6cd6669614de3f82b96a160dea5cdd8c0dac5b850.jpg) Additional information, aids, and tips that help users perform tasks. ![The image displays a standard warning sign consisting of a yellow triangle with a black border. Inside the triangle is a black exclamation point. Directly below the triangle, the word 'CAUTION:' is printed in black capital letters.](.express-at-50-1j021-1000-200/21a9ab3cb3f177d047e5c8ec52519b62e98d9963119bc2d20f2ee00f01b51113.jpg) Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image displays a triangular warning sign. It features a red triangle with a black border, containing a large white exclamation point in the center and a small white dot near the bottom edge. Below the triangle, the text 'WARNING:' is written in black, uppercase letters.](.express-at-50-1j021-1000-200/0ea3df82c4308d766e08305915de13f9c4fd46c102334611bf4688c9e103a9c6.jpg) Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # 1 Introduction # 1.1 Description The Express-AT is a low power, low cost, COM Express module specially designed to facilitate speedy development of semi custom designs. The COM Express standard embodies the convergence of the latest technology standards based on serial differential signaling such as PCI Express, USB 2.0, SATA, LVDS and Serial DVO implemented on a compact, 95mm x 125mm, Computer on Module. Signals are brought out through two 220-pin board-to-board connectors that permit data transmission rates of up to 5GHz. Mounting holes connect the module with a custom-made, application specific carrier boards which provide protection from shock and vibration. The Express-AT features a 45nm process Intel® Atom™ processor N270 with 512 kByte L2 cache. The Atom N270 processor has a thermal design power of just 2.5 watts at peak levels while supporting Intel® SpeedStep® Technology. The Intel® Atom™ processor N270 also supports Hyper-Threading Technology allowing it perform like a dual-core processor. ![The image displays the Intel Atom Inside logo. It features the blue text 'intel' inside a swoosh at the top, the blue text 'Atom™' in the center, and the white text 'inside™' on a blue background strip at the bottom.](.express-at-50-1j021-1000-200/e9451ca1dcb99c15d74bb196afd70d4da9164d6533b8ce25d428a2a06a0bdb80.jpg) The Express-AT is positioned as an entry level COM Express module for systems that require a full set of graphics features. The module comes with integrated support for high resolution CRT, single/dual channel LVDS and TV out (SDTV and HDTV). In addition to the onboard integrated graphics, the chipset's SDVO bus can be used to connect to DVI, TMDS or additional LVDS device controllers by extension to a custom designed carrier. Primary focus for applications areas are: Medical Diagnostics and Medical Imaging, Gaming, Industrial Automation, Test and Measurement, Video Preprocessing and Industrial Control. The Express-AT supports up to 2 GB of DDR2 667MHz memory on a single SODIMM socket. The Mobile Intel® 945GSE Express Chipset integrates an Intel® Graphics Media Accelerator 950 that provides CRT, single/dual channel LVDS and TV-out (SDTV and HDTV). In addition to the onboard integrated graphics, the SDVO bus can connect to DVI, TMDS or TV-out device controllers. The board also allows connection of up to three additional PCI Express x1 devices on the Intel® I/O Controller Hub 7-M (ICH7-M) Southbridge. The module comes with a single onboard Gigabit Ethernet port and two SATA ports. It has legacy support for a single parallel IDE channel, 32-bit PCI and LPC. The Express-AT comes equipped with AMIBIOS®8 supporting embedded features such as: Remote Console, CMOS backup, CPU and System Monitoring and a Dual Watchdog Timer for NMI or RESET. ![The image displays a logo containing the text 'ADLINK' in black uppercase letters above the word 'GREEN' in large, bright green uppercase letters. To the right of the text is a graphic of a globe with three green leaves sprouting from the top. Curving around the right side of the globe is the text 'RoHS' at the top and 'Compliant' at the bottom.](.express-at-50-1j021-1000-200/e2ee9fb105a3adcd2f181d20afd0d531ea566213b60f00ccf88e20645eff9baa.jpg) The Express-AT is a RoHS compliant and leadfree product. # 2 Specifications # 2.1 General f CPU: Intel® ATOM™ N270, FSB 533, 1.6 GHz with 512 KB L2 cache, 2.5 W, on-die primary 32-kB instructions cache and 24-kB write-back data cache - 2-thread support - Advanced gunning transceiver logic (AGTL+) bus driver technology - Enhanced Intel® SpeedStep® Technology - Source synchronous double-pumped (2x) Address - Source synchronous quad-pumped (4x) Data - C0\~C4 low power states supported f Memory: Single SODIMM socket memory, for max 2 GB of non-ECC, 400/533 MHz DDR2 f Chipset: Intel® 945GSE Express Graphic Memory Controller Hub and Intel® I/O Controller Hub 7 Mobile (ICH7-M) f BIOS: AMIBIOS®8 with CMOS backup in 8 Mbit SPI BIOS f Hardware Monitor: Supply Voltages and CPU temperature f Watchdog Timer: Programmable timer ranges to generate RESET f Expansion Busses: - 4x PCI Express x1 (0 - 2 free, 3 occupied by GbE LAN) or (0 - 3 free, no GbELAN) \- single SDVO digital video bus \- 32-bit PCI 2.3 at 33MHz, supporting 6 bus masters \- LPC \- SMBus, I2C # 2.2 Integrated Video f Chipset: Intel® Graphics Media Accelerator 950 integrated into 945GSE GMCH supporting dual independent displays f CRT Interface: Analog CRT support up to 2048 x1536 resolution @ 70Hz (QXGA) f LVDS Interface: single or dual channel 18-bit TFT with resolution from 640x480 (VGA) up to 1600x1200 (UXGA) f TV-out: NTSC/PAL up to 1024x768 resolution, HDTV 480p/720p/1080i/1080p modes supported (without Macrovision) # 2.3 Audio f Chipset: Integrated in Intel® I/O Controller Hub 7 Mobile (ICH7M) f Audio Codec: AC97 or HDA type on carrier # 2.4 LAN f Chipset: PCIe x1 type Realtek RTL8111C f Interface: 10/100/1000 Mbps # 2.5 Multi I/O f IDE (PATA): Single channel IDE with UDMA 100 support f SATA: Two ports SATA150 f USB: Supports up to eight ports USB v.2.0 # 2.6 Solid State Storage f IDE based SSD: Optional 512 MB, 1 GB, 2 GB or 4 GB # 2.7 TPM (Trusted Platform Module) f Chipset: Infineon SLB9635TT1.2 f Type: TPM 1.2 # 2.8 Super I/O f Connected to LPC bus on carrier if needed # 2.9 Power Specifications f Input Power: AT mode (12 V) and ATX mode (12 V and $5 \vee _ { \mathtt { S B } } )$ f Power Management: ACPI 3.0 compliant with battery support. All power testing was done on power supply wiring leading to the Express carrier board. Although all voltages were measured, only 12 V and 5 VSB are relevant because they are the only ones used by the Express module. The Idle power level was measured under Windows XP with no applications running (logon screen). CPU Stress was measured using Kpower, and Total System Stress was measured under burn-in conditions. ![Yellow lightning bolt symbol on white background (no text or symbols)](.express-at-50-1j021-1000-200/6a95e6b7eacebe549d9106ec9834a3310907243643aabfd8c4f02cfbe1790f29.jpg) Intel® Atom™ N270, 1.6 GHz

Power State	+12V	$+5V_{SB}$	Power Consumption
DOS (idle)	0.94 A	N.S.	11.3 W
Windows XP logon screen (idle)	0.85 A	N.S.	10.2 W
Windows XP CPU Stress (Kpower)	0.98 A	N.S.	11.8 W
Windows XP Total System Stress (Burnin)	1.09 A	N.S.	13.1 W
S4 Mode (hibernate)	-	322.3 mA	1.61 W
S3 Mode (suspend to RAM)	-	204 mA	1.02 W

CMOS Battery Power Consumption

Current (+3V)	Power
4.1 μA

# 3 Functional Diagram ![**Labeled Blocks:**\n\n* **CPU** (Atom™ N270)\n* **GMCH** (Intel® 945GSE)\n * Analog VGA\n * SDTV HDTV\n * Graphic Core 250 MHz\n * LVDS dual 18-bit\n * Single channel SDVO\n * DDR-2 Memory Controller\n* **DDR2 533 SODIMM socket up to 2 GB**\n* **ICH** (Intel® ICH7M)\n * HDA Audio\n * Four PCIe x1 lanes\n * RTC\n * 2x SATA\n * 8x USB 2.0\n * PATA 1x\n * PCI\n * SMBus\n * SPI\n * LPC\n* **GbE LAN** (Realtek RTL8111C)\n* **Solid State Drive** (512MB up to 8 GB)\n* **TPM**\n* **BIOS**\n* **LPC header**\n* **BC**\n* **GPIO**\n* **LM87**\n* Vertical Bus/Interface Bars: **AB** and **CD**\n\n**Connections:**\n\n* **CPU** connects to **GMCH** via **FSB 533 Mhz**.\n* **GMCH** connects to **DDR2 533 SODIMM socket up to 2 GB** via **Channel A**.\n* **GMCH** connects to **CRT**, **TV-out**, and **LVDS** (all lines route to the **AB** bar).\n* **GMCH** connects to the **CD** bar via **SDVO**.\n* **GMCH** connects to **ICH** via **DMI**.\n* **ICH** connects to **Audio** (routing to **AB**).\n* **ICH** connects to **GbE LAN Realtek RTL8111C** via **PCIe x1 port 3** (routing to **AB**).\n* **ICH** connects to **PCIe x1 lane 0/1/2 (optional 0/1/2/3 for x4)** (routing to **AB**).\n* **ICH** connects to **SATA_0/1** (routing to **AB**).\n* **ICH** connects to **USB_0/1/2/3/4/5/6/7** (routing to **AB**).\n* **ICH** connects to **I2C**, which connects to **BC**, which routes to **AB**.\n* **ICH** connects to **SMBus**, which connects to **GPIO**, which routes to **AB**.\n* **GPIO** connects to **LM87**.\n* **ICH** connects to the **AB** bar via **LPC** (bottom arrow).\n* **ICH** connects to **IDE** (routing to **CD**) via **PATA 1x**.\n* **ICH** connects to **PCI 33 MHz, v2.3** (routing to **CD**) via **PCI**.\n* **ICH** connects to **TPM**, **LPC header**, and **BIOS** via **LPC** and **SPI**.\n* **Solid State Drive** (512MB up to 8 GB) is connected via a dotted line to the **PATA 1x** area.](.express-at-50-1j021-1000-200/da110b2f10797aeaf934e6b8034717c33e557e342b886f2f7afe7c361aae06bb.jpg) # 4 Mechanical Dimensions ![Top View\n82.75\nø6\nø2.7\n4\n91\n45\n125\n121\n80\nconnectors on\nbottom side\n16.5\n4\n0\n63\n18\n6\nSide View](.express-at-50-1j021-1000-200/9288a6da134f89df4bccb31424c719abff37f5371a5bddcc3c7698ba7654d2f4.jpg) All tolerances ± 0.05 mm Other tolerances ± 0.2 mm # 5 Pinout and Signal Descriptions # 5.1 COM Express™ Type 2 All pinouts on AB and CD connector of the Express-AT comply with pin-out and signal descriptions used in the original “PICMG® COM.0 R1.0: COM Express™ Module Base Specification”. This document contains a pinouts, signal descriptions, and mechanical characteristics of the COM Express™ (Express®) form factor. An additional document called, “PICMG COM Express™ Carrier Design Guide” is a detailed 160 pages design reference for custom carrier board designs and is available free of charge. In addtion ADLINK provides baseboard schematics and mechanical design files of our evalation board called Express-BASE to end users to get them started with carrier board design. # AB Connector 1 Gigabit Ethernet port LPC interface 4 Serial ATA channels High Definition Audio 8 USB 2.0 ports 5 PCI Express Lanes x1 Dual 24-bit LVDS channels Analog VGA TV-out ports (SDTV/HDTV) 8 GPIO pins +12V primary power input +5V standby and 3V RTC ![125mm.\n95mm\nAB\nCD](.express-at-50-1j021-1000-200/2bc41e948b4f391fac624198508e2fb2dcf9221cb559852a16189deb6c7e6d11.jpg) # CD Connector Parallel ATA, IDE port alternate definition assigns this to 2 additional Gigabit Ethernet ports 32-bit PCI v2.3 bus alternate definition assigns this to 10 additional PCI Express x1 lanes PCI Express x16 for Graphics these pins can also be assigned to two SDVO extensions (multiplexed) SMB and I2 C bus Power / Thermal control +12V primary power input ![COM\nExpress](.express-at-50-1j021-1000-200/d843766eb378e3403b3ad329d0384c347286b31dcd34b272b565003832fac23a.jpg) # 5.2 Pin Definitions Pinouts for: Basic form factor, Type 2 ![D1\nC1\nD110\nC110](.express-at-50-1j021-1000-200/34899fd79529e1e09e9176efd0729c09b56731785543df00fa959f20e9acdb27.jpg) C D ![B1\nA1\nB110\nA110](.express-at-50-1j021-1000-200/d593bd7a79c400cad16bbc39f8717c00e2f65e6a3c6a21f20bc01d8d05796ebb.jpg) A B ![The image displays three concentric circle patterns arranged horizontally. From left to right, the patterns increase in overall size. Each pattern features a small central solid circle surrounded by eight concentric rings. Moving outward from the center, the rings alternate between thin solid black lines and thicker dashed black lines, beginning with a solid outer ring.](.express-at-50-1j021-1000-200/8ab29f3001dda39061d926e0a5325d79729ae6fecbb3c4e4108ed7a344093015.jpg) ![The image displays three concentric circular patterns arranged horizontally against a white background. Each pattern consists of a central white circle surrounded by alternating thin solid black rings and dashed black rings. The leftmost circle is enclosed by a dashed outer ring, while the middle and rightmost circles are enclosed by a solid outer ring.](.express-at-50-1j021-1000-200/19969092ac4004c4bc89825f1efe820dfb665556c99304ffda182c13221602dd.jpg) Row A Row B

Pin No.	Pin Name	Pin No.	Pin Name
A1	GND (FIXED)	B1	GND (FIXED)
A2	GBE0_MDI3-	B2	GBE0_ACT#
A3	GBE0_MDI3+	B3	LPC_FRAME#
A4	GBE0_LINK100#	B4	LPC_AD0
A5	GBE0_LINK1000#	B5	LPC_AD1
A6	GBE0_MDI2-	B6	LPC_AD2
A7	GBE0_MDI2+	B7	LPC_AD3
A8	GBE0_LINK#	B8	LPC_DRQ0#
A9	GBE0_MDI1-	B9	LPC_DRQ1#
A10	GBE0_MDI1+	B10	LPC_CLK
A11	GND (FIXED)	B11	GND (FIXED)
A12	GBE0_MDI0-	B12	PWRBTN#
A13	GBE0_MDI0+	B13	SMB_CK
A14	GBE0_CTREF	B14	SMB_DAT
A15	SUS_S3#	B15	SMB_ALERT#
A16	SATA0_TX+	B16	SATA1_TX+
A17	SATA0_TX-	B17	SATA1_TX-
A18	SUS_S4#	B18	SUS_STAT#
A19	SATA0_RX+	B19	SATA1_RX+
A20	SATA0_RX-	B20	SATA1_RX-
A21	GND (FIXED)	B21	GND (FIXED)
A22	SATA2_TX+	B22	SATA3_TX+
A23	SATA2_TX-	B23	SATA3_TX-
A24	SUS_S5#	B24	PWR_OK
A25	SATA2_RX+	B25	SATA3_RX+
A26	SATA2_RX-	B26	SATA3_RX-
A27	BATLOW#	B27	WDT
A28	ATA_ACT#	B28	AC_SDIN2
A29	AC_SYNC	B29	AC_SDIN1
A30	AC_RST#	B30	AC_SDIN0
A31	GND (FIXED)	B31	GND (FIXED)
A32	AC_BITCLK	B32	SPKR
A33	AC_SDOUT	B33	I2C_CK
A34	BIOS_DISABLE#	B34	I2C_DAT
A35	THRMTRIP#	B35	THRM#
A36	USB6-	B36	USB7-
A37	USB6+	B37	USB7+
A38	USB_6_7_OC#	B38	USB_4_5_OC#
A39	USB4-	B39	USB5-
A40	USB4+	B40	USB5+
A41	GND (FIXED)	B41	GND (FIXED)
A42	USB2-	B42	USB3-
A43	USB2+	B43	USB3+
A44	USB_2_3_OC#	B44	USB_0_1_OC#
A45	USB0-	B45	USB1-
A46	USB0+	B46	USB1+
A47	VCC_RTC	B47	NC
A48	EXCD0_PERST#	B48	NC
A49	EXCD0_CPPE#	B49	SYS_RESET#
A50	LPC_SERIRQ	B50	CB_RESET#

Row C Row D

Pin No.	Pin Name	Pin No.	Pin Name
C1	GND FIXED)	D1	GND FIXED)
C2	IDE_D7	D2	IDE_D5
C3	IDE_D6	D3	IDE_D10
C4	IDE_D3	D4	IDE_D11
C5	IDE_D15	D5	IDE_D12
C6	IDE_D8	D6	IDE_D4
C7	IDE_D9	D7	IDE_D0
C8	IDE_D2	D8	IDE_REQ
C9	IDE_D13	D9	IDE_IOW#
C10	IDE_D1	D10	IDE_ACK#
C11	GND (FIXED)	D11	GND (FIXED)
C12	IDE_D14	D12	IDE_IRQ
C13	IDE_ORDY	D13	IDE_A0
C14	IDE_IOR#	D14	IDE_A1
C15	PCI_PME#	D15	IDE_A2
C16	PCI_GNT2#	D16	IDE_CS1#
C17	PCI_REQ2#	D17	IDE_CS3#
C18	PCI_GNT1#	D18	IDE_RESET#
C19	PCI_REQ1#	D19	PCI_GNT3#
C20	PCI_GNT0#	D20	PCI_REQ3#
C21	GND (FIXED)	D21	GND (FIXED)
C22	PCI_REQ0#	D22	PCI_AD1
C23	PCI_RESET#	D23	PCI_AD3
C24	PCI_AD0	D24	PCI_AD5
C25	PCI_AD2	D25	PCI_AD7
C26	PCI_AD4	D26	PCI_C/BE0#
C27	PCI_AD6	D27	PCI_AD9
C28	PCI_AD8	D28	PCI_AD11
C29	PCI_AD10	D29	PCI_AD13
C30	PCI_AD12	D30	PCI_AD15
C31	GND (FIXED)	D31	GND (FIXED)
C32	PCI_AD14	D32	PCI_PAR
C33	PCI_C/BE1#	D33	PCI_SERR#
C34	PCI_PERR#	D34	PCI_STOP#
C35	PCI_LOCK#	D35	PCI_TRDY#
C36	PCI_DEVSEL#	D36	PCI_FRAME#
C37	PCI_IRDY#	D37	PCI_AD16
C38	PCI_C/BE2#	D38	PCI_AD18
C39	PCI_AD17	D39	PCI_AD20
C40	PCI_AD19	D40	PCI_AD22
C41	GND (FIXED)	D41	GND (FIXED)
C42	PCI_AD21	D42	PCI_AD24
C43	PCI_AD23	D43	PCI_AD26
C44	PCI_C/BE3#	D44	PCI_AD28
C45	PCI_AD25	D45	PCI_AD30
C46	PCI_AD27	D46	PCI_IRQC#
C47	PCI_AD29	D47	PCI_IRQD#
C48	PCI_AD31	D48	PCI_CLKRUN#
C49	PCI_IRQA#	D49	NC
C50	PCI_IRQB#	D50	PCI_CLK

Row A Row B

Pin No.	Pin Name		Pin No.	Pin Name
A51	GND (FIXED)		B51	GND (FIXED)
A52	PCIE_TX5+		B52	PCIE_RX5+
A53	PCIE_TX5-		B53	PCIE_RX5-
A54	GPIO		B54	GPO1
A55	PCIE_TX4+		B55	PCIE_RX4+
A56	PCIE_TX4-		B56	PCIE_RX4-
A57	GND		B57	GPO2
A58	$PCIE\_TX3+ ^{(1)}$		B58	$PCIE\_RX3+ ^{(1)}$
A59	$PCIE\_TX3- ^{(1)}$		B59	$PCIE\_RX3- ^{(1)}$
A60	GND (FIXED)		B60	GND (FIXED)
A61	PCIE_TX2+		B61	PCIE_RX2+
A62	PCIE_TX2-		B62	PCIE_RX2-
A63	GPI1		B63	GPO3
A64	PCIE_TX1+		B64	PCIE_RX1+
A65	PCIE_TX1-		B65	PCIE_RX1-
A66	GND	B66		WAKE0#
A67	GPI2		B67	WAKE1#
A68	PCIE_TX0+		B68	PCIE_RX0+
A69	PCIE_TX0-		B69	PCIE_RX0-
A70	GND (FIXED)		B70	GND (FIXED)
A71	LVDS_A0+		B71	LVDS_B0+
A72	LVDS_A0-		B72	LVDS_B0-
A73	LVDS_A1+		B73	LVDS_B1+
A74	LVDS_A1-		B74	LVDS_B1-
A75	LVDS_A2+		B75	LVDS_B2+
A76	LVDS_A2-		B76	LVDS_B2-
A77	LVDS_VDD_EN		B77	LVDS_B3+
A78	LVDS_A3+		B78	LVDS_B3-
A79	LVDS_A3-		B79	LVDS_BKLT_EN
A80	GND (FIXED)		B80	GND (FIXED)
A81	LVDS_A_CK+		B81	LVDS_B_CK+
A82	LVDS_A_CK-		B82	LVDS_B_CK-
A83	LVDS_I2C_CK		B83	LVDS_BKLT_CTRL
A84	LVDS_I2C_DAT		B84	VCC_5V_SBY
A85	GPI3		B85	VCC_5V_SBY
A86	KBD_RST#		B86	VCC_5V_SBY
A87	KBD_A20GATE		B87	VCC_5V_SBY
A88	PCIE0_CK_REF+		B88	RSVD
A89	PCIE0_CK_REF-		B89	VGA_RED
A90	GND (FIXED)		B90	GND (FIXED)
A91	RSVD		B91	VGA_GRN
A92	RSVD		B92	VGA_BLU
A93	GPO0		B93	VGA_HSYNC
A94	RSVD		B94	VGA_VSYNC
A95	RSVD		B95	VGA_I2C_CK
A96	GND		B96	VGA_I2C_DAT
A97	VCC_12V		B97	TV_DAC_A
A98	VCC_12V		B98	TV_DAC_B
A99	VCC_12V		B99	TV_DAC_C
A100	GND (FIXED)		B100	GND (FIXED)
A101	VCC_12V		B101	VCC_12V
A102	VCC_12V		B102	VCC_12V
A103	VCC_12V		B103	VCC_12V
A104	VCC_12V		B104	VCC_12V
A105	VCC_12V		B105	VCC_12V
A106	VCC_12V		B106	VCC_12V
A107	VCC_12V		B107	VCC_12V
A108	VCC_12V		B108	VCC_12V
A109	VCC_12V		B109	VCC_12V
A110	GND (FIXED)		B110	GND (FIXED)

Row D

Pin No.	Pin Name	Pin No.	Pin Name
C51	GND (FIXED)	D51	GND (FIXED)
C52	PEG_RX0+	D52	SDVO B [RED]+
C53	PEG_RX0-	D53	SDVO B [RED]-
C54	TYPE0#	D54	PEG_LANE_RV#
C55	PEG_RX1+	D55	SDVO B [GRN]+
C56	PEG_RX1-	D56	SDVO B [GRN]-
C57	TYPE1#	D57	TYPE2#
C58	PEG_RX2+	D58	SDVO B [BLU]+
C59	PEG_RX2-	D59	SDVO B [BLU]-
C60	GND (FIXED)	D60	GND (FIXED)
C61	PEG_RX3+	D61	SDVO B Clock+
C62	PEG_RX3-	D62	SDVO B Clock-
C63	RSVD	D63	RSVD
C64	RSVD	D64	RSVD
C65	PEG_RX4+	D65	SDVO C [RED]+
C66	PEG_RX4-	D66	SDVO C [RED]-
C67	RSVD (1)	D67	GND
C68	PEG_RX5+	D68	SDVO C [GRN]+
C69	PEG_RX5-	D69	SDVO C [GRN]-
C70	GND (FIXED)	D70	GND (FIXED)
C71	PEG_RX6+	D71	SDVO C [BLU]+
C72	PEG_RX6-	D72	SDVO C [BLU]-
C73	SDVO_DATA	D73	SDVO_CLK
C74	PEG_RX7+	D74	SDVO C Clock+
C75	PEG_RX7-	D75	SDVO C Clock-
C76	GND	D76	GND
C77	RSVD	D77	IDE_CBLID#
C78	PEG_RX8+	D78	PEG_TX8+
C79	PEG_RX8-	D79	PEG_TX8-
C80	GND (FIXED)	D80	GND (FIXED)
C81	PEG_RX9+	D81	PEG_TX9+
C82	PEG_RX9-	D82	PEG_TX9-
C83	RSVD	D83	RSVD
C84	GND	D84	GND
C85	PEG_RX10+	D85	PEG_TX10+
C86	PEG_RX10-	D86	PEG_TX10-
C87	GND	D87	GND
C88	PEG_RX11+	D88	PEG_TX11+
C89	PEG_RX11-	D89	PEG_TX11-
C90	GND (FIXED)	D90	GND (FIXED)
C91	PEG_RX12+	D91	PEG_TX12+
C92	PEG_RX12-	D92	PEG_TX12-
C93	GND	D93	GND
C94	PEG_RX13+	D94	PEG_TX13+
C95	PEG_RX13-	D95	PEG_TX13-
C96	GND	D96	GND
C97	RSVD	D97	PEG_ENABLE#
C98	PEG_RX14+	D98	PEG_TX14+
C99	PEG_RX14-	D99	PEG_TX14-
C100	GND (FIXED)	D100	GND (FIXED)
C101	PEG_RX15+	D101	PEG_TX15+
C102	PEG_RX15-	D102	PEG_TX15-
C103	GND	D103	GND
C104	VCC_12V	D104	VCC_12V
C105	VCC_12V	D105	VCC_12V
C106	VCC_12V	D106	VCC_12V
C107	VCC_12V	D107	VCC_12V
C108	VCC_12V	D108	VCC_12V
C109	VCC_12V	D109	VCC_12V
C110	GND (FIXED)	D110	GND (FIXED)

![The image features a white document icon with faint horizontal lines and a large red checkmark on the left. Below the icon is the text 'NOTE:' in bold black letters, followed by horizontal gray lines.](.express-at-50-1j021-1000-200/3abd241df0370dce6cffa52b8a7809913080b3a275475ec5ba1a307f7d4a5bb3.jpg) XXX Strikethrough pins are not supported on this module (1) The 4th PCI Express x1 port (PCIE3) is occupied by the on-board LAN controller. There is a BOM option to remove the LAN and make the 4th PCI Express port available for 4 x1 or 1 x4. 5.3 Signal Descriptions Row A

Pin	Signal	Description	Type	PU/PD	Comment
A1	GND	Ground	PWR	-	-
A2	GBE0_MDI3-	Ethernet Media Dependent Interface -	I/O - DP	-	-
A3	GBE0_MDI3+	Ethernet Media Dependent Interface +	I/O - DP	-	-
A4	GBE0_LINK100#	Ethernet Speed LED (100Mb)	O-3.3	-	On at 100Mb/s
A5	GBE0_LINK1000#	Ethernet Speed LED (1000Mb)	O-3.3	-	On at 1000Mb/s
A6	GBE0_MDI2-	Ethernet Media Dependent Interface -	I/O - DP	-	-
A7	GBE0_MDI2+	Ethernet Media Dependent Interface +	I/O - DP	-	-
A8	GBE0_LINK#	LAN Link LED	O-3.3	-	-
A9	GBE0_MDI1-	Ethernet Media Dependent Interface -	I/O - DP	-	-
A10	GBE0_MDI1+	Ethernet Media Dependent Interface +	I/O - DP	-	-
A11	GND	Ground	PWR	-	-
A12	GBE0_MDI0-	Ethernet Media Dependent Interface -	I/O - DP	-	-
A13	GBE0_MDI0+	Ethernet Media Dependent Interface +	I/O - DP	-	-
A14	GBE0_CTREF	ETHCTREF	O-1,8	-	NC
A15	SUS_S3#	PM_SLP_S#3	O-3.3	-	-
A16	SATA0_TX+	SATA0_TX+ \| SATA 0 Transmit Data +	O - DP	-	-
A17	SATA0_TX-	SATA0_TX- \| SATA 0 Transmit Data -	O - DP	-	-
A18	SUS_S4#	PM_SLP_S#4	O-3.3	-	-
A19	SATA0_RX+	SATA0_RX+ \| SATA 0 Receive Data +	I - DP	-	-
A20	SATA0_RX-	SATA0_RX - \| SATA 0 Receive Data -	I - DP	-	-
A21	GND	Ground	PWR	-	-
A22	SATA2_TX+	SATA2_TX+ \| SATA 2 Transmit Data +	O - DP	-	not supported
A23	SATA2_TX-	SATA2_TX- \| SATA 2 Transmit Data -	O - DP	-	not supported
A24	SUS_S5#	PM_SLP_S#5	O-3.3	-	-
A25	SATA2_RX+	SATA2_RX+ \| SATA 2 Receive Data +	I - DP	-	not supported
A26	SATA2_RX-	SATA2_RX- \| SATA 2 Receive Data -	I - DP	-	not supported
A27	BATLOW#	PM_BATLOW# \| Battery Low	I-3.3	PU 8k2 3.3Vsb	-
A28	ATA_ACT#	ATA_LED# \| SATA LED	O-3.3	PU 10k 3.3V	int. PU 15k in ICH7
A29	AC_SYNC	AC_SYNC \| AC'97 Sync	O-3.3	-	int. PD 20k in ICH7
A30	AC_RST#	AC_RST# \| AC'97 Reset	O-3.3	-	int. PD 20k in ICH7
A31	GND	Ground	PWR	-
A32	AC_BITCLK	AC_BITCLK \| AC'97 Clock	O-3.3	-	int. PD 20k in ICH7
A33	AC_SDOUT	AC_SDATAOUT \| AC'97 Data	O-3.3	-	int. PD 20k in ICH7
A34	BIOS_DISABLE#	BIOS_DISABLE#	I-3.3	PU 10k 3.3Vsb	-
A35	THRMTRIP#	PM_THRMTRIP#_CON	O-3.3	PU 330R 3.3V	-
A36	USB6-	USB_PN6 \| USB Data - Port6	I/O - DP	-	int. PD 15k in ICH7
A37	USB6+	USB_PP6 \| USB Data + Port6	I/O - DP	-	int. PD 15k in ICH7
A38	USB_6_7_OC#	USB_OC#_6_7 \| USB OverCurrent Port 6/7	I-3.3	PU 10k 3.3Vsb	-
A39	USB4-	USB_PN4 \| USB Data - Port4	I/O - DP	-	int. PD 15k in ICH7
A40	USB4+	USB_PP4 \| USB Data + Port4	I/O - DP	-	int. PD 15k in ICH7
A41	GND	Ground	PWR	-	-
A42	USB2-	USB_PN2 \| USB Data - Port2	I/O - DP	-	int. PD 15k in ICH7
A43	USB2+	USB_PP2 \| USB Data + Port2	I/O - DP	-	int. PD 15k in ICH7
A44	USB_2_3_OC#	USB_OC#_2_3 \| USB OverCurrent Port 2/3	I-3.3	PU 10k 3.3Vsb
A45	USB0-	USB_PN0 \| USB Data - Port0	I/O - DP	-	int. PD 15k in ICH7
A46	USB0+	USB_PP0 \| USB Data + Port0	I/O - DP	-	int. PD 15k in ICH7
A47	VCC_RTC	V_BAT	PWR	-	-
A48	EXCD0_PERST#	Express Card Support [0] \| card reset	O-3.3	PU 10k 3.3Vsb	-
A49	EXCD0_CPPE#	Express Card Support [0] \| capable c. request	I-3.3	PU 10k 3.3V	-
A50	LPC_SERIRQ	INT_SERIRQ \| Serial Interrupt Request	IO-3.3	PU 8k2 3.3V	-
A51	GND	Ground	PWR	-	-
A52	PCIE5_TX+	PCI Express 5 Transmit +	NC	-	not supported
A53	PCIE5_TX-	PCI Express 5 Transmit -	NC	-	not supported
A54	GPIO	General Purpose Input 0	I-3.3	PU 10k 3.3Vsb	-
A55	PCIE4_TX+	PCI Express 4 Transmit +	O - DP	-	not supported

# Signal Descriptions (cont’d) # Row A

Pin	Signal	Description	Type	PU/PD	Comment
A56	PCIE4_TX-	PCI Express 4 Transmit -	O - DP	-	not supported
A57	GND	Ground	PWR	-	-
A58	PCIE3_TX+	PCI Express 3 Transmit + (occupied by LAN)	O - DP	-	Optional : O - DP
A59	PCIE3_TX-	PCI Express 3 Transmit - (occupied by LAN)	O - DP	-	Optional : O - DP
A60	GND	Ground	PWR	-	-
A61	PCIE2_TX+	PCI Express 2 Transmit +	O - DP	-	-
A62	PCIE2_TX-	PCI Express 2 Transmit -	O - DP	-	-
A63	GPI1	General Purpose Input 1	I-3.3	PU 10k 3.3Vsb	-
A64	PCIE1_TX+	PCI Express 1 Transmit +	O - DP	-	-
A65	PCIE1_TX-	PCI Express 1 Transmit -	O - DP	-	-
A66	GND	Ground	PWR	-	-
A67	GPI2	General Purpose Input 2	I-3.3	PU 10k 3.3Vsb	-
A68	PCIE0_TX+	PCI Express 0 +	O - DP	-	-
A69	PCIE0_TX-	PCI Express 0 -	O - DP	-	-
A70	GND	Ground	PWR	-	-
A71	LVDS_A0+	LVDS_AP0 \| LVDS Channel A	O - DP	-	-
A72	LVDS_A0-	LVDS_AN0 \| LVDS Channel A	O - DP	-	-
A73	LVDS_A1+	LVDS_AP1 \| LVDS Channel A	O - DP	-	-
A74	LVDS_A1-	LVDS_AN1 \| LVDS Channel A	O - DP	-	-
A75	LVDS_A2+	LVDS_AP2 \| LVDS Channel A	O - DP	-	-
A76	LVDS_A2-	LVDS_AN2 \| LVDS Channel A	O - DP	-	-
A77	LVDS_VDD_EN	LVDS_VDDEN \| LVDS Panel Power	O-2,5	PD 100k	-
A78	LVDS_A3+	LVDS_AP3 \| LVDS Channel A	O - DP	-	not supported, no 24-bit
A79	LVDS_A3-	LVDS_AN3 \| LVDS Channel A	O - DP	-	not supported, no 24-bit
A80	GND	Ground	PWR	-	-
A81	LVDS_A_CK+	LVDS_CLKAP \| LVDS Channel A	O - DP	-	-
A82	LVDS_A_CK-	LVDS_CLKAN \| LVDS Channel A	O - DP	-	-
A83	LVDS_I2C_CK	LVDS_DDCPCLK \| JILI I2C Clock	IO-3.3	PU 10k 3.3V	-
A84	LVDS_I2C_DAT	LVDS_DDCPDATA \| JILI I2C Data	IO-3.3	PU 10k 3.3V	-
A85	GPI3	General Purpose Input 3	I-3.3	PU 10k 3.3Vsb	-
A86	KBD_RST#	H_RCIN# \| Keyboard Reset	I-3.3	PU 10k 3.3V	-
A87	KBD_A20GATE	H_A20GATE	I-3.3	PU 10k 3.3V	-
A88	PCIE_CK_REF+	CLK_PCIE_REF P	O - DP	-	-
A89	PCIE_CK_REF-	CLK_PCIE_REF N	O - DP	-	-
A90	GND	Ground	PWR	-	-
A91	RSVD		NC	-	-
A92	RSVD		NC	-	-
A93	GPO0	General Purpose Output 0	O-3.3	PU 10k 3.3Vsb	-
A94	RSVD		NC	-	-
A95	RSVD		NC	-	-
A96	GND	Ground	PWR	-	-
A97	VCC_12V	Power 12V	PWR	-	-
A98	VCC_12V	Power 12V	PWR	-	-
A99	VCC_12V	Power 12V	PWR	-	-
A100	GND	Ground	PWR	-	-
A101	VCC_12V	Power 12V	PWR	-	-
A102	VCC_12V	Power 12V	PWR	-	-
A103	VCC_12V	Power 12V	PWR	-	-
A104	VCC_12V	Power 12V	PWR	-	-
A105	VCC_12V	Power 12V	PWR	-	-
A106	VCC_12V	Power 12V	PWR	-	-
A107	VCC_12V	Power 12V	PWR	-	-
A108	VCC_12V	Power 12V	PWR	-	-
A109	VCC_12V	Power 12V	PWR	-	-
A110	GND	Ground	PWR	-	-
B1	GND	Ground	PWR	-	-
B2	GBE0_ACT#	LAN_ACTLED# \| Ethernet Activity LED	O-3.3	-	-
B3	LPC_FRAME#	LPC_FRAME# \| LPC Frame Indicator	O-3.3	-	-
B4	LPC_AD0	LPC_AD0 \| LPC Adress & DATA Bus	IO-3.3	-	int. PU 20k in ICH7
B5	LPC_AD1	LPC_AD1 \| LPC Adress & DATA Bus	IO-3.3	-	int. PU 20k in ICH7
B6	LPC_AD2	LPC_AD2 \| LPC Adress & DATA Bus	IO-3.3	-	int. PU 20k in ICH7
B7	LPC_AD3	LPC_AD3 \| LPC Adress & DATA Bus	IO-3.3	-	int. PU 20k in ICH7
B8	LPC_DRQ0#	SIO_DRQ#0 \| LPC Serial DMA Request 0	I-3.3	-	int. PU 20k in ICH7
B9	LPC_DRQ1#	SIO_DRQ#1 \| LPC Serial DMA Request 1	I-3.3	-	int. PU 20k in ICH7
B10	LPC_CLK	CLK_SIOEXTPCI	O-3.3	-	-
B11	GND	Ground	I-3.3	-	-
B12	PWRBTN#	Power Button	I-3.3	PU 10K 3.3Vsb	-
B13	SMB_CK	SMBUS Clock	O-3.3	PU 2k2 3.3V	-
B14	SMB_DAT	SMBUS Data	IO-3.3	PU 2k2 3.3V	-
B15	SMB_ALERT#	SMB_ALERT#	I-3.3	PU 10k 3.3Vsb	-
B16	SATA1_TX+	SATA1_TX+ \| SATA 1 Transmit Data +	O - DP	-	-
B17	SATA1_TX-	SATA1_TX- \| SATA 1 Transmit Data -	O - DP	-	-
B18	SUS_STAT#	PM_SUS_STAT#	O-3.3	-	-
B19	SATA1_RX+	SATA1_RX+ \| SATA 1 Receive Data +	I - DP	-	-
B20	SATA1_RX-	SATA1_RX - \| SATA 1 Receive Data -	I - DP	-	-
B21	GND	Ground	PWR	-	-
B22	SATA3_TX+	SATA3_TX+ \| SATA 3 Transmit Data +	NC	-	not supported
B23	SATA3_TX-	SATA3_TX- \| SATA 3 Transmit Data -	NC	-	not supported
B24	PWR_OK	Power OK	I-3.3	-	-
B25	SATA3_RX+	SATA3_RX+ \| SATA 3 Receive Data +	NC	-	not supported
B26	SATA3_RX-	SATA3_RX - \| SATA 3 Receive Data -	NC	-	not supported
B27	WDT	Watch Dog Timer	O-3.3	-	-
B28	AC_SDIN2	AC_SDATAIN2	I-3.3	-	int. PD 20k in ICH7
B29	AC_SDIN1	AC_SDATAIN1	I-3.3	-	int. PD 20k in ICH7
B30	AC_SDIN0	AC_SDATAIN0	I-3.3	-	int. PD 20k in ICH7
B31	GND	Ground	PWR	-
B32	SPKR	AC_SPKR	O-3.3	-	int. PD 20k in ICH7
B33	I2C_CK	I2CLK	O-3.3	PU 10k 3.3Vsb	-
B34	I2C_DAT	I2DAT	IO-3.3	PU 10k 3.3Vsb	-
B35	THRM#	PM THRM# CON \| Over Temperature	I-3.3	-	-
B36	USB7-	USB_PN7 \| USB Data - Port7	I/O - DP	-	int. PD 15k in ICH7
B37	USB7+	USB_PP7 \| USB Data + Port7	I/O - DP	-	int. PD 15k in ICH7
B38	USB_4_5_OC#	USB_OC#_4_5 \| USB OverCurrent Port	I-3.3	PU 10k 3.3Vsb
B39	USB5-	USB_PN5 \| USB Data- Port5	I/O - DP	-	int. PD 15k in ICH7
B40	USB5+	USB_PP5 \| USB Data+ Port5	I/O - DP	-	int. PD 15k in ICH7
B41	GND	Ground	PWR	-	-
B42	USB3-	USB_PN3 \| USB Data- Port3	I/O - DP	-	int. PD 15k in ICH7
B43	USB3+	USB_PP3 \| USB Data+ Port3	I/O - DP	-	int. PD 15k in ICH7
B44	USB_0_1_OC#	USB_OC#_0_1 \| USB OverCurrent Port	I-3.3	PU 10k 3.3Vsb	-
B45	USB1-	USB_PN1 \| USB Data- Port1	I/O - DP	-	int. PD 15k in ICH7
B46	USB1+	USB_PP1 \| USB Data+ Port1	I/O - DP	-	int. PD 15k in ICH7
B47	EXCD1_PERST#	Express Card Support [1]\|card reset	O-3.3	PU 10k 3.3Vsb	-
B48	EXCD1_CPPE#	Express Card Support [1] capable c.	I-3.3	PU 10k 3.3V	-
B49	SYS_RESET#	ETX_SYS_RESET# \| Reset Input	I-3.3	PU 10k 3.3V	-
B50	CB_RESET#	PCI_RST# \| PCI Bus Reset	O-3.3	-	-
B51	GND	Ground	PWR	-	-
B52	PCIE5_RX+	PCI Express 5 Recieve +	NC	-	not supported
B53	PCIE5_RX-	PCI Express 5 Receive -	NC	-	not supported
B54	GPO1	General Purpose Output 1	O-3.3	PU 10k 3.3Vsb	-
B55	PCIE4_RX+	PCI Express 4 Recieve +	I - DP	-	not supported

# Signal Descriptions (cont’d) # Row B

Pin	Signal	Description	Type	PU/PD	Comment
B56	PCIE4_RX-	PCI Express 4 Receive -	I - DP	-	not supported
B57	GPO2	General Purpose Output 2	O-3.3	PU 10k 3.3Vsb	-
B58	PCIE3_RX+	PCI Express 3 Recieve + (occupied by LAN)	I - DP	-	Optional: I - DP
B59	PCIE3_RX-	PCI Express 3 Receive - (occupied by LAN)	I - DP	-	Optional: I - DP
B60	GND	Ground	PWR	-	-
B61	PCIE2_RX+	PCI Express 2 Receive +	I - DP	-	-
B62	PCIE2_RX-	PCI Express 2 Receive -	I - DP	-	-
B63	GPO3	General Purpose Output 3	O-3.3	PU 10k 3.3Vsb	-
B64	PCIE1_RX+	PCI Express 1 Receive +	I - DP	-	-
B65	PCIE1_RX-	PCI Express 1 Receive -	I - DP	-	-
B66	WAKE0#	PCIE_WAKEI#	I-3.3	PU 1k 3.3Vsb	-
B67	WAKE1#	WAKE1#	I-3.3	PU 10k 3.3Vsb	-
B68	PCIE0_RX+	PCI Express 0 Receive +	I - DP	-	-
B69	PCIE0_RX-	PCI Express 0 Receive -	I - DP	-	-
B70	GND	Ground	PWR	-	-
B71	LVDS_B0+	LVDS_BP0 \| LVDS Channel B Data0+	O - DP	-	-
B72	LVDS_B0-	LVDS_BN0 \| LVDS Channel B Data0-	O - DP	-	-
B73	LVDS_B1+	LVDS_BP1 \| LVDS Channel B Data1+	O - DP	-	-
B74	LVDS_B1-	LVDS_BN1 \| LVDS Channel B Data1-	O - DP	-	-
B75	LVDS_B2+	LVDS_BP2 \| LVDS Channel B Data2+	O - DP	-	-
B76	LVDS_B2-	LVDS_BN2 \| LVDS Channel B Data2-	O - DP	-	-
B77	LVDS_B3+	LVDS_BP3 \| LVDS Channel B Data3+	O - DP	-	not supported, no 24-bit
B78	LVDS_B3-	LVDS_BN3 \| LVDS Channel B Data3-	O - DP	-	not supported, no 24-bit
B79	LVDS_BKLT_EN	LVDS Panel Backlight Enable	O-3.3	PD 100k 3.3V	-
B80	GND	Ground	PWR	-	-
B81	LVDS_B_CK+	LVDS_CLKBP \| LVDS Channel B	O - DP	-	-
B82	LVDS_B_CK-	LVDS_CLKBM \| LVDS Channel B	O - DP	-	-
B83	LVDS_BKLT_CTRL	Backlight Brightness	O-3.3	-	-
B84	VCC_5V_SBY	5V Standby	PWR	-	-
B85	VCC_5V_SBY	5V Standby	PWR	-	-
B86	VCC_5V_SBY	5V Standby	PWR	-	-
B87	VCC_5V_SBY	5V Standby	PWR	-	-
B88	RSVD	NC	NC	-	-
B89	VGA_RED	Analog Video RGB-RED	OA	PD 150R	-
B90	GND	Ground	PWR	-	-
B91	VGA_GRN	Analog Video RGB-GREEN	OA	PD 150R	-
B92	VGA_BLU	Analog Video RGB-BLUE	OA	PD 150R	-
B93	VGA_HSYNC	Analog Video H-Sync	O-3.3	-	-
B94	VGA_VSYNC	Analog Video V-Sync	O-3.3	-	-
B95	VGA_I2C_CK	Display Data Channel - Clock	O-3.3	PU 2k2 3.3V	-
B96	VGA_I2C_DAT	Display Data Channel - Data	IO-3.3	PU 2k2 3.3V	-
B97	TV_DAC_A	Composite CVBS	OA	PD 150R	-
B98	TV_DAC_B	TV Luminance Signal	OA	PD 150R	-
B99	TV_DAC_C	TV Chrominance Signal	OA	PD 150R	-
B100	GND	Ground	PWR	-	-
B101	VCC_12V	Power 12V	PWR	-	-
B102	VCC_12V	Power 12V	PWR	-	-
B103	VCC_12V	Power 12V	PWR	-	-
B104	VCC_12V	Power 12V	PWR	-	-
B105	VCC_12V	Power 12V	PWR	-	-
B106	VCC_12V	Power 12V	PWR	-	-
B107	VCC_12V	Power 12V	PWR	-	-
B108	VCC_12V	Power 12V	PWR	-	-
B109	VCC_12V	Power 12V	PWR	-	-
B110	GND	Ground	PWR	-	-
C1	GND	Ground	PWR	-	-
C2	IDE_D7	IDE Data Bus	IO	-	int.PD 11.5k in ICH7
C3	IDE_D6	IDE Data Bus	IO	-	-
C4	IDE_D3	IDE Data Bus	IO	-	-
C5	IDE_D15	IDE Data Bus	IO	-	-
C6	IDE_D8	IDE Data Bus	IO	-	-
C7	IDE_D9	IDE Data Bus	IO	-	-
C8	IDE_D2	IDE Data Bus	IO	-	-
C9	IDE_D13	IDE Data Bus	IO	-	-
C10	IDE_D1	IDE Data Bus	IO	-	-
C11	GND	Ground	PWR	-	-
C12	IDE_D14	IDE Data Bus	IO	-	-
C13	IDE_IORDY	IDE I/O Ready	I-3.3	PU 4K7 3.3V	-
C14	IDE_IOR#	I/O read line to IDE device	O-3.3		-
C15	PCI_PME#	PCI Power Management Event	IO-3.3		int. PU 20k in ICH7
C16	PCI_GNT2#	PCI Bus Grant 2	O-3.3		int. PU 20k in ICH7
C17	PCI_REQ2#	PCI Bus Request 2	I-3.3	PU 8K2 3.3V	-
C18	PCI_GNT1#	PCI Bus Grant 1	O-3.3		int. PU 20k in ICH7
C19	PCI_REQ1#	PCI Bus Request 1	I-3.3	PU 8K2 3.3V	-
C20	PCI_GNT0#	PCI Bus Grant 0	O-3.3		int. PU 20k in ICH7
C21	GND	Ground	PWR		-
C22	PCI_REQ0#	PCI Bus Request 0	I-3.3	PU 8K2 3.3V	-
C23	PCI_RESET#	PCI Bus Reset	O-3.3	-	-
C24	PCI_AD0	PCI Adress & Data Bus line	IO-3.3	-	-
C25	PCI_AD2	PCI Adress & Data Bus line	IO-3.3	-	-
C26	PCI_AD4	PCI Adress & Data Bus line	IO-3.3	-	-
C27	PCI_AD6	PCI Adress & Data Bus line	IO-3.3	-	-
C28	PCI_AD8	PCI Adress & Data Bus line	IO-3.3	-	-
C29	PCI_AD10	PCI Adress & Data Bus line	IO-3.3	-	-
C30	PCI_AD12	PCI Adress & Data Bus line	IO-3.3	-	-
C31	GND	Ground	PWR	-	-
C32	PCI_AD14	PCI Adress & Data Bus line	IO-3.3	-	-
C33	PCI_C/BE1#	PCI Bus Command and Byte enables	IO-3.3	-	-
C34	PCI_PERR#	PCI Bus Grant Error	IO-3.3	PU 8K2 3.3V	-
C35	PCI_LOCK#	PCI Bus Lock	IO-3.3	PU 8K2 3.3V	-
C36	PCI_DEVSEL#	PCI Bus Device Select	IO-3.3	PU 8K2 3.3V	-
C37	PCIIRDY#	PCI Bus Bus Initiator Ready	IO-3.3	PU 8K2 3.3V	-
C38	PCI_C/BE2#	PCI Bus Command and Byte enables	IO-3.3		-
C39	PCI_AD17	PCI Adress & Data Bus line	IO-3.3	-	-
C40	PCI_AD19	PCI Adress & Data Bus line	IO-3.3	-	-
C41	GND	Ground	PWR	-	-
C42	PCI_AD21	PCI Adress & Data Bus line	IO-3.3	-	-
C43	PCI_AD23	PCI Adress & Data Bus line	IO-3.3	-	-
C44	PCI_C/BE3#	PCI Bus Command and Byte enables	IO-3.3	-	-
C45	PCI_AD25	PCI Adress & Data Bus line	IO-3.3	-	-
C46	PCI_AD27	PCI Adress & Data Bus line	IO-3.3	-	-
C47	PCI_AD29	PCI Adress & Data Bus line	IO-3.3	-	-
C48	PCI_AD31	PCI Adress & Data Bus line	IO-3.3		-
C49	PCI_IRQA#	PCI Bus Interrupt Request A	I-3.3	PU 8K2 3.3V	-
C50	PCI_IRQB#	PCI Bus Interrupt Request B	I-3.3	PU 8K2 3.3V	-
C51	GND	Ground	PWR		-
C52	PEG_RX0+	PCIe 0 Recieve + / SDVO TV clock +	I - DP		only SDVO supported
C53	PEG_RX0-	PCIe 0 Recieve - / SDVO TV clock -	I - DP	-	only SDVO supported
C54	TYPE0#	Module type ID pin 0	STO	-	not connected
C55	PEG_RX1+	PCIe 1 Recieve + / SDVO B Interrupt +	I - DP	-	only SDVO supported

# Signal Descriptions (cont’d) # Row C

Pin	Signal	Description	Type	PU/PD	Comment
C56	PEG_RX1-	PCIe 1 Recieve - / SDVO B interrupt -	I - DP	-	only SDVO supported
C57	TYPE1#	Module type ID pin 1	STO	-	not connected
C58	PEG_RX2+	PCIe 2 Recieve + / SDVO Field stall +	I - DP	-	only SDVO supported
C59	PEG_RX2-	PCIe 2 Recieve - / SDVO Field stall -	I - DP	-	only SDVO supported
C60	GND	Ground	PWR	-	-
C61	PEG_RX3+	PCIe 3 Recieve +	I - DP	-	not supported
C62	PEG_RX3-	PCIe 3 Recieve -	I - DP	-	not supported
C63	RSVD	Rx from Board Controller	I-3.3	-	-
C64	RSVD	Tx from Board Controller	O-3.3	-	-
C65	PEG_RX4+	PCIe 4 Recieve +	I - DP	-	not supported
C66	PEG_RX4-	PCIe 4 Recieve -	I - DP	-	not supported
C67	RSVD	FAN_PWM_CTRL	0-5	-	-
C68	PEG_RX5+	PCIe 5 Recieve + / SDVO C Interrupt +	I - DP	-	not supported
C69	PEG_RX5-	PCIe 5 Recieve - / SDVO C interrupt -	I - DP	-	not supported
C70	GND	Ground	PWR	-	-
C71	PEG_RX6+	PCIe 6 Recieve +	I - DP	-	not supported
C72	PEG_RX6-	PCIe 6 Recieve -	I - DP	-	not supported
C73	SDVO_DATA	SDVO_CTRLDATA	IO-2,5	-	-
C74	PEG_RX7+	PCIe 7 Recieve +	I - DP	-	not supported
C75	PEG_RX7-	PCIe 7 Recieve -	I - DP	-	not supported
C76	GND	Ground	PWR	-	-
C77	RSVD	FAN_TACH	I-5	-	-
C78	PEG_RX8+	PCIe 8 Recieve +	I - DP	-	not supported
C79	PEG_RX8-	PCIe 8 Recieve -	I - DP	-	not supported
C80	GND	Ground	PWR	-	-
C81	PEG_RX9+	PCIe 9 Recieve +	I - DP	-	not supported
C82	PEG_RX9-	PCIe 9 Recieve -	I - DP	-	not supported
C83	RSVD	Physical Presence	I-3.3	-	-
C84	GND	Ground	PWR	-	-
C85	PEG_RX10+	PCIe 10 Recieve +	I - DP	-	not supported
C86	PEG_RX10-	PCIe 10 Recieve -	I - DP	-	not supported
C87	GND	Ground	PWR	-	-
C88	PEG_RX11+	PCIe 11 Recieve +	I - DP	-	not supported
C89	PEG_RX11-	PCIe 11 Recieve -	I - DP	-	not supported
C90	GND	Ground	PWR	-	-
C91	PEG_RX12+	PCIe 12 Recieve +	I - DP	-	not supported
C92	PEG_RX12-	PCIe 12 Recieve -	I - DP	-	not supported
C93	GND	Ground	PWR	-	-
C94	PEG_RX13+	PCIe 13 Recieve +	I - DP	-	not supported
C95	PEG_RX13-	PCIe 13 Recieve -	I - DP	-	not supported
C96	GND	Ground	PWR	-	-
C97	RSVD	NC	NC	-	-
C98	PEG_RX14+	PCIe 14 Recieve +	I - DP	-	not supported
C99	PEG_RX14-	PCIe 14 Recieve -	I - DP	-	not supported
C100	GND	Ground	PWR	-	-
C101	PEG_RX15+	PCIe 15 Recieve +	I - DP	-	not supported
C102	PEG_RX15-	PCIe 15 Recieve -	I - DP	-	not supported
C103	GND	Ground	PWR	-	-
C104	VCC_12V	Power 12V	PWR	-	-
C105	VCC_12V	Power 12V	PWR	-	-
C106	VCC_12V	Power 12V	PWR	-	-
C107	VCC_12V	Power 12V	PWR	-	-
C108	VCC_12V	Power 12V	PWR	-	-
C109	VCC_12V	Power 12V	PWR	-	-
C110	GND	Ground	PWR	-	-
D1	GND	Ground	PWR	-	-
D2	IDE_D5	IDE Data Bus	IO	-	-
D3	IDE_D10	IDE Data Bus	IO	-	-
D4	IDE_D11	IDE Data Bus	IO	-	-
D5	IDE_D12	IDE Data Bus	IO	-	-
D6	IDE_D4	IDE Data Bus	IO	-	-
D7	IDE_D0	IDE Data Bus	IO	-	-
D8	IDE_REQ#	IDE Device DMA Request.	IO	-	int. PD 11.5k in ICH7
D9	IDE_IOW#	IDE IO Write	O-3.3	-	-
D10	IDE_ACK#	IDE DMA Acknowledge	O-3.3	-	-
D11	GND	Ground	PWR	-	-
D12	IDE_IRQ	IDE Interrupt Request	I-3.3	PU 8K2 3.3V	-
D13	IDE_A0	IDE Adress Bus	O-3.3	-	-
D14	IDE_A1	IDE Adress Bus	O-3.3	-	-
D15	IDE_A2	IDE Adress Bus	O-3.3	-	-
D16	IDE_CS1#	IDE Chip Select for 1F0h to 1FFh range	O-3.3	-	-
D17	IDE_CS3#	IDE Chip Select for 3F0h to 3FFh range	O-3.3	-	-
D18	IDE_RESET#	IDE Reset Output to Device	O-3.3	-	-
D19	PCI_GNT3#	PCI Bus Grant 3	O-3.3	-	int. PU 20k in ICH7
D20	PCI_REQ3#	PCI Bus Request 3	I-3.3	PU 8K2 3.3V	-
D21	GND	Ground	PWR	-	-
D22	PCI_AD1	PCI Adress & Data Bus line	IO-3.3	-	-
D23	PCI_AD3	PCI Adress & Data Bus line	IO-3.3	-	-
D24	PCI_AD5	PCI Adress & Data Bus line	IO-3.3	-	-
D25	PCI_AD7	PCI Adress & Data Bus line	IO-3.3	-	-
D26	PCI_C/BE0#	PCI Bus Command and Byte enables 0	IO-3.3	-	-
D27	PCI_AD9	PCI Adress & Data Bus line	IO-3.3	-	-
D28	PCI_AD11	PCI Adress & Data Bus line	IO-3.3	-	-
D29	PCI_AD13	PCI Adress & Data Bus line	IO-3.3	-	-
D30	PCI_AD15	PCI Adress & Data Bus line	IO-3.3	-	-
D31	GND	Ground	PWR	-	-
D32	PCI_PAR	PCI Bus Parity	IO-3.3	-	-
D33	PCI_SERR#	PCI Bus System Error	IO-3.3	PU 8K2 3.3V	-
D34	PCI_STOP#	PCI Bus Stop	IO-3.3	PU 8K2 3.3V	-
D35	PCI_TRDY#	PCI Bus Target Ready	IO-3.3	PU 8K2 3.3V	-
D36	PCI_FRAME#	PCI Bus Cycle Frame	IO-3.3	PU 8K2 3.3V	-
D37	PCI_AD16	PCI Adress & Data Bus line	IO-3.3	-	-
D38	PCI_AD18	PCI Adress & Data Bus line	IO-3.3	-	-
D39	PCI_AD20	PCI Adress & Data Bus line	IO-3.3	-	-
D40	PCI_AD22	PCI Adress & Data Bus line	IO-3.3	-	-
D41	GND	Ground	PWR	-	-
D42	PCI_AD24	PCI Adress & Data Bus line	IO-3.3	-	-
D43	PCI_AD26	PCI Adress & Data Bus line	IO-3.3	-	-
D44	PCI_AD28	PCI Adress & Data Bus line	IO-3.3	-	-
D45	PCI_AD30	PCI Adress & Data Bus line	IO-3.3	-	-
D46	PCI_IRQC#	PCI Bus Interrupt Request C	I-3.3	PU 8K2 3.3V	-
D47	PCI_IRQD#	PCI Bus Interrupt Request D	I-3.3	PU 8K2 3.3V	-
D48	PCI_CLKRUN#	PCI Clock Run	I-3.3	PU 8K2 3.3V	-
D49	PCI_M66EN#	Control PCI Speed 33/66 Mhz	I-3.3	-	Fixed to 33 Mhz
D50	PCI_CLK	PCI Clock	O-3.3	-	-
D51	GND	Ground	PWR	-	-
D52	PEG_TX0+	PCIe 0 Transmit + / SDVO B [RED] +	O - DP	-	only SDVO supported
D53	PEG_TX0-	PCIe 0 Transmit - / SDVO B [RED] -	O - DP	-	only SDVO supported
D54	PEG_LANE_RV#	PCIe Lane Reversal	I-3.3	-	-
D55	PEG_TX1+	PCIe 1 Transmit + / SDVO B [GRN] +	O - DP	-	only SDVO supported

# Signal Descriptions (cont’d) # Row D

Pin	Signal	Description	Type	PU/PD	Comment
D56	PEG_TX1-	PCIe 1 Transmit - / SDVO B [GRN] -	O - DP	-	only SDVO supported
D57	TYPE2#	Module type ID pin 2	STO	-	not connected
D58	PEG_TX2+	PCIe 2 Transmit + / SDVO B [BLU] +	O - DP	-	only SDVO supported
D59	PEG_TX2-	PCIe 2 Transmit - / SDVO B [BLU] -	O - DP	-	only SDVO supported
D60	GND	Ground	PWR	-	-
D61	PEG_TX3+	PCIe 3 Transmit + / SDVO B Clock +	O - DP	-	only SDVO supported
D62	PEG_TX3-	PCIe 3 Transmit - / SDVO B Clock -	O - DP	-	only SDVO supported
D63	RSVD		NC	-	#VALUE!
D64	RSVD		NC	-	-
D65	PEG_TX4+	PCIe 4 Transmit + / SDVO C [RED] +	O - DP	-	not supported
D66	PEG_TX4-	PCIe 4 Transmit - / SDVO C [RED] -	O - DP	-	not supported
D67	GND	Ground	PWR	-	-
D68	PEG_TX5+	PCIe 5 Transmit + / SDVO C [GRN] +	O - DP	-	not supported
D69	PEG_TX5-	PCIe 5 Transmit - / SDVO C [GRN] -	O - DP	-	not supported
D70	GND	Ground	PWR	-	-
D71	PEG_TX6+	PCIe 6 Transmit + / SDVO C [BLU] +	O - DP	-	not supported
D72	PEG_TX6-	PCIe 6 Transmit - / SDVO C [BLU] -	O - DP	-	not supported
D73	SDVO_CLK	SDVO_CTRLCLK	IO-2,5	-	-
D74	PEG_TX7+	PCIe 7 Transmit + / SDVO C Clock +	O - DP	-	not supported
D75	PEG_TX7-	PCIe 7 Transmit - / SDVO C Clock -	O - DP	-	not supported
D76	GND	Ground	PWR	-	-
D77	IDE_CBLID#	IDE Cable Indicator Signal	I-3.3	PD 10k	-
D78	PEG_TX8+	PCIe 8 Transmit +	O - DP	-	not supported
D79	PEG_TX8-	PCIe 8 Transmit -	O - DP	-	not supported
D80	GND	Ground	PWR	-	-
D81	PEG_TX9+	PCIe 9 Transmit +	O - DP	-	not supported
D82	PEG_TX9-	PCIe 9 Transmit -	O - DP	-	not supported
D83	RSVD		NC	-	-
D84	GND	Ground	PWR	-	-
D85	PEG_TX10+	PCIe 10 Transmit +	O - DP	-	not supported
D86	PEG_TX10-	PCIe 10 Transmit -	O - DP	-	not supported
D87	GND	Ground	PWR	-	-
D88	PEG_TX11+	PCIe 11 Transmit +	O - DP	-	not supported
D89	PEG_TX11-	PCIe 11 Transmit -	O - DP	-	not supported
D90	GND	Ground	PWR	-	-
D91	PEG_TX12+	PCIe 12 Transmit +	O - DP	-	not supported
D92	PEG_TX12-	PCIe 12 Transmit -	O - DP	-	not supported
D93	GND	Ground	PWR	-	-
D94	PEG_TX13+	PCIe 13 Transmit +	O - DP	-	not supported
D95	PEG_TX13-	PCIe 13 Transmit -	O - DP	-	not supported
D96	GND	Ground	PWR	-	-
D97	PEG_ENABLE#	PCIe Enable	I-3.3		NC
D98	PEG_TX14+	PCIe 14 Transmit +	O - DP	-	not supported
D99	PEG_TX14-	PCIe 14 Transmit -	O - DP	-	not supported
D100	GND	Ground	PWR	-	-
D101	PEG_TX15+	PCIe 15 Transmit +	O - DP	-	not supported
D102	PEG_TX15-	PCIe 15 Transmit -	O - DP	-	not supported
D103	GND	Ground	PWR	-	-
D104	VCC_12V	Power 12V	PWR	-	-
D105	VCC_12V	Power 12V	PWR	-	-
D106	VCC_12V	Power 12V	PWR	-	-
D107	VCC_12V	Power 12V	PWR	-	-
D108	VCC_12V	Power 12V	PWR	-	-
D109	VCC_12V	Power 12V	PWR	-	-
D110	GND	Ground	PWR	-	-

Signal Descriptions (cont’d)

Signal Type Legend
IO-2,5	Bi-directional 2,5 V Input/Output
IO-3,3	Bi-directional 3,3 V Input/Output
IO-5	Bi-directional 5 V Input/Output
I-3,3	3,3 V Input
I-5	5 V Input
O-2,5	2,5 V Output
O-3,3	3,3 V Output
O-5	5 V Output
IO	Input/Output
OA	Analog Output
OD	Open Drain
IO-DP	Differential Pair Input/Output
O -DP	Differential Pair Output
I -DP	Differential Pair Input
PWR	Power or Ground
STO	Strapping Output
PU	Pull Up Resistor
PD	Pull Down Resistor
NC	Not Connected / Reserved

# 6 Embedded Functions All embedded board functions on ADLINK’s Computer on Modules are supported at the operating system level using the ADLINK Intelligent Device Interface (AIDI) library. The AIDI API programming interface is compatible and identical across all ADLINK Computer on Modules and all supported operating systems. The AIDI library includes a demo program to demonstrate the library’s functionallity. # 6.1 Watchdog Timer The Express-AT implements a Watchdog timer that can be used to automatically detect software execution problems or system hangs and reset the board if necessary. The Watchdog timer consists of a counter that counts down from an initial value to zero. When the system is operating normally, the software that sets the intial value periodically resets the counter so that the it never reaches zero. If the counter reaches zero before the software resets it, the system is presumed to be malfunctioning and a reset signal is asserted. ![Cartoon illustration of a bulldog wearing a red collar (no text or symbols)](.express-at-50-1j021-1000-200/f55747db57a00c70d7d46cd92a155d0e6808e88c20b7eeec19f0e9aa46cc60ed.jpg) The AIDI Library Watchdog functions support Watchdog control of the board. If the Watchdog begins countdown and reaches zero, it will access the CPU's RESET signal to reset the system. This application must call another function named AidiWDogTrigger that triggers the Watchdog to restart to prevent system reset. AIDI Demo Program - Watchdog Tab The AIDI Demo Program allows retrieval of the current Watchdog status and updating of the Watchdog settings If the Watchdog is enabled, the user can click the WDT Trigger button to manually reset the counter and prevent the system from resetting ![AIDI DEMO Program\nBoard Info StorageArea I2C-Buses HW-Monitor GPIO WatchDog\nWatchDog Info\nNumber: 1 MinTimeout: 0 ms MaxTimeout: 255000 ms\nMinDelay: 0 ms MaxDelay: 255000 ms\nWatchDog Operation\nStart WatchDog\nTimeout(dec): ms\nDelay(dec): ms\nEnable Disable\nGet WatchDog Config\nTimeout(dec): ms\nDelay(dec): ms\nGetConfig\nWDT Trigger\nNote: the sum of timeout value and delay value can't exceed MaxTimeout or MaxDelay](.express-at-50-1j021-1000-200/35db82ae4b04b8b2c0af1caef343eec2cf47b2703bb604f4d242db890f00aa64.jpg) # 6.2 GPIO GPIO library support is limited to GPIO signals that originate from the Computer on Module and extended to the carrier board. COM Express modules support 4 GPO and 4 GPI signals. Some of ADLINK’s COM Express boards can configure all 8 ports for GPI or GPO use. GPIO signals can be monitored and controlled by using the ADLINK Intelligent Device Interface (AIDI) library that is compatible and identical across all ADLINK COM Express modules and all supported operating systems. The COM Express type II standard assigns the following pins for either GPI or GPO

Pin	Signal Type #	AIDI ID (bit)	Remark
A54	GPI0	0	Express-AT can configure this pin for GPI and GPO
A63	GPI1	1	Express-AT can configure this pin for GPI and GPO
A67	GPI2	2	Express-AT can configure this pin for GPI andGPO
A85	GPI3	3	Express-AT can configure this pin for GPI andGPO
A93	GPO0	4	Express-AT can configure this pin for GPI and GPO
B54	GPO1	5	Express-AT can configure this pin for GPI and GPO
B57	GPO2	6	Express-AT can configure this pin for GPI and GPO
B63	GPO3	7	Express-AT can configure this pin for GPI and GPO

AIDI Demo Program - GPIO Tab The AIDI Demo Program displays current GPI or GPO status and allows reading of GPI and writing to GPO. The table above links logical port numbers in AIDI to physical port numbers on the COM Express board-to-board connector. For boards that support multidirection the “SetDirection” button can configure the port for either GPI or GPO ![AIDI DEMO Program\nBoard Info | StorageArea | I2C-Buses | HW-Monitor | GPIO | WatchDog |\nGPIO Info\nNumber: 0\nCapabilities(hex): Direction for now: 0x0000003C GetDirection\nin: 0x0000003C Input New Direction(hex): SetDirection\nout: 0x00220000\nIORead\nValue(hex): 1 GetValues\nIOWrite\nnew Value(hex): Write\nIOXorAndXor\nXor1(hex): And(hex): Xor2(hex): Write](.express-at-50-1j021-1000-200/c09f872e209ecb21b4a0bcad462ea9e497031e247eebd8b2058920197e3f4412.jpg) # 6.3 Hardware Monitoring To ensure system health of your embedded system ADLINK’s COM Express modules come with built in support for monitoring and control of CPU and system temperatures, fan speed and critical module voltage levels. The AIDI Library provides simple APIs at the application level to support these functions and adds alarm functions when voltage or temperature levels exceeds the upper or lower limit set by the user. On the Express-AT the following monitored values can be read from the module: CPU temperature, system temperature, Vcore, 1.8V, 5V, 3.3V and 12V. # AIDI Demo Program \- HW Monitor Tab Field 1 displays detected sensors (number). Field 2 allows setting of upper and lower alarm limits. Field 3 displays read out information of sensors. ![AIDI DEMO Program\nBoard Info | StorageArea | I2C-Buses | HW-Monitor | GPIO | WatchDog |\nSensor Info\n1\nTemperature Fan Voltage Number:\nType:\nSensor Limit\n2\nUpper Alarm Threshold: Lower Alarm Threshold:\nUpper Alarm Hysteresis Lower Alarm Hysteresis: GetLimit\nMaximum Value: Minimum Value: Unit: SetLimit\nNote: Input decimal data, threshold value must higher than hysteresis value\nStatus\n3\nValue: Unit:\nStatus: Get Data](.express-at-50-1j021-1000-200/7b9d1e5956f6b6676004cfbb1ff678092648bd777531a5090eb324731291ff44.jpg) # 7 System Resources # 7.1 System Memory Map

Address Range (decimal)	Address Range (hex)	Size	Description
(4GB-2MB)	FFE00000-FFFFFFFF	2 MB	High BIOS Area
(4GB-18MB)-(4GB-17MB-1)	FEE00000-FEEFFFFFF	1 MB	FSB Interrupt Memory Space
(4GB-19MB)-(4GB-18MB-1)	FED00000-FEDFFFFFF	1 MB	Chipset configuration Space
(4GB-20MB)-(4GB-19MB-1)	FEC00000-FECFFFFFF	1 MB	APIC Configuration Space
15MB - 16MB	F00000-FFFFFFFF	1 MB	ISA Hole
960 K - 1024 K	F0000-FFFFF	64 KB	System BIOS Area
896 K - 960 K	E0000-EFFFF	64 KB	Extended System BIOS Area
768 K - 896 K	C0000-DFFFF	128 KB	PCI expansion ROM areaC0000-CEFFF: Onboard VGA BIOSCF000-D0FFF: PXE option ROM when onboard LAN boot ROM is enabled
640 K - 768 K	A0000-BFFFF	128 KB	Video Buffer & SMM space
0 K - 640 K	00000-9FFFF	640 KB	DOS Area

# 7.2 Direct Memory Access Channels

Channel Number	Data Width	System Resource	Comment
0	8-bits	Parallel port	Note (1)
1	8-bits	Parallel port	Note (1)
2	8-bits	Diskette drive	Note (1)
3	8-bits	Parallel port	Note (1)
4		Reserved - cascade channel
5	16-bits	Open
6	16-bits	Open
7	16-bits	Open

![The image features a white document icon with a folded top-right corner. A large red checkmark is centered on the paper. Below the document, the text 'NOTE:' is written in black, uppercase letters.](.express-at-50-1j021-1000-200/f0786345530cac1dc691a3a501d5a7de023e18b90df82bf88e3d7037a0ae945b.jpg) (1) DMA channel 0/1/3 is selected when using parallel port. DMA2 is used by Floppy. 7.3 Legacy I/O Map

Address (hex)	Size	Description	Comment
0000 – 001F	32 bytes	DMA controller
0020 – 0021	2 bytes	Interrupt controller
0024 – 0025	2 bytes	Interrupt controller
0028 – 0029	2 bytes	Interrupt controller
002C – 002D	2 bytes	Interrupt controller
002E – 002F	2 bytes	LPC SIO
0030 – 0031	2 bytes	Interrupt controller
0034 – 0035	2 bytes	Interrupt controller
0038 – 0039	2 bytes	Interrupt controller
003C – 003D	2 bytes	Interrupt controller
0040 – 0043	4 bytes	Counter/Timer
0044 – 0047	4 bytes	System reserved
0048 – 004B	4 bytes	Counter/Timer
004E – 004F	2 bytes	TPM configuration port
0050 – 0053	4 bytes	Counter/Timer
0054 – 005F	12 bytes	System reserved
0060	1 byte	Keyboard controller
0061	1 byte	NMI, speaker control
0063	1 byte	NMI controller
0064	1 byte	Keyboard controller
0065	1 byte	NMI controller
0067	1 byte	NMI controller
0070 – 0071	2 bytes	Real time clock controller
0072 – 0073	2 bytes	Real time clock controller
0074 – 0075	2 bytes	Real time clock controller
0076 – 0077	2 bytes	Real time clock controller
0080 – 0091	18 bytes	DMA controller
0092	1 bytes	Reset Generator
0093 – 009F	13 bytes	DMA controller
00A0 – 00A1	2 bytes	Interrupt controller
00A4 – 00A5	2 bytes	Interrupt controller
00A8 – 00A9	2 bytes	Interrupt controller
00AC – 00AD	2 bytes	Interrupt controller
00B0 – 00B1	2 bytes	Interrupt controller
00B2 – 00B3	2 bytes	Power Management
00B4 – 00B5	2 bytes	Interrupt controller
00B8 – 00B9	2 bytes	Interrupt controller
00BC – 00BD	2 bytes	Interrupt controller
00C0 – 00DF	32 bytes	DMA controller
00E0 – 00EF	16 bytes	System reserved
00F0 – 00FF	16 bytes	Numeric processor
0170 – 0177	8 bytes	Secondary IDE controller
01F0 – 01F7	8 bytes	Primary IDE controller
0274 – 0277	4 bytes	ISA PnP read port
0278 – 027F	8 bytes	LPT2
0290 – 029F	16 bytes	Onboard Sensor index(0x295)/data port (0x296)
02E8 – 02EF	8 bytes	COM4/Video
02F8 – 02FF	8 bytes	COM2
0376 – 0377	2 bytes	Secondary IDE controller
0378 – 037F	8 bytes	LPT1
03B0 – 03BB	12 bytes	Video (monochrome)
03BC – 03BF	4 bytes	LPT3
03C0 – 03DF	32 bytes	Video (VGA†)
03E8 – 03EF	8 bytes	COM3
03F0 – 03F5, 03F7	7 bytes	Diskette controller
03F6 – 03F7	2 bytes	Primary IDE controller
03F8 – 03FF	8 bytes	COM1
0400 – 041F	32 bytes	Onboard SMBus control registers
0480 – 04BF	64 bytes	GPIO control registers
04D0 – 04D1	2 bytes	Edge/level triggered PIC
0800 – 087F	128 bytes	ACPI control registers.
0A79 – 0A79	1 bytes	ISA PnP read data Port
0CF8 – 0CFF*	8 bytes	PCI configuration registers	Note (*)
0CF9**	1 byte	Reset control register	Note (**)
04700 – 0470F	16 bytes	TPM control registers

![The image features a white document icon with a folded top-right corner and faint horizontal lines. A large red checkmark is centered on the document. Below the icon, the text 'NOTE:' is written in black, bold, sans-serif capital letters.](.express-at-50-1j021-1000-200/4399d85135b3f58a61fe09223a896f9ae00ec5f7b0aebee26fb6b91dd84d39df.jpg) (\*) DWORD access only (\*\*) Byte access only # 7.4 Interrupt Request (IRQ) Lines PIC Mode

IRQ#	Typical Interrupt Resource	Connected	Available
0	Counter 0	N/A	No
1	Keyboard controller	N/A	No
2	Cascade interrupt from slave PIC	N/A	No
3	Serial Port 2 (COM2) / PCI	IRQ3 via SERIRQ	Note (1)
4	Serial Port 1 (COM1) / PCI	IRQ4 via SERIRQ	Note (1)
5	Parallel Port 2 (LPT2) / PCI	IRQ5 via SERIRQ	Note (1)
6	Floppy Drive Controller	IRQ6 via SERIRQ	No
7	Parallel Port 1 (LPT1) / PCI	IRQ7 via SERIRQ,	Note (1)
8	Real-time clock	N/A	No
9	SCI / PCI	IRQ9 via SERIRQ	Note (1)
10	PCI	IRQ10 via SERIRQ	Note (1)
11	PCI	IRQ11 via SERIRQ	Note (1)
12	PS/2 Mouse / PCI	IRQ12 via SERIRQ	Note (1)
13	Math Processor	N/A	No
14	Primary IDE controller / PCI	IRQ14 via SERIRQ	Note (1)
15	Secondary IDE controller / PCI	IRQ15 via SERIRQ	Note (1)

![The image features a white document icon with a folded top-right corner containing a large red checkmark. Below the icon is the text 'NOTE:' in bold, black, uppercase letters.](.express-at-50-1j021-1000-200/5b07aa99e39fa13046e869743bf95254490a1c36f5de0008762c9457fd4cfab2.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. APIC Mode

IRQ#	Typical Interrupt Resource	Connected	Available
0	Counter 0	N/A	No
1	Keyboard controller	N/A	No
2	Cascade interrupt from slave PIC	N/A	No
3	Serial Port 2 (COM2) / PC	IRQ3 via SERIRQ	Note (1)
4	Serial Port 1 (COM1) / PCI	IRQ4 via SERIRQ	Note (1)
5	Parallel Port 2 (LPT2) / PCI	IRQ5 via SERIRQ	Note (1)
6	Floppy Drive Controller	IRQ6 via SERIRQ	No
7	Parallel Port 1 (LPT1) / PCI	IRQ7 via SERIRQ	Note (1)
8	Real-time clock	N/A	No
9	SCI / PCI	IRQ9 via SERIRQ	Note (1)
10	PCI	IRQ10 via SERIRQ	Note (1)
11	PCI	IRQ11 via SERIRQ	Note (1)
12	PS/2 Mouse / PCI	IRQ12 via SERIRQ	Note (1)
13	Math Processor	N/A	No
14	Primary IDE controller / PCI	IRQ14 via SERIRQ	Note (1)
15	Secondary IDE controller / PCI	IRQ15 via SERIRQ	Note (1)
16	N/A	PCI Slot INT A, USB, VGA controller, High Definition Audio controller	Yes
17	N/A	PCI Slot INT B	Yes
18	N/A	PCI Slot INT C, USB	Yes
19	N/A	PCI Slot INT D, USB controller, PCI-E Gigabit Ethernet NIC	Yes
20	N/A		No
21	N/A		No
22	N/A		No
23	N/A	EHCI, USB	No

![The image displays a digital icon featuring a white document with faint horizontal lines and a large red checkmark in the center. Below the document is the text 'NOTE:' in bold, black, uppercase letters.](.express-at-50-1j021-1000-200/6ebacfb3d8ae1a8c14f7127577f0aa12242de3178544c0dfaa2f864a11e8c4a3.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. 7.5 PCI Configuration Space Map

Bus No.	Device No.	Function No.	Routing	Description
00h	00h	00h	N/A	Intel 945 GME GMCH Host-Hub Interface Bridge
00h	02h	00h	Internal	Intel Integrated Graphics Device
00h	02h	01h	Internal	Intel Integrated Graphics Device (Function 1)
00h	1Bh	00h	Internal	High Definition Audio controller
00h	1Ch	00h	Internal	Intel ICH Express Root port
00h	1Dh	00h	Internal	Intel USB UHCI Controller 1
00h	1Dh	01h	Internal	Intel USB UHCI Controller 2
00h	1Dh	07h	Internal	Intel USB EHCI Controller
00h	1Eh	00h	N/A	Intel Hub Interface to PCI Bridge
00h	1Fh	00h	N/A	Intel LPC Interface Bridge
00h	1Fh	01h	Internal	Intel IDE Controller
00h	1Fh	02h	Internal	Intel SATA controller
00h	1Fh	03h	Internal	Intel SMBus Controller
02h	00h	00h	onboard	Onboard LAN controller
03h	04h	00h	PIRQA-PIRQD	External PCI Slot 1
03h	05h	00h	PIRQA-PIRQD	External PCI Slot 2
03h	06h	00h	PIRQA-PIRQD	External PCI Slot 3
03h	07h	00h	PIRQA-PIRQD	External PCI Slot 4

7.6 PCI Interrupt Routing Map

PIRQ

INT

VGA

UHCI 1

UHCI 2

EHCI

SATA

SMbus

Audio

PCI Slot 1

PCI Slot 2

PCI Slot 3

PCI Slot 4

LAN

INTA

INTD

INTC

INTB

INTA

INTD

INTC

INTB

INTA

INTD

INTC

INTB

INTA

7.7 SMBus Slave Device Address

Address (hex)	Device	Function
D2		Clock Generator
A0	DIMMA	DDR2 socket
5C	LM87	Hardware Monitor

# 8 BIOS Setup Utility The following chapter describes basic navigation for the AMIBIOS8 BIOS setup utility. # 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL or Delete to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus. ![The image features a large, red triangle composed of horizontal stripes. Centered within this red structure is a solid black inverted triangle. Below the graphic, white text reads: www.ami.com](.express-at-50-1j021-1000-200/44534239d87c37d72066190fd0fc52084a20542aad78ce7de84ec0d4525094e1.jpg) # American Megatrends AMIBIOS (C)2002 Amer ican Megatrends，Inc. BIOS Date:10/08/0712:39:39 Uer:08.00.04 Intel(R) Celeron(R)M Processor Press DEL torun Setup Check ing NURAM.. USB Device(s):2 Keyboards，2 Hice，1 Hub，1 Storage Device 1024MBOK Auto-Detecting Pri Master..IDE Hard Disk Auto-Detecting Pri Slaue...ATAPI CDROM Pri Master:3.20 ST38410A ![The image displays a white document icon featuring a large red checkmark in the center. Below the icon is the text 'NOTE:' in black capital letters.](.express-at-50-1j021-1000-200/51e09a90a753b99364986ff8c7778e4300dbf5eb9966dd7587018cfab783c721.jpg) In most cases, the < Delete > key is used to invoke the setup screen. There are several cases that use other keys, such as < F1 >, < F2 >, and so on. # 8.1.1 Main Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

BIOS SETUP UTILITY
Main	Advanced	Power	Boot	Security	Exit
System Overview					Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.
AMIBIOS
Version :08.00.15
Build Date:01/16/09
ID :EXPAT000
Processor
Speed :255MHz
Count :255
System Memory					← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit
Size :1016MB
System Time [00:15:44]
System Date [Tue 01/01/2002]

# 8.1.2 Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. ![The flowchart begins at the top with a block labeled 'BIOS Setup Utility'.\n\n* A downward arrow connects 'BIOS Setup Utility' to the text 'Screens'.\n* To the left of the screen row, a block labeled 'Left and Right Keys to Select a Setup Screen' connects via a dotted arrow to a horizontal sequence of boxes: 'Screen 1' \$\leftrightarrow\$ 'Screen 2' \$\leftrightarrow\$ 'Screen 3' \$\leftrightarrow\$ 'Screen 4' \$\leftrightarrow\$ 'Screen 5'.\n* A downward arrow connects the 'Screens' text area to the text 'Items'.\n* Below 'Items' are two rows of boxes containing the symbol '±'.\n * The top row consists of three '±' boxes connected by double-headed arrows.\n * A block labeled 'Tab Key to Select Fields' connects via a dotted arrow to this top row.\n * A block labeled '± To Change Field Values' connects via a dotted arrow to this top row.\n* Downward and upward arrows connect the top row of '±' boxes to the bottom row of '±' boxes.\n * A block labeled 'Up and Down Keys to Select a Setup Item' connects via a dotted arrow to these vertical arrows.\n * The bottom row consists of three '±' boxes connected by double-headed arrows.\n* To the left of the bottom section, the text 'Fields' is connected via a bracket to both the top and bottom rows of '±' boxes.](.express-at-50-1j021-1000-200/5086c7ce3594770743bad047e2cc25be9c2da22b0930980d830c0d45c2ab7448.jpg) ![The image displays a line drawing of a document with horizontal lines, featuring a large red checkmark in the center. Below the document icon, the word 'NOTE:' is printed in bold, black capital letters, followed by a small, partially visible logo or symbol to the right.](.express-at-50-1j021-1000-200/b340d0b03ee5540ca2b6a727a29c08b8290786827cf929f677ae80ca5ac737e3.jpg) There is a hot key legend located in the right frame on most setup screens.

Hot Key	Description
→←	Left/Right The Left and Rightkeys allow you to select a setup screen.For example: Main screen, Advanced screen, Chipset screen, and so on.
↑↓	Up/Down The Up and Downkeys allow you to select a setup item or sub-screen.
+-	Plus/Minus The Plus and Minuskeys allow you to change the field value of a particular setup item.For example: Date and Time.
Tab	Thekey allows you to select setup fields.

![The image displays a graphic of a white document with horizontal lines and a large red checkmark overlaid on it. Below this icon is the text 'NOTE' in black capital letters, followed by a small square box.](.express-at-50-1j021-1000-200/38d75ea63d80d4b766572c821211ab510359c2a07e920badf978e3d65be3e6d1.jpg) The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings. # Hot Key Description F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. General Help

←→	Select Screen	↓↑	Select Item
+-	Change Screen	Enter	Go to Sub Screen
PGDN	Next Page	PGUP	Previous Page
Home	Go to Top of the Screen	End	Go to Bottom of Screen
F2/F3	Change Colors	F7	Discard Changes
F8	Load Failsafe Defaults	F9	Load Optimal Defaults
F10	Save and Exit	ESC	Exit

[ok] F10 The < F10 > key allows you to save any changes you have made and exit Setup. Press the < F10 > key to save your changes. The following screen will appear: Save configuration changes and exit now? [ok] [Cancel] Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the < Esc > key to exit the setup without saving your changes. The following screen will appear: Discard changes and exit setup now? [ok] [Cancel] Press the < Enter > key to discard changes and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. # 8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.

BIOS SETUP UTILITY
Main	Advanced	Power	Boot	Security	Exit
System Overview					Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.
AMIBIOS
Version :08.00.15Build Date:01/16/09ID :EXPAT000
Processor
Speed :255MHzCount :255
System Memory					← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit
Size :1016MB
System Time [00:15:44]System Date [Tue 01/01/2002]

# 8.2.1 System Time/System Date Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values using the keyboard. Press the < Tab > key or the < Arrow > keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. ![The image features a white document icon with horizontal lines and a large red checkmark. Below the document, the text 'NOTE:' is displayed in black capital letters.](.express-at-50-1j021-1000-200/73999f14c90bbd12883252dbb13afbaa121dbbc0732d4f654a7035f60082e737.jpg) The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00. # 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the < Arrow > keys. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages.

BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Advanced Settings	Configure CPU.
►CPU Configuration ►Chipset Configuration ►Video Function Configuration ►IDE Configuration ►Onboard Device Configuration ►USB Configuration ►PCI Express Configuration ►PCIPnP Configuration ►Remote Access Configuration ►Trusted Computing	← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

![The image displays a standard safety warning sign. It features a red triangle with a black exclamation point (!) in the center. Directly below the triangle is the word 'WARNING:' printed in bold, black capital letters.](.express-at-50-1j021-1000-200/fb12dd5fbaf78aef0f51fd1cde7ec000eede825d4a8a3a04e7d6f8de3d8444bf.jpg) Setting incorrect or conflicting values in Advanced BIOS Setup may cause system malfunctions. # 8.3.1 CPU Configuration # CPU Configuration Settings You can use this screen to select options for the CPU Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.

BIOS SETUP UTILITY
Advanced
Configure advanced CPU settings Module Version:3F.0E	Disabled for WindowsXP
Manufacturer:Intel
Frequency :255MHz FSB Speed :532MHz Cache L1 :0 KB Cache L2 :0 KB Ratio Actual Value:12
Max CPUID Value Limit [Disabled]
Execute-Disable Bit Capability [Enabled]	← Select Screen
Hyper Threading Technology [Enabled]	↑↓ Select Item
Intel (R) SpeedStep (tm) tech [Enabled]	+- Change Option
Intel (R) C-STATE tech [Enabled]	F1 General Help
Enhanced C-States [Enabled]	F10 Save and Exit
MPS Revision [1.4]	ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Max CPUID Value Limit When the computer is boots, the operating system executes its CPUID instruction to identify the processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input value the CPUID recognizes. This determines the kind of basic information CPUID can provide the operating system. This option allows you to circumvent problems with older operating systems. When Enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When Disabled, the processor will return the actual maximum CPUID input value of the processor when queried. # Execute Disable Bit Capability This is an Intel hardware-based security feature that can help reduce system exposure to viruses and malicious code. It allows the processor to classify areas in memory where application code can or cannot execute. When a malicious worm attempts to insert code in the buffer, the processor disables its code execution, preventing damage and worm propagation. To use Execute Disable Bit you must have a PC or server with a processor with Execute Disable Bit capability and a supporting operating system. # Hyper Threading Technology This item allows you to Enable/Disable Hyper-Threading Technology. # Intel® SpeedStep tech This option enables or disables Intel SpeedStep technology. # Intel® C-STATE tech This item allows you to Enable/Disable the C-STATE function. C-STATE make the power and thermal control unit part of the core logic and not part of the chipset as before. # Enhanced C-STATE This item allows you to Enable/Disable the Enhanced C-STATE function. # MPS Revision This item allows you to select which MPS revision to use for the operating system. # 8.3.2 Chipset Configuration # Chipset Configuration Settings Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the < Arrow > keys. The Chipset BIOS Setup screen is shown below.

BIOS SETUP UTILITY
Advanced
Advanced Chipset Settings	Options
DRAM Frequency [Auto] Memory Hole [Disabled] APIC ACPI SCI IRQ [Disabled]	Auto 400 MHz 533 MHz
	← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# DRAM Frequency Set DRAM frequency. You can let frequency be set by BIOS automatically or configure it manually. # Configure DRAM Timing by SPD Enable/Disable the timing set of DRAM is configured from SPD or set by manually. # APIC ACPI SCI IRQ This item allows you to enable or disable the APIC ACPI SCI interrupt. # 8.3.3 Video Function Configuration # Video Function Configuration Settings You can use this screen to select options for Video Function configuration settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The video function BIOS Setup screen is shown below.

BIOS SETUP UTILITY Advanced
Video Function Configuration Boots Graphic Adapter Priority [PCI/IGD] Internal Graphics Mode Select [Enabled, 8MB] DUMT Mode Select [DUMT Model] DUMT/FIXED Memory [128MB] Boot Display Device [CRT] Local Flat Panel Scaling [Auto] Flat Panel Type [800x600 18Bit ] TV Standard [VBIOS-Default]	Select which graphics controller to use as the primary boot device. ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Boots Graphic Adapter Priority Select which graphics controller to use as the primary boot display device. IGD=Integrated Graphic device. PCI means external PCI graphics device. # Internal Graphics Mode Select Select amount of system memory which is used by internal graphics device. # DVMT Mode Select Unified Memory Architecture (UMA) is a concept whereby system memory is shared by both CPU and graphics processor. While this reduces cost, it also reduces the system's performance by taking up a large portion of memory for the graphics processor. Intel's Dynamic Video Memory Technology (DVMT) takes that concept further by allowing the system to dynamically allocate memory resources according to the demands of the system at any point in time. The key idea in DVMT is to improve the efficiency of the memory allocated to either system or graphics processor. When set to Fixed Mode, the graphics driver will reserve a fixed portion of the system memory as graphics memory. When set to DVMT Mode, the graphics chip will dynamically allocate system memory as graphics memory, according to system and graphics requirements. When set to Combo Mode, the graphics driver will allocate a fixed amount of memory as dedicated graphics memory, as well as allow more system memory to be dynamically allocated between the graphics processor and the operating system. # DVMT/FIXED Memory Set the amount of memory according to DVMT Mode Select. # Boot Display Device Select which display interface you want to make it active. # Local Flat Panel Scaling Allows you to determine how various resolutions appear on your LCD display. Auto: The scaling unit on your graphics card will rescale the image before it reaches your LCD display. This option results in the best image quality. Forced Scaling: This option will maintain the original aspect ratio of the chosen resolution and display it with black bars to the sides/above/below the on-screen image as required. Disabled: The image isn't scaled at all, but instead your LCD display will run at its maximum resolution and the image will display in the centre of your LCD display. This may result in a black border around the sides of the image. # Flat Panel Type Once LVDS is selected from Boot Display Device, this option opens some resolution settings for correct timing out to LVDS interface you want to use. # TV Standard This field allows you to set the appropriate standard for your TV. VBIOS-Default: Default setting of onboard VGA BIOS. NTSC: National Television System Committee PAL: Phase Alternating Line # 8.3.4 IDE Configuration # IDE Configuration Settings You can use this screen to select options for the IDE Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.

BIOS SETUP UTILITY Advanced
IDE Configuration	Options
ATA/IDE Configuration Legacy IDE Channels [Compatible] [SATA Pri, PATA Sec]	Disabled Compatible Enhanced
► Primary IDE Master : [Not Detected]
► Primary IDE Slave : [Not Detected]
► Secondary IDE Master : [Not Detected]
► Secondary IDE Slave : [Not Detected]
Hard Disk Write Protect [Disabled]
IDE Detect Time Out (Sec) [35]
ATA(PI) 80Pin Cable Detection [Host & Device]	← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.

# ATA/IDE Configuration This item specifies whether the IDE channels should be initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced. # Legacy IDE Channels When running in compatible mode, the SATA channel can be configured as a legacy IDE channel. The location of the IDE channel is selectable. # Primary IDE Master/Slave, Secondary IDE Master/Slave Select one of the hard disk drives to configure it. Press < Enter > to access its sub menu. # Hard Disk Write Protect Set this value to Enabled to prevent the hard disk drive from being overwritten. # IDE Detect Time Out This field allows you to set the time to stop searching for IDE devices within the specified number of seconds. # ATA(PI)80Pin Cable Detection Selects the method used to detect the type of IDE cable used. # 8.3.5 Onboard Device Configuration # Onboard Device Configuration Settings You can use this screen to specify options for the onboard device configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

BIOS SETUP UTILITY
Advanced
Onboard Device Configuration	Options
Audio Controller [Auto] Onboard Lan Boot ROM [Disabled] ► SuperIO Configuration	Auto Azalia AC'97 Audio and Modem All Disabled
	← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Audio Controller Set this value to Enable/Disable the Audio Controller. # Onboard Lan Boot ROM Set this value to enable/disable the onboard LAN’s PXE ROM to enable boot from LAN. Setting to Disabled can shorten the POST time without initializing LAN PXE ROM if boot from LAN is not needed. # SuperIO Configuration Screen SuperIO configuration screen is a sub-menu of Onboard Device Configuration. You can use this screen to select options for the Super IO settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below. The visibility of this SuperIO configuration screen depends on the presence of an onboard SuperIO (Winbond W83627HF). If the Express-AT is used on carrier w/o a SIO chip, the legacy-free mode will take effect.

BIOS SETUP UTILITY
Advanced
Configure Win627 Super IO Chipset
Floppy A [1.44 MB 3½"] OnBoard Floppy Controller [Enabled] Serial Port1 Address [3F8/IRQ4] Serial Port2 Address [Disabled] Parallel Port Address [378] Parallel Port Mode [Normal] Parallel Port IRQ [IRQ7] ► Hardware Health Configuration	Select the type of floppy drive connected to the system.
	← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Floppy A Use this field to specify options for the Floppy Configuration Settings. Options: Disabled, 360 KB 5 ¼”, 1.2 MB 5 ¼”, 720 KB 3 ½”, 1.44 MB 3 ½”, 2.88 MB 3 ½”. # OnBoard Floppy Controller This option enables/disables the Super IO’s floppy controller. # Serial Port1 Address This option specifies the base I/O port address and Interrupt Request address of serial port 1.

Option	Description
Disabled	Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable.
3F8/IRQ4	Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt address.
3E8/IRQ4	Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 4 for the interrupt address.
2F8/IRQ3	Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 3 for the interrupt address.
2E8/IRQ3	Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 3 for the interrupt address.

# Serial Port2 Address This option specifies the base I/O port address and Interrupt Request address of Serial Port2. The settings of Serial Port2 are the same as Serial Port1. However, the setting used by Serial Port1 will not be available for Serial Port2. For example, if Serial Port1 uses 3F8/ IRQ4, the option, the 3F8/IRQ4 will not appear in the options of Serial Port2. # Parallel Port Address This option lets to configure the SuperIO’s parallel port address. # Parallel Port Mode This option specifies the parallel port mode.

Option	Description
Normal	Set this value to allow the standard parallel port mode to be used.
EPP	The parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data transfer driven by the host device.
ECP	The parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per second. ECP provides symmetric Bidirectional communication.
EPP+ECP	Allows the parallel port to support both the ECP and EPP modes simultaneously.

# Parallel Port IRQ This option specifies the IRQ used by the parallel port.

Option	Description
IRQ5	Set this value to allow the serial port to use Interrupt 5.
IRQ7	Set this value to allow the serial port to use Interrupt 7. The majority of parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.

# Hardware Health Configuration The hardware health on SuperIO only supports FAN speed monitoring.

BIOS SETUP UTILITY
Advanced
Hardware Health ConfigurationH/W Health Function [Enabled]Hardware Health Event MonitoringFan1 Speed :0 RPMFan2 Speed :7031 RPMFan3 Speed :2721 RPM	Enables HardwareHealth MonitoringDevice.< Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit

# 8.3.6 USB Configuration # USB Configuration Settings You can use this screen to specify options for the USB configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

BIOS SETUP UTILITY Advanced
USB Configuration	Options
Module Version - 2.24.3-13.4	Disabled 2 USB Ports 4 USB Ports 6 USB Ports 8 USB Ports
USB Devices Enabled :
1 Drive
USB Functions [8 USB Ports]
USB 2.0 Controller [Enabled]
USB 2.0 Controller Mode [HiSpeed]
Legacy USB Support [Enabled]
USB Keyboard Legacy Support [Enabled]
USB Mouse Legacy Support [Enabled]	← Select Screen ↑↓ Select Item +- Change Option
USB Storage Device Support [Enabled]
USB Beep Message [Enabled]	F1 General Help
BIOS EHCI Hand-Off [Enabled]	F10 Save and Exit
► USB Mass Storage Device Configuration	ESC Exit

# USB Function Set this value to allow the system to Disable, Enable, and select a set number of onboard USB ports. # USB 2.0 Controller Depends on the setting of USB Function. If USB Function is set to Disabled, this option will have no effect. Enabled will open USB 2.0 functionality to all USB ports. # USB 2.0 Controller Mode The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps). # Legacy USB Support Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is not enabled, any attached USB mouse or keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or keyboard can control the system even when there are no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB Support (see below).

Option	Description
Disabled	Set this value to prevent the use of any USB device in DOS or during system boot.
Enabled	Set this value to allow the use of USB devices during boot and while using DOS.
Auto	This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS.

# USB Beep Message Allows you to Enable/Disable the beep during USB device enumeration. # BIOS EHCI hand-off This option provides a work around for OSes without ECHI hand-off support. The EHCI ownership change should be claimed by the EHCI driver. # USB Mass Storage Device Configuration This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on the USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). ). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.

BIOS SETUP UTILITY
Advanced
USB Mass Storage Device Configuration USB Mass Storage Reset Delay [20 Sec] Device #1 USB Flash Disk Emulation Type [Auto]	Number of seconds POST waits for the USB mass storage device after start unit command. ← Select Screen ↑↓ Select Item +- Change Option

# 8.3.7 PCI Express Configuration You can use this screen to specify options for the PCI Express Configuration Settings.

PCI Express Configuration			Enable/Disable PCI Express L0s and L1 link power states.
Active State Power-Management [Disabled]
PCIE Ports 0-3 Configuration [Four x1 Ports]
PCIE Port 0 [Auto]
PCIE Port 1 [Auto]
PCIE Port 2 [Auto]
PCIE Port 3 [Auto]
PCIE Port 4 [Auto]
PCIE Port 5 [Auto]
PCIE High Priority Port [Disabled]
PCIE Port 0 IOxAPIC Enable [Disabled]			← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
PCIE Port 1 IOxAPIC Enable [Disabled]
PCIE Port 2 IOxAPIC Enable [Disabled]
PCIE Port 3 IOxAPIC Enable [Disabled]
PCIE Port 4 IOxAPIC Enable [Disabled]
PCIE Port 5 IOxAPIC Enable [Disabled]
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Active State Power-Management This option allows you to enable/disable the Active State Power Management (ASPM) function. ASPM is a PCIe power management specification. # PCIE Ports 0-3 Configuration Allows you to configure the PCIE0\~PCIE3 of the south bridge as one x4 slot or four x1 slots. # PCIE Port (0-5) IOxAPIC Enable This function is used to control the availability of the PCIE Port 0\~5 IOxAPIC. # PCIE High Priority Port This function is used to select a PCIE port as high priority port. Transactions on this port have higher priority than other ports. # 8.3.8 PCIPnP Configuration You can use this screen to specify options for Plug and Play BIOS Configuration. ![BIOS SETUP UTILITY\nAdvanced\nAdvanced PCI/PnP Settings\nWARNING: Setting wrong values in below sections\nmay cause system to malfunction.\nClear NURAM (No)\nPlug & Play O/S (No)\nPCI Latency Timer (64)\nAllocate IRQ to PCI VGA (Yes)\nIRQ3 (Reserved)\nIRQ4 (Reserved)\nIRQ5 (Available)\nIRQ7 (Reserved)\nIRQ9 (Available)\nIRQ10 (Available)\nIRQ11 (Available)\nIRQ14 (Available)\nIRQ15 (Available)\nClear NURAM during\nSystem Boot.\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.express-at-50-1j021-1000-200/f5d56e462f1e5843a348511092bf605af04740610cb3aeeb3a46753f05f171c7.jpg) # Clear NVRAM This option clears ESCD (Extended System Configuration Data) information in NVRAM. # Plug & Play O/S When set to "Yes" and a Plug and Play operating system is installed, the operating system configures the Plug and Play devices not required for boot. # PCI Latency Timer Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of all PCI devices on the PCI bus. # Allocate IRQ to PCI VGA When set to "Yes", the BIOS will assign an IRQ for a PCI VGA card. # IRQ Set this value to allow the IRQ settings to be modified. Available - This setting allows the specified IRQ to be used by a PCI/PnP device. Reserved - This setting allows the specified IRQ to be used by a legacy ISA device. # 8.3.9 Remote Access Configuration # Remote Access Configuration Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access. This screen will not be visible if the module is used on a carrier w/o a SuperIO chip, due to lack of serial port support.

BIOS SETUP UTILITY Advanced
Configure Remote Access type and parameters
Remote Access	[Enabled]
Serial port number	[COM1]
Base Address, IRQ	[3F8h, 4]
Serial Port Mode	[115200 8,n,1]
Flow Control	[None]
Redirection After BIOS POST	[Always]
Terminal Type	[ANSI]
VT-UTF8 Combo Key Support	[Enabled]
Sredir Memory Display Delay	[No Delay]

# Remote Access Select this option to Enable or Disable the BIOS remote access feature here. ![The image displays a white document icon with a large red checkmark overlaid on it. Below the icon is the text 'NOTE:' in black capital letters.](.express-at-50-1j021-1000-200/664dfe7076633ec4c2ea560e30a9b5fc79377060ef69a6a6b8aac051f68633fd.jpg) Enabled Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot. # Serial Port Number Select the serial port you want to use for the remote access interface. You can set the value for this option to either COM1 or COM2. ![The image displays a white document icon with a folded top-right corner and a large red checkmark in the center. Below the document graphic, the text 'NOTE:' appears in black capital letters.](.express-at-50-1j021-1000-200/13eb207478f1bc15ce4c39b2fc2d8e77a945bc93bdbcd176f1330572f2cc21f7.jpg) If you have changed the resource assignment of the serial ports in Advanced>Onboard Device Configuration>SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the available Remote Access options. # Serial Port Mode Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1. # Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software. # Redirection After BIOS POST This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.

Option	Description
Disabled	Set this value to turn off the redirection after POST
Boot Loader	Set this value to allow the redirection to be active during POST and Boot Loader.
Always	Set this value to allow the redirection to be always active.

# Terminal Type This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8. # VT-UTF8 Combo Key Support This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled. # Sredir Memory Display Delay This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec. # 8.3.10 Trusted Computing Trusted computing is an industry standard to make personal computers more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support.

BIOS SETUP UTILITY
Advanced
Trusted ComputingTCG/TPM SUPPORT [Yes]Execute TPM Command [Don't change]Clearing the TPM [Press Enter]TPM Enable/Disable Status [Disabled]TPM Owner Status [UnOwned]	Enable/Disable TPMTCG (TPM 1.1/1.2) supp in BIOS← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.

# Execute TPM Command This field is used to Enable(activate)/Disable(deactivate) the Execute TPM Command function. # 8.4 Power Management Select the Power tab from the setup screen to enter the power management BIOS Setup screen. You can select any of the items in the left frame of the screen, such as ACPI Configuration, to go to the sub menu for that item. The power management BIOS Setup screen is shown below.

BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Power Management Settings	Section for Advanced ACPI Configuration.
ACPI Configuration APM Configuration Hardware Health Configuration	Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# 8.4.1 ACPI Configuration # Advanced ACPI Configuration You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on this page. The screen is shown below.

BIOS SETUP UTILITY
Power
ACPI Settings
ACPI Version Features	[ACPI v2.0]
ACPI APIC support	[Enabled]
AMI OEMB table	[Enabled]
Suspend mode	[S1 (POS)]
USB Device Wakeup From S3/S4	[Disabled]
Headless mode	[Disabled]

# ACPI Version Features The item allows you to select the ACPI version. # ACPI APIC Support Used to enable or disable the Advanced Programmable Interrupt Controller (APIC) for PC2001 compliance. Enabling APIC mode will expand available IRQs resources for the system # AMI OEMB Table Include OEMB table pointer to R(X)SDT pointer lists. # Suspend mode This setting selects either S1 (POS) or S3 (STR) system suspend mode. The Optimal and Fail-Safe Default setting is S3 (STR).

Option	Description
S1 (POS)	Power On Suspend - Under this setting the CPU is not executing instructions, all power resources that supply system level reference of S0 are off, system memory context is maintained, devices that reference power resources that are on are on, and devices that can wake-up the system can cause the cpu to continue to execute from where it left off.
S3 (STR)	Suspend to RAM - Under this setting the system enters a low power state instead of being completely shut off. This allows the computer system to boot up in a few seconds.

# USB Device Wakeup from S3/S4 This option allows a USB device to wake up the system from S3/S4. # Headless mode This is a server-specific feature. A headless server is one that operates without a keyboard, monitor or mouse. To run in headless mode, both BIOS and operating system (e.g. Windows Server 2003) must support headless operation # 8.4.2 APM Configuration Select the Advanced tab from the setup screen to enter the APM Configuration Setup screen. You can display a Power Management/APM Setup option by highlighting it using the < Arrow > keys.

BIOS SETUP UTILITY
Power
APM Configuration		Enable or disable APM.
Power Management/APM	[Enabled]
Video Power Down Mode	[Disabled]
Hard Disk Power Down Mode	[Disabled]
Suspend Time Out	[Disabled]
Throttle Slow Clock Ratio	[50%]
Advanced Resume Event Controls
Resume On LAN	[Disabled]
Resume On PME#	[Disabled]
Resume On RTC Alarm	[Disabled]
Restore on AC Power Loss	[Last State]
		← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Power Management/APM Set this value to Enable or Disable Power Management/APM (Advanced Power Management) features. # Video Power Down Mode This option specifies the Power State that the video subsystem enters when the BIOS places it in a power saving state after the specified period of display inactivity has expired. The options are Disabled and Suspend. # Hard Disk Drive Power Down Mode This option specifies the power conserving state that the hard disk drive enters after the specified period of hard drive inactivity has expired. # Suspend Time Out This option specifies the length of time the system waits before it enters suspend mode. The options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min, and 60 Min. # Throttle Slow Clock Ratio When the system enters suspend or standby mode, the CPU clock runs only part of the time. You may select the percent of time that the clock runs. You may select the percentage of time that the clock runs. When CPU temperature exceeds the setting of CPU Throttling Temperature, the CPU clock will also be throttled according to this setting. # Advanced Resume Event Controls These settings specify which events will generate a system wake event. The available events are On LAN, PME# and RTC Alarm. The options are Enabled and Disabled. # Restore on AC Power Loss Determines what state the computer enters when AC power is restored after a power loss. The options for this value are Last State, Power On and Power Off.

Option	Description
Power Off	Set this value to always power off the system while AC power is restored.
Power On	Set this value to always power on the system while AC power is restored.
Last State	Set this value to power off/on the system depending on the last system power state while AC power is restored.

# 8.4.3 Hardware Health Configuration

BIOS SETUP UTILITY
Power
H/W Health Function	[Enabled]	Enables HardwareHealth MonitoringDevice.
Current CPU Temperature	:38°C/100°F
CPU VCORE	:1.122 V
3.3V	:3.192 V
1.8V	:1.852 V
5V	:5.086 V
12V	:12.027 V
		← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# 8.5 Boot Setup Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display an Boot BIOS Setup option by highlighting it using the < Arrow > keys. The Boot Settings screen is shown below:

BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Boot Settings	Configure Settings during System Boot.
► Boot Settings Configuration
1st Boot Device [1st FLOPPY DRIVE]
2nd Boot Device [CD/DVD]
3rd Boot Device [Hard Drive]
4th Boot Device [USB:Kingston DataT]
5th Boot Device [Network]
► Hard Disk Drives
► Removable Drives
► CD/DVD Drives
► USB Drives
► Network Drives	← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.

# Boot Settings Configuration Use this screen to select options for the Boot Settings Configuration. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

BIOS SETUP UTILITYBoot
Boot Settings Configuration
Quick Boot[Enabled]Quiet Boot[Disabled]AddOn ROM Display Mode[Force BIOS]Bootup Num-Lock[On]PS/2 Mouse Support[Auto]Wait For 'F1' If Error[Enabled]Hit 'DEL' Message Display[Enabled]Interrupt 19 Capture[Disabled]	Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.< Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit

# Quick Boot Disabled - Set this value to allow the BIOS to perform all POST tests. Enabled - Set this value to allow the BIOS to skip certain POST tests to boot faster. # Quiet Boot Disabled - Set this value to allow the computer system to display the POST messages. Enabled - Set this value to allow the computer system to display the OEM logo. # AddOn ROM Display Mode This BIOS feature controls the display of ROM messages from the BIOS of add-on devices like the graphics card or the SATA controller during the boot sequence. When set to Force BIOS, AddOn ROM messages will be forced to display during the boot sequence. When set to Keep Current, AddOn ROM messages will only be displayed if the third-party manufacturer had set the add-on device to do so. An AddOn ROM typically consists of firmware that is called by the system BIOS. For example, an adapter card that controls a boot device might contain firmware that is used to connect the device to the system once the AddOn ROM is loaded. # Bootup Num-Lock Set this value to allow the Number Lock setting to be modified during boot up. Off - This option does not enable the keyboard Number Lock automatically. To use the 10- keys on the keyboard, press the Number Lock key located on the upper left-hand corner of the 10-key pad. The Number Lock LED on the keyboard will light up when the Number Lock is engaged. On - Set this value to allow the Number Lock on the keyboard to be enabled automatically when the computer system is boot up. This allows the immediate use of 10-keys numeric keypad located on the right side of the keyboard. To confirm this, the Number Lock LED light on the keyboard will be lit. # PS/2 Mouse Support Allows you to Enable/Disable PS/2 mouse support. # Wait for ‘F1’ If Error If this option is set to Disabled, AMIBIOS does not wait for you to press the <F1> key after an error message. # Hit ‘DEL’ Message Display When set to Enabled, the system displays the message "Press DEL to run Setup during POST". # Interrupt 19 Capture Interrupt 19 is the software interrupt that handles the boot disk function. When enabled, this BIOS feature allows the AddOn ROM of these host adaptors to “capture” Interrupt 19 during the boot process so that drives attached to these adaptors can function as bootable disks. In addition, it allows you to gain access to the host adaptor’s AddOn ROM setup utility, if one is available. When disabled, the AddOn ROM of these host adaptors will not be able to “capture” interrupt 19. Therefore, you will not be able to boot operating systems from any bootable disks attached to these host adaptors. Nor will you be able to gain access to their AddOn ROM utilities. # Boot Device Priority Set the boot device options to determine the sequence in which the computer checks which device to boot from. # Boot Device Groups The Boot devices are listed in groups by device type. First press <Enter> to enter the submenu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or <PageUp>, <PageDown> key to move it up/down in the priority list. For example, USB storage disks will be listed as “USB Drives” in the sub-menu as below. Only the first device in each device group will be available for selection in the Boot Device Priority option.

BIOS SETUP UTILITY Boot
USB Drives	Specifies the boot sequence from the available devices.
1st Drive [USB:USB Flash Disk]
	← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# 8.6 Security Setup

BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Security Settings	Install or Change the password.
Supervisor Password :Not Installed User Password :Not Installed
Change Supervisor Password Change User Password Clear User Password	← Select Screen ↑↓ Select Item Enter Change F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# 8.6.1 Password Support # Two Levels of Password Protection Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password. The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure. # Remember the Password Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM. Select Security Setup from the Setup main BIOS setup menu. Security Setup options, such as password protection and virus protection, are described in this section. To access the sub menu for the following items, select the item and press < Enter >: - Change Supervisor Password - Change User Password - Clear User Password # Supervisor Password Indicates whether a supervisor password has been set. # User Password Indicates whether a user password has been set. # Change Supervisor Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the supervisor password. # Change User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the user password. # Clear User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to clear the user password. # 8.6.2 Change Supervisor Password Select Change Supervisor Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.3 Change User Password Select Change User Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.4 Clear User Password Select Clear User Password from the Security Setup menu and press < Enter >. Clear New Password [Ok] [Cancel] Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.7 Exit Menu Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the < Arrow > keys. The Exit BIOS Setup screen is shown below.

BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Exit Options Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe Defaults	Exit system setup after saving the changes. F10 key can be used for this operation. Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Save Changes and Exit When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect. Select Exit Saving Changes from the Exit menu and press < Enter >. Save Configuration Changes and Exit Now? [Ok] [Cancel] appears in the window. Select Ok to save changes and exit. # Discard Changes and Exit Select this option to quit Setup without making any permanent changes to the system configuration. Select Exit Discarding Changes from the Exit menu and press <Enter>. Discard Changes and Exit Setup Now? [Ok] [Cancel] appears in the window. Select Ok to discard changes and exit. # Discard Changes Select Discard Changes from the Exit menu and press < Enter >. Select Ok to discard changes. # Load Optimal Defaults Automatically sets all Setup options to a complete set of default settings when you Select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems. Select Load Optimal Defaults from the Exit menu and press < Enter >. Select Ok to load optimal defaults. # Load Failsafe Defaults Automatically sets all Setup options to a complete set of default settings when you Select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the Fail-Safe Setup options if your computer is experiencing system configuration problems. Select Load Fail-Safe Defaults from the Exit menu and press < Enter >. Load Fail-Safe Defaults? [Ok] [Cancel] appears in the window. Select Ok to load Fail-Safe defaults. # 9 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMIBIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMIBIOS checkpoints. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2001 American Megatrends, Inc.\nBIOS Date: 10/01/01 12:39:39 Ver: 08.00.03\nPentium (R) III Processor, 933MHz\nPress DEL to run Setup\nChecking NURAM..\nCheckpoint Display\nEVALUATION COPY, NOT FOR SALE\n(C) American Megatrends Inc.,\n63-0100-000001-00101111-100101-015-0AAXT004-Y2KC\n6B3B](.express-at-50-1j021-1000-200/34f99761e9b76ca729974a4e2040a2018a4e9405c3702b8ccf8db5924280d5f0.jpg) # 9.1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS: ![The image displays a graphic icon of a document with a folded top-right corner featuring a large red checkmark. Below the document graphic is the text 'NOTE:' in black capital letters.](.express-at-50-1j021-1000-200/04c45846dc35bd46adda50d853a8736d1b9702d2f958d423cb14819f94cb82d0.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

Checkpoint	Description
Before D0	If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point. Stack will be enabled from this point.
D0	Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU critical initialization. Early chipset initialization is done.
D1	Early super I/O initialization is done including RTC and keyboard controller. Serial port is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled.
D2	Verify the boot block checksum. System will hang here if checksum is bad.
D3	Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing module not executed, start memory refresh and do memory sizing in Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4	Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5	Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly.
D6	Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.
D7	Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.
D8	The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9	Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.
DA	Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.
DC	System is waking from ACPI S3 state
E1-E8, EC-EE	OEM memory detection/configuration error. This range is reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.

# 9.2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS: ![The image displays a digital icon representing a document. It features a white rectangular sheet of paper with the top-right corner folded down (a 'dog-ear'). Faint, horizontal gray lines are visible on the paper, suggesting text. Superimposed over the center of the document is a large, bold red checkmark. A soft, gray drop shadow is cast behind and below the document, giving it a slight three-dimensional appearance.](.express-at-50-1j021-1000-200/ed46b2dbe4776c7d2223fc8b4b0877869f786d5972c4621cf8d4929360cc082d.jpg) NOTE: Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.

Checkpoint	Description
E0	Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9	Set up floppy controller and data. Attempt to read from floppy.
EA	Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB	Disable ATAPI hardware. Jump back to checkpoint E9.
EF	Read error occurred on media. Jump back to checkpoint EB.
F0	Search for pre-defined recovery file name in root directory.
F1	Recovery file not found.
F2	Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3	Start reading the recovery file cluster by cluster.
F5	Disable L1 cache.
FA	Check the validity of the recovery file configuration to the current configuration of the flash part.
FB	Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.
F4	The recovery file size does not equal the found flash part size.
FC	Erase the flash part.
FD	Program the flash part.
FF	The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.

# 9.3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS: ![The image displays a white document icon with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed on the paper. Below the graphic, the text 'NOTE:' appears in black, uppercase letters.](.express-at-50-1j021-1000-200/c5dbe76722d15ca0e3f82932e36a3486c3990b1708e7d3f2f781b033286ce26c.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.

Checkpoint	Description
03	Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04	Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system
05	Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06	Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
07	Fixes CPU POST interface calling pointer.
08	Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.
C0	Early CPU Init Start -- Disable Cache - Init Local APIC
C1	Set up boot strap processor Information
C2	Set up boot strap processor for POST
C5	Enumerate and set up application processors
C6	Re-enable cache for boot strap processor
C7	Early CPU Init Exit
0A	Initializes the 8042 compatible Key Board Controller.
0B	Detects the presence of PS/2 mouse.
0C	Detects the presence of Keyboard in KBC port.
0E	Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
13	Early POST initialization of chipset registers.
20	Relocate System Management Interrupt vector for all CPU in the system.
24	Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this checkpoint.
2A	Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
2C	Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2E	Initializes all the output devices.

POST Code Checkpoints cont’d:

Checkpoint	Description
31	Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33	Initializes the silent boot module. Set the window for displaying text information.
37	Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38	Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point.
39	Initializes DMAC-1 & DMAC-2.
3A	Initialize RTC date/time.
3B	Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
3C	Mid POST initialization of chipset registers.
40	Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA...etc.
52	Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
60	Initializes NUM-LOCK status and programs the KBD typematic rate.
75	Initialize Int-13 and prepare for IPL detection.
78	Initializes IPL devices controlled by BIOS and option ROMs.
7C	Generate and write contents of ESCD in NVRam.
84	Log errors encountered during POST.
85	Display errors to the user and gets the user response for error.
87	Execute BIOS setup if needed / requested. Check boot password if installed.
8C	Late POST initialization of chipset registers.
8D	Build ACPI tables (if ACPI is supported)
8E	Program the peripheral parameters. Enable/Disable NMI as selected
90	Initialization of system management interrupt by invoking all handlers. Please note this checkpoint comes right after checkpoint 20h
A1	Clean-up work needed before booting to OS.
A2	Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
A4	Initialize runtime language module. Display boot option popup menu.
A7	Displays the system configuration screen if enabled. Initialize the CPU's before boot, which includes the programming of the MTRR's.
A9	Wait for user input at config display if needed.
AA	Uninstall POST INT1Ch vector and INT09h vector.
AB	Prepare BBS for Int 19 boot. Init MP tables.
AC	End of POST initialization of chipset registers. De-initializes the ADM module.
B1	Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.
00	Passes control to OS Loader (typically INT19h).

# 9.4 OEM POST Error Checkpoints Checkpoints from the range 61h to 70h are reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next. # 9.5 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed: ![The image features a white document icon tilted slightly to the left with a large red checkmark on it. Below the icon, the text 'NOTE:' appears in bold, black, capital letters.](.express-at-50-1j021-1000-200/cf3afe15b32716748a0e68949eb793c8f2fe691afe662204e34535a9c28bf6a3.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

Checkpoint	Description
2A	Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI- PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.
38	Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.

While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: # HIGH BYTE XY The upper nibble ‘X’ indicates the function number that is being executed. ‘X’ can be from 0 to 7. 0 = func#0, disable all devices on the BUS concerned. 1 = func#1, static devices initialization on the BUS concerned. 2 = func#2, output device initialization on the BUS concerned. 3 = func#3, input device initialization on the BUS concerned. 4 = func#4, IPL device initialization on the BUS concerned. 5 = func#5, general device initialization on the BUS concerned. 6 = func#6, error reporting for the BUS concerned. 7 = func#7, add-on ROM initialization for all BUSes. 8 = func#8, BBS ROM initialization for all BUSes. The lower nibble ‘Y’ indicates the BUS on which the different routines are being executed. ‘Y’ can be from 0 to 5. 0 = Generic DIM (Device Initialization Manager). 1 = Onboard System devices. 2 = ISA devices. 3 = EISA devices. 4 = ISA PnP devices. 5 = PCI devices. # 9.6 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events: ![The image displays a graphic icon resembling a piece of paper or a document with a folded top-right corner. A large red checkmark is prominently placed in the center of the page. Below the document graphic, the text 'NOTE:' is written in black capital letters, positioned above faint horizontal lines.](.express-at-50-1j021-1000-200/2f74ba058771dcc5de66fab78b690fabd31b29ebe71b0e59f54438b01305997d.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices. # 9.7 Boot Block Beep Codes

No. of Beeps	Description
1	Insert diskette in floppy drive A:
2	‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3	Base Memory error
4	Flash Programming successful
5	Floppy read error
6	Keyboard controller BAT command failed
7	No Flash EPROM detected
8	Floppy controller failure
9	Boot Block BIOS checksum error
10	Flash Erase error
11	Flash Program error
12	‘AMIBOOT.ROM’ file size error
13	BIOS ROM image mismatch (file layout does not match image present in flash device)

# 9.8 POST BIOS Beep Codes

No. of Beeps	Description
1	Memory refresh timer error.
2	Parity error in base memory (first 64KB block)
3	Base memory read/write test error
4	Motherboard timer not operational
5	Processor error
6	8042 Gate A20 test error (cannot switch to protected mode)
7	General exception error (processor exception interrupt error)
8	Display memory error (system video adapter)
9	AMIBIOS ROM checksum error
10	CMOS shutdown register read/write error
11	Cache memory test failed

# 9.9 Troubleshooting POST BIOS Beep Codes

No. of Beeps	Description
1, 2 or 3	Reseat the memory, or replace with known good modules.
4-7, 9-11	Fatal error indicating a serious problem with the system. Consult your system manufacturer.Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.- If beep codes are generated when all other expansion cards are absent, consult your system manufacturer's technical support.- If beep codes are not generated when all other expansion cards are absent, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem happens again. This will reveal the malfunctioning card.
8	If the system video adapter is an add-in card, replace or reseat the video adapter. If the video adapter is an integrated part of the system board, the board may be faulty.

# Important Safety Instructions For user safety, please read and follow all instructions, warnings, cautions, and notes marked in this manual and on the associated equipment before handling/operating the equipment. f Read these safety instructions carefully. f Keep this user’s manual for future reference. f Read the specifications section of this manual for detailed information on the operating environment of this equipment. f When installing/mounting or uninstalling/removing equipment: \- Turn off power and unplug any power cords/cables. f To avoid electrical shock and/or damage to equipment: - Keep equipment away from water or liquid sources; - Keep equipment away from high heat or high humidity; - Keep equipment properly ventilated (do not block or cover ventilation openings); - Make sure to use recommended voltage and power source settings; - Always install and operate equipment near an easily accessible electrical socket-outlet; - Secure the power cord (do not place any object on/over the power cord); - Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and, - If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. f Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. f A Lithium-type battery may be provided for uninterrupted, backup or emergency power. ![The image shows a standard warning sign featuring a yellow triangle with a black border and a black exclamation mark in the center. Below the triangle, the word 'CAUTION:' is printed in bold, black, capital letters.](.express-at-50-1j021-1000-200/34cea6bd7f7828bf16f6980576668608631ee19a3b2481cea0e6ba488c4f17a2.jpg) Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries according to the instructions. f Equipment must be serviced by authorized technicians when: - The power cord or plug is damaged; - Liquid has penetrated the equipment; - It has been exposed to high humidity/moisture; - It is not functioning or does not function according to the user’s manual; - It has been dropped and/or damaged; and/or, - It has an obvious sign of breakage. # Getting Service Contact us should you require any service or assistance. # ADLINK Technology Inc. Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan ؀קᗼխࡉؑ৬ԫሁ166ᇆ 9ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com # Ampro ADLINK Technology Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1 োⲜ߯ ࡯ࡼ ໻ॺ E ᑻ 801 ᅸ (100085) Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing 100085, China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com # ADLINK Technology Shanghai Address: Ϟ⍋Ꮦⓩ⊇⋒催⾥ᡔᓔথऎ䩺∳䏃 333 ো 39 ᐶ 4 ሖ (200233) Tel: +86-21-6495-5210 Fax: +86-21-5450-0414 Email: market@adlinktech.com # ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bld. A1, Cyber-Tech Zone, Gao Xin Ave. Sec 7, High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com # ADLINK Technology Inc. (German Liaison Office) Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: emea@adlinktech.com # ADLINK (French Liaison Office) Address: 15 rue Emile Baudot, 91300 MASSY Cedex, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com # ADLINK Technology Japan Corporation Address: 151-0072 ᧲੩ㇺᷦ⼱඙ᐈ䊱⼱ 1-1-2 ᦺᣣ↢๮ᐈ䊱⼱䊎䊦 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan Tel: +81-3-4455-3722 Fax: +81-3-5333-6040 Email: japan@adlinktech.com # ADLINK Technology Inc. (Korean Liaison Office) Address: 昢殾柢儛單割嚂笊壟 60-12 壟昷捒娯 4 猻 402 笾 No.402, Dongsung B/D, 60-12, Nonhyeon-Dong Gangnam-gu, Seoul, 135-010, Korea. Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com # ADLINK Technology Singapore Pte Ltd. Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com # ADLINK Technology Singapore Pte Ltd. (Indian Liaison Office) Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email: india@adlinktech.com ![The image displays a black circle containing the white universal recycling symbol. It features three white arrows arranged in a triangular loop, chasing each other, with three black stripes running along the inner edge of each arrow.](.express-at-50-1j021-1000-200/4132aa8766a9b38ee36d2995265266ba7fc0a865356acbf36e4dab81e1cfbbc0.jpg) [🔗 Link to the original document](.express-at-50-1j021-1000-200/express-at-50-1j021-1000-200.pdf)