# Express BASE6 R3.1

User’s Guide

![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/c05e883c11b9c93375fac996a59fc84c5a848662298f40ba7640e08a888df555.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2023-10-30</td><td>CC</td></tr><tr><td>0.2</td><td>Additional spec added</td><td>2023-12-28</td><td>CC</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangular warning sign with a thick black border containing a black exclamation mark in the center.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ff805bc2677fcb08b692955146ab97c533661387b0a638f6c7359b78d7871a91.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![A black and white line drawing depicts a wheeled waste bin crossed out with a large 'X', positioned directly above a solid black rectangular block.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/d5d012569199a91c8c8023325b9a967a44c4bb1099515e48aef77e9ef8cb063e.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2023 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image features a red icon on a white background. It depicts a stylized document or page with a folded top-right corner. Inside the document outline, two horizontal red lines are centered.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/70e191758e29e9430978f9f9b31a60bf40913aa9fcb4b9dc088c2331c648de80.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![This is an image of a standard warning symbol. It features a yellow triangle with rounded corners set against a white background. Inside the triangle is a black exclamation point.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/085d12b4c1af354612d1a1a97481ee8201642e910e168caa0fa06bfa72744d44.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image features a red triangular warning sign with a white exclamation point centered inside it.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/a0a7425a924781f14b128607abfd904aa5917f00dd49242d052606fa17ab5299.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

1. Introduction .. .10
2. Special Features...... ..11

2.1. One PCI Express Gen4 x16 slot + One x4 Slot.... ..12
2.2. Two USB4 Type-C Connectors .. ..12
2.3. Display ... ..12
2.4. SD Card... ..12
2.5. RS-232/422/485 .. .12

3. Component Location.... .13
4. Functional Diagram... .14
5. Mechanical Dimension.. .15
6. Connectors and Pinouts... .17

6.1. Carrier Board Signals — Type 6... ..17
6.2. Connector Location and Pinout Compatibility... ... 18
6.3. Carrier Board Design .. ..19
6.4. COM Express R3.1 Type 6 Board-to-board Connectors ..... ..19
6.5. PCIe x16 Connectors.. ..23
6.6. PCIe x4 Connector .. ..24
6.7. PCIe x1 Connector .. ..25
6.8. USB2.0 Port Header... ..26
6.9. Audio Header .. ..26
6.10. SATA Port... ..27
6.11. LPC/ eSPI Debug Header ... ..28
6.12. PS2 Header... ... 28
6.13. COM Port Connector..... ..29
6.14. VGA Connector... ..30
6.15 Audio Phone Jack.. ..31
6.16 LAN and USB 3.2 Gen 2 . ..31
6.17 USB Connector... ..32

6.18 DP connector... ... 34
6.19 BASE6 GPIO Expander Header ... ..34
6.20. GPIO Header... ... 35
6.21. SMBus Header... ... 35
6.22. I2C Header.... ... 35
6.23. Fan Header .. ..36
6.24. General Purpose SPI Header.. ..37
6.25. Front Panel Control.. ... 37
6.26. Panel Connector... ... 38
6.27. Battery Connector... ... 39
6.28. Power Connectors . ... 39
6.29. Carrier EEPROM Address Switch .. ... 40
6.30. Other Jumpers... ..... 41

7. Secondary BIOS .. ..44

8. Switches, POST, and LEDs.... .....45

8.1. Switches (S0-S5) .. ... 45

8.2. POST and Inductor LEDs .. ... 47

8.3. ATX Power Connectors . ... 48

# List of Figures

Figure 1 – Carrier top view... .11
Figure 2 – Component location.. .13
Figure 3 – Functional diagram... .14
Figure 4 – Mechanical dimensions .... .15
Figure 5 – Carrier board signals, type 6 pinout ... .17

# Introduction

The COM Express approach of custom carrier combined with off-the-shelf system cores relieves developers the need to design their own system core, thereby not only accelerating their proof of concept significantly but also empowers them to upgrade to later-generation processors without having to redesign. It fits most system integration projects with production volumes ranging from 500 to 10,000 pcs per year. The COM Express concept reduces engineering complexity, lowers the threshold for total project quantity, and last but not least brings your product to the market in no time. The average time to design a carrier board is less than half the time of a full custom OEM board.

The Express-BASE6 R3.1, based on PICMG COM-Express R3.1, is an extended ATX size carrier board. Together with the COM Express Type 6 module of your choice and off-the-shelf add-on cards, you can quickly emulate the functionality of your desired end product for software development and hardware verification.

To build a functional prototype of your target system, you will need:

COM Express Type 6 module
Express-BASE6 R3.1 carrier
PCI Express-based storage or SATA storage (SATA storage solutions are dependent on module specifications)

The Express-BASE6 R3.1 carrier is compatible with Basic size and Compact size COMe modules and may accommodate:

1x PCI Express x16 slot, 1x PCI Express x4 slots, 4x PCI Express x1 slots
1x VGA, 1x DP, 1x general purpose LAN, 2x USB 4.0, 4x USB 3.2, 2x USB 2.0, 1x DB-9 COM port, 1x SPDIF, 1x Line-in/Mic-in/Speaker-out (at rear I/O)

# Special Features

![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/29a6465fc38c3125ae929d35612544aba508f41b0441e74b665b7824288637a6.jpg)

Figure 1 – Carrier top view

# 2.1. One PCI Express Gen4 x16 slot + One x4 Slot

1x FHFL PCI Express Gen4 card at PEG slot and 1x PCI Express Gen4 card at PCIE0\_3 slot

# 2.2. Two USB4 Type-C Connectors

2x USB Type-C connector that support USB4 spec (Thunderbolt 4 compatible), can be used to transmit data or output images

# 2.3. Display

1x VGA, 1x DP, 1x LVDS and 1x eDP (BOM option) connector onboard, can display without going through T6DDI

# 2.4. SD Card

1x SD Card connector (with GPIO function by BOM option)

# 2.5. RS-232/422/485

1x DB9 connector and 3x pin header onboard

![The image features a red icon on a white background. It depicts a document symbol with a thick red outline and a folded bottom-right corner. Inside the outline are horizontal red bars of varying lengths, resembling lines of text.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/091bb61d7f677f0f836c182378fc19fdef777f6f66ee2c22c2fb06a379cabf6c.jpg)

Note: Before installing an USB, PCIe Gen4, or SD card module, make sure the function is supported by your module.

# 3. Component Location

![PWR BIN\nModule GPIO\nSMBUS GPIO\nI2C SMBUS IP5\nST BIN\nSLP BIN TO BIN\nAUDIO\nAUD SUR\nF PANEL\nPWR ON\nHDD\nSVSB CN23\nS1\nJP33\nEEP\nSD CARD\nSWI\nIP6\nGP SP1 IP7\nCOM\nExpress\nPCIE7\nPCIE6\nPCIE5\nPCIE4\nPCIE0 3\nPEG\nI27 I24 LVDS SATA PWR SATA 3\neDP JP35 SATA 2\nBL CTRL UP29\nBATTERY\nATX 4\nIP32 JP33\nATX 24\nAB\nCD\nAUDIO\nSPD/F\nUSB 4.5\nLAN USB 2.3\nUSB 0.1\nDP DD13\nUSB4 1\nUSB4 2\nVGA_COM0\nFAN COMC FAN 1 FAN 2 COM1 COM2 COM3 LP- CSPI KB MS](.express-base6-r3-1-manual-50m-77107-1000-02-231228/070090bb7d28656f75a0ba2bf5340245a61759e9c5fef3d857994b70d79cb8bc.jpg)

Figure 2 – Component location

# 4 Functional Diagram

![This block diagram depicts a system architecture organized into three vertical sections connected by bus interfaces labeled vertically as **AB** and **CD**.\n\n**Left Section (Peripherals & Controllers):**\n*   **LVDS/eDP:** **34 pin LVDS** and **eDP** (build option) connect to bus **AB**.\n*   **SATA:** **SATA 0**, **SATA 1**, **SATA 2**, and **SATA 3** connect to bus **AB**.\n*   **PCIe:** **PCIe 0-3 (x4)**, **PCIe 4**, and **PCIe 5** connect to bus **AB**.\n*   **Audio:** **Audio Codec ACL888** connects to bus **AB** via **HDA**. It also connects to audio jacks (blue, green, pink) and **SPDIF**.\n*   **Super I/O:** **Super I/O NCT6126D** connects to bus **AB** via **LPC**. It connects to **Port 80** (labeled **8 8**), **RS-232 pitch 2.54**, **SP 339**, **Analog VGA**, a **2x** connector, and **FAN**.\n\n**Middle Section (I/O & Connectivity):**\n*   **USB/TB:** **USB 4(2.0/1.1)** connects to **TBT4 JHL8540**. **USB 5(2.0/1.1)** connects to **USB PD**. These connect to **USB4 1** and **USB4 2**.\n*   **LAN:** **LAN (2.5GbE)** connects to a network jack.\n*   **USB Ports (Group 1):** **USB 2 (2.0/1.1)** and **USB 3 (2.0/1.1)** connect to USB ports. **USB 2 (3.x)** and **USB 3 (3.x)** connect to the same ports.\n*   **USB Ports (Group 2):** **USB 0 (2.0/1.1)** and **USB 1 (2.0/1.1)** connect to USB ports. **USB 0 (3.x)** and **USB 1 (3.x)** connect to the same ports.\n*   **USB Port (Group 3):** **USB 6 (2.0/1.1)** connects to a USB port.\n*   **USB Hub:** **USB 7 (2.0/1.1)** connects to **USB Hub**, which connects to **2x** and **9-pin pitch 2.54**.\n*   **SD/GPIO:** **MUX** connects to **SD Slot** and **8-pin GPIO pitch 2.54**.\n*   **Serial/Bus:** **SER 0/1** connects to serial ports. **I2C, SMB** connects to a header. **Feature, Controls** connects to a header. **SPI** connects to a connector.\n\n**Right Section (Expansion & Video):**\n*   **PCIe/HDMI:** **PCIe 16-31 (x16)** connects to a large slot. **DDI 3** connects to **HDMI**. **PCIe 6** and **PCIe 7** connect to respective slots.\n\n**Connections:**\n*   Bus **AB** links the Left Section to the Middle Section.\n*   Bus **CD** links the Middle Section to the Right Section.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/866c5c65591db20719d3c098ed055159399f2ea508f252a20373cd4cddd0bd65.jpg)

Figure 3 – Functional diagram

# 5. Mechanical Dimension

![227.33\n154.94\n0\n16.51\n0\n58.42\n24.4\n44.72\n65.04\n78.74\n85.36\n105.68\n124.46\n126\n154.55\n241.55\n281.94\n227.33\n189.9\n159.9\n148.9\n72.9\n22.86\n281.94](.express-base6-r3-1-manual-50m-77107-1000-02-231228/19953abe2f878b8f41829fe591decbb4124b0a0646448908758618544c59e6e3.jpg)

Figure 4 – Mechanical dimensions

![The image displays a simple icon of a document or memo pad. It features a red outline on a white background, with a folded bottom-right corner. Inside the shape, two horizontal red lines represent text.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/005538cdd7165d6fe056acaed281718434692a6404a8696ad4139b3f4f9a9acb.jpg)

# Note:

1. All dimensions are shown in millimeters with a tolerance of ± 0.25mm unless otherwise noted.

2. To install a Basic size module, you can lock it in place using self-supplied screws via the yellow and green locations of the carrier.
3. To install a Compact size module, you can lock it in place using self-supplied screws via the blue and green locations of the carrier.
4. The screws used to lock the module onto the carrier shall be of the following specifications:

![Φ4.25 ±0.25\nΦ4.8 ±0.2](.express-base6-r3-1-manual-50m-77107-1000-02-231228/f28122bfd8df89845d0d58028d10cf3bc0536a04412f72b03cfc082a490e29c9.jpg)

![Φ4.8 (MAX.)\n0.60 (MIN)\n0.5±0.1\n1.7±0.2\n15.6 ± 0.4](.express-base6-r3-1-manual-50m-77107-1000-02-231228/40fd382e6ac21c8af48e7bbb1072cc58e56852e9cfa3458f869bde4b1f2e5ada.jpg)

# 6. Connectors and Pinouts

# 6.1. Carrier Board Signals — Type 6

![Type 6\n2x 220 pins\n| Category | Subcategories | Value |\n| :--- | :--- | :--- |\n| CD | LPC | 4x USB 3.x upgrade |\n| CD | GbE | 2x PCIe |\n| AB | 4x SATA | DDI_1 / USB4_1 |\n| AB | HDA / SNDW | DDI_2 / USB4_2 |\n| AB | 8x USB 2.0 | DDI_3 |\n| AB | PCIe x16 | 12V |\n| AB | 6x PCIe | LVDS / eDP |\n| AB | CRT (VGA) | CRT (VGA) |\n| AB | GP SPI | GP SPI |\n| Type 6 | 4x USB 3.x upgrade | 4x USB 3.x upgrade |\n| Type 6 | 2x PCIe | 2x PCIe |\n| Type 6 | DDI_1 / USB4_1 | DDI_1 / USB4_1 |\n| Type 6 | DDI_2 / USB4_2 | DDI_2 / USB4_2 |\n| Type 6 | DDI_3 | DDI_3 |\n| Type 6 | PCIe x16 | PCIe x16 |\n| Type 6 | 12V | 12V |\n| Type 6 | 5Vsb | 5Vsb |\nThe chart displays a single bar for each category. The values are estimated based on the numerical labels above each bar. The label '2x 220 pins' indicates the number of pins in two rows.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/58e3eb18d5a435465570ebecf3720c9d580c38ad71f038e69be7dfe151c8e200.jpg)

Figure 5 – Carrier board signals, type 6 pinout

# New Features of COM.0 R3.1

• PCIe Gen4 support
• USB4 over current DDI (USB port 1,2 overlap with DDI 1,2)
General-purpose SPI added
• Sound Wire over current HDA added

# 6.2. Connector Location and Pinout Compatibility

Connector positions and pinouts comply with the pinout and signal descriptions within PICMG® COM.0 - COM Express Module Base specification, Revision 3.1. This document includes description of pinouts, signal descriptions and mechanical characteristics of the COM Express specification. The Express-BASE6 R3.1 is compatible with COM Express modules in Basic and Compact form factor, Type 6 pinout, COM.0 Rev. 3.1.

Signals and Pinout for: COM Express Type 6.

![D1\nC1\nD110\nC D\nC110\nB1\nA1\nB110\nA B\nA10](.express-base6-r3-1-manual-50m-77107-1000-02-231228/0648777496938e3976bec5c69c19ae37db7055c0d70f2e4df740d4b95ba9a2c1.jpg)

# 6.3. Carrier Board Design

Express-BASE6 R3.1 follows the PICMG COM Express Carrier Design Guide where possible, and its design and schematic have been fully verified. It is recommend to utilize them as references for your carrier board design. Express-BASE6 R3.1 schematics and mechanical files, as well as the CDG, can be downloaded from ADLINK COM’s webpage.

# 6.4. COM Express R3.1 Type 6 Board-to-board Connectors

Signals and Pinouts of COM Express R3.1 Type 6. Differences of R3.1 (from R3.0) are marked as bold.

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>GND</td><td></td><td>B1</td><td>GND</td><td></td><td>C1</td><td>GND</td><td></td><td>D1</td><td>GND</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td></td><td>B2</td><td>GBE0_ACT#</td><td></td><td>C2</td><td>GND</td><td></td><td>D2</td><td>GND</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td></td><td>B3</td><td>LPC_FRAME#/ESPI_CS0#</td><td></td><td>C3</td><td>USB_SSRX0-</td><td></td><td>D3</td><td>USB_SSTX0-</td></tr><tr><td>A4</td><td>GBE0_LINK100#</td><td></td><td>B4</td><td>LPC_AD0/ESPI_IO_0</td><td></td><td>C4</td><td>USB_SSRX0+</td><td></td><td>D4</td><td>USB_SSTX0+</td></tr><tr><td>A5</td><td>GBE0_LINK1000#</td><td></td><td>B5</td><td>LPC_AD1/ESPI_IO_1</td><td></td><td>C5</td><td>GND</td><td></td><td>D5</td><td>GND</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td></td><td>B6</td><td>LPC_AD2/ESPI_IO_2</td><td></td><td>C6</td><td>USB_SSRX1-</td><td></td><td>D6</td><td>USB_SSTX1-</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td></td><td>B7</td><td>LPC_AD3/ESPI_IO_3</td><td></td><td>C7</td><td>USB_SSRX1+</td><td></td><td>D7</td><td>USB_SSTX1+</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td></td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td><td></td><td>C8</td><td>GND</td><td></td><td>D8</td><td>GND</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td></td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td><td></td><td>C9</td><td>USB_SSRX2-</td><td></td><td>D9</td><td>USB_SSTX2-</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td></td><td>B10</td><td>LPC_CLK/ESPI_CK</td><td></td><td>C10</td><td>USB_SSRX2+</td><td></td><td>D10</td><td>USB_SSTX2+</td></tr><tr><td>A11</td><td>GND</td><td></td><td>B11</td><td>GND</td><td></td><td>C11</td><td>GND</td><td></td><td>D11</td><td>GND</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td></td><td>B12</td><td>PWRBTN#</td><td></td><td>C12</td><td>USB_SSRX3-</td><td></td><td>D12</td><td>USB_SSTX3-</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td></td><td>B13</td><td>SMB_CK</td><td></td><td>C13</td><td>USB_SSRX3+</td><td></td><td>D13</td><td>USB_SSTX3+</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td></td><td>B14</td><td>SMB_DAT</td><td></td><td>C14</td><td>GND</td><td></td><td>D14</td><td>GND</td></tr><tr><td>A15</td><td>SUS_S3#</td><td></td><td>B15</td><td>SMB_ALERT#</td><td></td><td>C15</td><td>USB4_1_LSTX</td><td></td><td>D15</td><td>DDI1_CTRLCLK_AUX+/USB4_1_AUX+</td></tr><tr><td>A16</td><td>SATA0_TX+</td><td></td><td>B16</td><td>SATA1_TX+</td><td></td><td>C16</td><td>USB4_1_LSRX</td><td></td><td>D16</td><td>DDI1_CTRLDATA_AUX-/USB4_1_AUX-</td></tr><tr><td>A17</td><td>SATA0_TX-</td><td></td><td>B17</td><td>SATA1_TX-</td><td></td><td>C17</td><td>USB4_RT_ENA</td><td></td><td>D17</td><td>USB4_PD_I2C_ALERT#</td></tr><tr><td>A18</td><td>SUS_S4#</td><td></td><td>B18</td><td>SUS_STAT#/ESPI_RESET#</td><td></td><td>C18</td><td>GND</td><td></td><td>D18</td><td>PMCALERT#</td></tr><tr><td>A19</td><td>SATA0_RX+</td><td></td><td>B19</td><td>SATA1_RX+</td><td></td><td>C19</td><td>PCIE_RX6+</td><td></td><td>D19</td><td>PCIE_TX6+</td></tr><tr><td>A20</td><td>SATA0_RX-</td><td></td><td>B20</td><td>SATA1_RX-</td><td></td><td>C20</td><td>PCIE_RX6-</td><td></td><td>D20</td><td>PCIE_TX6-</td></tr><tr><td>A21</td><td>GND</td><td></td><td>B21</td><td>GND</td><td></td><td>C21</td><td>GND</td><td></td><td>D21</td><td>GND</td></tr><tr><td>A22</td><td>SATA2_TX+</td><td></td><td>B22</td><td>SATA3_TX+</td><td></td><td>C22</td><td>PCIE_RX7+</td><td></td><td>D22</td><td>PCIE_TX7+</td></tr></table>

<table><tr><td colspan="2">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td colspan="2">Row D</td></tr><tr><td>A23</td><td>SATA2_TX-</td><td>B23</td><td>SATA3_TX-</td><td>C23</td><td>PCIE_RX7-</td><td>D23</td><td>PCIE_TX7-</td></tr><tr><td>A24</td><td>SUS_S5#</td><td>B24</td><td>PWR_OK</td><td>C24</td><td>DDI1_HPD</td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>SATA2_RX+</td><td>B25</td><td>SATA3_RX+</td><td>C25</td><td>SML0_CLK</td><td>D25</td><td>GND</td></tr><tr><td>A26</td><td>SATA2_RX-</td><td>B26</td><td>SATA3_RX-</td><td>C26</td><td>SML0_DAT</td><td>D26</td><td>DDI1_PAIR0+/USB4_1_SSTX0+</td></tr><tr><td>A27</td><td>BATLOW#</td><td>B27</td><td>WDT</td><td>C27</td><td>SML1_CLK</td><td>D27</td><td>DDI1_PAIR0-/USB4_1_SSTX0-</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td>B28</td><td>HDA_SDIN2/SNDW0_CLK</td><td>C28</td><td>SML1_DAT</td><td>D28</td><td>GND</td></tr><tr><td>A29</td><td>HDA_SYNC</td><td>B29</td><td>HDA_SDIN1/SNDW0_DAT</td><td>C29</td><td>USB4_PD_I2C_CLK</td><td>D29</td><td>DDI1_PAIR1+/USB4_1_SSRX0+</td></tr><tr><td>A30</td><td>HDA_RST#</td><td>B30</td><td>HDA_SDIN0</td><td>C30</td><td>USB4_PD_I2C_DAT</td><td>D30</td><td>DDI1_PAIR1-/USB4_1_SSRX0-</td></tr><tr><td>A31</td><td>GND</td><td>B31</td><td>GND</td><td>C31</td><td>GND</td><td>D31</td><td>GND</td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td>B32</td><td>SPKR</td><td>C32</td><td>DDI2_CTRLCLK_AUX+/USB4_2_AUX+</td><td>D32</td><td>DDI1_PAIR2+/USB4_1_SSTX1+</td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td>B33</td><td>I2C_CK</td><td>C33</td><td>DDI2_CTRLDATA_AUX-/USB4_2_AUX-</td><td>D33</td><td>DDI1_PAIR2-/USB4_1_SSTX1-</td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS</td><td>B34</td><td>I2C_DAT</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td>B35</td><td>THRM#</td><td>C35</td><td>USB4_2_LSTX</td><td>D35</td><td>USB4_2_LSRX</td></tr><tr><td>A36</td><td>USB6-</td><td>B36</td><td>USB7-</td><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td>D36</td><td>DDI1_PAIR3+/USB4_1_SSRX1+</td></tr><tr><td>A37</td><td>USB6+</td><td>B37</td><td>USB7+</td><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td>D37</td><td>DDI1_PAIR3-/USB4_1_SSRX1-</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td>B38</td><td>USB_4_5_OC#</td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td>D38</td><td>GND</td></tr><tr><td>A39</td><td>USB4-</td><td>B39</td><td>USB5-</td><td>C39</td><td>DDI3_PAIR0+</td><td>D39</td><td>DDI2_PAIR0+/USB4_2_SSTX0+</td></tr><tr><td>A40</td><td>USB4+</td><td>B40</td><td>USB5+</td><td>C40</td><td>DDI3_PAIR0-</td><td>D40</td><td>DDI2_PAIR0-/USB4_2_SSTX0-</td></tr><tr><td>A41</td><td>GND</td><td>B41</td><td>GND</td><td>C41</td><td>GND</td><td>D41</td><td>GND</td></tr><tr><td>A42</td><td>USB2-</td><td>B42</td><td>USB3-</td><td>C42</td><td>DDI3_PAIR1+</td><td>D42</td><td>DDI2_PAIR1+/USB4_2_SSRX0+</td></tr><tr><td>A43</td><td>USB2+</td><td>B43</td><td>USB3+</td><td>C43</td><td>DDI3_PAIR1-</td><td>D43</td><td>DDI2_PAIR1-/USB4_2_SSRX0-</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td>B44</td><td>USB_0_1_OC#</td><td>C44</td><td>DDI3_HPD</td><td>D44</td><td>DDI2_HPD</td></tr><tr><td>A45</td><td>USB0-</td><td>B45</td><td>USB1-</td><td>C45</td><td>GP_SPI_CS0#</td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>USB0+</td><td>B46</td><td>USB1+</td><td>C46</td><td>DDI3_PAIR2+</td><td>D46</td><td>DDI2_PAIR2+/USB4_2_SSTX1+</td></tr><tr><td>A47</td><td>VCC_RTC</td><td>B47</td><td>ESPI_EN#</td><td>C47</td><td>DDI3_PAIR2-</td><td>D47</td><td>DDI2_PAIR2-/USB4_2_SSTX1-</td></tr><tr><td>A48</td><td>RSMRST_OUT#</td><td>B48</td><td>USB0_HOST_PRSNT</td><td>C48</td><td>RSVD</td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GBEO_SDP</td><td>B49</td><td>SYS_RESET#</td><td>C49</td><td>DDI3_PAIR3+</td><td>D49</td><td>DDI2_PAIR3+/USB4_2_SSRX1+</td></tr><tr><td>A50</td><td>LPC_SERIRQ/ESPI_CS1#</td><td>B50</td><td>CB_RESET#</td><td>C50</td><td>DDI3_PAIR3-</td><td>D50</td><td>DDI2_PAIR3-/USB4_2_SSRX1-</td></tr><tr><td>A51</td><td>GND</td><td>B51</td><td>GND</td><td>C51</td><td>GND</td><td>D51</td><td>GND</td></tr><tr><td>A52</td><td>PCIE_TX5+</td><td>B52</td><td>PCIE_RX5+</td><td>C52</td><td>PEG_RX0+</td><td>D52</td><td>PEG_TX0+</td></tr><tr><td>A53</td><td>PCIE_TX5-</td><td>B53</td><td>PCIE_RX5-</td><td>C53</td><td>PEG_RX0-</td><td>D53</td><td>PEG_TX0-</td></tr><tr><td>A54</td><td>GPIO</td><td>B54</td><td>GPO</td><td>C54</td><td>TYPE0#</td><td>D54</td><td>PEG_LANE_RV#</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td>B55</td><td>PCIE_RX4+</td><td>C55</td><td>PEG_RX1+</td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td>B56</td><td>PCIE_RX4-</td><td>C56</td><td>PEG_RX1-</td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td>B57</td><td>GPO2</td><td>C57</td><td>TYPE1#</td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td>B58</td><td>PCIE_RX3+</td><td>C58</td><td>PEG_RX2+</td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td>B59</td><td>PCIE_RX3-</td><td>C59</td><td>PEG_RX2-</td><td>D59</td><td>PEG_TX2-</td></tr></table>

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A60</td><td>GND</td><td></td><td>B60</td><td>GND</td><td></td><td>C60</td><td>GND</td><td></td><td>D60</td><td>GND</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td></td><td>B61</td><td>PCIE_RX2+</td><td></td><td>C61</td><td>PEG_RX3+</td><td></td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td></td><td>B62</td><td>PCIE_RX2-</td><td></td><td>C62</td><td>PEG_RX3-</td><td></td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1</td><td></td><td>B63</td><td>GPO3</td><td></td><td>C63</td><td>GND</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td></td><td>B64</td><td>PCIE_RX1+</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>GND</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td></td><td>B65</td><td>PCIE_RX1-</td><td></td><td>C65</td><td>PEG_RX4+</td><td></td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td></td><td>B66</td><td>WAKE0#</td><td></td><td>C66</td><td>PEG_RX4-</td><td></td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2</td><td></td><td>B67</td><td>WAKE1#</td><td></td><td>C67</td><td>RAPID_SHUTDOWN</td><td></td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td></td><td>B68</td><td>PCIE_RX0+</td><td></td><td>C68</td><td>PEG_RX5+</td><td></td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td></td><td>B69</td><td>PCIE_RX0-</td><td></td><td>C69</td><td>PEG_RX5-</td><td></td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND</td><td></td><td>B70</td><td>GND</td><td></td><td>C70</td><td>GND</td><td></td><td>D70</td><td>GND</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td></td><td>B71</td><td>LVDS_B0+</td><td></td><td>C71</td><td>PEG_RX6+</td><td></td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td></td><td>B72</td><td>LVDS_B0-</td><td></td><td>C72</td><td>PEG_RX6-</td><td></td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td></td><td>B73</td><td>LVDS_B1+</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td></td><td>B74</td><td>LVDS_B1-</td><td></td><td>C74</td><td>PEG_RX7+</td><td></td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td></td><td>B75</td><td>LVDS_B2+</td><td></td><td>C75</td><td>PEG_RX7-</td><td></td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td></td><td>B76</td><td>LVDS_B2-</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td></td><td>B77</td><td>LVDS_B3+</td><td></td><td>C77</td><td>GND</td><td></td><td>D77</td><td>GND</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td></td><td>B78</td><td>LVDS_B3-</td><td></td><td>C78</td><td>PEG_RX8+</td><td></td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td></td><td>B79</td><td>LVDS_BKLT_EN</td><td></td><td>C79</td><td>PEG_RX8-</td><td></td><td>D79</td><td>PEG_TX8-</td></tr><tr><td>A80</td><td>GND</td><td></td><td>B80</td><td>GND</td><td></td><td>C80</td><td>GND</td><td></td><td>D80</td><td>GND</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td></td><td>B81</td><td>LVDS_B_CK+</td><td></td><td>C81</td><td>PEG_RX9+</td><td></td><td>D81</td><td>PEG_TX9+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td></td><td>B82</td><td>LVDS_B_CK-</td><td></td><td>C82</td><td>PEG_RX9-</td><td></td><td>D82</td><td>PEG_TX9-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td></td><td>B83</td><td>LVDS_BKLT_CTRL</td><td></td><td>C83</td><td>GND</td><td></td><td>D83</td><td>GND</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td></td><td>B84</td><td>VCC_5V_SBY</td><td></td><td>C84</td><td>GND</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3</td><td></td><td>B85</td><td>VCC_5V_SBY</td><td></td><td>C85</td><td>PEG_RX10+</td><td></td><td>D85</td><td>PEG_TX10+</td></tr><tr><td>A86</td><td>GP_SPI_MOSI</td><td></td><td>B86</td><td>VCC_5V_SBY</td><td></td><td>C86</td><td>PEG_RX10-</td><td></td><td>D86</td><td>PEG_TX10-</td></tr><tr><td>A87</td><td>eDP_HPD</td><td></td><td>B87</td><td>VCC_5V_SBY</td><td></td><td>C87</td><td>GND</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE_CLK_REF+</td><td></td><td>B88</td><td>BIOS_DIS1#</td><td></td><td>C88</td><td>PEG_RX11+</td><td></td><td>D88</td><td>PEG_TX11+</td></tr><tr><td>A89</td><td>PCIE_CLK_REF-</td><td></td><td>B89</td><td>VGA_RED</td><td></td><td>C89</td><td>PEG_RX11-</td><td></td><td>D89</td><td>PEG_TX11-</td></tr><tr><td>A90</td><td>GND</td><td></td><td>B90</td><td>GND</td><td></td><td>C90</td><td>GND</td><td></td><td>D90</td><td>GND</td></tr><tr><td>A91</td><td>SPI_POWER</td><td></td><td>B91</td><td>VGA_GRN</td><td></td><td>C91</td><td>PEG_RX12+</td><td></td><td>D91</td><td>PEG_TX12+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td></td><td>B92</td><td>VGA_BLU</td><td></td><td>C92</td><td>PEG_RX12-</td><td></td><td>D92</td><td>PEG_TX12-</td></tr><tr><td>A93</td><td>GPO0</td><td></td><td>B93</td><td>VGA_HSYNC</td><td></td><td>C93</td><td>GND</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td></td><td>B94</td><td>VGA_VSYNC</td><td></td><td>C94</td><td>PEG_RX13+</td><td></td><td>D94</td><td>PEG_TX13+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td></td><td>B95</td><td>VGA_I2C_CK</td><td></td><td>C95</td><td>PEG_RX13-</td><td></td><td>D95</td><td>PEG_TX13-</td></tr><tr><td>A96</td><td>TPM_PP</td><td></td><td>B96</td><td>VGA_I2C_DAT</td><td></td><td>C96</td><td>GND</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td></td><td>B97</td><td>SPI_CS#</td><td></td><td>C97</td><td>GND</td><td></td><td>D97</td><td>GND</td></tr><tr><td>A98</td><td>SER0_TX</td><td></td><td>B98</td><td>GP_SPI_MISO</td><td></td><td>C98</td><td>PEG_RX14+</td><td></td><td>D98</td><td>PEG_TX14+</td></tr><tr><td>A99</td><td>SER0_RX</td><td></td><td>B99</td><td>GP_SPI_CK</td><td></td><td>C99</td><td>PEG_RX14-</td><td></td><td>D99</td><td>PEG_TX14-</td></tr><tr><td>A100</td><td>GND</td><td></td><td>B100</td><td>GND</td><td></td><td>C100</td><td>GND</td><td></td><td>D100</td><td>GND</td></tr><tr><td>A101</td><td>SER1_TX</td><td></td><td>B101</td><td>FAN_PWMOUT</td><td></td><td>C101</td><td>PEG_RX15+</td><td></td><td>D101</td><td>PEG_TX15+</td></tr><tr><td>A102</td><td>SER1_RX</td><td></td><td>B102</td><td>FAN_TACHIN</td><td></td><td>C102</td><td>PEG_RX15-</td><td></td><td>D102</td><td>PEG_TX15-</td></tr><tr><td>A103</td><td>LID#</td><td></td><td>B103</td><td>SLEEP#</td><td></td><td>C103</td><td>GND</td><td></td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td></td><td>B104</td><td>VCC_12V</td><td></td><td>C104</td><td>VCC_12V</td><td></td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td></td><td>B105</td><td>VCC_12V</td><td></td><td>C105</td><td>VCC_12V</td><td></td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td></td><td>B106</td><td>VCC_12V</td><td></td><td>C106</td><td>VCC_12V</td><td></td><td>D106</td><td>VCC_12V</td></tr><tr><td>A107</td><td>VCC_12V</td><td></td><td>B107</td><td>VCC_12V</td><td></td><td>C107</td><td>VCC_12V</td><td></td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td></td><td>B108</td><td>VCC_12V</td><td></td><td>C108</td><td>VCC_12V</td><td></td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td></td><td>B109</td><td>VCC_12V</td><td></td><td>C109</td><td>VCC_12V</td><td></td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND</td><td></td><td>B110</td><td>GND</td><td></td><td>C110</td><td>GND</td><td></td><td>D110</td><td>GND</td></tr></table>

# 6.5. PCIe x16 Connectors

PEG: PCIe Gen4 x16 slot, PEG lanes 0 to 15 assigned PCIe slot

![Pure electrical circuit lines without any symbols](.express-base6-r3-1-manual-50m-77107-1000-02-231228/09149b81f89a5073e96604595ad01006596756bf2b21cbdc9121d9f014ec3da2.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+ 12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+ 12V</td><td>A2</td><td>+ 12V</td></tr><tr><td>B3</td><td>+ 12V</td><td>A3</td><td>+ 12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+ 3.3V</td></tr><tr><td>B10</td><td>+ 3.3VAUX</td><td>A10</td><td>+ 3.3V</td></tr><tr><td>B11</td><td>WAKE#</td><td>A11</td><td>PERST#</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B64</td><td>GND</td><td>A64</td><td>PERp11</td></tr><tr><td>B65</td><td>GND</td><td>A65</td><td>PERn11</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td>B33</td><td>PETp4</td><td>A33</td><td>RSVD</td></tr><tr><td>B34</td><td>PETn4</td><td>A34</td><td>GND</td></tr><tr><td>B35</td><td>GND</td><td>A35</td><td>PERp4</td></tr><tr><td>B36</td><td>GND</td><td>A36</td><td>PERn4</td></tr><tr><td>B37</td><td>PETp5</td><td>A37</td><td>GND</td></tr><tr><td>B38</td><td>PETn5</td><td>A38</td><td>GND</td></tr><tr><td>B39</td><td>GND</td><td>A39</td><td>PERp5</td></tr><tr><td>B40</td><td>GND</td><td>A40</td><td>PERn5</td></tr><tr><td>B41</td><td>PETp6</td><td>A41</td><td>GND</td></tr><tr><td>B42</td><td>PETn6</td><td>A42</td><td>GND</td></tr><tr><td>B71</td><td>PETn13</td><td>A71</td><td>GND</td></tr><tr><td>B72</td><td>GND</td><td>A72</td><td>PERp13</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B43</td><td>GND</td><td>A43</td><td>PERp6</td></tr><tr><td>B44</td><td>GND</td><td>A44</td><td>PERn6</td></tr><tr><td>B45</td><td>PETp7</td><td>A45</td><td>GND</td></tr><tr><td>B46</td><td>PETn7</td><td>A46</td><td>GND</td></tr><tr><td>B47</td><td>GND</td><td>A47</td><td>PERp7</td></tr><tr><td>B48</td><td>PRSNT</td><td>A48</td><td>PERn7</td></tr><tr><td>B49</td><td>GND</td><td>A49</td><td>GND</td></tr><tr><td>B50</td><td>PETp8</td><td>A50</td><td>RSVD</td></tr><tr><td>B51</td><td>PETn8</td><td>A51</td><td>GND</td></tr><tr><td>B52</td><td>GND</td><td>A52</td><td>PERp8</td></tr><tr><td>B53</td><td>GND</td><td>A53</td><td>PERn8</td></tr><tr><td>B54</td><td>PETp9</td><td>A54</td><td>GND</td></tr><tr><td>B55</td><td>PETn9</td><td>A55</td><td>GND</td></tr><tr><td>B56</td><td>GND</td><td>A56</td><td>PERp9</td></tr><tr><td>B57</td><td>GND</td><td>A57</td><td>PERn9</td></tr><tr><td>B58</td><td>PETp10</td><td>A58</td><td>GND</td></tr><tr><td>B59</td><td>PETn10</td><td>A59</td><td>GND</td></tr><tr><td>B60</td><td>GND</td><td>A60</td><td>PERp10</td></tr><tr><td>B61</td><td>GND</td><td>A61</td><td>PERn10</td></tr><tr><td>B62</td><td>PETp11</td><td>A62</td><td>GND</td></tr><tr><td>B63</td><td>PETn11</td><td>A63</td><td>GND</td></tr><tr><td>B78</td><td>PETp15</td><td>A78</td><td>GND</td></tr><tr><td>B79</td><td>PETn15</td><td>A79</td><td>GND</td></tr><tr><td>B66</td><td>PETp12</td><td>A66</td><td>GND</td></tr><tr><td>B67</td><td>PETn12</td><td>A67</td><td>GND</td></tr><tr><td>B68</td><td>GND</td><td>A68</td><td>PERp12</td></tr><tr><td>B69</td><td>GND</td><td>A69</td><td>PERn12</td></tr><tr><td>B70</td><td>PETp13</td><td>A70</td><td>GND</td></tr></table>

<table><tr><td>B73</td><td>GND</td><td>A73</td><td>PERn13</td></tr><tr><td>B74</td><td>PETp14</td><td>A74</td><td>GND</td></tr><tr><td>B75</td><td>PETn14</td><td>A75</td><td>GND</td></tr><tr><td>B76</td><td>GND</td><td>A76</td><td>PERp14</td></tr><tr><td>B77</td><td>GND</td><td>A77</td><td>PERn14</td></tr></table>

<table><tr><td>B80</td><td>GND</td><td>A80</td><td>PERp15</td></tr><tr><td>B81</td><td>PRSNT</td><td>A81</td><td>PERn15</td></tr><tr><td>B82</td><td>RSVD</td><td>A82</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.6. PCIe x4 Connector

PCIE0\_3: PCIe Gen4 x4 slot, PCIE lanes 0 to 3 assigned PCIe slot

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

![The image displays a long, horizontal grey rectangular object, resembling a server chassis or a large battery unit, set against a white background. The front face is black and features three rows of vertical black slats or vents. A vertical divider separates these slats into left and right sections. On the far left edge, there is a protruding grey rectangular panel, and on the far right edge, near the bottom, is a small light-colored circular detail.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/c4f30a8b07ce43af17586f8bbe01501a138e4bd47577c491efe99927ed671144.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.7. PCIe x1 Connector

PCIE4: PCIe Gen3 x1 slot, PCIe lane 4 assigned PCIe slot PCIE5: PCIe Gen3 x1 slot, PCIe lane 5 assigned PCIe slot PCIE6: PCIe Gen3 x1 slot, PCIe lane 6 assigned PCIe slot PCIE7: PCIe Gen3 x1 slot, PCIe lane 7 assigned PCIe slot

![The image displays a schematic representation of a computer memory module (RAM). It features a grey rectangular base with two large black rectangular areas resembling chips, filled with vertical parallel lines. Green rectangular contacts are visible along the left edge, right edge, and top edge. There is no text visible in the image.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/e3251dbee1025fd89c33f347b8b2386fd585a8f4dbb9d3b7b419601e469eaf22.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.8. USB2.0 Port Header

F\_2XUSB: HUB USB2.0 Port 2 and Port 3 header

<table><tr><td>Pin</td><td>Signal</td><td></td><td></td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+5V</td></tr><tr><td>3</td><td>HUB1_USB7_N2</td><td>4</td><td>HUB1_USB7_N3</td></tr><tr><td>5</td><td>HUB1_USB7_P2</td><td>6</td><td>HUB1_USB7_P3</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image displays five stacked, light grey, rounded rectangular shapes, resembling buttons. Each shape contains three numbers separated by spaces. The text reads from top to bottom:\n\n2 0 1\n4 0 3\n6 0 5\n8 0 7\n10 0 9](.express-base6-r3-1-manual-50m-77107-1000-02-231228/b894f594337152d252af0dd7b33851f84ad2ea2621760d53981b151b5edee917.jpg)

# 6.9. Audio Header

F\_AUD: AUDIO Front Panel header

<table><tr><td></td><td></td><td></td><td></td></tr><tr><td>1</td><td>MIC2_L_HD</td><td>2</td><td>AGND_AU</td></tr><tr><td>3</td><td>MIC2_R_HD</td><td>4</td><td>PRESENCE</td></tr><tr><td>5</td><td>LINE2_R_HD</td><td>6</td><td>MIC2_JD</td></tr><tr><td>7</td><td>AGND_AU</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>LINE2_L_HD</td><td>10</td><td>LINE2_JD</td></tr></table>

![The image displays a phone keypad interface with white, rectangular buttons containing black numbers. The buttons are arranged in a grid with three columns.\n\nThe rows display the following numbers:\n*   Top row: 1, 2, 3\n*   Second row: 4, 5, 6\n*   Third row: 7, 8, 9\n*   Bottom row: 0, 10\n\nThe button labeled '0' is highlighted with a black border. The button labeled '10' is located in the bottom right corner. All other buttons are white.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/4cf5f37176b0c24e51201aba4ac725fd40609e89e00b25c3fd91bad7f6a32650.jpg)

# 6.10. SATA Port

SATA\_0/SATA\_1/SATA\_2/SATA\_3: Serial ATA port

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX_P</td></tr><tr><td>3</td><td>TX_N</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX_P</td></tr><tr><td>6</td><td>RX_N</td></tr><tr><td>7</td><td>SATA0_P7</td></tr></table>

![The image displays a grayscale icon of a rectangular electronic device, resembling a computer tower or rack-mounted equipment. Inside the main rectangular border, the upper section features a white circle on the left, a black rectangle in the center, and another white circle on the right. The lower section consists of a horizontal row of seven vertical rectangular slots or vents.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6aba29348cecc5c1cf1d7332322dbdce79d8d286e0e8e8ee39270a0601e72645.jpg)

SATA\_PWR: Voltage supply 12V and 5V to HDD device.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P12V</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>P5V</td></tr></table>

![The image displays a schematic diagram of a connector housing on the left, featuring four circular pin positions arranged in a vertical column. To the right of the housing is a vertical list of numbers labeled 1, 2, 3, and 4, which correspond respectively to the top, second, third, and bottom pin positions.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/9cafe42c71b06615bb654d40308e0be6746d83168a5d94b7ef64b1cebdf830bf.jpg)

# 6.11. LPC/ eSPI Debug Header

LPC\_eSPI: for LPC/ eSPI debugging connection purposes

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CLK_DEBUG</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>LPC_FRAMEJ / ESPI CS0#</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>RST_DBG</td><td>6</td><td>+5V</td></tr><tr><td>7</td><td>eSPI_IO_3 / LPC_AD3</td><td>8</td><td>LPC_AD2/ eSPI_IO_1</td></tr><tr><td>9</td><td>+ 3.3VSB</td><td>10</td><td>LPC_AD1/ eSPI_IO_1</td></tr><tr><td>11</td><td>LPC_AD0/eSPI_IO_0</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>SMB_CK</td><td>14</td><td>SMB_DAT</td></tr><tr><td>15</td><td>1V8SB</td><td>16</td><td>NC</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>LPC_SERIRQ / eSPI_CS1#</td></tr><tr><td>19</td><td>LPC_DRQ0J /eSPI_ALEART0#</td><td>20</td><td>LPC_DRQ1J /eSPI_ALEART1#</td></tr></table>

![This image displays a diagram featuring a central column of ten gray, rounded rectangular buttons, each containing a white square outline. Flanking this central column are two columns of numbers.\n\nThe left column lists the even numbers: 2, 4, 6, 8, 10, 12, 14, 16, 18, 20.\nThe right column lists the odd numbers: 1, 3, 5, 7, 9, 11, 13, 15, 17, 19.\n\nEach pair of numbers corresponds to a row with a button in the center.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/970b52c00900b07b598f12ba0c20de9fb64d5190a2dc7bf058c3d23afea8daf2.jpg)

# 6.12. PS2 Header

KB\_MS: PS2 function from SIO6126D

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>KBVCC (5V)</td><td>2</td><td>KBVCC (5V)</td></tr><tr><td>3</td><td>MSDAT</td><td>4</td><td>KBDAT</td></tr><tr><td>5</td><td>MSCLK</td><td>6</td><td>KBCLK</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr></table>

![The image displays a grid of eight numbered buttons arranged in four rows and two columns. To the left of each button is a black number. The numbers are 1, 2, 3, 4, 5, 6, 7, and 8. Each button is a grey rectangle with rounded corners and contains two small horizontal ovals. The button next to the number 1 is distinct, featuring a square shape inside the top oval instead of a second oval.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6906fc180f2d48980c20d585dab5b34459884714b50b769fd55fa3a6c391e281.jpg)

# 6.13. COM Port Connector

COM1: Module UART port 1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>SER1_RX_R</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>SER1_TX_R</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image displays a sequence of numbers flanking a central black rectangle. On the left, the odd numbers 1, 3, 5, 7, 9 are stacked vertically. In the center, a black rectangle contains six white dots arranged in two columns of three. On the right, the even numbers 2, 4, 6, 8, 10 are stacked vertically.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ae119da9a7b03db30e6ec43880fab29d7fd33adcc6c6095b4d7b18b20f4a7171.jpg)

COM2: Module UART port 0

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>SER1_RX_R</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>SER1_TX_R</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image features a vertical column of the numbers '1 3 5 7 9' on the left. Next to it is a black square containing five white dots arranged in a quincunx pattern. To its right is a second black square with five identical white dots. Finally, a vertical column of the numbers '2 4 6 8 10' is on the far right.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/44a20dd59082916f0f23b55e0abd7b458d4253ff187e873ea65dbde23c5b5ce7.jpg)

COM3: SIONCT6126D UART port B

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CM2_DCD</td><td>2</td><td>CM2_DSR</td></tr><tr><td>3</td><td>CM2_RXD</td><td>4</td><td>CM2_RTS</td></tr><tr><td>5</td><td>CM2_TXD</td><td>6</td><td>CM2_CTS</td></tr><tr><td>7</td><td>CM2_DTR</td><td>8</td><td>CM2_RI</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image displays numbers arranged in two vertical columns on a white background, flanking a central black rectangle. On the left, the numbers 1, 3, 5, 7, and 9 are listed vertically. On the right, the numbers 2, 4, 6, 8, and 10 are listed vertically. Inside the central black rectangle, nine white dots are arranged in a three-by-three grid.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/7faccf7aa7b9b0bcb2e5461ade4d691054356c1fe5d374d597ecaf9001b0f9c6.jpg)

VGA\_COM4: SIONCT6126D UART port A, D-SUB9 connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CM1_DCD</td><td>2</td><td>CM1_RXD</td></tr><tr><td>3</td><td>CM1_TXD</td><td>4</td><td>CM1_DTR</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>CM1_DSR</td></tr><tr><td>7</td><td>CM1_RTS</td><td>8</td><td>CM1_CTS</td></tr><tr><td>9</td><td>RI</td><td></td><td></td></tr></table>

![The image shows a schematic diagram of a DB9 connector. It depicts a rectangular metal housing with two screw holes on the left and right sides. In the center is a recessed area containing two rows of pins: a top row with five pins and a bottom row with four pins.\n\nText labels with vertical lines identify specific pin locations:\n*   **Pin 1** points to the top-left pin.\n*   **Pin 5** points to the top-right pin.\n*   **Pin 6** points to the bottom-left pin.\n*   **Pin 9** points to the bottom-right pin.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/84b50c029a87079ebc9bc2a47982eb87a0882e2acaeb8cd0334701edc4d7cc24.jpg)

# 6.14. VGA Connector

SMBUS\_GPIO: BASE6 GPIO expander output GPIO 0:3

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>RED</td><td>2</td><td>GREEN</td></tr><tr><td>3</td><td>BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>NC</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>DDC POWER</td><td>12</td><td>DDC2B DATA</td></tr><tr><td>13</td><td>HSYNC</td><td>14</td><td>VSYNC</td></tr><tr><td>15</td><td>DDC2B CLOCK</td><td></td><td></td></tr></table>

![The image displays a schematic line drawing of a DE-9 connector (D-sub 9-pin). It features a central rectangular housing with a 3x3 grid of nine circular pins. Flanking the connector on the far left and right are two circular mounting holes.\n\nRed numbers are positioned outside the connector to indicate pin assignments:\n*   On the left side, the numbers **5**, **10**, and **15** are stacked vertically.\n*   On the right side, the numbers **1**, **6**, and **11** are stacked vertically.\n\nSmall vertical lines extend downward from the bottom edge of the connector, representing mounting feet or leads.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ceb87f6c354af3836ca866123f0f656916d8d64e72ddcce558275341973c0a78.jpg)

# 6.15 Audio Phone Jack

Audio: 3-port Audio Phone jack

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>BLUE</td><td>Line-In</td></tr><tr><td>GREEN</td><td>Line-Out</td></tr><tr><td>PICK</td><td>MIC-In</td></tr></table>

![The image displays a vertical line drawing of a rectangular panel featuring three circular vents with horizontal slats and central hubs, stacked vertically. Next to the top vent, the text 'BLUE' appears in blue. Below that is a small circle, followed by a second vent with the text 'GREEN' in green to its right. Below the second vent is a third vent with the text 'PICK' in pink to its right. The bottom of the panel features a series of vertical slats.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/1464de8c2e6731e782a91fa0bae26c0969dbc0a4cd16d2b4433e2b4ef4292844.jpg)

# 6.16 LAN and USB 3.2 Gen 2

LAN\_USB\_2\_3: 1x General purpose LAN (up to 2.5G)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>BI_DA+</td></tr><tr><td>2</td><td>BI_DA-</td></tr><tr><td>3</td><td>BI_DB+</td></tr><tr><td>4</td><td>BI_DC+</td></tr><tr><td>5</td><td>BI_DC-</td></tr><tr><td>6</td><td>BI_DB-</td></tr><tr><td>7</td><td>BI_DD+</td></tr><tr><td>8</td><td>BI_DD-</td></tr></table>

![INDICATOR\nGREEN/ORANGE\nINDICATOR\nYELLOW\n8\n1](.express-base6-r3-1-manual-50m-77107-1000-02-231228/fb94eb1a4f8aba434394f5c82955c131968a57b2d1f1dec3e945373c3b829205.jpg)

LAN\_USB\_2\_3: 2x USB3.2 Gen2

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>USB3.0_PV5A</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![The image displays a technical line drawing of a rectangular connector housing. It features two rows of terminal slots labeled with numbers. The top row contains the numbers 9, 8, 7, 6, and 5 arranged horizontally from left to right. The bottom row contains the numbers 1, 2, 3, and 4 arranged horizontally from left to right. Small rectangular tabs are visible on the top and bottom edges of the housing.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/8470f2722aa4deaad892112297e5785de9355ec08bf5544380d6a1290199dab0.jpg)

# 6.17 USB Connector

USB\_4\_5: USB connector supporting USB 2.0 signal

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td></tr><tr><td>2</td><td>USB-</td></tr><tr><td>3</td><td>USB+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.express-base6-r3-1-manual-50m-77107-1000-02-231228/e9ed6d0703f40bd5f63826803d97ebc70956dfcf0b7d0db2b3171ebce5290ca3.jpg)

USB\_0\_1: USB connector supporting USB 3.2 Gen2 signal

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VBUS</td></tr><tr><td>2</td><td>USB-</td></tr><tr><td>3</td><td>USB+</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>SSRX-</td></tr><tr><td>6</td><td>SSRX+</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>SSTX-</td></tr><tr><td>9</td><td>SSTX+</td></tr></table>

![Technical line drawing of a dual-chamber electronic connector (no text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/70d41dc57b2681f8a26721d9e1909faacfc35daef898d028aca21fe4b4dc6782.jpg)

USB4\_1/USB4\_2: USB Type C connector supporting USB 3.2 Gen2 x2 signal

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>A1</td><td>VBUS</td><td>B1</td><td>GND</td></tr><tr><td>A2</td><td>TX+</td><td>B2</td><td>TX2+</td></tr><tr><td>A3</td><td>TX-</td><td>B3</td><td>TX2-</td></tr><tr><td>A4</td><td>VBUS</td><td>B4</td><td>VBUS</td></tr><tr><td>A5</td><td>CC1</td><td>B5</td><td>VCONN</td></tr><tr><td>A6</td><td>D+</td><td>B6</td><td>NC</td></tr><tr><td>A7</td><td>D-</td><td>B7</td><td>NC</td></tr><tr><td>A8</td><td>SUB1</td><td>B8</td><td>SUB2</td></tr><tr><td>A9</td><td>VBUS</td><td>B9</td><td>VBUS</td></tr><tr><td>A10</td><td>RX2-</td><td>B10</td><td>RX1-</td></tr><tr><td>A11</td><td>RX2+</td><td>B11</td><td>RX1+</td></tr><tr><td>A12</td><td>GND</td><td>B12</td><td>GND</td></tr></table>

![A1\nA12\nB12\nB1](.express-base6-r3-1-manual-50m-77107-1000-02-231228/63901c54c2effbbc1f0c730601f3bbf7956798511b4141d67163850d25e57cce.jpg)

# 6.18 DP connector

DP\_DDI3: DP connector that uses DDI signal from module

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>Lane0+</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>Lane0-</td><td>4</td><td>Lane1+</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>Lane1-</td></tr><tr><td>7</td><td>Lane2+</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>Lane21</td><td>10</td><td>Lane3+</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>Lane3-</td></tr><tr><td>13</td><td>CONFIG1</td><td>14</td><td>CONFIG2</td></tr><tr><td>15</td><td>AUX CH+</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>AUX CH-</td><td>18</td><td>Hot Plug</td></tr><tr><td>19</td><td>Return</td><td>20</td><td>DP_PWR</td></tr></table>

![19 17 15 13 11 9 7 5 3 1\n20 18 16 14 12 10 8 6 4 2](.express-base6-r3-1-manual-50m-77107-1000-02-231228/93e42f242dc2466f32b92fa1f4308ac34ec0ef0c6819609e018028419023dcc5.jpg)

# 6.19 BASE6 GPIO Expander Header

SMBUS\_GPIO: BASE6 GPIO expander outputs, GPIO 0 to 3

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>BASE_GPI0</td><td>2</td><td>BASE_GPO0</td></tr><tr><td>3</td><td>BASE_GPI1</td><td>4</td><td>BASE_GPO1</td></tr><tr><td>5</td><td>BASE_GPI2</td><td>6</td><td>BASE_GPO2</td></tr><tr><td>7</td><td>BASE_GPI3</td><td>8</td><td>BASE_GPO3</td></tr></table>

![This image displays four gray, rounded rectangles stacked vertically. Each rectangle features two small gray circles. Flanking the rectangles are numbers: 1, 3, 5, and 7 on the left, and 2, 4, 6, and 8 on the right. The top rectangle uniquely features a small black square on its left side.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/d0bdc1fd62e08550ca0b7ce66dc95a7b6d3b55a76f6ec41db4985599a5d8de67.jpg)

# 6.20. GPIO Header

Module GPIO: Module output GPIO Header;

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>MUX_GPI0</td><td>2</td><td>MUX_GPO0</td></tr><tr><td>3</td><td>MUX_GPI1</td><td>4</td><td>MUX_GPO1</td></tr><tr><td>5</td><td>MUX_GPI2</td><td>6</td><td>MUX_GPO2</td></tr><tr><td>7</td><td>MUX_GPI3</td><td>8</td><td>MUX_GPO3</td></tr></table>

![The image displays numbers 1 through 8 arranged in a grid of four rows and two columns. To the right of each number is a grey, rounded rectangular icon. The icon next to the number 1 contains a small black square. The icons next to numbers 2, 3, 4, 5, 6, 7, and 8 each contain two small grey circles.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/4e1c47ec3d41a73421f07d7a3328785377258c4e3a1e7148afdf271bc4aa7b42.jpg)

# 6.21. SMBus Header

SMBus: additional SMBus from module

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P3V3_SM</td></tr><tr><td>2</td><td>SMB_DAT_O</td></tr><tr><td>3</td><td>SMB_CLK_O</td></tr><tr><td>4</td><td>GND</td></tr></table>

![The image displays a vertical list with the numbers 1, 2, 3, and 4. To the right of each number is a stack of three circular icons. Next to the number 1, the top circle has a dark center, while the middle and bottom circles have light gray centers. Next to numbers 2, 3, and 4, all three circles in each stack have light gray centers.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6eceb57511e317435c8d8804e1f977ceae64f5ade1f259e09609be9a2434a867.jpg)

# 6.22. I2C Header

I2C: additional I2C from module

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P3V3_I2C</td></tr><tr><td>2</td><td>I2C_DAT_O</td></tr><tr><td>3</td><td>I2C_CLK_O</td></tr><tr><td>4</td><td>GND</td></tr></table>

![The image displays a vertical list of four rows. On the left side, the numbers **1**, **2**, **3**, and **4** appear in black text. To the right of each number is a grey circular button. The top button (next to number 1) contains a white square with a black square inside. The buttons next to numbers 2, 3, and 4 contain a white square with a light grey square inside.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ac8b438756f467e83953399fb3d5ee7743a5ab5a54a80e1bae6de8c0a8288c23.jpg)

# 6.23. Fan Header

FAN\_COMe: Module-controlled Fan

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image displays a vertical column of the numbers 1, 2, 3, and 4 on the left side. To the right of these numbers is a large rectangular outline. Inside this large rectangle, there is a narrower vertical rectangle on the left side which is divided near the bottom by a horizontal line. To the right of this inner rectangle are four small squares arranged in a vertical column.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/acfb0bcda98e255fd67a646f20c4995b989375b5df574871e43f01d6abfc045e.jpg)

FAN\_1: SIO6126D-controlled FAN 1

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image displays a vertical list of the numbers 1, 2, 3, and 4 aligned on the left side. Next to these numbers is a tall, empty rectangular outline. To the right of this rectangle is a column of four small, empty square outlines.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6174206a610379e5cfda8eb32cd62b5dc8b8faee2c328ed10db83c20e0b8f7e9.jpg)

FAN\_2: SIO6126D-controlled FAN 2

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image displays a black-and-white line drawing resembling a schematic or floor plan. On the far left, the numbers 1, 2, 3, and 4 are stacked vertically. To the right of the numbers is a thin vertical strip. Next to that is a rectangular section divided horizontally into two parts. To the right of that is another thin vertical strip. On the far right is a larger section containing a vertical column of five small squares.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/7700a35a8876d987d0349af9095875b69d4db4c9ae7cf50ce295d57f04eaae00.jpg)

# 6.24. General Purpose SPI Header

GP\_SPI: General Purpose SPI

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>GP_SPI_CS0#</td><td>4</td><td>SPI0_DIN</td></tr><tr><td>5</td><td>NC</td><td>6</td><td>SPI0_CLK</td></tr><tr><td>7</td><td>SPI0_DO</td><td>8</td><td>GND</td></tr></table>

![The image displays a section of an elevator control panel featuring four rows of elements against a white background.\n\n*   **Top Row:** The number **1** is on the left, a grey square button with a smaller square outline inside is in the center, and the number **2** is on the right.\n*   **Second Row:** The number **3** is on the left, a grey rounded rectangular button with a small circle in the center is in the middle, and the number **4** is on the right.\n*   **Third Row:** The number **5** is on the left, a grey rounded rectangular button with a small circle in the center is in the middle, and the number **6** is on the right.\n*   **Fourth Row:** The number **7** is on the left, a grey rounded rectangular button with a small circle in the center is in the middle, and the number **8** is on the right.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/96625946495b52135e373caaa361ac2ffdd7b513855b9d8d1fc7516bd170b70e.jpg)

# 6.25. Front Panel Control

FRONT\_PANEL: Power Button, Reset Button, HDD LED, Power LED for front panel header

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>5VSB</td><td>2</td><td>PWR_LED_P</td></tr><tr><td>3</td><td>UID_LED_N</td><td>4</td><td>FAN_FAIL_LED_N</td></tr><tr><td>5</td><td>UID_LED_P</td><td>6</td><td>PWR_LED_N</td></tr><tr><td>7</td><td>SLED_G</td><td>8</td><td>HDD_LED_P</td></tr><tr><td>9</td><td>SLED_R</td><td>10</td><td>HDD_LED_N</td></tr><tr><td>11</td><td>LAN1_LED_P</td><td>12</td><td>PWR_BUT_P</td></tr><tr><td>13</td><td>LAN1_LED_N</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>SENSOR_SDA</td><td>16</td><td>RST_BUT_P</td></tr><tr><td>17</td><td>SENSOR_SCL</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>CASE_OPEN_N</td><td>20</td><td>R_UID_BUT_P</td></tr><tr><td>21</td><td>LAN2_LED_P</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>LAN2_LED_N</td><td>24</td><td>NMI_SW</td></tr></table>

![The image displays a vertical column of twelve grey, pill-shaped objects. Flanking this column are two lists of numbers. On the left side, the even numbers 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, and 24 are arranged in ascending order from top to bottom. On the right side, the odd numbers 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, and 23 are arranged in ascending order from top to bottom. The topmost grey object contains a small black square, while the remaining eleven objects each contain two small white circles resembling eyes.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/8a5f141e148debb21df022ee93517c6d39c3a0fd738bf882a453c1e06d0a3ee2.jpg)

# 6.26. Panel Connector

LVDS panel connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>LVSD_I2C_DAT</td><td>2</td><td>LVSD_I2C_CK</td></tr><tr><td>3</td><td>N.C</td><td>4</td><td>N.C</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>LVDS_A0-</td></tr><tr><td>7</td><td>LVDS_A0+</td><td>8</td><td>LVSD_VDD_EN</td></tr><tr><td>9</td><td>LVDS_A1-</td><td>10</td><td>LVDS_A1+</td></tr><tr><td>11</td><td>LVSD_BKLT_EN</td><td>12</td><td>LVDS_A2+</td></tr><tr><td>13</td><td>LVDS_A2-</td><td>14</td><td>N.C</td></tr><tr><td>15</td><td>LVDS_A_CK-</td><td>16</td><td>LVDS_A_CK+</td></tr><tr><td>17</td><td>N.C</td><td>18</td><td>LVDS_A3+</td></tr><tr><td>19</td><td>LVDS_A3-</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>LVDS_B0-</td><td>22</td><td>LVDS_B0+</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>LVDS_B1-</td></tr><tr><td>25</td><td>LVDS_B1+</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>LVDS_B2-</td><td>28</td><td>LVDS_B2+</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>LVDS_B_CK+</td></tr><tr><td>31</td><td>LVDS_B_CK-</td><td>32</td><td>N.C</td></tr><tr><td>33</td><td>LVDS_B3+</td><td>34</td><td>LVDS_B3-</td></tr></table>

![The image displays a vertical rectangular diagram. The left side is a black rectangle containing a vertical column of white dots, while the right side is a white rectangle. The corners are labeled with the numbers '1' (top left), '2' (top right), '33' (bottom left), and '34' (bottom right).](.express-base6-r3-1-manual-50m-77107-1000-02-231228/edab9d2128d7b81d900d3f30009aced1600c8d5f18b32334b4946b9ec3735601.jpg)

Smart Battery Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>Panel PWR</td></tr><tr><td>3</td><td>Backlight CTRL</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>Backlight Enable</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>Backlight PWR</td></tr></table>

![The image displays a vertical black rectangle containing a grid of white dots. The dots are arranged in three columns and four rows. The left and right columns each contain four dots. The middle column contains three dots, leaving the bottom position empty. To the right of the black rectangle, the numbers 1, 2, 7, and 8 are stacked vertically in white text.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/e506eed4ed3621393a0be73e0babd79f875d01e93481963ab0ba76bfe7c6cb5f.jpg)

# 6.27. Battery Connector

Smart Battery connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>I2C_CK</td><td>2</td><td>I2C_DAT</td></tr><tr><td>3</td><td>PWRBTN#</td><td>4</td><td>BATLOW#</td></tr><tr><td>5</td><td>PS_ON#</td><td>6</td><td>SUS_S45#</td></tr><tr><td>7</td><td>+12V</td><td>8</td><td>+5VSB</td></tr><tr><td>9</td><td>SUS_STAT#</td><td>10</td><td>GND</td></tr></table>

![The image displays a dark, vertical rectangle resembling a card or connector faceplate. In the corners, white numbers serve as labels: '1' is at the top left, '2' is at the top right, '9' is at the bottom left, and '10' is at the bottom right. Inside the rectangle, there is a pattern of eight white dots arranged in two vertical columns of four dots each. A faint, thin vertical white line is visible on the left side within the dark rectangle.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6ada1b3a19fb7c9e0c0f916d0b8b7f0fd35a0de6ab9f1ce5fb7d16013e9a9518.jpg)

# 6.28. Power Connectors

# ATX\_24: ATX 24-pin Power Connector

Connect the ATX 24-pin (or 20-pin) connector to supply power to the COM Express Base R3.1 carrier.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>13</td><td>+3.3V</td></tr><tr><td>2</td><td>+3.3V</td><td>14</td><td>-12V</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>COM</td></tr><tr><td>4</td><td>+5V</td><td>16</td><td>PWR_ON</td></tr><tr><td>5</td><td>GND</td><td>17</td><td>COM</td></tr><tr><td>6</td><td>+5V</td><td>18</td><td>COM</td></tr><tr><td>7</td><td>GND</td><td>19</td><td>COM</td></tr><tr><td>8</td><td>PWR_GOOD</td><td>20</td><td>-5V</td></tr><tr><td>9</td><td>+5VSB</td><td>21</td><td>+5V</td></tr><tr><td>10</td><td>+12V</td><td>22</td><td>+5V</td></tr><tr><td>11</td><td>+12V</td><td>23</td><td>+5V</td></tr><tr><td>12</td><td>+3.3V</td><td>24</td><td>COM</td></tr></table>

![| Power Supply | Pin Number |\n| ------------ | ---------- |\n| +3.3 V       | 13         |\n| -12 V        | 14         |\n| COM          | 15         |\n| PWR_ON       | 16         |\n| COM          | 17         |\n| COM          | 18         |\n| COM          | 19         |\n| -5 V         | 20         |\n| +5 V         | 21         |\n| +5 V         | 22         |\n| +5 V         | 23         |\n| COM          | 24         |](.express-base6-r3-1-manual-50m-77107-1000-02-231228/1fac6607154fa2b244cef063a1da2f56e706c0da3882dc8969165fd67033590e.jpg)

# ATX\_4: ATX 12V 4-pin Connector.

Connect the ATX 12V 4-pin connector to supply power to the COM Express Base R3.1 carrier

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>+12V</td></tr><tr><td>4</td><td>+12V</td></tr></table>

![The image displays a square divided into four quadrants.\n- **Top-left:** A shape resembling a square with a semi-circle cut out from its right side.\n- **Top-right:** A square.\n- **Bottom-left:** A square.\n- **Bottom-right:** A shape resembling a square with a semi-circle cut out from its left side.\n\nSurrounding the square are numbers and a bracket:\n- **Left side:** The number **2** is aligned with the top row, and the number **1** is aligned with the bottom row.\n- **Right side:** The number **4** is aligned with the top row, and the number **3** is aligned with the bottom row. A vertical bracket is positioned next to the numbers 4 and 3.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/341a00a85e4f07961b58575fa1885ac23465271b6e4f9334968ea3169c14af8f.jpg)

# 6.29. Carrier EEPROM Address Switch

SW1: COM Express BASE6 R3.1 carrier board EEPROM address setting

Default Address: AEh

<table><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>A2</td><td>A1</td><td>A0</td><td>R/W</td></tr><tr><td colspan="8">MSB LSB</td></tr></table>

<table><tr><td>SW1</td><td>I2C EEPROM_U53</td></tr><tr><td>1-8</td><td>A2_OFF</td></tr><tr><td>2-7</td><td>A1_OFF</td></tr><tr><td>3-6</td><td>A0_OFF</td></tr></table>

![The image shows a black rectangular 4-position DIP switch. White text at the top reads 'ON DIP'. Below this are four vertical toggle switches with white rectangular knobs. The knobs for switches 1, 2, and 3 are in the up position, while the knob for switch 4 is in the down position. At the bottom, the numbers '1 2 3 4' are printed in white, aligned beneath each corresponding switch.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ce364779253253b79eaf23ef4b95bbd9547acaeea38dee3dc88a224563a58384.jpg)

# 6.30. Other Jumpers

JP33: Switching Module, GPIO or SDIO signal workable

<table><tr><td>JP33</td><td>Status</td></tr><tr><td>1-2</td><td>SD_CARD workable (default)</td></tr><tr><td>2-3</td><td>Module GPIO header workable</td></tr></table>

![The image displays the numbers 1, 2, and 3 arranged vertically on the left side. To the right of each number is a corresponding section of a vertical rectangular bar:\n*   **1:** A black section containing two small white dots.\n*   **2:** A white section containing two small black dots.\n*   **3:** A grey section containing a single black square.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/01890c79e4e8d06721eb34d7e89c652fd5d9098dac1d877c934d5cdf897a1e61.jpg)

JP3: SIO I/O address

<table><tr><td>JP3</td><td>Status</td></tr><tr><td>1-2</td><td>4Eh</td></tr><tr><td>2-3</td><td>2Eh (default)</td></tr></table>

![The image displays a vertical list with the numbers 1, 2, and 3 aligned on the left side in black text. To the right is a vertical bar. The top portion of the bar is a grey rounded rectangle containing a small white square with a black border. The remainder of the bar is black and contains two white dots aligned vertically. The number 1 aligns with the grey section, number 2 aligns with the upper dot, and number 3 aligns with the lower dot.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/db6870dde8c553da6256023b55c5a9efbb75d3adf900591bc215dcd7bc6347fc.jpg)

JP6/JP7: BIOS select

<table><tr><td>JP6</td><td>JP7</td><td>Status</td></tr><tr><td>1-2</td><td>1-2</td><td>Module SPI (default)</td></tr><tr><td>2-3</td><td>1-2</td><td>Carrier FWH</td></tr><tr><td>1-2</td><td>2-3</td><td>Carrier SPI0</td></tr><tr><td>2-3</td><td>2-3</td><td>Carrier SPI1</td></tr></table>

![The image displays three horizontal rows. Each row features a number on the far left, a vertical rectangular graphic in the center, and a number on the far right. The numbers are 1, 2, and 3 from top to bottom. The central graphic is a vertical bar divided vertically into a black left section and a white right section. The black section contains three small white dots arranged vertically. The bottom of the black section is a grey semi-circle containing a small black dot. The numbers are black digits.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/80a1f53c017c875c52a4e066a7c63052985d5ebbb7f7fccda45a915442f6e55a.jpg)

JP27: LVDS Backlight enabler

<table><tr><td>JP27</td><td>Status</td></tr><tr><td>1-2</td><td>Low Active</td></tr><tr><td>2-3</td><td>High Active (default)</td></tr></table>

![The image features the numbers 1, 2, and 3 stacked vertically on the left side. To their right is a vertical rectangular bar divided into three sections. The top section, corresponding to the number 1, is a grey shape with a rounded top containing a small white square. The middle section, corresponding to the number 2, is a black rectangle with a centered white dot. The bottom section, corresponding to the number 3, is a black rectangle with a centered white dot.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/367b3207cc06a58d20316a8455774dc4e3daf8ebdefdea1feb33f3004a548b22.jpg)

JP34: LVDS Backlight PWM control source

<table><tr><td>JP34</td><td>Status</td></tr><tr><td>1-2</td><td>GPU</td></tr><tr><td>2-3</td><td>LVDS I2C (default)</td></tr></table>

![The image displays a vertical column of the numbers '1', '2', and '3' on the left side. To the right is a vertical, pill-shaped object. The top portion is light grey and rounded, featuring a small white square outline. The bottom portion is black and rectangular, containing three white dots arranged in a vertical line.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/5f268e234b0c41869374ec657af7aca983ffd1b518dd2d1a31e45258ec1a61c1.jpg)

JP35: LVDS Backlight control mode

<table><tr><td>JP35</td><td>Status</td></tr><tr><td>1-2</td><td>Voltage level</td></tr><tr><td>2-3</td><td>PWM (default)</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically in black text on the left side. To the right is a vertical rectangular graphic resembling a test strip with a rounded top. The top portion of the strip is light grey and features a small square outline at the very top center. The remainder of the strip is black and contains two white dots arranged vertically inside it.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/95c1554ca2629d9d7c6f52de43dcb4018657d8864ac45eceb55c6c034d00da5c.jpg)

JP28: LVDS panel power

<table><tr><td>JP28</td><td>Status</td></tr><tr><td>1-2</td><td>3.3V (default)</td></tr><tr><td>2-3</td><td>5V</td></tr></table>

![The image displays the numbers '1', '2', and '3' stacked vertically in black font on the left side. To the right is a rectangular strip divided into two sections. The upper section is black and contains two small white dots arranged vertically. The lower section is grey with a rounded bottom and contains a single white circle.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/3e626b8452a3c0e8fbd83c983b3db8fbd4f80eca040bc7bea5d9869e0de441b6.jpg)

JP29: LVDS Panel Backlight power

<table><tr><td>JP29</td><td>Status</td></tr><tr><td>1-2</td><td>12V</td></tr><tr><td>2-3</td><td>5V (default)</td></tr></table>

![The image displays the numbers 1, 2, and 3 arranged vertically on the left side. To the right is a vertical rectangular shape resembling a battery icon. The top portion of this shape is grey and features a small rectangular cutout at the very top center. The lower portion is black and contains two small white dots arranged vertically. The number 1 aligns with the top edge of the black section, the number 2 aligns with the upper dot, and the number 3 aligns with the lower dot.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/164fbf08216f32880d8db87f9175a8d7b131f5209270e4e9ce41b333e49c2b55.jpg)

JP31: Carrier Power mode

<table><tr><td>JP31</td><td>Status</td></tr><tr><td>1-2</td><td>ATX mode (default)</td></tr><tr><td>2-3</td><td>AT mode</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically in black text on the left side. To the right of these numbers is a vertical rectangular column. The top portion of this column is black, and the bottom portion is grey. Inside the column, aligned with each number, is a small white square. The top two white squares (next to 1 and 2) are set against the black background and contain a small black dot. The bottom white square (next to 3) is set against the grey background and contains a small black square.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/6ea09a7ed5621b0eca979fab700a957559d2c84dd74ecb82c25a0b5eff9d7225.jpg)

JP32: VCC\_12V On/Off during S3/S5 (In AT mode, put pin 2-3 to output 12V during S3/S5.)

<table><tr><td>JP32</td><td>Status</td></tr><tr><td>1-2</td><td>ATX to Module (default)</td></tr><tr><td>2-3</td><td>AT to Module</td></tr></table>

![The image displays a vertical column of numbers **1**, **2**, and **3** on the left side. To the right is a vertical tube-like shape. The upper portion of the tube is black and contains three white dots arranged vertically. The lower portion is grey with a rounded bottom and contains a single white square.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/05643031c073b59ceb4b0011276651c391a8f93fe3ed748adbbbe79a08c4618e.jpg)

JP40: BIOS boot device select

<table><tr><td>JP32</td><td>Status</td></tr><tr><td>1-2</td><td>LPC Mode (default)</td></tr><tr><td>2-3</td><td>eSPI Mode</td></tr></table>

![The image displays the numbers 1, 2, and 3 arranged vertically on the left side. To their right is a vertical black rectangular bar. Inside the upper portion of the bar, three white dots are aligned vertically. At the bottom of the bar, there is a grey semi-circle containing a white square.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ad920266df05f8f678d38cb3622610a5cc7d60747e4b6a1cd54a4492475e828c.jpg)

JP41/JP42: BIOS boot device select

<table><tr><td>JP41</td><td>JP42</td><td>Status</td></tr><tr><td>1-2</td><td>2-3</td><td>RS-232 (default)</td></tr><tr><td>2-3</td><td>1-2</td><td>RS-485</td></tr><tr><td>1-2</td><td>1-2</td><td>RS-422</td></tr></table>

![The image displays two vertical columns of numbers, labeled 1, 2, and 3 in each column.\n\nTo the left of the numbers:\n- Next to **1**: A black rectangle containing a white dot near the top.\n- Next to **2**: A black rectangle containing a white dot in the center.\n- Next to **3**: A gray rectangle with a rounded top containing a white dot near the top.\n\nTo the right of the numbers:\n- Next to **1**: A gray rectangle with a rounded top containing a white dot near the top.\n- Next to **2**: A black rectangle containing a white dot near the bottom.\n- Next to **3**: A black rectangle containing a white dot near the top.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/b5276f227a9aa3deec360b0abf7da9015798b0492018f8cf9ba117db62f144d4.jpg)

JP43: SIO enabler

<table><tr><td>JP43</td><td>Status</td></tr><tr><td>1-2</td><td>Enable SIO (default)</td></tr><tr><td>2-3</td><td>Disable SIO</td></tr></table>

![The image features the numbers **1**, **2**, and **3** stacked vertically in white text on the left side. On the right side, there is a vertical rectangular shape. The upper part of this shape is black and contains three white dots arranged in a vertical column. The lower part is a grey, rounded section containing a small white square. The numbers align roughly with the corresponding features on the right: **1** with the top dot, **2** with the middle dot, and **3** with the bottom grey section.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/360169fe8f5d6d43fa781fcaeedb9e5d7d538a019a841e0ec3d0eacd0ba31056.jpg)

JP5: Clear CMOS

To clear CMOS, turn power off and short pins 2 and 3 (short VBT to ground)

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>Normal &lt;&lt;&lt;</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr></table>

![The image displays a vertical column of numbers on the left side: '1', '2', and '3'. To the right of these numbers is a vertical rectangular bar divided into three distinct sections. The top section, aligned with the number '1', is black with a single white dot in the center. The middle section, aligned with the number '2', is black with two white dots arranged vertically in the center. The bottom section, aligned with the number '3', is grey and features a white square outline containing a small white dot in its center.](.express-base6-r3-1-manual-50m-77107-1000-02-231228/fdea0f4e459a12f70819a35b85785a6bdc52133904b99710df75dfc579f92dfe.jpg)

# Secondary BIOS

The Express-BASE6 R3.1 carrier board supports Secondary BIOS for COM modules, using the Boot SPI (Serial Peripheral Interface).

Secondary BIOS solutions can be used as an alternative to the on-module BIOS and provide support for the following:

• Testing new BIOS versions
• Development of firmware modifications
• Recovery if soldered BIOS on module is corrupted

To use the BIOS on the module, short pins 1-2 on JP6, JP7, reference section 6.30

To use the BIOS on the carrier board, Short pins 2-3 on JP6, and keep pin 1-2 on JP7, reference section 6.30

Make sure that the secondary BIOS flash chip has been properly installed onto the Carrier BIOS socket before Boot BIOS adjusting.

![Close-up of a green printed circuit board with electronic components and connectors (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/4b3339bc0ea2fc948db2bdb9b057b84b093b25450100bea9736139dc27b34ed0.jpg)

# 8. Switches, POST, and LEDs

# 8.1. Switches (S0-S5)

There are two switches, at the center and lower-right of the carrier.

# PWR\_BTN

Indicates getting into S0 from S5 of the system.

![F_PANEL\nS3\n5VSB\nHDD\nPWR_ON\n160\nA18F\n72.00\n198F\nPWR_BTN\nF_2XUSB](.express-base6-r3-1-manual-50m-77107-1000-02-231228/8ac91047d7999a03e9f64ad863a13a8c89123871a27155308554dad93eff47f1.jpg)

# RST\_BTN

Indicates resetting of the system.

![RST_BTN\nJP5\nRTC](.express-base6-r3-1-manual-50m-77107-1000-02-231228/7b26e137c739f47544c1fb64a535d9c490497992a95e7e52958525a9b683ba6b.jpg)

# 8.2. POST and Inductor LEDs

An eSPI-based POST display is added for debugging.

The two 7-SEG LEDs show the actual POST data.

![Close-up of a green printed circuit board with two 8-pin LED indicators and a PWR_BTN sensor (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/186ed0c99437148dbb8ef54a89ee2d5bbdd2738b16b17a971a5890603ab66d1f.jpg)

A row of mini-LEDs below the POST display indicates the following:

S3: Indicates S3 status

5VSB: ATX power attached on standby or active

HDD: Indicates HDD activity

PWR\_ON: Indicates power on

![S3\n5VSB\nHDD\nPWR_ON\nF PANEL](.express-base6-r3-1-manual-50m-77107-1000-02-231228/3fc12f9f1cfc34208d798538aeefaace8bc18a4d0b565ee3d90425efed85b67f.jpg)

# 8.3. ATX Power Connectors

The COM Express Base6 R3.1 has one ATX 24-pin connector to supply power to the carrier board and one ATX 12V 4-pin connector to supply power to the COM module.

The system will not power on unless an ATX 12V 4-pin connector is connected.

If your power supply has a 24-pin ATX connector, then attach the connectors as shown.

![FAN_COMc\nPLOTECH 6 94V-0\n08065-TB-B2544\n22\nJP31 Power Mode Select\n1:2\nATX Mode\n2:3\nATI Mode\nATX_24\nJP32\nJP31\nCN33\nATX_4\nBA\n1 2](.express-base6-r3-1-manual-50m-77107-1000-02-231228/c0f621afb64f20b54756b96323b0a858888073417d6adfd7bcb351a4bfb04774.jpg)

If your power supply has a 24-pin ATX connector, then attach the connectors as shown.

![Close-up of a green printed circuit board with multiple colored cable connectors and electronic components (no visible text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/ae6ae325eec03d5b8c015b4b1d728c9dbef3592769b23d4796941b4475e2f925.jpg)

If your power supply has a 20-pin ATX connector, then attach the connectors as shown.

![Close-up of a green circuit board with multiple colored and black wires attached to its connectors (no visible text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/37f44d5484e2353a55537ecc624117a2ff7a816c316fd6e3143343e49a5dd5d8.jpg)

DO NOT plug the ATX 12V 4-pin connector into the ATX 24-pin power connector.

![Close-up of a green printed circuit board with multiple colored cable connectors and electronic components (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-02-231228/fe5ffe75f0d71447410f8766655c2e1c0534b3e6f28aebe737279e92a4755e33.jpg)
[🔗 Link to the original document](.express-base6-r3-1-manual-50m-77107-1000-02-231228/express-base6-r3-1-manual-50m-77107-1000-02-231228.pdf)