# Express BASE6 R3.1

User’s Guide

![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-10-231030/e8708977ca4cfe10e13bad53ac11c2d390b7d6dbac2bce0c32cefb8304c5ecd9.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2023-10-30</td><td>Chris Chang</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangular warning sign featuring a thick black border and a large black exclamation point in the center.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/9f5422a14291126cf63b9e512de18bd23693b047debfda34c6638c5697b872c0.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black outline of a wheeled refuse bin with a lid, overlaid with a large 'X'. Beneath this symbol is a solid black rectangular block.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/e09967282012d2fd9a0c3190386628a037d97adae0f05082df9457cd2fe0676a.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2023 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a red icon of a document page. It features a thick red border shaped like a sheet of paper with a folded bottom-right corner (a 'dog-ear'). Inside the border, there are two horizontal red lines centered horizontally, representing text.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/764b724f6e80eaada30e5ac97e3c9c77407746a389c2bcbc96aa7bd8a41c18c8.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image shows a standard warning symbol consisting of a yellow isosceles triangle pointing upward. Inside the triangle is a black exclamation point. The background is white.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/c46c828e10e5cd5bfff32daf919784b7827c2517ca21c752ff8d0357cf0e1ba4.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard red triangular warning sign featuring a white exclamation mark centered within it.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/10682a0143cdfb2d63bfad5a4ac9cc11dd0a3a31ba5918c3c43d1d734ba82c1f.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

1. Introduction .. .10
2. Special Features (Differences from R3.0 Carrier)..

2.1. One PCI Express Gen4 x16 slot + One x4 Slot.... ..12
2.2. Two USB4 Type-C connector.. ..12
2.3. Onboard Audio... ..12
2.4. Display ... ..12
2.5. SD Card... ..12

3. Component Location.... .13
4. Functional Diagram... .14
5. Mechanical Dimension.. .15
6. Connectors and Pinouts... .16

6.1. Carrier Board Signals — Type 6... ... 16
6.2. Connector Location and Pinout Compatibility... ..17
6.3. Carrier Board Design .. ... 18
6.4. COM Express R3.1 Type 6 Board-to-board Connectors ... ... 18
6.5. PCIe x16 Connectors.. ..22
6.6. PCIe x4 Connector .. ..23
6.7. PCIe x1 Connector .. ..24
6.8. USB2.0 Port Header... ..25
6.9. Audio Header .. ..25
6.10. SATA Port... ..26
6.11. LPC/ eSPI Debug Header .... ..27
6.12. PS2 Header... ... 27
6.13. COM Port Connector... ... 28
6.14. BASE6 GPIO Expander Header .. ..29
6.15. GPIO Header.. ..29
6.16. SMBus Header.. ..30
6.17. I2C Header.... ..30

6.18. Fan Header .... ..31
6.19. General Purpose SPI Header.... ..32
6.20. Front Panel Control.. ... 32
6.21. Panel Connector... ... 33
6.22. Battery Connector.. ..34
6.23. Power Connectors . ..34
6.24. Carrier EEPROM Address Switch . ..35
6.25. Other Jumpers.. ..36

7. Switches, POST, and LEDs.... ...39

7.1. Switches (S0-S5) .. ..39

7.2. POST and Inductor LEDs .. ... 41

7.3. ATX Power Connectors . ... 42

# List of Figures

Figure 1 – Carrier top view.... .11
Figure 2 – Component location.. .13
Figure 3 – Functional diagram.... .14
Figure 4 – Mechanical dimensions ..... ...15
Figure 5 – Carrier board signals, type 6 pinout ... .16

# Introduction

![A red triangular warning symbol featuring a white exclamation mark in the center.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/13c7291d0fd77575bd3d0190b2aa23aff15b02f55937221c7cafe92252f0df8c.jpg)

Warning: This is an EA (early available) engineering manual. The contents may not accurately reflect the actual or final version of this product.

The COM Express approach of custom carrier combined with off-the-shelf system cores relieves developers the need to design their own system core, thereby not only accelerating their proof of concept significantly but also empowers them to upgrade to later-generation processors without having to redesign. It fits most system integration projects with production volumes ranging from 500 to 10,000 pcs per year. The COM Express concept reduces engineering complexity, lowers the threshold for total project quantity, and last but not least brings your product to the market in no time. The average time to design a carrier board is less than half the time of a full custom OEM board.

The Express-BASE6 R3.1, based on PICMG COM-Express R3.1, is an extended ATX size carrier board. Together with the COM Express Type 6 module of your choice and off-the-shelf add-on cards, you can quickly emulate the functionality of your desired end product for software development and hardware verification.

To build a functional prototype of your target system, you will need:

COM Express Type 6 module
Express-BASE6 R3.1 carrier
PCI Express-based storage or SATA storage (SATA storage solutions are dependent on module specifications)

The Express-BASE6 R3.1 carrier is compatible with Basic size and Compact size COMe modules and may accommodate:

1x PCI Express x16 slot, 1x PCI Express x4 slots, 4x PCI Express x1 slots
1x VGA, 1x DP, 1x general purpose LAN, 2x USB 4.0, 4x USB 3.2, 2x USB 2.0, 1x DB-9 COM port, 1x SPDIF, 1x Line-in/Mic-in/Speaker out. (at rear I/O)

# 2. Special Features (Differences from R3.0 Carrier)

![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-10-231030/0fe8326082bf5faf76ca3fa99724920cb1b2ed7ecae67f1a1da43aca2b0c710f.jpg)

Figure 1 – Carrier top view

# 2.1. One PCI Express Gen4 x16 slot + One x4 Slot

1x FHFL PCI Express Gen4 card at PEG slot and 1x PCI Express Gen4 card at PCIE0\_3 slot

# 2.2. Two USB4 Type-C connector

2x USB Type-C connector that support USB4 spec (thunderbolt 4 compatible), can be used to transmit data or output images

# 2.3. Onboard Audio

Realtek ALC888 Audio codec onboard, with Audio I/O provided by 1x three-jack connector and 1x SPDIF connector

# 2.4. Display

1x VGA, 1x DP, 1x LVDS and 1x eDP (BOM option) connector onboard, can display without going through T6DDI

# 2.5. SD Card

1x SD Card connector (with GPIO function by BOM option)

# 3. Component Location

![PWR BIN\nSMBUS CPG\nModule CPG\nFXUSB\nI2C SMBUS I2S ST BIN SLP BIN TO BIN F AUD\nAUD SUR\nF PANEL\nPWR ON\nHDD\nSVSB CN23\nS3\nJP23 EEEP\nSD CARD\nSWI\nJP6\nGP SP1 IP7\nCOM\nExpress\nPCIE7\nPCIE6\nPCIE5\nPCIE4\nPCIE0 3\nPEG\nIP27 JP24 LVDS SATA PWR\neDP JP35 SATA 3 SATA 2\nBL CTRL JP29\nJP28\nBATTERY\nATX 4\nJP32 JP33\nATX 241\nAB\nCD\nAUDIO\nSPD/F\nUSB 4 5\nLAN USB 2 3\nUSB 0 1\nDP DD13\nUSB4 1\nUSB4 2\nVGA_COM0\nFAN COM5 FAN 1 FAN 2 COM1 COM2 COM3 LP- CSPI KB MS](.express-base6-r3-1-manual-50m-77107-1000-10-231030/9f13744fac17297ec3db832804cc81ce030d6ee27355f30c29620ee018508048.jpg)

Figure 2 – Component location

# 4 Functional Diagram

![The diagram illustrates a system architecture with two central vertical blocks labeled **AB** and **CD**, connecting various peripherals and interfaces.\n\n**Left Side Components:**\n*   **34-pin LVDS** and **eDP** (labeled with **build option**).\n*   Four SATA connectors labeled **SATA 0**, **SATA 1**, **SATA 2**, and **SATA 3**.\n*   A connector labeled **PCIe 0-3 (x4)**.\n*   Two connectors labeled **PCIe 4** and **PCIe 5**.\n*   An **Audio Codec ACL888** block connected to **HDA** (right), **SPDIF** (down), and audio jacks (left).\n*   A **Super I/O NCT6126D** chip connected to:\n    *   **2x** (up)\n    *   **Port 80** (right, showing two small squares labeled '8')\n    *   **LPC** (right)\n    *   **RS-232 pitch 2.54** (left)\n    *   **RS-232/485** (left)\n    *   **SP339** (right)\n    *   **Analog VGA** (down)\n    *   **FAN** (right)\n\n**Central Connections (Between AB and CD):**\n*   **USB 4 (2.0/1.1)** and **USB 5 (2.0/1.1)** connect to a block containing **TBT4 JHL8540** and **USB PD**.\n    *   **TBT4** connects to **USB4 1**.\n    *   **USB PD** connects to **USB4 2**.\n*   **LAN (2.5GbE)** connects to a LAN port icon.\n*   **USB 2 (2.0/1.1)** and **USB 3 (2.0/1.1)** connect to a USB port icon, which connects to **USB 2 (3.x)** and **USB 3 (3.x)**.\n*   **USB 0 (2.0/1.1)** and **USB 1 (2.0/1.1)** connect to a USB port icon, which connects to **USB 0 (3.x)** and **USB 1 (3.x)**.\n*   **USB 6 (2.0/1.1)** connects to a USB port icon.\n*   **USB 7 (2.0/1.1)** connects to a **USB Hub**, which connects via **2x** to a **9-pin pitch 2.54** connector.\n*   A **MUX** block connects to an **SD Slot** and an **8-pin GPIO pitch 2.54** connector.\n*   **SER 0/1** connects to a serial port icon.\n*   **I²C, SMB** connects to a header.\n*   **Feature, Controls** connects to a header.\n*   **SPI** connects to a small black connector.\n\n**Right Side Components (Connected to CD):**\n*   **PCIe 16-31 (x16)** connects to a large PCIe connector.\n*   **DDI 3** connects to an **HDMI** port.\n*   **PCIe 6** and **PCIe 7** connect to PCIe connectors.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/118356e445170c563093612f28bba394e947f04b66783099b120665e2d50f453.jpg)

Figure 3 – Functional diagram

# 5. Mechanical Dimension

![227.33\n233.68\n154.94\n0\n10.16\n16.51\n0\n58.42\n24.4\n44.72\n65.04\n78.74\n85.36\n105.68\n124.46\n126\n124.46\n124.46\n154.55\n241.55\n281.94\n281.94\n227.33\n189.9\n159.9\n148.9\n72.9\n22.86](.express-base6-r3-1-manual-50m-77107-1000-10-231030/51944d2fe16af79f19395ed4f02f41196f016835ff9c1c63acbdbc4975abad33.jpg)

Figure 4 – Mechanical dimensions

![The image features a red-outlined icon of a document or file. It has a white fill and a folded bottom-right corner. Inside, two horizontal red lines represent text.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/330bb3ec644ef88513f0b6655e81e0aceece79176ce903cb3f7642647e1bafe9.jpg)

Note: All dimensions are shown in millimeters with a tolerance of ± 0.25mm unless otherwise noted.

# 6. Connectors and Pinouts

# 6.1. Carrier Board Signals — Type 6

![Type 6\n2x 220 pins\n| Category | Component | Value |\n| :--- | :--- | :--- |\n| CD | 4x USB 3.x upgrade | 4x USB 3.x upgrade |\n| CD | LPC | LPC |\n| CD | GbE | GbE |\n| CD | 4x SATA | 4x SATA |\n| CD | HDA / SNDW | HDA / SNDW |\n| CD | 8x USB 2.0 | 8x USB 2.0 |\n| CD | DDI_1 / USB4_1 | DDI_1 / USB4_1 |\n| CD | DDI_2 / USB4_2 | DDI_2 / USB4_2 |\n| CD | DDI_3 | DDI_3 |\n| CD | PCIe x16 | PCIe x16 |\n| AB | 6x PCIe | 6x PCIe |\n| AB | LVDS / eDP | LVDS / eDP |\n| AB | CRT (VGA) | CRT (VGA) |\n| AB | GP SPI | GP SPI |\n| AB | 5Vsb | 5Vsb |\n12V](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a93b21912e025ed65807b51afd4e049efbd619d40d8962043243d1c6284c163a.jpg)

Figure 5 – Carrier board signals, type 6 pinout

# 6.2. Connector Location and Pinout Compatibility

Connector positions and pinouts comply with the pinout and signal descriptions within PICMG® COM.0 - COM Express Module Base specification, Revision 3.1. This document includes description of pinouts, signal descriptions and mechanical characteristics of the COM Express specification. The Express-BASE6 R3.1 is compatible with COM Express modules in Basic and Compact form factor, Type 6 pinout, COM.0 Rev. 3.1.

Signals and Pinout for: COM Express Type 6.

![D1\nC1\nD110\nC D\nC110\nB1\nA1\nB110\nA B\nA10](.express-base6-r3-1-manual-50m-77107-1000-10-231030/7dab2d5e6e7a02f4d9abdc202e7f5b483984afc0e4cdad3569e272c7b79e100a.jpg)

# 6.3. Carrier Board Design

Express-BASE6 R3.1 follows the PICMG COM Express Carrier Design Guide where possible, and its design and schematic have been fully verified. It is recommend to utilize them as references for your carrier board design. Express-BASE6 R3.1 schematics and mechanical files, as well as the CDG, can be downloaded from ADLINK COM’s webpage.

# 6.4. COM Express R3.1 Type 6 Board-to-board Connectors

Signals and Pinouts for COM Express R3.1 Type 6

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>GND</td><td></td><td>B1</td><td>GND</td><td></td><td>C1</td><td>GND</td><td></td><td>D1</td><td>GND</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td></td><td>B2</td><td>GBE0_ACT#</td><td></td><td>C2</td><td>GND</td><td></td><td>D2</td><td>GND</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td></td><td>B3</td><td>LPC_FRAME#/ESPI_CS0#</td><td></td><td>C3</td><td>USB_SSRX0-</td><td></td><td>D3</td><td>USB_SSTX0-</td></tr><tr><td>A4</td><td>GBE0_LINK100#</td><td></td><td>B4</td><td>LPC_AD0/ESPI_IO_0</td><td></td><td>C4</td><td>USB_SSRX0+</td><td></td><td>D4</td><td>USB_SSTX0+</td></tr><tr><td>A5</td><td>GBE0_LINK1000#</td><td></td><td>B5</td><td>LPC_AD1/ESPI_IO_1</td><td></td><td>C5</td><td>GND</td><td></td><td>D5</td><td>GND</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td></td><td>B6</td><td>LPC_AD2/ESPI_IO_2</td><td></td><td>C6</td><td>USB_SSRX1-</td><td></td><td>D6</td><td>USB_SSTX1-</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td></td><td>B7</td><td>LPC_AD3/ESPI_IO_3</td><td></td><td>C7</td><td>USB_SSRX1+</td><td></td><td>D7</td><td>USB_SSTX1+</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td></td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td><td></td><td>C8</td><td>GND</td><td></td><td>D8</td><td>GND</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td></td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td><td></td><td>C9</td><td>USB_SSRX2-</td><td></td><td>D9</td><td>USB_SSTX2-</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td></td><td>B10</td><td>LPC_CLK/ESPI_CK</td><td></td><td>C10</td><td>USB_SSRX2+</td><td></td><td>D10</td><td>USB_SSTX2+</td></tr><tr><td>A11</td><td>GND</td><td></td><td>B11</td><td>GND</td><td></td><td>C11</td><td>GND</td><td></td><td>D11</td><td>GND</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td></td><td>B12</td><td>PWRBTN#</td><td></td><td>C12</td><td>USB_SSRX3-</td><td></td><td>D12</td><td>USB_SSTX3-</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td></td><td>B13</td><td>SMB_CK</td><td></td><td>C13</td><td>USB_SSRX3+</td><td></td><td>D13</td><td>USB_SSTX3+</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td></td><td>B14</td><td>SMB_DAT</td><td></td><td>C14</td><td>GND</td><td></td><td>D14</td><td>GND</td></tr><tr><td>A15</td><td>SUS_S3#</td><td></td><td>B15</td><td>SMB_ALERT#</td><td></td><td>C15</td><td>USB4_1_LSTX</td><td></td><td>D15</td><td>DDI1_CTRLCLK_AUX+/USB4_1_AUX+</td></tr><tr><td>A16</td><td>SATA0_TX+</td><td></td><td>B16</td><td>SATA1_TX+</td><td></td><td>C16</td><td>USB4_1_LSRX</td><td></td><td>D16</td><td>DDI1_CTRLDATA_AUX-/USB4_1_AUX-</td></tr><tr><td>A17</td><td>SATA0_TX-</td><td></td><td>B17</td><td>SATA1_TX-</td><td></td><td>C17</td><td>USB4_RT_ENA</td><td></td><td>D17</td><td>USB4_PD_I2C_ALERT#</td></tr><tr><td>A18</td><td>SUS_S4#</td><td></td><td>B18</td><td>SUS_STAT#/ESPI_RESET#</td><td></td><td>C18</td><td>GND</td><td></td><td>D18</td><td>PMCALERT#</td></tr><tr><td>A19</td><td>SATA0_RX+</td><td></td><td>B19</td><td>SATA1_RX+</td><td></td><td>C19</td><td>PCIE_RX6+</td><td></td><td>D19</td><td>PCIE_TX6+</td></tr><tr><td>A20</td><td>SATA0_RX-</td><td></td><td>B20</td><td>SATA1_RX-</td><td></td><td>C20</td><td>PCIE_RX6-</td><td></td><td>D20</td><td>PCIE_TX6-</td></tr><tr><td>A21</td><td>GND</td><td></td><td>B21</td><td>GND</td><td></td><td>C21</td><td>GND</td><td></td><td>D21</td><td>GND</td></tr><tr><td>A22</td><td>SATA2_TX+</td><td></td><td>B22</td><td>SATA3_TX+</td><td></td><td>C22</td><td>PCIE_RX7+</td><td></td><td>D22</td><td>PCIE_TX7+</td></tr></table>

<table><tr><td colspan="2">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td colspan="2">Row D</td></tr><tr><td>A23</td><td>SATA2_TX-</td><td>B23</td><td>SATA3_TX-</td><td>C23</td><td>PCIE_RX7-</td><td>D23</td><td>PCIE_TX7-</td></tr><tr><td>A24</td><td>SUS_S5#</td><td>B24</td><td>PWR_OK</td><td>C24</td><td>DDI1_HPD</td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>SATA2_RX+</td><td>B25</td><td>SATA3_RX+</td><td>C25</td><td>SML0_CLK</td><td>D25</td><td>GND</td></tr><tr><td>A26</td><td>SATA2_RX-</td><td>B26</td><td>SATA3_RX-</td><td>C26</td><td>SML0_DAT</td><td>D26</td><td>DDI1_PAIR0+/USB4_1_SSTX0+</td></tr><tr><td>A27</td><td>BATLOW#</td><td>B27</td><td>WDT</td><td>C27</td><td>SML1_CLK</td><td>D27</td><td>DDI1_PAIR0-/USB4_1_SSTX0-</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td>B28</td><td>HDA_SDIN2/SNDW0_CLK</td><td>C28</td><td>SML1_DAT</td><td>D28</td><td>GND</td></tr><tr><td>A29</td><td>HDA_SYNC</td><td>B29</td><td>HDA_SDIN1/SNDW0_DAT</td><td>C29</td><td>USB4_PD_I2C_CLK</td><td>D29</td><td>DDI1_PAIR1+/USB4_1_SSRX0+</td></tr><tr><td>A30</td><td>HDA_RST#</td><td>B30</td><td>HDA_SDIN0</td><td>C30</td><td>USB4_PD_I2C_DAT</td><td>D30</td><td>DDI1_PAIR1-/USB4_1_SSRX0-</td></tr><tr><td>A31</td><td>GND</td><td>B31</td><td>GND</td><td>C31</td><td>GND</td><td>D31</td><td>GND</td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td>B32</td><td>SPKR</td><td>C32</td><td>DDI2_CTRLCLK_AUX+/USB4_2_AUX+</td><td>D32</td><td>DDI1_PAIR2+/USB4_1_SSTX1+</td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td>B33</td><td>I2C_CK</td><td>C33</td><td>DDI2_CTRLDATA_AUX-/USB4_2_AUX-</td><td>D33</td><td>DDI1_PAIR2-/USB4_1_SSTX1-</td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS</td><td>B34</td><td>I2C_DAT</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td>B35</td><td>THRM#</td><td>C35</td><td>USB4_2_LSTX</td><td>D35</td><td>USB4_2_LSRX</td></tr><tr><td>A36</td><td>USB6-</td><td>B36</td><td>USB7-</td><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td>D36</td><td>DDI1_PAIR3+/USB4_1_SSRX1+</td></tr><tr><td>A37</td><td>USB6+</td><td>B37</td><td>USB7+</td><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td>D37</td><td>DDI1_PAIR3-/USB4_1_SSRX1-</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td>B38</td><td>USB_4_5_OC#</td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td>D38</td><td>GND</td></tr><tr><td>A39</td><td>USB4-</td><td>B39</td><td>USB5-</td><td>C39</td><td>DDI3_PAIR0+</td><td>D39</td><td>DDI2_PAIR0+/USB4_2_SSTX0+</td></tr><tr><td>A40</td><td>USB4+</td><td>B40</td><td>USB5+</td><td>C40</td><td>DDI3_PAIR0-</td><td>D40</td><td>DDI2_PAIR0-/USB4_2_SSTX0-</td></tr><tr><td>A41</td><td>GND</td><td>B41</td><td>GND</td><td>C41</td><td>GND</td><td>D41</td><td>GND</td></tr><tr><td>A42</td><td>USB2-</td><td>B42</td><td>USB3-</td><td>C42</td><td>DDI3_PAIR1+</td><td>D42</td><td>DDI2_PAIR1+/USB4_2_SSRX0+</td></tr><tr><td>A43</td><td>USB2+</td><td>B43</td><td>USB3+</td><td>C43</td><td>DDI3_PAIR1-</td><td>D43</td><td>DDI2_PAIR1-/USB4_2_SSRX0-</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td>B44</td><td>USB_0_1_OC#</td><td>C44</td><td>DDI3_HPD</td><td>D44</td><td>DDI2_HPD</td></tr><tr><td>A45</td><td>USB0-</td><td>B45</td><td>USB1-</td><td>C45</td><td>GP_SPI_CS0#</td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>USB0+</td><td>B46</td><td>USB1+</td><td>C46</td><td>DDI3_PAIR2+</td><td>D46</td><td>DDI2_PAIR2+/USB4_2_SSTX1+</td></tr><tr><td>A47</td><td>VCC_RTC</td><td>B47</td><td>ESPI_EN#</td><td>C47</td><td>DDI3_PAIR2-</td><td>D47</td><td>DDI2_PAIR2-/USB4_2_SSTX1-</td></tr><tr><td>A48</td><td>RSMRST_OUT#</td><td>B48</td><td>USB0_HOST_PRSNT</td><td>C48</td><td>RSVD</td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GBEO_SDP</td><td>B49</td><td>SYS_RESET#</td><td>C49</td><td>DDI3_PAIR3+</td><td>D49</td><td>DDI2_PAIR3+/USB4_2_SSRX1+</td></tr><tr><td>A50</td><td>LPC_SERIRQ/ESPI_CS1#</td><td>B50</td><td>CB_RESET#</td><td>C50</td><td>DDI3_PAIR3-</td><td>D50</td><td>DDI2_PAIR3-/USB4_2_SSRX1-</td></tr><tr><td>A51</td><td>GND</td><td>B51</td><td>GND</td><td>C51</td><td>GND</td><td>D51</td><td>GND</td></tr><tr><td>A52</td><td>PCIE_TX5+</td><td>B52</td><td>PCIE_RX5+</td><td>C52</td><td>PEG_RX0+</td><td>D52</td><td>PEG_TX0+</td></tr><tr><td>A53</td><td>PCIE_TX5-</td><td>B53</td><td>PCIE_RX5-</td><td>C53</td><td>PEG_RX0-</td><td>D53</td><td>PEG_TX0-</td></tr><tr><td>A54</td><td>GPIO</td><td>B54</td><td>GPO</td><td>C54</td><td>TYPE0#</td><td>D54</td><td>PEG_LANE_RV#</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td>B55</td><td>PCIE_RX4+</td><td>C55</td><td>PEG_RX1+</td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td>B56</td><td>PCIE_RX4-</td><td>C56</td><td>PEG_RX1-</td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td>B57</td><td>GPO2</td><td>C57</td><td>TYPE1#</td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td>B58</td><td>PCIE_RX3+</td><td>C58</td><td>PEG_RX2+</td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td>B59</td><td>PCIE_RX3-</td><td>C59</td><td>PEG_RX2-</td><td>D59</td><td>PEG_TX2-</td></tr></table>

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A60</td><td>GND</td><td></td><td>B60</td><td>GND</td><td></td><td>C60</td><td>GND</td><td></td><td>D60</td><td>GND</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td></td><td>B61</td><td>PCIE_RX2+</td><td></td><td>C61</td><td>PEG_RX3+</td><td></td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td></td><td>B62</td><td>PCIE_RX2-</td><td></td><td>C62</td><td>PEG_RX3-</td><td></td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1</td><td></td><td>B63</td><td>GPO3</td><td></td><td>C63</td><td>GND</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td></td><td>B64</td><td>PCIE_RX1+</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>GND</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td></td><td>B65</td><td>PCIE_RX1-</td><td></td><td>C65</td><td>PEG_RX4+</td><td></td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td></td><td>B66</td><td>WAKE0#</td><td></td><td>C66</td><td>PEG_RX4-</td><td></td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2</td><td></td><td>B67</td><td>WAKE1#</td><td></td><td>C67</td><td>RAPID_SHUTDOWN</td><td></td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td></td><td>B68</td><td>PCIE_RX0+</td><td></td><td>C68</td><td>PEG_RX5+</td><td></td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td></td><td>B69</td><td>PCIE_RX0-</td><td></td><td>C69</td><td>PEG_RX5-</td><td></td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND</td><td></td><td>B70</td><td>GND</td><td></td><td>C70</td><td>GND</td><td></td><td>D70</td><td>GND</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td></td><td>B71</td><td>LVDS_B0+</td><td></td><td>C71</td><td>PEG_RX6+</td><td></td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td></td><td>B72</td><td>LVDS_B0-</td><td></td><td>C72</td><td>PEG_RX6-</td><td></td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td></td><td>B73</td><td>LVDS_B1+</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td></td><td>B74</td><td>LVDS_B1-</td><td></td><td>C74</td><td>PEG_RX7+</td><td></td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td></td><td>B75</td><td>LVDS_B2+</td><td></td><td>C75</td><td>PEG_RX7-</td><td></td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td></td><td>B76</td><td>LVDS_B2-</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td></td><td>B77</td><td>LVDS_B3+</td><td></td><td>C77</td><td>GND</td><td></td><td>D77</td><td>GND</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td></td><td>B78</td><td>LVDS_B3-</td><td></td><td>C78</td><td>PEG_RX8+</td><td></td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td></td><td>B79</td><td>LVDS_BKLT_EN</td><td></td><td>C79</td><td>PEG_RX8-</td><td></td><td>D79</td><td>PEG_TX8-</td></tr><tr><td>A80</td><td>GND</td><td></td><td>B80</td><td>GND</td><td></td><td>C80</td><td>GND</td><td></td><td>D80</td><td>GND</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td></td><td>B81</td><td>LVDS_B_CK+</td><td></td><td>C81</td><td>PEG_RX9+</td><td></td><td>D81</td><td>PEG_TX9+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td></td><td>B82</td><td>LVDS_B_CK-</td><td></td><td>C82</td><td>PEG_RX9-</td><td></td><td>D82</td><td>PEG_TX9-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td></td><td>B83</td><td>LVDS_BKLT_CTRL</td><td></td><td>C83</td><td>GND</td><td></td><td>D83</td><td>GND</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td></td><td>B84</td><td>VCC_5V_SBY</td><td></td><td>C84</td><td>GND</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3</td><td></td><td>B85</td><td>VCC_5V_SBY</td><td></td><td>C85</td><td>PEG_RX10+</td><td></td><td>D85</td><td>PEG_TX10+</td></tr><tr><td>A86</td><td>GP_SPI_MOSI</td><td></td><td>B86</td><td>VCC_5V_SBY</td><td></td><td>C86</td><td>PEG_RX10-</td><td></td><td>D86</td><td>PEG_TX10-</td></tr><tr><td>A87</td><td>eDP_HPD</td><td></td><td>B87</td><td>VCC_5V_SBY</td><td></td><td>C87</td><td>GND</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE_CLK_REF+</td><td></td><td>B88</td><td>BIOS_DIS1#</td><td></td><td>C88</td><td>PEG_RX11+</td><td></td><td>D88</td><td>PEG_TX11+</td></tr><tr><td>A89</td><td>PCIE_CLK_REF-</td><td></td><td>B89</td><td>VGA_RED</td><td></td><td>C89</td><td>PEG_RX11-</td><td></td><td>D89</td><td>PEG_TX11-</td></tr><tr><td>A90</td><td>GND</td><td></td><td>B90</td><td>GND</td><td></td><td>C90</td><td>GND</td><td></td><td>D90</td><td>GND</td></tr><tr><td>A91</td><td>SPI_POWER</td><td></td><td>B91</td><td>VGA_GRN</td><td></td><td>C91</td><td>PEG_RX12+</td><td></td><td>D91</td><td>PEG_TX12+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td></td><td>B92</td><td>VGA_BLU</td><td></td><td>C92</td><td>PEG_RX12-</td><td></td><td>D92</td><td>PEG_TX12-</td></tr><tr><td>A93</td><td>GPO0</td><td></td><td>B93</td><td>VGA_HSYNC</td><td></td><td>C93</td><td>GND</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td></td><td>B94</td><td>VGA_VSYNC</td><td></td><td>C94</td><td>PEG_RX13+</td><td></td><td>D94</td><td>PEG_TX13+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td></td><td>B95</td><td>VGA_I2C_CK</td><td></td><td>C95</td><td>PEG_RX13-</td><td></td><td>D95</td><td>PEG_TX13-</td></tr><tr><td>A96</td><td>TPM_PP</td><td></td><td>B96</td><td>VGA_I2C_DAT</td><td></td><td>C96</td><td>GND</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td></td><td>B97</td><td>SPI_CS#</td><td></td><td>C97</td><td>GND</td><td></td><td>D97</td><td>GND</td></tr><tr><td>A98</td><td>SER0_TX</td><td></td><td>B98</td><td>GP_SPI_MISO</td><td></td><td>C98</td><td>PEG_RX14+</td><td></td><td>D98</td><td>PEG_TX14+</td></tr><tr><td>A99</td><td>SER0_RX</td><td></td><td>B99</td><td>GP_SPI_CK</td><td></td><td>C99</td><td>PEG_RX14-</td><td></td><td>D99</td><td>PEG_TX14-</td></tr><tr><td>A100</td><td>GND</td><td></td><td>B100</td><td>GND</td><td></td><td>C100</td><td>GND</td><td></td><td>D100</td><td>GND</td></tr><tr><td>A101</td><td>SER1_TX</td><td></td><td>B101</td><td>FAN_PWMOUT</td><td></td><td>C101</td><td>PEG_RX15+</td><td></td><td>D101</td><td>PEG_TX15+</td></tr><tr><td>A102</td><td>SER1_RX</td><td></td><td>B102</td><td>FAN_TACHIN</td><td></td><td>C102</td><td>PEG_RX15-</td><td></td><td>D102</td><td>PEG_TX15-</td></tr><tr><td>A103</td><td>LID#</td><td></td><td>B103</td><td>SLEEP#</td><td></td><td>C103</td><td>GND</td><td></td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td></td><td>B104</td><td>VCC_12V</td><td></td><td>C104</td><td>VCC_12V</td><td></td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td></td><td>B105</td><td>VCC_12V</td><td></td><td>C105</td><td>VCC_12V</td><td></td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td></td><td>B106</td><td>VCC_12V</td><td></td><td>C106</td><td>VCC_12V</td><td></td><td>D106</td><td>VCC_12V</td></tr><tr><td>A107</td><td>VCC_12V</td><td></td><td>B107</td><td>VCC_12V</td><td></td><td>C107</td><td>VCC_12V</td><td></td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td></td><td>B108</td><td>VCC_12V</td><td></td><td>C108</td><td>VCC_12V</td><td></td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td></td><td>B109</td><td>VCC_12V</td><td></td><td>C109</td><td>VCC_12V</td><td></td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND</td><td></td><td>B110</td><td>GND</td><td></td><td>C110</td><td>GND</td><td></td><td>D110</td><td>GND</td></tr></table>

# 6.5. PCIe x16 Connectors

PEG: PCIe x16 Gen4 Slot, PEG Lanes 0:15 assigned PCIe Slot

![Pure electrical circuit lines without any symbols](.express-base6-r3-1-manual-50m-77107-1000-10-231030/9824b2f8dc62c99e8bf672ce80ca367a3927c44389283a6cf728ed944cf3104d.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+ 12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+ 12V</td><td>A2</td><td>+ 12V</td></tr><tr><td>B3</td><td>+ 12V</td><td>A3</td><td>+ 12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+ 3.3V</td></tr><tr><td>B10</td><td>+ 3.3VAUX</td><td>A10</td><td>+ 3.3V</td></tr><tr><td>B11</td><td>WAKE#</td><td>A11</td><td>PERST#</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B64</td><td>GND</td><td>A64</td><td>PERp11</td></tr><tr><td>B65</td><td>GND</td><td>A65</td><td>PERn11</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td>B33</td><td>PETp4</td><td>A33</td><td>RSVD</td></tr><tr><td>B34</td><td>PETn4</td><td>A34</td><td>GND</td></tr><tr><td>B35</td><td>GND</td><td>A35</td><td>PERp4</td></tr><tr><td>B36</td><td>GND</td><td>A36</td><td>PERn4</td></tr><tr><td>B37</td><td>PETp5</td><td>A37</td><td>GND</td></tr><tr><td>B38</td><td>PETn5</td><td>A38</td><td>GND</td></tr><tr><td>B39</td><td>GND</td><td>A39</td><td>PERp5</td></tr><tr><td>B40</td><td>GND</td><td>A40</td><td>PERn5</td></tr><tr><td>B41</td><td>PETp6</td><td>A41</td><td>GND</td></tr><tr><td>B42</td><td>PETn6</td><td>A42</td><td>GND</td></tr><tr><td>B71</td><td>PETn13</td><td>A71</td><td>GND</td></tr><tr><td>B72</td><td>GND</td><td>A72</td><td>PERp13</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B43</td><td>GND</td><td>A43</td><td>PERp6</td></tr><tr><td>B44</td><td>GND</td><td>A44</td><td>PERn6</td></tr><tr><td>B45</td><td>PETp7</td><td>A45</td><td>GND</td></tr><tr><td>B46</td><td>PETn7</td><td>A46</td><td>GND</td></tr><tr><td>B47</td><td>GND</td><td>A47</td><td>PERp7</td></tr><tr><td>B48</td><td>PRSNT</td><td>A48</td><td>PERn7</td></tr><tr><td>B49</td><td>GND</td><td>A49</td><td>GND</td></tr><tr><td>B50</td><td>PETp8</td><td>A50</td><td>RSVD</td></tr><tr><td>B51</td><td>PETn8</td><td>A51</td><td>GND</td></tr><tr><td>B52</td><td>GND</td><td>A52</td><td>PERp8</td></tr><tr><td>B53</td><td>GND</td><td>A53</td><td>PERn8</td></tr><tr><td>B54</td><td>PETp9</td><td>A54</td><td>GND</td></tr><tr><td>B55</td><td>PETn9</td><td>A55</td><td>GND</td></tr><tr><td>B56</td><td>GND</td><td>A56</td><td>PERp9</td></tr><tr><td>B57</td><td>GND</td><td>A57</td><td>PERn9</td></tr><tr><td>B58</td><td>PETp10</td><td>A58</td><td>GND</td></tr><tr><td>B59</td><td>PETn10</td><td>A59</td><td>GND</td></tr><tr><td>B60</td><td>GND</td><td>A60</td><td>PERp10</td></tr><tr><td>B61</td><td>GND</td><td>A61</td><td>PERn10</td></tr><tr><td>B62</td><td>PETp11</td><td>A62</td><td>GND</td></tr><tr><td>B63</td><td>PETn11</td><td>A63</td><td>GND</td></tr><tr><td>B78</td><td>PETp15</td><td>A78</td><td>GND</td></tr><tr><td>B79</td><td>PETn15</td><td>A79</td><td>GND</td></tr><tr><td>B66</td><td>PETp12</td><td>A66</td><td>GND</td></tr><tr><td>B67</td><td>PETn12</td><td>A67</td><td>GND</td></tr><tr><td>B68</td><td>GND</td><td>A68</td><td>PERp12</td></tr><tr><td>B69</td><td>GND</td><td>A69</td><td>PERn12</td></tr><tr><td>B70</td><td>PETp13</td><td>A70</td><td>GND</td></tr></table>

<table><tr><td>B73</td><td>GND</td><td>A73</td><td>PERn13</td></tr><tr><td>B74</td><td>PETp14</td><td>A74</td><td>GND</td></tr><tr><td>B75</td><td>PETn14</td><td>A75</td><td>GND</td></tr><tr><td>B76</td><td>GND</td><td>A76</td><td>PERp14</td></tr><tr><td>B77</td><td>GND</td><td>A77</td><td>PERn14</td></tr></table>

<table><tr><td>B80</td><td>GND</td><td>A80</td><td>PERp15</td></tr><tr><td>B81</td><td>PRSNT</td><td>A81</td><td>PERn15</td></tr><tr><td>B82</td><td>RSVD</td><td>A82</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.6. PCIe x4 Connector

PCIE0\_3: PCIe x4 Gen4 Slot, PCIE Lanes 0:3 assigned PCIe Slot

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

![The image shows a horizontal, grey, rack-mountable server chassis or storage enclosure. The front face is dominated by a dark grey, vented panel divided into four quadrants by a central cross-shaped gap. Each quadrant features rows of vertical slots, resembling drive bays or cooling vents. A vertical handle is visible on the far left edge. Near the bottom center of the chassis, there are small, faint green indicator lights. The object is depicted against a plain white background.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a9b1c6fdcbac0de319bf059a9045b504fb10a4acf7a8446e6d1c4ca9da1eba5e.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.7. PCIe x1 Connector

PCIE4: PCIe x1Gen3 Slot, PCIE Lanes 4 assigned PCIE Slot

PCIE5: PCIe x1Gen3 Slot, PCIE Lanes 5 assigned PCIE Slot

PCIE6: PCIe x1Gen3 Slot, PCIE Lanes 6 assigned PCIE Slot

PCIE7: PCIe x1Gen3 Slot, PCIE Lanes 7 assigned PCIE Slot

![The image displays a black computer cooling fan with a rectangular shape and rounded corners. The fan's face features a black grille with horizontal slats, surrounding a central circular area that contains vertical slats. Green mounting tabs are visible at the four corners, and green mounting hinges are located on the left and right sides. There is no text in the image.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/e099b25537794c3322fa86157f09d49df02d2e8ce052228e3a3f5de86a746f80.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 6.8. USB2.0 Port Header

F\_2XUSB: HUB USB2.0 Port 2 and Port 3 header

<table><tr><td>Pin</td><td>Signal</td><td></td><td></td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+5V</td></tr><tr><td>3</td><td>HUB1_USB7_N2</td><td>4</td><td>HUB1_USB7_N3</td></tr><tr><td>5</td><td>HUB1_USB7_P2</td><td>6</td><td>HUB1_USB7_P3</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image displays a grey cartoon hand holding a white calculator. The calculator features a grid of buttons with numbers printed on them. Reading from left to right and top to bottom, the numbers are:\n\n2 0 1\n4 3 3\n6 6 5\n8 8 7\n10 9 9](.express-base6-r3-1-manual-50m-77107-1000-10-231030/75e060b48af632892532d608cea50b8aedb4a792f6773261077e161622e4ae78.jpg)

# 6.9. Audio Header

F\_AUD: AUDIO Front Panel Header

<table><tr><td></td><td></td><td></td><td></td></tr><tr><td>1</td><td>MIC2_L_HD</td><td>2</td><td>AGND_AU</td></tr><tr><td>3</td><td>MIC2_R_HD</td><td>4</td><td>PRESENCE</td></tr><tr><td>5</td><td>LINE2_R_HD</td><td>6</td><td>MIC2_JD</td></tr><tr><td>7</td><td>AGND_AU</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>LINE2_L_HD</td><td>10</td><td>LINE2_JD</td></tr></table>

![The image shows a standard numeric keypad layout with black text on light gray buttons. The text reads, from top to bottom and left to right:\n\n1 2 3\n4 5 6\n7 8 9\n* 0 #](.express-base6-r3-1-manual-50m-77107-1000-10-231030/3cdeb2a0d44334c0a044168b475c6d8cefdfb38db9ebf3cade1d10420da2a3dd.jpg)

# 6.10. SATA Port

SATA\_0/SATA\_1/SATA\_2/SATA\_3: Serial ATA Port

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX_P</td></tr><tr><td>3</td><td>TX_N</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX_P</td></tr><tr><td>6</td><td>RX_N</td></tr><tr><td>7</td><td>SATA0_P7</td></tr></table>

![This is a grayscale digital illustration of a horizontal rectangular interface, resembling an audio equalizer or sound mixer. The central panel is dark grey and features a row of six vertical rectangular tracks, each containing a dark grey slider bar. Above the sliders, centered at the top, is a small black rectangle. On the far left and right sides of the panel are two white circles with grey outlines.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/880d6c62946826c1ad3aade0af8976b16d8bd97fb699c8e3ac35c5afe9acb9e1.jpg)

SATA\_PWR: Voltage supply 12V and 5V to HDD Device.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P12V</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>P5V</td></tr></table>

![The image displays a schematic symbol for a 4-pin connector. On the left side, a vertical rectangular outline with rounded corners encloses four white circles arranged in a vertical column. To the right of this rectangle is a column of four squares, each containing the numbers 1, 2, 3, and 4 from top to bottom.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/8fe6655fef7210fa63e7a3ef6304688f5be2a4529d697e24f310fccf0e330cd0.jpg)

# 6.11. LPC/ eSPI Debug Header

LPC\_eSPI: for LPC/ eSPI debugging connection purpose

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CLK_DEBUG</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>LPC_FRAMEJ / ESPI CS0#</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>RST_DBG</td><td>6</td><td>+5V</td></tr><tr><td>7</td><td>eSPI_IO_3 / LPC_AD3</td><td>8</td><td>LPC_AD2/ eSPI_IO_1</td></tr><tr><td>9</td><td>+ 3.3VSB</td><td>10</td><td>LPC_AD1/ eSPI_IO_1</td></tr><tr><td>11</td><td>LPC_AD0/eSPI_IO_0</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>SMB_CK</td><td>14</td><td>SMB_DAT</td></tr><tr><td>15</td><td>1V8SB</td><td>16</td><td>NC</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>LPC_SERIRQ / eSPI_CS1#</td></tr><tr><td>19</td><td>LPC_DRQ0J /eSPI_ALEART0#</td><td>20</td><td>LPC_DRQ1J /eSPI_ALEART1#</td></tr></table>

![The image displays a vertical list of ten rows. Each row features a number on the far left, a grey oval checkbox with a small white square in the center, and a number on the far right.\n\nThe numbers in the left column are even numbers in ascending order:\n2\n4\n6\n8\n10\n12\n14\n16\n18\n20\n\nThe numbers in the right column are odd numbers in ascending order:\n1\n3\n5\n7\n9\n11\n13\n15\n17\n19](.express-base6-r3-1-manual-50m-77107-1000-10-231030/8e34c5bc5bcdaa0752b5e501677b3d6cbb8f8c0cbc6ba7f0da580f336846f6c6.jpg)

# 6.12. PS2 Header

KB\_MS: PS2 function from SIO6126D

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>KBVCC (5V)</td><td>2</td><td>KBVCC (5V)</td></tr><tr><td>3</td><td>MSDAT</td><td>4</td><td>KBDAT</td></tr><tr><td>5</td><td>MSCLK</td><td>6</td><td>KBCLK</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr></table>

![The image displays a list of numbers from 1 to 8 arranged in pairs on either side of checkboxes.\n\n*   **Row 1:** The number '1' is next to a checked box, followed by the number '2'.\n*   **Row 2:** The number '3' is next to an unchecked box, followed by the number '4'.\n*   **Row 3:** The number '5' is next to an unchecked box, followed by the number '6'.\n*   **Row 4:** The number '7' is next to an unchecked box, followed by the number '8'.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a4f3f44943a67e0adff71a55a603e58dd9683558cc849a0772ce5d0ab92b2898.jpg)

# 6.13. COM Port Connector

COM1: the Module UART port1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>SER1_RX_R</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>SER1_TX_R</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image displays a black background with three distinct elements. On the left, the numbers 1, 3, 5, 7, and 9 are listed vertically in white text. On the right, the numbers 2, 4, 6, 8, and 10 are listed vertically in white text. In the center, a black rectangle contains a grid of fifteen white dots arranged in five rows and three columns.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/3e907ac026e3326a218fd456955de930393214cad828f119a6a88bdd48d5b51a.jpg)

COM2: the Module UART port0

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>SER1_RX_R</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>SER1_TX_R</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image features a central black rectangle containing a 5x5 grid of white dots. Flanking this rectangle are two columns of numbers aligned with the rows of dots. On the left, the odd numbers 1, 3, 5, 7, and 9 are listed vertically. On the right, the even numbers 2, 4, 6, 8, and 10 are listed vertically. Each pair of numbers shares a horizontal line with a row of dots in the central block.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/33d6a564d636ac6ba21f4b511e5ba1bd7c6db7f8b2209d14d371e5fd6aa00a9e.jpg)

COM3: the SIONCT6126D UART portB

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CM2_DCD</td><td>2</td><td>CM2_DSR</td></tr><tr><td>3</td><td>CM2_RXD</td><td>4</td><td>CM2_RTS</td></tr><tr><td>5</td><td>CM2_TXD</td><td>6</td><td>CM2_CTS</td></tr><tr><td>7</td><td>CM2_DTR</td><td>8</td><td>CM2_RI</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![The image shows a central black rectangle containing ten white dots arranged in two columns of five. Flanking the rectangle are vertical columns of white numbers. On the left are the numbers 1, 3, 5, 7, 9. On the right are the numbers 2, 4, 6, 8, 10.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a8d61d76c2c6dad1c82a2b85e0e5c682baf62eab91614743dd015c1a2dd141f9.jpg)

COM4: the SIONCT6126D UART portA, D-SUB9 Type connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CM1_DCD</td><td>2</td><td>CM1_RXD</td></tr><tr><td>3</td><td>CM1_TXD</td><td>4</td><td>CM1_DTR</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>CM1_DSR</td></tr><tr><td>7</td><td>CM1_RTS</td><td>8</td><td>CM1_CTS</td></tr><tr><td>9</td><td>RI</td><td></td><td></td></tr></table>

![VGA_COM0](.express-base6-r3-1-manual-50m-77107-1000-10-231030/d86e7e0147ecb810d049ec2018778b85d26858407ed453753220c4de0d9a3fc3.jpg)

# 6.14. BASE6 GPIO Expander Header

SMBUS\_GPIO: BASE6 GPIO expander outputs GPIO 0:3

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>BASE_GPIO</td><td>2</td><td>BASE_GPO0</td></tr><tr><td>3</td><td>BASE_GPI1</td><td>4</td><td>BASE_GPO1</td></tr><tr><td>5</td><td>BASE_GPI2</td><td>6</td><td>BASE_GPO2</td></tr><tr><td>7</td><td>BASE_GPI3</td><td>8</td><td>BASE_GPO3</td></tr></table>

![The image displays a grid-like arrangement of numbers and shapes organized into four rows.\n\n*   **Left Column:** The numbers 1, 3, 5, and 7 appear vertically.\n*   **Right Column:** The numbers 2, 4, 6, and 8 appear vertically.\n*   **Center Column:** There are four horizontal, pill-shaped rectangles stacked vertically.\n    *   The **top rectangle** (aligned with numbers 1 and 2) contains a small black square.\n    *   The **second rectangle** (aligned with numbers 3 and 4) contains two small dots arranged horizontally.\n    *   The **third rectangle** (aligned with numbers 5 and 6) contains two small dots arranged horizontally.\n    *   The **fourth rectangle** (aligned with numbers 7 and 8) contains two small dots arranged horizontally.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/218353fc2844cac28fda0fcdad01d495024976a9bf131240c109d76e0a19cdbc.jpg)

# 6.15. GPIO Header

Module GPIO: Module outputs GPIO Header;

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>MUX_GPI0</td><td>2</td><td>MUX_GPO0</td></tr><tr><td>3</td><td>MUX_GPI1</td><td>4</td><td>MUX_GPO1</td></tr><tr><td>5</td><td>MUX_GPI2</td><td>6</td><td>MUX_GPO2</td></tr><tr><td>7</td><td>MUX_GPI3</td><td>8</td><td>MUX_GPO3</td></tr></table>

![The image displays a vertical column of four grey, rounded-rectangular buttons. To the left and right of each button are black numbers.\n- The top button is positioned between the numbers **1** and **2**. It features two circular indentations, with the left one containing a black square icon.\n- The second button is between **3** and **4**, showing two empty circular indentations.\n- The third button is between **5** and **6**, also showing two empty circular indentations.\n- The bottom button is between **7** and **8**, showing two empty circular indentations.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/04990f6f4d538401ec4c5df2af737f5759b21c662fb815054be8524813a025ce.jpg)

# 6.16. SMBus Header

SMBus: additional SMBus from module

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P3V3_SM</td></tr><tr><td>2</td><td>SMB_DAT_O</td></tr><tr><td>3</td><td>SMB_CLK_O</td></tr><tr><td>4</td><td>GND</td></tr></table>

1324

# 6.17. I2C Header

I2C: additional I2C from module

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P3V3_I2C</td></tr><tr><td>2</td><td>I2C_DAT_O</td></tr><tr><td>3</td><td>I2C_CLK_O</td></tr><tr><td>4</td><td>GND</td></tr></table>

132

# 6.18. Fan Header

FAN\_COMe: Module controlled Fan

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image is a line drawing of a four-story building layout. On the far left, the numbers **1**, **2**, **3**, and **4** are stacked vertically. Next to these numbers is a tall, narrow rectangle divided horizontally into two sections, representing a staircase. To the right of the staircase is the main building structure. The top floor (level 4) features a door adjacent to the staircase and a square window on the far right. The three lower floors (levels 1, 2, and 3) each feature a single square window aligned vertically on the right side of the building.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/9919facdf01560941f853e8e52c8bfd447a58980f36665c93ca21f091be066fc.jpg)

FAN\_1: SIO6126D controlled FAN 1

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image displays a simple line drawing with three vertical columns aligned in rows.\n\n*   **Left Column:** The numbers '1', '2', '3', and '4' are listed vertically from top to bottom.\n*   **Middle Column:** A tall, thin rectangle is divided horizontally by three lines, creating four distinct sections corresponding to the rows.\n*   **Right Column:** Four squares are stacked vertically, aligned with the numbers and the middle rectangle's sections.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/c88d7b86b80c1ccbd37f595c8895e38906f181bf6c4a0ed197c0ac9bd2f07429.jpg)

FAN\_2: SIO6126D controlled FAN 2

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image is a schematic diagram showing a section of a building layout. On the far left, the numbers **1**, **2**, **3**, and **4** are stacked vertically. Next to these numbers is a rectangular symbol with a vertical line, representing an elevator car. To the right of the elevator is a horizontal corridor containing four small squares aligned along the bottom wall. Above the corridor is a solid black rectangular area, and to the right of the corridor is a large, empty rectangular space.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/272d78d8ce918e5cad8029562bd040335dc9cbb704878d3c6c42a581d44b8db3.jpg)

# 6.19. General Purpose SPI Header

GP\_SPI: General Purpose SPI for widely used interfaces

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>GP_SPI_CS0#</td><td>4</td><td>SPI0_DIN</td></tr><tr><td>5</td><td>NC</td><td>6</td><td>SPI0_CLK</td></tr><tr><td>7</td><td>SPI0_DO</td><td>8</td><td>GND</td></tr></table>

![The image displays a section of a keypad or interface featuring eight grey, pill-shaped buttons arranged in four rows.\n\n- **Text:** The numbers 1, 3, 5, and 7 are positioned vertically to the left of the left column of buttons. The numbers 2, 4, 6, and 8 are positioned vertically to the right of the right column of buttons.\n- **Visuals:**\n    - The buttons in the left column (aligned with 1, 3, 5, 7) contain black outlines of shapes: the top button contains a square, and the three buttons below it contain circles.\n    - The buttons in the right column (aligned with 2, 4, 6, 8) appear to be plain grey ovals without any internal symbols.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/38daeb0d97353ce561ef7f65e46031cbee46089f1c9e18a6e9a1b844fc36930b.jpg)

# 6.20. Front Panel Control

FRONT\_PANEL: Power Button, Reset Button, HDD LED, Power LED for front panel header

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>5VSB</td><td>2</td><td>PWR_LED_P</td></tr><tr><td>3</td><td>UID_LED_N</td><td>4</td><td>FAN_FAIL_LED_N</td></tr><tr><td>5</td><td>UID_LED_P</td><td>6</td><td>PWR_LED_N</td></tr><tr><td>7</td><td>SLED_G</td><td>8</td><td>HDD_LED_P</td></tr><tr><td>9</td><td>SLED_R</td><td>10</td><td>HDD_LED_N</td></tr><tr><td>11</td><td>LAN1_LED_P</td><td>12</td><td>PWR_BUT_P</td></tr><tr><td>13</td><td>LAN1_LED_N</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>SENSOR_SDA</td><td>16</td><td>RST_BUT_P</td></tr><tr><td>17</td><td>SENSOR_SCL</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>CASE_OPEN_N</td><td>20</td><td>R_UID_BUT_P</td></tr><tr><td>21</td><td>LAN2_LED_P</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>LAN2_LED_N</td><td>24</td><td>NMI_SW</td></tr></table>

![The image displays a central column of 12 grey, rounded rectangular icons flanked by two columns of numbers.\n\nThe left column lists even numbers vertically: 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24.\nThe right column lists odd numbers vertically: 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23.\n\nThe topmost icon in the center contains a small white square. The remaining 11 icons each contain two small white dots arranged horizontally.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/4e254aa009878ff45999cb723225e26ed40a7fd96b33ea119a511b04a4204a5e.jpg)

# 6.21. Panel Connector

LVDS Panel connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>LVSD_I2C_DAT</td><td>2</td><td>LVSD_I2C_CK</td></tr><tr><td>3</td><td>N.C</td><td>4</td><td>N.C</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>LVDS_A0-</td></tr><tr><td>7</td><td>LVDS_A0+</td><td>8</td><td>LVSD_VDD_EN</td></tr><tr><td>9</td><td>LVDS_A1-</td><td>10</td><td>LVDS_A1+</td></tr><tr><td>11</td><td>LVSD_BKLT_EN</td><td>12</td><td>LVDS_A2+</td></tr><tr><td>13</td><td>LVDS_A2-</td><td>14</td><td>N.C</td></tr><tr><td>15</td><td>LVDS_A_CK-</td><td>16</td><td>LVDS_A_CK+</td></tr><tr><td>17</td><td>N.C</td><td>18</td><td>LVDS_A3+</td></tr><tr><td>19</td><td>LVDS_A3-</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>LVDS_B0-</td><td>22</td><td>LVDS_B0+</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>LVDS_B1-</td></tr><tr><td>25</td><td>LVDS_B1+</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>LVDS_B2-</td><td>28</td><td>LVDS_B2+</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>LVDS_B_CK+</td></tr><tr><td>31</td><td>LVDS_B_CK-</td><td>32</td><td>N.C</td></tr><tr><td>33</td><td>LVDS_B3+</td><td>34</td><td>LVDS_B3-</td></tr></table>

![The image shows a tall black rectangle containing two vertical columns of white dots. The number '1' is at the top left, '2' is at the top right, '33' is at the bottom left, and '34' is at the bottom right.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/57ed69ca4f68dee921960bb6752b046a783599c4736a273fd0ee4435165538fe.jpg)

Smart Battery Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>Panel PWR</td></tr><tr><td>3</td><td>Backlight CTRL</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>Backlight Enable</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>Backlight PWR</td></tr></table>

![The image features a black rectangular panel centrally positioned between four vertical white bars. Each bar displays a single black digit. From left to right, the numbers are '1', '2', '7', and '8'.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a44305d5559db44f6329931c7586c04893fd64f84e665ff263e319f457625d09.jpg)

# 6.22. Battery Connector

Smart Battery Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>I2C_CK</td><td>2</td><td>I2C_DAT</td></tr><tr><td>3</td><td>PWRBTN#</td><td>4</td><td>BATLOW#</td></tr><tr><td>5</td><td>PS_ON#</td><td>6</td><td>SUS_S45#</td></tr><tr><td>7</td><td>+12V</td><td>8</td><td>+5VSB</td></tr><tr><td>9</td><td>SUS_STAT#</td><td>10</td><td>GND</td></tr></table>

![The image shows a vertical black rectangle containing eight white dots arranged in two columns of four. The corners are labeled with white numbers: '1' at the top left, '2' at the top right, '9' at the bottom left, and '10' at the bottom right.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/280bd8acf44bf7eec35fd5b1a9eed85bdc85e80ab9b2244ec34575554b7aed13.jpg)

# 6.23. Power Connectors

# ATX\_24: ATX 24-pin Power Connector

Connect the ATX 24-pin (or 20-pin) connector to supply power to COM Express Base R3.1 carrier.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>13</td><td>+3.3V</td></tr><tr><td>2</td><td>+3.3V</td><td>14</td><td>-12V</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>COM</td></tr><tr><td>4</td><td>+5V</td><td>16</td><td>PWR_ON</td></tr><tr><td>5</td><td>GND</td><td>17</td><td>COM</td></tr><tr><td>6</td><td>+5V</td><td>18</td><td>COM</td></tr><tr><td>7</td><td>GND</td><td>19</td><td>COM</td></tr><tr><td>8</td><td>PWR_GOOD</td><td>20</td><td>-5V</td></tr><tr><td>9</td><td>+5VSB</td><td>21</td><td>+5V</td></tr><tr><td>10</td><td>+12V</td><td>22</td><td>+5V</td></tr><tr><td>11</td><td>+12V</td><td>23</td><td>+5V</td></tr><tr><td>12</td><td>+3.3V</td><td>24</td><td>COM</td></tr></table>

![| Power Supply | Pin Number |\n| ------------ | ---------- |\n| +3.3 V       | 13         |\n| -12 V        | 14         |\n| COM          | 15         |\n| PWR_ON       | 16         |\n| COM          | 17         |\n| COM          | 18         |\n| COM          | 19         |\n| -5 V         | 20         |\n| +5 V         | 21         |\n| +5 V         | 22         |\n| +5 V         | 23         |\n| COM          | 24         |\n| Ground       | 1          |\n| +5 V        | 2          |\n| Ground       | 3          |\n| Ground       | 4          |\n| Ground       | 5          |\n| Ground       | 6          |\n| Ground       | 7          |\n| Ground       | 8          |\n| PWR_GOOD     | 9          |\n| +5 V_SB      | 10         |\n| +12 V       | 11         |\n| +12 V       | 12         |\n| +3.3 V       | 13         |](.express-base6-r3-1-manual-50m-77107-1000-10-231030/02d5a07277c3b5470765ba7686b89246f77d91ad416e9aa572547cb1010c0000.jpg)

# ATX\_4: ATX 12V 4-pin Connector.

Connect the ATX 12V 4-pin connector to supply power to the COM Express Base R3.1 carrier

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>+12V</td></tr><tr><td>4</td><td>+12V</td></tr></table>

![The image displays a 2x2 grid of shapes enclosed within a square border. Inside the grid:\n*   **Top-left:** A square with a semi-circular indentation on its left side.\n*   **Top-right:** A plain square.\n*   **Bottom-left:** A plain square.\n*   **Bottom-right:** A square with a semi-circular indentation on its right side.\n\nSurrounding the grid are numbers and a bracket:\n*   On the left side, the number **2** is aligned with the top row, and the number **1** is aligned with the bottom row.\n*   On the right side, the number **4** is aligned with the top row, and the number **3** is aligned with the bottom row.\n*   A vertical bracket is positioned to the right of the grid.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/8199af729f5778af054eb160477d69f1d8fe341696249fb0a3652462856d0641.jpg)

# 6.24. Carrier EEPROM Address Switch

SW1: COM Express BASE6 R3.1 Carrier Board EEPROM address setting

Default Address: AEh

<table><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>A2</td><td>A1</td><td>A0</td><td>R/W</td></tr><tr><td colspan="8">MSB LSB</td></tr></table>

<table><tr><td>SW1</td><td>I2C EEPROM_U53</td></tr><tr><td>1-8</td><td>A2_OFF</td></tr><tr><td>2-7</td><td>A1_OFF</td></tr><tr><td>3-6</td><td>A0_OFF</td></tr></table>

![The image shows a row of four white DIP switches set against a black background. Above the switches, the text 'ON DIP' is printed in white. Below the switches, the numbers '1 2 3 4' are printed in white, corresponding to each switch from left to right.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/bab3186d79bfcbb03a4c89b64c4f2408fb90109a1b2d91c50b59bda00f740c3c.jpg)

# 6.25. Other Jumpers

JP33: Switching Module GPIO or SDIO signal workable.

<table><tr><td>JP33</td><td>Status</td></tr><tr><td>1-2</td><td>SD_CARD workable (default)</td></tr><tr><td>2-3</td><td>Module GPIO Header workable</td></tr></table>

![The image displays a vertical list on the left with the numbers 1, 2, and 3. To the right of these numbers is a vertical rectangular graphic. The upper portion of this graphic is black and contains two white dots arranged vertically. The lower portion is grey with a rounded bottom and contains a white square with a black dot in the center. The number 1 aligns with the top dot, 2 with the lower dot in the black section, and 3 aligns with the bottom grey section.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/51282b129616b9cd77fab4dcb72bd92debc27a490af42414bd5a9a5a9c3ee89c.jpg)

JP3: SIO I/O Address

<table><tr><td>JP3</td><td>Status</td></tr><tr><td>1-2</td><td>4Eh</td></tr><tr><td>2-3</td><td>2Eh (default)</td></tr></table>

![The image shows a vertical list of numbers 1, 2, and 3 aligned on the left side. To the right of these numbers is a vertical rectangular graphic. The top portion is a grey rounded rectangle containing a small white square. The bottom portion is a black rectangle containing two small white dots arranged vertically.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/8fa5998d0bfc3087c4384b390ea6482dabfaf8537813a23637525baf9d217e22.jpg)

JP6/JP7: BIOS Select

<table><tr><td>JP6</td><td>JP7</td><td>Status</td></tr><tr><td>1-2</td><td>1-2</td><td>Module SPI (default)</td></tr><tr><td>2-3</td><td>1-2</td><td>Carrier FWH</td></tr><tr><td>1-2</td><td>2-3</td><td>Carrier SPI0</td></tr><tr><td>2-3</td><td>2-3</td><td>Carrier SPI1</td></tr></table>

![The image displays two identical vertical, pill-shaped objects positioned side-by-side in the center against a white background. To the left of the first object and to the right of the second object are the numbers 1, 2, and 3 stacked vertically in black text.\n\nEach of the central objects has a black upper body with a rounded top, featuring two small white dots arranged vertically. Below the black section is a grey, rounded bottom cap containing a small black circle.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/5d43d8be7e63e55ec82fc7144a3c47a2bb8bf9a5a77a9b99c6460e658c91ca98.jpg)

JP27: LVDS Backlight Enable.

<table><tr><td>JP27</td><td>Status</td></tr><tr><td>1-2</td><td>Low Active</td></tr><tr><td>2-3</td><td>High Active (default)</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically in black text on the left side. To the right is a vertical, pill-shaped graphic. Its top portion is grey with a small square centered inside, and its bottom portion is black with two white dots arranged vertically inside it.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/24ad7fbc2cc8d92f880ca32b8631f19fa2fec052fb1ac45497aabf144e0dcdcc.jpg)

JP34: LVDS Backlight PWM Control Source.

<table><tr><td>JP34</td><td>Status</td></tr><tr><td>1-2</td><td>GPU</td></tr><tr><td>2-3</td><td>LVDS I2C (default)</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically on the left side. To their right is a tall, rounded rectangular bar. The top portion of the bar is grey and features a small square cutout in the center. The bottom portion is black and contains two white dots arranged vertically.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/c0dfbb6db805854adeee30125ef8f81fa12fac6ddde775b304a964b88d75e4f0.jpg)

JP35: LVDS Backlight control Mode.

<table><tr><td>JP35</td><td>Status</td></tr><tr><td>1-2</td><td>Voltage level</td></tr><tr><td>2-3</td><td>PWM (default)</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically on the left side in black font. To the right is a vertical rectangular strip with rounded top corners. The strip is divided into sections aligned with the numbers. The top section (aligned with 1) is grey and features a small white square outline in the center. The middle section (aligned with 2) is black with a small white dot. The bottom section (aligned with 3) is black with a small white dot.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/fa683cfffaf483471b88209055527c1c68146daa8260ae91803092a095c6a112.jpg)

JP28: LVDS Panel Power.

<table><tr><td>JP28</td><td>Status</td></tr><tr><td>1-2</td><td>3.3V (default)</td></tr><tr><td>2-3</td><td>5V</td></tr></table>

![The image displays the numbers 1, 2, and 3 stacked vertically on the left. To their right is a tall, black rectangular bar. Inside the upper portion of this bar are three white dots arranged vertically. At the bottom of the bar is a grey section containing a white square.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/853a13ca0e5554f5098123700f33fe7f8db6133437eccb3287d4beef8bccd617.jpg)

JP29: LVDS Panel Backlight Power.

<table><tr><td>JP29</td><td>Status</td></tr><tr><td>1-2</td><td>12V</td></tr><tr><td>2-3</td><td>5V (default)</td></tr></table>

![The image features the numbers 1, 2, and 3 stacked vertically on the left side. To the right is a vertical rectangular strip. The top portion of the strip is grey with a rounded top edge and contains a small white square. The remainder of the strip is black, and inside this black section, there are three white dots arranged vertically.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/4655bf4d1da2b25c84f6738aa9edb9788b4d62cd2081350dcbd5d6e4b93260d7.jpg)

JP31: Carrier Power Mode.

<table><tr><td>JP31</td><td>Status</td></tr><tr><td>1-2</td><td>ATX mode (default)</td></tr><tr><td>2-3</td><td>AT mode</td></tr></table>

![The image displays a diagram featuring the numbers 1, 2, and 3 stacked vertically on the left side. To their right is a vertical rectangular column divided into sections. The upper portion, aligned with numbers 1 and 2, has a black background containing two white dots stacked vertically. The lower portion, aligned with number 3, has a grey background containing a single white circle.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/66887f86e7e7ab786a31621b1edd3cfee5c12bbd955e480ba7e1e71cc81eba0b.jpg)

JP32: VCC\_12V On/Off during S3/S5 (In AT mode, put pin 2-3 to output 12V during S3/S5.)

<table><tr><td>JP32</td><td>Status</td></tr><tr><td>1-2</td><td>ATX to Module (default)</td></tr><tr><td>2-3</td><td>AT to Module</td></tr></table>

![The image displays a vertical column of the numbers 1, 2, and 3 on the left side. To the right is a black, rounded rectangular shape resembling a test tube. Inside this shape are three small white squares arranged vertically. The top two squares are against the black background, while the lowest square is situated within a grey-filled section at the base of the shape.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/add6791489e127ca54315e5ea1ec77e87d778f37ce67642c94005a4acf1fb954.jpg)

JP40: BIOS Boot Device Select.

<table><tr><td>JP32</td><td>Status</td></tr><tr><td>1-2</td><td>LPC Mode (default)</td></tr><tr><td>2-3</td><td>eSPI Mode</td></tr></table>

![The image displays the numbers 1, 2, and 3 arranged vertically on the left side. To their right is a vertical rectangular bar. The top portion of the bar is black and contains two white square dots, vertically aligned with the numbers 1 and 2. The bottom portion of the bar is grey and contains one white square dot, aligned with the number 3.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/72018318c0bdabf86ff2a102c80edc260b1ea1b887d5d8bdb9701503adc86c9f.jpg)

JP41/JP42: BIOS Boot Device Select.

<table><tr><td>JP41</td><td>JP42</td><td>Status</td></tr><tr><td>1-2</td><td>2-3</td><td>RS-232 (default)</td></tr><tr><td>2-3</td><td>1-2</td><td>RS-485</td></tr><tr><td>1-2</td><td>1-2</td><td>RS-422</td></tr></table>

![The image displays two columns of vertical bars, each aligned with the numbers 1, 2, and 3 on the left side.\n\n**Left Column:**\n*   **1:** A black vertical bar with a white dot near the center and a grey semi-circle at the bottom.\n*   **2:** A black vertical bar with a white dot near the center.\n*   **3:** A black vertical bar with a white dot near the center and a grey semi-circle at the bottom.\n\n**Right Column:**\n*   **1:** A vertical bar with a grey semi-circle at the top and a black body containing a white dot near the center.\n*   **2:** A black vertical bar with a white dot near the center.\n*   **3:** A black vertical bar with a white dot near the center and a grey semi-circle at the bottom.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a009f0095a6775ec69dc2014e71a8982cd25b9130f85cf0ef9aeed51316bc040.jpg)

JP43: SIO Enable and Disable.

<table><tr><td>JP43</td><td>Status</td></tr><tr><td>1-2</td><td>Enable SIO (default)</td></tr><tr><td>2-3</td><td>Disable SIO</td></tr></table>

![The image displays a vertical column of the numbers 1, 2, and 3 on the left side. To the right is a tall, narrow rectangular bar. The upper two-thirds of the bar are black, while the lower third is grey. Inside the black section, there are three white squares arranged vertically. Inside the grey section, there is a white square and a small white horizontal bar to its right.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/970c676cf8b37c52875991787b6fffaafee8f528b831a01688b8a14b2263b41b.jpg)

JP5: Clear CMOS

To clear CMOS, shut down the power and short pins 2 and 3 (short VBT to ground)

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>Normal &lt;&lt;&lt;</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr></table>

![The image displays a vertical sequence. On the left are the numbers '1', '2', and '3' stacked vertically. On the right is a vertical bar with three corresponding segments. The top segment (aligned with 1) is black with a white dot. The middle segment (aligned with 2) is black with a white dot. The bottom segment (aligned with 3) is grey with a white square outline.](.express-base6-r3-1-manual-50m-77107-1000-10-231030/a0efd3063a1736c39985aa408f646604281aa67e43b35fb3667d38d1d653978b.jpg)

# 7 Switches, POST, and LEDs

# 7.1. Switches (S0-S5)

There are two switches, at the center and lower-right of the carrier.

# PWR\_BTN

Indicates getting into S0 from S5 of the system.

![F_PANEL\nS3\n5VSB\nHDD\nPWR_ON\n160\nA18F\n72.00\n198F\nPWR_BTN\nF_2XUSB](.express-base6-r3-1-manual-50m-77107-1000-10-231030/86e96d0d41c9477f3af6be75c571df505cfe61470d412955a863cc658aab7d27.jpg)

# RST\_BTN

Indicates resetting of the system.

![RST_BTN\nJP5\nRTC](.express-base6-r3-1-manual-50m-77107-1000-10-231030/3441ab312a431821eb7394b54039d0ccd918c3f21feb948b022de84537b1808c.jpg)

# 7.2. POST and Inductor LEDs

An eSPI-based POST display is added for debugging.

The two 7-SEG LEDs shows the actual POST data.

![Close-up of a green printed circuit board with two 8-pin LED indicators and a PWR_BTN sensor (no readable text or symbols)](.express-base6-r3-1-manual-50m-77107-1000-10-231030/3b6b1601efc787b588cf1a973553ddc1eb4fc8498c4041f4cbe1d7822ec79d1c.jpg)

A row of mini-LEDs below the POST display indicates the following:

S3: Indicates S3 status

5VSB: ATX power attached on standby or active

HDD: Indicates HDD activity

PWR\_ON: Indicates power on

![S3\n5VSB\nHDD\nPWR_ON\nF PANEL](.express-base6-r3-1-manual-50m-77107-1000-10-231030/32eaee542305b823a65bb11c3ee6a0470796228bc3de8333f4d238a8f221593f.jpg)

# 7.3. ATX Power Connectors

The COM Express Base6 R3.1 has one ATX 24-pin connector to supply power to the carrier board and one ATX 12V 4-pin connector to supply power to the COM module.

The system will not power on unless an ATX 12V 4-pin connector is connected.

If your power supply has a 24-pin ATX connector, then attach the connectors as shown.

![FAN_COMc\nPLOTECH 6 94V-0\n08065-TB-B2544\n22\nJP31 Power Mode Select\n1:2\nATX Mode\n2:3\nATI Mode\nATX_24\nJP32\nJP31\nCN33\nATX_4\nBA\n1 2](.express-base6-r3-1-manual-50m-77107-1000-10-231030/9d1fc4005f145ae5ada9af40083e0631fc524c792a73b4fd1898143fd190a8ab.jpg)
[🔗 Link to the original document](.express-base6-r3-1-manual-50m-77107-1000-10-231030/express-base6-r3-1-manual-50m-77107-1000-10-231030.pdf)