# Express-DN7 # User's Manual COM Express Basic Size Type 7 Module with up to 16 cores Intel Atom® C3000 SoC (Denverton-NS) ![Close-up of a green printed circuit board with visible components and gold contacts (no readable text or symbols)](.express-dn7-50m-00049-1020-12/59fcf0b96d963110354ce73021dd30bea1251ff82cdd8bf4b9987d2701029db0.jpg) COM Express® Manual Rev.: 1.2 Revision Date: October 6, 2021 Part Number: 50M-00049-1020 # Preface # Copyright Copyright © 2018, 2019, 2021 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. Battery Labels (for products with battery) ![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.express-dn7-50m-00049-1020-12/31f1a453fb6386596358e5a021407467d7b51002e4fc8f0ebb967a65106eab87.jpg) ![The image displays a black-and-white line drawing of the standard recycling symbol (the Mobius loop). It features three chasing arrows forming a triangle, enclosed within a square border with rounded corners. There is no text present in the image.](.express-dn7-50m-00049-1020-12/8565fdeebb42778146d243b311e07b18e15d218f6116a6454c209b5cf78926ef.jpg) Li-ion ![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.express-dn7-50m-00049-1020-12/f4f479b710c7b69c3e2568b32cfdfef7e119d5b570e5e5ecdf8eaf193cb93e9d.jpg) ![The image displays a black square icon with rounded corners. Inside the black border, four white arrows point outward toward each of the four corners, intersecting in the center to form an 'X' shape. This is a standard icon representing 'expand' or 'fullscreen.'](.express-dn7-50m-00049-1020-12/e19a9835064f504b60aafa3c4508d545a9c4becfbd4bd57bf29719e857c7d4db.jpg) 廢電池請回收 # California Proposition 65 Warning ![A yellow triangular warning sign with a thick black border and a black exclamation point in the center.](.express-dn7-50m-00049-1020-12/726c3e156586c7349a2d51d2463594fa1d837dd5306cb08750341b3847a70092.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. Revision History

Revision	Description	Date	By
1.0	Initial release	2018-09-14	JC
1.1	Update specifications, pin descriptions, BMC codes, BIOS	2019-03-29	JC
1.2	Update BIOS, Fixed I/O Address Range Map	2021-10-06	JC

# Table of Contents Preface....ii List of Figures ......v List of Tables......vi 1. Introduction......1 2. Specifications ....3 2.1. Core System....3 2.2. Expansion Busses ....4 2.3. 10GBASE-KR 4 2.4. Gigabit Ethernet....5 2.5. NC-SI 5 2.6. Multi I/O and Storage....5 2.7. Serial I/O on Module 6 2.8. Trusted Platform Module (TPM) 7 2.9. SEMA Board Controller 7 2.10. Debug....7 2.11. Power Specifications....7 2.12. Power Consumption 7 2.13. Operating Temperatures 8 2.14. Environmental 8 2.15. Specification Compliance 8 2.16. Operating Systems 8 2.17. Functional Diagram 9 2.18. Mechanical Drawing 10 3. Pinouts and Signal Descriptions....11 3.1. AB/CD Pin Definitions....11 3.2. Signal Description Terminology....14 3.3. AB Signal Descriptions 15 3.4. CD Signal Descriptions....24 4. Connector Pinouts on Module....31 4.1. Connector, Switch and LED Locations 31 4.2. 40-pin Debug Connector....33 4.3. Status LEDs....34 4.4. MIPI60 Debug Header 35 4.5. Fan Connector 36 4.6. BIOS Setup Defaults Reset Button....37 4.7. Switch Settings 38 4.8. PCIe x8-to-two-x4 Adapter Card....39 # 5. Smart Embedded Management Agent (SEMA) 41 5.1. Board Specific SEMA Functions (update later) 42 # 6. System Resources ....45 6.1. System Memory Map....45 6.2. Direct Memory Access Channels....45 6.3. Fixed I/O Address Range Map 45 6.4. Variable I/O Address Range Map 47 6.5. APIC Interrupt Mapping 47 6.6. PCI Configuration Space Map 48 6.7. PCI Interrupt Routing Map....49 6.8. SMBus Address Table....49 # 7. BIOS Setup....51 7.1. Menu Structure 51 7.2. Main 52 7.3. IntelRCSetup 54 7.4. Advanced....76 7.5. Event Logs....91 7.6. Security....92 7.7. Boot 93 # 8. BIOS Checkpoints, Beep Codes......95 8.1. Status Code Ranges....96 8.2. Standard Status Codes....96 8.3. OEM-Reserved Checkpoint Ranges....103 # 9. Mechanical Information....105 9.1. Board-to-Board Connectors.... 105 9.2. Thermal Solution....106 9.3. Mounting Methods ...... 109 9.4. Standoff Types....110 # Safety Instructions....111 # Getting Service....112 # List of Figures Figure 1: Express-DN7 Functional Block Diagram....9 Figure 2: Express-DN7 Mechanical Drawing .... 10 Figure 3: Express-DN7 Connector, Switch and LED Locations.... 31 Figure 4: Express-DN7 and the DB40 Debug Module 32 Figure 5: cExpress Switch Locations .... 38 Figure 6: COM Express Mounting Methods....109 Figure 7: COM Express Standoff Types.... 110 # List of Tables Table 1: Express-DN7 AB/CD Pin Definitions.... 11 Table 2: 40-pin Debug Connector Pin Definition.... 33 Table 3: Express-DN7 LED Descriptions ...... 34 Table 4: MIPI60 Debug Header Pin Definition .... 35 Table 5: Fan Connector Pin Definition ...... 36 Table 6: BIOS Select and Mode Configuration Switch Settings.... 38 Table 7: SEMA Onboard Voltage Monitor 42 Table 8: SEMA BMC Status 42 Table 9: SEMA Exception Codes....43 Table 10: SEMA BMC Flags....44 # 1. Introduction The Express-DN7 is a COM Express® COM.0 R3.0 Basic Size Type 7 module supporting the 64-bit Intel Atom® C3000 processor (formerly “Denverton-NS”) system-on-chip (SoC). 16 CPU cores with 31W TDP and integrated 10G Ethernet make the Express-DN7 especially suited for customers who need excellent computing performance with low power consumption, such as edge computing applications, in a long product life solution. The Express-DN7 features Intel® Quick Assist Technology (cryptographic and compression acceleration), Intel® Virtualization Technology (including VT-x, VT-d), Intel® AES-NI Technology, and DDR4 ECC (or non-ECC) dual-channel memory at 1866/2133/2400 MHz (dependent on SoC SKU) to provide excellent overall performance. In addition, the Express-DN7 has up to three SODIMM sockets that are fully compliant with the COM Express mechanical specification. An integrated Intel® 10G Ethernet controller supports a maximum of four 10GBASE-KR interfaces, relevant sideband signals and NC-SI. The Express-DN7 is designed to serve customers with optimized computing capability per watt and high speed connectivity requirements who want to outsource the custom core logic of their systems for reduced development time. Input/output features include expanded PCIe bandwidth up to two PCIe x8 Gen3 lanes, a single onboard Gigabit Ethernet port with IEEE 1588 support suitable for real-time applications, USB 3.0/2.0 ports, and SATA 6 Gb/s ports. Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer. This page intentionally left blank. # 2. Specifications # 2.1. Core System

CPU	Intel Atom® processor C3000 SoC, 14nm (formerly Denverton-NS)Intel Atom® C3808 2.0GHz 25W (12C/2133MHz, 20HSIO, eTEMP)Intel Atom® C3708 1.7GHz 17W (8C/2133MHz, 20HSIO, eTEMP)Intel Atom® C3508 1.6GHz 12W (4C/1866MHz, 8HSIO, eTEMP)Intel Atom® C3308 1.6/2.1GHz 10W (2C/1866MHz, 6HSIO, eTEMP)Intel Atom® C3958 2.0GHz 31W (16C/2400MHz, 20HSIO, by request)Intel Atom® C3858 2.0GHz 25W (12C/2400MHz, 20HSIO, by request)Intel Atom® C3758 2.2GHz 25W (8C/2400MHz, 20HSIO, by request)Intel Atom® C3558 2.2GHz 16W (4C/2133MHz, 12HSIO, by request)Intel Atom® C3538 2.1GHz 15W (4C/2133MHz, 12HSIO, by request)Intel Atom® C3338 1.5/2.2GHz 9W (2C/1866MHz, 10HSIO, by request)Supporting: Intel® Quick Assist Technoloty (cryptographic and compression acceleration), Intel® VT (including VT-x, VT-d, VT-x with Extended Page Tables), Intel® Turbo Boost Technology 2.0, Intel® SSE4.2, Intel® 64 Architecture, Intel® ISA compatibility, Intel® Execurt Disable Bit, Intel® OS Guard, Intel® Secure Key, Intel® AES-NI, Intel® Security Hash Algorithm Extensions (SHA-1, SHA-256)Notes:Availability of features may vary between processor SKUs.SoC SKUs not listed above or marked “by request” are supported by project basis.Please contact your local ADLINK representative.
Cache	16MB for C3708/C3958/C3758, 12MB for C3808/C3858, 8MB for C3508/C3558/C3538, 4MB for C3308/C3338
Memory	Dual channel ECC (or non-ECC) 1866/2133/2400 MHz DDR4 memory up to 48GB in three SODIMM sockets (support for 96GB is under verification)Notes:Supported memory frequencies may vary between processor SKUs.The $3^{rd}$ SODIMM on the module’s bottom side is supported by project basis. Please contact local sales.C3308/C3338 only support one channel in the lower SODIMM socket on top side.
Embedded BIOS	AMI Aptio 5 EFI with CMOS backup in 16MB SPI BIOS
Chipset	Integrated in SoC

# 2.2. Expansion Busses

PCI Express

Up to 1 PCI Express x8 Lanes Gen3 (CD):Lanes 16-23: four controllers/root ports, can be configured to x8, x4, x2, x1 (connected to PCIe Cluster 1 which has four root ports RP 4/5/6/7)Up to 1 PCI Express x8 Lanes Gen3 (AB & CD):Lanes 0-7: four controllers/root ports, can be configured to x8, x4, x2, x1 (dependent on GbE support, connected to PCIe Cluster 0 which has four root ports, RP 0/1/2/3)Notes:Number of PCIe lanes depends on SoC SKUs. Refer to 2.6 Multi I/O and Storage for detailed infoRoot port 3 (PCIe lanes 6/7) is connected to GbE controller by default; support for PCIe lanes 6/7 is by build option.Although the Denverton-NS platform supports four roots on Lanes 0-7, the PICMG COM.0 R3.0 specification for Lanes 0-7 states: “Type 7 module may support eight x1 root hubs. It is expected that future generation products may limit the number of available root hubs.”

Other

LPC busSMBus (system) $I^{2}C$ (user)

# 2.3. 10GBASE-KR

Integrated on Processor

Intel® 10G Ethernet Controller (two controllers)

10GbE Feature Support

Four 10GBASE-KR ports (on CD connector)Sideband signals (on CD connector) for 10GbENotes:10GBASE-KR ports 0, 1 are from LAN controller 0, 10GBASE-KR ports 2, 3 are from LAN controller 1Maximum combined throughput on all four ports is 20Gb/s<img src="images/ad71ef3be96102f1dca0525166ba34f1cc441aca887a69cd5f1da165fb3e9fc7.jpg"/><img src="images/1f2d1217cb4ef08599905af7148f504d45cb95fb45c451d611355d9ae4c7ef03.jpg"/>Note:The default 10GbE firmware supports four ports optical fiber PHY. Support for 10GBASE-T (copper PHY) is by project basis.

# 2.4. Gigabit Ethernet

Intel Controller	Intel® i210 Ethernet Controller, IEEE 1588 PTP support
Interface	10/100/1000 Mbit/s connection

Note: GbE0\_SDP pin (A49) is supported. # 2.5. NC-SI ● NC-SI (on AB connector): manageability interface, connecting to IPMI BMC located on carrier board - Routing from Intel® i210 Ethernet Controller to row AB connector # 2.6. Multi I/O and Storage

I/O Hub	Integrated on SoC
USB	Up to 2x USB 3.0/2.0 (USB 0,1), 2x USB 2.0 (USB 2,3)
SATA*	Up to 2x SATA 6Gb/s (SATA 0,1)
GPIO	4 GPO and 4 GPI (GPI with interrupt)
eMMC 5.0 (build option)	8/16/32/64GB (boot-up device functionality supported by project basis)

\*Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board. # I/O Support of SoC SKUs C3808, C3708, C3958, C3858, C3758 20 HSIO, 2CH DDR4 max., 48 GB DDR4 ![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Top Section (PCIe Layouts & Interfaces)**\n* **Main Columns:** Four columns labeled **B1**, **B3**, **B4**, and **B2**.\n* **Rows:**\n * Each column has an **x8** block at the top.\n * Below the x8 blocks, **B1** and **B3** have **x4** blocks (colored yellow). **B4** and **B2** have **x4** blocks (white).\n * The bottom rows break these down into **x2** and **x1** blocks. The blocks under **B1** and **B3** are colored yellow; the blocks under **B4** and **B2** are white.\n* **Interface Blocks (Top Right):**\n * **SATA** with blocks **0**, **1**.\n * **USB 3.0 upgrade** with blocks **0**, **1**, **2**, **3**.\n * **USB 2.0** with blocks **0**, **1**, **2**, **3**.\n* **Annotation:** The text **last PCIe port for GbE** is positioned below the main grid, with dashed arrows pointing downward.\n\n**Bottom Section (Layouts & Definitions)**\n* **Left Grid:** A smaller grid labeled **B1** showing an **x8** block, two **x4** blocks, four **x2** blocks, and four **x1** blocks (all colored yellow). Below this grid is the text **no GbE**.\n* **Center Text Box:** 'Dual layout supports default GbE using last PCIe port in the B1 bucket, alternative is no GbE but full PCIe x8 on B1'.\n* **Right Text Box:**\n * 'B1: ports 0-7'\n * 'B3: ports 16-23'\n * 'B4: ports 24-31'\n * 'B2: ports 8-15'\n\n**Legend and Notes**\n* **Yellow Square:** 'compliant with PICMG definition'.\n* **Light Yellow Square:** 'Supported by Express-DN7 design, please note the description from PICGM specification below before using these po'.\n* **Additional Text:** 'Type 7 modules may support more x1 root hubs in bucket one (B1). It's expected that future generation products may limit the number of available root hubs on the bucket one (B1) to 2.'](.express-dn7-50m-00049-1020-12/d5a2ca6c0182ca5d96174961f02b027aefd2b8fc53d1b57d76d8d1656a837fe1.jpg) C3558, C3538 12 HSIO, 2CH DDR4, max. 48 GB DDR4 ![This diagram illustrates a PCIe lane layout and port configuration, likely for a motherboard or expansion card.\n\n**Main Grid (Top Left)**\n* **Headers:** The top row features blocks labeled **B1**, **B3**, **B4**, and **B2**.\n* **Lanes:** Below the headers is a hierarchical grid of blocks representing lane widths:\n * A row of four blocks labeled **x8**.\n * A row of eight blocks labeled **x4**.\n * A row of sixteen blocks labeled **x2**.\n * A bottom row of thirty-two blocks labeled **x1**.\n* **Highlighting:** Various blocks in this grid are highlighted in shades of yellow/orange, indicating active connections.\n\n**Top Right Headers**\n* **SATA:** A block labeled **SATA** containing sub-blocks **0** (highlighted yellow) and **1**.\n* **USB 3.0 upgrade:** A block labeled **USB 3.0 upgrade** containing sub-blocks **0**, **1**, **2**, and **3**.\n* **USB 2.0:** A block labeled **USB 2.0** containing sub-blocks **0**, **1** (highlighted yellow), **2**, and **3**.\n\n**Bottom Left Box**\n* A smaller grid labeled **B1** at the top.\n* Inside, it shows a hierarchy: **x8** (yellow), **x4** (yellow), **x2** (light yellow), and a bottom row of **x1** blocks (alternating orange and white).\n* Below this grid is the text **no GbE**.\n\n**Text Box and Connections**\n* A dashed arrow points downward from the main grid (specifically the bottom row of the B1 column) to the bottom left box. The label on this arrow is **last PCIe port for GbE**.\n* A solid arrow points from the text **last PCIe port for GbE** to a text box on the right.\n* The text box contains the following explanation: **Dual layout supports default GbE using last PCIe port in the B1 bucket, alternative is no GbE but full PCIe x8 on B1**](.express-dn7-50m-00049-1020-12/353e1f3b12e67f276061991e018dd0ac0cafcde8e9698e6bb97085021be752c2.jpg) # C3338 10 HSIO, 1CH DDR4, max. 16 GB DDR4

last PCIe port for GbE

SATA		USB 3.0 upgrade				USB 2.0
0	1	0	1	2	3	0	1	2	3

B1
x8
x4		x4
x2	x2	x2	x2
x1	x1	x1	x1

no GbE

Dual layout supports default GbE using last PCIe port in the B1 bucket, alternative is no GbE but full PCIe x8 on B1

# C3508 8 HSIO, 2CH DDR4, max. 48 GB DDR4

last PCIe port for GbE

SATA		USB 3.0 upgrade				USB 2.0
0	1	0	1	2	3	0	1	2	3

# C3308 6 HSIO, 1CH DDR4, max. 16 GB DDR4

last PCIe port for GbE

SATA		USB 3.0 upgrade
0	1	0	1	2	3

Note: PCIe configurations not listed in standard BIOS setting can be supported by project basis. Please contact your local ADLINK representative. # 2.7. Serial I/O on Module ● Chipset: Nuvoton NCT5104D Note: two UART ports native from SoC instead of NCT5104D supported by build option - Ports: 2x UARTs Rx/Tx only - Console Redirection: COM 1 or COM 2 selectable in BIOS

COM Port	Description	IRQ	Address	Console redirection support
COM 1	Supported by module (SER0, A98/A99), via NCT5104D	4	0x3F8	YES
COM 2	Supported by module (SER1, A101/A102), via NCT5104D	3	0x2F8	YES
COM 3	Supported by Super I/O (W83627DHG) on carrier board	5	0x240	YES
COM 4	Supported by Super I/O (W83627DHG) on carrier board	7	0x248	YES

Note: NCT5104D is 16550-compatible and it supports up to 1.5Mb/s (baud rate at 24MHz) # 2.8. Trusted Platform Module (TPM) - Chipset: Infineon (TPM is supported by build option) - Type: TPM 2.0 # 2.9. SEMA Board Controller ● Type: ADLINK Smart Embedded Management Agent (SEMA) - Functions: • Voltage/Current monitoring • Power sequence debug support • AT/ATX mode control • Logistics and forensic information - Flat panel control (not supported on this product, as the platform has no GPU) - General purpose I2C • Failsafe BIOS (dual BIOS) • Watchdog timer and fan control # 2.10. Debug - 40-pin flat cable connector to be used with DB-40 debug module Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs ● MIPI60 header for debug of SoC (build option) # 2.11. Power Specifications

Power Modes	AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
Standard Voltage Input	ATX @ 12V±5%,/ 5Vsb ±5% or AT @ 12V ±5%
Wide Voltage Input	ATX @ 8.5-20V, 5Vsb ±5% or AT @ 8.5-20V
Power Management	ACPI 5.0 compliant, Smart Battery support
Power States	Supports C0, C1, C2, C3, S0, S4, S5, S5 ECO mode(Wake-on-USB S4, WOL S4/S5)
ECO Mode	Supports deep S5 for 5Vsb power saving

# 2.12. Power Consumption Please contact your ADLINK representative for the document "COM Express Module Power Consumption". # 2.13. Operating Temperatures

Standard Operating Temperature	0°C to +60°C (Wide Voltage Input)Storage: -20°C to +80°C
Extreme Rugged Operating Temperature (optional)	-40°C to +85°C (Standard Voltage Input, only for eTEMP SKUs, by build option, TBC)Storage: -40°C to +85°C

# 2.14. Environmental

Humidity	Operating: 5-90% RH, non-condensingStorage: 5-95% RH (and operating with conformal coating)
Shock and Vibration	IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D
HALT	Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

# 2.15. Specification Compliance ● PICMG COM.0: Rev 3.0 Type 7, Basic size 125 x 95 mm # 2.16. Operating Systems

Standard Support	• Windows Server 2012/2016 (64-bit)• Yocto project based Linux(64-bit)
Extended Support (BSP)	• Yocto project based Linux (64-bit)

# 2.17. Functional Diagram ![This block diagram illustrates the architecture of an **Intel® Atom® C3000 'Denverton-NS'** system.\n\n**Central Component:**\nThe core of the diagram is the **Intel® Atom® C3000 'Denverton-NS'** block.\n\n**Left Side Connections (Vertical Bar 'AB'):**\n* **Memory:** Three blocks labeled **SODIMM 1**, **SODIMM 2**, and **SODIMM 3** are listed. Each contains the text 'Up to 2400 MHz' and '4-16 GB ECC/non-ECC DDR4'.\n * **SODIMM 1** connects to **CH_A**.\n * **SODIMM 2** connects to **CH_B**.\n * **SODIMM 3** connects via a dotted line.\n * Text below reads: 'Note: Memory frequency dependent on SoC SKU'.\n* **Peripherals:**\n * **Up to 6 PCIe lanes (Gen3)** connects to the left bar. Text: '(ports 0-5, B1, 3 controllers)'.\n * **2x SATA 6Gb/s** connects to the left bar. Text: '(port 0/1)'.\n * **NC-SI** connects from **GbE Controller** to the left bar.\n * **GbE Controller** connects to the central block (via dotted line) and the left bar.\n * **4 x USB 2.0** connects to the left bar. Text: '(ports 0/1/2/3)'.\n * **UART0/1** connects from **LPC to UART NCT5014D** to the left bar.\n * **LPC to UART NCT5014D** connects to the central block (via dotted line).\n * **Debug header**, **TPM 2.0**, and **LPC bus** are interconnected. **LPC bus** connects to the central block (via dotted line).\n * **SMBus** connects the central block to **GPIO PCA9535**.\n * **GPIO PCA9535** connects to the left bar with text '4x GPO, 4x GPI'.\n * **GP I2C** connects **GPIO PCA9535** to the left bar.\n * **SPI_CS#** and **SPI** connect **New SEMA BMC** to the left bar.\n\n**Right Side Connections (Vertical Bar 'CD'):**\n* **MIPI60 header** connects bidirectionally to the central block. Text: 'By BOM option'.\n* **LAN_Controller_0** connects to **2x 10G KR ports**, which then connects to the right bar.\n* **LAN_Controller_1** connects to **2x 10G KR ports**, which then connects to the right bar.\n* **10G Sideband Signals** connects to the right bar. Text: 'Note: 10G KR bandwidth dependent on SoC SKU'.\n* **Up to 1 PCIe x8 lanes (Gen3)** connects to the right bar. Text: '(ports 16-23, B3, 4 controllers)'.\n* **Up to 2 PCIe lanes (Gen3)** connects via a dotted line to the right bar. Text: '(ports 6-7, B3, 1 controller)'.\n* **Up to 2x USB 3.0 upgrade** connects to the right bar. Text: '(port 0/1)'.\n* **eMMC 5.0** connects via a dotted line from the central block. Text: '8/16/32/64GB'.\n\n**Bottom Right Section:**\n* **New SEMA BMC** connects to **SMBus** (via dotted line from central block), **GPIO PCA9535**, and three blocks below it:\n * **SPI 0 BIOS**\n * **SPI 1 BIOS**\n * **LM73 Sensor**](.express-dn7-50m-00049-1020-12/42621fecfd833b6fe47ca53adf7830b97cf26384d6bf14536839eb94f5741473.jpg) Figure 1: Express-DN7 Functional Block Diagram Note: I/O dependent on the specific SoC SKU, described in 2.6 Multi I/O and Storage above. # 2.18. Mechanical Drawing ![The image displays a technical engineering drawing consisting of two sections: a 'Top View' and a 'Side View.'\n\n**Top View**\nThis section shows the layout of a rectangular board with various dimensions and features:\n* **Text:** 'Top View' and 'connector on bottom side'.\n* **Dimensions (Left/Vertical):** 95, 91 (top), 75.32 (center), 28.33, 18, 6, 4, 0 (bottom left).\n* **Dimensions (Bottom/Horizontal):** 0, 4, 16.50, 40.67, 70.14, 74.20, 80.\n* **Dimensions (Right/Vertical):** 121, 125.\n* **Visual Elements:** Four horizontal rows of slots are visible in the lower-left quadrant. Four vertical slots are aligned on the right side. Circular mounting holes are located at the corners and the center.\n\n**Side View**\nThis section shows the profile of the object below the top view:\n* **Text:** 'Side View'.\n* **Dimensions:** '2' (left, indicating thickness), '4' and '8' (right side, indicating heights), and '4' (bottom right corner).\n* **Visual Elements:** A long, thin horizontal profile representing the board, with connector details visible on both the left and right ends.](.express-dn7-50m-00049-1020-12/6252e2920b557cdae23b796961b56440812da4b5cb7657c32596f0b43b32340f.jpg) All dimensions are shown in millimeters. Tolerances should be $\pm$ 0.25mm, unless otherwise noted. The tolerances on the module connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00]) should be $\pm$ 0.10mm. Figure 2: Express-DN7 Mechanical Drawing # 3. Pinouts and Signal Descriptions # 3.1. AB/CD Pin Definitions The Express-DN7 is a Type 7 module supporting up to 16 PCIe lanes and four 10GBASE-KR ports on the CD connector and NC-SI on the AB connector. In the table below, all standard pins of the COM Express specification are described, including those not supported on the Express-DN7. Signals not supported on the Express-DN7 module are crossed out. Table 1: Express-DN7 AB/CD Pin Definitions

Row A			Row B		Row C		Row D
Pin	Name	Pin	Name	Pin	Name	Pin	Name
A1	GND (fixed)	B1	GND (fixed)	C1	GND (fixed)	D1	GND (fixed)
A2	GBE0_MDI3-	B2	GBE0_ACT#	C2	GND	D2	GND
A3	GBE0_MDI3+	B3	LPC_FRAME#/ESPI_CS0#	C3	USB_SSRX0-	D3	USB_SSTX0-
A4	GBE0_LINK100#	B4	LPC_AD0/ESPI_IO-0	C4	USB_SSRX0+	D4	USB_SSTX0+
A5	GBE0_LINK1000#	B5	LPC_AD1/ESPI_IO-1	C5	GND	D5	GND
A6	GBE0_MDI2-	B6	LPC_AD2/ESPI_IO-2	C6	USB_SSRX1-	D6	USB_SSTX1-
A7	GBE0_MDI2+	B7	LPC_AD3/ESPI_IO-3	C7	USB_SSRX1+	D7	USB_SSTX1+
A8	GBE0_LINK#	B8	LPC_DRQ0#/ESPI_ALERT0#	C8	GND	D8	GND
A9	GBE0_MDI1-	B9	LPC_DRQ1#/ESPI_ALERT1#	C9	USB_SSRX2-	D9	USB_SSTX2-
A10	GBE0_MDI1+	B10	LPC_CLK/ESPI_CK	C10	USB_SSRX2+	D10	USB_SSTX2+
A11	GND (fixed)	B11	GND (fixed)	C11	GND (fixed)	D11	GND (fixed)
A12	GBE0_MDI0-	B12	PWRBTN#	C12	USB_SSRX3-	D12	USB_SSTX3-
A13	GBE0_MDI0+	B13	SMB_CK	C13	USB_SSRX3+	D13	USB_SSTX3+
A14	GBE0_CTREF	B14	SMB_DAT	C14	GND	D14	GND
A15	SUS_S3#	B15	SMB_ALERT#	C15	10G_PHY_MDC_SCL3	D15	10G_PHY_MDIO_SDA3
A16	SATAO_TX+	B16	SATA1_TX+	C16	10G_PHY_MDC_SCL2	D16	10G_PHY_MDIO_SDA2
A17	SATAO_TX-	B17	SATA1_TX-	C17	10G_SDP2	D17	10G_SDP3
A18	SUS_S4#	B18	SUS_STAT#/ESPI_RESET#	C18	GND	D18	GND
A19	SATAO_RX+	B19	SATA1_RX+	C19	PCIE_RX6+ *	D19	PCIE_TX6+ *
A20	SATAO_RX-	B20	SATA1_RX-	C20	PCIE_RX6- *	D20	PCIE_TX6- *
A21	GND (fixed)	B21	GND (fixed)	C21	GND (fixed)	D21	GND (fixed)
A22	PCIE_TX15+	B22	PCIE_RX15+	C22	PCIE_RX7+ *	D22	PCIE_TX7+ *
A23	PCIE_TX15-	B23	PCIE_RX15-	C23	PCIE_RX7- *	D23	PCIE_TX7- *
A24	SUS_S5#	B24	PWR_OK	C24	10G_INT2	D24	10G_INT3
A25	PCIE_TX14+	B25	PCIE_RX14+	C25	GND	D25	GND
A26	PCIE_TX14-	B26	PCIE_RX14-	C26	10G_KR_RX3+	D26	10G_KR_TX3+
A27	BATLOW#	B27	WDT	C27	10G_KR_RX3-	D27	10G_KR_TX3-
A28	(S)ATA_ACT#	B28	RSVD	C28	GND	D28	GND
A29	RSVD	B29	RSVD	C29	10G_KR_RX2+	D29	10G_KR_TX2+
A30	RSVD	B30	RSVD	C30	10G_KR_RX2-	D30	10G_KR_TX2-
A31	GND (fixed)	B31	GND (fixed)	C31	GND (fixed)	D31	GND (fixed)
A32	RSVD	B32	SPKR	C32	10G_SFP_SDA3	D32	10G_SFP_SCL3
A33	RSVD	B33	I2C_CK	C33	10G_SFP_SDA2	D33	10G_SFP_SCL2
A34	BIOS_DIS0#/ESPI_SAFS	B34	I2C_DAT	C34	10G_PHY_RST_23	D34	10G_PHY_CAP_23
A35	THRMTRIP#	B35	THRM#	C35	10G_PHY_RST_01	D35	10G_PHY_CAP_01

Row A Row B Row C Row D

Pin	Name	Pin	Name	Pin	Name	Pin	Name
A36	PCIE_TX13+	B36	PCIE_RX13+	C36	10G_LED_SDA	D36	RSVD
A37	PCIE_TX13-	B37	PCIE_RX13-	C37	10G_LED_SCL	D37	RSVD
A38	GND	B38	GND	C38	10G_SFP_SDA1	D38	10G_SFP_SCL1
A39	PCIE_TX12+	B39	PCIE_RX12+	C39	10G_SFP_SDA0	D39	10G_SFP_SCL0
A40	PCIE_TX12-	B40	PCIE_RX12-	C40	10G_SDP0	D40	10G_SDP1
A41	GND (fixed)	B41	GND (fixed)	C41	GND (fixed)	D41	GND (fixed)
A42	USB2-	B42	USB3-	C42	10G_KR_RX1+	D42	10G_KR_TX1+
A43	USB2+	B43	USB3+	C43	10G_KR_RX1-	D43	10G_KR_TX1-
A44	USB_2_3_OC#	B44	USB_0_1_OC#	C44	GND	D44	GND
A45	USB0-	B45	USB1-	C45	10G_PHY_MDC_SCL1	D45	10G_PHY_MDIO_SDA1
A46	USB0+	B46	USB1+	C46	10G_PHY_MDC_SCL0	D46	10G_PHY_MDIO_SDA0
A47	VCC_RTC	B47	ESPI_EN	C47	10G_INT0	D47	10G_INT1
A48	RSVD	B48	USB0_HOST_PRSNT	C48	GND	D48	GND
A49	GBE0_SDP	B49	SYS_RESET#	C49	10G_KR_RX0+	D49	10G_KR_TX0+
A50	LPC_SERIRQ/ESPI_CS1#	B50	CB_RESET#	C50	10G_KR_RX0-	D50	10G_KR_TX0-
A51	GND (fixed)	B51	GND (fixed)	C51	GND (fixed)	D51	GND (fixed)
A52	PCIE_TX5+	B52	PCIE_RX5+	C52	PCIE_RX16+	D52	PCIE_TX16+
A53	PCIE_TX5-	B53	PCIE_RX5-	C53	PCIE_RX16-	D53	PCIE_TX16-
A54	GPIO	B54	GPO1	C54	TYPE0#	D54	RSVD
A55	PCIE_TX4+	B55	PCIE_RX4+	C55	PCIE_RX17+	D55	PCIE_TX17+
A56	PCIE_TX4-	B56	PCIE_RX4-	C56	PCIE_RX17-	D56	PCIE_TX17-
A57	GND	B57	GPO2	C57	TYPE1#	D57	TYPE2#
A58	PCIE_TX3+	B58	PCIE_RX3+	C58	PCIE_RX18+	D58	PCIE_TX18+
A59	PCIE_TX3-	B59	PCIE_RX3-	C59	PCIE_RX18-	D59	PCIE_TX18-
A60	GND (fixed)	B60	GND (fixed)	C60	GND (fixed)	D60	GND (fixed)
A61	PCIE_TX2+	B61	PCIE_RX2+	C61	PCIE_RX19+	D61	PCIE_TX19+
A62	PCIE_TX2-	B62	PCIE_RX2-	C62	PCIE_RX19-	D62	PCIE_TX19-
A63	GPIO1	B63	GPO3	C63	RSVD	D63	RSVD
A64	PCIE_TX1+	B64	PCIE_RX1+	C64	RSVD	D64	RSVD
A65	PCIE_TX1-	B65	PCIE_RX1-	C65	PCIE_RX20+	D65	PCIE_TX20+
A66	GND	B66	WAKE0#	C66	PCIE_RX20-	D66	PCIE_TX20-
A67	GPIO2	B67	WAKE1#	C67	RAPID_SHUTDOWN	D67	GND
A68	PCIE_TX0+	B68	PCIE_RX0+	C68	PCIE_RX21+	D68	PCIE_TX21+
A69	PCIE_TX0-	B69	PCIE_RX0-	C69	PCIE_RX21-	D69	PCIE_TX21-
A70	GND (fixed)	B70	GND (fixed)	C70	GND (fixed)	D70	GND (fixed)
A71	PCIE_TX8+	B71	PCIE_RX8+	C71	PCIE_RX22+	D71	PCIE_TX22+
A72	PCIE_TX8-	B72	PCIE_RX8-	C72	PCIE_RX22-	D72	PCIE_TX22-
A73	GND	B73	GND	C73	GND	D73	GND
A74	PCIE_TX9+	B74	PCIE_RX9+	C74	PCIE_RX23+	D74	PCIE_TX23+
A75	PCIE_TX9-	B75	PCIE_RX9-	C75	PCIE_RX23-	D75	PCIE_TX23-
A76	GND	B76	GND	C76	GND	D76	GND
A77	PCIE_TX10+	B77	PCIE_RX10+	C77	RSVD	D77	RSVD
A78	PCIE_TX10-	B78	PCIE_RX10-	C78	PCIE_RX24+	D78	PCIE_TX24+
A79	GND	B79	GND	C79	PCIE_RX24-	D79	PCIE_TX24-

Row A			Row B		Row C		Row D
Pin	Name	Pin	Name	Pin	Name	Pin	Name
A80	GND (fixed)	B80	GND (fixed)	C80	GND (fixed)	D80	GND (fixed)
A81	PCIE_TX11+	B81	PCIE_RX11+	C81	PCIE_RX25+	D81	PCIE_TX25
A82	PCIE_TX11-	B82	PCIE_RX11-	C82	PCIE_RX25-	D82	PCIE_TX25-
A83	GND	B83	GND	C83	RSVD	D83	RSVD
A84	NCSI_TX_EN	B84	VCC_5V_SBY	C84	GND	D84	GND
A85	GPI3	B85	VCC_5V_SBY	C85	PCIE_RX26+	D85	PCIE_TX26+
A86	RSVD	B86	VCC_5V_SBY	C86	PCIE_RX26-	D86	PCIE_TX26-
A87	RSVD	B87	VCC_5V_SBY	C87	GND	D87	GND
A88	PCIE0_CK_REF+	B88	BIOS_DIS1#	C88	PCIE_RX27+	D88	PCIE_TX27+
A89	PCIE0_CK_REF-	B89	NSCI_RX_ER	C89	PCIE_RX27-	D89	PCIE_TX27-
A90	GND (fixed)	B90	GND (fixed)	C90	GND (fixed)	D90	GND (fixed)
A91	SPI_POWER	B91	NCSI_CLK_IN	C91	PCIE_RX28+	D91	PCIE_TX28+
A92	SPI_MISO	B92	NCSI_RXD1	C92	PCIE_RX28-	D92	PCIE_TX28-
A93	GPO0	B93	NCSI_RXD0	C93	GND	D93	GND
A94	SPI_CLK	B94	NCSI_CRS_DV	C94	PCIE_RX29+	D94	PCIE_TX29+
A95	SPI_MOSI	B95	NCSI_TXD1	C95	PCIE_RX29-	D95	PCIE_TX29-
A96	TPM_PP	B96	NCSI_TXD0	C96	GND	D96	GND
A97	TYPE10#	B97	SPI_CS#	C97	RSVD	D97	RSVD
A98	SER0_TX	B98	NCSI_ARB_IN	C98	PCIE_RX30+	D98	PCIE_TX30+
A99	SER0_RX	B99	NCSI_ARB_OUT	C99	PCIE_RX30-	D99	PCIE_TX30-
A100	GND (fixed)	B100	GND (fixed)	C100	GND (fixed)	D100	GND (fixed)
A101	SER1_TX	B101	FAN_PWMOUT	C101	PCIE_RX31+	D101	PCIE_TX31+
A102	SER1_RX	B102	FAN_TACHIN	C102	PCIE_RX31-	D102	PCIE_TX31-
A103	LID#	B103	SLEEP#	C103	GND	D103	GND
A104	VCC_12V	B104	VCC_12V	C104	VCC_12V	D104	VCC_12V
A105	VCC_12V	B105	VCC_12V	C105	VCC_12V	D105	VCC_12V
A106	VCC_12V	B106	VCC_12V	C106	VCC_12V	D106	VCC_12V
A107	VCC_12V	B107	VCC_12V	C107	VCC_12V	D107	VCC_12V
A108	VCC_12V	B108	VCC_12V	C108	VCC_12V	D108	VCC_12V
A109	VCC_12V	B109	VCC_12V	C109	VCC_12V	D109	VCC_12V
A110	GND (fixed)	B110	GND (fixed)	C110	GND (fixed)	D110	GND (fixed)

# Notes: - LPC and eSPI are muxed in the standard COM Express specification. The Denverton-NS platform only supports the LPC bus. - PCIe lanes 6 & 7 are supported by build option, in place of GbE (PCIe lanes 6/7 come from one controller) - PCIe lanes, USB 3.0 upgrade signals, SATA ports dependent on SoC SKUs. Refer to 2.6 Multi I/O and Storage for detailed info. # 3.2. Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input/output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Bi-directional 3.3V tolerant active in standby state I 3.3Vsb Input 3.3V tolerant active in standby state P Power Input/Output REF Reference voltage output that may be sourced from a module power plane. PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected. The signal is used to indicate the PICMG module type to the Carrier Board. PU ADLINK implemented pull-up resistor on module PD ADLINK implemented pull-down resistor on module # 3.3. AB Signal Descriptions # 3.3.1. Network Controller Sideband Interface (NC-SI)

Signal	Pin	Description	I/O	PU/PD	Comment
NCSI_CLK_IN	B91	Clock reference for receive, transmit and control interface	I 3.3VSB	PD 10k
NCSI_RXD[1:0]	B92B93	Receive Data (from NC to BMC)	O 3.3VSB	PU 10k3.3VSB	PU 10k that aligns with LAN chip specification
NCSI_TXD[1:0]	B95B96	Transmit Data (from BMC to NC)	I 3.3VSB	PU 10k3.3VSB
NCSI_CRS_DV	B94	Carrier Sense/Receive Data valid to MC, indicating that the transmitted data from NC to BMC is valid	O 3.3VSB	PD 10k	PU 10k that aligns with LAN chip specification
NCSI_TX_EN	A84	Transmit enable	I 3.3VSB	PD 10k
NCSI_RX_ER	B89	Receive error	O 3.3VSB
NCSI_ARB_IN	B98	Network Controller hardware arbitration input	I 3.3VSB		Left floating on module, that aligns with LAN chip specification
NCSI_ARB_OUT	B99	Network Controller hardware arbitration output	O 3.3VSB

# 3.3.2. Gigabit Ethernet

Gigabit Ethernet	Pin	Description	I/O	PU/PD	Comment
GBE0_MDI0+GBE0_MDI0-GBE0_MDI1+GBE0_MDI1-GBE0_MDI2+GBE0_MDI2-GBE0_MDI3+GBE0_MDI3-	A13A12A10A9A7A6A3A2	Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:____1000BASE-T 100BASE-TX 10BASE-TMDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-	I/OAnalog		Twisted pair signals for external transformer.
GBE0_ACT#	B2	Gigabit Ethernet Controller 0 activity indicator, active low.	O 3.3VSB
GBE0_LINK#	A8	Gigabit Ethernet Controller 0 link indicator, active low.	O 3.3VSB
GBE0_LINK100#	A4	Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.	O 3.3VSB
GBE0_LINK1000#	A5	Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.	O 3.3VSB
GBE0_CTREF	A14	Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.	REFGND min3.3V max		NC pin
GBE0_SDP	A49	Gigabit Ethernet Controller 0 Software-Definable Pins.Can also be used for IEEE1588 support such as a 1pps signal.	I/O3.3VSB

3.3.3. SATA

Signal	Pin	Description	I/O	PU/PD	Comment
SATA0_TX+SATA0_TX-	A16A17	Serial ATA channel 0, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA0_RX+SATA0_RX-	A19A20	Serial ATA channel 0, Receive Input differential pair.	I SATA		AC coupled on Module
SATA1_TX+SATA1_TX-	B16B17	Serial ATA channel 1, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA1_RX+SATA1_RX-	B19B20	Serial ATA channel 1, Receive Input differential pair.	I SATA		AC coupled on Module
(S)ATA_ACT#	A28	ATA (parallel and serial) or SAS activity indicator, active low.	O 3.3V

SATA on COMe Module	HSIO Function on SoC
SATA 0	SATA controller #2, 5 (Lane 16)
SATA 1	SATA controller #2, 6 (Lane 17)

Note: Maximum number of HSIO dependent on SoC SKU. C3808 is used as an example here (20 HSIO). 3.3.4. PCI Express

Signal	Pin	Description	I/O	PU/PD	Comment
PCIE_TX0+PCIE_TX0-	A68A69	PCI Express channel 0, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX0+PCIE_RX0-	B68B69	PCI Express channel 0, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX1+PCIE_TX1-	A64A65	PCI Express channel 1, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX1+PCIE_RX1-	B64B65	PCI Express channel 1, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX2+PCIE_TX2-	A61A62	PCI Express channel 2, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX2+PCIE_RX2-	B61B62	PCI Express channel 2, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX3+PCIE_TX3-	A58A59	PCI Express channel 3, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX3+PCIE_RX3-	B58B59	PCI Express channel 3, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX4+PCIE_TX4-	A55A56	PCI Express channel 4, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX4+PCIE_RX4-	B55B56	PCI Express channel 4, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX5+PCIE_TX5-	A52A53	PCI Express channel 5, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX5+PCIE_RX5-	B52B53	PCI Express channel 5, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX8+PCIE_TX8-	A71A72	PCI Express channel 8, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX8+PCIE_RX8-	B71B72	PCI Express channel 8, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX9+PCIE_TX9-	A74A75	PCI Express channel 9, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX9+PCIE_RX9-	B74B75	PCI Express channel 9, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX10+PCIE_TX10-	A77A78	PCI Express channel 10, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX10+PCIE_RX10-	B77B78	PCI Express channel 10, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX11+PCIE_TX11-	A81A82	PCI Express channel 11, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX11+PCIE_RX11-	B81B82	PCI Express channel 11, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX12+PCIE_TX12-	A39A40	PCI Express channel 12, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX12+PCIE_RX12-	B39B40	PCI Express channel 12, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX13+PCIE_TX13-	A36A37	PCI Express channel 13, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX13+PCIE_RX13-	B36B37	PCI Express channel 13, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX14+PCIE_TX14-	A25A26	PCI Express channel 14, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX14+PCIE_RX14-	B25B26	PCI Express channel 14, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX15+PCIE_TX15-	A22A23	PCI Express channel 15, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX15+PCIE_RX15-	B22B23	PCI Express channel 15, Receive Input differential pair.	I PCIE		Not supported
PCIE_CLK_REF+PCIE_CLK_REF-	A88A89	PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.	O PCIE

PCIe on COMe Module	HSIO Function on SoC	Note
PCIE 0	Lane 0	The behavior of this platform:Only four controllers on Lanes 0-7. It can be used as one x8, two x4 or four x2/x1.Lanes 0-7 are from PCIe Cluster 0.It supports RP 0/1/2/3:RP0 for Lane 0/1RP1 for Lane 2/3RP3 for Lane 4/5RP4 for Lane 6/7
PCIE 1	Lane 1
PCIE 2	Lane 2
PCIE 3	Lane 3
PCIE 4	Lane 4
PCIE 5	Lane 5
PCIE 6	Lane 6
PCIE 7	Lane 7
PCIE 16	Lane 8	The behavior of this platform:Only four controllers on Lanes 8-15. It can be used as one x8, two x4 or four x2/x1.Lanes 16-23 are from PCIe Cluster 1.
PCIE 17	Lane 9
PCIE 18	Lane 10
PCIE 19	Lane 11	It supports RP 4/5/6/7:RP4 for Lane 8/9RP5 for Lane 10/11RP6 for Lane 12/13RP7 for Lane 14/15
PCIE 20	Lane 12
PCIE 21	Lane 13
PCIE 22	Lane 14
PCIE 23	Lane 15

Note: Maximum number of HSIO dependent on SoC SKUs. C3808 is used as an example (20 HSIO). # 3.3.5. LPC Bus

Signal	Pin	Description	I/O	PU/PD	Comment
LPC_AD[0:3]	B4-B7	LPC multiplexed address, command and data bus	I/O 3.3V
LPC_FRAME#	B3	LPC frame indicates the start of an LPC cycle	O 3.3V
LPC_DRQ0#LPC_DRQ1#	B8B9	LPC serial DMA request	I 3.3V		Not supported
LPC_SERIRQ	A50	LPC serial interrupt	I/O OD 3.3V	PU 8.2k 3.3V
LPC_CLK	B10	LPC clock output -33MHz nominal	O 3.3V		This platform supports 24MHz nominal

Note: eSPI and LPC buses are muxed as defined by PICMG. The Denverton-NS platform only supports LPC interface. # 3.3.6. USB

Signal	Pin	Description	I/O	PU/PD	Comment
USB0+USB0-	A46A45	USB differential data pairs for Port 0	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB1+USB1-	B46B45	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB2+USB2-	A43A42	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB3+USB3-	B43B42	USB differential data pairs for Port 2	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB_0_1_OC#	B44	USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.	I 3.3VSB	PU 10K3.3VSB	Do not pull high on carrier
USB_2_3_OC#	A44	USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low..	I 3.3VSB	PU 10K3.3VSB	Do not pull high on carrier
USB0_HOST_PRSNT	A48	Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.	I 3.3VSB		Not Supported. Limitation of this platform

# 3.3.7. USB Root Segmentation Denverton-NS USB Ports Express-DN7 USB Ports

USB Combo Controller
USB 3.0				USB 2.0
0	1	2	3	0	1	2	3

	USB 3 Port 0	USB 3 Port 0	USB 2 Port 0	USB 2 Port 1	USB 2 Port 2	USB 2 Port 3

Notes: Maximum number of HSIO dependent on SoC SKU. C3808 is used as an example (20 HSIO). USB 3.0 0/1/2/3 mapping to HSIO Lane 16/17/18/19. Lane 16 & 17 are SATA and USB 3.0 muxed. On Express-DN7, the Lanes 16 & 17 are used for SATA ports support. # 3.3.8. SPI (BIOS only)

Signal	Pin	Description	I/O	PU/PD	Comment
SPI_CS#	B97	Chip select for Carrier Board SPI BIOS Flash.	O 3.3VSB	PU 10k3.3VSB
SPI_MISO	A92	Data in to module from carrier board SPI BIOS flash.	I 3.3VSB
SPI_MOSI	A95	Data out from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_CLK	A94	Clock from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_POWER	A91	Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER.SPI_POWER shall only be used to power SPI devices on the Carrier	OP3.3VSB
BIOS_DIS0#	A34	Selection strap to determine the BIOS boot device.	I	PU 10k3.3VSB	Carrier shall pull to GND or leave not-connected.
BIOS_DIS1#	B88	Selection strap to determine the BIOS boot device.	I	PU 10k3.3VSB	Carrier shall pull to GND or leave not-connected

# 3.3.9. Miscellaneous

Signal	Pin	Description	I/O	PU/PD	Comment
SPKR	B32	Output for audio enunciator, the “speaker” in PC-AT systems	O 3.3V	PU 10k 3.3V	Not Supported
WDT	B27	Output indicating that a watchdog time-out event has occurred.	O 3.3V	PU 10k 3.3V
THRM#	B35	Input from off-module temp sensor indicating an over-temp situation.	I 3.3VSB
THRMTRIP#	A35	Active low output indicating that the CPU has entered thermal shutdown.	O 3.3V	PU 10k 3.3V
FAN_PWMOUT	B101	Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.	O OD 3.3V	PU 2.2K 3.3V
FAN_TACHIN	B102	Fan tachometer input for a fan with a two pulse output.	I OD 3.3V	PU 47K 3.3V
TPM_PP	A96	Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.	I 3.3V	PD 100k 3.3V	PD only when TPM on module

# 3.3.10. SMBus

Signal	Pin	Description	I/O	PU/PD	Comment
SMB_CK	B13	System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.	I/O OD3.3VSB	PU 2.2k3.3VSB	Equivalent resistor is 2.2k
SMB_DAT#	B14	System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.	I/O OD3.3VSB	PU 2.2k3.3VSB	Equivalent resistor is 2.2k
SMB_ALERT#	B15	System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.	I 3.3VSB	PU 10k3.3VSB

# 3.3.11. I2C Bus

Signal	Pin	Description	I/O	PU/PD	Comment
I2C_CK	B33	General purpose I2C port clock output/input	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC
I2C_DAT	B34	General purpose I2C port data I/O line	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC

# 3.3.12. General Purpose I/O (GPIO)

Signal	Pin	Description	I/O	PU/PD	Comment
GPO[0]	A93	General purpose output pins.	O 3.3V	PU 10K 3.3V	After hardware RESET output low
GPO[1]	B54	General purpose output pins.	O 3.3V	PU 10K 3.3V	After hardware RESET output low
GPO[2]	B57	General purpose output pins.	O 3.3V	PU 10K 3.3V	After hardware RESET output low
GPO[3]	B63	General purpose output pins.	O 3.3V	PU 10K 3.3V	After hardware RESET output low
GPI[0]	A54	General purpose input pins.Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[1]	A63	General purpose input pins.Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[2]	A67	General purpose input pins.Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[3]	A85	General purpose input pins.Pulled high internally on the module.	I 3.3V	PU 10K 3.3V

# 3.3.13. Serial Interface Signals

Signal	Pin	Description	I/O	PU/PD	Comment
SER0_TX	A98	General purpose serial port transmitter (TTL level output)	O CMOS		Power rail tolerance 5V, 12V
SER0_RX	A99	General purpose serial port receiver (TTL level input)	I CMOS	PU 10k 3.3V	Power rail tolerance 5V, 12V
SER1_TX	A101	General purpose serial port transmitter (TTL level output)	O CMOS		Power rail tolerance 5V, 12V
SER1_RX	A102	General purpose serial port receiver (TTL level input)	I CMOS	PU 10k 3.3V	Power rail tolerance 5V, 12V

# 3.3.14. Power and System Management

Signal	Pin	Description	I/O	PU/PD	Comment
PWRBTN#	B12	Power button to bring system out of S5 (soft off), active on falling edge.	I 3.3VSB	PU 10k 3.3VSB
SYS_RESET#	B49	Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.	I 3.3VSB	PU 10k 3.3VSB
CB_RESET#	B50	Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.	O 3.3V
PWR_OK	B24	Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.	I 3.3VSB	PU 1k 3.3VSB	Should have weak pull up
SUS_STAT#	B18	Indicates imminent suspend operation; used to notify LPC devices.	O 3.3VSB
SUS_S3#	A15	Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.	O 3.3VSB
SUS_S4#	A18	Indicates system is in Suspend to Disk state. Active low output.	O 3.3VSB
SUS_S5#	A24	Indicates system is in Soft Off state.	O 3.3VSB
WAKE0#	B66	PCI Express wake up signal.	I 3.3VSB	PU 10k 3.3VSB
WAKE1#	B67	General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.	I 3.3VSB	PU 10k 3.3VSB	Connect to WAKE 1#
BATLOW#	A27	Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.	I 3.3VSB	PU 10k 3.3VSB
LID#	A103	LID button. Low active signal used by the ACPI operating system for a LID switch.	I OD 3.3VSB	PU 47k 3.3VSB
SLEEP#	B103	Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.	I OD 3.3VSB	PU 47k 3.3VSB

3.3.15. Power and Ground

Signal	Pin	Description	I/O	PU/PD	Comment
VCC_12V	A104-A109B104-B109	Primary power input: +12V nominal (wide range). All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
VCC_5V_S BY	B84-B87	Standby power input: +5.0V nominal. See COM.0 Base Specification, Section 7 “Electrical Specifications” for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.	P		5Vsb ±5%
VCC_RTC	A47	Real-time clock circuit-power input. Nominally +3.0V.	P
GND	A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21,B31, B41, B51, B60, B70, B80, B90, B100, B110	Ground - DC power and signal and AC signal return path.	P

# 3.4. CD Signal Descriptions # 3.4.1. USB 3.0 Extension

Signal	Pin	Description	I/O	PU/PD	Comment
USB_SSRX0-USB_SSRX0+	C3C4	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0	I PCIE		AC coupled off module
USB_SSTX0-USB_SSTX0+	D3D4	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0	O PCIE		AC coupled on module
USB_SSRX1-USB_SSRX1+	C6C7	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1	I PCIE		AC coupled off module
USB_SSTX1-USB_SSTX1+	D6D7	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1	O PCIE		AC coupled on module
USB_SSRX2-USB_SSRX2+	C9C10	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2	I PCIE		Not supported
USB_SSTX2-USB_SSTX2+	D9D10	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2	O PCIE		Not supported
USB_SSRX3-USB_SSRX3+	C12C13	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3	I PCIE		Not supported
USB_SSTX3-USB_SSTX3+	D12D13	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3	O PCIE		Not supported

# 3.4.2. PCI Express x1

Signal	Pin	Description	I/O	PU/PD	Comment
PCIE_TX6+PCIE_TX6-	D19D20	PCI Express channel 6, Transmit Output differential pair.	O PCIE		AC coupled on module
PCIE_RX6+PCIE_RX6-	C19C20	PCI Express channel 6, Receive Input differential pair.	I PCIE		AC coupled off module
PCIE_TX7+PCIE_TX7-	D22D23	PCI Express channel 7, Transmit Output differential pair.	O PCIE		AC coupled on module
PCIE_RX7+PCIE_RX7-	C22C23	PCI Express channel 7, Receive Input differential pair.	I PCIE		AC coupled off module

Note: PCIe lane 6 is supported by build option in place of GbE. # 3.4.3. 10G Ethernet 10GbE port 0/1

Signal	Pin	Description	I/O	PU/PD	Comment
10G_KR_RX0+10G_KR_RX0-10G_KR_RX1+10G_KR_RX1-	C49C50C42C43	10GBASE-KR ports,Receive Input differential paris	I KR		AC coupled on Module
10G_KR_TX0+10G_KR_TX0-10G_KR_TX1+10G_KR_TX1-	D49D50D42D43	10GBASE-KR ports,Transmit Output differential paris	O KR		AC coupled on Carrier
10G_INT010G_INT1	C47D47	Interrupt pin from Copper PHY or Optical SFP+ module to the 10GbE controller	I 3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDIO_SDA0	D46	MDIO ModeManagement Data I/O Interface mode data signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDIO_SDA0	D46	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDC_SCL0	C46	MDIO ModeManagement Data I/O Interface mode clock signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDC_SCL0	C46	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDIO_SDA1	D45	MDIO ModeManagement Data I/O Interface mode data signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDIO_SDA1	D45	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDC_SCL1	C45	MDIO ModeManagement Data I/O Interface mode clock signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDC_SCL1	C45	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_SDP010G_SDP1	C40D40	Software-Definable Pins	I/O3.3VSB		Not supported
10G_SFP_SDA010G_SFP_SDA1	C39C38	$I^{2}C$ Data signal, of the 2-wire management interface used by 10GbEcontroller to access the management registers of an external Optical SFP+ module	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_SFP_SCL010G_SFP_SCL1	D39D38	$I^{2}C$ Clock signal, of the 2-wire management interface used by 10GbE controller to access the management registers of an external Optical SFP+ module	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_RST_01	C35	Output signal that resets and Optical PHY on port 0 and port 1	O3.3VSB		This signal is not used for Copper PHY
10G_PHY_CAP_01	D35	Phy mode capability pin: Indicates if the PHY for 10G lanes 0 and1 is capable of configuration by I2C. High indicates MDIO-only configuration, and low indicates configuration capability via I2C or MDIO. The actual protocol used for PHY configuration is determined by the module, in part based on this input. The actual protocol used is indicated over the dedicated I2C interface	I 3.3VSB	PU 10k3.3VSB	Default state is MDIO mode. For $I^{2}C$ mode pull down with 1K on carrier
10G_LED_SDA	C36	$I^{2}C$ Data signal, of the 2-wire that transfers all LED signals and additional Strapping signal for $I^{2}C$ or MDIO mode of Optical PHY	I/O OD3.3VSB	PU 2.2k3.3VSB	LED signals for 10GbE port 2/3 are also transferred through this pin
10G_LED_SCL	C37	$I^{2}C$ Clock signal, of the 2-wire that transfers all LED signals and additional Strapping signal for $I^{2}C$ or MDIO mode of Optical PHY	I/O OD3.3VSB	PU 2.2k3.3VSB	LED signals for 10GbE port 2/3 are also transferred through this pin

10GbE port 2/3

Signal	Pin	Description	I/O	PU/PD	Comment
10G_KR_RX2+	C29	10GBASE-KR ports,Receive Input differential paris	I KR		AC coupled on Module
10G_KR_RX2-	C30
10G_KR_RX3+	C26
10G_KR_RX3-	C27
10G_KR_TX2+	D29	10GBASE-KR ports,Transmit Output differential paris	O KR		AC coupled on Carrier
10G_KR_TX2-	D30
10G_KR_TX3+	D26
10G_KR_TX3-	D27
10G_INT2	C24	Interrupt pin from Copper PHY or Optical SFP+ module to the 10GbE controller	I 3.3VSB	PU 2.2k 3.3VSB
10G_INT3	D24		I 3.3VSB	PU 2.2k 3.3VSB
10G_PHY_MDIO_SDA2	D16	MDIO Mode Management Data I/O Interface mode data signal for serial data transfers between the MAC and an external PHY	O 3.3VSB
10G_PHY_MDIO_SDA2	D16	$I^2C$ Mode $I^2C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD 3.3VSB	PU 2.2k 3.3VSB
10G_PHY_MDC_SCL2	C16	MDIO Mode Management Data I/O Interface mode clock signal for serial data transfersbetween the MAC and an external PHY	O 3.3VSB
		$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDIO_SDA3	D15	MDIO ModeManagement Data I/O Interface mode data signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDIO_SDA3	D15	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_MDC_SCL3	C15	MDIO ModeManagement Data I/O Interface mode clock signal for serial data transfers between the MAC and an external PHY	O3.3VSB
10G_PHY_MDC_SCL3	C15	$I^{2}C$ Mode $I^{2}C$ Data signal, of the 2-wire management interface used for serial data transfers between the MAC and the external PHY	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_SDP210G_SDP3	C17D17	Software-Definable Pins	I/O3.3VSB		Not supported
10G_SFP_SDA210G_SFP_SDA3	C33C32	$I^{2}C$ Data signal, of the 2-wire management interface used by 10GbE controller to access the management registers of an external Optical SFP+ module	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_SFP_SCL210G_SFP_SCL3	D33D32	$I^{2}C$ Clock signal, of the 2-wire management interface used by 10GbE controller to access the management registers of an external Optical SFP+ module	I/O OD3.3VSB	PU 2.2k3.3VSB
10G_PHY_RST_23	C34	Output signal that resets and Optical PHY on port 0 and port 1	O3.3VSB		This signal is not used for Copper PHY
10G_PHY_CAP_23	D34	Phy mode capability pin: Indicates if the PHY for 10G lanes 0 and1 is capable of configuration by I2C. High indicates MDIO-only configuration, and low indicates configuration capability via I2C or MDIO. The actual protocol used for PHY configuration is determined by the module, in part based on this input. The actual protocol used is indicated over the dedicated I2C interface	I 3.3VSB	PU 10k3.3VSB	Default state is MDIO mode. For $I^{2}C$ mode pull down with 1K on carrier

3.4.4. PCI Express

Signal	Pin	Description	I/O	PU/PD	Comment
PCIE_TX16+PCIE_TX16-	D52D53	PCI Express channel 16, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX16+PCIE_RX16-	C52C53	PCI Express channel 16, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX17+PCIE_TX17-	D55D56	PCI Express channel 17, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX17+PCIE_RX17-	C55C56	PCI Express channel 17, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX18+PCIE_TX18-	D58D59	PCI Express channel 18, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX18+PCIE_RX18-	C58C59	PCI Express channel 18, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX19+PCIE_TX19-	D61D62	PCI Express channel 19, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX19+PCIE_RX19-	C61C62	PCI Express channel 19, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX20+PCIE_TX20-	D65D66	PCI Express channel 20, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX20+PCIE_RX20-	C65C66	PCI Express channel 20, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX21+PCIE_TX21-	D68D69	PCI Express channel 21, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX21+PCIE_RX21-	C68C69	PCI Express channel 21, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX22+PCIE_TX22-	D71D72	PCI Express channel 22, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX22+PCIE_RX22-	C71C72	PCI Express channel 22, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX23+PCIE_TX23-	D74D75	PCI Express channel 23, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX23+PCIE_RX23-	C74C75	PCI Express channel 23, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX24+PCIE_TX24-	D78D79	PCI Express channel 24, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX24+PCIE_RX24-	C78C79	PCI Express channel 24, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX25+PCIE_TX25-	D81D82	PCI Express channel 25, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX25+PCIE_RX25-	C81C82	PCI Express channel 25, Receive Input differential pair.	I PCIE		Not supported
PCIE_TX26+PCIE_TX26-	D85D86	PCI Express channel 26, Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX26+PCIE_RX26-	C85C86	PCI Express channel 26,Receive Input differential pair.	I PCIE		Not supported
PCIE_TX27+PCIE_TX27-	D88D89	PCI Express channel 27,Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX27+PCIE_RX27-	C88C89	PCI Express channel 27,Receive Input differential pair.	I PCIE		Not supported
PCIE_TX28+PCIE_TX28-	D91D92	PCI Express channel 28,Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX28+PCIE_RX28-	C91C92	PCI Express channel 28,Receive Input differential pair.	I PCIE		Not supported
PCIE_TX29+PCIE_TX29-	D94D95	PCI Express channel 29,Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX29+PCIE_RX29-	C94C95	PCI Express channel 29,Receive Input differential pair.	I PCIE		Not supported
PCIE_TX30+PCIE_TX30-	D98D99	PCI Express channel 30,Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX30+PCIE_RX30-	C98C99	PCI Express channel 30,Receive Input differential pair.	I PCIE		Not supported
PCIE_TX31+PCIE_TX31-	D101D102	PCI Express channel 31,Transmit Output differential pair.	O PCIE		Not supported
PCIE_RX31+PCIE_RX31-	C101C102	PCI Express channel 31,Receive Input differential pair.	I PCIE		Not supported

3.4.5. Module Type Definition

Signal	Pin	Description				I/O	Comment
TYPE0#	C54	The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don't care (X).					Type 7
TYPE1#	C57
TYPE2#	D57
TYPE7#		TYPE2#	TYPE1#	TYPE0#
		X	X	X	Pinout Type 1
		NC	NC	NC	Pinout Type 2
		NC	NC	GND	Pinout Type 3 (no IDE)
		NC	GND	NC	Pinout Type 4 (no PCI)
		NC	GND	GND	Pinout Type 5 (no IDE, no PCI)
		GND	NC	NC	Pinout Type 6 (no IDE, no PCI)
		GND	NC	GND	Pinout Type 7 (server level with 10GbE)
		The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

# 3.4.6. Power and Ground

Signal	Pin	Description	I/O	PU/PD	Comment
VCC_12V	C104-C109D104-D109	Primary power input: +12V nominal (wide range 5-20V).All available VCC_12V pins on the connector(s) shall be used	P		8.5-20V
GND	C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73 D76, D80, D84, D87, D90, D93, D96, D100, D103, D110	Ground - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to carrier board GND plane.	P

# 4. Connector Pinouts on Module This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification # 4.1. Connector, Switch and LED Locations ![40-pin Multi-\nPurpose\nBIOS\nDefaults\nReset\nSwitch\nCD\nAB\nFan\n4-pin\nFan](.express-dn7-50m-00049-1020-12/61421b5b914a0a68dc308ed4891d13d2628b250545974c7d5b0fa705b8957f2e.jpg) ![Bottom View\nCD\nAB](.express-dn7-50m-00049-1020-12/11d4cdfd217ecb36a294fe69bc070a7f39f75f72e800a8967dc5b113dd5dd39a.jpg) Note: $3^{rd}$ SODIMM is located on back-side of module (supported by build option). Figure 3: Express-DN7 Connector, Switch and LED Locations # COM Express module and the DB40 Debug Module For illustration purposes only ![Two views of a green printed circuit board with internal components and connectors, showing close-up assembly (no readable text or symbols)](.express-dn7-50m-00049-1020-12/7b1c3ab8365a6d22a65b38170e55c7a31ba93491a64e14a8a4d3ef60a19db0f4.jpg) Figure 4: COM Express module and the DB40 Debug Module # 4.2. 40-pin Debug Connector FPC Connector Type: Molex 502790-4091 Pin Orientation ![Close-up of a green printed circuit board with a black connector (no visible text or symbols)](.express-dn7-50m-00049-1020-12/5d892ea4a673cecdfb174a9f0ab6c7aa78ad8c1d0dbfc58746d5c0bf88c900bc.jpg) 40-pin Debug Connector Pin Definition on the COM Express Module

Pin	Interface	Signal	Remark
40	SPI Program interface	VCC_SPI_IN
39		GND
38		SPI_BIOS_CS0#
37		SPI_BIOS_CS1#	PU 10k 3.3VSB
36		SPI_BIOS_MISO
35		SPI_BIOS_MOSI
34		SPI_BIOS_CLK
33	LPC Bus	3V3_LPC
32		GND
31		BIOS_DIS0	PU 10k 3.3VSB
30		RST#
29		CLK33_LP C
28		LPC_FRAME#
27		LPC_AD3
26		LPC_AD2
25		LPC_AD1
24		LPC_AD0
23	BMC Program interface	3.3V_BMC
22		3.3VSB
21		GND

Pin	Interface	Signal	Remark
20	BMC Program interface (cont'd)	TXD6
19		RXD6
18		FUMD0
17		RESET_IN#	PU 10k 3.3VSB
16		DATA	PU 2.2k 3.3VSB Equivalent
15		CLK	PU 2.2k 3.3VSB Equivalent
14		OCD0A
13		OCD0B
12	Test points	PWRBTN#	PU 10k 3.3VSB
11		SYS_RESET #	PU 10k 3.3VSB
10		CB_RESET#	PU 1k 3.3VSB
9		CB_PWROK
8		SUS_S3#
7		SUS_S4#
6		SUS_S5#
5	BMC Debug signals	POSTWDT_DIS#	PU 100k 3.3VSB
4		SEL_BIOS
3		BIOS_MODE
2		BMC_STATUS
1	Reserved		Tied to GND through 0ohm resistor

Table 2: 40-pin Debug Connector Pin Definition Note: The pin definition on the debug module is the inverse of that on the COM Express module. # 4.3. Status LEDs To facilitate easier maintenance, status LED's are mounted on the board. ![Close-up of a green printed circuit board with visible traces and components (no readable text or symbols)](.express-dn7-50m-00049-1020-12/30872dbf3454e17cd22bcbc805ca3e65bc2ce0db31ee87a24cae822f5c67fa04.jpg) LED1 LED2 LED3 LED Descriptions

Name	Color	Connection	Function
LED1	Blue	BMC output	Power Sequence Status Code (BMC)Power Changes, RESET(see 5.1.4 Exception Codes below)
LED2	Green	Power Source 3Vcc	S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3	Red	BMC outputand same signal as WDT (B27) on BtB connector	Module power up LED OFFWatchdog counting Keep last stateWatchdog timed out LED ONWatchdog RESET LED ONRebooted after WD RESET LED ONRebooted after PWRBTN LED OFFRebooted after RESET BTN LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)

Table 3: Express-DN7 LED Descriptions # 4.4. MIPI60 Debug Header Not all pins of the Intel MIPI60 connector are connected to the CombiProbe Intel x86/x64 MIPI-C.

Pin	Signal
1	VREF_DEBUG
3	TCK0
5	TDI
7	Reset In
9	TRST_N
11	PRDY_N
13	PTI_0_CLK
15	GND
17	No Connect
19	PTI_0_DATA[0]
21	PTI_0_DATA[1]
23	PTI_0_DATA[2]
25	PTI_0_DATA[3]
27	PTI_0_DATA[4]
29	PTI_0_DATA[5]
31	PTI_0_DATA[6]
33	PTI_0_DATA[7]
35	No Connect
37	No Connect
39	No Connect
41	No Connect
43	No Connect
45	No Connect
47	No Connect
49	No Connect
51	No Connect
53	No Connect
55	No Connect
57	GND
59	No Connect

Pin	XDP Signal
2	TMS
4	TDO
6	Open Drain Reset Out
8	No Connect
10	PREQ_N
12	VREF_TRACE
14	PTI_1_CLK
16	GND
18	PTI_1_DATA[0]
20	PTI_1_DATA[1]
22	PTI_1_DATA[2]
24	PTI_1_DATA[3]
26	No Connect
28	No Connect
30	No Connect
32	No Connect
34	Reset Out
36	Boot Stall
38	CPU Boot Stall
40	Power Button
42	PWRGOOD
44	No Connect
46	No Connect
48	I2C_SCL
50	I2C_SDA
52	No Connect
54	DBG_UART_TX
56	DBG_UART_RX
58	GND
60	No Connect

Table 4: MIPI60 Debug Header Pin Definition # 4.5. Fan Connector Connector Type: JVE 24W1125A-04M00 Pin Orientation ![Close-up of a green printed circuit board with a yellow circular component and various electronic components (no visible text or symbols)](.express-dn7-50m-00049-1020-12/be9c4bedd36e3cdb7db66130c8d1c279fc42a5b35e5c174508518b911f5c0db7.jpg) 1234 # Pin Assignment

Name	Signal
1	FAN_PWMOUT
2	FAN_TACHIN
3	Ground
4	5V

Table 5: Fan Connector Pin Definition # 4.6. BIOS Setup Defaults Reset Button ![Close-up of a green printed circuit board with visible traces and components (no readable text or symbols)](.express-dn7-50m-00049-1020-12/526ad646a042b975c9b52f8e2701a18c3ea146c5aa1572ffe91d035aa5ac60f9.jpg) To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Hold down the BIOS Setup Defaults Reset Button and boot up the system. You can release the button when the BIOS prompt screen appears 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.express-dn7-50m-00049-1020-12/08762ea75ad6267bf8b5844764eeafbbde7ab4267f31cf1ad9b9671fd6e3639a.jpg) # 4.7. Switch Settings # Switch Locations ![NDAV\n76JFB\n100\nBIOS Select and Mode\nConfiguration Switch (SW2)](.express-dn7-50m-00049-1020-12/e6766ff543adb98b5372f0f68358ff7cb566b74d67d4fc1c982d1bd257535d60.jpg) Figure 5: Express-DN7 Switch Locations # BIOS Select and Mode Configuration Switch The module has two BIOS chips and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using the BIOS Select and Mode Configuration Switch (SW2), Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, Pin 1 is used to select whether to boot from SPI0 or SPI1.

Mode	Pin 1	Pin 2
Boot from SPI0 (default)	On	—
Boot from SPI1	Off	—
Set BIOS to PICMG mode	—	On
Set BIOS to Failsafe BIOS mode (default)	—	Off

Table 6: BIOS Select and Mode Configuration Switch Settings # 4.8. PCIe x8-to-two-x4 Adapter Card The Express-DN7 can be used with the PCIe x8-to-two-x4 Adapter Card on the Express-BASE7 Reference Carrier to support bifurbication of the PCIe x8 interface. The card reroutes the PCIe x8 to two x4 and allows testing of two independent PCIe add-on cards with x4/x2/x1 width. To use the card, set BIOS > Chipset > IIO Configuration > IIO0 Configuration > IOU2 (IIO PCIe Port 1) to "x4x4". ![Green printed circuit board with black plastic connectors and gold contacts (no readable text or symbols)](.express-dn7-50m-00049-1020-12/87815b6688fd4579ef8b2d3d732fcf1fe4daf71dc8399fcc880071dc901da78f.jpg) PCIex8-to-two-x4 Adapter Card (Model: P8TO24, Part No.:) This page intentionally left blank. # 5. Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: • Total operating hours counter. Counts the number of hours the module has been run in minutes. - On-time minutes counter. Counts the seconds since last system start. - Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash. • Power cycles counter - Boot counter. Counts the number of boot attempts. - Watchdog Timer. Set/Reset/Disable Watchdog Timer. Features auto-reload at power-up. • System Restart Cause. Power loss/BIOS Fail/Watchdog/Internal Reset/External Reset - Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS. • Flash area. 1kB Flash area for customer data • 2K Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region. • Board Identify. Vendor/Board/Serial number/Production Date • Main-current & voltage. Monitors drawn current and main voltages For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/sema/. # 5.1. Board Specific SEMA Functions (update later) Note: To be confirmed. # 5.1.1. Voltages The BMC of the Express-DN7 implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

ADC Channel	Voltage Name	Voltage Formula [V]
0	VCORE	(MSB<<8 + LSB) x 1.0 x 3.3 / 1024
1	VMEM	(MSB<<8 + LSB) x 1.0 x 3.3 / 1024
2	RTC	(MSB<<8 + LSB) x 1.0 x 3.3 / 1024
3	3.3V	(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
4	5VSB	(MSB<<8 + LSB) x 1.826 x 3.3 / 1024
5	VIN	(MSB<<8 + LSB) x 3.7 x 3.3 / 1024
6	3.3VSB	(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
7	5V	(MSB<<8 + LSB) x 1.826 x 3.3 / 1024

Table 7: SEMA Onboard Voltage Monitor # 5.1.2. Main Current The BMC of the Express-DN7 implements a current monitor. The current can be read by calling the SEMA function "Get Main Current". The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access. $$ \text { Main Current } = (\text { MSB\_n } < < 8 + \text { LSB\_n }) \times 8. 0 6 \mathrm{mA} $$ # 5.1.3. BMC Status This register shows the status of BMC controlled signals on the Express-DN7. <table>Status BitSignal0WDT_OUT1Reserved2Reserved3BIOS_MODE4POSTWDT_DISn5SEL_BIOS6BIOS_DIS0n7BIOS_DIS1n Table 8: SEMA BMC Status # 5.1.4. Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

Exception Code	Error Message
0	NOERROR
2	NO_SUSCLK
3	NO_SLP_S45
4	NO_SLP_S3
5	RESET_FAIL
6	BIOS_FAIL
7	NO_CB_PWROK
8	POWER_FAIL
9	VOLTAGE_FAIL
10	NO_VCC_CORE
11	NO_VDDQ
12	NO_VRTC
13	NO_V3P3_S
14	NO_V5VSB
15	NO_V12
16	NO_V3P3_A
17	NO_V5V_S
18	NO_P_5V_3P3_PG
19	NO_5V_PG
20	NO_VCCRAM_PG
21	NO_VNN_PG
22	NO_V5_DUAL
23	NO_V1P8_A_PG
24	NO_V1P05_A_PG
25	NO_ALL_SYS_PG
26	CRITICAL_TEMP
27	RESETIN_FAIL

Table 9: SEMA Exception Codes # 5.1.5. BMC Flags The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

Bit	Description
[0 ~ 4]	Exception Code
[6]	0 = AT mode1 = ATX mode
[7]	0 = Standard BIOS1 = Fail-safe BIOS.

Table 10: SEMA BMC Flags # 6. System Resources # 6.1. System Memory Map

Memory Range	Target
0000 0000h – 000D FFFFh0010 0000h – TOM(Top of Memory)	Main Memory
000E 0000h – 000F FFFFh	Motherboard resources

FEC0 0000h-FEC0 0fffh	IO(x) APIC
FED0 0000 – FED0 03FF	HPET
FF00 0000 h – FFFF FFFFh	IFAW (BIOS)

# 6.2. Direct Memory Access Channels

Channel Number	Data Width	System Resource
0	8-bits	Generic
1	8-bits	Generic
2	8-bits	Generic
3	8-bits	Generic
4		Reserved - cascade channel
5	16-bits	Generic
6	16-bits	Generic
7	16-bits	Generic

# 6.3. Fixed I/O Address Range Map

Hex Range	Device
020-021	Interrupt Controller
024-025	Interrupt Controller
028-029	Interrupt Controller
02C-02D	Interrupt Controller
02E-02F	LPC SIO
030-031	Interrupt Controller
034-035	Interrupt Controller
038-039	Interrupt Controller
03C-03D	Interrupt Controller
040-042	Timer/Counter
043	Timer/Counter
04E-04F	LPC SIO
050-052	Timer/Counter
053	Timer/Counter
060	Microcontroller
061	NMI Controller
062	Microcontroller
064	Microcontroller
066	Microcontroller
070-077	RTC
080081-083084-086087088089-08B08C-08E08F	DMA Controller and LPC,PCI,or PCIE
090-091	DMA Controller
093-09F	DMA Controller
092	Reset Generator
0A0-0A10A4-0A50A8-0A90AC-0AD	Interrupt Controller
0B0-0B10B4-0B50B8-0B90BC-0BD	Interrupt Controller
0B2-0B3	Power Management
0C0-0D10D2-0DD0DE-0DF	DMA Controller
0F0	FERR# / Interrupt Controller
240-247	COM3
248-24F	COM4
2F8-2FF	COM2
3F8-3FF	COM1
4D0-4D1	Interrupt Controller
CA0-CB0	IPMI Usage
CF9	Reset Generator

6.4. Variable I/O Address Range Map

Hex Range	Device
Anywhere in 64 KB I/O Space	ACPI
Anywhere in 64 KB I/O Space	SATA Index/Data Pair
Anywhere in 64 KB I/O Space	SMBus
96 Bytes above ACPI Base	TCO
Anywhere in 64 KB I/O Space	GPIO
8 Ranges in 64 KB I/O Space	Serial Port 1
8 Ranges in 64 KB I/O Space	Serial Port 2
Anywhere in 64 KB I/O Space	LAN
Anywhere in 64 KB I/O Space	LPC Generic 1
Anywhere in 64 KB I/O Space	LPC Generic 2
Anywhere in 64 KB I/O Space	LPC Generic 3
Anywhere in 64 KB I/O Space	LPC Generic 4
Anywhere in 64 KB I/O Space	I/O Trapping Ranges

6.5. APIC Interrupt Mapping

IRQ#	Typical Interrupt Resource	Using SERIRQ
0	Cascade from 8259 #1	No
1		Yes
2	8254 Counter 0,HPET #0(Legacy mode)	No
3	COM2	Yes
4	COM1	Yes
5	COM3	Yes
6		Yes
7	COM4	Yes
8	RTC,HPET #1(Legacy mode)	No
9	Option for SCI,TCO	Yes
10	Option for SCI,TCO	Yes
11	HPET #2,Option for SCI,TCO	Yes
12		Yes
13	FERR# logic	No
14
15
16	Internal devices are routable.	PIRQA#
17	Internal devices are routable.	PIRQB#
18	Internal devices are routable.	PIRQC#
19	Internal devices are routable.	PIRQD#
20	Option for SCI,TCO,HPET #0,1,2,3.Other internal device are routable.	N/A
21	Option for SCI,TCO,HPET #0,1,2,3.Other internal device are routable.	N/A
22	Option for SCI,TCO,HPET #0,1,2,3.Other internal device are routable.	N/A
23	Option for SCI,TCO,HPET #0,1,2,3.Other internal device are routable.	N/A

6.6. PCI Configuration Space Map

Bus Number	Device Number	Function Number	Description
00h	00h	00h	System Agent
00h	04h	00h	Global and Local Error Registers (GLMREG)
00h	05h	00h	Root Complex Event Collector
00h	06h	00h	RP - Intel® QuickAssist Technology
00h	09h~0Ch,0Eh~11h	00h	PCI Express Root Ports
00h	13h	00h	SATA Controllers
00h	15h	00h	USB Combo Controller
00h	18h	00h	System Management
00h	1Ah	00h	HSUART Controller
00h	1Bh	00h	Innovation Engine
00h	1Ch	00h	eMMC Controller
00h	1Fh	00h	LPC Controller
00h	1Fh	01h	Primary to Side Band Bridge
00h	1FH	02H	Power Management Controller
00h	1Fh	04h	SMBus - Legacy
00h	1Fh	05h	SPI Controller

# 6.7. PCI Interrupt Routing Map

INT Line	xHCI Controller	PCIE Port1	PCIE Port 2	PCIE Port 3	PCIE Port 4	PCIE Port 5	PCIE Port 6
Int0	INTD:19	INTA:16	INTB:17	INTC:18	INTD:19	INTE:20	INTH:23
Int1		INTB:17	INTC:18	INTD:19	INTA:16	INTF:21	INTE:20
Int2		INTC:18	INTD:19	INTA:16	INTB:17	INTG:22	INTF:21
Int3		INTD:19	INTA:16	INTB:17	INTC:18	INTH:23	INTG:22

INT Line	PCIE Port 7	PCIE Port 8	SATA Controller	SMBus Controller
Int0	INTG:22	INTH:23	INTE:20
Int1	INTH:23	INTE:20
Int2	INTE:20	INTF:21		INTH:23
Int3	INTF:21	INTG:22

# 6.8. SMBus Address Table

Device	Address
BMC	50h
Extend GPIO	40h

This page intentionally left blank. # 7. BIOS Setup # 7.1. Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the Submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Main	IntelRCSetup	Advanced	Event Logs	Security	Boot	Save & Exit
BIOS Information System Information Board Information System Date and Time Access Level	PlatformRC RevisionProcessor BSPRevisionMicrocodeRevisionProcessorConfigurationCPU ThermalConfigurationCK420ConfigurationServer MEConfigurationServer MEConfigurationSystem EventLogNorth BridgeChipsetConfigurationSouth BridgeChipsetConfiguration	PowerManagement ▶SystemManagement ▶ThermalManagement ▶Watchdog Timer ▶CSM Configuration ▶Super IOConfiguration ▶Serial ConsoleRedirection ▶USB Configuration ▶Network StackConfiguration ▶Miscellaneous ▶Driver Health ▶Trusted Computing ▶	Change SMBIOS Event Log Settings ▶Vies SMBIOS Event Log ▶	SetupAdministratorPassword ▶User PasswordSecure Boot ▶	Boot ▶ConfigurationFIXED BOOT ORDER ▶PrioritiesUEFI USBKey DriveBBS Priorities ▶	Save Change and Exit ▶Discard Changes and Exit ▶Save Changes and Reset ▶Discard Changes and Reset ▶Save OptionsBoot Override ▶

# Notes: ▶ indicates a Submenu Gray text indicates info only # 7.2. Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the settings. 7.2.1. Main > BIOS Information

Feature	Options	Description
BIOS Vender	Info only	American Megatrends
BIOS Version	Info only	ADLINK BIOS version
Build Date	Info only	ADLINK BIOS Build Date
SPS Firmware Version	Info only	Display SPS Firmware Version

7.2.2. Main > System Information

Feature	Options	Description
Project Name	Info only	Display Project Name.
Hardware version	Info only	Display CPU Board Version.
CPU Brand String	Info only	Display CPU Board String.
CPU Frequency	Info only	Display CPU Frequency.
Total Memory	Info only	Display Installed Memory Size.
SOC SKU	Info only

# 7.2.3. Main > Board Information

Feature	Options	Description
Board Information	Submenu
Board Information	Info only
Serial Number	Info only	Display SEMA serial Number.
Manufacturing Date	Info only	Display SEMA manufacturing date.
Last Repair Date	Info only	Display SEMA last repair date.
MAC ID	Info only	Display SEMA MAC ID.
Runtime Statistics	Info only
Total Runtime	Info only	The returned value specifies the total time in minutes the system is running in S0 state.
Current Runtime	Info only	The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.
Power Cycles	Info only	The returned value specifies the number of times the external power supply has been shut down
Boot Cycles	Info only	The Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
Boot Reason	Info only	The boot reason is the event which causes the reboot of the system.

# 7.2.4. Main >System Date/Time

Feature	Options	Description
System Date	Info only
System Time	Info only

# 7.2.5. Main >Access Level

Feature	Options	Description
Access Level	Info only

# 7.3. IntelRCSetup 7.3.1. IntelRCSetup >Processor Configuration

Feature	Options	Description
Processor Configuration	Info only
EIST (GV3)	Disabled Enabled	Enable/Disable EIST. GV3 and TM1 must be enabled for TM2 to be available. GV3 must be enabled for Turbo. Auto-Enable for B0 CPU stepping, all others disabled, change setting to override.
BIOS Request Frequency	Disabled Enabled	Two modes: Min Frequency and Max Frequency (the CPU will be instructed to provide the highest possible legal frequency to the processor).
Turbo	Disabled Enabled	Enable or Disable CPU Turbo capability. This option only applies to ES2 and above.
TM1	Disabled Enabled	Enable/Disable TM1. TM1 and GV3 must be enabled in order to support TM2
TM2 Mode	LFM Throttling Adaptive Throttling	Select LFM throttling or adaptive throttling for TM2 mechanisms.
Dynamic Self Refresh	Disabled Enabled	Enable or Disable dynamic self refresh in memory controller
PMOP Levels	Slow Fast	Power Mode Opcode during Self Refresh Slow/Fast
CPU C State	Disabled Enabled	Enables the Enhanced Cx state of the CPU, takes effect after reboot. Auto - Enable for B0 CPU stepping, all others disabled, change setting to override.
Package C State limit	No Pkg C-State No S0lx No Limit	No Package C State limit
Max Core C-State	C1 C6	Options are: C1 and C6.
Enhanced Halt State (C1E)	Disabled Enabled	Enables the Enhanced C1E state of the CPU, takes effect after reboot.
Monitor/Mwait	Disabled Enabled	Enable or Disable the Monitor/Mwait instruction
L1 Prefetcher	Disabled Enabled	Enable/Disable L1 Prefetch
L2 Prefetcher	Disabled Enabled	Enable/Disable L2 Prefetch
ACPI 3.0 T-States	Disabled Enabled	Enable/Disable ACPI 3.0 T-States.
Fast String	Disabled Enabled	When enabled, enables fast strings for REP MOVS/STOS
Machine Check	Disabled Enabled	Enable or Disable the Machine Check
Max CPUID Value Limit	Disabled Enabled	This should be enabled in order to boot legacy OSes that cannot support CPUs with extended CPUID functions.
Execute Disable Bit	Disabled Enabled	When disabled, forces the XD feature flag to always return 0.
vmx	DisabledEnabled	Enables the Vanderpool Technology, takes effect after reboot.
BIST Selection	DisabledEnabled	Enables BIST, takes effect after reboot.
Extended APIC	Info only
MSR 606PKG_POWER_SKU_UNIT	Info only
Lock PACKAGE_RAPL_LIMIT	DisabledEnabled	Allows the user to lock the MSR 0x610(PACKAGE_RAPL_LIMIT) by setting the lock bit
PL1 Time Window	45	Defines RAPL time window 1 in milliseconds
PL1 Power Level	25	Defines RAPL power limit 1 in Watts
PL2 Power Level	29	Defines RAPL power limit 2 in Watts
Active Processor Cores	0	Set the number of Active Processor Cores in the SoC.A 0 indicates all Existing Processor Cores are Active.
Dump Crash Log	DisabledEnabled	Enable Dump Crash Lo
CPU Flex Ratio Override	DisabledEnabled	Enable/Disable CPU Flex Ratio Programming
CPU Core Ratio	Info only
Ratio Limits	DisabledEnabled	Enable/Disable the configuration of the ratio limits MSRs
Ratio Limits Configuration	Submenu
Processor DFX Configuration	Submenu

7.3.1.1. IntelRCSetup >Processor Configuration >Ratio Limits Configuration

Feature	Options	Description
Ratio Limits Configuration	Info only
Ratio Limit 0	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_0 in FREQ_LIMIT_CORES.
Ratio Limit 1	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_1 in FREQ_LIMIT_CORES.
Ratio Limit 2	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_2 in FREQ_LIMIT_CORES.
Ratio Limit 3	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_3 in FREQ_LIMIT_CORES.
Ratio Limit 4	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_4 in FREQ_LIMIT_CORES.
Ratio Limit 5	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_5 in FREQ_LIMIT_CORES.
Ratio Limit 6	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_6 in FREQ_LIMIT_CORES.
Ratio Limit 7	0	The frequency limit corresponding to the maximum number of active cores specified in CORE_COUNT_7 in FREQ_LIMIT_CORES.
Core Count 0	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_0 in FREQ_LIMIT_RATIOS.
Core Count 1	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_1 in FREQ_LIMIT_RATIOS.
Core Count 2	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_2 in FREQ_LIMIT_RATIOS.
Core Count 3	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_3 in FREQ_LIMIT_RATIOS.
Core Count 4	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_4 in FREQ_LIMIT_RATIOS.
Core Count 5	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_5 in FREQ_LIMIT_RATIOS.
Core Count 6	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_6 in FREQ_LIMIT_RATIOS.
Core Count 7	0	The number of maximum active cores corresponding to the frequency limit specified in RATIO_LIMIT_7 in FREQ_LIMIT_RATIOS.

7.3.1.2. IntelRCSetup >Processor Configuration >Processor DFX Configuration

Feature	Options	Description
Processor DFX Configuration	Info only
Energy Performance Bias	PerformanceBalanced PerformanceBalanced EfficiencyEnergy Efficient	Selects the energy efficiency policies used in making turbo decision by the CPU. The energy policy controls turbo performance vs. power.
Lock PL3_CONTROL	DisabledEnabled	Allows the user to lock the MSR 0x615 (PACKAGE_RAPL_LIMIT) by setting the lock bit
PL3 Time Window	2ms4ms8ms16ms	Defines RAPL time window 3 in milliseconds
PL3 Enable	DisabledEnabled	Enable/Disable PL3 Algorithm
PL3 Power Level	0	Defines RAPL power limit 3 in Watts
PL3 Duty Cycle Percentage	25	Power limit excursion duty cycle control for PL3, describing what percentage of time it is allowed for the SOC to exceed the programmed PL3 power limit. This is expressed as a percentage
PMAX Power	0	The SOC guarantees it will never exceed this power limit even for very short time windows
Self Refresh Delay	30	Configures self refresh delay in microseconds. DDR-1600 up to 1300us, DDR-1867 up to 1100us, DDR-2133 up to 950us, DDR-2400 up to 850us, DDR-2666 up to 750us.

7.3.2. IntelRCSetup >CPU Thermal Configuration

Feature	Options	Description
CPU Thermal Configuration	Info only
TJ Target	0	Offset below TJMAX to set as the PROCHOT# activation temperature. Valid range 0C to 63C.
Tcontrol Offset	0	Offset to modify Tcontrol for DTS2.0. Valid range 0C to 63C.
Tcontrol Offset Sign	Positive Negative	To select the the sign for the Tcontrol Offset value
TM1	Disabled Enabled	Enable/Disable TM1. TM1 and GV3 must be enabled in order to support TM2
TM2 Status	Info only
TM2 Mode	LFM Throttling Adaptive Throttling	Select LFM throttling or adaptive throttling for TM2 mechanisms.
CPU DFX Thermal Configuration	Submenu

7.3.3. IntelRCSetup >CPU Thermal Configuration >CPU DFX Thermal Configuration

Feature	Options	Description
CPU DFX Thermal Configuration	Info only
Out of Spec Interrupt	DisabledEnabled	Enables generation of a thermal interrupt whenever Out of Spec temperature threshold is crossed.
Low Temp Interrupt	DisabledEnabled	Trigger an interrupt when the temperature goes from HOT to NOT_HOT.
High Temp Interrupt	DisabledEnabled	Triggers an interrupt when the temperature goes from NOT_HOT to HOT.
Threshold 1 Rel Temp	5	Degrees below TJMAX to signal an interrupt whenever the temperature crosses this threshold. Range is 0C - 127C
Threshold 2 Rel Temp	10	Degrees below TJMAX to signal an interrupt whenever the temperature crosses this threshold. Range is 0C - 127C
Threshold 1 Interrupt	DisabledEnabled	Enables generation of a thermal interrupt whenever Threshold 1 is crossed.
Threshold 2 Interrupt	DisabledEnabled	Enables generation of a thermal interrupt whenever Threshold 2 is crossed.
External PROCHOT Interrupt	DisabledEnabled	Enables generation of an interrupt when an external device drives the PROCHOT# pin.
PROCHOT RESPONSE	DisabledEnabled	Prochot Configurable Response Enable. INTERNAL INTEL ONLY:Ucode will copy this value to/from PCU_CR_FIRM_CONFIG(12).
Prochot Output Mode Disable	DisabledEnabled	Prochot output disable. INTERNAL INTEL ONLY:Prochot output disable. Ucode will copy this value to/from PCU_CR_FIRM_CONFIG(11).
VR_THERM_ALERT_DISABLE	DisabledEnabled	When set to 1, disables the VR_THERMAL_ALERT signaling. INTERNAL INTEL ONLY:Disable SVID during bclk overclocking mode. This bit is a mirror of PCU_CR_FIRM_CONFIG(14).
Prochot Frequency Response	DisabledEnabled	Control the level of PROCHOT throttling.
LOCK_THERM_INT	DisabledEnabled	Ties thermal interrupts from both cores. If set then thermal interrupt on one core is routed to all cores.

7.3.4. IntelRCSetup >CK420 Configuration

Feature	Options	Description
CK420 Configuration	Info only
CK420 Spread spectrum		Spread spectrum off/on

# 7.3.5. IntelRCSetup >Server ME Configuration

Feature	Options	Description
Server ME Configuration	Info only
Altitude	80000000	The altitude of the platform location above the see level, expressed in meters. The hex number is decoded as 2's complement signed integer.\nProvide the 80000000 value if the altitude is unknown.
MCTP Bus Owner	0	MCTP bus owner location on PCIe: [15:8] bus, [7:3] device, [2:0] function. If all zeros sending bus owner is disabled.
ME Shutdown Message	DisabledEnabled	Enable/Disable sending ME_SHUTDOWN message to ME when launching operating system

# 7.3.6. IntelRCSetup >System Event Log

Feature	Options	Description
System Event Log	Info only
System Errors	DisabledEnabled	System Error Enable/Disable/ Auto setup options. If Auto is selected the enabling or disbling of errors in the driver is skipped.
Memory Event Log	Submenu
PCIe Event Log	Submenu
Whea Settings	Submenu

# 7.3.6.1. IntelRCSetup >System Event Log >Memory Event Log

Feature	Options	Description
Memory ELog Support	DisabledEnabled	Enable/Disable Memory Error logging support
Parity Check	DisabledEnabled	Enable/Disable Parity Check
Log Correctable Errors	DisabledEnabled	Enable/Disable Correctable Memory Error logging support
Log Un-Correctable Errors	DisabledEnabled	Enable/Disable Un-Correctable Memory Error logging support
Enable/Disable Error Cloaking	DisabledEnabled	Error Cloaking Feature to Hide CE Errors to O

7.3.6.2. IntelRCSetup >System Event Log >PCIe Event Log

Feature	Options	Description
PCIe Event Log	Info only
PCIe ELog Support	Disabled Enabled	Enable/Disable PCIe Error logging support
Log Fatal Error	Disabled Enabled	Send system event Signal on Fatal error
Log Non-Fatal Error	Disabled Enabled	Send system event Signal on Non Fatal error
Log Correctable Error	Disabled Enabled	Send system event Signal on Correctable error
PCIe System Error	Disabled Enabled	Enable System Error reporting on all enumerated Root ports, bridges and devices
PCIe Parity Error	Disabled Enabled	Enable Parity Error reporting on all enumerated Root ports, bridges and devices

7.3.6.3. IntelRCSetup >System Event Log >Whea Settings

Feature	Options	Description
Whea Settings	Info only
WHEA Support	DisabledEnabled	Enable/Disable WHEA ACPI support
WHEA Error Injection 5.0 Extension	DisabledEnabled	Whea EINJ ACPI 5.0 support for set error type with address and vendor extensions.
Whea Logging	DisabledEnabled	Enable/Disable Whea logging of errors.
WHEA PCIe Error Injection	DisabledEnabled	Enable/Disable WHEA PCIe Error Injection

7.3.6.4. IntelRCSetup >North Bridge Chipset Configuration

Feature	Options	Description
North Bridge Chipset Configuration	Info only
Pass Gate Setup	Submenu
Leaky Bucket Setup	Submenu
NonVolatile Memory Setup	Submenu
Fast Boot	DisabledEnabled	Enables/Disables fast boot which skips memory training and attempts to boot using last known good configuration.
Command Mode	Default1N2N	Set tCMD to Default, 1N or 2N
Smm Size (MB)	24816	Specify the size of the SMM/TSEG region 1 MB aligned
Command Address Parity	Info only
Memory Frequency	DDR-1600 DDR-1867 DDR-2133 DDR-2400	DDR memory frequency: DDR4 up to DDR-2666. DDR3 up to DDR-1867
Enable 32 bit bus	Disabled Enabled	This enables 32 bit bus memory mode
TCL performance	Disabled Enabled	Enable TCL increase for performance
Enable Parallel Training	Disabled Enabled	Memory Training Algorithms will run in parallel
Memory Channels	Dual Channel Single Channel	DDR Memory Channels
MRC Debug Messages	Disabled Minimum Medium Maximum General options	Enable to display debug output in MRC
Memory Preservation	Disabled Enabled	Enables memory content preservation thru Warm Reset
Fine Ddr Voltag	100	Select between -100 to 100 mV in steps of 5mv. 0 -> -100mV :: 100 -> 0mV :: 200 -> 100mV
Read Per Bit Training	Disabled Enabled	Enables/Disables the Read Per Bit memory training
Write Per Bit Training	Disabled Enabled	Enables/Disables the Write Per Bit memory training
ECC Support	Disabled Enabled	Select to enable/disable ECC Support
Faulty Part Tracking	Disabled Enabled	Select to enable/disable faulty part tracking
On Correctable Faulty Part	Halt Continue	On Correctable Faulty DIMM issue (single bit) halt or continue
Patrol Scrub Enable	Disabled Enabled	Select to enable/disable Patrol Scrub Support
Patrol Scrub Period	1 hour 4 hours 10 hours 20 hours	Select the Patrol Scrub Period
Demand Scrub Enable	Disabled Enabled	Select to enable/disable Demand Scrub Support
AB Segments in DRAM	Disabled Enabled	When this bit is set reads and writes targeting AorB-segments are routed to DRAM
E Segment in DRAM	Disabled Enabled	When this bit is set reads and writes targeting E segment are routed to DRAM
F Segment in DRAM	Disabled Enabled	When this bit is set reads and writes targeting F segment are routed to DRAM
ZQ Calibration	Disabled Enabled	Enables ZQ Calibration.
Rank Margin Tool	DisabledEnabled	Enable Rank Margin Tool support
RMT CPGC exp_loop_cnt	12	Set the CPGC exp_loop_cnt field for MRC trainings 2^(exp_loop_cnt -1)
RMT CPGC num_bursts	6	Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1)
Out of order memory processing	DisabledEnabled	Enables out of order memory processing, improving performance
Read Two Clock Preamble	DisabledEnabled	Enables Two Clock Preamble for Reads
Write Two Clock Preamble	DisabledEnabled	Enables Two Clock Preamble for Writes
Write Data Early Enable	DisabledEnabled	Enables Write Data Early
Out of order aging threshold	8	Specifies the number of requests that can be processed ahead of another request sitting in the In-Progress request queue before OOO is disabled
New request bypass	DisabledEnabled	Enables new memory requests to be processed immediately, skipping the In-Progress queue, if the queue is empty
Select Refresh Rate	1x/2X1X/2X/4X	Disable, 1x, 2x or 4x options available
CKE Power Down	DisabledActive Power DownPrecharge Power Down	Enables/Disables the CKE Power Down
RAPL Time Window	0	DRAM RAPL Time Window for PL1
RAPL Power Limit Enable	DisabledEnabled	DRAM RAPL Power Limit[1] Enable for DDR Domain
RAPL Power Limit	2047875	DRAM RAPL Power Limit[1] for DDR Domain specified in mWatts
LOCK MSR 618DDR_RAPL_LIMIT	DisabledEnabled	Allows user to lock the corresponding MSRs by setting the lock bit
PMOP Value for PC0	4	Power Mode Opcode for PC0
PMOP Value for PCX	7	Power Mode Opcode for PCX
Open Page Policy Timer	DisabledEnabled	Set Page Closure Timer to Disabled / Immediate / 30-60 ns / 60-120ns / 120-240ns / 240-480ns / 480-960ns / 1-2us
Memory Thermal Throttling	AutoDisabled	Enable/Disable Memory Thermal Throttling Management mode
Thermal Throttling Type	CLTTOLTT	Select CLTT/OLTT mode
CLTT Mode	NormalPassthru	Select CLTT Normal/Passthru mode
High Temperature	105	Set temperature level from 105C to 255C
Medium Temperature	85	Set temperature level from 85C to 104C
Low Temperature	82	Set temperature level from 0C to 84C
Critical BW Level	3	Set Bandwidth level from 0% to 9%
High BW Level	10	Set Bandwidth level from 10% to 50%
Medium BW Level	100	Set Bandwidth level from 51% to 100%
MEMHOT Level	DisabledMidHiCritical	MEMHOT disabled (no response to pin assertion), Mid Level, Hi Level, Critical Level (MEMHOT re-uses CLTT THRT MID/HI/CRIT registers or OLTT BW Level)
MEMTRIP	DisabledEnabled	Enable\Disable MEMTRIP
Rx Skew Control	No Skew+2 Ticks-2 Ticks	Selects Rx Skew Control 0: No skew, 1: +2, 2: -2 ticks
Tx Skew Control	No Skew+2 Ticks-2 Ticks	Selects Tx Skew Control 0: No skew, 1: +2, 2: -2 ticks
Performance Profile	17_19_13_1817_19_6_1817_19_6_7	Performance profile for DMAP
Override Checkpoints	AutoDisabledEnabled	Set to Auto (normal function)/Enabled(Adds a breakpoint if warm-reset can't be executed)/Disabled
Scrambler	DisabledEnabled	Enable / Disable the scrambler
Slow Power Down Exit	DisabledEnabled	Enable / Disable Slow Power Down Exit from pre-charge
Timing Configuration	Submenu
SSA Config	Submenu
Memory config DFX Menu	Submenu

7.3.6.5. IntelRCSetup >North Bridge Chipset Configuration >Pass Gate Setup

Feature	Options	Description
Pass Gate Setup	Info only
Pass Gate Test	DisabledEnabled	Enables/Disables the Pass Gate Test
Pass Gate Test Direction	Lowest->HighesHighest->Lowest	Selects if move through memory from Lowest->Highest or from Highest->Lowest
Pass Gate Test Repetition	900	Pass Gate Test Repetition Count Range over the same row (1000x)
Pass Gate Test Iterations	1	Pass Gate Test Iterations on Row (repeat the 'Pass Gate Test Repetition')
Pass Gate Swizzle	AutoEnabled	Forces Swizzle mode (for Samsung)
Pass Gate Pattern	0's1's	Select between Pattern 1's or 0's Agressor
Pass Gate Target Pattern	0's1's	Select to target pattern 1's or 0's
Pass Gate Speed	1x Only2x Only4x Only8x Only	Speed of execution of the characterization test
Pass Gate Partial	DisabledEnabled	Enables/Disables the Pass Gate Test in an specified memory range
Row Bank Min	0	Select the minimum address to test. If DDR3 'Row Bank Min[2:0] -> Banks' and 'Row Bank Min[18:3] -> Rows', if DDR4 'Row Bank Min[1:0] -> Banks', 'Row Bank Min[3:2] -> Banks Groups' and 'Row Bank Min[21:4] -> Rows'
Row Bank Max	8	Select the maximum address to test. If DDR3 'Row Bank Max[2:0] -> Banks' and 'Row Bank Max[18:3] -> Rows', if DDR4 'Row Bank Max[1:0] -> Banks', 'Row Bank Max[3:2] -> Banks Groups' and 'Row Bank Max[21:4] -> Rows'
Channel x:	Info only
Rank x	DisabledEnabled	Allow the Rank x to be tested
Pass Gate MonteCarlo	DisabledEnabled	Enable/Disable Search Algorithm in order to find PG Max
Pass Gate Max Failures	50	The number of failures before reducing repetition value
Pass Gate Montecarlo Start	900	The start repetition value for MonteCarlo
Pass Gate Montecarlo Decrement	10	Step Decrement value

7.3.6.6. IntelRCSetup >North Bridge Chipset Configuration >Leaky Bucket Setup

Feature	Options	Description
Leaky Bucket Setup	Info only
Channel x	Info only
Leak Rate Units	Microseconds Days	Configure Leak Rate Units for programming all Ranks
Leak Rate Configuration	Info only
Rank x	0	Allow the Rank x to be tested
Correctable Error Threshold	Info only
Rank x	0	Allow the Rank x to be tested

7.3.6.7. IntelRCSetup >North Bridge Chipset Configuration >NonVolatile Memory Setup

Feature	Options	Description
NonVolatile Memory Setup	Info only
Method	DisabledEnabled
SoC Pwr loss support	DisabledEnabled	enable internal detection of ADR entry instead of a CPLD
Cache Flushing	MemCtrlr onlyL1, L2 and MemCtrlr	Select the amount of cache that should be flushed
ADR State source	Internal external	Selects whether ADR State source is internal or external
Internal Pwr Loss Event Setup	Submenu
Interleaving	DisabledEnabled	interleaved or separate NVDIMMs address space
Restore	DisabledEnabled	Enable restoring of data from the NVDIMMs
Erase & Arm	DisabledEnabled	Enable erasing and arming of NVDIMM after data recovery
NVDIMM battery	inactive - charging	NVDIMM not available until adequate charge is available
LBA Start Location	Fixed LBAC2F disk Partition	The method used to determine the C2F storage space
LBA	0	the starting LBA where C2F data will be saved
Size(MB)	1024	the amount (in megabytes) from the top of memory space to be saved, limited to memory space above 4gig
Test NonVol mode:	DisabledEnabled	force a NonVolatile memory flow

IntelRCSetup >North Bridge Chipset Configuration >NonVolatile Memory Setup >Internal Pwr Loss Event Setup

Feature	Options	Description
SoC Pwr loss support	DisabledEnabled	enable internal detection of ADR entry instead of a CPLD
PMC reset	DisabledEnabled	Notify when global reset because of SMBUS Slave pwr down; CF9 w/global reset; Host partition timeout w/Promote to global reset; Sx entry timeout
Power Button Override	DisabledEnabled	Notify when Power Button Override
ME Pwr Button Override	DisabledEnabled	Notify when ME initiated Power Button Override
ME WDT	DisabledEnabled	Notify when ME watchdog timer expire
ME reset	DisabledEnabled	Notify when ME initiated global reset
PMC WDT	DisabledEnabled	Notify when PMC watchdog timer expire
ME uncorr Error	DisabledEnabled	Notify when ME uncorrectable error
SYS_PWROK	DisabledEnabled	Notify when SYS_PWROK failure
PMC parity error	DisabledEnabled	Notify when PMC parity error
Return power	DisabledEnabled	Power up ~4 sec after ADR entry

7.3.6.8. IntelRCSetup >North Bridge Chipset Configuration >Timing Configuration

Feature	Options	Description
Timing Configuration	Info only
tCL	Auto	Set tCL to Auto \| 7 -> 18, 20 DRAM Clocks
tRCD	Auto	Set tRCD to Auto \| 7 -> 18, 20 DRAM Clocks
tRP	Auto	Set tRP to Auto \| 7 -> 18, 20 DRAM Clocks
tRAS	Auto	Set tRAS to Auto \| 24 -> 44 DRAM clocks
tRTP	Auto	Set tRTP to Auto \| 6 -> 10 DRAM clocks
tRRD	Auto	Set tRRD to Auto \| 4 -> 10 DRAM clocks
tFAW	Auto	Set tFAW to Auto \| 16 \| 20 \| 22 \| 23 \| 24 \| 26 \| 27 \| 30 \| 32 \| 33 DRAM clocks
tCCD	Auto	Set tCCD to Auto \| 4 -> 8 DRAM clocks
tWTP	Auto	Set tWTP to Auto / 15 / 16 / 17 / 18 / 19 / 20 / 21 / 22 / 23 / 24 / 25 / 26 / 27 / 28 / 29 / 30 DRAM clocks
tWCL	Auto	Set tWCL to Auto \| 7 -> 12, 14, 16, 18 DRAM clocks

7.3.6.9. IntelRCSetup >North Bridge Chipset Configuration >SSA Config

Feature	Options	Description
SSA Config	Info only
VT-d	Disabled Enabled	COption to Enable / Disable VT-d
VT-d Interrupt remapping	Disabled Enabled	Option to Enable/Disable VT-d Interrupt remapping

IntelRCSetup >North Bridge Chipset Configuration >SSA Config >DFX SSA Config

Feature	Options	Description
DFX SSA Config	Info only
SSA Clock Gating	Disabled Enabled	Enable SSA Clock Gating on NorthBridge
In Order APIC	Disabled Enabled	Enable/Disable In Order APIC. Option applies to B0 Stepping ONLY.
Scheduler Lat	8	Scheduler Latency. Value programmed has 250ns resolution.
MSI algorithm	Fixed priority Round Robin	Allow change the MSI algorithm
COS CAT Agentx	0	COS Category for Agent
BestEffortMaxLat	63	Best Effort Max Latency
PageHitDelay	0	Page Hit Delay
ISOCBankPref	0	ISOC Bank Prefetch
BestEffortBankPref	32	Best Effort Bank Prefetch

7.3.6.10. IntelRCSetup >North Bridge Chipset Configuration >Memory config DFX Menu

Feature	Options	Description
Memory config DFX Menu	Info only
Bank XOR Mapping	DisabledEnabled	Memory Bank XOR Mapping
Error Threshold	16384	Modify the MCI Error threshold from 1->32768
Rank-to-Rank	DisabledEnabled	Enables/Disables the Rank To Rank Switching
Memory Test Loop	DisabledEnabled	Enable to repeat memory test infinitely
LoopCount	1	Number of time CPGC will be tested 1 - 65535
Interleave Mode	Mode 0Mode 1Mode 2HVM Mode	Selects the Interleave Mode Settings
Halt on Memtest Fail	DisabledEnabled	Enable to halt the system if an error is observed during memory test
MRC Reset Test	DisabledEnabled	Enable to execute MRC Reset Test a defined number of cycles
Max Scrub Debit Count	0	Maximum Number of debit Patrol scrub operations
BRAM Parity	AutoDisabled	Enables MC Error reporting for BRAM parity errors. 'Auto' applies the safest setting for the stepping.
Training CPGC exp_loop_cnt	10	Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1)
Training CPGC num_bursts	8	Set the CPGC num_bursts field for MRC trainings 2^(num_bursts -1)
Vref Override Enable	DisabledEnabled	Enables/Disables Vref Override Enable
MeSeg Enable	DisabledEnabled	Enables Memory for Manageability Engine Usage
MMIO Size / BMBOUND Base	Auto1024M / 3072M3072M / 1024M	Size of memory mapped IO space / Corresponding BMBOUND Base setting. BMBound base plus Memory map IO low will always be 4GB
BDebug1 DRAM Self Refresh	DisabledEnabled	Enable/Disable DRAM Self Refresh During C0

IntelRCSetup >North Bridge Chipset Configuration >Memory config DFX Menu >PPR Option 0\~7

Feature	Options	Description
PPR Sequence	DisabledEnabled	Enables/Disables the PPR Sequence
Target Row	0	Selects the failure row
Target Bank	0	Selects the failure bank
Target Bank Group	0	Selects the failure bank group
Target Dram Device	0	Selects the failure DRAM device for max device is 7 and for x4 is 16
Target Rank	0	Selects the failure rank
Target Channel	0	Selects the failure channel

7.3.7. IntelRCSetup >South Bridge Chipset Configuration

Feature	Options	Description
South Bridge Chipset Configuration	Info only
SATA Configuration	Submenu
USB Configuration	Submenu
PCIE IP Configuration	Submenu
PPM Config	Submenu
IQAT Configuration	Submenu
GPIO Status	DisabledEnabled	GPIO Status Help
DCI Enable	DisabledEnabled	When DCI is Enabled, it is taken as user consent to enable the DCI which allows debug over the USB3 interface. When Disabled, the host control is not enabling DCI feature.
SMBUS Controller	DisabledEnabled	SMBUS Controller options
SMBusIOSFClockGating	DisabledEnabled	SMBusIOSFClockGating
SMBus Host Speed	Standard (80 kHz)Standard (100 kHz)Fast Mode (400 kHz)Fast Mode Plus (1 MHz)	SMBus Host Speed: Value to indicate what speed physical bus must operate.
IOAPIC 24-119 Entries	DisabledEnabled	Enables/Disables IOAPIC 24-119 Entries to expand to PIRQI-PIRQX
SouthBridge DFX Configuration	Submenu

7.3.7.1. IntelRCSetup >South Bridge Chipset Configuration >SATA Configuration

Feature	Options	Description
SATA x	Submenu

7.3.7.2. IntelRCSetup >South Bridge Chipset Configuration >SATA Configuration >SATA 0\~1

Feature	Options	Description
Enable controller	DisabledEnabled	Enables/Disables SATA Controller if supported by current cpu SKU.
SATA Testmode	DisabledEnabled	Enable/Disable SATA test mode
LPM	DisabledEnabled	Enables/Disables Link Power Management
Speed limit	Gen 1Gen 2Gen 3	Indicates the highest allowable speed of the interface
Port Multiplier Support	DisabledEnabled	Enables port multiplier support in CAP register of the controller.
Port 0	Submenu
Port 1	Submenu

IntelRCSetup >South Bridge Chipset Configuration >SATA Configuration >SATA 0\~1 >Port 0\~1

Feature	Options	Description
SATA x Port x	Info only
Enable/disable port	DisabledEnabled	Enables/Disables SATA Controller port if supported by current cpu SKU.
Hot plug	DisabledEnabled	Hot plug
Spin up	DisabledEnabled	Spin up
Topology	UnknownISATADirect ConnectFlexM2	Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2

7.3.7.3. IntelRCSetup >South Bridge Chipset Configuration >USB Configuration

Feature	Options	Description
USB SS Configuration	Submenu
USB HS Configuration	Submenu
USB Precondition	DisabledEnabled	Precondition work on USB host controller and root ports for faster enumeration.
Inactivity Initiated L1	Disabled1024 bb_cclk	If programmed to non-zero, it allows L1 power managed to be enabled after the time-out period specified
XHC Initiated L1	DisabledEnabled	If set, allow the XHC initiated L1 power management to be enabled.
XHCI Compliance Mode	DisabledEnabled	Disable Compliance Mode

IntelRCSetup >South Bridge Chipset Configuration >USB Configuration >USB SS Configuration >Port 0\~3

Feature	Options	Description
USB SS Physical Connector	DisabledEnabled	Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

IntelRCSetup >South Bridge Chipset Configuration >USB Configuration >USB HS Configuration >Port 0\~3

Feature	Options	Description
USB HS Physical Connector	DisabledEnabled	Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.

7.3.7.4. IntelRCSetup >South Bridge Chipset Configuration >PCIE IP Configuration

Feature	Options	Description
Bifurcation PCIE0	X2X2X4	Select and force Root Complex BifurcationConfiguration regardless board or trident detection
Bifurcation PCIE1	X2X2X4X4X8	Select and force Root Complex BifurcationConfiguration regardless board or trident detection
Compliance Test Mode	DisabledEnabled	Enable when using Compliance Load Board
Root Port x	Submenu
Topologies for PCIE lane by lane	Submenu

IntelRCSetup >South Bridge Chipset Configuration >PCIE IP Configuration >Root Port x

Feature	Options	Description
Link Speed	Gen1Gen2Gen3	Select upper limit on link operational speed for PCI Express RootPort.
Clock Gating	DisabledEnabled	Enable / Disable Clock Gating for PCI Express RootPort.
Max Payload	128 Bytes256 Bytes512 Bytes1024 Bytes2048 Bytes4096 Bytes	Set Maximum Payload of PCI Express RootPort or allow BIOS to select the value
Max Read Request	Auto128 Bytes256 Bytes512 Bytes1024 Bytes2048 Bytes4096 Bytes	Set Maximum Read Request of PCI Express RootPort or allow BIOS to select the value
Extended Tag	DisabledEnabled	If Enabled allows Device to use 8-bit Tag field as a requester
Relaxed Ordering	DisabledEnabled	Enables or Disables PCI Express Device Relaxed Ordering.
Extended Synch	DisabledEnabled	If Enabled allows generation of Extended Synchronization patterns
De-Emphasis	-3.5 dB-6.0 dB	When the link is operating at 5 Gb/s speed, this bit selects the level of de-emphasis for an Downstream Port
Stop and Scream	DisabledEnabled	Stop and Scream option
ASPM Support	L1Disabled	Enable PCI Express Active State Power Management settings.
Surprise link	DisabledEnabled	Activate surprise link
RW - Lock	UnLockLock	Root Port lock option
Lane Reversal	DisabledEnabled	Enable / Disable Dynamic Lane Reversal on PCI Express RootPort
Completion Timeout Disabled	DisabledEnabled	Enable / Disable Completion Timeout
Completion Timeout Range	65ms to 210ms	This field indicates the Completion Timeout Range value

IntelRCSetup >South Bridge Chipset Configuration >PCIE IP Configuration >Topologies for PCIE lane by lane

Feature	Options	Description
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X2Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X4X1Unknown	Identify PCIE Topology:x1, X4, sata express or M2
	M2X4M2X1X4X1Unknown
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X 1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express orM2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4X1Unknown	Identify PCIE Topology:x1, x4, sata express or M2
Topology	SATA ExpressM2X4M2X1X4x1Unknown	Identify PCIE Topology:x1, x4, sata express or M2

# 7.3.7.5. IntelRCSetup >South Bridge Chipset Configuration >PPM Config

Feature	Options	Description
C-state POPUP	DisabledEnabled	Enable/Disable C-state POPUP

# 7.3.7.6. IntelRCSetup >South Bridge Chipset Configuration >IQAT Configuration

Feature	Options	Description
IQAT	DisabledEnabled	Hides IQAT device from an OS
Set IQAT FUSECTL	DisabledEnabled	Enable the setting of IQAT FUSECTL Register
Set 64B MRR/MPL	DisabledEnabled	Enable the setting of 64B MRR/MPL in IQAT DevCtl Register

# 7.3.7.7. IntelRCSetup >South Bridge Chipset Configuration >SouthBridge DFX Configuration

Feature	Options	Description
SouthBridge DFX Configuration	Info only
IQAT Configuration	Submenu

IntelRCSetup >South Bridge Chipset Configuration >SouthBridge DFX Configuration >IQAT Configuration

Feature	Options	Description
IQAT	DisabledEnabled	Hides IQAT device from an OS
Set IQAT FUSECTL	DisabledEnabled	Enable the setting of IQAT FUSECTL Register
Set 64B MRR/MPL	DisabledEnabled	Enable the setting of 64B MRR/MPL in IQAT DevCtl Register

# 7.4. Advanced This menu contains the settings for most of the user interfaces in the system. 7.4.1. Advanced > Power Management

Feature	Options	Description
Power Management	Info only
Enable ACPI Auto Configuration	Disabled Enabled	Enable or Disables BIOS ACPI Auto Configuration.
Enable Hibernation	Disabled Enabled	Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS.
Lock Legacy Resource	Disabled Enabled	Enables or Disables Lock of Legacy Resources
Emulation AT/ATX	Emulation AT ATX	Select Emulation AT or ATX function. If this option is set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. In windows XP, it will make OS show shutdown
LID Function	Disabled Enabled	Enable/Disable LID Function
ECO Mode	Disabled Enabled
Power-up Mode	Turn On Remain Off Last State
Power Consumption	Submenu	Power Consumption information.

7.4.2. Advanced > Power Management->Power Consumption

Feature	Options	Description
Power Consumption	Info Only
Current Input Current	Info Only	Display Current Input Current
Current Input Power	Info Only	Display Current Input Power
VCORE	Info Only	Display VCORE Voltage
VMEM	Info Only	Display VMEM Voltage
5VSB	Info Only	Display 5VSB Voltage
VIN	Info Only	Display VIN Voltage
3.3VSB	Info Only	Display 3.3VSB Voltage
5V	Info Only	Display 5V Voltage

7.4.3. Advanced > System Management

Feature	Options	Description
System Management	Info Only
Version	Info Only	Display SEMA Module Version.
SEMA Firmware	Info Only	Display SEMA Firmware Version.
Build Date	Info Only	Display SEMA Firmware Build Date.
SEMA Bootloader	Info Only	Display SEMA Bootloader Version.
Build Date	Info Only	Display SEMA Bootloader Build Date.
SEMA Features	Submenu	Display SEMA Supported Features
SEMA Supported Features	Info only	Display SEMA Supported Features
Flags	Submenu	Flag
Flags	Info only
BMC Flags	Info Only
BIOS Select	Info Only
ATX/AT-Mode	Info Only
Exception Code	Info Only

7.4.4. Advanced > Thermal Management

Feature	Options	Description
Temperatures and Fan Speed	Info Only
CPU Temperature	Info Only
Current	Info Only	Display Current CPU Temperature
Startup	Info Only	Display Startup CPU Temperature
Min	Info Only	Display Min CPU Temperature
Max		Display Max CPU Temperature
Board Temperature	Info Only
Current	Info Only	Display Current Board Temperature
Startup	Info Only	Display Startup Board Temperature
Min	Info Only	Display Min Board Temperature
Max	Info Only	Display Max Board Temperature
CPU Fan Speed	Info Only	Display CPU Fan Speed
Smart Fan	Submenu
Critical Trip Point	Disabled65 C75 C85 C	The value is the temperature threshold of the Critical Trip Point.
Passive Cooling Trip Point	Disabled80 C90 C	The value is the temperature threshold of the Passive Cooling Trip Point.
Watchdog ACPI Event Shutdown	DisabledEnabled	Watchdog ACPI Event Shutdown Enabled/Disabled

7.4.4.1. Advanced > Thermal Management > Smart Fan

Feature	Options	Description
Smart Fan	Info Only
CPU Smart Fan Temperature Source	CPU Sensor Board Sensor	CPU Smart Fan Temperature Source
CPU Fan Mode	AUTO (Smart Fan) Fan Off Fan On	CPU Fan Mode
Trigger Point 1 to 4	Info Only	Display Trigger Point 1 to 4 information
Trigger Temperature	0-100	Select Trigger Temperature
PWM Level	0-100	Select Trigger Temperature

# 7.4.5. Advanced > Watchdog Timer

Feature	Options	Description
Watchdog Timer	Info only
RunTime Watchdog	DisabledEnabled	The RunTime Watchdog resets the system after a certain amount of time after power up.
Power-Up Watchdog	DisabledEnabled	The Power Up Watchdog resets the system after a certain amount of time after power up.

# 7.4.6. Advanced > CSM Configuration

Feature	Options	Description
Compatibility Support Module Configuration	Info only
CSM Support	Disabled Enabled	Enabled / Disabled CSM Support.
CSM16 Module Version	Info only	Display CSM16 Module Version
GateA20 Active	Upon Request Always	UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.
Boot option filter	UEFI and Legacy Legacy only UEFI only	This option controls Legacy/UEFI ROMs priority
Option ROM execution	Info only
Network	Do not launch UEFI Legacy	Controls the execution of UEFI and Legacy PXE OpROM
Storage	Do not launch UEFI Legacy	Controls the execution of UEFI and Legacy Storage OpROM
Video	Do not launch UEFI Legacy	Controls the execution of UEFI and Legacy Video OpROM
Other PCI devices	Do not launch UEFI Legacy	Determines OpROM execution policy for devices other than Network, Storage, or Video

# 7.4.7. Advanced > Super IO Configuration

Feature	Options	Description
Super IO Configuration	Info only
Super IO Chip NCT5104D	Info only
Serial Port 1 Configuration	Submenu	Set Parameters of Serial Port 1 (COMA).
Serial Port 2 Configuration	Submenu	Set Parameters of Serial Port 2 (COMB).
Super IO Chip W83627DHG	Info Only
Serial Port 1 Configuration	Submenu	Set Parameters of Serial Port 1 (COMA).
Serial Port 2 Configuration	Submenu	Set Parameters of Serial Port 2 (COMB).

# 7.4.7.1. Advanced > Super IO Configuration > Serial Port 1 Configuration (NCT5104D)

Feature	Options	Description
Serial Port 1 Configuration	Submenu	Set Parameters of Serial Port 1 (COMA).
Serial Port 1 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=240h; IRQ=10;IO=240h; IRQ=3,4,5,6,7,10,11,12IO=248h; IRQ=3,4,5,6,7,10,11,12IO=250h; IRQ=3,4,5,6,7,10,11,12IO=258h; IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.

# 7.4.7.2. Advanced > Super IO Configuration > Serial Port 2 Configuration (NCT5104D)

Feature	Options	Description
Serial Port 2 Configuration	Submenu	Set Parameters of Serial Port 2 (COMB).
Serial Port 2 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=248h; IRQ=11;IO=240h; IRQ=3,4,5,6,7,10,11,12IO=248h; IRQ=3,4,5,6,7,10,11,12IO=250h; IRQ=3,4,5,6,7,10,11,12IO=258h; IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.

7.4.7.3. Advanced > Super IO Configuration > Serial Port 1 Configuration (W83627DHG)

Feature	Options	Description
Serial Port 1 Configuration	Submenu	Set Parameters of Serial Port 1 (COMA).
Serial Port 1 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=3F8h; IRQ=4;IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.

7.4.7.4. Advanced > Super IO Configuration > Serial Port 2 Configuration (W83627DHG)

Feature	Options	Description
Serial Port 2 Configuration	Submenu	Set Parameters of Serial Port 2 (COMB).
Serial Port 2 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=2F8h; IRQ=3;IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.

7.4.8. Advanced > Serial Console Redirection

Feature	Options	Description
COM1	Info only
Console Redirection	EnabledDisabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM2	Info only
Console Redirection	EnabledDisabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM3	Info only
Console Redirection	EnabledDisabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM4	Info only
Console Redirection	EnabledDisabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
Serial Port for Out-of-Band Management Windows Emergency Management Services (EMS)	Info only
Console Redirection	DisabledEnabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

7.4.8.1. Advanced > Serial Console Redirection > Console Redirection Settings (If COM1 Enable)

Feature	Options	Description
COM1	Info only
Console Redirection Settings	Info only
Teriminal Type	VT100VT100+VT-UTF8ANSI	Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key Support	EnabledDisabled	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnabled	With this mode enabled only text will be sent.This is to capture terminal data.
Resolution 100x31	EnabledDisabled	On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad	VT100Intel LinuxXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

7.4.8.2. Advanced > Serial Console Redirection > Console Redirection Settings (If COM2 Enable)

Feature	Options	Description
COM2	Info only
Console Redirection Settings	Info only
Teriminal Type	VT100VT100+VT-UTF8ANSI	Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key Support	EnabledDisabled	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnabled	With this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31	EnabledDisabled	On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad	VT100Intel LinuxXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

7.4.8.3. Advanced > Serial Console Redirection > Console Redirection Settings (If COM3 Enable)

Feature	Options	Description
COM3	Info only
Console Redirection Settings	Info only
Teriminal Type	VT100VT100+VT-UTF8ANSI	Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key Support	EnabledDisabled	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnabled	With this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31	EnabledDisabled	On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad	VT100Intel LinuxXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

7.4.8.4. Advanced > Serial Console Redirection > Console Redirection Settings (If COM4 Enable)

Feature	Options	Description
COM4	Info only
Console Redirection Settings	Info only
Teriminal Type	VT100VT100+VT-UTF8ANSI	Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key Support	EnabledDisabled	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnabled	With this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31	EnabledDisabled	On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad	VT100Intel LinuxXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

7.4.9. Advanced > USB Configuration

Feature	Options	Description
USB Configuration	Info Only
USB Module Version	Info Only	Display USB Module Version
USB Controllers:	Info Only	Display USB Controllers is XHCI or EHCI.
USB Devices:	Info Only	Display attatcment USB deviecs.
Legacy USB Support	EnabledDisabledAuto	Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.
XHCI Hand-off	EnabledDisabled	This is a workaround for Oses without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.
EHCI Hand-off	DisabledEnabled	This is a workaround for Oses without EHCI hand-off support. The EHCI ownership change should be claimed by EHCI driver.
USB Mass Storage Driver Support	DisabledEnabled	Enable / Disable USB Mass Storge Driver Support.
USB hardware delays and time-outs:	Info Only
USB transfer rime-out	1 sec5sec10sec20 sec	The time-out value for Control, Bulk, and Interrupt transfers.
Device reset time-out	10 sec20 sec30 sec40 sec	USB mass storage device Start Unit command time-out.
Device power-up delay	AutoManual	Maximum time the device will take before it properly reports itself to the Hot Controller.'Auto' uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.

7.4.10. Advanced > Network Stack Configuration

Feature	Options	Description
Network Stack	Disable Enable	Enable / Disable UEFI Network Stack.

# 7.4.11. Advanced > Miscellaneous

Feature	Options	Description
Miscellaneous	Info Only
NVMe Configuration	Submenu	NVMe Device Options Settings
Smart Battery Function	DisableEnable	Enable / Disable Battery Function
SPD write protect	DisableEnable	Enable:Writes to SMBus slave addresses A0h - AEh are disabled.
Onboard LAN Controller	DisabledEnabled	Enable/Disable onboard Intel I210LM LAN controller.
Wake On Lan from S5	DisabledEnabled	Enable or Disable the Wake on Lan from S5
BMC I2C Mode	400Kbps100Kbps	BMC I2C Mode
eMMC SPEED	HS400HS200	Adjust eMMC speed HS400/HS200

# 7.4.11.1. Advanced > Miscellaneous> NVMe Configuration

Feature	Options	Description
NVMe controller and Drive information	Info Only	NVMe controller and Drive information.
Bus:x Dev:x Func:x	Info only
Nvme Size	Info only

# 7.4.12. Advanced > TPM Configuration

Feature	Options	Description
TPM20 Device Found	Info Only
Security Device Support	Disable Enable	Enables or Disable BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.
Active PCR banks*	Info Only
Available PCR banks*	Info Only
SHA-1 PCR Bank*	Disabled Enabled	Enable or Disable SHA-1 PCR Bank
SHA256 PCR Bank*	Disabled Enabled	Enable or Disable SHA256 PCR Bank
Pending operation*	None TPM Clear	Schedule an Operation for the Security Device.NOTE: Your Computer will reboot during restart in order to change State of Security Device.

\*Note: Displayed if Security Device Support is enabled when TPM device is connected. 7.4.13. Advanced > Intel® I210 Gigabit Network Connection

Feature	Options	Description
Port Configuration Menu	Info only
NIC Configuration	Submenu
Link Speed	Auto Negotiated10 Mbps Half10Mbps Full100Mbps Half100Mbps Full	Specifies the port speed used for the selected boot protocol.
Wake On LAN	DisableEnable	Enables the server to be powered on using an in-band magic packet.
Blink LEDs	0	Identify the physical network port by blinking the associated LED
Port Configuration Information	Info Only
UEFI Driver:	Info Only
Adapter PBA:	Info Only
Chip Type	Info Only
PCI Device ID	Info Only
PCI Address	Info Only
Link Status	Info Only
MAC Address	Info Only
Virtual MAC Address	Info Only

7.4.14. Advanced > Intel® Ethernet Connection X553 10 GbE SFP+

Feature	Options	Description
NIC Configuration	Submenu
Link Speed	Auto Negotiated10 Mbps Half10Mbps Full100Mbps Half100Mbps Full	Specifies the port speed used for the selected boot protocol.
Wake On LAN	DisableEnable	Enables the server to be powered on using an in-band magic packet.
Blink LEDs	0	Identify the physical network port by blinking the associated LED
Port Configuration Information	Info Only
UEFI Driver:	Info Only
Adapter PBA:	Info Only
Chip Type	Info Only
PCI Device ID	Info Only
PCI Address	Info Only
Link Status	Info Only
MAC Address	Info Only
Virtual MAC Address	Info Only

# 7.5. Event Logs # 7.5.1. Event Logs >Change SMBIOS Event Log Settings

Feature	Options	Description
Enabling/Disabling Options	Info only
SMBIOS Event Log	DisabledEnabled	Change this to enable or disable all features of SMBIOS Event Logging during boot.
Erasing Setting	Info only
Erase Event Log	NoYes, Next resetYes, Every reset	Choose options for erasing SMBIOS Event Log.Erasing is done prior to any logging activation during reset.
When Log is Full	Do NothingErase Immediately
SMBIOS Event Log Standard Settings	Info only
Log System Boot Event	DisabledEnabled	Choose option to enable/disable logging of System boot event
MECI	1	Multiple Event Count Increment: The number of occurrences of a duplicate event that must pass before the multiple-event counter of log entry is updated. The value ranges from 1 to 255.
METW	60	Multiple Event Time Window: The number of minutes which must pass between duplicate log entries which utilize a multiple-event counter. The value ranges from 0 to 99 minutes.
Custom Options	Info only
Log OEM Codes	DisabledEnabled	Enable or disable the logging of EFI Status Codes as OEM Codes (if not already converted to legacy).
Convert OEM Codes	DisabledEnabled	Enable or disable the converting of EFI Status Codes to Standard SMBIOS Types (Not all may be translated).

# 7.5.2. Event Logs >View SMBIOS Event Log

Feature	Options	Description
Date Time Error Code Severity	Info only

# 7.6. Security 7.6.1. Security > Password Description

Feature	Options	Description
Password Description	Info only
Setup Administrator Password	Enter Password	Set Setup Administrator Password
User Password	Enter Password	Set User Password
Secure Boot menu	Submenu	Customizable Secure Boot settings.
System Mode	Info only
Secure Boot	Info only
Secure Boot Control	DisabledEnabled	Secure Boot activated when\n Platform Key(PK) is enrolled,\n System mode is User/Deployed,\n and CSM function is disabled

7.7. Boot

Feature	Options	Description
Boot Configuration	Info only
Setup Prompt Timeout	1	Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.
Bootup NumLock State	On Off	Select the keyboard Number state.
Ouiet Boot	Disabled Enabled	Select the keyboard NumLock state.
Fast Boot	Disabled Enabled	Enable or Disable FastBoot features. Most probes are skipped to reduce time cost during boot.
SATA Support	All SATA Devices Last Boot HDD Only"	Last Boot HDD Only: only last boot HDD device will be available in POST. All SATA Devices: all SATA devices will be available in OS and POST.
VGA Support	EFI Driver Auto	Auto: only install Legacy OpRom with Legacy OS and logo will NOT be shown during POST. EFI Driver: will still be installed with EFI OS.
USB Support	Disabled Full Initial Partial Initial	If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Full Initial, all USB devices will be available in OS and Post.
PS2 Devices Support	Disabled Enabled	If Disabled, PS2 devices will be skipped.
NetWork Stack Driver Support	Disabled Enabled	If Disabled, NetWork Stack Driver will be skipped.
Boot mode select	UEFI Legacy	Select boot mode LEGACY/UEFI

7.7.1. Boot > Fixed Boot Order Priorities

Feature	Options	Description
Boot Option #1	Hardware	Set the system boot order.
Boot Option #2	CD/DVD	Set the system boot order.
Boot Option #3	USB Hard Disk	Set the system boot order.
Boot Option #4	USB CD/DVD	Set the system boot order.
Boot Option #5	USB Key	Set the system boot order.
Boot Option #6	USB Floppy	Set the system boot order.
Boot Option #7	USB Lan	Set the system boot order.
Boot Option #8	Network	Set the system boot order.

This page intentionally left blank. # 8. BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Aptio Boot Flow While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions: • Security (SEC) – initial low-level initialization - Pre-EFI Initialization (PEI) – memory initialization $^{1}$ - Driver Execution Environment (DXE) – main hardware initialization $^{2}$ - Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, ...) # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints. $^{1}$ Analogous to “bootblock” functionality of legacy BIOS $^{2}$ Analogous to “POST” functionality in legacy BIOS # 8.1. Status Code Ranges

Status Code Range	Description
0x01 – 0x0B	SEC execution
0x0C – 0x0F	SEC errors
0x10 – 0x2F	PEI execution up to and including memory detection
0x30 – 0x4F	PEI execution after memory detection
0x50 – 0x5F	PEI errors
0x60 – 0x8F	DXE execution up to BDS
0x90 – 0xCF	BDS execution
0xD0 – 0xDF	DXE errors
0xE0 – 0xE8	S3 Resume (PEI)
0xE9 – 0xEF	S3 Resume errors (PEI)
0xF0 – 0xF8	Recovery (PEI)
0xF9 – 0xFF	Recovery errors (PEI)

# 8.2. Standard Status Codes # 8.2.1. SEC Phase

Status Code	Description
0x00	Not used
Progress Codes
0x01	Power on. Reset type detection (soft/hard).
0x02	AP initialization before microcode loading
0x03	North Bridge initialization before microcode loading
0x04	South Bridge initialization before microcode loading
0x05	OEM initialization before microcode loading
0x06	Microcode loading
0x07	AP initialization after microcode loading
0x08	North Bridge initialization after microcode loading
0x09	South Bridge initialization after microcode loading
0x0A	OEM initialization after microcode loading
0x0B	Cache initialization
SEC Error Codes
0x0C – 0x0D	Reserved for future AMI SEC error codes
0x0E	Microcode not found
0x0F	Microcode not loaded

# 8.2.2. SEC Beep Codes None # 8.2.3. PEI Phase

Status Code	Description
Progress Codes
0x10	PEI Core is started
0x11	Pre-memory CPU initialization is started
0x12	Pre-memory CPU initialization (CPU module specific)
0x13	Pre-memory CPU initialization (CPU module specific)
0x14	Pre-memory CPU initialization (CPU module specific)
0x15	Pre-memory North Bridge initialization is started
0x16	Pre-Memory North Bridge initialization (North Bridge module specific)
0x17	Pre-Memory North Bridge initialization (North Bridge module specific)
0x18	Pre-Memory North Bridge initialization (North Bridge module specific)
0x19	Pre-memory South Bridge initialization is started
0x1A	Pre-memory South Bridge initialization (South Bridge module specific)
0x1B	Pre-memory South Bridge initialization (South Bridge module specific)
0x1C	Pre-memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2A	OEM pre-memory initialization codes
0x2B	Memory initialization. Serial Presence Detect (SPD) data reading
0x2C	Memory initialization. Memory presence detection
0x2D	Memory initialization. Programming memory timing information
0x2E	Memory initialization. Configuring memory
0x2F	Memory initialization (other).
0x30	Reserved for ASL (see ASL Status Codes section below)
0x31	Memory Installed
0x32	CPU post-memory initialization is started
0x33	CPU post-memory initialization. Cache initialization
0x34	CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35	CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36	CPU post-memory initialization. System Management Mode (SMM) initialization
0x37	Post-Memory North Bridge initialization is started
0x38	Post-Memory North Bridge initialization (North Bridge module specific)
0x39	Post-Memory North Bridge initialization (North Bridge module specific)
0x3A	Post-Memory North Bridge initialization (North Bridge module specific)
0x3B	Post-Memory South Bridge initialization is started
0x3C	Post-Memory South Bridge initialization (South Bridge module specific)
0x3D	Post-Memory South Bridge initialization (South Bridge module specific)
0x3E	Post-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4E	OEM post memory initialization codes
0x4F	DXE IPL is started
PEI Error Codes
0x50	Memory initialization error. Invalid memory type or incompatible memory speed
0x51	Memory initialization error. SPD reading has failed
0x52	Memory initialization error. Invalid memory size or memory modules do not match.
0x53	Memory initialization error. No usable memory detected
0x54	Unspecified memory initialization error.
0x55	Memory not installed
0x56	Invalid CPU type or Speed
0x57	CPU mismatch
0x58	CPU self test failed or possible CPU cache error
0x59	CPU micro-code is not found or micro-code update is failed
0x5A	Internal CPU error
0x5B	reset PPI is not available
0x5C-0x5F	Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0	S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1	S3 Boot Script execution
0xE2	Video repost
0xE3	OS S3 wake vector call
0xE4-0xE7	Reserved for future AMI progress codes
S3 Resume Error Codes
0xE8	S3 Resume Failed
0xE9	S3 Resume PPI not Found
0xEA	S3 Resume Boot Script Error
0xEB	S3 OS Wake Error
0xEC-0xEF	Reserved for future AMI error codes
Recovery Progress Codes
0xF0	Recovery condition triggered by firmware (Auto recovery)
0xF1	Recovery condition triggered by user (Forced recovery)
0xF2	Recovery process started
0xF3	Recovery firmware image is found
0xF4	Recovery firmware image is loaded
0xF5-0xF7	Reserved for future AMI progress codes
Recovery Error Codes
0xF8	Recovery PPI is not available
0xF9	Recovery capsule is not found
0xFA	Invalid recovery capsule
0xFB – 0xFF	Reserved for future AMI error codes

8.2.4. PEI Beep Codes

# of Beeps	Description
1	Memory not Installed
1	Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
2	Recovery started
3	DXEIPL was not found
3	DXE Core Firmware Volume was not found
4	Recovery failed
4	S3 Resume failed
7	Reset PPI is not available

8.2.5. DXE Status Codes

Status Code	Description
0x60	DXE Core is started
0x61	NVRAM initialization
0x62	Installation of the South Bridge Runtime Services
0x63	CPU DXE initialization is started
0x64	CPU DXE initialization (CPU module specific)
0x65	CPU DXE initialization (CPU module specific)
0x66	CPU DXE initialization (CPU module specific)
0x67	CPU DXE initialization (CPU module specific)
0x68	PCI host bridge initialization
0x69	North Bridge DXE initialization is started
0x6A	North Bridge DXE SMM initialization is started
0x6B	North Bridge DXE initialization (North Bridge module specific)
0x6C	North Bridge DXE initialization (North Bridge module specific)
0x6D	North Bridge DXE initialization (North Bridge module specific)
0x6E	North Bridge DXE initialization (North Bridge module specific)
0x6F	North Bridge DXE initialization (North Bridge module specific)
0x70	South Bridge DXE initialization is started
0x71	South Bridge DXE SMM initialization is started
0x72	South Bridge devices initialization
0x73	South Bridge DXE Initialization (South Bridge module specific)
0x74	South Bridge DXE Initialization (South Bridge module specific)
0x75	South Bridge DXE Initialization (South Bridge module specific)
0x76	South Bridge DXE Initialization (South Bridge module specific)
0x77	South Bridge DXE Initialization (South Bridge module specific)
0x78	ACPI module initialization
0x79	CSM initialization
0x7A – 0x7F	Reserved for future AMI DXE codes
0x80 – 0x8F	OEM DXE initialization codes
0x90	Boot Device Selection (BDS) phase is started
0x91	Driver connecting is started
0x92	PCI Bus initialization is started
0x93	PCI Bus Hot Plug Controller Initialization
0x94	PCI Bus Enumeration
0x95	PCI Bus Request Resources
0x96	PCI Bus Assign Resources
0x97	Console Output devices connect
0x98	Console input devices connect
0x99	Super IO Initialization
0x9A	USB initialization is started
0x9B	USB Reset
0x9C	USB Detect
0x9D	USB Enable
0x9E – 0x9F	Reserved for future AMI codes
0xA0	IDE initialization is started
0xA1	IDE Reset
0xA2	IDE Detect
0xA3	IDE Enable
0xA4	SCSI initialization is started
0xA5	SCSI Reset
0xA6	SCSI Detect
0xA7	SCSI Enable
0xA8	Setup Verifying Password
0xA9	Start of Setup
0xAA	Reserved for ASL (see ASL Status Codes section below)
0xAB	Setup Input Wait
0xAC	Reserved for ASL (see ASL Status Codes section below)
0xAD	Ready To Boot event
0xAE	Legacy Boot event
0xAF	Exit Boot Services event
0xB0	Runtime Set Virtual Address MAP Begin
0xB1	Runtime Set Virtual Address MAP End
0xB2	Legacy Option ROM Initialization
0xB3	System Reset
0xB4	USB hot plug
0xB5	PCI bus hot plug
0xB6	Clean-up of NVRAM
0xB7	Configuration Reset (reset of NVRAM settings)
0xB8 – 0xBF	Reserved for future AMI codes
0xC0 – 0xCF	OEM BDS initialization codes
DXE Error Codes
0xD0	CPU initialization error
0xD1	North Bridge initialization error
0xD2	South Bridge initialization error
0xD3	Some of the Architectural Protocols are not available
0xD4	PCI resource allocation error. Out of Resources
0xD5	No Space for Legacy Option ROM
0xD6	No Console Output Devices are found
0xD7	No Console Input Devices are found
0xD8	Invalid password
0xD9	Error loading Boot Option (LoadImage returned error)
0xDA	Boot Option is failed (StartImage returned error)
0xDB	Flash update is failed
0xDC	Reset protocol is not available

# 8.2.6. DXE Beep Codes

# of Beeps	Description
1	Invalid password
4	Some of the Architectural Protocols are not available
5	No Console Output Devices are found
5	No Console Input Devices are found
6	Flash update is failed
7	Reset protocol is not available
8	Platform PCI resource requirements cannot be met

# 8.2.7. ACPI/ASL Checkpoint

Status Code	Description
0x01	System is entering S1 sleep state
0x02	System is entering S2 sleep state
0x03	System is entering S3 sleep state
0x04	System is entering S4 sleep state
0x05	System is entering S5 sleep state
0x10	System is waking up from the S1 sleep state
0x20	System is waking up from the S2 sleep state
0x30	System is waking up from the S3 sleep state
0x40	System is waking up from the S4 sleep state
0xAC	System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAA	System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

# 8.3. OEM-Reserved Checkpoint Ranges

Status Code	Description
0x05	OEM SEC initialization before microcode loading
0x0A	OEM SEC initialization after microcode loading
0x1D – 0x2A	OEM pre-memory initialization codes
0x3F – 0x4E	OEM PEI post memory initialization codes
0x80 – 0x8F	OEM DXE initialization codes
0xC0 – 0xCF	OEM BDS initialization codes

This page intentionally left blank. # 9. Mechanical Information # 9.1. Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. # Tyco 3-1827253-6 # Foxconn QT002206-2131-3H - 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. - This connector can be used with 5 mm through-hole standoffs (SMT type). ![Exterior view of a multi-layered electronic component with metallic pins and mounting holes (no text or symbols visible)](.express-dn7-50m-00049-1020-12/17f2936f4abb337549dd90ee63cb04db08c601da184abe29e1c41b2cd92a3c91.jpg) # Tyco 3-6318491-6 # Foxconn QT002206-4141-3H - 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm. - This connector can be used with 8 mm through-hole standoffs (SMT type). ![Exterior view of a rectangular electronic component with multiple slots and mounting holes (no text or symbols visible)](.express-dn7-50m-00049-1020-12/24b3d4716c96f72345cb9374168a5ce14d336915b187227ddefbc09fa2ca2121.jpg) # Common Specifications • Current capacity: 0.5A per pin • Rated voltage: 50 VAC • Insulation resistance: 100M or greater @ 500 VDC • Temperature rating: $-40^{\circ}C \sim 85^{\circ}C$ • UL certification (ECBT2.E28476) • Copper alloy (contacts) • Housing: thermo-plastic molded compound (L.C.P.) # 9.2. Thermal Solution # 9.2.1. Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. # 9.2.2. Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. # 9.2.3. Installation Install a heat spreader or heat sink using the following instructions. Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module. ![Hand in white glove holding a green printed circuit board with multiple components, set against a green background (no visible text or symbols)](.express-dn7-50m-00049-1020-12/7818ca3834d0cc135af54810b38b1d70a051cde2a6ae4ffc83db11c278c948e3.jpg) Step 2: Remove the protective membranes from the thermal pads. ![Close-up of a small green textured object being processed with tweezers, placed on a white surface (no text or symbols visible)](.express-dn7-50m-00049-1020-12/154896700ed9ccafc101fcfc3d26597dd7efaed4adcf7885f5d2abb8f6a17467.jpg) Step 3: Assemble the heatsink onto the COM Express module. Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. ![Close-up of a green printed circuit board with ADLINK logo and soldering probe, no visible text or symbols on components](.express-dn7-50m-00049-1020-12/82f24ad4587956dc12e3ca5b59be1288c41d1acc0ae590892ae6a5221b7ea559.jpg) ![Four metallic screw or connector pins arranged horizontally on a plain background (no text or symbols visible)](.express-dn7-50m-00049-1020-12/39e54ac241dc8f5e30178d892d1df8d91582fb39e234488bc792de93041915a2.jpg) Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. ![Close-up of a green circuit board with electronic components and a white hard drive component (no visible text or symbols)](.express-dn7-50m-00049-1020-12/8f62793b9cbd579784fb51f3dbe39819efd111242a8f88358fc8bd7155819b70.jpg) Then press down on the module until it is firmly seated on the carrier board. Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. ![Close-up of a green printed circuit board with multiple electronic components and red circular annotations (no readable text or symbols)](.express-dn7-50m-00049-1020-12/3a11ef03cdf8a616b8b5af277bfab8a572e44ef86e92d592b1b0ac445818a16d.jpg) ![Five metallic screw pins arranged horizontally on a plain background (no text or symbols visible)](.express-dn7-50m-00049-1020-12/383c90dcfb8ed60a2cce0c41d6c267db7ebc33444f79ebb55bc0b4c7759b92fc.jpg) Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown. ![Close-up of a green printed circuit board with electronic components and a hand holding a cooling fan (no visible text or symbols)](.express-dn7-50m-00049-1020-12/78336c08b805f76c94eeedcf88060247f24c621cf91195adf380690f4bd19af7.jpg) # 9.3. Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs. ![Top Mounting\nwith 5 mm connectors\nM2.5 : 18 mm\nwith spring / was r\nØ27\nØ5C\n9 nm heatsprader with\n9 mm through-hole standoffs](.express-dn7-50m-00049-1020-12/e9ad9771290d7b5ff94b1cf99f3769c42503fb3633f8244cff9d75cd82e936aa.jpg) Figure 6: COM Express Mounting Methods COM Express Module \~ 2 mm M2 5 ∅55 ∅38 5 mm threaded standoff (DIP) # 9.4. Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type)P/N: 33-72000-0050<img src="images/219cf5c717dfb3fe6c678729702fd1d06a89fc936075124a05dd4444057d9ff6.jpg"/>	5mm threaded standoff (DIP type)P/N: 33-72016-0050<img src="images/67bc22fa21d1074b5eafd2c3a1b4f7fe4ea1a0e14703a0e9aedb47c94ac17dfd.jpg"/>
8mm through-hole standoff (SMT type)P/N: 33-72000-0080<img src="images/d27b160b8f4e2ebb1de2231d985d42b2f083d7439e652e6288b4822656574599.jpg"/>	8mm threaded standoff (DIP type)P/N: 33-72015-0050<img src="images/c77f216b9ddae710390fc3b9ccbfe323e3b1da08b7e780847935bf288d170330.jpg"/>

Figure 7: COM Express Standoff Types # Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. - Please read these safety instructions carefully. - Please keep this User's Manual for later reference. - Read the specifications section of this manual for detailed information on the operating environment of this equipment. - When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables. • To avoid electrical shock and/or damage to equipment: - Keep equipment away from water or liquid sources. - Keep equipment away from high heat or high humidity. - Keep equipment properly ventilated (do not block or cover ventilation openings). ■ Make sure to use recommended voltage and power source settings. ■ Always install and operate equipment near an easily accessible electrical socket-outlet. - Secure the power cord (do not place any object on/over the power cord). - Only install/attach and operate equipment on stable surfaces and/or recommended mountings. - If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. \- Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. # Getting Service Ask an Expert: http://askanexpert.adlinktech.com # ADLINK Technology, Inc. No. 66, Huaya 1st Road, Guishan District, Taoyuan City 333, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5723 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Address: Hans-Thoma-Straße 11, D-68163, Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. [🔗 Link to the original document](.express-dn7-50m-00049-1020-12/express-dn7-50m-00049-1020-12.pdf)