# COM Express # Express-DW400 # User’s Manual ![Close-up of a green printed circuit board with multiple microchips and electronic components (no readable text or symbols)](.express-dw400-50-1j011-1010-201/88432879a64b831c80ea3f4f48f7ddd297c98f8f17295ae0d35f89d8fbd2ab9e.jpg) Manual Revision: 2.01 Revision Date: March 2, 2009 Part Number: 50-1J011-1010 Revision History
ReleaseDateChange(s)
2.002008/11/20Initial Release
2.012009/03/02Correct Signal Descriptions
# Table of Contents Express-DW400 .. Preface . 5 1 Introduction .. 1.1 Description .. 2 Specifications.. 9 2.1 General ... 9 2.2 Video . .. 10 2.3 LAN . . 10 2.4 Multi I/O . .. 10 2.5 Super I/O . . 11 2.6 TPM (Trusted Platform Module) . . 11 2.7 Power Specifications . . 11 2.9 Operating Systems . .. 13 2.10 Mechanical and Environmental . . 13 3 Function diagram .. . 14 4 Mechanical Dimensions . 15 5 Watch Dog Timer (WDT) . . 16 5.1 Overview . . 16 5.2 Installing the WDT Driver .. . 16 5.3 Interface with the Driver . .17 5.4 Watch Dog Timer Windows® XP Demo Utility .. .. 22 5.5 Using the Demo Application .. .. 23 6 Connectors .. . 27 6.1 COM Express® Type 2 ... .27 6.2 COM Express® Board to Board Connectors . .. 28 6.3 Signal Descriptions ...... .. 30 # 7 System Resources. . 39 7.1 System Memory Map ....... . 39 7.2 Direct Memory Access Channels .. . 39 7.3 I/O Map ....... ... 40 7.4 Interrupt Request (IRQ) Lines . . 42 7.5 PCI Configuration Space Map . . 44 7.6 PCI Interrupt Routing Map . 44 7.7 System Management Bus (I2C compatible) ... 45 # 8 BIOS Setup Utility .. . 46 8.1 Starting the BIOS .. .. 46 8.2 Main Setup ....... . 50 8.3 Advanced BIOS Setup . .51 8.4 Power Setup.. . 68 8.5 Boot Setup.. . 73 8.6 Security Setup .. .. 76 8.7 Exit Menu . .. 79 # 9 BIOS Checkpoints, Beep Codes .. . 81 9.1 Bootblock Initialization Code Checkpoints.. . 82 9.2 Bootblock Recovery Code Checkpoints . . 83 9.3 POST Code Checkpoints . .84 9.4 OEM POST Error Checkpoints . . 86 9.5 DIM Code Checkpoints ... . 86 9.6 ACPI Runtime Checkpoints. .87 9.7 Boot Block Beep Codes . .. 88 9.8 POST BIOS Beep Codes.. . 88 9.9 Troubleshooting POST BIOS Beep Codes .... . 89 # Appendix A: Available USB Ports. . 90 A.1 Description . . 90 # Important Safety Instructions. . 92 # Getting Service . . 94 # Preface # Copyright 2009 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks AMIBIOS®8 is a registered trademark of American Megatrends, Inc. COM Express™, and PICMG® are registered trademarks of the PCI Industrial Computer Manufacturers Group. Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image displays a white document icon featuring a large red checkmark on the left side. Below the icon is the text 'NOTE:' written in black, uppercase letters.](.express-dw400-50-1j011-1010-201/f1e09085cbe8825ff8ee014b93e720f1039152f1add1d8378d4681010b2c4d95.jpg) Additional information, aids, and tips that help users perform tasks. ![A low-resolution image showing a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION:' is printed in black capital letters.](.express-dw400-50-1j011-1010-201/38a617b15ad78c1b45af37d09174a731b68b211eb81cdc26d05cb60de096c505.jpg) Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image features a triangular warning sign with a white border and a red background. Inside the triangle is a large white exclamation point. Below the triangle is the text 'WARNING:' printed in black capital letters.](.express-dw400-50-1j011-1010-201/d45b5648ddbedceb17bcaf56bbb54efc3b751d69712d6303d9d71616c7a36560.jpg) Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # 1 Introduction # 1.1 Description The Express-DW400 is based on the Intel® 3100 single chip, server-class chipset. The Intel® 3100 Chipset is a single integrated chip that contains the functionality of a Memory Controller Hub and an I/O Controller Hub. It can support Intel® Core™ Duo and Intel® Core™2 Duo CPUs from 1.06 GHz up to 2.1 GHz at 667MHz FSB. The Intel® 3100 chipset combines server-class memory and I/O controller functions into a single component, creating the first integrated Intel® chipset specifically optimized for embedded, communications, and storage applications. Both chipset and processors are part of the Embedded Intel® Architecture (IA) that warrants long production life for applications that need extended availability. ![The image features the Intel Core Duo logo. It is a rounded rectangle divided horizontally. The upper white section displays the blue 'intel' logo within a swoosh. The lower blue section contains the white text 'Core' stacked above 'Duo,' followed by the italicized white word 'inside.' Small 'TM' symbols are positioned next to 'Core' and 'inside.'](.express-dw400-50-1j011-1010-201/cfd98cb4f9728eb47a98063609829c6ace45d09147f477b30b100ca3d6f64488.jpg) ![The image displays the Intel Core 2 Duo logo badge. It features the 'intel' logo in blue at the top. Below that is the text 'Core™ 2' stacked above 'Duo' in blue lettering. In the bottom right corner, on a blue background, is the text 'inside™' in white.](.express-dw400-50-1j011-1010-201/e3035671934469ece8dbd65fe66c43337314337efd0fef950a33c2670c8ed579.jpg) ![Close-up of a green integrated circuit chip with Intel logo (no text or symbols beyond branding)](.express-dw400-50-1j011-1010-201/4d9717594cb6e9a837ccad06c2a99c3c3b0836b51f557d1240026c96e2f178b9.jpg) # ECC Memory Support The Express-DW400 supports registered ECC type, single channel DDR2 400MHz memory. The module is available with either two vertically placed SODIMM sockets or one horizontally placed SODIMM socket. A single SODIMM can support up to 2 GB of memory allowing maximum support of 4 GB memory if the two vertical socket configuration is used. # High Bandwidth PCI Express up to x8 The Intel® 3100 chipset provides one configurable x8 PCI Express interface with a maximum theoretical bandwidth of 4 GByte/s. The x8 PCI Express interface may alternatively be configured as two independent x4 PCI Express interfaces with a maximum theoretical bandwidth of 2 GBytes/s each. The Intel® 3100 Chipset also supports an additional x4 PCI Express interface with a maximum theoretical bandwidth of 2 GBytes/s which may alternatively be configured as four independent x1 PCI Express interfaces. Of these four x1 lanes, one is occupied by the Ethernet controller and three are extended to the carrier board. ![Intel®\n3100\nChipset\nx1\nx1\nx1\n(x1)\nx4\nx4\n} x8](.express-dw400-50-1j011-1010-201/877357fd65a55d73b75a3998f59d3b7dbe886ea72b70d2a94b8986ae9cf00484.jpg) # EDMA on PCI Express The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA) controller to perform background data transfers between locations in main memory, or from main memory to a memory-mapped I/O destination. These transfers may be individually designated to be coherent (snooped on the FSB) or non-coherent (not snooped on the FSB), providing improvements in system performance and utilization when cache coherence is managed by software rather than hardware # Other Features The module comes with a single onboard Gigabit Ethernet port and four channel SATA. It has legacy support for Parallel IDE, 32-bit PCI and LPC bus support. The Express-DW400 comes equipped with many embedded features such as: Remote console, CMOS backup, CPU and System monitoring and a Dual Watchdog timer for NMI or RESET. Express-DW400 is RoHS compliant and leadfree product ![ADLINK\nGREEN](.express-dw400-50-1j011-1010-201/a3e4d5da49158c4e262194ececef63bc21633878c4fd796d8fc8e9119ad7bbc6.jpg) # 2 Specifications # 2.1 General f CPU: Merom Core socket type Intel® Core™ 2 Duo T7400, 2.16 GHz with 4MB L2 cache, 34 W Intel® Celeron® M 530, 1.73 GHz, with 1MB L2 cache 27 W Merom Core BGA type Intel® Core™ 2 Duo U7500 ULV 1.06 GHz with 2MB L2 cache, 10 W Yonah Core socket type Intel® Celeron® M 440, 1.86 GHz, with 1MB L2 cache 27 W Yonah Core BGA type Intel® Celeron M 423 ULV 1.06GHz, with 1MB L2 cache 5.5 W f Memory: Single channel registered ECC DDR2 at 400MHz up to 4 GB Option 1: one horizontal SODIMM socket, max. 2 GB Option 2: two vertical SODIMM sockets, max. 4 GB ![Close-up of a green printed circuit board with multiple microchips and connectors (no visible text or symbols)](.express-dw400-50-1j011-1010-201/91d04c1610546f7c7c24f665f111ba64860025151ffc6e0b289fbb44197466ce.jpg) Option 1 Memory Configuration Option 2 Memory Configuration ![Close-up of a green computer motherboard with visible CPU socket and cooling slots (no text or symbols)](.express-dw400-50-1j011-1010-201/0cb114424a3361f12b27eb79eee850a15764439ff699b523231c734505fdb152.jpg) f Chipset: Intel® 3100 single integrated chipset containing MCH and ICH f L2 Cache: 1 MB (Celeron® M), 2/4 MB (Core (2) Duo) f BIOS: AMIBIOS8 with CMOS backup in 8 Mbit LPC BIOS f Hardware Monitor: Supply Voltages and CPU temperature f Watchdog Timer: Dual stage watchdog timer f Expansion Busses: - One PCI Express® x8 lane can also be used as two PCI Express® x4 lanes - Four PCIe x1 lanes (one occupied by onboard GbE) - Four 32-bit PCI 2.3 Masters at 33/66 MHz - Low Pin Count (LPC) interface for Super I/O on carrier - SMBus interface support - Four GPIO input, Four GPIO output f Power Mode Support: \- ACPI 2.0, supports S0, S3, S4, S5 power modes # 2.2 Video f No integrated video support f On carrier: optional VGA support can be obtained by using PCI or PCI Express® x1, X4 or X8 based VGA cards # 2.3 LAN f Chipset: Intel® 82573 PCIe-based Gigabit Ethernet connection f Type: Triple speed 10/100/1000BASE-T IEEE 802.3 compliant which supports ASF 2.0 and Advanced Pass # 2.4 Multi I/O f Chipset: integrated in Intel® 3100 f USB: supports up to four USB 2.0 ports, supports legacy keyboard/mouse f SATA: four integrated Serial ATA 150 ports f PATA IDE: single channel IDE for CF card support (SATA to IDE conversion) # 2.5 Super I/O f Connected to LPC bus on carrier if needed # 2.6 TPM (Trusted Platform Module) f Chipset: Infineon SLB9635TT1.2 f Type: TPM 1.2 # 2.7 Power Specifications f Input Power: AT mode (12 V) and ATX mode (12 V and $5 \mathrm { \Delta V _ { s B } } )$ f Power Management: ACPI 2.0 compliant All power testing was done on power supply wiring leading to the Express carrier board. Although all voltages were measured, only 12 V and $5 \vee _ { \mathbb { S } \mathbb { B } }$ are relevant because they are the only ones used by the Express module. The Idle power level was measured under Windows XP with no applications running (logon screen). CPU Stress was measured using only Kpower, and Total System Stress was measured under heavy burn-in conditions. ![Yellow lightning bolt symbol on white background (no text or symbols)](.express-dw400-50-1j011-1010-201/d48236ad534bd9971b6e15ad322731f401f116144c2a379d30e7c561205703b5.jpg) Intel® Core™2 Duo T7400, 2.16 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)4.21 AN.S.50.5 W
Windows XP logon screen (idle)4.33 AN.S.52.0 W
Windows XP CPU Stress (Kpower)4.54 AN.S.54.4 W
Windows XP Total System Stress (Burnin)4.47 AN.S.53.6 W
S4 Mode (hibernate)-207.4 mA1.02 W
S3 Mode (suspend to RAM)-442.9 mA2.21 W
Intel® Celeron® M 530, 1.73 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)4.66 AN.S.55.9 W
Windows XP logon screen (idle)4.68 AN.S.56.1 W
Windows XP CPU Stress (Kpower)5.03 AN.S.60.4 W
Windows XP Total System Stress (Burnin)4.74 AN.S.56.9 W
S4 Mode (hibernate)-203.1 mA1.01 W
S3 Mode (suspend to RAM)-427.8 mA2.14 W
Intel® Core™2 Duo U7500 ULV, 1.06 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)3.54 AN.S.42.4 W
Windows XP logon screen (idle)3.47 AN.S.41.6 W
Windows XP CPU Stress (Kpower)3.97 AN.S.47.6 W
Windows XP Total System Stress (Burnin)3.74 AN.S.44.9 W
S4 Mode (hibernate)-219.7 mA1.10 W
S3 Mode (suspend to RAM)-506.8 mA2.53 W
Intel® Celeron® M 440, 1.86 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)4.63 AN.S.55.5 W
Windows XP logon screen (idle)4.52 AN.S.54.2 W
Windows XP CPU Stress (Kpower)4.76 AN.S.57.1 W
Windows XP Total System Stress (Burnin)4.67 AN.S.56.1 W
S4 Mode (hibernate)-318.9 mA1.59 W
S3 Mode (suspend to RAM)-316.9 mA1.58 W
Intel® Celeron® M 423 ULV, 1.06 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)3.91 AN.S.46.9 W
Windows XP logon screen (idle)4.10 AN.S.49.2 W
Windows XP CPU Stress (Kpower)4.30 AN.S.51.7 W
Windows XP Total System Stress (Burnin)4.18 AN.S.50.2 W
S4 Mode (hibernate)-105.7 mA0.53 W
S3 Mode (suspend to RAM)-307.5 mA1.54 W
CMOS/RTC Battery Power Consumption
CurrentVoltage
3.5 μA+3 V
# 2.9 Operating Systems f Standard Support Windows XP (32/64-bit) Linux 2.6.x f Extended Support (BSP) - Linux 2.6.x BSP (32/64-bit) - AIDI I2C Library for Windows and Linux # 2.10 Mechanical and Environmental f Form Factor and Type: PICMG COM.0, Standard COM Express™ Type II f Dimensions: 95 x 125 mm f Standard Operating Temperature: $0 ^ { \circ } \complement$ to $6 0 ^ { \circ } \complement$ f Relative Humidity: up to 90% at $5 5 ^ { \circ } \complement$ # 3 Function diagram ![The diagram illustrates a motherboard architecture centered around the **MCH + ICH** (Intel® 3100) chipset.\n\n**Central Components and Connections:**\n* **CPU:** A block at the top lists 'CPU', 'Celeron® M', 'Core™ Duo', 'Core™ 2 Duo', 'SMT µFCBGA2', and 'or µFCPGA2'. It connects via a double-headed arrow labeled **FSB 533/667 Mhz** to the **MCH + ICH** block.\n* **Memory:** To the right of the MCH, a **DDR2 Memory Controller with ECC** connects via double-headed arrows labeled **Channel A** to two memory blocks: **DDR2 400 MHz SO-RDIMM socket (horizontal x1)** and **DDR2 400 MHz SO-RDIMM socket (optional 2x vertical)**.\n* **PCIe Expansion:** Below the memory controller is a block labeled **PCIe with EDMA**, detailing 'One PCIe x 8', 'Two PCIe x4 or', and 'Two PCIe x1'. This connects via an arrow labeled **PCIe x8 (or 2 x4, or 2 x1)** to the vertical **CD** bar.\n\n**Peripheral Connections (Left Side / AB Bar):**\n* **LAN:** A **GBe LAN** (Intel 82573) block connects to the MCH via an arrow labeled **PCIe x1, lane 0**.\n* **PCIe Lanes:** The MCH connects to the vertical **AB** bar via arrows labeled **PCIe x1, lane 1/2/3** and **Four PCIe x1 lanes**.\n* **Storage and USB:** The MCH connects to dashed boxes for **1x SATA**, **4x SATA**, and **4x USB 2.0**.\n * The **1x SATA** path goes via **SATA_0** to a **SATA to PATA** (JM20330) block, which connects to **IDE**, which finally connects to the **CD** bar.\n * The **4x SATA** path goes via **SATA_1/2/3/4** to the **AB** bar.\n * The **4x USB 2.0** path goes via **USB_0/1/2/3** to the **AB** bar.\n * A dashed **RTC** block is situated near these connections.\n* **Low Speed Buses:** The **AB** bar connects to blocks labeled **GPIO**, **I2C**, and **SMBus**. The **SMBus** connects to **LM95235** and **LM87** blocks.\n\n**Peripheral Connections (Bottom Right):**\n* **PCI:** A dashed **PCI** block connects to the MCH and outputs via an arrow labeled **PCI 33 Mhz, v2.3** to the **CD** bar.\n* **LPC:** A dashed **LPC** block connects to the MCH and outputs via an arrow labeled **LPC** to three blocks: **BIOS**, **TPM**, and **LPC header**.](.express-dw400-50-1j011-1010-201/c57eb423cbbe9708268c63e9bb8bff64925622258fc141883ca71214fa5d42de.jpg) # 4 Mechanical Dimensions ![| Dimension | Value |\n| --------- | ----- |\n| Width | 125.00 |\n| Height | 4.00 |\n| Width | 2.80 |\n| Height | 80.00 |\n| Width | 34.00 |\n| Height | 16.5 |\n| Width | 4.00 |\n| Height | 0.00 |\n| Width | 4.00 |\n| Height | 6.00 |\n| Width | 18.00 |\n| Height | 51.00 |\n| Width | 66.00 |\n| Height | 91.00 |\n| Width | 125.00 |\n| Height | 121.00 |\n| Width | 4.00 |\n| Height | 95.00 |\n| Width | 91.00 |\n| Height | 95.00 |](.express-dw400-50-1j011-1010-201/f2f4b00e4dbe6d9326cde8bdd20663f43c7d02b6f466a576ca5fd7e9599d415b.jpg) All tolerances ± 0.05 mm Other tolerances ± 0.2 mm # 5 Watch Dog Timer (WDT) # 5.1 Overview The Intel® 3100 Chipset Watch Dog Timer (WDT) is a kernel mode driver designed to run on Microsoft® Windows® OS (XP, Server® 2003, Vista®, and XP Embedded) platforms. When enabled, the WDT can generate an interrupt or reboot the system in the event of a system lockup. This WDT supports a number of IOCTL commands. These commands enable the applications to access and control all the aspects of the WDT. The WDT is located on the LPC bus. As such, it is not detected by the Plug-n-Play (PnP) manager. To install the driver, the user must manually go through the “Add Device” wizard in the Control Panel. Installation details are covered later in this chapter. # 5.2 Installing the WDT Driver The WDT driver does not announce itself to the device manager. To install the WDT driver: ![The image displays a document icon featuring a white page with a folded top-right corner and faint horizontal gray lines representing text. A large, bold red checkmark is superimposed over the center of the page. Below the document graphic is the word 'NOTE' in black capital letters, followed by three small gray squares arranged vertically.](.express-dw400-50-1j011-1010-201/cb4bcf6d7d29c89d6fb80c7d19225a3e72537ca672bc4f4e8bda214e7e5ccbb9.jpg) These instructions assume that you are in the default Microsoft Windows® XP control panel view. 1. Open Control Panel and click “Printers and Other Hardware”. 2. In the “See Also” box at the top left hand corner, click “Add Hardware”. 3. Click “Next” to look for hardware. 4. Click “Yes, I have already connected the hardware” and then click “Next”. 5. Scroll to the bottom of the “Installed hardware” list and select “Add a new hardware device”. 6. Click “Install the hardware that I manually select from a list” and then Click “Next”. 7. Click “Show All Devices” and then Click “Next”. 8. Click “Have Disk…”, point to the location where the WDT driver is stored and click “OK”. 9. Click on “Intel® 3100 Chipset Watch Dog Timer” and install. # 5.3 Interface with the Driver The only supported driver communication method is through IOCTLs. The IOCTLs defined in this section allow a user-mode application to access all the capabilities of the WDT. # 5.3.1 Symbolic Link The driver creates a named device object that can be accessed through the symbolic link "\\\\.\\SAWD1”. As such, the application can communicate with the driver by obtaining a handle from CreateFile() with the path, “\\\\.\\SAWD1”. ```txt /* Example: Getting a handle to the WDT driver */ HANDLE handle_to_wdt; handle_to_wdt = CreateFile( "\\\\\\.\\SAWD1", GENERIC_WRITE, FILE_SHARE_WRITE, NULL, OPEN_EXISTING, 0, NULL); ``` Once a handle is obtained successfully, the application uses the DeviceIoControl() function to communicate with the driver. ```c /* Example: Sending an IOCTL to the driver. Here we assume * handle_to_wdt was obtained successfully */ BOOL status; int return_length; status = DeviceIoControl( handle_to_wdt, /* handle to wdt */ IOCTL_ENABLE_WDT, /* IOCTL to send */ NULL, /* no input buffer */ 0, /* input length = 0 */ NULL, /* no output buffer */ 0, /* output length = 0 */ &return_length,/* should be 0 */ NULL); /* wait until I/O completes */ ``` # 5.3.2 Supported IOCTLs IOCTL\_GET\_CAPABILITIES ```c #define IOCTL_GET_CAPABILITIES \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x802, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts a buffer of type PSAWD\_CAPABILITY\_OUT\_BUFF, and fills in the min and max field, indicating the minimum and maximum downcounter value. The Version field will be set to 1. ```c typedef struct _SAWD_CAPABILITY_OUT_BUFF { unsigned long Version; /* version of interface used */ unsigned long min; /* minimum value in msecs */ unsigned long max; /* maximum value in msecs */ } SAWD_CAPABILITY_OUT_BUFF, *PSAWD_CAPABILITY_OUT_BUFF; ``` IOCTL\_ENABLE\_WDT ```c #define IOCTL_ENABLE_WDT \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D00, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL enables the Watch Dog Timer. IOCTL\_DISABLE\_WDT ```c #define IOCTL_DISABLE_WDT \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D01, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL disables the Watch Dog Timer. IOCTL\_LOAD\_COUNTER ```c #define IOCTL_LOAD_COUNTER \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D02, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts a buffer of type PSAWD\_CTRL, and loads the preload counter 1 and 2 using the data in the Preload1 and Preload2 fields. ```c unsigned long ConfigReg; /* 16 bit Configuration register */ unsigned short DeviceStatus; /* store device status bits */ unsigned short ReloadReg; /* 16 bit reload register */ unsigned short LockReg; /* 8 bit Lock register */ unsigned long InterruptCount; /* # of times stage 1 INT occurred */ unsigned short IRQ; short BusType; unsigned short BusNumber; unsigned short IrqOffset; } SAWD_CTRL, *PSAWD_CTRL; ``` # IOCTL\_PING\_THE\_WDT ```c #define IOCTL_PING_THE_WDT \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D02, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL reloads the Watch Dog Timer’s down-counter with the preload value to prevent a timeout. If the WDT is in stage 1 of the countdown, then preload value 1 will be loaded into the main down counter. If the WDT is in stage 2 of the countdown, then preload value 2 will be loaded into the main down counter. # IOCTL\_SET\_PRESCALAR ```c #define IOCTL_SET_PRESCALAR \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D04, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL sets how the 20-bit preload value will be loaded into the 35-bit down counter. The IOCTL accepts an unsigned long integer set to 0 or 1 in the input buffer. If the input is 0, then the 20-bit preload value will be counted down at 1KHz. If the input is 1, then the 20-bit preload value will be counted down at 1MHz. # IOCTL\_READ\_DOWN\_COUNTER ```c #define IOCTL_READ_DOWN_COUNTER \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D05, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL returns the current value of the down counter (in an unsigned long integer). # IOCTL\_SET\_EXTERNAL\_OUT ```c #define IOCTL_SET_EXTERNAL_OUT \ ``` IOCTL\_LOCK\_DEVICE ```c #define IOCTL_LOCK_DEVICE \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D08, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL locks the WDT device. Once locked, the state (WDT mode vs. free running mode, and Enabled vs. Disabled) of the Watch Dog Timer cannot be changed until the system resets. IOCTL\_ROUTE\_INTERRUPT ```c #define IOCTL_ROUTE_INTERRUPT \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D09, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts an unsigned long integer, sets to 0-3, and uses it to set the type of interrupt to trigger when stage 1 timer expires. 0 sets interrupt type to PCI 1 sets interrupt type to NMI 2 sets interrupt type to SMI 3 disables stage 1 interrupt IOCTL\_USER\_HANDLE ```c #define IOCTL_USER_HANDLE \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D0D, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts a buffer of type PSAWD\_CTRL, and creates an internal reference to the function specified by the UserEvent field. When a stage 2 timeout occurs, the driver will call this function. IOCTL\_TEST\_CALLBACK ```c #define IOCTL_TEST_CALLBACK \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D0F, \ METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL is used for testing the event handling code and to verify that the application thread is released when the shared UserEvent is signaled by the WDT driver. This IOCTL exists mainly for application developers to debug their application. IOCTL\_GET\_STATUS ```c #define IOCTL_SET_MODE \ CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D15, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts an unsigned long integer, sets to 0 or 1, and uses it to set the WDT mode. If the input is 0, then the WDT is set to Watch Dog Timer mode. If the input is 1, then the WDT is set to free running mode. IOCTL\_GET\_TIMEOUT\_STATUS ```c #define IOCTL_GET_TIMEOUT_STATUS CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D16, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts an unsigned long integer and uses it as both input and output. As an input parameter, if the integer is set to 1, then the time out bit on the WDT device will be reset. As an output parameter, the integer is set to 1 if both stage 1 and stage 2 timers have expired. IOCTL\_GET\_STAGE\_1\_TIMEOUT\_STATUS ```c #define IOCTL_GET_STAGE_1_TIMEOUT_STATUS CTL_CODE( FILE_DEVICE_UNKNOWN, 0x0D17, METHOD_BUFFERED, FILE_ANY_ACCESS ) ``` This IOCTL accepts an unsigned long integer and uses it as both input and output. As an input parameter, if the integer is set to 1, then the time out bit on the WDT device will be reset. As an output parameter, the integer is set to 1 if the stage 1 timer has expired. # 5.4 Watch Dog Timer Windows® XP Demo Utility This specification describes the WDT demo utility “Wdtdemo.exe”. The demo tool is a MFC based dialog application that is used to control and monitor the WDT device in the Microsoft\* Windows\* OS environment. Wdtdemo.exe is to be used only for demonstration of the WDT’s functionality and should not be used as a customer solution. ```txt MFC UTILITY APPLICATION Wdtdemo.exe iwdtlib.dll ``` ```sql KERNEL MODE DRIVER wdtdrvr.sys ``` # 5.5 Using the Demo Application The Wdtdemo.exe application has a number of buttons and text entry fields for configuring and controlling the Watch Dog Timer (WDT). Each of the following items has a corresponding button or entry field on the application screen. f Setting the mode [Mode] fLocking the WDT device [LOCK] fConfiguring the WDT device [Configure] f Testing the user mode call function [Test Callback] fRetrieving the driver and dynamic link version number [Lib Version] fDownloading the Stage 1 and Stage 2 time-out values [Preload Counters] fInformation about WDT [WDT Status] fSetting the refresh rate [WDT Reload Rate] fStarting and Stopping the refresh of the WDT [Enable] [Disable] fSynchronizing the start of reload [Synch Start of Reload] fStarting and Stopping the reload counter [Reload Counter] ![Watchdog Timer Demo Application\nMode\nWatchdog\nFree Running\nPreload Counters\nCount 1 Max Count 2 Max\nDownload to WDT\nLock\nConfigure\nTest Callback\nAbout\nWDT Status\nWDT_LOCK BIT 0\nWDT_ENABLE BIT 0\nWDT_TOUT_CNF BIT 0\nWDT_INTR_ACT BIT 0\nWDT_TIMEOUT BIT 0 CLR\nStage 1 Timeouts 0\nIRQ Count 0\nWDT Reload Rate\n1 x 1000 ms\nExit WDT Control Cancel\nIntel Corporation Copyright 2006\nStage 1 Stage 2\n0 0\nEnable Disable\nSync Start of Reload\nReload Counter\n0\nStart Stop\nForce Reload Now](.express-dw400-50-1j011-1010-201/322c87594435d48963375a88d101fdb65f6e5d9a3835aa21e88be410c6c43449.jpg) # 5.5.1 Setting the Mode The mode can be set to either Watch Dog Mode or Free Running Mode using the radio select button at the upper left of the dialog. ![Mode\n● Watchdog\n○ Free Running](.express-dw400-50-1j011-1010-201/dfa5e2a6a5cf38f6fa2e45e19a15dd605740b7dc7792fb9cfa0afb34c3d3f51d.jpg) # 5.5.2 Locking the WDT Device The WDT can be locked by software. The LOCK button locks the WDT so that no further changes to the configuration registers are possible until a system reset. A locked WDT cannot be enabled or disabled. # 5.5.3 Configuring the WDT Click the configure button to program the following three configuration options: Output Enable, Set Prescalar and Interrupt Routing. ![Set Configuration Register\nOutput Enable\nEnabled Disabled\nSet Prescalar\n34 : 15 24 : 5\nInterrupt Routing\nSERIRQ\nNMI\nSMI\nDisabled\nOK Cancel](.express-dw400-50-1j011-1010-201/6ebd6872aa959f3a910a65af0c790d845003999f47ee10e20df6a21072d6fac0.jpg) [Output Enable] Enables or disables the toggling of the external output pin if the WDT times out. [Set Prescalar] Specifies a prescalar value for the 35-bit, count-down counter. The default value is 34:15. See the WDT Driver Specification for details on pre-scalar. [Interrupt Routing] Select one of the three interrupt methods (SERIRQ, NMI, or SMI) or “Disabled” to disable interrupt. When SERIRQ is selected, the System BIOS designated interrupt is retrieved from the WDT. # 5.5.4 Testing the User Mode Call Function This button verifies that the interrupt handler and callback mechanism are working correctly. Clicking the Test Callback button increments the Stage 1 interrupt count. # 5.5.5 Retrieving the Driver and Dynamic Link Version Number Click the Lib Version button to retrieve the driver and dynamic link version number. # 5.5.6 Downloading the Stage 1 and Stage 2 Time-out Values There are two edit boxes that specify Stage 1 and Stage 2 count-down values. Enter the values and then click the Download to WDT button to program the values from the application to the WDT device. Both counters are 35-bit counters that decrement using a 20-bit prescalar. # 5.5.7 Information about WDT This area shows status of the WDT. # 5.5.8 Setting the Reload Rate The reload rate is set by using the button control that is in the lower center of the application. The rate can be adjusted from between 0 and 100 seconds. ![WDT Reload Rate\n1 x 1000 ms](.express-dw400-50-1j011-1010-201/30b7d18106c645546436da3e051b953ddf4bc03ead56caf5be116585f9ce3d5a.jpg) # 5.5.9 Starting and Stopping the Refresh of the WDT Clicking the Enable button starts the WDT counting down. Click the Disable button to stop the WDT from counting down. ![Stage 1\n0\n0\nStage 2\nEnable\nDisable](.express-dw400-50-1j011-1010-201/8a3e348e4223bb8e339907c6f4127c0e229a44b4950da98add9bb71ee5d866b3.jpg) # 5.5.10 Starting and Stopping the reload counter Click the Start button to begin refreshing the WDT. Click the Stop button to stop refreshing the WDT. You can force an immediate refresh of the WDT by clicking the Force Reload Now button. To prevent Stage 1 or Stage 2 timeouts you must start “refresh” and have a refresh rate that ensures that the timer is refreshed before the first stage and or second stage time out. ![Reload Counter\n0\nStart Stop\nForce Reload Now](.express-dw400-50-1j011-1010-201/2d13ad247564c9daac0af6481caa2c064c2866e3f6f98d5c8411dff21f2b054a.jpg) # 6 Connectors # 6.1 COM Express® Type 2 All pin-outs on AB and CD connector of the Express-IW400 comply with pin-out and signal descriptions used in the original “PICMG® COM.0 R1.0: COM Express Module Base Specification”. This document contains a description of pin-outs, signal descriptions, and mechanical characteristics of the COM Express® (Expresss®) formfactor. An additional document, “ Express® Design Guide” gives a general introduction to carrier board designs for COM Express® (Express®) modules. # AB Connector 1 Gigabit Ethernet port LPC interface 4 Serial ATA channels High Definition Audio 8 USB 2.0 ports 3 PCI Express Lanes x1 Dual 24-bit LVDS channels Analog VGA TV-out ports (SDTV/HDTV) 8 GPIO pins +12V primary power input +5V standby and 3V RTC ![125mm.\n95mm\nAB\nCD](.express-dw400-50-1j011-1010-201/b0beb248e7e92910dfb3894cb87cd0b29897505c2113ad5479e9f5e35e43a503.jpg) # CD Connector Parallel ATA, IDE port alternate definition assigns this to 2 additional Gigabit Ethernet ports 32-bit PCI v2.3 bus alternate definition assigns this to 10 additional PCI Express x1 lanes PCI Express x16 for Graphics these pins can also be assigned to two SDVO extensions (multiplexed) SMB and I2 C bus Power / Thermal control +12V primary power input ![COM\nExpress](.express-dw400-50-1j011-1010-201/67b26f296f9fba97233a1a6177cd12d123fb51d1648c0f282fb982142d5030db.jpg) # 6.2 COM Express® Board to Board Connectors Signals and Pin-out for: Basic formfactor, Type 2 ![D1\nC1\nD110\nC110](.express-dw400-50-1j011-1010-201/dc25b1a513d30557d4866e871f74fdb0e96b50b50e5779f84998c5dd1b353281.jpg) C D ![B1\nA1\nB110\nA10](.express-dw400-50-1j011-1010-201/3c66134bee02afa5a65b207128c0ca0379f7ab274d16f39fb82f7928bd7c6cde.jpg) A B ![The image displays three sets of concentric circles arranged horizontally from left to right against a white background. Each set consists of multiple rings. The circles are drawn with dashed lines. The set on the far left is the smallest, the middle set is of medium size, and the set on the far right is the largest. All the lines are thin and appear to be light grey or black.](.express-dw400-50-1j011-1010-201/9871acff8b675773c1ff8ec5cef0ef775675ee086c75e69bb0eb6e7884546ecf.jpg) ![The image features a white background displaying two distinct sets of concentric circles arranged horizontally. On the left and right sides, there are identical groups, each consisting of five concentric rings. The rings are composed of light gray dashed lines rather than solid strokes.](.express-dw400-50-1j011-1010-201/37dc3b0576cf77222dbcb5ded2aae53e1b30165dbdf5c1860b7b968bf428697b.jpg) Row A
Pin No.Pin NamePin No.Pin Name
A1GND (FIXED)B1GND (FIXED)
A2GBE0_MDI3-B2GBE0_ACT#
A3GBE0_MDI3+B3LPC_FRAME#
A4GBE0_LINK100#B4LPC_AD0
A5GBE0_LINK1000#B5LPC_AD1
A6GBE0_MDI2-B6LPC_AD2
A7GBE0_MDI2+B7LPC_AD3
A8NCB8LPC_DRQ1#
A9GBE0_MDI1-B9LPC_DRQ1#
A10GBE0_MDI1+B10LPC_CLK
A11GND (FIXED)B11GND (FIXED)
A12GBE0_MDI0-B12PWRBTN#
A13GBE0_MDI0+B13SMB_CK
A14GBE0_CTREFB14SMB_DAT
A15SUS_S3#B15SMB_ALERT#
A16SATA0_TX+B16SATA1_TX+
A17SATA0_TX-B17SATA1_TX-
A18SUS_S4#B18SUS_STAT#
A19SATA0_RX+B19SATA1_RX+
A20SATA0_RX-B20SATA1_RX-
A21GND (FIXED)B21GND (FIXED)
A22SATA2_TX+B22SATA3_TX+
A23SATA2_TX-B23SATA3_TX-
A24SUS_S5#B24PWR_OK
A25SATA2_RX+B25SATA3_RX+
A26SATA2_RX-B26SATA3_RX-
A27BATLOW#B27WDT
A28ATA_ACT#B28NC
A29NCB29NC
A30NCB30NC
A31GND (FIXED)B31GND (FIXED)
A32NCB32SPKR
A33NCB33I2C_CK
A34BIOS_DISABLE#B34I2C_DAT
A35THRMTRIP#B35THRM#
A36NCB36NC
A37NCB37NC
A38NCB38USB_4_5_OC#
A39USB4- ClientB39NC
A40USB4+ ClientB40NC
A41GND (FIXED)B41GND (FIXED)
A42USB2-B42USB3-
A43USB2+B43USB3+
A44USB_2_3_OC#B44USB_0_1_OC#
A45USB0-B45USB1-
A46USB0+B46USB1+
A47VCC_RTCB47EXCD1_PERST#
A48EXCD0_PERST#B48EXCD1_CPPE#
A49EXCD0_CPPE#B49SYS_RESET#
A50LPC_SERIRQB50CB_RESET#
Row B Row C Row D
Pin No.Pin NamePin No.Pin Name
C1GND FIXED)D1GND FIXED)
C2IDE_D7D2IDE_D5
C3IDE_D6D3IDE_D10
C4IDE_D3D4IDE_D11
C5IDE_D15D5IDE_D12
C6IDE_D8D6IDE_D4
C7IDE_D9D7IDE_D0
C8IDE_D2D8IDE_REQ
C9IDE_D13D9IDE_IOW#
C10IDE_D1D10IDE_ACK#
C11GND (FIXED)D11GND (FIXED)
C12IDE_D14D12IDE_IRQ
C13IDE_IORDYD13IDE_A0
C14IDE_IOR#D14IDE_A1
C15PCI_PME#D15IDE_A2
C16PCI_GNT2#D16IDE_CS1#
C17PCI_REQ2#D17IDE_CS3#
C18PCI_GNT1#D18IDE_RESET#
C19PCI_REQ1#D19PCI_REQ3#
C20PCI_GNT0#D20PCI_GNT3#
C21GND (FIXED)D21GND (FIXED)
C22PCI_REQ0#D22PCI_AD1
C23PCI_RESET#D23PCI_AD3
C24PCI_AD0D24PCI_AD5
C25PCI_AD2D25PCI_AD7
C26PCI_AD4D26PCI_C/BE0#
C27PCI_AD6D27PCI_AD9
C28PCI_AD8D28PCI_AD11
C29PCI_AD10D29PCI_AD13
C30PCI_AD12D30PCI_AD15
C31GND (FIXED)D31GND (FIXED)
C32PCI_AD14D32PCI_PAR
C33PCI_C/BE1#D33PCI_SERR#
C34PCI_PERR#D34PCI_STOP#
C35PCI_LOCK#D35PCI_TRDY#
C36PCI_DEVSEL#D36PCI_FRAME#
C37PCIIRDY#D37PCI_AD16
C38PCI_C/BE2#D38PCI_AD18
C39PCI_AD17D39PCI_AD20
C40PCI_AD19D40PCI_AD22
C41GND (FIXED)D41GND (FIXED)
C42PCI_AD21D42PCI_AD24
C43PCI_AD23D43PCI_AD26
C44PCI_C/BE3#D44PCI_AD28
C45PCI_AD25D45PCI_AD30
C46PCI_AD27D46PCI_IRQC#
C47PCI_AD29D47PCI_IRQD#
C48PCI_AD31D48PCI_CLKRUN#
C49PCI_IRQA#D49PCI_M66EN
C50PCI_IRQB#D50PCI_CLK
Row ARow B
Pin No.Pin NamePin No.Pin Name
A51GND (FIXED)B51GND (FIXED)
A52NCB52NC
A53NCB53NC
A54GPIOB54GPO1
A55NCB55NC
A56NCB56NC
A57GNDB57GPO2
A58NCB58NC
A59NCB59NC
A60GND (FIXED)B60GND (FIXED)
A61PCIE_TX2+B61PCIE_RX2+
A62PCIE_TX2-B62PCIE_RX2-
A63GPI1B63GPO3
A64PCIE_TX1+B64PCIE_RX1+
A65PCIE_TX1-B65PCIE_RX1-
A66GNDB66WAKE0#
A67GPI2B67WAKE1#
A68PCIE_TX0+B68PCIE_RX0+
A69PCIE_TX0-B69PCIE_RX0-
A70GND (FIXED)B70GND (FIXED)
A71NCB71NC
A72NCB72NC
A73NCB73NC
A74NCB74NC
A75NCB75NC
A76NCB76NC
A77NCB77NC
A78NCB78NC
A79NCB79NC
A80GND (FIXED)B80GND (FIXED)
A81NCB81NC
A82NCB82NC
A83NCB83NC
A84NCB84VCC_5V_SBY
A85GPI3B85VCC_5V_SBY
A86KBD_RST#B86VCC_5V_SBY
A87KBD_A20GATEB87VCC_5V_SBY
A88PCIE0_CK_REF+B88RSVD
A89PCIE0_CK_REF-B89NC
A90GND (FIXED)B90GND (FIXED)
A91RSVDB91NC
A92RSVDB92NC
A93GPO0B93NC
A94RSVDB94NC
A95RSVDB95NC
A96GNDB96NC
A97VCC_12VB97NC
A98VCC_12VB98NC
A99VCC_12VB99NC
A100GND (FIXED)B100GND (FIXED)
A101VCC_12VB101VCC_12V
A102VCC_12VB102VCC_12V
A103VCC_12VB103VCC_12V
A104VCC_12VB104VCC_12V
A105VCC_12VB105VCC_12V
A106VCC_12VB106VCC_12V
A107VCC_12VB107VCC_12V
A108VCC_12VB108VCC_12V
A109VCC_12VB109VCC_12V
A110GND (FIXED)B110GND (FIXED)
Row CRow D
Pin No.Pin NamePin No.Pin Name
C51GND (FIXED)D51GND (FIXED)
C52PEG_RX0+D52PEG_TX0+
C53PEG_RX0-D53PEG_TX0-
C54NCD54NC
C55PEG_RX1+D55PEG_TX1+
C56PEG_RX1-D56PEG_TX1-
C57NCD57NC
C58PEG_RX2+D58PEG_TX2+
C59PEG_RX2-D59PEG_TX2-
C60GND (FIXED)D60GND (FIXED)
C61PEG_RX3+D61PEG_TX3+
C62PEG_RX3-D62PEG_TX3-
C63RSVDD63RSVD
C64RSVDD64RSVD
C65PEG_RX4+D65PEG_TX4+
C66PEG_RX4-D66PEG_TX4-
C67RSVDD67GND
C68PEG_RX5+D68PEG_TX5+
C69PEG_RX5-D69PEG_TX5-
C70GND (FIXED)D70GND (FIXED)
C71PEG_RX6+D71PEG_TX6+
C72PEG_RX6-D72PEG_TX6-
C73NCD73NC
C74PEG_RX7+D74PEG_TX7+
C75PEG_RX7-D75PEG_TX7-
C76GNDD76GND
C77RSVDD77IDE_CBLID#
C78NCD78NC
C79NCD79NC
C80GND (FIXED)D80GND (FIXED)
C81NCD81NC
C82NCD82NC
C83RSVDD83RSVD
C84GNDD84GND
C85NCD85NC
C86NCD86NC
C87GNDD87GND
C88NCD88NC
C89NCD89NC
C90GND (FIXED)D90GND (FIXED)
C91NCD91NC
C92NCD92NC
C93GNDD93GND
C94NCD94NC
C95NCD95NC
C96GNDD96GND
C97RSVDD97NC
C98NCD98NC
C99NCD99NC
C100GND (FIXED)D100GND (FIXED)
C101NCD101NC
C102NCD102NC
C103GNDD103GND
C104VCC_12VD104VCC_12V
C105VCC_12VD105VCC_12V
C106VCC_12VD106VCC_12V
C107VCC_12VD107VCC_12V
C108VCC_12VD108VCC_12V
C109VCC_12VD109VCC_12V
C110GND (FIXED)D110GND (FIXED)
6.3 Signal Descriptions Row A
PinSignalDescriptionTypePU/PDComment
A1GNDGroundPWR--
A2GBE0_MDI3-Ethernet Receive Data -I/O - DP--
A3GBE0_MDI3+Ethernet Receive Data +I/O - DP--
A4GBE0_LINK100#Ethernet Speed LED (100Mb)O-3,3-On at 100Mb/s
A5GBE0_LINK1000#Ethernet Speed LED (1000Mb)O-3,3-On at 1000Mb/s
A6GBE0_MDI2-Ethernet Receive Data -I/O - DP--
A7GBE0_MDI2+Ethernet Receive Data +I/O - DP--
A8GBE0_LINK#LAN Link LEDNC--
A9GBE0_MDI1-Ethernet Receive Data -I/O - DP--
A10GBE0_MDI1+Ethernet Receive Data +I/O - DP--
A11GNDGroundPWR--
A12GBE0_MDI0-Ethernet Receive Data -I/O - DP--
A13GBE0_MDI0+Ethernet Receive Data +I/O - DP--
A14GBE0_CTREFETHCTREFO-2,5--
A15SUS_S3#PM_SLP_S#3O-3,3--
A16SATA0_TX+SATA0_TX+ | SATA 0 Transmit Data +O - DP--
A17SATA0_TX-SATA0_TX- | SATA 0 Transmit Data -O - DP--
A18SUS_S4#PM_SLP_S#4O-3,3--
A19SATA0_RX+SATA0_RX+ | SATA 0 Receive Data +I - DP--
A20SATA0_RX-SATA0_RX - | SATA 0 Receive Data -I - DP--
A21GNDGroundPWR--
A22SATA2_TX+SATA0_TX+ | SATA 2 Transmit Data +O - DP--
A23SATA2_TX-SATA0_TX- | SATA 2 Transmit Data -O - DP--
A24SUS_S5#PM_SLP_S#5O-3,3--
A25SATA2_RX+SATA0_RX+ | SATA 2 Receive Data +I - DP--
A26SATA2_RX-SATA0_RX- | SATA 2 Receive Data -I - DP--
A27BATLOW#PM_BATLOW# | Battery LowI-3,3PU 8k2 3,3VSB-
A28ATA_ACT#ATA_LED# | SATA LEDO-3,3PU 1k 3,3V-
A29AC_SYNCAC_SYNC | AC'97 SyncNC--
A30AC_RST#AC_RST# | AC'97 ResetNC--
A31GNDGroundPWR--
A32AC_BITCLKAC_BITCLK | AC'97 ClockNC--
A33AC_SDOUTAC_SDATAOUT | AC'97 DataNC--
A34BIOS_DISABLE#BIOS_DISABLE#I-3,3PU 4k7 3,3V-
A35THRMTRIP#PM_THRMTRIP#_CONO-3,3PU 330 3,3V-
A36USB6-USB_PN6 | USB Data - Port6NC--
A37USB6+USB_PP6 | USB Data + Port6NC--
A38USB_6_7_OC#USB_OC#_6_7 | USB OverCurrent Port 6/7NC-
A39USB4-USB_PN4 | USB Data - Port4I/O - DP--
A40USB4+USB_PP4 | USB Data + Port4I/O - DP--
A41GNDGroundPWR--
A42USB2-USB_PN2 | USB Data - Port2I/O - DP-
A43USB2+USB_PP2 | USB Data + Port2I/O - DP--
A44USB_2_3_OC#USB_OC#_2_3 | USB OverCurrent Port 2/3I-3,3PU 10k 3,3VSB-
A45USB0-USB_PN0 | USB Data - Port0I/O - DP--
A46USB0+USB_PP0 | USB Data + Port0I/O - DP--
A47VCC_RTCV_BATPWR--
A48EXCD0_PERST#Express Card Support [0] | card resetO-3,3PU 10k 3,3VSB-
A49EXCD0_CPPE#Express Card Support [0] | capable c. requestI-3,3PU 8.2k 3,3V-
A50LPC_SERIRQINT_SERIRQ | Serial Interrupt RequestIO-3,3--
A51GNDGroundPWR--
A52PCIE5_TX+PCI Express lane 5 +NC--
A53PCIE5_TX-PCI Express lane 5 -NC--
A54GPIOGeneral Purpose Input 0I-3,3PU 8k2 3,3V-
A55PCIE4_TX+PCI Express lane 4 +NC--
A56PCIE4_TX-PCI Express lane 4 -NC--
A57GNDGroundPWR--
A58PCIE3_TX+PCI Express lane 3 + (used by LAN)NC--
A59PCIE3_TX-PCI Express lane 3 - (used by LAN)NC--
A60GNDGroundPWR--
A61PCIE2_TX+PCI Express lane 2 +O - DP--
A62PCIE2_TX-PCI Express lane 2 -O - DP--
A63GPI1General Purpose Input 1I-3,3PU 8k2 3,3V-
A64PCIE1_TX+PCI Express lane 1 +O - DP--
A65PCIE1_TX-PCI Express lane 1 -O - DP--
A66GNDGroundPWR--
A67GPI2General Purpose Input 2I-3,3PU 8k2 3,3V-
A68PCIE0_TX+PCI Express lane 0 +O - DP--
A69PCIE0_TX-PCI Express lane 0 -O - DP--
A70GNDGroundPWR--
A71LVDS_A0+LVDS_AP0 | LVDS Channel ANC--
A72LVDS_A0-LVDS_AN0 | LVDS Channel ANC--
A73LVDS_A1+LVDS_AP1 | LVDS Channel ANC--
A74LVDS_A1-LVDS_AN1 | LVDS Channel ANC--
A75LVDS_A2+LVDS_AP2 | LVDS Channel ANC--
A76LVDS_A2-LVDS_AN2 | LVDS Channel ANC--
A77LVDS_VDD_ENLVDS_VDDEN | LVDS Panel PowerNC--
A78LVDS_A3+LVDS_AP3 | LVDS Channel ANC--
A79LVDS_A3-LVDS_AN3 | LVDS Channel ANC--
A80GNDGroundPWR--
A81LVDS_A_CK+LVDS_CLKAP | LVDS Channel ANC--
A82LVDS_A_CK-LVDS_CLKAN | LVDS Channel ANC--
A83LVDS_I2C_CKLVDS_DDCPCLK | JILI I2C ClockNC--
A84LVDS_I2C_DATLVDS_DDCPDATA | JILI I2C DataNC--
A85GPI3General Purpose Input 3I-3,3PU 8k2 3,3V-
A86KBD_RST#H_RCIN# | Keyboard ResetI-3,3--
A87KBD_A20GATEH_A20GATEI-3,3--
A88PCIE_CK_REF+CLK_PCIE_REF PO - DP--
A89PCIE_CK_REF-CLK_PCIE_REF NO - DP--
A90GNDGroundPWR--
A91RSVD-NC--
A92RSVD-NC--
A93GPO0General Purpose Output 0O-3,3--
A94RSVD-NC--
A95RSVD-NC--
A96GNDGroundPWR--
A97VCC_12VPower 12VPWR--
A98VCC_12VPower 12VPWR--
A99VCC_12VPower 12VPWR--
A100GNDGroundPWR--
A101VCC_12VPower 12VPWR--
A102VCC_12VPower 12VPWR--
A103VCC_12VPower 12VPWR--
A104VCC_12VPower 12VPWR--
A105VCC_12VPower 12VPWR--
A106VCC_12VPower 12VPWR--
A107VCC_12VPower 12VPWR--
A108VCC_12VPower 12VPWR--
A109VCC_12VPower 12VPWR--
A110GNDGroundPWR--
B1GNDGroundPWR--
B2GBE0_ACT#LAN_ACTLED# | Ethernet Activity LEDO-3,3--
B3LPC_FRAME#LPC_FRAME# | LPC Frame IndicatorO-3,3--
B4LPC_AD0LPC_AD0 | LPC Adress & DATA BusIO-3,3--
B5LPC_AD1LPC_AD1 | LPC Adress & DATA BusIO-3,3--
B6LPC_AD2LPC_AD2 | LPC Adress & DATA BusIO-3,3--
B7LPC_AD3LPC_AD3 | LPC Adress & DATA BusIO-3,3--
B8LPC_DRQ0#SIO_DRQ#0 | LPC Request 0I-3,3--
B9LPC_DRQ1#SIO_DRQ#1 | LPC Request 1I-3,3PU 8k2 3,3V-
B10LPC_CLKCLK_SIOEXTPCIO-3,3--
B11GNDGroundI-3,3--
B12PWRBTN#Power ButtonI-3,3PU 10k 3,3VSB-
B13SMB_CKSMBUS ClockO-3,3PU 1k2 3,3V-
B14SMB_DATSMBUS DataIO-3,3PU 1k2 3,3V-
B15SMB_ALERT#SMB_ALERT#I-3,3PU 8k2 3,3VSB-
B16SATA1_TX+SATA1_TX+O - DP--
B17SATA1_TX-SATA1_TX-O - DP--
B18SUS_STAT#PM_SUS_STAT#O-3,3--
B19SATA1_RX+SATA1_RX+I - DP--
B20SATA1_RX-SATA1_RX-I - DP--
B21GNDGroundPWR--
B22SATA3_TX+SATA3_TX+O - DP--
B23SATA3_TX-SATA3_TX-O - DP--
B24PWR_OKPower OKI-3,3PU 10k 3,3VSB-
B25SATA3_RX+SATA3_RX+I - DP--
B26SATA3_RX-SATA3_RX-I - DP--
B27WDTWatch Dog TimerO-3,3PU 4k7 3,3V-
B28AC_SDIN2AC_SDATAIN2NC--
B29AC_SDIN1AC_SDATAIN1NC--
B30AC_SDIN0AC_SDATAIN0NC--
B31GNDGroundPWR--
B32SPKRAC_SPKRO-3,3--
B33I2C_CKI2CLKO-3,3PU 1k2 3,3V-
B34I2C_DATI2DATIO-3,3PU 1k2 3,3V-
B35THRM#PM THRM# CON | Over TemperatureI-3,3PU 1k 1,05V-
B36USB7-USB_PN7 | USB Data - Port7NC--
B37USB7+USB_PP7 | USB Data + Port7NC--
B38USB_4_5_OC#USB_OC#_4_5 | USB OverCurrent PortI-3,3PU 100k 3,3VSB-
B39USB5-USB_PN5 | USB Data- Port5NC--
B40USB5+USB_PP5 | USB Data+ Port5NC--
B41GNDGroundPWR--
B42USB3-USB_PN3 | USB Data- Port3I/O - DP--
B43USB3+USB_PP3 | USB Data+ Port3I/O - DP--
B44USB_0_1_OC#USB_OC#_0_1 | USB OverCurrent PortI-3,3PU 10k 3,3VSB-
B45USB1-USB_PN1 | USB Data- Port1I/O - DP--
B46USB1+USB_PP1 | USB Data+ Port1I/O - DP--
B47EXCD1_PERST#Express Card Support [1] | card resetO-3,3PU 10k 3,3VSB-
B48EXCD1_CPPE#Express Card Support [1] | capable c.I-3,3PU 8k2 3,3V-
B49SYS_RESET#ETX_SYS_RESET# | Reset InputI-3,3PU 10k 3,3VSB-
B50CB_RESET#PCI_RST# | PCI Bus ResetO-3,3--
B51GNDGroundPWR--
B52PCIE5_RX+BOM option (LAN on PCIe 5)NC--
B53PCIE5_RX-BOM option (LAN on PCIe 5)NC--
B54GPO1General Purpose Output 1O-3,3--
B55PCIE4_RX+PCI Express lane 4 + RecieveNC--
B56PCIE4_RX-PCI Express lane 4 - RecieveNC--
B57GPO2General Purpose Output 2O-3,3--
B58PCIE3_RX+PCI Express lane 3 + RecieveNC--
B59PCIE3_RX-PCI Express lane 3 - RecieveNC--
B60GNDGroundPWR--
B61PCIE2_RX+PCI Express lane 2 + RecieveI - DP--
B62PCIE2_RX-PCI Express lane 2 - RecieveI - DP--
B63GPO3General Purpose Output 3O-3,3--
B64PCIE1_RX+PCI Express lane 1 + RecieveI - DP--
B65PCIE1_RX-PCI Express lane 1 - RecieveI - DP--
B66WAKE0#PCIE_WAKEI#I-3,3PU 1k 3,3VSB-
B67WAKE1#WAKE1#I-3,3PU 8k2 3,3VSB-
B68PCIE0_RX+PCI Express lane 0 + RecieveI - DP--
B69PCIE0_RX-PCI Express lane 0 - RecieveI - DP--
B70GNDGroundPWR--
B71LVDS_B0+LVDS_BP0 | LVDS Channel B Data0+NC--
B72LVDS_B0-LVDS_BNO | LVDS Channel B Data0-NC--
B73LVDS_B1+LVDS_BP1 | LVDS Channel B Data1+NC--
B74LVDS_B1-LVDS_BN1 | LVDS Channel B Data1-NC--
B75LVDS_B2+LVDS_BP2 | LVDS Channel B Data2+NC--
B76LVDS_B2-LVDS_BN2 | LVDS Channel B Data2-NC--
B77LVDS_B3+LVDS_BP3 | LVDS Channel B Data3+NC--
B78LVDS_B3-LVDS_BN3 | LVDS Channel B Data3-NC--
B79LVDS_BKLT_ENPanel Backlight ONNC--
B80GNDGroundPWR--
B81LVDS_B_CK+LVDS_CLKBP | LVDS Channel BNC--
B82LVDS_B_CK-LVDS_CLKBM | LVDS Channel BNC--
B83LVDS_BKLT_CTRLBacklight BrightnessNC--
B84VCC_5V_SBY5V StandbyPWR--
B85VCC_5V_SBY5V StandbyPWR--
B86VCC_5V_SBY5V StandbyPWR--
B87VCC_5V_SBY5V StandbyPWR--
B88RSVD-NC--
B89VGA_REDAnalog Video RGB-REDNC--
B90GNDGroundPWR--
B91VGA_GRNAnalog Video RGB-GREENNC--
B92VGA_BLUAnalog Video RGB-BLUENC--
B93VGA_HSYNCAnalog Video H-SyncNC--
B94VGA_VSYNCAnalog Video V-SyncNC--
B95VGA_I2C_CKDisplay Data ChannelNC--
B96VGA_I2C_DATDisplay DataNC--
B97TV_DAC_AComposite CVBSNC--
B98TV_DAC_BTV Luminance SignalNC--
B99TV_DAC_CTV Chrominance SignalNC--
B100GNDGroundPWR--
B101VCC_12VPower 12VPWR--
B102VCC_12VPower 12VPWR--
B103VCC_12VPower 12VPWR--
B104VCC_12VPower 12VPWR--
B105VCC_12VPower 12VPWR--
B106VCC_12VPower 12VPWR--
B107VCC_12VPower 12VPWR--
B108VCC_12VPower 12VPWR--
B109VCC_12VPower 12VPWR--
B110GNDGroundPWR--
C1GNDGroundPWR--
C2IDE_D7IDE Data BusIOPD 10K-
C3IDE_D6IDE Data BusIO--
C4IDE_D3IDE Data BusIO--
C5IDE_D15IDE Data BusIO--
C6IDE_D8IDE Data BusIO--
C7IDE_D9IDE Data BusIO--
C8IDE_D2IDE Data BusIO--
C9IDE_D13IDE Data BusIO--
C10IDE_D1IDE Data BusIO--
C11GNDGroundPWR--
C12IDE_D14IDE Data BusIO--
C13IDE_IORDYIDE ReadyI-3,3PU 4K7 3,3V-
C14IDE_IOR#IDE IO ReadO-3,3--
C15PCI_PME#PCI Power Management EventIO-3,3--
C16PCI_GNT2#PCI Bus Grant 2O-3,3--
C17PCI_REQ2#PCI Bus Request 2I-3,3--
C18PCI_GNT1#PCI Bus Grant 1O-3,3--
C19PCI_REQ1#PCI Bus Request 1I-3,3--
C20PCI_GNT0#PCI Bus Grant 0O-3,3--
C21GNDGroundPWR--
C22PCI_REQ0#PCI Bus Request 0I-3,3--
C23PCI_RESET#PCI Bus ResetO-3,3--
C24PCI_AD0PCI Adress & Data Bus lineIO-3,3--
C25PCI_AD2PCI Adress & Data Bus lineIO-3,3--
C26PCI_AD4PCI Adress & Data Bus lineIO-3,3--
C27PCI_AD6PCI Adress & Data Bus lineIO-3,3--
C28PCI_AD8PCI Adress & Data Bus lineIO-3,3--
C29PCI_AD10PCI Adress & Data Bus lineIO-3,3--
C30PCI_AD12PCI Adress & Data Bus lineIO-3,3--
C31GNDGroundPWR--
C32PCI_AD14PCI Adress & Data Bus lineIO-3,3--
C33PCI_C/BE1#PCI Bus Command and Byte enablesIO-3,3--
C34PCI_PERR#PCI Bus Grant ErrorIO-3,3PU 2K7 3,3V-
C35PCI_LOCK#PCI Bus LockIO-3,3PU 2K7 3,3V-
C36PCI_DEVSEL#PCI Bus Device SelectIO-3,3PU 2K7 3,3V-
C37PCI_IRDY#PCI Bus Bus Initiator ReadyIO-3,3PU 2K7 3,3V-
C38PCI_C/BE2#PCI Bus Command and Byte enablesIO-3,3--
C39PCI_AD17PCI Adress & Data Bus lineIO-3,3--
C40PCI_AD19PCI Adress & Data Bus lineIO-3,3--
C41GNDGroundPWR--
C42PCI_AD21PCI Adress & Data Bus lineIO-3,3--
C43PCI_AD23PCI Adress & Data Bus lineIO-3,3--
C44PCI_C/BE3#PCI Bus Command and Byte enablesIO-3,3--
C45PCI_AD25PCI Adress & Data Bus lineIO-3,3--
C46PCI_AD27PCI Adress & Data Bus lineIO-3,3--
C47PCI_AD29PCI Adress & Data Bus lineIO-3,3--
C48PCI_AD31PCI Adress & Data Bus lineIO-3,3--
C49PCI_IRQA#PCI Bus Interrupt Request AI-3,3PU 2K7 3,3V-
C50PCI_IRQB#PCI Bus Interrupt Request BI-3,3PU 2K7 3,3V-
C51GNDGroundPWR--
C52PEG_RX0+PCI Express Recieve + (0)I - DP--
C53PEG_RX0-PCI Express Recieve - (0)I - DP--
C54TYPE0#-STO-not connected
C55PEG_RX1+PCI Express Recieve + (1)I - DP--
C56PEG_RX1-PCI Express Recieve - (1)I - DP--
C57TYPE1#-STO-not connected
C58PEG_RX2+PCI Express Recieve + (2)I - DP--
C59PEG_RX2-PCI Express Recieve - (2)I - DP--
C60GNDGroundPWR--
C61PEG_RX3+PCI Express Recieve + (3)I - DP--
C62PEG_RX3-PCI Express Recieve - (3)I - DP--
C63RSVDRx from Board ControllerNC--
C64RSVDTx from Board ControllerNC--
C65PEG_RX4+PCI Express Recieve + (4)I - DP--
C66PEG_RX4-PCI Express Recieve - (4)I - DP--
C67RSVDFAN_PWR_CTRLNC--
C68PEG_RX5+PCI Express Recieve + (5)I - DP--
C69PEG_RX5-PCI Express Recieve - (5)I - DP--
C70GNDGroundPWR--
C71PEG_RX6+PCI Express Recieve + (6)I - DP--
C72PEG_RX6-PCI Express Recieve - (6)I - DP--
C73SDVO_DATASDVO_CTRLDATANC--
C74PEG_RX7+PCI Express Recieve + (7)I - DP--
C75PEG_RX7-PCI Express Recieve - (7)I - DP--
C76GNDGroundPWR--
C77RSVDFAN_TACHNC--
C78PEG_RX8+PCI Express Recieve + (8)NC--
C79PEG_RX8-PCI Express Recieve - (8)NC--
C80GNDGroundPWR--
C81PEG_RX9+PCI Express Recieve + (9)NC--
C82PEG_RX9-PCI Express Recieve - (9)NC--
C83RSVDTPMPP (modify TPM address)NC--
C84GNDGroundNC--
C85PEG_RX10+PCI Express Recieve + (10)NC--
C86PEG_RX10-PCI Express Recieve - (10)NC--
C87GNDGroundPWR--
C88PEG_RX11+PCI Express Recieve + (11)NC--
C89PEG_RX11-PCI Express Recieve – (11)NC--
C90GNDGroundPWR--
C91PEG_RX12+PCI Express Recieve + (12)NC--
C92PEG_RX12-PCI Express Recieve - (12)NC--
C93GNDGroundPWR--
C94PEG_RX13+PCI Express Recieve + (13)NC--
C95PEG_RX13-PCI Express Recieve - (13)NC--
C96GNDGroundPWR--
C97RSVD-NC--
C98PEG_RX14+PCI Express Recieve + (14)NC--
C99PEG_RX14-PCI Express Recieve - (14)NC--
C100GNDGroundPWR--
C101PEG_RX15+PCI Express Recieve + (15)NC--
C102PEG_RX15-PCI Express Recieve - (15)NC--
C103GNDGroundPWR--
C104VCC_12VPower 12VPWR--
C105VCC_12VPower 12VPWR--
C106VCC_12VPower 12VPWR--
C107VCC_12VPower 12VPWR--
C108VCC_12VPower 12VPWR--
C109VCC_12VPower 12VPWR--
C110GNDGroundPWR--
D1GNDGroundPWR--
D2IDE_D5IDE Data BusIO--
D3IDE_D10IDE Data BusIO--
D4IDE_D11IDE Data BusIO--
D5IDE_D12IDE Data BusIO--
D6IDE_D4IDE Data BusIO--
D7IDE_D0IDE Data BusIO--
D8IDE_REQ#IDE Data BusI-3,3PD 5K6-
D9IDE_IOW#IDE IO WriteO-3,3--
D10IDE_ACK#IDE DMA AcknowledgeO-3,3--
D11GNDGroundPWR--
D12IDE_IRQIDE Interrupt RequestI-3,3PD 10K-
D13IDE_A0IDE Adress BusO-3,3--
D14IDE_A1IDE Adress BusO-3,3--
D15IDE_A2IDE Adress BusO-3,3--
D16IDE_CS1#IDE Chip Select Channel 0O-3,3--
D17IDE_CS3#IDE Chip Select Channel 1O-3,3--
D18IDE_RESET#IDE Hard Drive ResetO-3,3--
D19PCI_GNT3#PCI Bus Grant 3O-3,3--
D20PCI_REQ3#PCI Bus Request 3I-3,3--
D21GNDGroundPWR--
D22PCI_AD1PCI Adress & Data Bus lineIO-3,3--
D23PCI_AD3PCI Adress & Data Bus lineIO-3,3--
D24PCI_AD5PCI Adress & Data Bus lineIO-3,3--
D25PCI_AD7PCI Adress & Data Bus lineIO-3,3--
D26PCI_C/BE0#PCI Bus Command and Byte enables 0IO-3,3--
D27PCI_AD9PCI Adress & Data Bus lineIO-3,3--
D28PCI_AD11PCI Adress & Data Bus lineIO-3,3--
D29PCI_AD13PCI Adress & Data Bus lineIO-3,3--
D30PCI_AD15PCI Adress & Data Bus lineIO-3,3--
D31GNDGroundPWR--
D32PCI_PARPCI Bus ParityIO-3,3--
D33PCI_SERR#PCI Bus System ErrorIO-3,3PU 2K7 3,3V-
D34PCI_STOP#PCI Bus StopIO-3,3PU 2K7 3,3V-
D35PCI_TRDY#PCI Bus Target ReadyIO-3,3PU 2K7 3,3V-
D36PCI_FRAME#PCI Bus Cycle FrameIO-3,3PU 2K7 3,3V-
D37PCI_AD16PCI Adress & Data Bus lineIO-3,3--
D38PCI_AD18PCI Adress & Data Bus lineIO-3,3--
D39PCI_AD20PCI Adress & Data Bus lineIO-3,3--
D40PCI_AD22PCI Adress & Data Bus lineIO-3,3--
D41GNDGroundPWR--
D42PCI_AD24PCI Adress & Data Bus lineIO-3,3--
D43PCI_AD26PCI Adress & Data Bus lineIO-3,3--
D44PCI_AD28PCI Adress & Data Bus lineIO-3,3--
D45PCI_AD30PCI Adress & Data Bus lineIO-3,3--
D46PCI_IRQC#PCI Bus Interrupt Request CI-3,3PU 2K7 3,3V-
D47PCI_IRQD#PCI Bus Interrupt Request DI-3,3PU 2K7 3,3V-
D48PCI_CLKRUN#PCI Clock RunI-3,3--
D49PCI_M66EN#Control PCI Speed 33/66 MhzI-3,3PD 0KFixed to 33 Mhz
D50PCI_CLKPCI ClockO-3,3--
D51GNDGroundPWR--
D52PEG_TX0+PCI Express Transmit + (0)O - DP--
D53PEG_TX0-PCI Express Transmit - (0)O - DP--
D54PEG_LANE_RV#PCI Express Lane ReversalNC--
D55PEG_TX1+PCI Express Transmit + (1)O - DP--
D56PEG_TX1-PCI Express Transmit - (1)O - DP--
D57TYPE2#Connected to GNDSTO-not connected
D58PEG_TX2+PCI Express Transmit + (2)O - DP--
D59PEG_TX2-PCI Express Transmit - (2)O - DP--
D60GNDGroundPWR--
D61PEG_TX3+PCI Express Transmit + (3)O - DP--
D62PEG_TX3-PCI Express Transmit - (3)O - DP--
D63RSVD-NC--
D64RSVD-NC--
D65PEG_TX4+PCI Express Transmit + (4)O - DP--
D66PEG_TX4-PCI Express Transmit - (4)O - DP--
D67GNDGroundPWR--
D68PEG_TX5+PCI Express Transmit + (5)O - DP--
D69PEG_TX5-PCI Express Transmit - (5)O - DP--
D70GNDGroundPWR--
D71PEG_TX6+PCI Express Transmit + (6)O - DP--
D72PEG_TX6-PCI Express Transmit - (6)O - DP--
D73SDVO_CLKSDVO_CTRLCLKNC--
D74PEG_TX7+PCI Express Transmit + (7)O - DP--
D75PEG_TX7-PCI Express Transmit - (7)O - DP--
D76GNDGroundPWR--
D77IDE_CBLID#IDE Primary ATA DetectI-3,3PU 8K2 3,3V-
D78PEG_TX8+PCI Express Transmit + (8)NC--
D79PEG_TX8-PCI Express Transmit - (8)NC--
D80GNDGroundPWR--
D81PEG_TX9+PCI Express Transmit + (9)NC--
D82PEG_TX9-PCI Express Transmit - (9)NC--
D83RSVD-NC--
D84GNDGroundPWR--
D85PEG_TX10+PCI Express Transmit + (10)NC--
D86PEG_TX10-PCI Express Transmit - (10)NC--
D87GNDGroundPWR--
D88PEG_TX11+PCI Express Transmit + (11)NC--
D89PEG_TX11-PCI Express Transmit - (11)NC--
D90GNDGroundPWR--
D91PEG_TX12+PCI Express Transmit + (12)NC--
D92PEG_TX12-PCI Express Transmit - (12)NC--
D93GNDGroundPWR--
D94PEG_TX13+PCI Express Transmit + (13)NC--
D95PEG_TX13-PCI Express Transmit - (13)NC--
D96GNDGroundPWR--
D97PEG_ENABLE#PCI Express EnableNC--
D98PEG_TX14+PCI Express Transmit + (14)NC--
D99PEG_TX14-PCI Express Transmit - (14)NC--
D100GNDGroundPWR--
D101PEG_TX15+PCI Express Transmit + (15)NC--
D102PEG_TX15-PCI Express Transmit - (15)NC--
D103GNDGroundPWR--
D104VCC_12VPower 12VPWR--
D105VCC_12VPower 12VPWR--
D106VCC_12VPower 12VPWR--
D107VCC_12VPower 12VPWR--
D108VCC_12VPower 12VPWR--
D109VCC_12VPower 12VPWR--
D110GNDGroundPWR--
Signal Descriptions (cont’d)
Signal Type Legend
IO-2,5Bi-directional 2,5 V Input/Output
IO-3,3Bi-directional 3,3 V Input/Output
IO-5Bi-directional 5 V Input/Output
I-3,33,3 V Input
I-55 V Input
O-2,52,5 V Output
O-3,33,3 V Output
O-55 V Output
IOInput/Output
OAAnalog Output
I/O - DPDifferential Pair Input/Output
O - DPDifferential Pair Output
I - DPDifferential Pair Input
PWRPower or Ground
STOStrapping Output
PUPull-Up Resistor
PDPull-Down Resistor
NCNot Connected / Reserved
# 7 System Resources # 7.1 System Memory Map
Address Range (decimal)Address Range (hex)SizeDescription
(4GB-2MB)FFE00000-FFFFFFFF2 MBHigh BIOS Area
(4GB-18MB)-(4GB-17MB-1)FEE00000-FEEFFFFF1 MBFSB Interrupt Memory Space
(4GB-19MB)-(4GB-18MB-1)FED00000-FEDFFFFF1 MBChipset configuration Space
(4GB-20MB)-(4GB-19MB-1)FEC00000-FECFFFFF1 MBAPIC Configuration Space
15MB – 16MBF00000-FFFFFFFF1 MBISA Hole
960 K – 1024 KF0000-FFFFF64 KBSystem BIOS Area
896 K – 960 KE0000-EFFFF64 KBExtended System BIOS Area
768 K – 896 KC0000-DFFFF128 KBPCI expansion ROM areaC0000 – CEFFF: Onboard VGA BIOSCF000 – D0FFF: PXE option ROM when onboard LAN boot ROM is enabled
640 K – 768 KA0000 – BFFFF128 KBVideo Buffer & SMM space
0 K – 640 K00000 – 9FFFF640 KBDOS Area
# 7.2 Direct Memory Access Channels
Channel NumberData WidthSystem ResourceAvailable
08-bitsParallel portNote (1)
18-bitsParallel portNote (1)
28-bitsDiskette driveNote (1)
38-bitsParallel portNote (1)
4Reserved - cascade channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
![The image displays an icon featuring a white document sheet with faint grey horizontal lines representing text. A large red checkmark is superimposed on the upper left portion of the document. Below the paper graphic, the text 'NOTE:' appears in bold, black capital letters.](.express-dw400-50-1j011-1010-201/9a003dcc635388c2fcd4a721e4650b6ab09bb89ce7349ef0decd74b16bc87274.jpg) (1) DMA channel 0/1/3 is selected when using parallel port. DMA2 is used by Floppy. 7.3 I/O Map
Address (hex)SizeDescription
00h – 08h9 bytesDMA Controller
09h – 0Eh6 bytesDMA Controller
0Fh1 byteDMA Controller
10h – 18h9 bytesDMA Controller
19h – 1Eh6 bytesDMA Controller
1Fh1 byteDMA Controller
20h – 21h2 bytesInterrupt Controller
24h – 25h2 bytesInterrupt Controller
28h – 29h2 bytesInterrupt Controller
2Ch – 2Dh2 bytesInterrupt Controller
2Eh – 2Fh2 bytesLPC SIO
30h – 31h2 bytesInterrupt Controller
34h – 35h2 bytesInterrupt Controller
38h – 39h2 bytesInterrupt Controller
3Ch – 3Dh2 bytesInterrupt Controller
40h – 42h3 bytesTimer/Counter
43h1 bytesTimer/Counter
4Eh – 4Fh2 bytesLPC SIO
50h – 52h3 bytesTimer/Counter
53h1 bytesTimer/Counter
60h1 byteMicrocontroller
61h1 byteNMI Controller
62h1 byteMicrocontroller
63h1 byteNMI Controller
64h1 byteMicrocontroller
65h1 byteNMI Controller
66h1 byteMicrocontroller
67h1 byteNMI Controller
70h1 byteNMI and RTC Controller
71h1 byteRTC Controller
72h1 byteNMI and RTC Controller
73h1 byteRTC Controller
74h1 byteNMI and RTC Controller
75h1 byteRTC Controller
76h1 byteNMI and RTC Controller
77h1 byteRTC Controller
80h1 byteDMA Controller, or LPC, or PCI
81h – 83h4 bytesDMA Controller
84h – 86h3 bytesDMA Controller, or LPC, or PCI
87h1 byteDMA Controller
88h1 byteDMA Controller, or LPC, or PCI
89h – 8Bh3 bytesDMA Controller
8Fh1 byteDMA Controller, or LPC, or PCI
90h – 91h2 bytesDMA Controller
92h1 byteReset Generator
93h – 9Fh13 byteDMA Controller
84h – 86h3 bytesDMA Controller, or LPC, or PCI
87h1 byteDMA Controller
88h1 byteDMA Controller, or LPC, or PCI
89h – 8Bh3 bytesDMA Controller
8Ch– 8Eh3 bytesDMA Controller, or LPC, or PCI
8Fh1 byteDMA Controller
90h – 91h2 bytesDMA Controller
92h1 byteReset Generator
93h – 9Fh13 bytesDMA Controller
A0h – A1h2 bytesInterrupt Controller
A4h – A5h2 bytesInterrupt Controller
A8h – A9h2 bytesInterrupt Controller
ACh – ADh2 bytesInterrupt Controller
B0h – B1h2 bytesInterrupt Controller
B2h – B3h2 bytesPower Management
B4h – B5h2 bytesInterrupt Controller
B8h – B9h2 bytesInterrupt Controller
BCh – BDh2 bytesInterrupt Controller
C0h – D1h17 bytesDMA Controller
D2h – DDh12 bytesDMA Controller
DEh – DFh2 bytesDMA Controller
F0h1 byteInterrupt Controller
170h – 177h8 bytesSATA or PCI
1F0h – 1F7h8 bytesSATA or PCI
200h – 207h8 bytesGameport Low
208h – 20Fh8 bytesGameport High
376h1 byteSATA or PCI
3F6h1 byteSATA or PCI
400h – 47Fh128 bytesACPI Control Register
4D0h – 4D1h2 bytesInterrupt Controller
500h – 53Fh64 bytesGPIO Control Register
540h – 55Fh32 bytesOnboard SMBus Control Register
A79h1 byteISA PnP read data port.
CF8h – CFFh*8 bytesPCI Configuration Register
CF9h**1 byteReset Generator
4700h – 470Fh16 bytesTPM Control Register
![The image features a graphic of a document with a folded corner and a large red checkmark. Below the document, the text 'NOTE:' is written in black capital letters.](.express-dw400-50-1j011-1010-201/06fa5c6936a841622cd674248917e5f12c7ba0ee6c63dabcc4ea7928a91b0fb4.jpg) \* DWORD access only \*\* Byte access only # 7.4 Interrupt Request (IRQ) Lines PIC Mode
IRQ#Typical Interrupt ResourceConnectedAvailable
0Counter 0N/ANo
1Keyboard controllerN/ANo
2Cascade interrupt from slave PICN/ANo
3Serial Port 2 (COM2) / PCIIRQ3 via SERIRQNote (1)
4Serial Port 1 (COM1) / PCIIRQ4 via SERIRQNote (1)
5Parallel Port 2 (LPT2) / PCIIRQ5 via SERIRQNote (1)
6Floppy Drive ControllerIRQ6 via SERIRQNo
7Parallel Port 1 (LPT1) / PCIIRQ7 via SERIRQ,Note (1)
8Real-time clockN/ANo
9SCI / PCIIRQ9 via SERIRQNote (1)
10PCISATA controller / USB Controller / PCINote (1)
11PCIIRQ11 via SERIRQNote (1)
12PS/2 Mouse / PCIIRQ12 via SERIRQNote (1)
13Math ProcessorN/ANo
14Primary IDE controller / PCIUSB Controller / PCINote (1)
15Secondary IDE controller / PCIUSB Controller / PCNote (1)
![An icon depicting a white document with a large red checkmark. Below the document, the text 'NOTE:' appears in bold, black capital letters.](.express-dw400-50-1j011-1010-201/447365d3e999feb1736175cb459fc3ba8dd08192c35ddf72067a5a02d8c94e91.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. APIC Mode
IRQ#Typical Interrupt ResourceConnectedAvailable
0Counter 0N/ANo
1Keyboard controllerN/ANo
2Cascade interrupt from slave PICN/ANo
3Serial Port 2 (COM2) / PCIRQ3 via SERIRQNote (1)
4Serial Port 1 (COM1) / PCIIRQ4 via SERIRQNote (1)
5Parallel Port 2 (LPT2) / PCIIRQ5 via SERIRQNote (1)
6Floppy Drive ControllerIRQ6 via SERIRQNo
7Parallel Port 1 (LPT1) / PCIIRQ7 via SERIRQNote (1)
8Real-time clockN/ANo
9SCI / PCIIRQ9 via SERIRQNote (1),
10PCIIRQ10 via SERIRQNote (1)
11PCIIRQ11 via SERIRQNote (1)
12PS/2 Mouse / PCIIRQ12 via SERIRQNote (1)
13Math ProcessorN/ANo
14Primary IDE controller / PCIIRQ14 via SERIRQNote (1)
15Secondary IDE controller / PCIIRQ15 via SERIRQNote (1)
16N/APCI Slot INT A,Yes
17N/APCI Slot INT BYes
18N/APCIYes
19N/ASATA Controller, PCIYes
20N/ANo
21N/ANo
22N/ANo
23N/AEHCI, USBNo
![The image displays a white document icon with a large red checkmark. Below the icon, the text 'NOTE:' is written in black capital letters.](.express-dw400-50-1j011-1010-201/0a1d63f24c70b2e2a73ec4d22805de506670dbeee5e2eaacb85f9870ff631b95.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. 7.5 PCI Configuration Space Map
Bus No.Device No.Function No.RoutingDescription
00h00h00hN/AIntel 3100 Chipset Memory Controller Hub
00h02h00hInternalIntel IMCH Express Root port A1
00h03h00hInternalIntel IMCH Express Root port A1
00h1Bh00hInternalHigh Definition Audio controller
00h1Ch00hInternalIntel IICH Express Root port B0
00h1Ch01hInternalIntel IICH Express Root port B1
00h1Ch02hInternalIntel IICH Express Root port B2
00h1Ch03hInternalIntel IICH Express Root port B3
00h1Dh00hInternalIntel USB UHCI Controller 1
00h1Dh01hInternalIntel USB UHCI Controller 2
00h1Dh07hInternalIntel USB EHCI Controller
00h1Eh00hN/AIntel Hub Interface to PCI Bridge
00h1Fh00hN/AIntel LPC Interface Bridge
00h1Fh02hInternalIntel SATA controller
00h1Fh03hInternalIntel SMBus Controller
01h04h00hPIRQA-PIRQDExternal PCI Slot 1
01h05h00hPIRQA-PIRQDExternal PCI Slot 2
05h00h00honboardOnboard LAN controller
7.6 PCI Interrupt Routing Map
PIROINTUCHI 1UCHI 2EHCISATASMBusAudioPCI Slot1PCI Slot2LAN
AINTAXINTAINTBX
BINTBINTBINTC
CINTCINTCINTD
DINTDXXXINTDINTA
E
F
G
HXX
# 7.7 System Management Bus (I2C compatible) Internally the SMB bus and I2C bus are one and the same. The Intel® 3100 chipset supports SMBDAT and SMBCLK lines that are I2C compatible. The connectors have pinouts for both the I2C and SMB bus. Both are connected to the same internal bus: the SMB bus. It is advisable to always connect external I2C devices to the I2C pins and SMB devices to the SMB pins to stay in line with other modules that might support two internal busses (separate I2C and SMB bus).
AddressFunctionDevice
A0hMemory AddressSORDIMM2 (vertical or horizontal)
A2hMemory AddressSORDIMM1 (vertical only)
AChBackup EEPROMBackup EEPROM
AEhBackup EEPROMBackup EEPROM
30hHardware MonitorLM95235
5ChHardware MonitorLM87
D2hTimingClock Generator
DChTimingClock Buffer (SRC)
# 8 BIOS Setup Utility The following chapter describes the basic navigation of the AMIBIOS®8 BIOS setup utility. # 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keybaord when you see the following text prompt: ```txt <Press DEL to run Setup> ``` 3. After you press the < Delete > key, the main BIOS setup menu diplays. You can access the other setup screens from the main BIOS setup menu, such as the Chipset and Power menus. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NVRAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST38410A 007A](.express-dw400-50-1j011-1010-201/ae542040ab73dc94991b1e924dc4a7a37b23226fadc36d5c30ccf70592abd18a.jpg) ![The image displays a graphic icon of a white document with faint horizontal lines and a large red checkmark in the center. Below the document icon is the text 'NOTE:' in bold, black capital letters.](.express-dw400-50-1j011-1010-201/ac2c816575556b80258166c4a4dfd03e5107a4924054d6f0b0c6e5adbf1ca245.jpg) In most cases, the <Delete> key is used to invoke the setup screen. There are a few cases that other keys are used, such as <F1>, <F2>, and so on. # 8.1.1 Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed-out” options cannot be configured. Options is blue can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.
BIOS SETUP UTILITY
MainAdvancedPowerBootSecurityExit
System OverviewUse [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.
AMIBIOS
Version :08.00.14Build Date:08/13/08ID :DW400000
Processor
Speed :255MHzCount :255
System Memory← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit
Size :1024MB
System Time [00:15:01]System Date [Tue 01/01/2002]
# 8.1.2 Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. ![The flowchart begins with a top block labeled **'BIOS Setup Utility'**. A downward arrow connects this to the text **'Screens'**.\n\nFrom 'Screens', the diagram splits into two main sections:\n\n1. **Horizontal Screen Navigation:** A row of boxes reads **'Screen 1'**, **'Screen 2'**, **'Screen 3'**, **'Screen 4'**, and **'Screen 5'**. These are connected by double-headed horizontal arrows. A dotted arrow from the text **'Left and Right Keys to Select a Setup Screen'** points to 'Screen 1'.\n\n2. **Vertical Items/Fields Navigation:** A downward arrow from 'Screens' leads to the text **'Items'**. Below this, there are two rows of square boxes containing a plus sign (**±**).\n * The top row has three boxes connected by horizontal arrows.\n * The bottom row has three boxes connected by horizontal arrows.\n * Vertical arrows (one pointing down, one pointing up) connect the top row to the bottom row.\n\nSurrounding text boxes explain controls:\n* **'Tab Key to Select Fields'** points via a dotted line to the top row of boxes.\n* **'± To Change Field Values'** points via a dotted line to the top row of boxes.\n* **'Up and Down Keys to Select a Setup Item'** points via a dotted line to the vertical arrows between the rows.\n* An arrow points from the bottom row of boxes to the left toward the word **'Fields'**.](.express-dw400-50-1j011-1010-201/88b30729004990a805479bedef1569155a6101753f584e5725da8437f84052cd.jpg) There is a hot key legend located in the right frame on most setup screens.
Hot KeyDescription
→←Left/Right The Left and Right <Arrow> keys allow you to select an setup screen.
For example: Main screen, Advanced screen, Chipset screen, and so on.
↑↓Up/Down The Up and Down <Arrow> keys allow you to select an setup item or sub-screen.
+-Plus/Minus The Plus and Minus <Arrow> keys allow you to change the field value of a particular setup item.
For example: Date and Time.
TabThe <Tab> key allows you to select setup fields.
![The image shows a white document icon with a large red checkmark on it. Below the document graphic, the text 'NOTE:' is written in bold, black capital letters.](.express-dw400-50-1j011-1010-201/00bf9d11eaa0af880ddbbfdedd72370be28758eb4b83d50f02cdd0e9b307e85d.jpg) The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings. # Hot Key Description F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. General Help
←→Select Screen↓↑Select Item
+-Change ScreenEnterGo to Sub Screen
PGDNNext PagePGUPPrevious Page
HomeGo to Top of the ScreenEndGo to Bottom of Screen
F2/F3Change ColorsF7Discard Changes
F8Load Failsafe DefaultsF9Load Optimal Defaults
F10Save and ExitESCExit
[ok] F10 The < F10 > key allows you to save any changes you have made and exit Setup. Press the < F10 > key to save your changes. The following screen will appear: Save configuration changes and exit now? [ok] [Cancel] Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the < Esc > key to exit the setup without saving your changes. The following screen will appear: Discard changes and exit setup now? [ok] [Cancel] Press the < Enter > key to discard changes and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. # 8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.
BIOS SETUP UTILITY
MainAdvancedPowerBootSecurityExit
System OverviewUse [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use $\left\lbrack +\right\rbrack$ or [-] to configure system Time.
AMIBIOS Version :08.00.14 Build Date:08/13/08 ID :DW400000 Processor Speed :255MHz Count :255 System Memory Size :1024MB System Time [00:15:01] System Date [Tue 01/01/2002]
← Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit
# 8.2.1 System Time/System Date Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values through the keyboard. Press the < Tab > key or the < Arrow > keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. ![The image displays a graphic icon of a white document with a folded top-right corner and faint horizontal lines. A large red checkmark is centered on the page. Below the document graphic is the text 'NOTE:' in bold, black, capital letters.](.express-dw400-50-1j011-1010-201/876f731ee91fded15a06c51bcc66038f925d219538b927c602da9d9185e7e774.jpg) The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00. # 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the < Arrow > keys. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages.
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Advanced SettingsConfigure CPU.
CPU Configuration Chipset Configuration IDE Configuration AHCI Configuration SuperIO Configuration USB Configuration PCIPnP Remote Access Configuration Trusted ComputingSelect Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
![This image features a red triangle containing a white exclamation point in the center. Below the triangle, the text 'WARNING!' is printed in black capital letters.](.express-dw400-50-1j011-1010-201/5285faa8e46663fa08ec957e7bff0207f1b9f06f3b0239a915d7327d285a3aa0.jpg) Setting incorrect or conflicting values in Advanced BIOS Setup may cause system malfunctions. # 8.3.1 CPU Configuration # CPU Configuration Settings You can use this screen to select options for the CPU Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < Plus > and < Minus > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.
BIOS SETUP UTILITY
Advanced
Configure advanced CPU settingsModule Version:3F.02Manufacturer:IntelFrequency :255MHzFSB Speed :72MHzCache L1 :0 KBCache L2 :0 KBRatio Actual Value:14Execute-Disable Bit Capability [Enabled]DTS-based Thermal Management [Enabled]DTS Calibration [Enabled]Intel(R) SpeedStep(tm) tech [Disabled]Intel(R) C-STATE tech [Enabled]Enhanced C-States [Enabled]When disabled, force the XD feature flag to always return 0.< Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Execute Disable Bit Capability This item allows you to enable/disable the “Execute-Disable Bit” function. Intel’s Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. It allows the processor to classify areas in memory where application code can or cannot execute. When a malicious worm attempts to insert code in the buffer, the processor disables its code execution, preventing damage and worm propagation. To use Execute Disable Bit you must have a PC or server with a processor with Execute Disable Bit capability and a supporting operating system. # DTS-based Thermal Management This item allows you to Enable/Disable the Thermal Management utilizing the CPU’s Digital Thermal Sensor. # DTS Calibration This item allows you to Enable/Disable the calibration function of the CPU’s Digital Thermal Sensor. # Intel® SpeedStep™ tech This item allows you to enable/disable Intel® SpeedStep™ Technology. This function switches both voltage and frequency in tandem between high and low levels in response to processor load. # Intel® C-STATE tech This item allows you to Enable/Disable the Intel® C-state technology. C-state technology makes the power and thermal control unit part of the core logic and not part of the chipset. # Enhanced C-STATE This item allows you to Enable/Disable the Enhanced C- state function. # 8.3.2 Chipset Setup Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display a Chipset BIOS Setup option by highlighting it using the <Arrow> keys. The Chipset BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Advanced
South Bridge Chipset ConfigurationOptions
SMBUS Controller [Enabled]Enabled Disabled
SLP_S4# Min. Assertion Width [1 to 2 seconds]
Restore on AC Power Loss [Last State]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# SMBus Controller This item allows you to Enabled/Disable the SMBus function of the chipset. # SLP\_S4# Min. Assertion Width Options: 4 to 5 seconds, 3 to 4 seconds, 2 to 3 seconds, 1 to 2 seconds. # Restore on AC Power Loss The options for this value are Last State, Power On and Power Off.
OptionDescription
Power OffThe system goes into off state after an AC power loss.
Power OnThe system goes on after an AC power loss.
Last StateThe system goes into either off or on states, whatever the system state was before the AC power loss.
# 8.3.3 IDE Configuration # IDE Configuration Settings You can use this screen to select options for the IDE Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < Plus > and < Minus > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.
BIOS SETUP UTILITY Advanced
IDE Configuration
ATA/IDE Configuration Configure SATA as[Enhanced] [IDE]
► Primary IDE Master: [Not Detected]
► Primary IDE Slave: [Not Detected]
► Secondary IDE Master: [Not Detected]
► Secondary IDE Slave: [Not Detected]
# ATA/IDE Configuration This item specifies whether the IDE channels should be initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced. # Configure SATA as This item specifies whether the SATA interface should be legacy IDE or AHCI supported. The settings are IDE and AHCI. # Primary IDE Master/Slave, Secondary IDE Master/Slave Select one of the hard disk drives to configure it. Press < Enter > to access its the sub menu. # 8.3.4 AHCI Settings You can use this screen to select options for the AHCI Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the AHCI Configuration screen is shown below.
BIOS SETUP UTILITY
Advanced
AHCI SettingsWhile entering setup, BIOS auto detects the presence of IDE devices. This displays the status of auto detection of IDE devices.
▶ AHCI Port0 [Not Detected]
▶ AHCI Port1 [Not Detected]
▶ AHCI Port2 [Not Detected]
▶ AHCI Port3 [Not Detected]
▶ AHCI Port4 [Not Detected]
← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# AHCI Portx Set this value to configure the Advanced Host Controller Interface. It is an interface specification that allows the SATA controller driver to support advanced features like Native Command Queuing and Hot Plug. Each AHCI Port is automatically detected by the system. Select one of the hard disk drives to configure the AHCI function. Press < Enter > to access its sub menu. # 8.3.5 Super IO Configuration # SuperIO Configuration Screen You can use this screen to select options for the Super IO settings. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
BIOS SETUP UTILITY Advanced
Configure Win627 Super IO ChipsetAllows BIOS to Enable or Disable Floppy Controller.
OnBoard Floppy Controller [Disabled]
Floppy Drive Swap [Disabled]
Serial Port1 Address [3F8/IRQ4]
Serial Port2 Address [2F8/IRQ3]
Serial Port2 Mode [Normal]
Parallel Port Address [378]
Parallel Port Mode [Normal]
Parallel Port IRQ [IRQ7]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
# OnBoard Floppy Controller Set this value to Enable/Disable the onboard floppy controller function. # Floppy Drive Swap This option is used to logically swap the mapping of drives A: and B:. This option is dependent upon having two installed floppy drives. The settigns are Enabled and Disabled. # Serial Port1 Address This option specifies the base I/O port address and Interrupt Request address of Serial Port 1.
OptionDescription
DisabledSet this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable.
3F8/IRQ4Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt address.
3E8/IRQ4Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 4 for the interrupt address.
2F8/IRQ3Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 3 for the interrupt address.
2E8/IRQ3Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 3 for the interrupt address.
# Serial Port2 Address This option specifies the base I/O port address and Interrupt Request address of serial port 2, and are identical to those for Serial Port 1 above. The option selected for Serial Port 1 will not be available for Serial Port 2 # Serial Port2 Mode This option allows installation of an Infra-red device via Serial Port2. The settings are Normal, IRDA and ASK IR.
OptionDescription
NormalThe standard RS-232 Communication Port.
IrDAInfrared Dealer's Association protocol
ASK IRASK IR (Ask Computer Company infrared protocol)
# Parallel Port Address This option specifies the I/O address used by the parallel port.
OptionDescription
DisabledSet this value to prevent the parallel port from accessing any system resources. When the value of this option is set to Disabled, the printer port becomes unavailable.
378Set this value to allow the parallel port to use 378 as its I/O port address. The majority of parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.
278Set this value to allow the parallel port to use 278 as its I/O port address.
3BCSet this value to allow the parallel port to use 3BC as its I/O port address.
# Parallel Port Mode This option specifies the parallel port mode.
OptionDescription
NormalSet this value to allow the standard parallel port mode to be used.
EPPThe parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bi-directional data transfer driven by the host device.
ECPThe parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per second. ECP provides symmetric Bi-directional communication.
EPP+ECPAllow the parallel port to support both the ECP and EPP modes simultaneously.
# Parallel Port IRQ This option specifies the IRQ used by the parallel port.
OptionDescription
IRQ5Set this value to allow the serial port to use Interrupt 5.
IRQ7Set this value to allow the serial port to use Interrupt 7. The majority of parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.
# 8.3.6 USB Configuration # USB Configuration You can use this screen to select options for the USB Configuration. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
BIOS SETUP UTILITY
Advanced
USB ConfigurationModule Version - 2.24.3-13.4USB Devices Enabled :1 Keyboard, 1 DriveUSB Function [4 USB Ports]USB 2.0 Controller [Enabled]USB 2.0 Controller Mode [HiSpeed]Legacy USB Support [Enabled]USB Keyboard Legacy Support [Enabled]USB Mouse Legacy Support [Enabled]Port 64/60 Emulation [Disabled]USB Storage Device Support [Enabled]USB Beep Message [Enabled]BIOS EHCI Hand-Off [Enabled]► USB Mass Storage Device ConfigurationEnables USB host controllers.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
# USB Function Set this value to allow the system to Disable, Enable, and select a set number of onboard USB 2.0 ports. The options are Disabled, 2 USB Ports, and 4 USB Ports. # USB 2.0 Controller This field allows you to Enable/Disable the EHCI (USB 2.0) controller. # USB 2.0 Controller Mode This field configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps). # Legacy USB Support Legacy USB Support refers to the USB mouse and USB keyboard support. Normally if this option is not enabled, any attached USB mouse or USB keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or USB keyboard can control the system even when there is no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB Support. The Optimal and Fail-Safe default setting is Disabled.
OptionDescription
DisabledSet this value to prevent the use of any USB device in DOS or during system boot. This is the default setting.
EnabledSet this value to allow the use of USB devices during boot and while using DOS.
AutoThis option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS.
# Port 60/64 Emulation This option allows you to Enable/Disable the I/O port 60h/64h emulation support for non-USB aware operating systems. # USB Storage Device Support Allows you to enable or disable the USB storage device support. # USB Beep Message Allows you to Enable/Disable the beep during USB device enumeration. # USB BIOS EHCI Hand-off Allows you to enable the support for operating systems without EHCU hand-off feature. # USB Mass Storage Reset Delay This item allows you to set the reset delay for USB mass storage device. # USB Mass Storage Device Configuration This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.
BIOS SETUP UTILITY
Advanced
USB Mass Storage Device ConfigurationUSB Mass Storage Reset Delay [20 Sec]Device #1 Generic STORAGE DEVICEEmulation Type [Auto]If Auto, USB devices less than 530MB will be emulated as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to boot as FDD (Ex. ZIP drive).← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.3.7 PCI/PnP Setup Select the PCI/PnP tab from the setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the <Arrow> keys. The Plug and Play BIOS Setup screen is shown below. ![BIOS SETUP UTILITY\nAdvanced\nAdvanced PCI/PnP Settings\nWARNING: Setting wrong values in below sections\nmay cause system to malfunction.\nClear NURAM (No)\nPlug & Play O/S (No)\nPCI Latency Timer (64)\nAllocate IRQ to PCI VGA (Yes)\nPalette Snooping (Disabled)\nOffBoard PCI/ISA IDE Card (Auto)\nIRQ3 (Available)\nIRQ4 (Available)\nIRQ5 (Available)\nIRQ7 (Available)\nIRQ9 (Available)\nIRQ10 (Available)\nIRQ11 (Available)\nIRQ14 (Available)\nClear NURAM during\nSystem Boot.\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.express-dw400-50-1j011-1010-201/9457429265002ea7bc95d5df9fe523696b49e41c51d8ff35063a94886522c04c.jpg) # Clear NVRAM This option clears ESCD (Extended System Configuration Data) information in NVRAM. # Plug & Play O/S When set to "Yes" and a Plug and Play operating system is installed, the operating system configures the Plug and Play devices not required for boot. # PCI Latency Timer Allows you to select the value in units of PCI clocks for the PCI device latency timer register. # Allocate IRQ to PCI VGA When set to "Yes", the BIOS will assign an IRQ for a PCI VGA card. # Palette Snooping Normally this option is always Disabled. Non standard VGA display adapters such as overlay cards or MPEG video cards may not show colors properly. Setting this option to Enabled should correct this problem. If set to Enabled, any I/O access on the ISA bus to the VGA card's palette registers will be reflected on the PCI bus. This will allow overlay cards to adapt to the changing palette colors. # OffBoard PCI/ISA IDE Card Set this option to allow the OffBoard PCI/ISA IDE Card to be selected. # IRQ Set this value to allow the IRQ settings to be modified. Available - This setting allows the specified IRQ to be used by a PCI/PnP device. Reserved - This setting allows the specified IRQ to be used by a legacy ISA device. # 8.3.8 Remote Access Configuration # Remote Access Configuration You can use this screen to select options for the Remote Access Configuration, which provides the settings to allow remote access by another computer to get POST messages and issue commands through serial port access. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
BIOS SETUP UTILITY
Advanced
Configure Remote Access type and parametersSelect Remote Access type.
Remote Access [Enabled]
Serial port number [COM1]
Base Address, IRQ [3F8h, 4]
Serial Port Mode [115200 8,n,1]
Flow Control [None]
Redirection After BIOS POST [Always]
Terminal Type [ANSI]
VT-UTF8 Combo Key Support [Enabled]
Sredir Memory Display Delay [No Delay]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Remote Access Select this option to Enable or Disable the BIOS remote access feature. ![The image displays an icon of a white document with a folded upper-right corner and faint horizontal lines, overlaid with a large, bold red checkmark. Below the document, the text 'NOTE:' appears in black capital letters.](.express-dw400-50-1j011-1010-201/15c3daab08f93d3d78d081cb0e7c3651ada044048f69b8f39ae6acbf414bfd41.jpg) Enabled Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot. # Serial Port Number Select the serial port you want to use for the remote access interface. You can set the value for this option to either COM1 or COM2. ![The image displays a digital icon of a white document with a folded top-right corner and faint horizontal lines. A large red checkmark is centered on the document. Below the graphic is the text 'NOTE:'.](.express-dw400-50-1j011-1010-201/bedad3638456bdef78630814e3bd741a85dbd93ca79c2e8c1cdbbe94fe2c5ffa.jpg) If you have changed the resource assignment of the serial ports in Advanced>SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the available Remote Access options. # Serial Port Mode Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1. # Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software. # Redirection After BIOS POST This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.
OptionDescription
DisabledSet this value to turn off the redirection after POST
Boot LoaderSet this value to allow the redirection to be active during POST and Boot Loader.
AlwaysSet this value to allow the redirection to be always active.
# Terminal Type This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8. # VT-UTF8 Combo Key Support This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled. # Sredir Memory Display Delay This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec. # 8.3.9 Trusted Computing Trusted computing is an industry standard to make personal computers more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support.
BIOS SETUP UTILITY
Advanced
Trusted ComputingEnable/Disable TPM TCG (TPM 1.1/1.2) supp in BIOS
TCG/TPM SUPPORT [Yes]
TPM Enable/Disable Status [No State]
TPM Owner Status [No State]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.4 Power Setup Select the Power tab from the setup screen to enter the Power Management Setting Setup screen. You can select any of the items in the left frame of the screen, such as ACPI Configuration, to go to the sub menu for that item. You can display a Power Management option by highlighting it using the < Arrow > keys. The Power Management BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Power Management SettingsSection for Advanced ACPI Configuration.
ACPI Configuration APM Configuration Hardware Health ConfigurationSelect Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.4.1 Advanced ACPI Configuration # Advanced ACPI Configuration You can use this screen to select options for the Advanced ACPI Configuration settings. Use the up and down <Arrow> keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The ACPI BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Power
Advanced ACPI ConfigurationSelect the ACPI state used for System Suspend.
Suspend mode [S3 (STR)]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Suspend mode This setting selects either S1 (POS) or S3 (STR) system suspend mode. # 8.4.2 APM Configuration You can use this screen to select options for the APM settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The APM BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Power
APM ConfigurationEnable or disable APM.
Power Management/APM [Enabled]
Video Power Down Mode [Suspend]
Hard Disk Power Down Mode [Suspend]
Suspend Time Out [Disabled]
Power Button Mode [On/Off]
Advanced Resume Event Controls
Resume On LAN [Disabled]
Resume On PME# [Disabled]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Power Management/APM Set this value to Enable or Disable Power Management/APM (Advanced Power Management) features. # Video Power Down Mode This option specifies the power management state that the video subsystem enters when the BIOS places it in a power saving state after the period of inactivity specified in Suspend Time Out has expired. The options are Disabled and Suspend. # Hard Disk Drive Power Down Mode This option specifies the power management state that the hard disk drive enters after the period of hard drive inactivity specified in Suspend Time Out has expired. # Suspend Time Out This option specifies the length of time the system waits before it enters suspend mode. The options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min, and 60 Min. # Power Button Mode This feature allows users to configure the Power Button function.
OptionDescription
On/OffTurn the system On/Off when the power button is pressed.
SuspendThe system goes into suspend mode or resumes from suspend mode when power button is pressed.
# Restore on AC Power Loss Determines what state the computer enters when AC power is restored after a power loss. The options for this value are Last State, Power On and Power Off.
OptionDescription
Power OffThe system remains powered off when AC power is restored.
Power OnThe system powers on after AC power is restored.
Last StateThe system will power off/on depending on the last system power state when AC power is restored.
# Advanced Resume Event Controls # Resume on LAN The item specifies how the system will be awakened from power saving mode by an onboard LAN device. # Resume on PME# The item specifies how the system will be awakened from power saving mode when a PCI input signal is detected. # 8.4.3 Hardware Health Configuration This option displays the current status of all of the monitored hardware devices/components such as CPU voltages, temperatures and fan speeds. The options are Enabled and Disabled.
BIOS SETUP UTILITY
Power
H/W Health Function[Enabled]Enables HardwareHealth MonitoringDevice.
System Temperature Reading:35°C/95°F
CPU Temperature Reading:52°C/125°F
VCORE:1.169 U
+1.05V:1.032 U
+1.8V:1.903 U
+5V:4.728 U
+12V:12.272 U
← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.5 Boot Setup Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display an Boot BIOS Setup option by highlighting it using the < Arrow > keys. The Boot Settings screen is shown below:
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Boot SettingsConfigure Settings during System Boot.
► Boot Settings Configuration
1st Boot Device [Removable Dev.]
2nd Boot Device [CD/DVD]
3rd Boot Device [USB:Kingston DataT]
► Hard Disk Drives
► Removable Drives
► CD/DVD Drives
← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
# Boot Device Priority Set the boot device options to determine the sequence in which the computer checks which device to boot from. # Boot Device Groups The Boot devices are listed in groups by device type. First press <Enter> to enter the submenu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or <PageUp>, <PageDown> key to move it up/down in the priority list. For example, USB storage disks will be listed as “USB Drives” in the sub-menu. Only the first device in each device group will be available for selection in the Boot Device Priority option. # Boot Settings Configuration Use this screen to select options for the Boot Settings Configuration. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The screen is shown below.
BIOS SETUP UTILITYBoot
Boot Settings Configuration
Quick Boot[Enabled]Quiet Boot[Disabled]AddOn ROM Display Mode[Force BIOS]Bootup Num-Lock[On]PS/2 Mouse Support[Auto]Wait For 'F1' If Error[Enabled]Hit 'DEL' Message Display[Enabled]Interrupt 19 Capture[Disabled]Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.< Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
# Quick Boot Disabled - Set this value to allow the BIOS to perform all POST tests. Enabled - Set this value to allow the BIOS to skip certain POST tests to boot faster. # Quiet Boot Disabled - Set this value to allow the computer system to display the POST messages. Enabled - Set this value to allow the computer system to display the OEM logo. # AddOn ROM Display Mode This feature controls the display of ROM messages from the BIOS of add-on devices like graphics cards or SATA controllers during the boot sequence. When set to Force BIOS, AddOn ROM messages will be forced to display during the boot sequence. When set to Keep Current, AddOn ROM messages will only be displayed if the third-party manufacturer had set the add-on device to do so. # Bootup Num-Lock Set this value to allow the Number Lock setting to be modified during boot up. Off - This option does not enable the keyboard Number Lock automatically. To use the 10- keys on the keyboard, press the Number Lock key located on the upper left-hand corner of the 10-key pad. The Number Lock LED on the keyboard will light up when the Number Lock is engaged. On - Set this value to allow the Number Lock on the keyboard to be enabled automatically when the computer system is boot up. This allows the immediate use of 10-keys numeric keypad located on the right side of the keyboard. To confirm this, the Number Lock LED light on the keyboard will be lit. # PS/2 Mouse Support Allows you to enable/disable PS/2 mouse support. # Wait for ‘F1’ If Error If this option is set to Disabled, AMIBIOS does not wait for you to press the <F1> key after an error message. # Hit ‘DEL’ Message Display When set to Enabled, the system displays the message "Press DEL to run Setup during POST". # Interrupt 19 Capture Interrupt 19 is the software interrupt that handles the boot disk function. When enabled, this feature allows the AddOn ROM of these host adaptors to “capture” Interrupt 19 during the boot process so that drives attached to these adaptors can function as bootable disks. In addition, it allows you to gain access to the host adaptor’s AddOn ROM setup utility, if one is available. When disabled, the AddOn ROM of these host adaptors will not be able to “capture” Interrupt 19. Therefore, you will not be able to boot operating systems from any bootable disks attached to these host adaptors. Nor will you be able to gain access to their AddOn ROM utilities. # 8.6 Security Setup
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Security SettingsInstall or Change the password.
Supervisor Password :Not Installed User Password :Not Installed
Change Supervisor Password Change User Password Clear User Password
There are no supported Hard Disks.
← Select Screen ↑↓ Select Item Enter Change F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.6.1 Password Support # Two Levels of Password Protection The BIOS provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password. The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure. # Remember the Password Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM. Select Security Setup from the Setup main BIOS setup menu. Security Setup options, such as password protection and virus protection, are described in this section. To access the sub menu for the following items, select the item and press < Enter >: - Change Supervisor Password - Change User Password - Clear User Password # Supervisor Password Indicates whether a supervisor password has been set. # User Password Indicates whether a user password has been set. # Change Supervisor Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the supervisor password. # Change User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the user password. # Clear User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to clear the user password. # 8.6.2 Change Supervisor Password Select Change Supervisor Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.3 Change User Password Select Change User Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.4 Clear User Password Select Clear User Password from the Security Setup menu and press < Enter >. Clear New Password [Ok] [Cancel] Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.7 Exit Menu Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the <Arrow> keys. The Exit BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Exit Options Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe DefaultsExit system setup after saving the changes. F10 key can be used for this operation. ← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Save Changes and Exit When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect. Select Exit Saving Changes from the Exit menu and press < Enter >. Save Configuration Changes and Exit Now? [Ok] [Cancel] appears in the window. Select Ok to save changes and exit. # Discard Changes and Exit Select this option to quit Setup without making any permanent changes to the system configuration. Select Exit Discarding Changes from the Exit menu and press <Enter>. Discard Changes and Exit Setup Now? [Ok] [Cancel] appears in the window. Select Ok to discard changes and exit. # Discard Changes Select Discard Changes from the Exit menu and press < Enter >. Select Ok to discard changes. # Load Optimal Defaults Automatically sets all Setup options to a complete set of default settings when you Select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems. Select Load Optimal Defaults from the Exit menu and press < Enter >. Select Ok to load optimal defaults. # Load Failsafe Defaults Automatically sets all Setup options to a complete set of default settings when you Select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the Fail-Safe Setup options if your computer is experiencing system configuration problems. Select Load Fail-Safe Defaults from the Exit menu and press < Enter >. Load Fail-Safe Defaults? [Ok] [Cancel] appears in the window. Select Ok to load Fail-Safe defaults. # 9 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMIBIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMIBIOS checkpoints. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2001 American Megatrends, Inc.\nBIOS Date: 10/01/01 12:39:39 Ver: 08.00.03\nPentium (R) III Processor, 933MHz\nPress DEL to run Setup\nChecking NURAM..\nCheckpoint Display\nEVALUATION COPY, NOT FOR SALE\n(C) American Megatrends Inc.,\n63-0100-000001-00101111-100101-015-0AAXT004-Y2KC\n6B3B](.express-dw400-50-1j011-1010-201/b5dd3c5b2038d511992742280b4a548e7af36ecaac9c49cc53f9c0d127385d8a.jpg) # 9.1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS: ![The image displays an icon of a white document with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed over the document. Below the icon, the text 'NOTE:' is written in black capital letters.](.express-dw400-50-1j011-1010-201/fdbba5741e67129cbc22bd3846cb59357cd34b5af025137f7f37b783e94ae5f5.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.
CheckpointDescription
Before D0If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point. Stack will be enabled from this point.
D0Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU critical initialization. Early chipset initialization is done.
D1Early super I/O initialization is done including RTC and keyboard controller. Serial port is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled.
D2Verify the boot block checksum. System will hang here if checksum is bad.
D3Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing module not executed, start memory refresh and do memory sizing in Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly.
D6Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.
D7Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.
D8The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.
DARestore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.
DCSystem is waking from ACPI S3 state
E1-E8, EC-EEOEM memory detection/configuration error. This range is reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.
# 9.2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS: ![The image displays a digital icon of a white document with a folded top-right corner. It features a large red checkmark in the upper left area and grey horizontal lines near the bottom representing text. Below the icon, the text 'NOTE:' appears in black capital letters.](.express-dw400-50-1j011-1010-201/42c4f4406f6d90fef1ed48077f6bfa765030a0ca0f23c70edde1c86a035a6902.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.
CheckpointDescription
E0Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9Set up floppy controller and data. Attempt to read from floppy.
EAEnable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EBDisable ATAPI hardware. Jump back to checkpoint E9.
EFRead error occurred on media. Jump back to checkpoint EB.
F0Search for pre-defined recovery file name in root directory.
F1Recovery file not found.
F2Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3Start reading the recovery file cluster by cluster.
F5Disable L1 cache.
FACheck the validity of the recovery file configuration to the current configuration of the flash part.
FBMake flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.
F4The recovery file size does not equal the found flash part size.
FCErase the flash part.
FDProgram the flash part.
FFThe flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
# 9.3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS: ![The image displays a white document icon with a folded top corner featuring a large red checkmark. Below the icon, the text 'NOTE:' appears in black capital letters.](.express-dw400-50-1j011-1010-201/441828cc363d1fc2dad6f5a0fe55508dc56213742513dca8e86218eac6d7598b.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.
CheckpointDescription
03Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system
05Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
07Fixes CPU POST interface calling pointer.
08Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.
C0Early CPU Init Start -- Disable Cache - Init Local APIC
C1Set up boot strap processor Information
C2Set up boot strap processor for POST
C5Enumerate and set up application processors
C6Re-enable cache for boot strap processor
C7Early CPU Init Exit
0AInitializes the 8042 compatible Key Board Controller.
0BDetects the presence of PS/2 mouse.
0CDetects the presence of Keyboard in KBC port.
0ETesting and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
13Early POST initialization of chipset registers.
20Relocate System Management Interrupt vector for all CPU in the system.
24Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this checkpoint.
2AInitializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
2CInitializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2EInitializes all the output devices.
POST Code Checkpoints cont’d:
CheckpointDescription
31Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33Initializes the silent boot module. Set the window for displaying text information.
37Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point.
39Initializes DMAC-1 & DMAC-2.
3AInitialize RTC date/time.
3BTest for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
3CMid POST initialization of chipset registers.
40Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA...etc.
52Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
60Initializes NUM-LOCK status and programs the KBD typematic rate.
75Initialize Int-13 and prepare for IPL detection.
78Initializes IPL devices controlled by BIOS and option ROMs.
7CGenerate and write contents of ESCD in NVRam.
84Log errors encountered during POST.
85Display errors to the user and gets the user response for error.
87Execute BIOS setup if needed / requested. Check boot password if installed.
8CLate POST initialization of chipset registers.
8DBuild ACPI tables (if ACPI is supported)
8EProgram the peripheral parameters. Enable/Disable NMI as selected
90Initialization of system management interrupt by invoking all handlers. Please note this checkpoint comes right after checkpoint 20h
A1Clean-up work needed before booting to OS.
A2Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
A4Initialize runtime language module. Display boot option popup menu.
A7Displays the system configuration screen if enabled. Initialize the CPU's before boot, which includes the programming of the MTRR's.
A9Wait for user input at config display if needed.
AAUninstall POST INT1Ch vector and INT09h vector.
ABPrepare BBS for Int 19 boot. Init MP tables.
ACEnd of POST initialization of chipset registers. De-initializes the ADM module.
B1Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.
00Passes control to OS Loader (typically INT19h).
# 9.4 OEM POST Error Checkpoints Checkpoints from the range 61h to 70h are reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next. # 9.5 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed: ![The image displays a document icon with a folded upper-right corner. A large red checkmark is superimposed on the left side of the document, which also features faint horizontal lines. Below the document graphic, the text 'NOTE:' is written in black, capital letters.](.express-dw400-50-1j011-1010-201/03ce52e2e3e2932d4fdfd12603cf24218fd0468d34a6bcfbd8013f9abf877e76.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.
CheckpointDescription
2AInitialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI- PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.
38Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.
While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: # HIGH BYTE XY The upper nibble ‘X’ indicates the function number that is being executed. ‘X’ can be from 0 to 7. 0 = func#0, disable all devices on the BUS concerned. 1 = func#1, static devices initialization on the BUS concerned. 2 = func#2, output device initialization on the BUS concerned. 3 = func#3, input device initialization on the BUS concerned. 4 = func#4, IPL device initialization on the BUS concerned. 5 = func#5, general device initialization on the BUS concerned. 6 = func#6, error reporting for the BUS concerned. 7 = func#7, add-on ROM initialization for all BUSes. 8 = func#8, BBS ROM initialization for all BUSes. The lower nibble ‘Y’ indicates the BUS on which the different routines are being executed. ‘Y’ can be from 0 to 5. 0 = Generic DIM (Device Initialization Manager). 1 = Onboard System devices. 2 = ISA devices. 3 = EISA devices. 4 = ISA PnP devices. 5 = PCI devices. # 9.6 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events: ![A document icon featuring a large red checkmark, with the text 'NOTE:' below it.](.express-dw400-50-1j011-1010-201/cfa6a15ffda78e4f5d7c7e4a9c5dbf1169c42c1316c26a66add1e3831f034701.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices. # 9.7 Boot Block Beep Codes
No. of BeepsDescription
1Insert diskette in floppy drive A:
2‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3Base Memory error
4Flash Programming successful
5Floppy read error
6Keyboard controller BAT command failed
7No Flash EPROM detected
8Floppy controller failure
9Boot Block BIOS checksum error
10Flash Erase error
11Flash Program error
12‘AMIBOOT.ROM’ file size error
13BIOS ROM image mismatch (file layout does not match image present in flash device)
# 9.8 POST BIOS Beep Codes
No. of BeepsDescription
1Memory refresh timer error.
2Parity error in base memory (first 64KB block)
3Base memory read/write test error
4Motherboard timer not operational
5Processor error
68042 Gate A20 test error (cannot switch to protected mode)
7General exception error (processor exception interrupt error)
8Display memory error (system video adapter)
9AMIBIOS ROM checksum error
10CMOS shutdown register read/write error
11Cache memory test failed
# 9.9 Troubleshooting POST BIOS Beep Codes
No. of BeepsDescription
1, 2 or 3Reseat the memory, or replace with known good modules.
4-7, 9-11Fatal error indicating a serious problem with the system. Consult your system manufacturer.Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.- If beep codes are generated when all other expansion cards are absent, consult your system manufacturer's technical support.- If beep codes are not generated when all other expansion cards are absent, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem happens again. This will reveal the malfunctioning card.
8If the system video adapter is an add-in card, replace or reseat the video adapter. If the video adapter is an integrated part of the system board, the board may be faulty.
# Appendix A: Available USB Ports # A.1 Description The Intel® 3100 chipset supports 4 USB ports. The figure on the right indicates which USB ports can be used on the Express-BASE carrier. ![Not connected\nUSB ports\nActive USB\nports](.express-dw400-50-1j011-1010-201/910865f32347953bdb7136c8db61868c9cb86767f96c6761d42581e0e1993f0a.jpg) This page intentionally left blank. # Important Safety Instructions For user safety, please read and follow all instructions, warnings, cautions, and notes marked in this manual and on the associated equipment before handling/operating the equipment. f Read these safety instructions carefully. f Keep this user’s manual for future reference. f Read the specifications section of this manual for detailed information on the operating environment of this equipment. f When installing/mounting or uninstalling/removing equipment: \- Turn off power and unplug any power cords/cables. f To avoid electrical shock and/or damage to equipment: - Keep equipment away from water or liquid sources; - Keep equipment away from high heat or high humidity; - Keep equipment properly ventilated (do not block or cover ventilation openings); - Make sure to use recommended voltage and power source settings; - Always install and operate equipment near an easily accessible electrical socket-outlet; - Secure the power cord (do not place any object on/over the power cord); - Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and, - If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. f Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. f A Lithium-type battery may be provided for uninterrupted, backup or emergency power. ![The image shows a yellow triangular warning sign containing a black exclamation point in the center. Below the triangle, the word 'CAUTION:' is printed in black capital letters on a white background.](.express-dw400-50-1j011-1010-201/a4b28da3925c216ca660a0547ecb2ddf035c274fc403f6397409e5156df95356.jpg) Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries according to the instructions. f Equipment must be serviced by authorized technicians when: - The power cord or plug is damaged; - Liquid has penetrated the equipment; - It has been exposed to high humidity/moisture; - It is not functioning or does not function according to the user’s manual; - It has been dropped and/or damaged; and/or, - It has an obvious sign of breakage. # Getting Service Contact us should you require any service or assistance. # ADLINK Technology Inc. Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan ؀קᗼխࡉؑ৬ԫሁ166ᇆ 9ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com # Ampro ADLINK Technology Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1 োⲜ߯ ࡯ࡼ ໻ॺ E ᑻ 801 ᅸ (100085) Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing 100085, China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com # ADLINK Technology Shanghai Address: Ϟ⍋Ꮦⓩ⊇⋒催⾥ᡔᓔথऎ䩺∳䏃 333 ো 39 ᐶ 4 ሖ (200233) Tel: +86-21-6495-5210 Fax: +86-21-5450-0414 Email: market@adlinktech.com # ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bld. A1, Cyber-Tech Zone, Gao Xin Ave. Sec 7, High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com # ADLINK Technology Inc. (German Liaison Office) Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: emea@adlinktech.com # ADLINK (French Liaison Office) Address: 15 rue Emile Baudot, 91300 MASSY Cedex, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com # ADLINK Technology Japan Corporation Address: 151-0072 ᧲੩ㇺᷦ⼱඙ᐈ䊱⼱ 1-1-2 ᦺᣣ↢๮ᐈ䊱⼱䊎䊦 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan Tel: +81-3-4455-3722 Fax: +81-3-5333-6040 Email: japan@adlinktech.com # ADLINK Technology Inc. (Korean Liaison Office) Address: 昢殾柢 儛單割 嚂笊壟 60-12 壟昷捒娯 4 猻 402 笾 No.402, Dongsung B/D, 60-12, Nonhyeon-Dong Gangnam-gu, Seoul, 135-010, Korea. Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com # ADLINK Technology Singapore Pte Ltd. Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com # ADLINK Technology Singapore Pte Ltd. (Indian Liaison Office) Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email: india@adlinktech.com ![The image displays the universal recycling symbol, also known as the Mobius loop. It features three white arrows arranged in a triangular formation against a solid black circular background. The arrows are stylized and arranged in a clockwise rotation, pointing towards one another to create a continuous cycle.](.express-dw400-50-1j011-1010-201/16074df3b684cce9ab1d5437f46de0b4bce95f1e04fbf341f8e4fb0289d45a4e.jpg) [🔗 Link to the original document](.express-dw400-50-1j011-1010-201/express-dw400-50-1j011-1010-201.pdf)