# Express-KL2 User's Manual

COM Express Basic Size Type 2 Module with 64-bit 7th Gen Intel® Core™, Xeon® E3 and Celeron® processors

![Close-up of a green printed circuit board with multiple microchips and connectors (no readable text or symbols)](.express-kl2-50-1j101-1000-10/8032c8ced31a9bb93b903efb4ccaf875d78bb9d9e96758f6bfdef7d8d676b6c6.jpg)

![COM\nExpress®](.express-kl2-50-1j101-1000-10/1f06eb7d747e3a60942d1404dbbd872054d5d6db217cf73b28d9cd79c71702b4.jpg)

Manual Rev.: 1.0

Revision Date: October 28, 2019

Part Number: 50-1J101-1000

# Preface

# Copyright

Copyright © 2019 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2019-10-28</td><td>JC</td></tr></table>

# Table of Contents

# Preface....ii

# List of Figures ......V

# List of Tables......vi

# 1. Introduction......1

# 2. Specifications ....3

2.1. Core System 3

2.2. Expansion Busses....3

2.3. Video....4

2.4. Audio....4

2.5. LAN 4

2.6. Multi I/O and Storage ....4

2.7. Trusted Platform Module (TPM)......5

2.8. SEMA Board Controller....5

2.9. Debug 5

2.10. Power Specifications....5

2.11. Power Consumption....5

2.12. Operating Temperatures....6

2.13.Environmental 6

2.14. Specification Compliance....6

2.15. Operating Systems....6

2.16. Functional Diagram....7

2.17. Mechanical Drawing....8

# 3. Pinouts and Signal Descriptions....9

3.1. AB/CD Pin Definitions 9

3.2. Signal Description Terminology .... 12

3.3. AB Signal Descriptions....13

3.4. CD Signal Descriptions 22

# 4. Connector Pinouts on Module....27

4.1. Connector, Switch and LED Locations....27

4.2. 40-pin Debug Connector....29

4.3. Status LEDs 30

4.4. Fan Connector 31

4.5. BIOS Setup Defaults Reset Button 32

4.6. Switch Settings ...... 33

4.7. PCIe x16-to-two-x8 Adapter Card 35

# 5. Smart Embedded Management Agent (SEMA) 37

5.1. Board Specific SEMA Functions 38

# 6. System Resources ....41

6.1. System Memory Map 41

6.2. Direct Memory Access Channels 41

6.3. I/O Map 41
6.4. Interrupt Request (IRQ) Lines 43
6.5. PCI Configuration Space Map....44
6.6. PCI Interrupt Routing Map 45
6.7. SMBus Address Table 45

# 7. BIOS Setup......47

7.1. Menu Structure....47
7.2. Main 48
7.3. Advanced 52
7.4. Boot....69
7.5. Security 70
7.6. Save & Exit 71

# 8. BIOS Checkpoints, Beep Codes....73

8.1. Status Code Ranges....74
8.2. Standard Status Codes....74
8.3. OEM-Reserved Checkpoint Ranges 81

# 9. Mechanical Information....83

9.1. Board-to-Board Connectors 83
9.2. Thermal Solution 84
9.3. Mounting Methods....87
9.4. Standoff Types....88

# Safety Instructions....89

# Getting Service....90

# List of Figures

Figure 1: Express-KL2 Functional Block Diagram ....7
Figure 2: Express-KL2 Mechanical Drawing....8
Figure 3: Express-KL2 Connector, Switch and LED Locations.... 27
Figure 4: Express-KL2 and the DB40 Debug Module 28
Figure 5: cExpress Switch Locations .... 33
Figure 6: COM Express Mounting Methods....87
Figure 7: COM Express Standoff Types....88

# List of Tables

Table 1: Express-KL2 AB/CD Pin Definitions....9
Table 2: 40-pin Debug Connector Pin Definition.... 29
Table 3: Express-KL2 LED Descriptions.... 30
Table 4: Fan Connector Pin Definition ...... 31
Table 5: PCI Express Configuration Switch Settings 33
Table 6: BIOS Select and Mode Configuration Switch Settings.... 34
Table 7: SEMA Onboard Voltage Monitor 38
Table 8: SEMA BMC Status 38
Table 9: SEMA Exception Codes....39
Table 10: SEMA BMC Flags.... 39

# 1. Introduction

The Express-KL2 is a COM Express® COM.0 R2.1 Type 2 module supporting the 64-bit 7th Generation Intel® Core™ and Intel® Xeon® E3 processors (formerly “Kaby Lake H”) with Intel® 175, HM175 and CM238 Chipset. The Express-KL2 supports all Type 2 legacy I/O as well as Windows 10 operating systems. It is ideally suited for customers who want to extend the production life of existing Type 2 based systems for at least another 10 years.

The Express-KL2 features Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and DDR4 dual-channel memory at 2133/2400 MHz with ECC/non-ECC support dependent on processor/chipset combination to provide excellent overall performance. Intel® Flexible Display Interface and Direct Media Interface provide high speed connectivity to the Mobile Intel® QM175, HM175, CM238 Chipset.

Integrated Intel® Generation 9 Graphics includes features such as OpenGL 4.4/4.3/4.2, DirectX 11, Intel® Clear Video HD Technology, Advanced Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full H.265/HEVC, MPEG2 hardware decode. Graphics outputs include VGA and LVDS.

The Express-KL2 supports a PATA port, 32-bit PCI bus rev 2.3, SATA 6Gb/s ports, a multiplexed PCI Express® x16 graphics bus for discrete graphics expansion or general purpose PCI Express x8 or x4 connectivity, USB 2.0 ports and a single onboard Gigabit Ethernet port. In addition, two DDI channels are supported by build option in place of PCI Express lanes. Support is also provided for SMBus and I²C and the module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, CMOS backup, hardware monitor, and watchdog timer.

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# 2. Specifications

# 2.1. Core System

<table><tr><td>CPU</td><td>7th Generation Intel® CoreTM and Xeon® E3-15xx v6 processors (formerly “Kaby Lake H”)Intel® Xeon® E3-1505M v6 3.0GHz (4.0GHz Turbo), 45W (35W cTDP) (4C/GT2)Intel® Xeon® E3-1505L v5 2.2GHz (3.0GHz Turbo), 25W (4C/GT2)Intel® CoreTM i7-7820EQ 3.0GHz (3.7GHz Turbo), 45W (35W cTDP) (4C/GT2)Intel® CoreTM i5-7440EQ 2.9GHz (3.6GHz Turbo), 45W (35W cTDP) (4C/GT2)Intel® CoreTM i5-7442EQ 2.1GHz (2.9GHz Turbo), 25W (4C/GT2)Intel® CoreTM i3-7100E 2.9GHz, 35W (4C/GT2)Intel® CoreTM i3-7102E 2.1GHz, 25W (4C/GT2)Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.0, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure Key, Intel® TSXNINote: Availability of features may vary between processor SKUs.</td></tr><tr><td>Cache</td><td>8MB for Xeon®/CoreTM i7, 6MB for CoreTM i5, 3MB for CoreTM i3</td></tr><tr><td>Memory</td><td>Dual channel non-ECC/ECC 2133/2400 MHz DDR4 memory up to 32GB in dual stacked SODIMM socket</td></tr><tr><td>Chipset</td><td>Mobile Intel® QM175, HM175 and CM238 Chipset (HM175 does not support Intel® AMT)CoreTM i7/i5 with QM175 Chipset (non-ECC memory support)CoreTM i3 with HM175 Chipset (non-ECC memory support)Xeon® with CM238 Chipset (ECC and non-ECC memory support)CoreTM i3 with CM238 Chipset (ECC and non-ECC memory support, by project basis)</td></tr><tr><td>BIOS</td><td>AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 11 support (AMT not supported by HM175)</td></tr></table>

# 2.2. Expansion Busses

<table><tr><td>PCI Express</td><td>PCI Express x16 Gen3( or 2 x8, or 1 x8 and 2 x4)6 PCI Express x1 (AB): Lanes 0/1/2/3/4/5PCI: 32-bit PCI bus, rev 2.3 (via PCIe-to-PCI chip)</td></tr><tr><td>Other</td><td>LPC busSMBus (system) $I^{2}C$  (user)</td></tr></table>

# 2.3. Video

<table><tr><td>Integrated on Processor</td><td>Intel® Generation 9 Graphics core architecture</td></tr><tr><td>GPU Feature Support</td><td>2 independent and simultaneous display combinations of VGA / LVDS monitorsEncode/transcode HD contentPlayback of Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D)DirectX Video Acceleration (DXVA) support for accelerated video processingHEVC/H.265, H.264, M/JPEG, MPEG2, VC1, WMV9, VP8/VP9 HW decodeHEVC/H.265, M/JPEG, MPEG2 HW encodeAdvanced Scheduler 2.0, 1.0, XPDM supportDirectX 12, DirectX 11.3, DirectX 11, DirectX 10.1, DirectX 10, DirectX 9 supporOpenGL up to 4.4, OpenCL up to 2.1 supportNote:Availability of features s dependent on OS (Win 10/8.1/7, Linux, VxWorks)</td></tr><tr><td>Multi Display Support</td><td>2 independent displays</td></tr><tr><td>Display Interface Support</td><td>VGA Interfacesupport through DP-to-VGA chipLVDS Interfacesingle/dual channel 18/24-bit LVDS through eDP-to-LVDS chip;supports DE mode and Hsync/Vsync mode; max. resolution 1920x1200 @60Hz in dual mode; pixel clock frequency up to 112MHz; VESA and JEIDA panel data formats supportedDigital Display Interfacesupport in place of PEG lanes (by build option, max. two DDI channels)</td></tr></table>

# 2.4. Audio

<table><tr><td>Integrated</td><td>Intel® HD Audio integrated in QM175/HM175/CM238 Chipset</td></tr><tr><td>Codec</td><td>Located on Express-BASE carrier (Realtek ALC886)</td></tr></table>

# 2.5. LAN

<table><tr><td>Integrated</td><td>MAC integrated in QM175/HM175/CM238 Chipset</td></tr><tr><td>Intel PHY</td><td>Intel® Ethernet Connection I219LM or I219V (only LM supports Intel® AMT)</td></tr><tr><td>Interface</td><td>10/100/1000 Mbit/s GbE connection</td></tr></table>

# 2.6. Multi I/O and Storage

<table><tr><td>Integrated</td><td>Intel® QM175/HM175/CM238 Chipset</td></tr><tr><td>USB</td><td>8x USB 2.0 (USB 0-7)</td></tr><tr><td>SATA*</td><td>3x SATA 6Gb/s (SATA 0-2)</td></tr><tr><td>PATA</td><td>1x PATA IDE (via SATA-to-PATA bridge), Master only</td></tr><tr><td>GPIO</td><td>4 GPO and 4 GPI with interrupt</td></tr></table>

\*Note: Fourth SATA port (SATA 3) supported by build option in place of PATA

# 2.7. Trusted Platform Module (TPM)

● Chipset: Infineon SLB 9665XT2.0
- Version: TPM 2.0

# 2.8. SEMA Board Controller

● Type: ADLINK Smart Embedded Management Agent (SEMA)
- Functions:

• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and forensic information
- Flat panel control
- General purpose I2C
- Failsafe BIOS (dual BIOS by build option)
• Watchdog timer and fan control

# 2.9. Debug

- 40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
- 60-pin XDP header for ICE debug of CPU/chipset

# 2.10. Power Specifications

<table><tr><td>Power Modes</td><td>AT and ATX mode (AT mode startup controlled by SEMA Board Controller)</td></tr><tr><td>Standard Voltage Input</td><td>ATX: 12V±5% / 5Vsb ±5%; or AT: 12V±5%</td></tr><tr><td>Wide Voltage Input</td><td>ATX: 8.5-20V, 5Vsb ±5%; or AT: 8.5-20V</td></tr><tr><td>Power Management</td><td>ACPI 5.0 compliant, Smart Battery support</td></tr><tr><td>Power States</td><td>Supports C1-C6, S0, S3, S4, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)</td></tr></table>

# 2.11. Power Consumption

Please contact your ADLINK representative for the document "COM Express Module Power Consumption".

# 2.12. Operating Temperatures

<table><tr><td>Standard Operating Temperature</td><td>0°C to +60°C (Wide Voltage Input)Storage: -20°C to +80°C</td></tr><tr><td>Extreme Rugged Operating Temperature (optional)</td><td>-40°C to +85°C (Standard Voltage Input, only select CPU SKUs by project basis)Storage: -40°C to +85°C</td></tr></table>

# 2.13. Environmental

<table><tr><td>Humidity</td><td>Operating: 5-90% RH, non-condensingStorage: 5-95% RH (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr></table>

# 2.14. Specification Compliance

● PICMG COM.0: Rev 2.1 Type 2, Basic size 125 x 95 mm

# 2.15. Operating Systems

<table><tr><td>Standard Support</td><td>• Windows 10 64-bit• Yocto based Linux 64-bit</td></tr><tr><td>Extended Support (BSP)</td><td>• Yocto based Linux• VxWorks</td></tr></table>

# 2.16. Functional Diagram

![Based on the provided flowchart, here is an accurate and concise description of the labeled blocks and their connections.\n\n**Labeled Blocks:**\n*   SODIMM 1 2133/2400 MHz DDR4\n*   SODIMM 2 2133/2400 MHz DDR4\n*   eDP - LVDS\n*   DP-to-VGA\n*   Mobile 7th Gen Intel® Xeon® Intel® Core™ Intel® Celeron® Processor ('Kaby Lake H')\n*   Switch PEG or DDI\n*   PEG or DDI 1 DDI 2\n*   Mobile Intel® QM175/HM175/CM238 Chipset\n*   GBe i219 LM/V\n*   PCIe-to-PCI\n*   SATA-to-PATA\n*   TPM 2.0\n*   GPIO\n*   New SEMA BMC\n*   SPI 0 BIOS\n*   SPI 1 BIOS\n*   Thermal Sensor\n\n**Connections:**\n\n**From the Processor:**\n*   **To Memory:** Arrows connect from the Processor block to 'SODIMM 1 2133/2400 MHz DDR4' and 'SODIMM 2 2133/2400 MHz DDR4'.\n*   **To Display/Video:**\n    *   A connection labeled 'eDP x2' goes to 'eDP - LVDS'. A dashed box around this block is labeled 'eDP x4'. An arrow labeled 'single/dual 18/24 bit LVDS' points left from 'eDP - LVDS'.\n    *   An arrow labeled 'VGA' connects from the Processor to 'DP-to-VGA'.\n*   **To Switch:** Three lines connect from the Processor to 'Switch PEG or DDI':\n    *   'PCIe x16 Gen3 1 x16, 2 x8, or 1 x8 + 2 x4'\n    *   'DDI 1 DP/HDMI/DVI'\n    *   'DDI 2 DP/HDMI/DVI'\n*   **To Chipset:** A large double-headed arrow labeled 'DMI' connects the Processor to the 'Mobile Intel® QM175/HM175/CM238 Chipset'.\n*   **To Output:** An arrow connects 'Switch PEG or DDI' to the block 'PEG or DDI 1 DDI 2'.\n\n**From the Chipset:**\n*   **To GBe:** An arrow labeled 'PCIe x1' connects 'GBe i219 LM/V' to the Chipset.\n*   **To PCIe/PCI Bridge:** A line labeled 'PCIe' connects the Chipset to 'PCIe-to-PCI', which outputs 'PCI' to the 'CD' column.\n*   **To SATA/PATA Bridge:** A line labeled 'SATA' connects the Chipset to 'SATA-to-PATA', which outputs 'PATA' to the 'CD' column.\n*   **To TPM:** A line labeled 'LPC bus' connects the Chipset to 'TPM 2.0'.\n*   **To BMC:** A line labeled 'SMBus' connects the Chipset to 'New SEMA BMC'.\n*   **To Left Side (AB Column):** Multiple bidirectional arrows connect the Chipset to the left side, labeled:\n    *   '6x PCIe x1 Gen3 (port 0-5)'\n    *   '3x SATA 6Gb/s (port 0/1/2)'\n    *   '1x SATA 6Gb/s (port 3)' (dashed line)\n    *   '8x USB 2.0'\n    *   'HD Audio'\n    *   'SMBus'\n    *   '4GPI, 4GPO'\n    *   'GP I2C'\n    *   'DDC I2C'\n    *   'SPI_CS#'\n    *   'SPI'\n\n**From New SEMA BMC:**\n*   Lines connect 'New SEMA BMC' to 'SPI 0 BIOS', 'SPI 1 BIOS', and 'Thermal Sensor'.\n*   A line connects 'New SEMA BMC' to 'GPIO'.\n\n**From GPIO:**\n*   A line connects 'GPIO' to the 'SMBus' line.\n*   A line labeled '4GPI, 4GPO' connects 'GPIO' to the left side (AB column).](.express-kl2-50-1j101-1000-10/527c77392488eb9104c8249fa8dfed70ed0be9ad86b4dbb26066591db368c00c.jpg)

Figure 1: Express-KL2 Functional Block Diagram

# 2.17. Mechanical Drawing

![| Section         | Dimension | Value |\n|-----------------|-----------|-------|\n| Top View        | Top View  | 95    |\n| Top View        | Top View  | 91    |\n| Top View        | Top View  | 81.79 |\n| Top View        | Side View | 2     |\n| Side View       | Side View | 2     |\n| Top View        | Connector on bottom side | 27.94 |\n| Side View       | Connector on bottom side | 18    |\n| Side View       | Connector on bottom side | 6     |\n| Side View       | Connector on bottom side | 4     |\n| Side View       | Connector on bottom side | 0     |\n| Side View       | Connector on bottom side | 0     |\n| Side View       | Connector on bottom side | 16.50 |\n| Side View       | Connector on bottom side | 46.61 |\n| Side View       | Connector on bottom side | 70.13 |\n| Side View       | Connector on bottom side | 74.20 |\n| Side View       | Connector on bottom side | 80    |\n| Side View       | Side View  | 4     |\n| Side View       | Side View  | 8     |\n| Side View       | Side View  | 4     |](.express-kl2-50-1j101-1000-10/0fb99d8d1bb73b3142720654f34861b94816c158b8530c9e5ba38d32b75802e1.jpg)

All are dimensions shown in millimeters.

Tolerances should be $\pm0.25mm\ (\pm0.010"$ ), unless otherwise noted. The tolerances of the module connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00]) should be $\pm0.10mm\ (\pm0.004"$ ).

Figure 2: Express-KL2 Mechanical Drawing

# 3. Pinouts and Signal Descriptions

# 3.1. AB/CD Pin Definitions

The Express-KL2 is a Type 2 module supporting PCI and PATA on the CD connector. All pins in the COM Express specification are described, including those not supported on the Express-KL2. Those not supported on the Express-KL2 module are crossed out.

Table 1: Express-KL2 AB/CD Pin Definitions

<table><tr><td colspan="2">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td colspan="2">Row D</td></tr><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td></tr><tr><td>A1</td><td>GND (FIXED)</td><td>B1</td><td>GND (FIXED)</td><td>C1</td><td>GND (FIXED)</td><td>D1</td><td>GND (FIXED)</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td>B2</td><td>GBE0_ACT#</td><td>C2</td><td>IDE_D7</td><td>D2</td><td>IDE_D5</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td>B3</td><td>LPC_FRAME#</td><td>C3</td><td>IDE_D6</td><td>D3</td><td>IDE_D10</td></tr><tr><td>A4</td><td>GBE0_LINK100#</td><td>B4</td><td>LPC_AD0</td><td>C4</td><td>IDE_D3</td><td>D4</td><td>IDE_D11</td></tr><tr><td>A5</td><td>GBE0_LINK1000#</td><td>B5</td><td>LPC_AD1</td><td>C5</td><td>IDE_D15</td><td>D5</td><td>IDE_D12</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td>B6</td><td>LPC_AD2</td><td>C6</td><td>IDE_D8</td><td>D6</td><td>IDE_D4</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td>B7</td><td>LPC_AD3</td><td>C7</td><td>IDE_D9</td><td>D7</td><td>IDE_D0</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td>B8</td><td>LPC_DRQ0#</td><td>C8</td><td>IDE_D2</td><td>D8</td><td>IDE_REQ</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td>B9</td><td>LPC_DRQ1#</td><td>C9</td><td>IDE_D13</td><td>D9</td><td>IDE_IOW#</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td>B10</td><td>LPC_CLK</td><td>C10</td><td>IDE_D1</td><td>D10</td><td>IDE_ACK#</td></tr><tr><td>A11</td><td>GND (FIXED)</td><td>B11</td><td>GND (FIXED)</td><td>C11</td><td>GND (FIXED)</td><td>D11</td><td>GND (FIXED)</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td>B12</td><td>PWRBTN#</td><td>C12</td><td>IDE_D14</td><td>D12</td><td>IDE_IRQ</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td>B13</td><td>SMB_CK</td><td>C13</td><td>IDE_IORDY</td><td>D13</td><td>IDE_A0</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td>B14</td><td>SMB_DAT</td><td>C14</td><td>IDE_IOR#</td><td>D14</td><td>IDE_A1</td></tr><tr><td>A15</td><td>SUS_S3#</td><td>B15</td><td>SMB_ALERT#</td><td>C15</td><td>PCI_PME#</td><td>D15</td><td>IDE_A2</td></tr><tr><td>A16</td><td>SATA0_TX+</td><td>B16</td><td>SATA1_TX+</td><td>C16</td><td>PCI_GNT2#</td><td>D16</td><td>IDE_CS1#</td></tr><tr><td>A17</td><td>SATA0_TX-</td><td>B17</td><td>SATA1_TX-</td><td>C17</td><td>PCI_REQ2#</td><td>D17</td><td>IDE_CS3#</td></tr><tr><td>A18</td><td>SUS_S4#</td><td>B18</td><td>SUS_STAT#</td><td>C18</td><td>PCI_GNT1#</td><td>D18</td><td>IDE_RESET#</td></tr><tr><td>A19</td><td>SATA0_RX+</td><td>B19</td><td>SATA1_RX+</td><td>C19</td><td>PCI_REQ1#</td><td>D19</td><td>PCI_GNT3#</td></tr><tr><td>A20</td><td>SATA0_RX-</td><td>B20</td><td>SATA1_RX-</td><td>C20</td><td>PCI_GNT0#</td><td>D20</td><td>PCI_REQ3#</td></tr><tr><td>A21</td><td>GND (FIXED)</td><td>B21</td><td>GND (FIXED)</td><td>C21</td><td>GND (FIXED)</td><td>D21</td><td>GND (FIXED)</td></tr><tr><td>A22</td><td>SATA2_TX+</td><td>B22</td><td>SATA3_TX+ *</td><td>C22</td><td>PCI_REQ0#</td><td>D22</td><td>PCI_AD1</td></tr><tr><td>A23</td><td>SATA2_TX-</td><td>B23</td><td>SATA3_TX *</td><td>C23</td><td>PCI_RESET#</td><td>D23</td><td>PCI_AD3</td></tr><tr><td>A24</td><td>SUS_S5#</td><td>B24</td><td>PWR_OK</td><td>C24</td><td>PCI_AD0</td><td>D24</td><td>PCI_AD5</td></tr><tr><td>A25</td><td>SATA2_RX+</td><td>B25</td><td>SATA3_RX+ *</td><td>C25</td><td>PCI_AD2</td><td>D25</td><td>PCI_AD7</td></tr><tr><td>A26</td><td>SATA2_RX-</td><td>B26</td><td>SATA3_RX *</td><td>C26</td><td>PCI_AD4</td><td>D26</td><td>PCI_C/BE0#</td></tr><tr><td>A27</td><td>BATLOW#</td><td>B27</td><td>WDT</td><td>C27</td><td>PCI_AD6</td><td>D27</td><td>PCI_AD9</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td>B28</td><td>AC/HDA_SDIN2</td><td>C28</td><td>PCI_AD8</td><td>D28</td><td>PCI_AD11</td></tr><tr><td>A29</td><td>AC/HDA_SYNC</td><td>B29</td><td>AC/HDA_SDIN1</td><td>C29</td><td>PCI_AD10</td><td>D29</td><td>PCI_AD13</td></tr><tr><td>A30</td><td>AC/HDA_RST#</td><td>B30</td><td>AC/HDA_SDINO</td><td>C30</td><td>PCI_AD12</td><td>D30</td><td>PCI_AD15</td></tr><tr><td>A31</td><td>GND (FIXED)</td><td>B31</td><td>GND (FIXED)</td><td>C31</td><td>GND (FIXED)</td><td>D31</td><td>GND (FIXED)</td></tr><tr><td>A32</td><td>AC/HDA_BITCLK</td><td>B32</td><td>SPKR</td><td>C32</td><td>PCI_AD14</td><td>D32</td><td>PCI_PAR</td></tr><tr><td>A33</td><td>AC/HDA_SDOUT</td><td>B33</td><td>I2C_CK</td><td>C33</td><td>PCI_C/BE1#</td><td>D33</td><td>PCI_SERR#</td></tr><tr><td>A34</td><td>BIOS_DISO#</td><td>B34</td><td>I2C_DAT</td><td>C34</td><td>PCI_PERR#</td><td>D34</td><td>PCI_STOP#</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td>B35</td><td>THRM#</td><td>C35</td><td>PCI_LOCK#</td><td>D35</td><td>PCI_TRDY#</td></tr></table>

Row A
Row B
Row C
Row D

<table><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td></tr><tr><td>A36</td><td>USB6-</td><td>B36</td><td>USB7-</td><td>C36</td><td>PCI_DEVSEL#</td><td>D36</td><td>PCI_FRAME#</td></tr><tr><td>A37</td><td>USB6+</td><td>B37</td><td>USB7+</td><td>C37</td><td>PCIIRDY#</td><td>D37</td><td>PCI_AD16</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td>B38</td><td>USB_4_5_OC#</td><td>C38</td><td>PCI_C/BE2#</td><td>D38</td><td>PCI_AD18</td></tr><tr><td>A39</td><td>USB4-</td><td>B39</td><td>USB5-</td><td>C39</td><td>PCI_AD17</td><td>D39</td><td>PCI_AD20</td></tr><tr><td>A40</td><td>USB4+</td><td>B40</td><td>USB5+</td><td>C40</td><td>PCI_AD19</td><td>D40</td><td>PCI_AD22</td></tr><tr><td>A41</td><td>GND (FIXED)</td><td>B41</td><td>GND (FIXED)</td><td>C41</td><td>GND (FIXED)</td><td>D41</td><td>GND (FIXED)</td></tr><tr><td>A42</td><td>USB2-</td><td>B42</td><td>USB3-</td><td>C42</td><td>PCI_AD21</td><td>D42</td><td>PCI_AD24</td></tr><tr><td>A43</td><td>USB2+</td><td>B43</td><td>USB3+</td><td>C43</td><td>PCI_AD23</td><td>D43</td><td>PCI_AD26</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td>B44</td><td>USB_0_1_OC#</td><td>C44</td><td>PCI_C/BE3#</td><td>D44</td><td>PCI_AD28</td></tr><tr><td>A45</td><td>USB0-</td><td>B45</td><td>USB1-</td><td>C45</td><td>PCI_AD25</td><td>D45</td><td>PCI_AD30</td></tr><tr><td>A46</td><td>USB0+</td><td>B46</td><td>USB1+</td><td>C46</td><td>PCI_AD27</td><td>D46</td><td>PCI_IRQC#</td></tr><tr><td>A47</td><td>VCC_RTC</td><td>B47</td><td>EXCD1_PERST#</td><td>C47</td><td>PCI_AD29</td><td>D47</td><td>PCI_IRQD#</td></tr><tr><td>A48</td><td>EXCD0_PERST #</td><td>B48</td><td>EXCD1_CPPE#</td><td>C48</td><td>PCI_AD31</td><td>D48</td><td>PCI_CLKRUN#</td></tr><tr><td>A49</td><td>EXCD0_CPPE#</td><td>B49</td><td>SYS_RESET#</td><td>C49</td><td>PCI_IRQA#</td><td>D49</td><td>PCI_M66EN GND)</td></tr><tr><td>A50</td><td>LPC_SERIRQ</td><td>B50</td><td>CB_RESET#</td><td>C50</td><td>PCI_IRQB#</td><td>D50</td><td>PCI_CLK</td></tr><tr><td>A51</td><td>GND (FIXED)</td><td>B51</td><td>GND (FIXED)</td><td>C51</td><td>GND (FIXED)</td><td>D51</td><td>GND (FIXED)</td></tr><tr><td>A52</td><td>PCIE_TX5+</td><td>B52</td><td>PCIE_RX5+</td><td>C52</td><td>PEG_RX0+</td><td>D52</td><td>PEG_TX0+</td></tr><tr><td>A53</td><td>PCIE_TX5-</td><td>B53</td><td>PCIE_RX5-</td><td>C53</td><td>PEG_RX0-</td><td>D53</td><td>PEG_TX0-</td></tr><tr><td>A54</td><td>GPIO</td><td>B54</td><td>GPO1</td><td>C54</td><td>TYPE0#</td><td>D54</td><td>PEG_LANE_RV #</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td>B55</td><td>PCIE_RX4+</td><td>C55</td><td>PEG_RX1+</td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td>B56</td><td>PCIE_RX4-</td><td>C56</td><td>PEG_RX1-</td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td>B57</td><td>GPO2</td><td>C57</td><td>TYPE1#</td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td>B58</td><td>PCIE_RX3+</td><td>C58</td><td>PEG_RX2+</td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td>B59</td><td>PCIE_RX3-</td><td>C59</td><td>PEG_RX2-</td><td>D59</td><td>PEG_TX2-</td></tr><tr><td>A60</td><td>GND (FIXED)</td><td>B60</td><td>GND (FIXED)</td><td>C60</td><td>GND (FIXED)</td><td>D60</td><td>GND (FIXED)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td>B61</td><td>PCIE_RX2+</td><td>C61</td><td>PEG_RX3+</td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td>B62</td><td>PCIE_RX2-</td><td>C62</td><td>PEG_RX3-</td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1</td><td>B63</td><td>GPO3</td><td>C63</td><td>RSVD</td><td>D63</td><td>RSVD</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td>B64</td><td>PCIE_RX1+</td><td>C64</td><td>RSVD</td><td>D64</td><td>RSVD</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td>B65</td><td>PCIE_RX1-</td><td>C65</td><td>PEG_RX4+</td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td>B66</td><td>WAKE0#</td><td>C66</td><td>PEG_RX4-</td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2</td><td>B67</td><td>WAKE1#</td><td>C67</td><td>RSVD</td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td>B68</td><td>PCIE_RX0+</td><td>C68</td><td>PEG_RX5+</td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td>B69</td><td>PCIE_RX0-</td><td>C69</td><td>PEG_RX5-</td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND (FIXED)</td><td>B70</td><td>GND (FIXED)</td><td>C70</td><td>GND (FIXED)</td><td>D70</td><td>GND (FIXED)</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td>B71</td><td>LVDS_B0+</td><td>C71</td><td>PEG_RX6+</td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td>B72</td><td>LVDS_B0-</td><td>C72</td><td>PEG_RX6-</td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td>B73</td><td>LVDS_B1+</td><td>C73</td><td>SDVO_DATA</td><td>D73</td><td>SDVO_CLK</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td>B74</td><td>LVDS_B1-</td><td>C74</td><td>PEG_RX7+</td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td>B75</td><td>LVDS_B2+</td><td>C75</td><td>PEG_RX7-</td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td>B76</td><td>LVDS_B2-</td><td>C76</td><td>GND</td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td>B77</td><td>LVDS_B3+</td><td>C77</td><td>RSVD</td><td>D77</td><td>IDE_CBLID#</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>B78</td><td>LVDS_B3-</td><td>C78</td><td>PEG_RX8+</td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>B79</td><td>LVDS_BKLT_EN</td><td>C79</td><td>PEG_RX8-</td><td>D79</td><td>PEG_TX8-</td></tr><tr><td>A80</td><td>GND (FIXED)</td><td>B80</td><td>GND (FIXED)</td><td>C80</td><td>GND (FIXED)</td><td>D80</td><td>GND (FIXED)</td></tr></table>

<table><tr><td colspan="3">Row A</td><td colspan="2">Row B</td><td colspan="3">Row C</td><td>Row D</td></tr><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td><td>Pin</td><td>Pin Name</td><td></td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td>B81</td><td>LVDS_B_CK+</td><td>C81</td><td>PEG_RX9+</td><td>D81</td><td>PEG_TX9+</td><td></td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td>B82</td><td>LVDS_B_CK-</td><td>C82</td><td>PEG_RX9-</td><td>D82</td><td>PEG_TX9-</td><td></td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td>B83</td><td>LVDS_BKLT_CTRL</td><td>C83</td><td>RSVD</td><td>D83</td><td>RSVD</td><td></td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td>B84</td><td>VCC_5V_SBY</td><td>C84</td><td>GND</td><td>D84</td><td>GND</td><td></td></tr><tr><td>A85</td><td>GPI3</td><td>B85</td><td>VCC_5V_SBY</td><td>C85</td><td>PEG_RX10+</td><td>D85</td><td>PEG_TX10+</td><td></td></tr><tr><td>A86</td><td>KBD_RST#</td><td>B86</td><td>VCC_5V_SBY</td><td>C86</td><td>PEG_RX10-</td><td>D86</td><td>PEG_TX10-</td><td></td></tr><tr><td>A87</td><td>KBD_A20GATE</td><td>B87</td><td>VCC_5V_SBY</td><td>C87</td><td>GND</td><td>D87</td><td>GND</td><td></td></tr><tr><td>A88</td><td>PCIE0_CK_REF+</td><td>B88</td><td>BIOS_DIS1#</td><td>C88</td><td>PEG_RX11+</td><td>D88</td><td>PEG_TX11+</td><td></td></tr><tr><td>A89</td><td>PCIE0_CK_REF-</td><td>B89</td><td>VGA_RED</td><td>C89</td><td>PEG_RX11-</td><td>D89</td><td>PEG_TX11-</td><td></td></tr><tr><td>A90</td><td>GND (FIXED)</td><td>B90</td><td>GND (FIXED)</td><td>C90</td><td>GND (FIXED)</td><td>D90</td><td>GND (FIXED)</td><td></td></tr><tr><td>A91</td><td>SPI_POWER</td><td>B91</td><td>VGA_GRN</td><td>C91</td><td>PEG_RX12+</td><td>D91</td><td>PEG_TX12+</td><td></td></tr><tr><td>A92</td><td>SPI_MISO</td><td>B92</td><td>VGA_BLU</td><td>C92</td><td>PEG_RX12-</td><td>D92</td><td>PEG_TX12-</td><td></td></tr><tr><td>A93</td><td>GPO0</td><td>B93</td><td>VGA_HSYNC</td><td>C93</td><td>GND</td><td>D93</td><td>GND</td><td></td></tr><tr><td>A94</td><td>SPI_CLK</td><td>B94</td><td>VGA_VSYNC</td><td>C94</td><td>PEG_RX13+</td><td>D94</td><td>PEG_TX13+</td><td></td></tr><tr><td>A95</td><td>SPI_MOSI</td><td>B95</td><td>VGA_I2C_CK</td><td>C95</td><td>PEG_RX13-</td><td>D95</td><td>PEG_TX13-</td><td></td></tr><tr><td>A96</td><td>GND</td><td>B96</td><td>VGA_I2C_DAT</td><td>C96</td><td>GND</td><td>D96</td><td>GND</td><td></td></tr><tr><td>A97</td><td>TYPE10#</td><td>B97</td><td>SPI_CS#</td><td>C97</td><td>RSVD</td><td>D97</td><td>PEG_ENABLE#</td><td></td></tr><tr><td>A98</td><td>RSVD</td><td>B98</td><td>RSVD</td><td>C98</td><td>PEG_RX14+</td><td>D98</td><td>PEG_TX14+</td><td></td></tr><tr><td>A99</td><td>RSVD</td><td>B99</td><td>RSVD</td><td>C99</td><td>PEG_RX14-</td><td>D99</td><td>PEG_TX14-</td><td></td></tr><tr><td>A100</td><td>GND (FIXED)</td><td>B100</td><td>GND (FIXED)</td><td>C100</td><td>GND (FIXED)</td><td>D100</td><td>GND (FIXED)</td><td></td></tr><tr><td>A101</td><td>RSVD</td><td>B101</td><td>RSVD</td><td>C101</td><td>PEG_RX15+</td><td>D101</td><td>PEG_TX15+</td><td></td></tr><tr><td>A102</td><td>RSVD</td><td>B102</td><td>RSVD</td><td>C102</td><td>PEG_RX15-</td><td>D102</td><td>PEG_TX15-</td><td></td></tr><tr><td>A103</td><td>RSVD</td><td>B103</td><td>RSVD</td><td>C103</td><td>GND</td><td>D103</td><td>GND</td><td></td></tr><tr><td>A104</td><td>VCC_12V</td><td>B104</td><td>VCC_12V</td><td>C104</td><td>VCC_12V</td><td>D104</td><td>VCC_12V</td><td></td></tr><tr><td>A105</td><td>VCC_12V</td><td>B105</td><td>VCC_12V</td><td>C105</td><td>VCC_12V</td><td>D105</td><td>VCC_12V</td><td></td></tr><tr><td>A106</td><td>VCC_12V</td><td>B106</td><td>VCC_12V</td><td>C106</td><td>VCC_12V</td><td>D106</td><td>VCC_12V</td><td></td></tr><tr><td>A107</td><td>VCC_12V</td><td>B107</td><td>VCC_12V</td><td>C107</td><td>VCC_12V</td><td>D107</td><td>VCC_12V</td><td></td></tr><tr><td>A108</td><td>VCC_12V</td><td>B108</td><td>VCC_12V</td><td>C108</td><td>VCC_12V</td><td>D108</td><td>VCC_12V</td><td></td></tr><tr><td>A109</td><td>VCC_12V</td><td>B109</td><td>VCC_12V</td><td>C109</td><td>VCC_12V</td><td>D109</td><td>VCC_12V</td><td></td></tr><tr><td>A110</td><td>GND (FIXED)</td><td>B110</td><td>GND (FIXED)</td><td>C110</td><td>GND (FIXED)</td><td>D110</td><td>GND (FIXED)</td><td></td></tr></table>

Note: SATA port 3 is supported by build option, in place of PATA port.

# 3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

I Input to the Module

O Output from the Module

I/O Bi-directional input/output signal

OD Open drain output

I 3.3V Input 3.3V tolerant

I 5V Input 5V tolerant

O 3.3V Output 3.3V signal level

O 5V Output 5V signal level

I/O 3.3V Bi-directional signal 3.3V tolerant

I/O 5V Bi-directional signal 5V tolerant

I/O 3.3Vsb Input 3.3V tolerant active in standby state

P Power Input/Output

REF Reference voltage output that may be sourced from a module power plane.

PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected. The signal is used to indicate the PICMG module type to the Carrier Board.

PU ADLINK implemented pull-up resistor on module

PD ADLINK implemented pull-down resistor on module

# 3.3. AB Signal Descriptions

# 3.3.1. Audio Signals

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>AC_RST# / HDA_RST#</td><td>A30</td><td>Reset output to codec, active low.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>AC_SYNC / HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the codec(s).</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>AC_BITCLK / HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external codec(s).</td><td>I/O 3.3V</td><td></td><td></td></tr><tr><td>AC_SDOUT / HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the codec.</td><td>O 3.3V</td><td></td><td>Boot strap pin. No external pull-up orpull-down resistor on carrier board is recommended to avoid changing the configuration of this signal</td></tr><tr><td>AC_SDIN[2:0] HDA_SDIN[2:0]</td><td>B28 B29 B30</td><td>Serial TDM data inputs from up to 3 codecs.</td><td>I/O 3.3VSB</td><td></td><td>AC_SDIN0: supported AC_SDIN1: supported AC_SDIN2: not supported</td></tr></table>

# 3.3.2. Analog VGA

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VGA_RED</td><td>B89</td><td>Red for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD150R</td><td>Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_GRN</td><td>B91</td><td>Green for monitorAnalog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD150R</td><td>Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_BLU</td><td>B92</td><td>Blue for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD150R</td><td>Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_HSYNC</td><td>B93</td><td>Horizontal sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_VSYNC</td><td>B94</td><td>Vertical sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_I2C_CK</td><td>B95</td><td>DDC clock line (I2C port dedicated to identify VGA monitor capabilities)</td><td>I/O OD3.3V</td><td>PU 2k23.3V</td><td></td></tr><tr><td>VGA_I2C_DAT</td><td>B96</td><td>DDC data line.</td><td>I/O OD3.3V</td><td>PU 2k23.3V</td><td></td></tr></table>

# 3.3.3. LVDS

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LVDS_A0+</td><td>A71</td><td rowspan="8">LVDS Channel A differential pairs</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>LVDS_A0-</td><td>A72</td></tr><tr><td>LVDS_A1+</td><td>A73</td></tr><tr><td>LVDS_A1-</td><td>A74</td></tr><tr><td>LVDS_A2+</td><td>A75</td></tr><tr><td>LVDS_A2-</td><td>A76</td></tr><tr><td>LVDS_A3+</td><td>A78</td></tr><tr><td>LVDS_A3-</td><td>A79</td></tr><tr><td>LVDS_A_CK+</td><td>A81</td><td rowspan="2">LVDS Channel A differential clock</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>LVDS_A_CK-</td><td>A82</td></tr><tr><td>LVDS_B0+</td><td>B71</td><td rowspan="8">LVDS Channel B differential pairs</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>LVDS_B0-</td><td>B72</td></tr><tr><td>LVDS_B1+</td><td>B73</td></tr><tr><td>LVDS_B1-</td><td>B74</td></tr><tr><td>LVDS_B2+</td><td>B75</td></tr><tr><td>LVDS_B2-</td><td>B76</td></tr><tr><td>LVDS_B3+</td><td>B77</td></tr><tr><td>LVDS_B3-</td><td>B78</td></tr><tr><td>LVDS_B_CK+</td><td>B81</td><td rowspan="2">LVDS Channel B differential clock</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>LVDS_B_CK-</td><td>B82</td></tr><tr><td>LVDS_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 10K</td><td></td></tr><tr><td>LVDS_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_I2C_CK</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

# 3.3.4. Gigabit Ethernet

<table><tr><td>Gigabit Ethernet</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>GBE0_MDI0+GBE0_MDI0-GBE0_MDI1+GBE0_MDI1-GBE0_MDI2+GBE0_MDI2-GBE0_MDI3+GBE0_MDI3-</td><td>A13A12A10A9A7A6A3A2</td><td>Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following: $\underline{\underline{1000BASE-T}}$   $\underline{100BASE-TX}$   $\underline{10BASE-T}$  $\underline{MDI[0]+/-}$   $\underline{B1_DA+/-}$   $\underline{TX+/-}$   $\underline{TX+/-}$  $\underline{MDI[1]+/-}$   $\underline{B1_DB+/-}$   $\underline{RX+/-}$   $\underline{RX+/-}$  $\underline{MDI[2]+/-}$   $\underline{B1_DC+/-}$  $\underline{MDI[3]+/-}$   $\underline{B1_DD+/-}$ </td><td>I/OAnalog</td><td></td><td>Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td>Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>O3.3VSB</td><td></td><td>Shares same source as A8</td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td>Gigabit Ethernet Controller 0 link indicator, active low.</td><td>O3.3VSB</td><td></td><td>Shares same as B2</td></tr><tr><td>GBE0_LINK100#</td><td>A4</td><td>Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK1000#</td><td>A5</td><td>Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td>Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>GND min 3.3V max</td><td></td><td>NC pin</td></tr></table>

3.3.5. SATA

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX*SATA1_TX-*</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX*SATA1_RX-*</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_TX+SATA2_TX-</td><td>A22A23</td><td>Serial ATA channel 2, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_RX+SATA2_RX-</td><td>A25A26</td><td>Serial ATA channel 2, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA3_TX+SATA3_TX-</td><td>B22B23</td><td>Serial ATA channel 3, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Supported by build option*AC coupled on Module</td></tr><tr><td>SATA3_RX+SATA3_RX-</td><td>B25B26</td><td>Serial ATA channel 3, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Supported by build option*AC coupled on Module</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

Note: SATA 3 port is supported by build option in place of PATA port.

# 3.3.6. PCI Express

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX4+PCIE_TX4-</td><td>A55A56</td><td>PCI Express channel 4, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX4+PCIE_RX4-</td><td>B55B56</td><td>PCI Express channel 4, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX5+PCIE_TX5-</td><td>A52A53</td><td>PCI Express channel 5, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX5+PCIE_RX5-</td><td>B52B53</td><td>PCI Express channel 5, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O PCIE</td><td></td><td></td></tr></table>

# 3.3.7. Express Card

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>EXCD0_CPPE#</td><td>A49</td><td rowspan="2">PCI ExpressCard: PCI Express capable card request</td><td rowspan="2">I 3.3V</td><td>PU 10k</td><td rowspan="2"></td></tr><tr><td>EXCD1_CPPE#</td><td>B48</td><td>3.3V</td></tr><tr><td>EXCD0_PERST#</td><td>A48</td><td rowspan="2">PCI ExpressCard: reset</td><td rowspan="2">O 3.3V</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>EXCD1_PERST#</td><td>B47</td></tr></table>

3.3.8. LPC Bus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LPC_AD[0:3]</td><td>B4-B7</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3V</td><td></td><td>Chipset has internal pull-up</td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>LPC_DRQ0#LPC_DRQ1#</td><td>B8B9</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>Not supported</td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O OD 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3V</td><td></td><td></td></tr></table>

3.3.9. USB

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 1</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 2</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 3</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 4</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 5</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 6</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td>Do not pull high on carrier</td></tr></table>

3.3.10. SPI (BIOS only)

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER.SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>OP3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not-connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not-connected</td></tr></table>

3.3.11. Miscellaneous

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the “speaker” in PC-AT systems</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3V</td><td></td><td></td></tr><tr><td>THERMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3V</td><td></td><td></td></tr></table>

# 3.3.12. SMBus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.</td><td>I/O OD 3.3VSB</td><td>PU 8k2 3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.</td><td>I/O OD 3.3VSB</td><td>PU 8k2 3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 2K2 3.3 VSB</td><td></td></tr></table>

# 3.3.13. I2C Bus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2k2 3.3VSB</td><td>Source SEMA BMC</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2k2 3.3VSB</td><td>Source SEMA BMC</td></tr></table>

# 3.3.14. General Purpose I/O (GPIO)

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

3.3.15. Power and System Management

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.</td><td>O 3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3V</td><td>PU 10k3.3VSB</td><td>Should have weak pull up</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates imminent suspend operation; used to notify LPC devices.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates system is in Suspend to Disk state. Active low output.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates system is in Soft Off state.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake up signal.</td><td>I 3.3VSB</td><td>PU 1K3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 1K3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr></table>

3.3.16. Power and Ground

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104-A109B104-B109</td><td>Primary power input: +12V nominal (wide range 5 ~ 20V).All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20 V</td></tr><tr><td>VCC_5V_S BY</td><td>B84-B87</td><td>Standby power input: +5.0V nominal. See section 7 “Electrical Specifications” for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21,B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 3.4. CD Signal Descriptions

# 3.4.1. PATA IDE

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>IDE_D0</td><td>D7</td><td rowspan="16">Bidirectional data to / from IDE device.</td><td rowspan="16">I/O3.3V</td><td rowspan="16"></td><td rowspan="16">D7 pin has PD 10K</td></tr><tr><td>IDE_D1</td><td>C10</td></tr><tr><td>IDE_D2</td><td>C8</td></tr><tr><td>IDE_D3</td><td>C4</td></tr><tr><td>IDE_D4</td><td>D6</td></tr><tr><td>IDE_D5</td><td>D2</td></tr><tr><td>IDE_D6</td><td>C3</td></tr><tr><td>IDE_D7</td><td>C2</td></tr><tr><td>IDE_D8</td><td>C6</td></tr><tr><td>IDE_D9</td><td>C7</td></tr><tr><td>IDE_D10</td><td>D3</td></tr><tr><td>IDE_D11</td><td>D4</td></tr><tr><td>IDE_D12</td><td>D5</td></tr><tr><td>IDE_D13</td><td>C9</td></tr><tr><td>IDE_D14</td><td>C12</td></tr><tr><td>IDE_D15</td><td>C5</td></tr><tr><td>IDE_A0</td><td>D13</td><td>Address lines to IDE device.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_A1</td><td>D14</td><td>Address lines to IDE device.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_A2</td><td>D15</td><td>Address lines to IDE device.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_IOW#</td><td>D9</td><td>I/O write line to IDE device. Data latched on trailing (rising) edge.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_IOR#</td><td>C14</td><td>I/O read line to IDE device.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_REQ</td><td>D8</td><td>IDE Device DMA Request. It is asserted by the IDE device to request a data transfer.</td><td>I 3.3V</td><td>PD 5K6</td><td></td></tr><tr><td>IDE_ACK#</td><td>D10</td><td>IDE Device DMA Acknowledge.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_CS1#</td><td>D16</td><td>IDE Device Chip Select for 1F0h to 1FFh range.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_CS3#</td><td>D17</td><td>IDE Device Chip Select for 3F0h to 3FFh range.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_IORDY</td><td>C13</td><td>IDE device I/O ready input. Pulled low by the IDE device to extend the cycle.</td><td>I 3.3V</td><td>PU 4k73.3V</td><td></td></tr><tr><td>IDE_RESET#</td><td>D18</td><td>Reset output to IDE device, active low.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>IDE_IRQ</td><td>D12</td><td>Interrupt request from IDE device.</td><td>I 3.3V</td><td>PD 10k</td><td></td></tr><tr><td>IDE_CBLID#</td><td>D77</td><td>Input from off-module hardware indicating the type of IDE cable being used. High indicates a 40-pin cable used for legacy IDE modes. Low indicates that an 80-pin cable with interleaved grounds is used. Such a cable is required for Ultra-DMA 66, 100 and 133 modes.</td><td>I 3.3V</td><td></td><td></td></tr></table>

3.4.2. PCI

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PCI_AD0</td><td>C24</td><td rowspan="32">PCI bus multiplexed address and data lines</td><td rowspan="32">I/O 3.3V</td><td rowspan="32"></td><td rowspan="32"></td></tr><tr><td>PCI_AD1</td><td>D22</td></tr><tr><td>PCI_AD2</td><td>C25</td></tr><tr><td>PCI_AD3</td><td>D23</td></tr><tr><td>PCI_AD4</td><td>C26</td></tr><tr><td>PCI_AD5</td><td>D24</td></tr><tr><td>PCI_AD6</td><td>C27</td></tr><tr><td>PCI_AD7</td><td>D25</td></tr><tr><td>PCI_AD8</td><td>C28</td></tr><tr><td>PCI_AD9</td><td>D27</td></tr><tr><td>PCI_AD10</td><td>C29</td></tr><tr><td>PCI_AD11</td><td>D28</td></tr><tr><td>PCI_AD12</td><td>C30</td></tr><tr><td>PCI_AD13</td><td>D29</td></tr><tr><td>PCI_AD14</td><td>C32</td></tr><tr><td>PCI_AD15</td><td>D30</td></tr><tr><td>PCI_AD16</td><td>D37</td></tr><tr><td>PCI_AD17</td><td>C39</td></tr><tr><td>PCI_AD18</td><td>D38</td></tr><tr><td>PCI_AD19</td><td>C40</td></tr><tr><td>PCI_AD20</td><td>D39</td></tr><tr><td>PCI_AD21</td><td>C42</td></tr><tr><td>PCI_AD22</td><td>D40</td></tr><tr><td>PCI_AD23</td><td>C43</td></tr><tr><td>PCI_AD24</td><td>D42</td></tr><tr><td>PCI_AD25</td><td>C45</td></tr><tr><td>PCI_AD26</td><td>D43</td></tr><tr><td>PCI_AD27</td><td>C46</td></tr><tr><td>PCI_AD28</td><td>D44</td></tr><tr><td>PCI_AD29</td><td>C47</td></tr><tr><td>PCI_AD30</td><td>D45</td></tr><tr><td>PCI_AD31</td><td>C48</td></tr><tr><td>PCI_C/BE0#</td><td>D26</td><td rowspan="4">PCI bus byte enable lines, active low</td><td rowspan="4">I/O 3.3V</td><td rowspan="4"></td><td rowspan="4"></td></tr><tr><td>PCI_C/BE1#</td><td>C33</td></tr><tr><td>PCI_C/BE2#</td><td>C38</td></tr><tr><td>PCI_C/BE3#</td><td>C44</td></tr><tr><td>PCI_DEVSEL#</td><td>C36</td><td>PCI bus Device Select, active low.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_FRAME#</td><td>D36</td><td>PCI bus Frame control line, active low.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCIIRDY#</td><td>C37</td><td>PCI bus Initiator Ready control line, active low.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_TRDY#</td><td>D35</td><td>PCI bus Target Ready control line, active low.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_STOP#</td><td>D34</td><td>PCI bus STOP control line, active low, driven by cycle initiator.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_PAR</td><td>D32</td><td>PCI bus parity</td><td>I/O 3.3V</td><td></td><td></td></tr><tr><td>PCI_PERR#</td><td>C34</td><td>Parity Error:An external PCI device drives PERR# when itreceives data that has a parity error.</td><td>I/O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_REQ0#</td><td>C22</td><td rowspan="4">PCI bus master request input lines, active low.</td><td rowspan="4">I 3.3V</td><td rowspan="4">PU 5K13.3V</td><td rowspan="4"></td></tr><tr><td>PCI_REQ1#</td><td>C19</td></tr><tr><td>PCI_REQ2#</td><td>C17</td></tr><tr><td>PCI_REQ3#</td><td>D20</td></tr><tr><td>PCI_GNT0#PCI_GNT1#PCI_GNT2#PCI_GNT3#</td><td>C20C18C16D19</td><td>PCI bus master grant output lines, active low.</td><td>O 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_RESET#</td><td>C23</td><td>PCI Reset output, active low.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>PCI_LOCK#</td><td>C35</td><td>PCI Lock control line, active low.</td><td>I/O 3.3V</td><td>PU 5k13.3V</td><td></td></tr><tr><td>PCI_SERR#</td><td>D33</td><td>System Error: SERR# may be pulsed active by any PCI device that detects a system error condition.</td><td>I/O 3.3V</td><td>PU 5k13.3V</td><td></td></tr><tr><td>PCI_PME#</td><td>C15</td><td>PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1-S5.</td><td>I3.3VSB</td><td>PU 5K13.3VSB</td><td></td></tr><tr><td>PCI_CLKRUN#</td><td>D48</td><td>Bidirectional pin used to support PCI clock run protocol for mobile systems.</td><td>I/O 3.3V</td><td>PU 10k3.3V</td><td></td></tr><tr><td>PCI_IRQA#PCI_IRQB#PCI_IRQC#PCI_IRQD#</td><td>C49C50D46D47</td><td>PCI interrupt request lines</td><td>I 3.3V</td><td>PU 5K13.3V</td><td></td></tr><tr><td>PCI_CLK</td><td>D50</td><td>PCI 33MHz clock output</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>PCI_M66EN</td><td>D49</td><td>Module input signal indicates whether an off-Module PCI device is capable of 66MHz operation. Pulled to GND by Carrier Board device or by Slot Card if the devices are NOT capable of 66 MHz operation.If the Module is not capable of supporting 66 MHz PCI operation, this input may be a no-connect on the Module.If the Module is capable of supporting 66 MHz PCI operation, and if this input is held low by the Carrier Board, the Module PCI interface shall operate at 33 MHz.</td><td>I 3.3V</td><td>PD 100 ohm</td><td></td></tr></table>

3.4.3. Module Type Definition

<table><tr><td>Signal</td><td>Pin #</td><td colspan="4">Description</td><td>I/O</td><td>Comment</td></tr><tr><td>TYPE0#</td><td>C54</td><td rowspan="2" colspan="4">The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don&#x27;t care (X).</td><td rowspan="3"></td><td rowspan="3">Type 6</td></tr><tr><td>TYPE1#</td><td>C57</td></tr><tr><td>TYPE2#</td><td>D57</td><td>TYPE2#</td><td>TYPE1#</td><td>TYPE0#</td><td></td></tr><tr><td></td><td></td><td>X</td><td>X</td><td>X</td><td>Pinout Type 1</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>NC</td><td>Pinout Type 2</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>GND</td><td>Pinout Type 3 (no IDE)</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>NC</td><td>Pinout Type 4 (no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>GND</td><td>Pinout Type 5 (no IDE, no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td>GND</td><td>NC</td><td>NC</td><td>Pinout Type 6 (no IDE, no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td colspan="4">The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.</td><td></td><td></td></tr></table>

# 3.4.4. Power and Ground

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>C104-C109D104-D109</td><td>Primary power input: +12V nominal (wide range 5 ~ 20V).All available VCC_12V pins on the connector(s) shall be used</td><td>P</td><td></td><td>8.5-20V</td></tr><tr><td>GND</td><td>C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110</td><td>Ground - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to carrier board GND plane.</td><td>P</td><td></td><td></td></tr></table>

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# 4. Connector Pinouts on Module

This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification

# 4.1. Connector, Switch and LED Locations

![BIOS\nDefaults\nReset\nButton\nCD\nAB\n4-pin\nFan\nLED1\nLED2\nLED3\n40-pin\nDebug connector](.express-kl2-50-1j101-1000-10/5c455bf9af398cc922b35a8908dd7d34ed6af38c3fd62d677e32dfdecba0c82c.jpg)

Figure 3: Express-KL2 Connector, Switch and LED Locations

# Express-KL2 and the DB40 Debug Module

For illustration purposes only

![DEV-0007359\nDF26A017\nADLINK\nDEV-0007359\nLF\nExpress-HL-5 300E\n51-772124-0A10\nCF-R-5 344-V\n1250E171928\nADLINK\nSYL-FEBETR\nCE-PBUN\nSUE-54V\nSUE-54V\nSUE-54V\nSUE-54V\nPINS-74V\nCEL-RESETR\n51-75027-0A10\nDB40 00DE LF](.express-kl2-50-1j101-1000-10/dbc6a62621f9f28245e1d0507f2323b6ab54ec2c6039388be31449f8541702bb.jpg)

Figure 4: Express-KL2 and the DB40 Debug Module

# 4.2. 40-pin Debug Connector

FPC Connector Type: FCI 59GF Flex 10042867

Pin Orientation
![Close-up of a green printed circuit board with a black connector and gold contacts, labeled with numbers 1 and 40 (no readable text beyond labels)](.express-kl2-50-1j101-1000-10/d611d3f88a9688c56d1a4c13a414854c7459f10c00059225310d586ea6e5773c.jpg)

40-pin Debug Connector Pin Definition on the COM Express Module

<table><tr><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td></tr><tr><td>40</td><td rowspan="7">SPI Program interface</td><td>VCC_SPI_IN</td><td>SPI Power Input from flash tool to module. HW need add MOS FET to switch SPI power for SPI ROM</td></tr><tr><td>39</td><td>GND</td><td></td></tr><tr><td>38</td><td>SPI_BIOS_CS 0#</td><td></td></tr><tr><td>37</td><td>SPI_BIOS_CS 1#</td><td></td></tr><tr><td>36</td><td>SPI_BIOS_MI SO</td><td></td></tr><tr><td>35</td><td>SPI_BIOS_M OSI</td><td></td></tr><tr><td>34</td><td>SPI_BIOS_CLK</td><td></td></tr><tr><td>33</td><td rowspan="10">LPC Bus</td><td>3V3_LPC</td><td>System power 3.3V provide from COM module</td></tr><tr><td>32</td><td>GND</td><td></td></tr><tr><td>31</td><td>BIOS_DIS0</td><td></td></tr><tr><td>30</td><td>RST#</td><td></td></tr><tr><td>29</td><td>CLK33_LPC</td><td></td></tr><tr><td>28</td><td>LPC_FRAME #</td><td></td></tr><tr><td>27</td><td>LPC_AD3</td><td></td></tr><tr><td>26</td><td>LPC_AD2</td><td></td></tr><tr><td>25</td><td>LPC_AD1</td><td>always power 3.3V provide from COM module</td></tr><tr><td>24</td><td>LPC_AD0</td><td></td></tr><tr><td>23</td><td rowspan="3">BMC Program interface</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td></tr><tr><td>22</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td></tr><tr><td>21</td><td>GND</td><td></td></tr></table>

<table><tr><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td></tr><tr><td>20</td><td rowspan="8">BMC Program interface (cont&#x27;d)</td><td>TXD6</td><td></td></tr><tr><td>19</td><td>RXD6</td><td></td></tr><tr><td>18</td><td>FUMD0</td><td></td></tr><tr><td>17</td><td>RESET_IN#</td><td></td></tr><tr><td>16</td><td>DATA</td><td></td></tr><tr><td>15</td><td>CLK</td><td></td></tr><tr><td>14</td><td>OCD0A</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>13</td><td>OCD0B</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>12</td><td rowspan="7">Test points</td><td>PWRBTN#</td><td></td></tr><tr><td>11</td><td>SYS_RESET#</td><td></td></tr><tr><td>10</td><td>CB_RESET#</td><td></td></tr><tr><td>9</td><td>CB_PWROK</td><td></td></tr><tr><td>8</td><td>SUS_S3#</td><td></td></tr><tr><td>7</td><td>SUS_S4#</td><td></td></tr><tr><td>6</td><td>SUS_S5#</td><td></td></tr><tr><td>5</td><td rowspan="4">BMC Debug signals</td><td>POSTWDT_DIS #</td><td>Connect to Jumper for Debug</td></tr><tr><td>4</td><td>SEL_BIOS</td><td>Connect to Jumper for Debug</td></tr><tr><td>3</td><td>BIOS_MODE</td><td>Connect to Jumper for Debug</td></tr><tr><td>2</td><td>BMC_STATUS</td><td></td></tr><tr><td>1</td><td>Reserved</td><td></td><td></td></tr></table>

Table 2: 40-pin Debug Connector Pin Definition

Note: The pin definition on the debug module is the inverse of that on the COM Express module.

# 4.3. Status LEDs

To facilitate easier maintenance, status LED's are mounted on the board.

![Close-up of a green printed circuit board with integrated circuits and connectors (no visible text or symbols)](.express-kl2-50-1j101-1000-10/2aaa836e35ab83b845845e6690e91ac35cd94b622c35bf3d67d5b8b079095702.jpg)

LED1 LED2 LED3

LED Descriptions

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC output</td><td>Power Sequence Status Code (BMC)Power Changes, RESET(see 5.1.4 Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>BMC output and same signal as WDT (B27) on BtB connector</td><td>Module power up LED OFFWatchdog counting Keep Last StateWatchdog timed out LED ONWatchdog RESET LED ONRebooted after WD RESET LED ONRebooted after PWRBTN LED OFFRebooted after RESET BTN LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

Table 3: Express-KL2 LED Descriptions

# 4.4. Fan Connector

Connector Type: JVE 24W1125A-04M00

Pin Orientation
![Close-up of a green printed circuit board with electronic components and a circular connector (no visible text or symbols)](.express-kl2-50-1j101-1000-10/1560edce9920584cb5811dbbdfaa4d62c31245c27df5bad5adac6de8595ac5af.jpg)

Pin Assignment

<table><tr><td>Name</td><td>Description</td></tr><tr><td>1</td><td>FAN_PWMOUT</td></tr><tr><td>2</td><td>FAN_TACHIN</td></tr><tr><td>3</td><td>Ground</td></tr><tr><td>4</td><td>5V</td></tr></table>

Table 4: Fan Connector Pin Definition

# 4.5. BIOS Setup Defaults Reset Button

![Close-up of a green printed circuit board with electronic components and a circular component (no visible text or symbols)](.express-kl2-50-1j101-1000-10/254ee7997411f874af4571a31bf3f5dece27914758dc4f697e457a37d5d3c62a.jpg)

To perform a hardware reset of BIOS default settings, perform the following steps:

1. Shut down the system.
2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears
3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.express-kl2-50-1j101-1000-10/1c59fef0be00c82b6db32775ec06f974df5b41b2e050d6eb4e1cab5518ebc410.jpg)

# 4.6. Switch Settings

# Switch Locations

![BIOS Select and Mode Configuration Switch\nPCI Express Configuration Switch](.express-kl2-50-1j101-1000-10/7177dfa12fcef5da7b5d80981f445f8e120e5ff1434a90ba0c40ef0ba4892ec2.jpg)

Figure 5: cExpress Switch Locations

# 4.6.1. PCI Express Configuration Switch.

The PCI Express Configuration Switch allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>1x PCIe x16 (default)</td><td>Off</td><td>Off</td></tr><tr><td>2x PCIe x8</td><td>On</td><td>Off</td></tr><tr><td>1x PCIe x8 + 2x PCIe x4</td><td>On</td><td>On</td></tr><tr><td>Reserved</td><td>Off</td><td>On</td></tr></table>

Table 5: PCI Express Configuration Switch Settings

# 4.6.2. BIOS Select and Mode Configuration Switch

The module has two BIOS chips and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2.

Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.

In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (default)</td><td>On</td><td>—</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>—</td></tr><tr><td>Set BIOS to PICMG mode</td><td>—</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode (default)</td><td>—</td><td>Off</td></tr></table>

Table 6: BIOS Select and Mode Configuration Switch Settings

# 4.7. PCIe x16-to-two-x8 Adapter Card

The Express-KL2 can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE Reference Carrier to support bifurbication of the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards with x8/x4/x2/x1 width. To use the card, set SW1 to "2 x8 PCI Express" as above.

![Green electronic circuit board with black plastic components and gold contacts (no visible text or symbols)](.express-kl2-50-1j101-1000-10/7cda6536570ce9c2d5df4376cdb6da46788b04433472f4967bc6f39f748ed7ee.jpg)

PClex16-to-two-x8 Adapter Card
(Model: P16TO28, Part No.: 91-79301-0010)

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# 5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented:

• Total operating hours counter. Counts the number of hours the module has been run in minutes.
- On-time minutes counter. Counts the seconds since last system start.
- Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash.
• Power cycles counter
- Boot counter. Counts the number of boot attempts.
- Watchdog Timer. Set/Reset/Disable Watchdog Timer. Features auto-reload at power-up.
• System Restart Cause. Power loss/BIOS Fail/Watchdog/Internal Reset/External Reset
- Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS.
• Flash area. 1kB Flash area for customer data
• 2K Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
• Board Identify. Vendor/Board/Serial number/Production Date
• Main-current & voltage. Monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/sema/.

# 5.1. Board Specific SEMA Functions

# 5.1.1. Voltages

The BMC of the Express-KL2 implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>VCORE</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>1</td><td>VGFX</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>2</td><td>VMEM</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>3</td><td>5VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>4</td><td>RTC</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>5</td><td>VIN</td><td>(MSB&lt;&lt;8 + LSB) x 6.000 x 3.3 / 1024</td></tr><tr><td>6</td><td>5V</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>7</td><td>3.3V</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>8</td><td>3.3VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>9</td><td>(MAIN CURRENT)</td><td>Use Main Current Function</td></tr></table>

Table 7: SEMA Onboard Voltage Monitor

# 5.1.2. Main Current

The BMC of the Express-KL2 implements a current monitor. The current can be read by calling the SEMA function "Get Main Current". The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) \times 8. 0 6 \mathrm{mA}
$$

# 5.1.3. BMC Status

This register shows the status of BMC controlled signals on the Express-KL2.

&lt;table&gt;<tr><td>Status Bit</td><td>Signal</td></tr><tr><td>0</td><td>WDT_OUT</td></tr><tr><td>1</td><td>LVDS_VDDEN</td></tr><tr><td>2</td><td>LVDS_BKLTEN</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>POSTWDT_DISn</td></tr><tr><td>5</td><td>SEL_BIOS</td></tr><tr><td>6</td><td>BIOS_DIS0n</td></tr><tr><td>7</td><td>BIOS_DIS1n</td></tr></table>

Table 8: SEMA BMC Status

# 5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>NO_CB_PWRGD</td></tr><tr><td>7</td><td>BIOS_FAIL</td></tr><tr><td>8</td><td>RESET_FAIL</td></tr><tr><td>9</td><td>RESETIN_FAIL</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>NO_SYS_GD</td></tr><tr><td>14</td><td>NO_3V3_A_PGD</td></tr><tr><td>15</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_P_5V_3V3_S0_PG</td></tr><tr><td>17</td><td>NO_1V0_A_PG</td></tr><tr><td>18</td><td>NO_VCORE_PG</td></tr><tr><td>19</td><td>MEMORY_ERROR</td></tr></table>

Table 9: SEMA Exception Codes

# 5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

<table><tr><td>Bit</td><td>Description</td></tr><tr><td>[0 ~ 4]</td><td>Exception Code</td></tr><tr><td>[6]</td><td>0 = AT mode1 = ATX mode</td></tr><tr><td>[7]</td><td>0 = Standard BIOS1 = Fail-safe BIOS.</td></tr></table>

Table 10: SEMA BMC Flags

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# 6. System Resources

# 6.1. System Memory Map

<table><tr><td>Address Range (decimal)</td><td>Address Range (hex)</td><td>Size</td><td>Description</td></tr><tr><td>(4GB-2MB)</td><td>FFE00000 – FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB-18MB) – (4GB-17MB-1)</td><td>FEE00000 – FEEFFFFF</td><td>1 MB</td><td>MSI Interrupts</td></tr><tr><td>(4GB-20MB) – (4GB-19MB-1)</td><td>FEC00000 – FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB – 16MB</td><td>F00000 – FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>1MB -15MB</td><td>100000 - EFFFFFF</td><td>14 MB</td><td>Main Memory</td></tr><tr><td>0K –1MB</td><td>00000 – FFFFFFF</td><td>1 MB</td><td>DOS Compatibility Memory</td></tr></table>

# 6.2. Direct Memory Access Channels

<table><tr><td>Channel Number</td><td>Data Width</td><td>System Resource</td></tr><tr><td>0</td><td>8-bits</td><td>Generic</td></tr><tr><td>1</td><td>8-bits</td><td>Generic</td></tr><tr><td>2</td><td>8-bits</td><td>Generic</td></tr><tr><td>3</td><td>8-bits</td><td>Generic</td></tr><tr><td>4</td><td></td><td>Reserved - cascade channel</td></tr><tr><td>5</td><td>16-bits</td><td>Generic</td></tr><tr><td>6</td><td>16-bits</td><td>Generic</td></tr><tr><td>7</td><td>16-bits</td><td>Generic</td></tr></table>

# 6.3. I/O Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>20h – 21h</td><td>Interrupt Controller</td></tr><tr><td>24h – 25h</td><td>Interrupt Controller</td></tr><tr><td>28h – 29h</td><td>Interrupt Controller</td></tr><tr><td>2Ch – 2Dh</td><td>Interrupt Controller</td></tr><tr><td>02E-02F</td><td>LPC/eSPI</td></tr><tr><td>30h – 31h</td><td>Interrupt Controller</td></tr><tr><td>34h – 35h</td><td>Interrupt Controller</td></tr><tr><td>38h – 39h</td><td>Interrupt Controller</td></tr><tr><td>3Ch – 3Dh</td><td>Interrupt Controller</td></tr><tr><td>040</td><td>Timer/Counter</td></tr><tr><td>42h – 43h</td><td>Timer/Counter</td></tr><tr><td>4Eh – 4Fh</td><td>LPC/eSPI</td></tr><tr><td>50h</td><td>Timer/Counter</td></tr><tr><td>52h – 53h</td><td>Timer/Counter</td></tr><tr><td>60h</td><td>LPC/eSPI</td></tr><tr><td>61h</td><td>NMI Controller</td></tr><tr><td>62h</td><td>Microcontroller</td></tr><tr><td>63h</td><td>NMI Controller1</td></tr><tr><td>64h</td><td>Microcontroller</td></tr><tr><td>65h</td><td>NMI Controller1</td></tr><tr><td>66h</td><td>Microcontroller</td></tr><tr><td>67h</td><td>NMI Controller1</td></tr><tr><td>70h</td><td>RTC Controller</td></tr><tr><td>71h</td><td>RTC Controller</td></tr><tr><td>72h</td><td>RTC Controller</td></tr><tr><td>73h</td><td>RTC Controller</td></tr><tr><td>74h</td><td>RTC Controller</td></tr><tr><td>75h</td><td>RTC Controller</td></tr><tr><td>76h – 77h</td><td>RTC Controller</td></tr><tr><td>80h</td><td>LPC/eSPI or PCIe</td></tr><tr><td>84h – 86h</td><td>Reserved</td></tr><tr><td>88h</td><td>Reserved</td></tr><tr><td>8Ch – 8Eh</td><td>Reserved</td></tr><tr><td>90h</td><td>(Alias to 80h)</td></tr><tr><td>092</td><td>Reset Generator</td></tr><tr><td>94h – 96h</td><td>(Aliases to 8xh)</td></tr><tr><td>98h</td><td>(Alias to 88h)</td></tr><tr><td>9Ch – 9Eh</td><td>(Alias to 8xh)</td></tr><tr><td>A0h – A1h</td><td>Interrupt Controller</td></tr><tr><td>A4h – A5h</td><td>Interrupt Controller</td></tr><tr><td>A8h – A9h</td><td>Interrupt Controller</td></tr><tr><td>ACh – ADh</td><td>Interrupt Controller</td></tr><tr><td>B0h – B1h</td><td>Interrupt Controller</td></tr><tr><td>B2h – B3h</td><td>Interrupt Controller</td></tr><tr><td>B4h – B5h</td><td>Interrupt Controller</td></tr><tr><td>B8h – B9h</td><td>Interrupt Controller</td></tr><tr><td>BCh – BDh</td><td>Interrupt Controller</td></tr><tr><td>200 – 207h</td><td>Gameport Low</td></tr><tr><td>208–20Fh</td><td>Gameport High</td></tr><tr><td>4D0h – 4D1h</td><td>Interrupt Controller</td></tr><tr><td>CF9h</td><td>Reset Generator</td></tr></table>

# 6.4. Interrupt Request (IRQ) Lines

PIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Parallel Port</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>Generic</td><td>IRQ6 via SERIRQ / PIRQ</td><td>No</td></tr><tr><td>7</td><td>Generic</td><td>IRQ7 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>Generic</td><td>N/A</td><td>Note (1)</td></tr><tr><td>10</td><td>Generic</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>11</td><td>Generic</td><td>IRQ11 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>GSPI, UART, I2C, SDIO</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Gpio</td><td>PIRQ</td><td>Note (1)</td></tr><tr><td>15</td><td>Gpio</td><td>PIRQ</td><td>Note (1)</td></tr></table>

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.
APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 4 (COM4)</td><td>IRQ3 via SERIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 3 (COM3)</td><td>IRQ4 via SERIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port 2 (COM2)</td><td>IRQ5 via SERIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>7</td><td>Serial Port 1 (COM1)</td><td>IRQ7 via SERIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>10</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>11</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Primary IDE controller</td><td>IRQ14 via SERIRQ</td><td>Note (1)</td></tr><tr><td>15</td><td>Secondary IDE controller</td><td>IRQ15 via SERIRQ</td><td>Note (1)</td></tr><tr><td>16</td><td>N/A</td><td>P.E.G Root Port,Intel HDA, PCIE Port 0/1/2/3/4/5/6, I.G.D., XHCI Controller</td><td>Note (1)</td></tr><tr><td>17</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,</td><td>Note (1)</td></tr><tr><td>18</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus Controller</td><td>Note (1)</td></tr><tr><td>19</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,</td><td>Note (1)</td></tr><tr><td>20</td><td>N/A</td><td>Gbe Controller</td><td>Note (1)</td></tr><tr><td>21</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>22</td><td>N/A</td><td>Intel HDA</td><td>Note (1)</td></tr><tr><td>23</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr></table>

6.5. PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel I.G.D.</td></tr><tr><td>00h</td><td>08h</td><td>00h</td><td>Internal</td><td>Gaussian Mixture Model</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>xHCI Controller</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel Management Engine Interface</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Internal</td><td>Intel AHCI controller</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port 1</td></tr><tr><td>00h</td><td>1Ch</td><td>01h</td><td>Internal</td><td>Intel PCI Express Root port 2</td></tr><tr><td>00h</td><td>1Ch</td><td>02h</td><td>Internal</td><td>Intel PCI Express Root port 3</td></tr><tr><td>00h</td><td>1Ch</td><td>03h</td><td>Internal</td><td>Intel PCI Express Root port 4</td></tr><tr><td>00h</td><td>1Dh</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port5</td></tr><tr><td>00h</td><td>1Dh</td><td>01h</td><td>Internal</td><td>Intel PCI Express Root port 6</td></tr><tr><td>00h</td><td>1Dh</td><td>02h</td><td>Internal</td><td>Intel PCI Express Root port 7</td></tr><tr><td>00h</td><td>1Dh</td><td>03h</td><td>Internal</td><td>Intel PCI Express Root port 8</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>N/A</td><td>Intel LPC Interface Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>02h</td><td>Internal</td><td>Memory Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>HDA Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>SMBus Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>06h</td><td>Internal</td><td>Ethernet Controller</td></tr></table>

# 6.6. PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>P.E.G. Root Port</td><td>xHCI Controller</td><td>ME Controller #1</td><td>GbE Controller</td><td>HD Audio Controller</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td>INTD:19</td><td></td><td></td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td>INTC:18</td><td></td><td></td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTD:19</td><td>INTB:17</td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>PCIE Port1</td><td>PCIE Port 2</td><td>PCIE Port 3</td><td>PCIE Port 4</td><td>PCIE Port 5</td><td>PCIE Port 6</td><td>PCIE Port 7</td><td>PCIE Port 8</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td></tr></table>

<table><tr><td>INT Line</td><td>LPC Controller</td><td>SATA Controller</td><td>SMBus Controller</td><td>Thermal Subsystem</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td></td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td></td><td></td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td></td><td>INTC:18</td></tr><tr><td>Int3</td><td>INTD:19</td><td></td><td></td><td></td></tr></table>

# 6.7. SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMM A</td><td>A0h</td></tr><tr><td>DIMM B</td><td>A4h</td></tr><tr><td>BMC</td><td>50h</td></tr><tr><td>Extend GPIO</td><td>40h</td></tr><tr><td>NXP (eDP to LVDS transmitter)</td><td>C0h</td></tr></table>

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# 7. BIOS Setup

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information</td><td>CPU ▶</td><td rowspan="2">Password Description ▶</td><td rowspan="2">Boot Configuration ▶</td><td>Reset Options ▶</td></tr><tr><td>Processor Information</td><td>Memory ▶</td><td>Save Options ▶</td></tr><tr><td>PCH Information</td><td>Graphics ▶</td><td>Secure Boot</td><td>CSM</td><td></td></tr><tr><td>SPI Clock Frequency</td><td>SATA ▶</td><td>Menu ▶</td><td>Configuration ▶</td><td></td></tr><tr><td>System ▶</td><td>USB ▶</td><td></td><td></td><td></td></tr><tr><td>Management</td><td>Network ▶</td><td></td><td></td><td></td></tr><tr><td>System Date</td><td>PCI and PCIe ▶</td><td></td><td></td><td></td></tr><tr><td>System Time</td><td>Super IO ▶</td><td></td><td></td><td></td></tr><tr><td></td><td>ACPI and Power Management Sound ▶</td><td></td><td></td><td></td></tr><tr><td></td><td>Serial Port Console ▶</td><td></td><td></td><td></td></tr><tr><td></td><td>ICC ▶</td><td></td><td></td><td></td></tr><tr><td></td><td>Thermal ▶</td><td></td><td></td><td></td></tr><tr><td></td><td>Miscellaneous ▶</td><td></td><td></td><td></td></tr></table>

# Notes:

indicates a submenu

Gray text indicates info only

# 7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.

# 7.2.1. System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vender</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>Core Version</td><td>Info only</td><td>Display Core version</td></tr><tr><td>Compliancy</td><td>Info only</td><td>Display compliancy information</td></tr><tr><td>Project Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Build Date and Time</td><td>Info only</td><td>ADLINK date the BIOS was build.</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 7.2.2. Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Display CPU Brand Name.</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>CPU Speed</td><td>Info only</td><td>Display CPU Frequency.</td></tr><tr><td>Processor ID</td><td>Info only</td><td>Display CPU ID.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU Stepping.</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Display number of Processors.</td></tr><tr><td>GT Info</td><td>Info only</td><td>Display GT info of Intel Graphics.</td></tr><tr><td>IGFX VBIOS Version</td><td>Info only</td><td>Display VBIOS Version.</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display memory version</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency</td></tr></table>

# 7.2.3. PCH Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Display PCH name.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH SKU.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display PCH stepping.</td></tr><tr><td>LAN PHY Revision</td><td>Info only</td><td>Display LAN PHY revision</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display version of ME.</td></tr><tr><td>ME Firmware SKU</td><td>Info only</td><td>Display ME Firmware Kit SKU number.</td></tr></table>

7.2.4. SPI Clock Frequency

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Dual Output Fast Read support</td><td>Info only</td><td></td></tr><tr><td>Read Status Clock Frequency</td><td>Info only</td><td>Display frequency.</td></tr><tr><td>Write Status Clock Frequency</td><td>Info only</td><td>Display frequency.</td></tr><tr><td>Fast Read Status Clock Frequency</td><td>Info only</td><td>Display frequency.</td></tr></table>

# 7.2.5. System Management

7.2.5.1. System Management > Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>SMC Firmware</td><td>Read only</td><td>Display SMC Firmware.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SMC firmware build date.</td></tr><tr><td>SMC Boot loader</td><td>Read only</td><td>Display SMC boot loader.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SMC boot loader build date.</td></tr><tr><td>Hardware Version</td><td>Read only</td><td>Display SMC hardware Version.</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC serial Number.</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC last repair date.</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display SMC MAC ID</td></tr></table>

7.2.5.2. System Management > Temperatures and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Temperature</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td>Display CPU current temperature.</td></tr><tr><td>Startup</td><td>Read only</td><td>Display CPU startup temperature.</td></tr><tr><td>Min</td><td>Read only</td><td>Display CPU min temperature.</td></tr><tr><td>Max</td><td>Read only</td><td>Display CPU max temperature.</td></tr><tr><td>Board Temperatures</td><td>Info only</td><td></td></tr><tr><td>Current</td><td>Read only</td><td>Display board current temperature.</td></tr><tr><td>Startup</td><td>Read only</td><td>Display board startup temperature.</td></tr><tr><td>Min</td><td>Read only</td><td>Display board min temperature.</td></tr><tr><td>Max</td><td>Read only</td><td>Display board max temperature.</td></tr><tr><td>CPU Fan Speed</td><td>Read only</td><td>Display CPU fan speed.</td></tr></table>

7.2.5.3. System Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power.</td></tr><tr><td>VCC_CORE</td><td>Read only</td><td>Display actual voltage of the VCC_CORE.</td></tr><tr><td>VGFX</td><td>Read only</td><td>Display actual voltage of the .VGFX</td></tr><tr><td>VMEM</td><td>Read only</td><td>Display actual voltage of the VMEM</td></tr><tr><td>5VSB</td><td>Read only</td><td>Display actual voltage of the 5VSB</td></tr><tr><td>RTC</td><td>Read only</td><td>Display actual voltage of the RTC</td></tr><tr><td>VIN</td><td>Read only</td><td>Display actual voltage of the VIN</td></tr><tr><td>5V</td><td>Read only</td><td>Display actual voltage of the. 5V</td></tr><tr><td>3.3V</td><td>Read only</td><td>Display actual voltage of the 3.3V</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Display actual voltage of the 3.3VSB</td></tr></table>

7.2.5.4. System Management > Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.2.5.5. System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td>Display the selection of current BIOS ROM.</td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td>Display ATX/AT-Mode.</td></tr><tr><td>Exception Code</td><td>Read only</td><td>System exception reason.</td></tr></table>

7.2.5.6. System Management > Power Up

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Up</td><td colspan="2">Info only</td></tr><tr><td>Power Up watchdogAttention: F12 disables the Power Up Watchdog.</td><td>EnabledDisabled</td><td>The Power-Up Watchdog resets the system after a certain amount of time after power-up.</td></tr><tr><td>ECO Mode</td><td>DisabledEnable</td><td>Reduces the power consumption of the system.</td></tr><tr><td>Power-up ModeAttention: The Power-Up Mode only has effect, if the module is in ATX-Mode.</td><td>Turn onRemain offLast State</td><td>Turn On: The machine starts automatically when the power supply is turned on.Remain Off: To start the machine the power button has to be pressed.Last State: when powered on during a power failure the system will automatically power on when power is restored</td></tr></table>

7.2.5.7. System Management > LVDS Backlight

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS Backlight</td><td colspan="2">Info only</td></tr><tr><td>LVDS Backlight Bright</td><td>255</td><td>The value range starts by 0 and ends by 255.</td></tr></table>

7.2.5.8. System Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Smart FanTemperature Source</td><td>CPU SensorSystem Sensor</td><td>Select CPU smart fan source.</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>Select CPU Fan Mode.</td></tr><tr><td>PWM Level</td><td>100</td><td>Select PWM level.</td></tr></table>

7.2.6. System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system

7.3.1. CPU

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU</td><td>Info only</td><td>Manufacturer, model, speed</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision.</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display Processor Cores.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel Virtualization Technology support or not.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.</td></tr><tr><td>VT-d</td><td>Disabled Enabled</td><td>Check to enable VT-d function on MCH.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled Enabled</td><td>Enable/Disable support for the Intel virtualization technology.</td></tr><tr><td>Intel(R) SpeedStep(TM)</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable/Disable turbo mode.</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal Deactivate</td><td>Configure TDP Mode as Nominal/Down/Disabled. Disabled option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>Config TDP Lock</td><td>Disabled Enabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.</td></tr><tr><td>Custom Configurable TDP</td><td>Disabled Enabled</td><td>Custom Configurable TDP settings</td></tr><tr><td>Power Limit 1</td><td>15W20W25W30W35W40W</td><td>Power Limit 1 in Milli Watts. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP Limit.</td></tr><tr><td>Power Limit 1 Time Window</td><td>01234567810121416202428</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 28. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>CPU C state</td><td>DisabledEnabled</td><td>Enable or disable CPU C states</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1C3C1 and C3</td><td>Configure C-State Auto Demotion</td></tr><tr><td>Package C State limit</td><td>AutoC2C3C6C7Auto</td><td>Package C State limit</td></tr><tr><td>DTS SMM</td><td>DisabledEnabled</td><td>Enable/Disable CPU DTS.</td></tr><tr><td>ACPI T-states</td><td>DisabledEnabled</td><td>Enable/Disable ACPI 3.0 T-States.</td></tr></table>

7.3.2. Memory

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display Memory Reference Code Version.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Total Memory.</td></tr><tr><td>VDD</td><td>Info only</td><td>Display Memory Voltage.</td></tr><tr><td>DIMM#0/1</td><td>Info only</td><td>Display DIMM#0/1.</td></tr><tr><td>Memory Timings(tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Display Memory timings</td></tr><tr><td>I2C Write Protect Control</td><td>ActiveWrite Protect</td><td>I2C write protect control</td></tr><tr><td>SPD Write Protect</td><td>EnabledDisabled</td><td>Enable:Writes to SMBus slave addresses A0h - AEh are disabled.</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto106712001333140016001800186720002133220024002600266728002933300032003467373340004133</td><td>Maximun Memory Frequency Selections in MHz</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller.</td></tr></table>

7.3.3. Graphics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info only</td><td></td></tr><tr><td>IGFX VBIOS Version</td><td>Info only</td><td>Display VBIOS Version.</td></tr><tr><td>Graphics Turbo IMON Current</td><td>Number entry field</td><td>Graphics turbo IMON current values supported (14-31).</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIE</td><td>Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.</td></tr><tr><td>Primary PEG</td><td>AutoPEG11PEG12</td><td>Select PEG0/PEG1/PEG2/PEG3 Graphics device should be Primary PEG.</td></tr><tr><td>Primary PCIE</td><td>AutoPCIE2PCIE3PCIE4PCIE5PCIE6PCIE7PCIE8</td><td>Select Auto/PCIE2/PCIE3/PCIE4 of D28:F0/F1/F2/F3,PCIE5/PCIE6/PCIE7/PCIE8 of D29:F0/F1/F2/F3, Graphics device should be Primary PCIE.</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnable</td><td>Keep IGD enabled based on the setup options.</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB4096MB</td><td>Select the Aperture Size.</td></tr><tr><td>DVMT Pre-Allocated</td><td>XXM</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>XXXM</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>Gfx Low Power Mode</td><td>EnabledDisabled</td><td>This option is applicable for SFF only.</td></tr><tr><td>EDP to LVDS Bridge Configuration</td><td>Info only</td><td></td></tr><tr><td>Data Format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/VESA 18 bpp</td><td>Data format and color depth select</td></tr><tr><td>LVDS Output Mode</td><td>Single LVDS busDual LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>LVDS/eDP Backlight Mode</td><td>BMC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>GTT LVDS/eDP Backlight Control</td><td>0%20%40%60%80%100%</td><td>Actual backlight value in percent of the maximum setting.</td></tr><tr><td>PEG/DDI MUX Select</td><td>PEGDDI</td><td>PEG/DDI select</td></tr><tr><td>DDI port 1</td><td>No deviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatible</td><td>DDI port 1 function choose to Display Port or HDMI.</td></tr><tr><td>DDI port 2</td><td>No deviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatible</td><td>DDI port 2 function choose to Display Port or HDMI.</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Primary IGFX Boot Display</td><td>VBIOS Default</td><td>Select the Video Device which will be activated during POS.</td></tr><tr><td>Select Secondary Display</td><td>Disabled</td><td>Select Secondary Display Device.</td></tr><tr><td>LCD Panel Type</td><td>VBIOS Default640X480800X6001024X7681280X10241400X10501600X12001366X7681680X10501920X12001440X9001600X9001024X768 LVDS21280X8001920X10802048X1536</td><td>Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>Active LFP</td><td>No LVDSeDP Port-A</td><td>Select the Active LFP Configuration.</td></tr><tr><td>Panel Scaling</td><td>AutoOffForce Scaling</td><td>Select the LCD panel scaling option used by the Internal Graphics Device.</td></tr><tr><td>RC6(Render Standby)</td><td>EnableDisable</td><td>Check to enable render standby support.</td></tr></table>

7.3.4. SATA

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST Premium</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Speed Selection</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back)</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td></td></tr><tr><td>Aggressive LPM Support</td><td>EnabledDisabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Port Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial ATA Port X</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port X</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td>Info only</td><td></td></tr><tr><td>Spin up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSold State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive.</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td>Identify the SATA Topology if it is Default, ISATA, Flex, DirectConnect or M2.</td></tr><tr><td>SATA Port X DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port X DevSlp. Board rework for LP needed before enable.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration.</td></tr></table>

7.3.4.1. SATA > Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Software Feature Mask Configuration</td><td>Info only</td><td></td></tr><tr><td>HDD Unlock</td><td>EnabledDisabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>EnabledDisabled</td><td>If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.</td></tr></table>

7.3.5. USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Module Version</td><td>Info only</td><td></td></tr><tr><td>USB Devices</td><td>Info only</td><td>X Drive, X Keyboards, X Mouse, X Hubs</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications and setup.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>EnabledDisabled</td><td>Enable/Disable USB Mass Storage Driver Support.</td></tr><tr><td>Port 60/64 Emulation</td><td>EnabledDisabled</td><td>Enables I/O port 60h/64h emulation support. This should be enabled for the complete USB keyboard legacy support for non-USB aware OSes.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info only</td><td></td></tr><tr><td>USB transfer time-out</td><td>1 sec5 sec10 sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Host Controller. &#x27;Auto&#x27; uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.</td></tr><tr><td>Mass Storage Devices</td><td>Info only</td><td>List current USB max stroge device.</td></tr></table>

7.3.5.1. USB > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Disable Compliance Mode</td><td>FALSETRUE</td><td>Options to disable Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode.</td></tr><tr><td>XDCI Support</td><td>DisabledEnabled</td><td>Enable/Disable XDCI (USB OTG Device)</td></tr><tr><td>USB Port Disable Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr></table>

7.3.6. Network

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>EnabledDisabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>PCH LAN Controller</td><td>EnabledDisabled</td><td>Enable/Disable onboard NIC.</td></tr><tr><td>Wake on LAN</td><td>EnabledDisabled</td><td>Enable/Disable integrated LAN to wake the system.</td></tr><tr><td>AMT BIOS Features</td><td>EnabledDisabled</td><td>When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup. Note: This option does not disable Manageability Features in FW.</td></tr><tr><td>MEBx hotkey Pressed</td><td>EnabledDisabled</td><td>OEMFLag Bit 1: Enable automatic MEBx hotkey press.</td></tr><tr><td>MEBx Selection Screen</td><td>EnabledDisabled</td><td>OEMFLag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens Press 2 to initiate a remote connection Note: Network Access must be activated from MEBx Setup for this screen to be displayed.</td></tr><tr><td>Hide Un-Configure ME Confirmation Prompt</td><td>EnabledDisabled</td><td>OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration.</td></tr><tr><td>MEBx Debug Message Output Enable</td><td>EnabledDisabled</td><td>OEMFlag Bit 14: Enable OEM debug menu in MEBx.</td></tr><tr><td>UnConfigure ME</td><td>EnabledDisabled</td><td>OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default.</td></tr><tr><td>ASF support</td><td>EnabledDisabled</td><td>Enable/Disable Alert Standard Format support.</td></tr><tr><td>Activate Remote Assistance Process</td><td>EnabledDisabled</td><td>Trigger CIRA boot Note: Network Access must be activated first from MEBx Setup.</td></tr><tr><td>USB Provisioning of AMT</td><td>EnabledDisabled</td><td>Enable/Disable of AMT USB Provisioning.</td></tr><tr><td>PET Progress</td><td>EnabledDisabled</td><td>Enable/Disable PET Events Progress to receive PET Events.</td></tr><tr><td>CIRA Timeout</td><td>0</td><td>OEM defined timeout for MPS connection to be established. 0 - use the default timeout value of 60 seconds. 255 - MEBX waits until the connection succeeds.</td></tr><tr><td>Watchdog</td><td>EnabledDisabled</td><td>Enable/Disable WatchDog Timer.</td></tr><tr><td>OS Timer</td><td></td><td>Set OS watchdog timer.</td></tr><tr><td>BIOS Timer</td><td></td><td>Set BIOS watchdog timer.</td></tr></table>

7.3.7. PCI and PCIe

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI BUS Driver Version</td><td colspan="2">Info only</td></tr><tr><td>PCI Devices Common Settings:</td><td colspan="2">Info only</td></tr><tr><td>PCIE Ports 1-4 Configuration</td><td>4x1 Port1x2 2x1 Port2x2 Port1x4 Port</td><td>Configures PCI-E Port 1-4 of PCH.[4X1]: Port 1-4 (x1) and Port 8 (x1)[1x2 2x1]: Port 1 (x2), Port 2 (disabled), Ports 3-4 (x1)[2x2]: Port 1-2 (x2) and Ports 3-4 (x2)[1x4]: Port 1 (x4), Ports 2-4 (disabled)</td></tr><tr><td></td><td></td><td></td></tr><tr><td>PCI Latency Timer</td><td>32 PCI Bus Clocks64 PCI Bus Clocks96 PCI Bus Clocks128 PCI Bus Clocks160 PCI Bus Clocks192 PCI Bus Clocks224 PCI Bus Clocks248 PCI Bus Clocks</td><td>Value to be programmed into PCI Latency Timer Register.</td></tr><tr><td>PCI-X Latency Timer</td><td>32 PCI Bus Clocks64 PCI Bus Clocks96 PCI Bus Clocks128 PCI Bus Clocks160 PCI Bus Clocks192 PCI Bus Clocks224 PCI Bus Clocks248 PCI Bus Clocks</td><td>Value to be programmed into PCI Latency Timer Register.</td></tr><tr><td>VGA Palette Snoop</td><td>DisabledEnabled</td><td>Allow PCI cards that do not contain their own VGA color palette to access the video core&#x27;s palette</td></tr><tr><td>PERR# Generation</td><td>DisabledEnabled</td><td>Enables or Disables PCI Device to Generate PERR#.</td></tr><tr><td>SERR# Generation</td><td>DisabledEnabled</td><td>Enables/Disables PCI Device to Generate SERR#.</td></tr><tr><td>PCI Express Configuration</td><td colspan="2">Submenu</td></tr><tr><td>PEG Configuration</td><td colspan="2">Submenu</td></tr></table>

7.3.7.1. PCI and PCIe > PEG Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG Configuration</td><td colspan="2">Info only</td></tr><tr><td>PCI Express Clock Gating</td><td>Disabled Enable</td><td>Enable/Disable PCI Express Clock Gating for each root port.</td></tr><tr><td>DMI Link ASPM Control</td><td>Disabled Enable</td><td>The control of Active State Power Management of the DMI Link.Auto is equal to POR setting.</td></tr><tr><td>Port8xh Decode</td><td>Disabled</td><td>PCI Express Port8xh Decode Enable/Disable.</td></tr><tr><td>Compliance Test Mode</td><td>Disabled</td><td>Enable when using Compliance Load Board.</td></tr><tr><td>PCI Express Gen3 EQ Lanes</td><td colspan="2">Submenu</td></tr><tr><td>PCI Express Root Port X</td><td colspan="2">Submenu</td></tr></table>

PCI and PCIe > PCI Express Configuration > PCI Express Gen3 EQ Lanes

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Override SW EQ settings</td><td>Disabled Enable</td><td>Override SW EQ settings</td></tr></table>

PCI and PCIe > PCI Express Configuration > PCI Express Root Port X

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port</td><td>DisabledEnable</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Topology</td><td>Unknownx1x4Sata ExpressM2</td><td>Identify the SATA Topology: Default, ISATA, Flex, DirectConnect or M2.</td></tr><tr><td>ASPM Support</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level.Force L0s - Force all links to L0s StateAuto - BIOS auto configure;Disabled - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.2L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Gen3 Eq Phase3 Method</td><td>HardwareStatic Coeff.Software Search</td><td>PCIe Gen3 Equalization Phase 3 Method</td></tr><tr><td>UPTP</td><td>5</td><td>Upstream Port Transmitter Preset</td></tr><tr><td>DPTP</td><td>7</td><td>Downstream Port Transmitter Preset</td></tr><tr><td>ACS</td><td>DisabledEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>URR</td><td>DisabledEnable</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled Enable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled Enable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled Enable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>CTO</td><td>Disabled Enable</td><td>PCI Express Completion Timer TO Enable/Disable</td></tr><tr><td>SEFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled Enable</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled Enable</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>Disabled Enable</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Configure PCIe Speed.</td></tr><tr><td>Transmitter Half Swing</td><td>Disabled Enabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Non-Compliance</td><td>Disabled Enable</td><td>Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reseved Memory</td><td>10</td><td>Reserved Memory Range for this Root Bridge.</td></tr><tr><td>Prefetchable Memory</td><td>10</td><td>Prefetchable Memory Range for this Root Bridge.</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/.../48K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIE LTR</td><td>Disabled Enable</td><td>PCH PCIE Latency Reporting Enable/Disable.</td></tr><tr><td>Snoop Latency Ocerrid</td><td>Disabled Manual Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow."</td></tr><tr><td>Non Snoop Latency Ocerrid</td><td>Disabled Manual Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>PCIE LTR Lock</td><td>DisabledEnable</td><td>PCIE LTR Configuration Lock.</td></tr><tr><td>PCH PCIe CLKREQ#Configuration</td><td>Info</td><td></td></tr><tr><td>PCIEX CLKREQ MappinOverride</td><td>DefaultNo CLKREQCustomer number</td><td>PCIE CLKREQ Override for default platform mapping.</td></tr></table>

7.3.7.2. PCI and PCIe > PEG Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG Configuration</td><td colspan="2">Info only</td></tr><tr><td>PEGX</td><td>Not Present</td><td>Display PEGX present or not.</td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable/Disable the Root Port.</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure 0:1:X Max Speed</td></tr><tr><td>PEG0 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG0 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEGX Physical Slot Number</td><td>1</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td>Detect Non-compliance Device</td><td>DisabledEnable</td><td>Detect Non-Compliance PCI Express Device in PEG.</td></tr><tr><td>Program PCIe ASPM after OpROM</td><td>DisabledEnabled</td><td>Enabled: PCIe ASPM will be programmed after OpROM. Disabled: PCIe ASPM will be programmed before OpROM.</td></tr><tr><td>Program Static Phase1 Eq</td><td>EnabledDisable</td><td>Program Phase1 Presets/CTLEp</td></tr><tr><td>Gen3 Root Port Preset Value for each lane 0~15</td><td>7</td><td>Root Port preset value per lane for Gen3 Equalization</td></tr><tr><td>Gen3 Endpoint Preset value for each Lane 0~15</td><td>7</td><td>Endpoint preset value per lane for Gen3 Equalization</td></tr><tr><td>Gen3 Endpoint Hint value for each Lane 0~15</td><td>2</td><td>Endpoint Hint value per lane for Gen3 Equalization</td></tr><tr><td>PEG Gen3 RxCTLE Control 0~7</td><td>0</td><td>PEG Gen3 RxCTLE Control per Bundle</td></tr><tr><td>Always Attempt SW EQ</td><td>DisabledEnabled</td><td>Always Attempt SW EQ, even it has been done once</td></tr><tr><td>Number of Presets to test</td><td>7, 3, 50 – 9Auto</td><td>Choose between 7,3,5 and 0-9. Auto = current default for CPU</td></tr><tr><td>Allow PERST# GPIO Usage</td><td>EnabledDisable</td><td>Enable/Disable GPIO-based resets to PEG endpoint(s) during margin search, if needed</td></tr><tr><td>SW EQ Enable VOC</td><td>Jitter Only Test ModeJitter &amp; VOC Test ModeAuto</td><td>Select Jitter &amp; VOC test mode (default) or Jitter only test mode. Auto will current default (Enabled)</td></tr><tr><td>Jitter Dwell Time</td><td>3000</td><td>PEG Gen3 Preset Search dwell time [0..65535] in [usec]</td></tr><tr><td>Jitter Error Target</td><td>2</td><td>The margin search error target value [1..65535]</td></tr><tr><td>VOC Dwell Time</td><td>10000</td><td>The VOC margin search dwell time [0..65535] in [usec]</td></tr><tr><td>VOC Error Target</td><td>2</td><td>The VOC margin search error target value [1..65535]</td></tr><tr><td>Generate BDAT PEG Margin Data</td><td>DisabledEnabled</td><td>Enable to generate BDAT PCIe margin tables</td></tr><tr><td>PCIe Rx CEM Test Mode</td><td>DisabledEnabled</td><td>Enable/Disable PEG Rx CEM Loopback Mode</td></tr><tr><td>PCIe Spread Spectrum Clocking</td><td>EnabledDisable</td><td>Allows disabling of Spread Spectrum Clocking for compliance testing</td></tr></table>

7.3.8. Super IO

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Chip</td><td colspan="2">Info only</td></tr><tr><td>W83627DHG Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration Serial PortDevice SettingsChange Settings</td><td>EnabledDisabledIO=3F8h; IRQ=4AutoIO=3F8h; IRQ=4IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 2 Configuration Serial PortDevice SettingsChange SettingsDevice Mode</td><td>EnabledDisabledIO=2F8h; IRQ=4AutoIO=2F8h; IRQ=3IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7.10,11,12Standard Serial Port ModeIrDA Active pulse 1.6 uSIrDA Active pulse 3/16 bit timeASKIR Mode</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Parallel Port Configuration</td><td>Info only</td><td></td></tr><tr><td>Parallel Port</td><td>DisableEnable</td><td>Enable or Disable Parallel Port (LPT/LPTE)</td></tr><tr><td>Change Setting</td><td>AutoIO=378h; IRQ5IO=378h; IRQ5,6,7,9,10,11,12IO=278h; IRQ5,6,7,9,10,11,12IO=3BCh; IRQ5,6,7,9,10,11,12</td><td>Select an optimal settings fpr super IO Device</td></tr><tr><td>Device Mode</td><td>STD Printer ModeSPP ModeEPP-1.9 and SPP ModeEPP-1.7 and SPP ModeECP ModeECP and EPP 1.9 ModeECP and EPP 1.7 Mode</td><td>Change the Printer Port mode.</td></tr></table>

7.3.9. ACPI and Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ACPI and Power Management</td><td colspan="2">Info only</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>EnabledDisabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>EnabledDisabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS.</td></tr><tr><td>ACPI Sleep State</td><td>S3 (Suspend to RAM)</td><td>Select ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>Lock Legacy Resources</td><td>EnabledDisabled</td><td>Enables or Disables Lock of Legacy Resources</td></tr><tr><td>Low Power S0 Idle Capability</td><td>EnabledDisabled</td><td>This variable determines if we enable ACPI Lower Power S0 Idle Capability (Mutually exclusive with Smart connect).</td></tr><tr><td>Emulation AT/ATX</td><td>Emulation ATATX</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown.</td></tr></table>

7.3.10. Sound

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Sound</td><td colspan="2">Info only</td></tr><tr><td>HD Audio</td><td>DisabledEnabledAuto</td><td>Control Detection of the HD-Audio device. Disabled: HDA will be unconditionally disabled. Enabled: HDA will be unconditionally enabled. Auto: HDA will be enabled if present, disabled otherwis.</td></tr></table>

7.3.11. Serial Port Console

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port Console</td><td colspan="2">Info only</td></tr><tr><td>COM1</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM2</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

7.3.11.1. Serial Port Console > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100:ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Select Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>Select Parity.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Select number of stop bits.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Select flow control.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Legacy OS Redirection</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS Post</td><td>Always EnabledBootLoader</td><td>The Settings specify if BootLoader is selected than Legacy console redirection is disabled before booting to Legacy OS. Default value is Always Enable which means Legaacy console Redirection is enabled for Legacy OS.</td></tr></table>

7.3.12. ICC Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ICC Information</td><td>Info only</td><td></td></tr></table>

Note: The item is “info only” in the standard BIOS. The options can be opened by customer request.

7.3.13. Thermal

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal</td><td colspan="2">Info only</td></tr><tr><td>Active Cooling Trip Point</td><td>Disabled40 C50 C60 C70 CBMC Default</td><td>This value is the temperature threshold of the Active Cooling Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled80 C90 C</td><td>This value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Critical Trip Point</td><td>Disabled65 C75 C85 C</td><td>This value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Watchdog ACPI Even Shutdown</td><td>DisabledEnable</td><td>Watchdog ACPI Even Shutdown Enable/Disable.</td></tr></table>

7.3.14. Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVME Configuration</td><td colspan="2">Submenu</td></tr><tr><td>Trusted Computing</td><td colspan="2">Submenu</td></tr></table>

7.3.14.1. Miscellaneous > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>EnabledDisabled</td><td>Enables or Disables BIOS support for security device. When disabled OS wil not show Security Device. TCG EFI protocol and INT1A interface will not be available</td></tr><tr><td>TPM State</td><td>EnabledDisabled</td><td>Enable/Disable Security Device. NOTE: Your Computer will reboot during restart in order to change State of the Device.</td></tr><tr><td>Pending operation</td><td>NoneTPM Clear</td><td>Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Device Start</td><td>TPM 1.2TPM 2.0Auto</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated</td></tr></table>

7.3.14.2. Miscellaneous > NVME Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVME controller and Drive information</td><td colspan="2">Info Only</td></tr></table>

# 7.4. Boot

# 7.4.1. Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Enable/Disable the onboard SATA controllers.</td></tr><tr><td>Bootup NumLock State</td><td>On</td><td>Select SATA controller mode.</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enable/Disable the PATA port. In fact this enables or disables the SATA channel on which the onboard SATA to PATA converter is attached. When set to enabled the system boot will be delayed for the time specified in PATA Port Detection Timeout if no PATA device is connected.Auto: Scan for PATA device and enable per default.</td></tr><tr><td>CSM Configuration</td><td>Submenu</td><td></td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Define the maximum time to wait for drive detection on PATA port.</td></tr><tr><td>New Boot Option Policy</td><td>DefaultPlace FirstPlace Last</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option.Has no effect for BBS boot options.</td></tr><tr><td>Boot Option Priorities</td><td>Info only</td><td></td></tr></table>

# 7.4.1.1. CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>EnabledDisable</td><td>This option controls if CSM will be launched.</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td></td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>Option ROM Messages</td><td>Force BIOSKeep Current</td><td>Set display mode for Option ROM.</td></tr><tr><td>INT19 Trap Response</td><td>ImmediatePostponed</td><td>BIOS reaction on INT19 trapping by Option ROM: IMMEDIATE - execute the trap right away; POSTPONED - execute the trap during legacy boot.</td></tr><tr><td>Boot Option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls what devices system can to boot.</td></tr><tr><td>Option ROM execution</td><td>Info only</td><td></td></tr><tr><td>Network</td><td>Do not launchLegacy onlyUEFI only</td><td>Controls the execution of UEFI and Legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI devices</td><td>UEFI OpROMLegacy OpROM</td><td>For PCI devices other than Network, Mass storage or Video defines which OpROM to launch.</td></tr></table>

# 7.5. Security

7.5.1. Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td></td></tr><tr><td>User Password</td><td>Enter password</td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td>Secure Boot</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>Vender Keys</td><td>Info only</td><td></td></tr><tr><td>Attempt Secure Boot</td><td>DisabledEnabled</td><td>Secure Boot activated when Platform Key(PK) is enrolled, System mode is User / Deployed, and CSM function is disabled</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot Mode - Custom &amp; Standard, Set UEFI Secure Boot Mode to STANDARD mode or CUSTOM mode, this change is effect after save.And after reset, the mode will return to STANDARD mode</td></tr></table>

# 7.6. Save & Exit

# 7.6.1. Reset Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Reset</td><td>Save changes and reset the system.</td><td>Save Changes and Reset</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system without saving any changes.</td><td>Discard Changes and Reset</td></tr></table>

# 7.6.2. Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr></table>

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# 8. BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

• Security (SEC) – initial low-level initialization
- Pre-EFI Initialization (PEI) – memory initialization $^{1}$
- Driver Execution Environment (DXE) – main hardware initialization $^{2}$
- Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, ...)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

$^{1}$ Analogous to “bootblock” functionality of legacy BIOS

$^{2}$ Analogous to “POST” functionality in legacy BIOS

# 8.1. Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xCF</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2. Standard Status Codes

# 8.2.1. SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2. SEC Beep Codes

None

# 8.2.3. PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4. PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5. DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

# 8.2.6. DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

# 8.2.7. ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

# 8.3. OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xFC</td><td>OEM BDS initialization codes</td></tr></table>

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# 9. Mechanical Information

# 9.1. Board-to-Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

# Tyco 3-1827253-6

# Foxconn QT002206-2131-3H

- 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
- This connector can be used with 5 mm through-hole standoffs (SMT type).

![Exterior view of a multi-pin electronic component with metallic pins and slots (no text or symbols visible)](.express-kl2-50-1j101-1000-10/522b1363eabc73c41c8acc320adea8bec2b0f71fd548fc0206c1272a231070ce.jpg)

# Tyco 3-6318491-6

# Foxconn QT002206-4141-3H

- 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
- This connector can be used with 8 mm through-hole standoffs (SMT type).

![Exterior view of a rectangular electronic component with multiple slots and mounting holes (no text or symbols visible)](.express-kl2-50-1j101-1000-10/c9110cd7fe3d50aa3f07efe0b488ad83c37699fd48b40dc9f48fa95b080d3919.jpg)

# Common Specifications

• Current capacity: 0.5A per pin
• Rated voltage: 50 VAC
• Insulation resistance: 100M or greater @ 500 VDC
• Temperature rating: $-40^{\circ}C \sim 85^{\circ}C$
• UL certification (ECBT2.E28476)
• Copper alloy (contacts)
• Housing: thermo-plastic molded compound (L.C.P.)

# 9.2. Thermal Solution

# 9.2.1. Heat Spreaders

The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.

# 9.2.2. Heat Sinks

A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.

# 9.2.3. Installation

Install a heat spreader or heat sink using the following instructions.

Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.

![Close-up of a green printed circuit board with multiple RAM chips and a USB drive, being handled by gloved hands (no visible text or symbols)](.express-kl2-50-1j101-1000-10/4772a1ab7a42946ae632d38889e25652121994f366ca656919b97344129bd60e.jpg)

Step 2: Remove the protective membranes from the thermal pads.

![Close-up of a green textured surface being held by tweezers, with a small inset showing a white rectangular block (no text or symbols visible)](.express-kl2-50-1j101-1000-10/3c1cd30b67670ebe9a93ed6c791ce4a20a741af3cf6b04b75f7ab1a9e534f4dc.jpg)

Step 3: Assemble the heatsink onto the COM Express module.

Use the three M2.5, L=6mm screws provided to fasten the heatsink to the module.

![Close-up of a green printed circuit board with visible components and a metal tool inserted (no text or symbols)](.express-kl2-50-1j101-1000-10/8bf56ac760454ed5c8b84ecca9c003440ed3694577dc32543d87c561b19cff21.jpg)

![Three silver screws are arranged vertically in a row on a plain, light-colored surface.](.express-kl2-50-1j101-1000-10/e0bfbd9b3ce558541015b9dcbe721b57d21905be16ef39b4957788fd5b3ff674.jpg)

Note: The Express-KL2 uses two screws to attach the heatsink to the COM Express module.

Step 4: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.

![Close-up of a green printed circuit board with electronic components and connectors, being handled by gloved hands (no visible text or symbols)](.express-kl2-50-1j101-1000-10/8f9bf47e2d179987c950e49dfe5bfe6b97dd6a4c5c147bedbeb42ba021eb9450.jpg)

Then press down on the module until it is firmly seated on the carrier board.

Step 5: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.

![Close-up of a green printed circuit board with multiple electronic components and red circular annotations (no readable text or symbols)](.express-kl2-50-1j101-1000-10/b144ac7d60b0c518b2d4a5dac71f2d8639ac00a82904377fb7a432eb1679ff44.jpg)

![Five metallic screw pins arranged horizontally on a plain background (no text or symbols visible)](.express-kl2-50-1j101-1000-10/ac37bb8733322cba2cb20c8b2ee2efb9bc7f9aed5c806918227551e7770f5198.jpg)

Step 6: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.

![Close-up of a green printed circuit board with electronic components and a hand adjusting a CPU socket (no visible text or symbols)](.express-kl2-50-1j101-1000-10/30dc0ae981922eca54769d54a26d3dd3e44ba905a8f3a9738e108cbb031be545.jpg)

# 9.3. Mounting Methods

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

Top Mounting
with 5 mm connectors
![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n5 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.express-kl2-50-1j101-1000-10/d5f2afd107efa3a1a6aebcf7ea8c7a582f84fccb89d3354f25345929ad7758fc.jpg)

Bottom Mounting
with 5 mm connectors
![2 mm heatspreader with\n9 mm threaded standoffs\nM2.5\nØ50\nØ27\nCOM Express Module ~ 2 mm\nØ27\nØ55\nØ38\n5 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 14 mm\nwith spring / washer](.express-kl2-50-1j101-1000-10/e8e45f28ffbae1993a361bd8d4ed1b54a53887eb628aa6f68d67abb5b6d410ce.jpg)

Top Mounting
with 8 mm connectors
![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n8 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.express-kl2-50-1j101-1000-10/031ccde4bb43ff261d55b0d99b87aee4db374050a27a73036caab52903fe0a34.jpg)

Bottom Mounting
with 8 mm connectors
![2 mm heatsprader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n8 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 16 mm\nwith spring / washer](.express-kl2-50-1j101-1000-10/69088f0e3f8d8292f7d1795d4487d8d0c899fe2447a1ac4e55e14082721b1444.jpg)

Figure 6: COM Express Mounting Methods

# 9.4. Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

<table><tr><td>5mm through-hole standoff (SMT type)P/N: 33-72000-0050&lt;img src="images/219cf5c717dfb3fe6c678729702fd1d06a89fc936075124a05dd4444057d9ff6.jpg"/&gt;</td><td>5mm threaded standoff (DIP type)P/N: 33-72016-0050&lt;img src="images/67bc22fa21d1074b5eafd2c3a1b4f7fe4ea1a0e14703a0e9aedb47c94ac17dfd.jpg"/&gt;</td></tr><tr><td>8mm through-hole standoff (SMT type)P/N: 33-72000-0080&lt;img src="images/d27b160b8f4e2ebb1de2231d985d42b2f083d7439e652e6288b4822656574599.jpg"/&gt;</td><td>8mm threaded standoff (DIP type)P/N: 33-72015-0050&lt;img src="images/c77f216b9ddae710390fc3b9ccbfe323e3b1da08b7e780847935bf288d170330.jpg"/&gt;</td></tr></table>

Figure 7: COM Express Standoff Types

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

- Please read these safety instructions carefully.
- Please keep this User's Manual for later reference.
- Read the specifications section of this manual for detailed information on the operating environment of this equipment.
- When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

- Keep equipment away from water or liquid sources.
- Keep equipment away from high heat or high humidity.
- Keep equipment properly ventilated (do not block or cover ventilation openings).
■ Make sure to use recommended voltage and power source settings.
■ Always install and operate equipment near an easily accessible electrical socket-outlet.
- Secure the power cord (do not place any object on/over the power cord).
- Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
- If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

\- Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

<table><tr><td>Address:</td><td>9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan</td></tr><tr><td>Tel:</td><td>+886-2-8226-5877</td></tr><tr><td>Fax:</td><td>+886-2-8226-5717</td></tr><tr><td>Email:</td><td>service@adlinktech.com</td></tr></table>

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

<table><tr><td>Address:</td><td>300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China</td></tr><tr><td>Tel:</td><td>+86-21-5132-8988</td></tr><tr><td>Fax:</td><td>+86-21-5132-3588</td></tr><tr><td>Email:</td><td>market@adlinktech.com</td></tr></table>

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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