# COM 1 Express # Express-MC800 # User’s Manual ![Close-up of a green printed circuit board with multiple integrated circuits and visible traces (no readable text or symbols)](.express-mc800-50-1j017-1000-200-1/e59a5cf19c7913873d33ede38b56bd932ea330ea80dab0f555bb3d701875ce05.jpg) Manual Revision: 2.00 Revision Date: February 25, 2009 Part Number: 50-1J017-1000 Revision History
ReleaseDateChange
2.002009/02/25Initial Release
# Table of Contents # Express-MC800 . Revision History 2 # Preface 5 # 1 Introduction . 1.1 Description ...... # 2 Specifications 8 2.1 General . 8 2.2 Video . 9 2.3 Audio . 9 2.4 LAN . 9 2.5 Multi I/O 9 2.6 Super I/O 9 2.7 TPM (Trusted Platform Module) 9 2.8 Power Specifications . 10 2.9 Operating Systems 11 2.10 Mechanical and Environmental . 11 # 3 Function diagram . . 12 # 4 Mechanical Dimensions 13 # 5 Pin-outs and Signal Descriptions . 14 5.1 COM Express™ Type 2 . 14 5.2 Pin Definitions . 15 5.3 Signal Descriptions ..... . 17 # 6 Embedded Functions . 26 6.1 Watchdog Timer ....... . 26 6.2 GPIO . . 27 6.3 Hardware Monitoring . . 28 # 7 System Resources . . 29 7.1 System Memory Map ....... . 29 7.2 Direct Memory Access Channels .. 29 7.3 I/O Map .......... . 30 7.4 Interrupt Request (IRQ) Lines . 31 7.5 PCI Configuration Space Map . 33 7.6 PCI Interrupt Routing Map . 34 7.7 SMBus Address . 34 7.8 SMBus Slave Device Address . . 35 # 8 BIOS Setup . . 36 8.1 Starting the BIOS . 36 8.2 Main Setup ........ . 40 8.3 Advanced BIOS Setup . 41 8.4 Power Management . 61 8.5 Boot Setup . 66 8.6 Security Setup . . 69 # 9 BIOS Checkpoints, Beep Codes . . 72 9.1 Bootblock Initialization Code Checkpoints . 73 9.2 Bootblock Recovery Code Checkpoints . 74 9.3 POST Code Checkpoints . 75 9.4 OEM POST Error Checkpoints . 77 9.5 DIM Code Checkpoints . 77 9.6 ACPI Runtime Checkpoints . 78 9.7 Boot Block Beep Codes . 79 9.8 POST BIOS Beep Codes . 79 9.9 Troubleshooting POST BIOS Beep Codes . 80 # Important Safety Instructions . 81 # Getting Service 82 # Preface # Copyright 2009 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks AMIBIOS®8 is a registered trademark of American Megatrends, Inc. COM Express™, and PICMG® are registered trademarks of the PCI Industrial Computer Manufacturers Group. Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image displays a graphic of a white document icon with a folded top-right corner. Inside the document, there are horizontal gray lines representing text, and a large red checkmark is superimposed on the left side. Below the icon, the text 'NOTE:' is written in bold, black capital letters.](.express-mc800-50-1j017-1000-200-1/12430d45297063646764b999c42eb0acedce715d2cf439530866748705f02d27.jpg) Additional information, aids, and tips that help users perform tasks. ![A yellow triangular warning sign with a black border contains a black exclamation point in the center. Below the triangle, the text 'CAUTION:' is written in bold black capital letters.](.express-mc800-50-1j017-1000-200-1/ea1beda35bbf7d82eb0a98f4a7a351ce3b73faedf3b8d76eeaf9a5aeb5deb2fb.jpg) Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image displays a red triangular warning sign with a thin black outline. Inside the triangle is a white exclamation point. Below the triangle, the text 'WARNING:' appears in black, bold, capital letters.](.express-mc800-50-1j017-1000-200-1/c80eba64f16b23421d3942e438fbc66d96e17cefac20bae39a7feb8ee0dbcc0b.jpg) Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # 1 Introduction # 1.1 Description Express-MC800 is a COM Express compliant module specially designed to facilitate speedy development of semi-custom designs. The COM Express standard embodies the convergence of the latest technology standards based on serial differential signaling such as PCI Express, USB 2.0, SATA, LVDS and Serial DVO implemented on a compact, 95mm x 125mm, Computer on Module. Signals are brought out through two 220-pin board-to-board connectors that permit data transmission rates of up to 5GHz. Mounting holes connect the module with a custom-made, application specific carrier board which provide protection from shock and vibration. The Express-MC800 combines a Core™2 Duo CPU with Intel’s Mobile GME965 Express Chipset. The chipset consisting of GME965GME/ICH8M North- and Southbridge supports up to 4 GB, dual channel DDR2 667MHz memory on two stacked SODIMM sockets. The Mobile Intel® GME965 Express chipset integrates a Mobile Intel® Graphics Media Accelerator X3100 that provides CRT, single/dual channel 24-bit LVDS and TV 0ut (SDTV and HDTV). In addition to the onboard integrated graphics, a PCI ![intel®\nCore™2\nDuo\ninside™](.express-mc800-50-1j017-1000-200-1/18616e96cf686e042d7d9fb33df8eacbcde370ca0d3fb918d6241ba2d27b1748.jpg) ![Close-up of a green printed circuit chip with an Intel logo on its surface (no text or symbols visible)](.express-mc800-50-1j017-1000-200-1/a762548198e32aaf71d6e310994d14f27dc077bfd2f0638e157fbbecb5bdfc6f.jpg) Express Graphics (PEG) x16 bus is available for connection to high end PCI Express x16 Graphic chipsets or General Purpose x8, x4 or x1 PCI Express devices. The PEG x16 bus can alternatively be used in SDVO mode to connect to DVI, TMDS or TV-out device controllers. The board allows connection of up to five additional PCI Express x1 devices via the ICH8M Southbridge. The module comes with a single onboard Gigabit Ethernet port and two SATA ports. It has legacy support for a single Parallel IDE channel, 32-bit PCI and LPC. The Express-MC800 comes equipped with AMIBIOS8 supporting many embedded features such as: Remote Console, CMOS backup, CPU and System monitoring, Dual Watchdog timer for NMI or RESET, operation over battery power, and extended power modes such as S0, S3, S4 and S5. ![ADLINK\nGREEN\nRoHS Compliant](.express-mc800-50-1j017-1000-200-1/b8c2d1fbca47779cbe7424ca4cbf09f628d147d2af596c34c10aca98a54ebc65.jpg) Express-MC800 is a RoHS compliant and leadfree product. # 2 Specifications # 2.1 General
CPU:Merom Core Socket-P typeIntel® CoreTM2 Duo T7500, FSB 800, 2.2 GHz with 4MB L2 cache, 34 WIntel® Celeron® M 550, FSB 533, 2.0 GHz, with 1MB L2 cache 27 W
Merom Core BGA typeIntel® CoreTM2 Duo T7500, FSB 800, 2.2 GHz with 4MB L2 cache, 34 WIntel® CoreTM2 Duo L7500, FSB 800, LV 1.5 GHz with 4MB L2 cache, 17 WIntel® CoreTM2 Duo U7500, FSB 533, ULV 1.06 GHz with 2MB L2 cache, 10 W
Memory:Dual stacked SODIMM socket memory supporting dual channel memory bandwidth, for max 4 GB of non-ECC, 533/667 MHz DDR2 (GME960 only supports 533 MHz)
Chipset:Express-MC800Intel® GME965 Express Graphic Memory Controller Hub and Intel® I/O Controller Hub 8 Mobile (ICH8-M)
Express-MC533Intel® GME960 Express Graphic Memory Controller Hub and Intel® I/O Controller Hub 8 Mobile (ICH8-M)
L2 Cache:1 MB (Celeron® M), 4/2 MB (CoreTM2 Duo)
BIOS:AMIBIOS8 with CMOS backup in 8 Mbit SPI BIOS
Hardware Monitor:Supply Voltages and CPU temperature
Watchdog Timer:Programmable timer ranges to generate RESET
Expansion Busses:
- 6 PCI Express x1 (0 – 4 free, 5 occupied by GbE LAN) optionally configurable as PCIe x4- Graphics PCI Express x16 or PCI Express x8/x4/x1, or SDVO digital video bus- 32-bit PCI 2.3 at 33MHz, supporting 6 bus masters- LPC, SMBus, I2C
# 2.2 Video f Chipset: GME965 GMCH integrated Mobile Intel® Graphics Media Accelerator X3100 f CRT Interface: Analog CRT support up to 2048x1536 at 60 Hz, 32-bpp f LVDS Interface: Single or Dual channel 18/24-bit at 25\~112 MHz f TV-out: NTSC/PAL up to 1024x768 resolution, HDTV 480p/720p/1080i/1080p modes supported (without Macrovision) # 2.3 Audio f Chipset: Integrated in Intel® I/O Controller Hub 8 Mobile (ICH8M) f Audio Codec: on carrier # 2.4 LAN f Chipset: Integrated in Intel® I/O Controller Hub 8 Mobile (ICH8M) f Interface: 10/100/1000 Mbps # 2.5 Multi I/O f Chipset: Integrated in Intel® I/O Controller Hub 8 Mobile (ICH8M) f IDE (PATA): Single channel IDE with UDMA 100/66/33 support f SATA: Three ports SATA300 f USB: Supports up to eight ports USB v.2.0 # 2.6 Super I/O f Connected to LPC bus on carrier if needed # 2.7 TPM (Trusted Platform Module) f Chipset: Infineon SLB9635TT1.2 f Type: TPM 1.2 # 2.8 Power Specifications Input Power: AT mode (12 V ± 5%) and ATX mode (12 V and $5 \ V _ { \mathrm { { { S B } } } } \pm 5 \% )$ f Power Management: ACPI 3.0 compliant with battery support. All power testing was done on power supply wiring leading to the Express carrier board. Although all voltages were measured, only 12 V and 5 VSB are relevant because they are the only ones used by the Express module. The Idle power level was measured under Windows XP with no applications running (logon screen). CPU Stress was measured using Kpower, and Total System Stress was measured under burn-in conditions. ![Yellow lightning bolt symbol on white background (no text or symbols)](.express-mc800-50-1j017-1000-200-1/b3ef0e5d5766f064bee6c8a688c07691019dce0d7b7753f9b732ecd9ad734258.jpg) Intel® Core™2 2 Duo T7500 at 2.2 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)2.49 A23.41 mA30 W
Windows XP logon screen (idle)1.78 A10.88 mA21.4 W
Windows XP CPU Stress (Kpower)2.94 A13.02 mA35.3 W
Windows XP Total System Stress (Burnin)3.45 A13.67 mA41.5 W
S4 Mode (hibernate)-640.0 mA3.2 W
S3 Mode (suspend to RAM)-663.8 mA3.3 W
Intel® Celeron® M 550 at 2.0 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)2.45 A12.41 mA29.5 W
Windows XP logon screen (idle)1.72 A8.437 mA20.7 W
Windows XP CPU Stress (Kpower)2.52 A12.13 mA30.3 W
Windows XP Total System Stress (Burnin)2.87 A12.33 mA34.4 W
S4 Mode (hibernate)-626.6 mA3.1 W
S3 Mode (suspend to RAM)-648.3 mA3.2 W
Intel® Core™2 Duo L7500 at 1.6 GHz
Power State+12V $+5V_{SB}$ Power Consumption
DOS (idle)2.02 A24.22 mA24.4 W
Windows XP logon screen (idle)1.75 A30.55 mA21.1 W
Windows XP CPU Stress (Kpower)2.51 A32.53 mA30.3 W
Windows XP Total System Stress (Burnin)2.77 A32.76 mA33.4 W
S4 Mode (hibernate)-270.1 mA1.35 W
S3 Mode (suspend to RAM)-284.6 mA1.42 W
Intel® Core $^ { T M } 2$ Duo U7500 at 1.06 GHz
Power State+12V+5 $V_{SB}$ Power Consumption
DOS (idle)1.73 A46.9 mA21.0 W
Windows XP logon screen (idle)1.48 A44.79 mA18.0 W
Windows XP CPU Stress (Kpower)2.01 A56.27 mA24.4 W
Windows XP Total System Stress (Burnin)2.22 A62.45 mA26.9 W
S4 Mode (hibernate)-266.1 mA1.3 W
S3 Mode (suspend to RAM)-272.0 mA1.4 W
# 2.9 Operating Systems f Standard Support Windows XP / Vista - Linux 2.6.x f Extended Support (BSP) Embedded XP support package - Linux 2.6.x BSP - Vxworks 6.x BSP (on request) - AIDI I2C Library for Windows and Linux # 2.10 Mechanical and Environmental f Form factor and Type: PICMG COM.0, Standard COM Express™ Type II f Dimensions: 95 x 125 mm f Standard Operating Temperature: $0 ^ { \circ } C$ to $6 0 ^ { \circ } \mathrm { C }$ f Relative Humidity: up to 90% at $5 5 ^ { \circ } \mathrm { C }$ # 3 Function diagram ![This block diagram illustrates a computer system architecture centered around a CPU, a GMCH (Graphics and Memory Controller Hub), and an ICH (I/O Controller Hub).\n\n**Top Section:**\n* **CPU Block:** Labeled 'CPU' with text 'Celeron® M', 'Core™ 2 Duo', 'SMT µFCBGA2', 'or µFCPGA2'.\n* **Connection:** A double-headed arrow labeled 'FSB 533/800 Mhz' connects the CPU to the GMCH block below it.\n\n**GMCH Section:**\n* **GMCH Block:** Labeled 'GMCH' and 'Intel® GME965'. It contains several internal sub-blocks:\n * 'Analog VGA'\n * 'Graphic Core X3100'\n * 'SDTV HDTV'\n * 'LVDS dual 18/24-bit'\n * 'Gfx PCIe x16 PCIe x8/x4/x2/x1 or 2x SDVO'\n * 'DDR-2 Memory Controller'\n* **Memory Connections:** Two double-headed arrows connect the 'DDR-2 Memory Controller' to two separate boxes on the right:\n * 'Channel A' connects to 'DDR2 533/667 SODIMM socket'.\n * 'Channel B' connects to 'DDR2 533/667 SODIMM socket'.\n* **Bus Connections (Left - AB):** Lines connect the GMCH to a vertical bus labeled 'AB':\n * 'CRT'\n * 'TV-out'\n * 'LVDS'\n* **Bus Connections (Right - CD):** A line labeled 'PCIe x16' connects the GMCH to a vertical bus labeled 'CD'.\n* **Connection to ICH:** A double-headed arrow labeled 'DMI' connects the GMCH to the ICH block below.\n\n**ICH Section:**\n* **ICH Block:** Labeled 'ICH' and 'Intel® ICH8M'. It contains internal sub-blocks:\n * 'HDA Audio'\n * 'GbE MAC'\n * 'PCI-E x1 (6 ports)'\n * 'RTC'\n * 'SMBus'\n * 'SPI'\n * 'LPC'\n * 'PATA 1x'\n * 'PCI'\n * '3x SATA2'\n * '8x USB 2.0'\n* **Bus Connections (Left - AB):** Multiple lines connect the ICH to the 'AB' bus:\n * 'Audio'\n * 'GbE PHY Intel 82566MM' (connected via a line labeled 'Port 5 : NA (Multifunction with LAN)' to the 'GbE MAC' inside ICH).\n * 'PCIe x1 port 0~4 (or x4 using 0~3)'\n * 'SATA_0-1'\n * 'USB 2.0 (8x)'\n * 'I2C' (connected to a block labeled 'BC')\n * 'SMBus'\n * 'GPIO' (connected to a block labeled 'GPIO F75111R')\n * 'LPC'\n* **Bus Connections (Right - CD):** Lines connect the ICH to the 'CD' bus:\n * 'IDE' (connected from 'PATA 1x')\n * 'PCI 33 Mhz, v2.3' (connected from 'PCI')\n* **External Connections:**\n * 'SMBus' connects to 'Monitor LM95235' and 'Monitor LM87'.\n * 'SPI' and 'LPC' connect to a block labeled 'BIOS'.\n * 'LPC' connects to 'TPM' and 'LPC header'.](.express-mc800-50-1j017-1000-200-1/c4635bf41dff229c65a2b8dd6fdc5abfb157472faa76bf5055b8f8da54d6f24f.jpg) # 4 Mechanical Dimensions ![| Node ID | Dimension (mm) |\n| ------- | -------------- |\n| 1 | 125.00 |\n| 2 | 121.00 |\n| 3 | 80.00 |\n| 4 | 16.50 |\n| 5 | 4.00 |\n| 6 | 0.00 |\n| 7 | 4.00 |\n| 8 | 6.00 |\n| 9 | 18.00 |\n| 10 | 45.00 |\n| 11 | 91.00 |\n| 12 | 91.00 |\n| 13 | 95.00 |\n| 14 | 125.00 |\n| 15 | 121.00 |\n| 16 | 80.00 |\n| 17 | 4.00 |](.express-mc800-50-1j017-1000-200-1/6028df9a6b859d5924054d55cad824d2f39268c5d01660cd4f3509d6277ece78.jpg) Top View All tolerances ± 0.05 mm Other tolerances ± 0.2 mm # 5 Pin-outs and Signal Descriptions # 5.1 COM Express™ Type 2 All pinouts on AB and CD connector of the Express-MC800 comply with pin-out and signal descriptions used in the original “PICMG® COM.0 R1.0: COM Express™ Module Base Specification”. This document contains a description of pinouts, signal descriptions, and mechanical characteristics of the COM Express™ (Express®) form factor. An additional document, “Express® Design Guide” gives a general introduction to carrier board designs for COM Express™ (Express®) modules. # AB Connector 1 Gigabit Ethernet port LPC interface 4 Serial ATA channels High Definition Audio 8 USB 2.0 ports 3 PCI Express Lanes x1 Dual 24-bit LVDS channels Analog VGA TV-out ports (SDTV/HDTV) 8 GPIO pins +12V primary power input +5V standby and 3V RTC ![125mm.\n95mm\nAB\nCD](.express-mc800-50-1j017-1000-200-1/0997cc450181ca0bc34d0636b8f3aa3506471921f62e78486c2d329d7cdaa0ce.jpg) # CD Connector Parallel ATA, IDE port alternate definition assigns this to 2 additional Gigabit Ethernet ports 32-bit PCI v2.3 bus alternate definition assigns this to 10 additional PCI Express x1 lanes PCI Express x16 for Graphics these pins can also be assigned to two SDVO extensions (multiplexed) SMB and I2 C bus Power / Thermal control +12V primary power input ![COM\nExpress](.express-mc800-50-1j017-1000-200-1/0c4010b98decd14a35060aa38ba7945546bd685f275c9de4857b70735be8d2f9.jpg) # 5.2 Pin Definitions Pinout description for: Basic form factor, Type 2 ![D1\nC1\nD110\nC110](.express-mc800-50-1j017-1000-200-1/66c7b7f3c1134693a513b3d3d722b0560890a7d305844e81eb9864bbe2bbe8bd.jpg) ![B1\nA1\nB110\nA110](.express-mc800-50-1j017-1000-200-1/882ac9725a4e62f02ccd8994e85d9294e6f7e3d185e8675a1234ccc511b551b8.jpg) A B ![The image displays two columns of concentric circles against a white background. On the left, there are five concentric circles drawn with solid, continuous lines that are irregular and wobbly. On the right, there are five concentric circles drawn with dashed, segmented lines that also appear somewhat irregular.](.express-mc800-50-1j017-1000-200-1/d9e99161db2400c5b76247de6eef80238aca4b41e2a6b0bee09312220573d106.jpg) ![The image displays two concentric circle patterns, resembling targets or bullseyes, arranged side-by-side horizontally on a white background. Both patterns consist of multiple thin, dashed grey rings decreasing in size toward the center, ending with a small central dot. The pattern on the right appears to be a duplicate of the one on the left, though slightly larger in diameter.](.express-mc800-50-1j017-1000-200-1/4b4f747e22564277d8f005bb2d72db6387a24c94c541b29f5ff5518cff6a52a8.jpg) Row A Row B
Pin No.Pin NamePin No.Pin Name
A1GND (FIXED)B1GND (FIXED)
A2GBE0_MDI3-B2GBE0_ACT#
A3GBE0_MDI3+B3LPC_FRAME#
A4GBE0_LINK100#B4LPC_AD0
A5GBE0_LINK1000#B5LPC_AD1
A6GBE0_MDI2-B6LPC_AD2
A7GBE0_MDI2+B7LPC_AD3
A8GBE0_LINK#B8NC
A9GBE0_MDI1-B9LPC_DRQ1#
A10GBE0_MDI1+B10LPC_CLK
A11GND (FIXED)B11GND (FIXED)
A12GBE0_MDIO-B12PWRBTN#
A13GBE0_MDIO+B13SMB_CK
A14GBE0_CTREFB14SMB_DAT
A15SUS_S3#B15SMB_ALERT#
A16SATA0_TX+B16SATA1_TX+
A17SATA0_TX-B17SATA1_TX-
A18SUS_S4#B18SUS_STAT#
A19SATA0_RX+B19SATA1_RX+
A20SATA0_RX-B20SATA1_RX-
A21GND (FIXED)B21GND (FIXED)
A22SATA2_TX+B22NC (1)
A23SATA2_TX-B23NC (1)
A24SUS_S5#B24PWR_OK
A25SATA2_RX+B25NC (1)
A26SATA2_RX-B26NC (1)
A27BATLOW#B27WDT
A28ATA_ACT#B28AC_SDIN2
A29AC_SYNCB29AC_SDIN1
A30AC_RST#B30AC_SDIN0
A31GND (FIXED)B31GND (FIXED)
A32AC_BITCLKB32SPKR
A33AC_SDOUTB33I2C_CK
A34BIOS_DISABLE#B34I2C_DAT
A35THRMTRIP#B35THRM#
A36USB6-B36USB7-
A37USB6+B37USB7+
A38USB_6_7_OC#B38USB_4_5_OC#
A39USB4-B39USB5-
A40USB4+B40USB5+
A41GND (FIXED)B41GND (FIXED)
A42USB2-B42USB3-
A43USB2+B43USB3+
A44USB_2_3_OC#B44USB_0_1_OC#
A45USB0-B45USB1-
A46USB0+B46USB1+
A47VCC_RTCB47NC
A48EXCD0_PERST#B48NC
A49EXCD0_CPPE#B49SYS_RESET#
A50LPC_SERIRQB50CB_RESET#
A51GND (FIXED)B51GND (FIXED)
A52PCIE_TX5+ (2)B52PCIE_RX5+ (2)
A53PCIE_TX5- (2)B53PCIE_RX5- (2)
A54GPIOB54GPO1
A55PCIE_TX4+B55PCIE_RX4+
Row C Row D
Pin No.Pin NamePin No.Pin Name
C1GND FIXED)D1GND FIXED)
C2IDE_D7D2IDE_D5
C3IDE_D6D3IDE_D10
C4IDE_D3D4IDE_D11
C5IDE_D15D5IDE_D12
C6IDE_D8D6IDE_D4
C7IDE_D9D7IDE_D0
C8IDE_D2D8IDE_REQ
C9IDE_D13D9IDE_IOW#
C10IDE_D1D10IDE_ACK#
C11GND (FIXED)D11GND (FIXED)
C12IDE_D14D12IDE_IRQ
C13IDE_IORDYD13IDE_A0
C14IDE_IOR#D14IDE_A1
C15PCI_PME#D15IDE_A2
C16PCI_GNT2#D16IDE_CS1#
C17PCI_REQ2#D17IDE_CS3#
C18PCI_GNT1#D18IDE_RESET#
C19PCI_REQ1#D19PCI_GNT3#
C20PCI_GNT0#D20PCI_REQ3#
C21GND (FIXED)D21GND (FIXED)
C22PCI_REQ0#D22PCI_AD1
C23PCI_RESET#D23PCI_AD3
C24PCI_AD0D24PCI_AD5
C25PCI_AD2D25PCI_AD7
C26PCI_AD4D26PCI_C/BE0#
C27PCI_AD6D27PCI_AD9
C28PCI_AD8D28PCI_AD11
C29PCI_AD10D29PCI_AD13
C30PCI_AD12D30PCI_AD15
C31GND (FIXED)D31GND (FIXED)
C32PCI_AD14D32PCI_PAR
C33PCI_C/BE1#D33PCI_SERR#
C34PCI_PERR#D34PCI_STOP#
C35PCI_LOCK#D35PCI_TRDY#
C36PCI_DEVSEL#D36PCI_FRAME#
C37PCI_IRDY#D37PCI_AD16
C38PCI_C/BE2#D38PCI_AD18
C39PCI_AD17D39PCI_AD20
C40PCI_AD19D40PCI_AD22
C41GND (FIXED)D41GND (FIXED)
C42PCI_AD21D42PCI_AD24
C43PCI_AD23D43PCI_AD26
C44PCI_C/BE3#D44PCI_AD28
C45PCI_AD25D45PCI_AD30
C46PCI_AD27D46PCI_IRQC#
C47PCI_AD29D47PCI_IRQD#
C48PCI_AD31D48PCI_CLKRUN#
C49PCI_IRQA#D49PCI_M66EN#
C50PCI_IRQB#D50PCI_CLK
C51GND (FIXED)D51GND (FIXED)
C52PEG_RX0+D52PEG_TX0+
C53PEG_RX0-D53PEG_TX0-
C54TYPE0#D54PEG_LANE_RV#
C55PEG_RX1+D55PEG_TX1+
Row A Row B
Pin No.Pin NamePin No.Pin Name
A56PCIE_TX4-B56PCIE_RX4-
A57GNDB57GPO2
A58PCIE_TX3+B58PCIE_RX3+
A59PCIE_TX3-B59PCIE_RX3-
A60GND (FIXED)B60GND (FIXED)
A61PCIE_TX2+B61PCIE_RX2+
A62PCIE_TX2-B62PCIE_RX2-
A63GPI1B63GPO3
A64PCIE_TX1+B64PCIE_RX1+
A65PCIE_TX1-B65PCIE_RX1-
A66GNDB66WAKE0#
A67GPI2B67WAKE1#
A68PCIE_TX0+B68PCIE_RX0+
A69PCIE_TX0-B69PCIE_RX0-
A70GND (FIXED)B70GND (FIXED)
A71LVDS_A0+B71LVDS_B0+
A72LVDS_A0-B72LVDS_B0-
A73LVDS_A1+B73LVDS_B1+
A74LVDS_A1-B74LVDS_B1-
A75LVDS_A2+B75LVDS_B2+
A76LVDS_A2-B76LVDS_B2-
A77LVDS_VDD_ENB77LVDS_B3+
A78LVDS_A3+B78LVDS_B3-
A79LVDS_A3-B79LVDS_BKLT_EN
A80GND (FIXED)B80GND (FIXED)
A81LVDS_A_CK+B81LVDS_B_CK+
A82LVDS_A_CK-B82LVDS_B_CK-
A83LVDS_I2C_CKB83LVDS_BKLT_CTRL
A84LVDS_I2C_DATB84VCC_5V_SBY
A85GPI3B85VCC_5V_SBY
A86KBD_RST#B86VCC_5V_SBY
A87KBD_A20GATEB87VCC_5V_SBY
A88PCIE0_CK_REF+B88RSVD (1)
A89PCIE0_CK_REF-B89VGA_RED
A90GND (FIXED)B90GND (FIXED)
A91RSVD (1)B91VGA_GRN
A92RSVD (1)B92VGA_BLU
A93GPO0B93VGA_HSYNC
A94RSVD (1)B94VGA_VSYNC
A95RSVD (1)B95VGA_I2C_CK
A96GNDB96VGA_I2C_DAT
A97VCC_12VB97TV_DAC_A
A98VCC_12VB98TV_DAC_B
A99VCC_12VB99TV_DAC_C
A100GND (FIXED)B100GND (FIXED)
A101VCC_12VB101VCC_12V
A102VCC_12VB102VCC_12V
A103VCC_12VB103VCC_12V
A104VCC_12VB104VCC_12V
A105VCC_12VB105VCC_12V
A106VCC_12VB106VCC_12V
A107VCC_12VB107VCC_12V
A108VCC_12VB108VCC_12V
A109VCC_12VB109VCC_12V
A110GND (FIXED)B110GND (FIXED)
Row D
Pin No.Pin NamePin No.Pin Name
C56PEG_RX1-D56PEG_TX1-
C57TYPE1#D57TYPE2# (3)
C58PEG_RX2+D58PEG_TX2+
C59PEG_RX2-D59PEG_TX2-
C60GND (FIXED)D60GND (FIXED)
C61PEG_RX3+D61PEG_TX3+
C62PEG_RX3-D62PEG_TX3-
C63BC_RX (4)D63RSVD (1)
C64BC_TX (4)D64RSVD (1)
C65PEG_RX4+D65PEG_TX4+
C66PEG_RX4-D66PEG_TX4-
C67BC_FANPWR (4)D67GND
C68PEG_RX5+D68PEG_TX5+
C69PEG_RX5-D69PEG_TX5-
C70GND (FIXED)D70GND (FIXED)
C71PEG_RX6+D71PEG_TX6+
C72PEG_RX6-D72PEG_TX6-
C73SDVO_DATAD73SDVO_CLK
C74PEG_RX7+D74PEG_TX7+
C75PEG_RX7-D75PEG_TX7-
C76GNDD76GND
C77BC_FANTACH (4)D77IDE_CBLID#
C78PEG_RX8+D78PEG_TX8+
C79PEG_RX8-D79PEG_TX8-
C80GND (FIXED)D80GND (FIXED)
C81PEG_RX9+D81PEG_TX9+
C82PEG_RX9-D82PEG_TX9-
C83BC_TPMPP (4)D83RSVD (1)
C84GNDD84GND
C85PEG_RX10+D85PEG_TX10+
C86PEG_RX10-D86PEG_TX10-
C87GNDD87GND
C88PEG_RX11+D88PEG_TX11+
C89PEG_RX11-D89PEG_TX11-
C90GND (FIXED)D90GND (FIXED)
C91PEG_RX12+D91PEG_TX12+
C92PEG_RX12-D92PEG_TX12-
C93GNDD93GND
C94PEG_RX13+D94PEG_TX13+
C95PEG_RX13-D95PEG_TX13-
C96GNDD96GND
C97RSVD (1)D97PEG_ENABLE#
C98PEG_RX14+D98PEG_TX14+
C99PEG_RX14-D99PEG_TX14-
C100GND (FIXED)D100GND (FIXED)
C101PEG_RX15+D101PEG_TX15+
C102PEG_RX15-D102PEG_TX15-
C103GNDD103GND
C104VCC_12VD104VCC_12V
C105VCC_12VD105VCC_12V
C106VCC_12VD106VCC_12V
C107VCC_12VD107VCC_12V
C108VCC_12VD108VCC_12V
C109VCC_12VD109VCC_12V
C110GND (FIXED)D110GND (FIXED)
![The image displays a graphic of a white document with faint horizontal lines and a large red checkmark. Below the document icon, the text 'NOTE:' is written in black capital letters.](.express-mc800-50-1j017-1000-200-1/85401b69b93da96eb1fc9df4f5cd7c42be466ec421fcc6554c182fb370852604.jpg) (1) These pins are NC on Express-MC800 ( PWROK, SATA3 and Reserved pins) (2) The 6th PCI Express x1 port (PCIE5) is occupied by on-board LAN controller. For six PCI Express x1 port support from the Express-MC800, please contact ADLINK for the no onboard LAN version (3) ADLINK connects TYPE2# to GND (4) These pins are for board controller usage. 5.3 Signal Descriptions Row A
PinSignalDescriptionTypePU/PDComment
A1GNDGroundPWR--
A2GBE0_MDI3-Ethernet Receive Data -I/O - DP--
A3GBE0_MDI3+Ethernet Receive Data +I/O - DP--
A4GBE0_LINK100#Ethernet Speed LED (100Mb)O-3,3PU 330 Ω 3,3VSBOn at 100Mb/s
A5GBE0_LINK1000#Ethernet Speed LED (1000Mb)O-3,3-On at 1000Mb/s
A6GBE0_MDI2-Ethernet Receive Data -I/O - DP--
A7GBE0_MDI2+Ethernet Receive Data +I/O - DP--
A8GBE0_LINK#LAN Link LEDO-3,3--
A9GBE0_MDI1-Ethernet Receive Data -I/O - DP--
A10GBE0_MDI1+Ethernet Receive Data +I/O - DP--
A11GNDGroundPWR--
A12GBE0_MDI0-Ethernet Receive Data -I/O - DP--
A13GBE0_MDI0+Ethernet Receive Data +I/O - DP--
A14GBE0_CTREFETHCTREFO-1,8--
A15SUS_S3#PM_SLP_S#3O-3,3--
A16SATA0_TX+SATA0_TX+ | SATA 0 Transmit Data +O - DP--
A17SATA0_TX-SATA0_TX- | SATA 0 Transmit Data -O - DP--
A18SUS_S4#PM_SLP_S#4O-3,3--
A19SATA0_RX+SATA0_RX+ | SATA 0 Receive Data +I - DP--
A20SATA0_RX-SATA0_RX - | SATA 0 Receive Data -I - DP--
A21GNDGroundPWR--
A22SATA2_TX+SATA0_TX+ | SATA 2 Transmit Data +O - DP--
A23SATA2_TX-SATA0_TX- | SATA 2 Transmit Data -O - DP--
A24SUS_S5#PM_SLP_S#5O-3,3--
A25SATA2_RX+SATA0_RX+ | SATA 2 Receive Data +I - DP--
A26SATA2_RX-SATA0_RX- | SATA 2 Receive Data -I - DP--
A27BATLOW#PM_BATLOW# | Battery LowI-3,3PU 10k 3,3VSB-
A28ATA_ACT#ATA_LED# | SATA LEDO-3,3PU 10k 3,3Vint. PU 15k to 3.3V in ICH8
A29AC_SYNCAC_SYNC | AC'97 SyncO-3,3-int. PD 20k in ICH8
A30AC_RST#AC_RST# | AC'97 ResetO-3,3--
A31GNDGroundPWR--
A32AC_BITCLKAC_BITCLK | AC'97 ClockO-3,3-int. PD 20k in ICH8
A33AC_SDOUTAC_SDATAOUT | AC'97 DataO-3,3-int. PD 20k in ICH8
A34BIOS_DISABLE#BIOS_DISABLE#I-3,3--
A35THRMTRIP#PM_THRMTRIP#_CONIO-3,3--
A36USB6-USB_PN6 | USB Data - Port6I/O - DP-int. PD 15k in ICH8
A37USB6+USB_PP6 | USB Data + Port6I/O - DP-int. PD 15k in ICH8
A38USB_6_7_OC#USB_OC#_6_7 | USB OverCurrent Port 6/7I-3,3PU 10k 3,3VSB
A39USB4-USB_PN4 | USB Data - Port4I/O - DP-int. PD 15k in ICH8
A40USB4+USB_PP4 | USB Data + Port4I/O - DP-int. PD 15k in ICH8
A41GNDGroundPWR--
A42USB2-USB_PN2 | USB Data - Port2I/O - DPint. PD 15k in ICH8
A43USB2+USB_PP2 | USB Data + Port2I/O - DP-int. PD 15k in ICH8
A44USB_2_3_OC#USB_OC#_2_3 | USB OverCurrent Port 2/3I-3,3PU 10k 3,3VSB-
A45USB0-USB_PN0 | USB Data - Port0I/O - DP-int. PD 15k in ICH8
A46USB0+USB_PP0 | USB Data + Port0I/O - DP-int. PD 15k in ICH8
A47VCC_RTCV_BATPWR--
A48EXCD0_PERST#Express Card Support [0] | card resetO-3,3--
A49EXCD0_CPPE#Express Card Support [0] | capable c. requestI-3,3--
A50LPC_SERIRQINT_SERIRQ | Serial Interrupt RequestIO-3,3PU 8.2k 3,3V-
A51GNDGroundPWR--
A52PCIE5_TX+BOM option (LAN on PCIe 5)NC-Optional : O - DP
A53PCIE5_TX-BOM option (LAN on PCIe 5)NC-Optional : O - DP
A54GPIOGeneral Purpose Input 0I-3,3PU 10k 3,3VSB-
A55PCIE4_TX+PCI Express lane 4 +O - DP--
A56PCIE4_TX-PCI Express lane 4 -O - DP--
A57GNDGroundPWR--
A58PCIE3_TX+PCI Express lane 3 +O - DP--
A59PCIE3_TX-PCI Express lane 3 -O - DP--
A60GNDGroundPWR--
A61PCIE2_TX+PCI Express lane 2 +O - DP--
A62PCIE2_TX-PCI Express lane 2 -O - DP--
A63GPI1General Purpose Input 1PWR--
A64PCIE1_TX+PCI Express lane 1 +O - DP--
A65PCIE1_TX-PCI Express lane 1 -O - DP--
A66GNDGroundPWR--
A67GPI2General Purpose Input 2I-3,3--
A68PCIE0_TX+PCI Express lane 0 +O - DP--
A69PCIE0_TX-PCI Express lane 0 -O - DP--
A70GNDGroundPWR--
A71LVDS_A0+LVDS_AP0 | LVDS Channel AO - DP--
A72LVDS_A0-LVDS_AN0 | LVDS Channel AO - DP--
A73LVDS_A1+LVDS_AP1 | LVDS Channel AO - DP--
A74LVDS_A1-LVDS_AN1 | LVDS Channel AO - DP--
A75LVDS_A2+LVDS_AP2 | LVDS Channel AO - DP--
A76LVDS_A2-LVDS_AN2 | LVDS Channel AO - DP--
A77LVDS_VDD_ENLVDS_VDDEN | LVDS Panel PowerO-2,5PD 100k-
A78LVDS_A3+LVDS_AP3 | LVDS Channel AO - DP--
A79LVDS_A3-LVDS_AN3 | LVDS Channel AO - DP--
A80GNDGroundPWR--
A81LVDS_A_CK+LVDS_CLKAP | LVDS Channel AO - DP--
A82LVDS_A_CK-LVDS_CLKAN | LVDS Channel AO - DP--
A83LVDS_I2C_CKLVDS_DDCPCLK | JILI I2C ClockIO-3,3PU 2k2, 3,3V-
A84LVDS_I2C_DATLVDS_DDCPDATA | JILI I2C DataIO-3,3PU 2k2, 3,3V-
A85GPI3General Purpose Input 3I-3,3PU 10k 3,3VSB-
A86KBD_RST#H_RCIN# | Keyboard ResetI-3,3PU 10k 3,3VSB-
A87KBD_A20GATEH_A20GATEI-3,3PU 10k 3,3VSB-
A88PCIE_CK_REF+CLK_PCIE_REF PO - DP--
A89PCIE_CK_REF-CLK_PCIE_REF NO - DP--
A90GNDGroundPWR--
A91RSVD-NC--
A92RSVD-NC--
A93GPO0General Purpose Output 0O-3,3PU 10k 3,3VSB-
A94RSVD-NC--
A95RSVD-NC--
A96GNDGroundPWR--
A97VCC_12VPower 12VPWR--
A98VCC_12VPower 12VPWR--
A99VCC_12VPower 12VPWR--
A100GNDGroundPWR--
A101VCC_12VPower 12VPWR--
A102VCC_12VPower 12VPWR--
A103VCC_12VPower 12VPWR--
A104VCC_12VPower 12VPWR--
A105VCC_12VPower 12VPWR--
A106VCC_12VPower 12VPWR--
A107VCC_12VPower 12VPWR--
A108VCC_12VPower 12VPWR--
A109VCC_12VPower 12VPWR--
A110GNDGroundPWR--
B1GNDGroundPWR--
B2GBE0_ACT#LAN_ACTLED# | Ethernet Activity LEDO-3,3PU 330 Ω 3,3VSB-
B3LPC_FRAME#LPC_FRAME# | LPC Frame IndicatorO-3,3--
B4LPC_AD0LPC_AD0 | LPC Adress & DATA BusIO-3,3--
B5LPC_AD1LPC_AD1 | LPC Adress & DATA BusIO-3,3--
B6LPC_AD2LPC_AD2 | LPC Adress & DATA BusIO-3,3--
B7LPC_AD3LPC_AD3 | LPC Adress & DATA BusIO-3,3--
B8LPC_DRQ0#SIO_DRQ#0 | LPC Request 0I-3,3--
B9LPC_DRQ1#SIO_DRQ#1 | LPC Request 1I-3,3--
B10LPC_CLKCLK_SIOEXTPCIO-3,3--
B11GNDGroundI-3,3--
B12PWRBTN#Power ButtonI-5--
B13SMB_CKSMBUS ClockO-3,3PU 8k2 3,3V-
B14SMB_DATSMBUS DataIO-3,3PU 8k2 3,3V-
B15SMB_ALERT#SMB_ALERT#I-3,3PU 10k 3,3V-
B16SATA1_TX+SATA1_TX+O - DP--
B17SATA1_TX-SATA1_TX-O - DP--
B18SUS_STAT#PM_SUS_STAT#O-3,3--
B19SATA1_RX+SATA1_RX+I - DP--
B20SATA1_RX-SATA1_RX-I - DP--
B21GNDGroundPWR--
B22NC-NC--
B23NC-NC--
B24PWR_OKPower OKI,5--
B25NC-NC--
B26NC-NC--
B27WDTWatch Dog TimerO-3,3--
B28AC_SDIN2AC_SDATAIN2I-3,3-int. PD 20k in ICH8
B29AC_SDIN1AC_SDATAIN1I-3,3-int. PD 20k in ICH8
B30AC_SDIN0AC_SDATAIN0I-3,3-int. PD 20k in ICH8
B31GNDGroundPWR--
B32SPKRAC_SPKRO-3,3-int. PD 20k in ICH8
B33I2C_CKI2CLKO-3,3PU 10k 3,3V-
B34I2C_DATI2DATIO-3,3PU 10k 3,3V-
B35THRM#PM THRM# CON | Over TemperatureI-3,3PU 8k2 3,3V-
B36USB7-USB_PN7 | USB Data - Port7I/O - DP-int. PD 15k in ICH8
B37USB7+USB_PP7 | USB Data + Port7I/O - DP-int. PD 15k in ICH8
B38USB_4_5_OC#USB_OC#_4_5 | USB OverCurrent PortI-3,3PU 10k 3,3VSB-
B39USB5-USB_PN5 | USB Data- Port5I/O - DP-int. PD 15k in ICH8
B40USB5+USB_PP5 | USB Data+ Port5I/O - DP-int. PD 15k in ICH8
B41GNDGroundI-3,3PU 10k 3,3VSB-
B42USB3-USB_PN3 | USB Data- Port3I/O - DP-int. PD 15k in ICH8
B43USB3+USB_PP3 | USB Data+ Port3I/O - DP-int. PD 15k in ICH8
B44USB_0_1_OC#USB_OC#_0_1 | USB OverCurrent PortI-3,3PU 10k 3,3VSB-
B45USB1-USB_PN1 | USB Data- Port1I/O - DP-int. PD 15k in ICH8
B46USB1+USB_PP1 | USB Data+ Port1I/O - DP-int. PD 15k in ICH8
B47EXCD1_PERST#Express Card Support [1] | card resetO-3,3--
B48EXCD1_CPPE#Express Card Support [1] | capable c.I-3,3--
B49SYS_RESET#ETX_SYS_RESET# | Reset InputI-3,3--
B50CB_RESET#PCI_RST# | PCI Bus ResetO-3,3--
B51GNDGroundPWR--
B52PCIE5_RX+BOM option (LAN on PCIe 5)NC-Optional: I - DP
B53PCIE5_RX-BOM option (LAN on PCIe 5)NC-Optional: I - DP
B54GPO1General Purpose Output 1O-3,3PU 10k 3,3VSB-
B55PCIE4_RX+PCI Express lane 4 + RecieveI - DP--
B56PCIE4_RX-PCI Express lane 4 - RecieveI - DP--
B57GPO2General Purpose Output 2O-3,3PU 10k 3,3VSB-
B58PCIE3_RX+PCI Express lane 3 + RecieveI - DP--
B59PCIE3_RX-PCI Express lane 3 - RecieveI - DP--
B60GNDGroundPWR--
B61PCIE2_RX+PCI Express lane 2 + RecieveI - DP--
B62PCIE2_RX-PCI Express lane 2 - RecieveI - DP--
B63GPO3General Purpose Output 3O-3,3PU 10k 3,3VSB-
B64PCIE1_RX+PCI Express lane 1 + RecieveI - DP--
B65PCIE1_RX-PCI Express lane 1 - RecieveI - DP--
B66WAKE0#PCIE_WAKEI#I-3,3PU 10k 3,3VSB-
B67WAKE1#WAKE1#I-3,3PU 10k 3,3VSB-
B68PCIE0_RX+PCI Express lane 0 + RecieveI - DP--
B69PCIE0_RX-PCI Express lane 0 - RecieveI - DP--
B70GNDGroundPWR--
B71LVDS_B0+LVDS_BP0 | LVDS Channel B Data0+O - DP--
B72LVDS_B0-LVDS_BN0 | LVDS Channel B Data0-O - DP--
B73LVDS_B1+LVDS_BP1 | LVDS Channel B Data1+O - DP--
B74LVDS_B1-LVDS_BN1 | LVDS Channel B Data1-O - DP--
B75LVDS_B2+LVDS_BP2 | LVDS Channel B Data2+O - DP--
B76LVDS_B2-LVDS_BN2 | LVDS Channel B Data2-O - DP--
B77LVDS_B3+LVDS_BP3 | LVDS Channel B Data3+O - DP--
B78LVDS_B3-LVDS_BN3 | LVDS Channel B Data3-O - DP--
B79LVDS_BKLT_ENPanel Backlight ONO-3,3PD 100k-
B80GNDGroundPWR--
B81LVDS_B_CK+LVDS_CLKBP | LVDS Channel BO - DP--
B82LVDS_B_CK-LVDS_CLKBM | LVDS Channel BO - DP--
B83LVDS_BKLT_CTRLBacklight BrightnessO-3,3--
B84VCC_5V_SBY5V StandbyPWR--
B85VCC_5V_SBY5V StandbyPWR--
B86VCC_5V_SBY5V StandbyPWR--
B87VCC_5V_SBY5V StandbyPWR--
B88RSVD-NC--
B89VGA_REDAnalog Video RGB-REDOA--
B90GNDGroundPWR--
B91VGA_GRNAnalog Video RGB-GREENOA--
B92VGA_BLUAnalog Video RGB-BLUEOA--
B93VGA_HSYNCAnalog Video H-SyncO-3,3--
B94VGA_VSYNCAnalog Video V-SyncO-3,3--
B95VGA_I2C_CKDisplay Data ChannelO-3,3PU 2k2 3,3V-
B96VGA_I2C_DATDisplay DataIO-3,3PU 2k2 3,3V-
B97TV_DAC_AComposite CVBSOA--
B98TV_DAC_BTV Luminance SignalOA--
B99TV_DAC_CTV Chrominance SignalOA--
B100GNDGroundPWR--
B101VCC_12VPower 12VPWR--
B102VCC_12VPower 12VPWR--
B103VCC_12VPower 12VPWR--
B104VCC_12VPower 12VPWR--
B105VCC_12VPower 12VPWR--
B106VCC_12VPower 12VPWR--
B107VCC_12VPower 12VPWR--
B108VCC_12VPower 12VPWR--
B109VCC_12VPower 12VPWR--
B110GNDGroundPWR--
C1GNDGroundPWR--
C2IDE_D7IDE Data BusIO-int. PD 15k in ICH8
C3IDE_D6IDE Data BusIO--
C4IDE_D3IDE Data BusIO--
C5IDE_D15IDE Data BusIO--
C6IDE_D8IDE Data BusIO--
C7IDE_D9IDE Data BusIO--
C8IDE_D2IDE Data BusIO--
C9IDE_D13IDE Data BusIO--
C10IDE_D1IDE Data BusIO--
C11GNDGroundPWR--
C12IDE_D14IDE Data BusIO--
C13IDE_IORDYIDE ReadyI-3,3PU 4K7 3,3V-
C14IDE_IOR#IDE IO ReadO-3,3--
C15PCI_PME#PCI Power Management EventIO-3,3-int. PU 20k in ICH8
C16PCI_GNT2#PCI Bus Grant 2O-3,3-int. PU 20k in ICH8
C17PCI_REQ2#PCI Bus Request 2I-3,3PU 8K2 3,3V-
C18PCI_GNT1#PCI Bus Grant 1O-3,3-int. PU 20k in ICH8
C19PCI_REQ1#PCI Bus Request 1I-3,3PU 8K2 3,3V-
C20PCI_GNT0#PCI Bus Grant 0O-3,3-int. PU 20k in ICH8
C21GNDGroundPWR--
C22PCI_REQ0#PCI Bus Request 0I-3,3PU 8K2 3,3V-
C23PCI_RESET#PCI Bus ResetO-3,3--
C24PCI_AD0PCI Adress & Data Bus lineIO-3,3--
C25PCI_AD2PCI Adress & Data Bus lineIO-3,3--
C26PCI_AD4PCI Adress & Data Bus lineIO-3,3--
C27PCI_AD6PCI Adress & Data Bus lineIO-3,3--
C28PCI_AD8PCI Adress & Data Bus lineIO-3,3--
C29PCI_AD10PCI Adress & Data Bus lineIO-3,3--
C30PCI_AD12PCI Adress & Data Bus lineIO-3,3--
C31GNDGroundPWR--
C32PCI_AD14PCI Adress & Data Bus lineIO-3,3--
C33PCI_C/BE1#PCI Bus Command and Byte enablesIO-3,3--
C34PCI_PERR#PCI Bus Grant ErrorIO-3,3PU 8K2 3,3V-
C35PCI_LOCK#PCI Bus LockIO-3,3PU 8K2 3,3V-
C36PCI_DEVSEL#PCI Bus Device SelectIO-3,3PU 8K2 3,3V-
C37PCI_IRDY#PCI Bus Bus Initiator ReadyIO-3,3PU 8K2 3,3V-
C38PCI_C/BE2#PCI Bus Command and Byte enablesIO-3,3--
C39PCI_AD17PCI Adress & Data Bus lineIO-3,3--
C40PCI_AD19PCI Adress & Data Bus lineIO-3,3--
C41GNDGroundPWR--
C42PCI_AD21PCI Adress & Data Bus lineIO-3,3--
C43PCI_AD23PCI Adress & Data Bus lineIO-3,3--
C44PCI_C/BE3#PCI Bus Command and Byte enablesIO-3,3--
C45PCI_AD25PCI Adress & Data Bus lineIO-3,3--
C46PCI_AD27PCI Adress & Data Bus lineIO-3,3--
C47PCI_AD29PCI Adress & Data Bus lineIO-3,3--
C48PCI_AD31PCI Adress & Data Bus lineIO-3,3--
C49PCI_IRQA#PCI Bus Interrupt Request AI-3,3PU 8K2 3,3V-
C50PCI_IRQB#PCI Bus Interrupt Request BI-3,3PU 8K2 3,3V-
C51GNDGroundPWR--
C52PEG_RX0+PCI Express Recieve + (0)I - DP--
C53PEG_RX0-PCI Express Recieve - (0)I - DP--
C54TYPE0#-STO--
C55PEG_RX1+PCI Express Recieve + (1)I - DP--
C56PEG_RX1-PCI Express Recieve - (1)I - DP--
C57TYPE1#-STO--
C58PEG_RX2+PCI Express Recieve + (2)I - DP--
C59PEG_RX2-PCI Express Recieve - (2)I - DP--
C60GNDGroundPWR--
C61PEG_RX3+PCI Express Recieve + (3)I - DP--
C62PEG_RX3-PCI Express Recieve - (3)I - DP--
C63RSVDRx from Board ControllerI-3.3--
C64RSVDTx from Board ControllerO-3.3--
C65PEG_RX4+PCI Express Recieve + (4)I - DP--
C66PEG_RX4-PCI Express Recieve - (4)I - DP--
C67RSVDFAN_PWR_CTRLI-5--
C68PEG_RX5+PCI Express Recieve + (5)I - DP--
C69PEG_RX5-PCI Express Recieve - (5)I - DP--
C70GNDGroundPWR--
C71PEG_RX6+PCI Express Recieve + (6)I - DP--
C72PEG_RX6-PCI Express Recieve - (6)I - DP--
C73SDVO_DATASDVO_CTRLDATAIO-2,5--
C74PEG_RX7+PCI Express Recieve + (7)I - DP--
C75PEG_RX7-PCI Express Recieve - (7)I - DP--
C76GNDGroundPWR--
C77RSVDFAN_TACHO-5--
C78PEG_RX8+PCI Express Recieve + (8)I - DP--
C79PEG_RX8-PCI Express Recieve - (8)I - DP--
C80GNDGroundPWR--
C81PEG_RX9+PCI Express Recieve + (9)I - DP--
C82PEG_RX9-PCI Express Recieve - (9)I - DP--
C83RSVDPhysical PresenceI-3,3PU 10k 3,3VSB-
C84GNDGroundPWR--
C85PEG_RX10+PCI Express Recieve + (10)I - DP--
C86PEG_RX10-PCI Express Recieve - (10)I - DP--
C87GNDGroundPWR--
C88PEG_RX11+PCI Express Recieve + (11)I - DP--
C89PEG_RX11-PCI Express Recieve – (11)I - DP--
C90GNDGroundPWR--
C91PEG_RX12+PCI Express Recieve + (12)I - DP--
C92PEG_RX12-PCI Express Recieve - (12)I - DP--
C93GNDGroundPWR--
C94PEG_RX13+PCI Express Recieve + (13)I - DP--
C95PEG_RX13-PCI Express Recieve - (13)I - DP--
C96GNDGroundPWR--
C97RSVD-NC--
C98PEG_RX14+PCI Express Recieve + (14)I - DP--
C99PEG_RX14-PCI Express Recieve - (14)I - DP--
C100GNDGroundPWR--
C101PEG_RX15+PCI Express Recieve + (15)I - DP--
C102PEG_RX15-PCI Express Recieve - (15)I - DP--
C103GNDGroundPWR--
C104VCC_12VPower 12VPWR--
C105VCC_12VPower 12VPWR--
C106VCC_12VPower 12VPWR--
C107VCC_12VPower 12VPWR--
C108VCC_12VPower 12VPWR--
C109VCC_12VPower 12VPWR--
C110GNDGroundPWR--
# Signal Descriptions (cont’d) # Row D
PinSignalDescriptionTypePU/PDComment
D1GNDGroundPWR--
D2IDE_D5IDE Data BusIO--
D3IDE_D10IDE Data BusIO--
D4IDE_D11IDE Data BusIO--
D5IDE_D12IDE Data BusIO--
D6IDE_D4IDE Data BusIO--
D7IDE_D0IDE Data BusIO--
D8IDE_REQ#IDE Data BusIO-int. PD 15k in ICH8
D9IDE_IOW#IDE IO WriteO-3,3--
D10IDE_ACK#IDE DMA AcknowledgeO-3,3--
D11GNDGroundPWR--
D12IDE_IRQIDE Interrupt RequestI-3,3PU 10K 3,3V-
D13IDE_A0IDE Adress BusO-3,3--
D14IDE_A1IDE Adress BusO-3,3--
D15IDE_A2IDE Adress BusO-3,3--
D16IDE_CS1#IDE Chip Select Channel 0O-3,3--
D17IDE_CS3#IDE Chip Select Channel 1O-3,3--
D18IDE_RESET#IDE Hard Drive ResetO-3,3--
D19PCI_GNT3#PCI Bus Grant 3O-3,3-int. PU 20k in ICH8
D20PCI_REQ3#PCI Bus Request 3I-3,3PU 8K2 3,3V-
D21GNDGroundPWR--
D22PCI_AD1PCI Adress & Data Bus lineIO-3,3--
D23PCI_AD3PCI Adress & Data Bus lineIO-3,3--
D24PCI_AD5PCI Adress & Data Bus lineIO-3,3--
D25PCI_AD7PCI Adress & Data Bus lineIO-3,3--
D26PCI_C/BE0#PCI Bus Command and Byte enables 0IO-3,3--
D27PCI_AD9PCI Adress & Data Bus lineIO-3,3--
D28PCI_AD11PCI Adress & Data Bus lineIO-3,3--
D29PCI_AD13PCI Adress & Data Bus lineIO-3,3--
D30PCI_AD15PCI Adress & Data Bus lineIO-3,3--
D31GNDGroundPWR--
D32PCI_PARPCI Bus ParityIO-3,3--
D33PCI_SERR#PCI Bus System ErrorIO-3,3PU 8K2 3,3V-
D34PCI_STOP#PCI Bus StopIO-3,3PU 8K2 3,3V-
D35PCI_TRDY#PCI Bus Target ReadyIO-3,3PU 8K2 3,3V-
D36PCI_FRAME#PCI Bus Cycle FrameIO-3,3PU 8K2 3,3V-
D37PCI_AD16PCI Adress & Data Bus lineIO-3,3--
D38PCI_AD18PCI Adress & Data Bus lineIO-3,3--
D39PCI_AD20PCI Adress & Data Bus lineIO-3,3--
D40PCI_AD22PCI Adress & Data Bus lineIO-3,3--
D41GNDGroundPWR--
D42PCI_AD24PCI Adress & Data Bus lineIO-3,3--
D43PCI_AD26PCI Adress & Data Bus lineIO-3,3--
D44PCI_AD28PCI Adress & Data Bus lineIO-3,3--
D45PCI_AD30PCI Adress & Data Bus lineIO-3,3--
D46PCI_IRQC#PCI Bus Interrupt Request CI-3,3PU 8K2 3,3V-
D47PCI_IRQD#PCI Bus Interrupt Request DI-3,3PU 8K2 3,3V-
D48PCI_CLKRUN#PCI Clock RunI-3,3PU 8K2 3,3V-
D49PCI_M66EN#Control PCI Speed 33/66 MhzO-3,3PDFixed to 33 Mhz
D50PCI_CLKPCI ClockO-3,3--
D51GNDGroundPWR--
D52PEG_TX0+PCI Express Transmit + (0)O - DP--
D53PEG_TX0-PCI Express Transmit - (0)O - DP--
D54PEG_LANE_RV#PCI Express Lane ReversalO-3,3--
D55PEG_TX1+PCI Express Transmit + (1)O - DP--
D56PEG_TX1-PCI Express Transmit - (1)O - DP--
D57TYPE2#Connected to GNDSTO-Fix PWR OK High
D58PEG_TX2+PCI Express Transmit + (2)O - DP--
D59PEG_TX2-PCI Express Transmit - (2)O - DP--
D60GNDGroundPWR--
D61PEG_TX3+PCI Express Transmit + (3)O - DP--
D62PEG_TX3-PCI Express Transmit - (3)O - DP--
D63RSVD-NC--
D64RSVD-NC--
D65PEG_TX4+PCI Express Transmit + (4)O - DP--
D66PEG_TX4-PCI Express Transmit - (4)O - DP--
D67GNDGroundPWR--
D68PEG_TX5+PCI Express Transmit + (5)O - DP--
D69PEG_TX5-PCI Express Transmit - (5)O - DP--
D70GNDGroundPWR--
D71PEG_TX6+PCI Express Transmit + (6)O - DP--
D72PEG_TX6-PCI Express Transmit - (6)O - DP--
D73SDVO_CLKSDVO_CTRLCLKIO-2,5--
D74PEG_TX7+PCI Express Transmit + (7)O - DP--
D75PEG_TX7-PCI Express Transmit - (7)O - DP--
D76GNDGroundPWR--
D77IDE_CBLID#IDE Primary ATA DetectI-3,3PD 10K-
D78PEG_TX8+PCI Express Transmit + (8)O - DP--
D79PEG_TX8-PCI Express Transmit - (8)O - DP--
D80GNDGroundPWR--
D81PEG_TX9+PCI Express Transmit + (9)O - DP--
D82PEG_TX9-PCI Express Transmit - (9)O - DP--
D83RSVD-NC--
D84GNDGroundPWR--
D85PEG_TX10+PCI Express Transmit + (10)O - DP--
D86PEG_TX10-PCI Express Transmit - (10)O - DP--
D87GNDGroundPWR--
D88PEG_TX11+PCI Express Transmit + (11)O - DP--
D89PEG_TX11-PCI Express Transmit - (11)O - DP--
D90GNDGroundPWR--
D91PEG_TX12+PCI Express Transmit + (12)O - DP--
D92PEG_TX12-PCI Express Transmit - (12)O - DP--
D93GNDGroundPWR--
D94PEG_TX13+PCI Express Transmit + (13)O - DP--
D95PEG_TX13-PCI Express Transmit - (13)O - DP--
D96GNDGroundPWR--
D97PEG_ENABLE#PCI Express EnableI-3,3PU 8K2 3,3V-
D98PEG_TX14+PCI Express Transmit + (14)O - DP--
D99PEG_TX14-PCI Express Transmit - (14)O - DP--
D100GNDGroundPWR--
D101PEG_TX15+PCI Express Transmit + (15)O - DP--
D102PEG_TX15-PCI Express Transmit - (15)O - DP--
D103GNDGroundPWR--
D104VCC_12VPower 12VPWR--
D105VCC_12VPower 12VPWR--
D106VCC_12VPower 12VPWR--
D107VCC_12VPower 12VPWR--
D108VCC_12VPower 12VPWR--
D109VCC_12VPower 12VPWR--
D110GNDGroundPWR--
Signal Descriptions (cont’d)
Signal Type Legend
IO-2,5Bi-directional 2,5 V Input/Output
IO-3,3Bi-directional 3,3 V Input/Output
IO-5Bi-directional 5 V Input/Output
I-3,33,3 V Input
I-55 V Input
O-2,52,5 V Output
O-3,33,3 V Output
O-55 V Output
IOInput/Output
OAAnalog Output
I/O - DPDifferential Pair Input/Output
O - DPDifferential Pair Output
I - DPDifferential Pair Input
PWRPower or Ground
STOStrapping Output
PUPull-Up Resistor
PDPull-Down Resistor
NCNot Connected / Reserved
# 6 Embedded Functions All embedded board functions on ADLINK’s Computer on Modules are supported at the operating system level using the ADLINK Intelligent Device Interface (AIDI) library. The AIDI API programming interface is compatible and identical across all ADLINK Computer on Modules and all supported operating systems. The AIDI library includes a demo program to demonstrate the library’s functionallity. # 6.1 Watchdog Timer The Express-MC800 implements a Watchdog timer that can be used to automatically detect software execution problems or system hangs and reset the board if necessary. The Watchdog timer consists of a counter that counts down from an initial value to zero. When the system is operating normally, the software that sets the intial value periodically resets the counter so that the it never reaches zero. If the counter reaches zero before the software resets it, the system is presumed to be malfunctioning and a reset signal is asserted. ![Cartoon illustration of a bulldog wearing a red collar (no text or symbols)](.express-mc800-50-1j017-1000-200-1/7e93a46e704b4222695225a9dc84c274c47eb7675c562c529277fa1fd0370ab7.jpg) The AIDI Library Watchdog functions support Watchdog control of the board. If the Watchdog begins countdown and reaches zero, it will access the CPU's RESET signal to reset the system. This application must call another function named AidiWDogTrigger that triggers the Watchdog to restart to prevent system reset. # AIDI Demo Program - Watchdog Tab The AIDI Demo Program allows retrieval of the current Watchdog status and updating of the Watchdog settings If the Watchdog is enabled, the user can click the WDT Trigger button to manually reset the counter and prevent the system from resetting ![AIDI DEMO Program\nBoard Info StorageArea I2C-Buses HW-Monitor GPIO WatchDog\nWatchDog Info\nNumber: 1 MinTimeout: 0 ms MaxTimeout: 255000 ms\nMinDelay: 0 ms MaxDelay: 255000 ms\nWatchDog Operation\nStart WatchDog\nTimeout(dec): ms\nDelay(dec): ms\nEnable Disable\nGetWatchDog Config\nTimeout(dec): ms\nDelay(dec): ms\nGetConfig\nWDT Trigger\nNote: the sum of timeout value and delay value can't exceed MaxTimeout or MaxDelay](.express-mc800-50-1j017-1000-200-1/da396a1ea3ded51b63d1117e7d794c4337708060b3f2efb6f4422a1014c80cc3.jpg) # 6.2 GPIO GPIO library support is limited to GPIO signals that originate from the Computer on Module and extended to the carrier board. COM Express modules support 4 GPO and 4 GPI signals. Some of ADLINK’s COM Express boards can configure all 8 ports for GPI or GPO use. GPIO signals can be monitored and controlled by using the ADLINK Intelligent Device Interface (AIDI) library that is compatible and identical across all ADLINK COM Express modules and all supported operating systems. The COM Express type II standard assigns the following pins for either GPI or GPO
PinSignal Type #AIDI ID (bit)Remark
A54GPI00Express-MC800 can configure this pin for GPI and GPO
A63GPI11Express-MC800 can configure this pin for GPI and GPO
A67GPI22Express-MC800 can configure this pin for GPI andGPO
A85GPI33Express-MC800 can configure this pin for GPI andGPO
A93GPO04Express-MC800 can configure this pin for GPI and GPO
B54GPO15Express-MC800 can configure this pin for GPI and GPO
B57GPO26Express-MC800 can configure this pin for GPI and GPO
B63GPO37Express-MC800 can configure this pin for GPI and GPO
# AIDI Demo Program - GPIO Tab The AIDI Demo Program displays current GPI or GPO status and allows reading of GPI and writing to GPO. The table above links logical port numbers in AIDI to physical port numbers on the COM Express board-to-board connector. For boards that support multidirection the “SetDirection” button can configure the port for either GPI or GPO ![AIDI DEMO Program\nBoard Info | StorageArea | I2C-Buses | HW-Monitor | GPIO | WatchDog |\nGPIO Info\nNumber: 0\nCapabilities(hex): Direction for now: 0x0000003C GetDirection\nin: 0x0000003C Input New Direction(hex): SetDirection\nout: 0x00220000\nIORead\nValue(hex): 1 GetValues\nIOWrite\nnew Value(hex): Write\nIOXorAndXor\nXor1(hex): And(hex): Xor2(hex): Write](.express-mc800-50-1j017-1000-200-1/b436332b36d1f6fb51ef0f1bd2beec455c474dcb874e12a6a96f528a855f840d.jpg) # 6.3 Hardware Monitoring To ensure system health of your embedded system ADLINK’s COM Express modules come with built in support for monitoring and control of CPU and system temperatures, fan speed and critical module voltage levels. The AIDI Library provides simple APIs at the application level to support these functions and adds alarm functions when voltage or temperature levels exceeds the upper or lower limit set by the user. On the Express-MC800 the following monitored values can be read from the module: CPU temperature, system temperature, Vcore, 1.8V, 5V, 3.3V and 12V. # AIDI Demo Program # - HW Monitor Tab Field 1 displays detected sensors (number). Field 2 allows setting of upper and lower alarm limits. Field 3 displays read out information of sensors. ![AIDI DEMO Program\nBoard Info | StorageArea | I2C-Buses | HW-Monitor | GPIO | WatchDog |\nSensor Info\n1\nTemperature Fan Voltage Number:\nType:\nSensor Limit\n2\nUpper Alarm Threshold: Lower Alarm Threshold:\nUpper Alarm Hysteresis Lower Alarm Hysteresis: GetLimit\nMaximum Value: Minimum Value: Unit: SetLimit\nNote: Input decimal data, threshold value must higher than hysteresis value\nStatus\n3\nValue: Unit\nStatus: Get Data](.express-mc800-50-1j017-1000-200-1/c1e737c8f4990d97a4c3a49e67ccf078b26af5464daac7b31515d4fe65ca55e8.jpg) # 7 System Resources # 7.1 System Memory Map
Address Range (decimal)Address Range (hex)SizeDescription
(4GB-2MB)FFE00000 - FFFFFFFF2 MBHigh BIOS Area
(4GB-18MB)-(4GB-17MB-1)FEE00000 - FEEFFFFFF1 MBFSB Interrupt Memory Space
(4GB-20MB)-(4GB-19MB-1)FEC00000 - FECFFFFFF1 MBAPIC Configuration Space
15MB - 16MBF00000 - FFFFFFF1 MBISA Hole
960 K - 1024 KF0000 - FFFFF64 KBSystem BIOS Area
896 K - 960 KE0000 - EFFFF64 KBExtended System BIOS Area
768 K - 896 KC0000 - DFFFF128 KBPCI expansion ROM areaC0000 - CEFFF: Onboard VGA BIOSCF000 - D0FFF: Intel 82566MM PXEoption ROM when onboard LAN boot ROM is enabled.
640 K - 768 KA0000-BFFFF128 KBVideo Buffer & SMM space
0 K - 640 K00000-9FFFF640 KBDOS Area
# 7.2 Direct Memory Access Channels
Channel NumberData WidthSystem ResourceComment
08-bitsParallel portNote (1)
18-bitsParallel portNote (1)
28-bitsDiskette driveNote (1)
38-bitsParallel portNote (1)
4Reserved - cascade channel
516-bitsOpen
616-bitsOpen
716-bitsOpen
![The image displays a white document icon with faint horizontal lines and a folded top-right corner. A large, bold red checkmark is superimposed over the center of the document. Below the icon, the text 'NOTE:' is written in black, uppercase letters.](.express-mc800-50-1j017-1000-200-1/b2cfbe884c039b7d6e7df7de6c6495aed325eda648b3eb080d48fefe29de1d59.jpg) (1) DMA channel 0/1/3 is selected when using parallel port.Floppy and parallel port cannot be used at the same time. 7.3 I/O Map
Address (hex)Device
000-01FDMA controller 1, 8237A-5 equivalent
020-02D and 030-03FInterrupt controller 1, 8259 equivalent
02E-02FLPC SIO (ITE8712F) configuration index/data registers
04E-04FTPM (SLB9635) configuration registers
040-05FTimer, 8254-2 equivalent
060, 062, 064, 066, 068-06F8742 equivalent (keyboard)
061, 063, 065, 067NMI control and status
070-07FReal Time Clock Controller( bit 7 -NMI mask)
080-091DMA page register
092Reset (Bit 0)/ Fast Gate A20 (Bit 1)
93-9FDMA page registers continued
0A0-0B1 and 0B4-0BFInterrupt controller 2, 8259 equivalent
0B2 and 0B3APM control and status port respectively
0C0-0DFDMA controller 2, 8237A-5 equivalent
0E0-0EFAvailable
0F0Co-processor error register
0F1N/A
0F2-0F3N/A
0F4IDE ID port
0F5-0F7N/A
0F8IDE Index port
0F9-0FBN/A
0FCIDE Data port
0FD-0FFN/A
100-179Available
180-181Default AIM4 SRAM control register (may be remapped)
182-1EFAvailable
1F0-1F7Primary IDE Controller (AT Drive)
1FB-22FAvailable
230-277Available
278-27FParallel Port 2
280-2F7Available
2F8-2FFSerial Port 2
300-36FAvailable
370-377Alt. Floppy Disk Controller
378-37FParallel Port 1
380-3AFAvailable
3B0-3BB and 3BFMono/VGA mode video
3BC-3BEReserved for parallel port
3C0-3DFVGA registers
3E0-3EFAvailable
3F0-3F7Primary Floppy disk controller
3F8-3FFSerial port 1
4D0Master PIC Edge/Level Trigger register
I/O Map (cnnt’d)
Address (hex)Device
4D1Slave PIC Edge/Level Trigger register
CF8-CFBPCI configuration address register (32 bit I/O only)
CF9Reset Control register (8 bit I/O)
CFC-CFFPCI configuration data register
400Smbus base address for SB.
500GPIO Base Address for SB
800PM (ACPI) Base Address for SB
860Alias for ICH TCO base address.
0A00~0AFFReserved for SIO functions base address (ex: PME /GPIO etc)
4700~47FFTPM (SLB9635) configuration registers
![The image features an icon of a white document with a folded top corner and faint horizontal lines. A large red checkmark is superimposed on the document. Below the document graphic is the text 'NOTE:' in bold, black capital letters.](.express-mc800-50-1j017-1000-200-1/3283d5e8561e48666f9b333d1706e5b94a514d5e0584b8c43ff8b50e397b7ccb.jpg) \* DWORD access only \*\* Byte access only # 7.4 Interrupt Request (IRQ) Lines PIC Mode
IRQ#Typical Interrupt ResourceConnected to PinAvailable
0Counter 0N/ANo
1Keyboard controllerN/ANo
2Cascade interrupt from slave PICN/ANo
3Serial Port 2 (COM2) / PCI / ISAIRQ3 via SERIRQ, IRQ3 at ISA busNote (1)
4Serial Port 1 (COM1) / PCI / ISAIRQ4 via SERIRQ, IRQ4 at ISA busNote (1)
5Parallel Port 2 (LPT2) / PCI / ISAIRQ5 via SERIRQ, IRQ5 at ISA busNote (1)
6Floppy Drive ControllerIRQ6 via SERIRQNo
7Parallel Port 1 (LPT1) / PCI / ISAIRQ7 via SERIRQ, IRQ7 at ISA busNote (1)
8Real-time clockN/ANo
9SCI / PCIIRQ9 via SERIRQ, IRQ9 at ISA busNote (1), (2)
10PCI / ISAIRQ10 via SERIRQ, IRQ10 at ISA busNote (1)
11PCI / ISAIRQ11 via SERIRQ, IRQ11 at ISA busNote (1)
12PS/2 Mouse / PCI / ISAIRQ12 via SERIRQ, IRQ12 at ISA busNote (1)
13Math ProcessorN/ANo
14Primary IDE controller / PCI / ISAIRQ14 via SERIRQ, IRQ14 at ISA busNote (1)
15Secondary IDE controller / PCI / ISAIRQ15 via SERIRQ, IRQ15 at ISA busNote (1)
![The image displays a graphic icon. The top portion shows a white rectangular shape resembling a page of lined paper with a large red checkmark overlaid on the left side. Below the icon, the word 'NOTE' appears in black, bold, uppercase letters. To the right of the word 'NOTE,' there are three small, dark dots arranged in a vertical column.](.express-mc800-50-1j017-1000-200-1/7f58c4a6e3c9767f894460628d18fbbbb4e3e58324a4e502a331509c175b90dc.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. (2) BIOS does not open IRQ 9 setting for ISA bus. APIC Mode
IRQ#Typical Interrupt ResourceConnected to PinAvailable
0Counter 0N/ANo
1Keyboard controllerN/ANo
2Cascade interrupt from slave PICN/ANo
3Serial Port 2 (COM2) / PCI / ISAIRQ3 via SERIRQ, IRQ3 at ISA busNote (1)
4Serial Port 1 (COM1) / PCI / ISAIRQ4 via SERIRQ, IRQ4 at ISA busNote (1)
5Parallel Port 2 (LPT2) / PCI / ISAIRQ5 via SERIRQ, IRQ5 at ISA busNote (1)
6Floppy Drive ControllerIRQ6 via SERIRQNo
7Parallel Port 1 (LPT1) / PCI / ISAIRQ7 via SERIRQ, IRQ7 at ISA busNote (1)
8Real-time clockN/ANo
9SCI / PCIIRQ9 via SERIRQ, IRQ9 at ISA busNote (1), (2)
10PCI / ISAIRQ10 via SERIRQ, IRQ10 at ISA busNote (1)
11PCI / ISAIRQ11 via SERIRQ, IRQ11 at ISA busNote (1)
12PS/2 Mouse / PCI / ISAIRQ12 via SERIRQ, IRQ12 at ISA busNote (1)
13Math ProcessorN/ANo
14Primary IDE controller / PCI / ISAIRQ14 via SERIRQ, IRQ14 at ISA busNote (1)
15Secondary IDE controller / PCI / ISAIRQ15 via SERIRQ, IRQ15 at ISA busNote (1)
16N/APCI Slot 1, VGA controller, UHCI Controller 3Yes
17N/APCI Slot INT BYes
18N/APCI Slot INT C, UHCI Controller 2,EHCI Controller 1, SMBUS, SATA controller 0Yes
19N/APCI Slot INT D, UHCI Controller 1Yes
20N/AN/ANo
21N/AUHCI Controller 4, ICH8M HDANo
22N/AN/ANo
23N/AUHCI Controller 0, EHCI Controller 0,ICH8M internal GBE controllerNo
![The image displays a graphic icon of a white document page with faint horizontal gray lines and a large red checkmark overlaid on it. Below the document graphic, the text 'NOTE:' is written in black capital letters.](.express-mc800-50-1j017-1000-200-1/c9d839e921530511a4b8538d650f6e0883fa375a89748a8bbf69ca231347325d.jpg) (1) These IRQs can be used for PCI devices when onboard device is disabled. (2) BIOS does not open IRQ 9 setting for ISA bus. 7.5 PCI Configuration Space Map
Bus #Device #Function #RoutingDescription
00h00h00hN/AIntel 965 GME GMCH Host-Hub Interface Bridge
0001H00HInternalP.E.G. Root Port
0200H0FFHN/AP.E.G. Port
00h02h00hInternalIntel Integrated Graphics Device
00h02h01hInternalIntel Integrated Graphics Device (Function 1)
00h19h00hInternalGbE Controller
00h1Ah00hInternalIntel USB UHCI Controller 3
00h1Ah01hInternalIntel USB UHCI Controller 4
00h1Ah07hInternalIntel USB EHCI Controller 1
00h1Bh00hInternalHigh Definition Audio controller
00h1Ch00hInternalIntel ICH Express Root port 0
00h1Ch01hInternalIntel ICH Express Root port 1
00h1Ch02hInternalIntel ICH Express Root port 2
00h1Ch03hInternalIntel ICH Express Root port 3
00h1Ch04hInternalIntel ICH Express Root port 4
00h1Ch05hInternalIntel ICH Express Root port 5
00h1Dh00hInternalIntel USB UHCI Controller 0
00h1Dh01hInternalIntel USB UHCI Controller 1
00h1Dh02hInternalIntel USB UHCI Controller 2
00h1Dh07hInternalIntel USB EHCI Controller
00h1Eh00hN/AIntel Hub Interface to PCI Bridge
00h1Fh00hN/AIntel LPC Interface Bridge
00h1Fh01hInternalIntel IDE Controller
00h1Fh02hInternalIntel SATA controller
00h1Fh03hInternalIntel SMBus Controller
00h1Fh06hInternalThermal Controller
02h00h0FFhInternalPCIE Port #0
03h00h0FFhInternalPCIE Port #1
04h00h0FFhInternalPCIE Port #2
05h00h0FFhInternalPCIE Port #3
06h00h0FFhInternalPCIE Port #4
01h04h0FFhPIROA-PIRQDExternal PCI Slot 1
7.6 PCI Interrupt Routing Map
PIRQABCDEFGH
INT LineINTAINTBINTCINTD
PEG Root PortXXXX
VGAX
SATA ControllerX
IDE ControllerX
SMBUSX
Thermal ControllerX
UHCI 0X
UHCI 1X
UHCI 2X
UHCI 3X
UHCI 4X
EHCI 0X
EHCI 0X
HDAX
Intel GBEX
PCIE port 0X
PCIE port 1X
PCIE port 2X
PCIE port 3X
PCIE port 4X
PCI Slot1 AD20INTAINTBINTCINTD
PCI Slot2 AD21INTBINTCINTDINTA
PCI Slot3 AD22INTACINTDINTAINTB
PCI Slot4 AD23INTDINTAINTBINTC
7.7 SMBus Address
Address (hex)Device
D2hClock Gen
DChClock Buffer
A0hDIMM A
A2hDIMM B
AChEEPROM
30hLM95235
5ChLM87
7.8 SMBus Slave Device Address
Address (hex)FunctionDevice
A0DDR2 channel ADDR2 socket
A2DDR2 channel BDDR2 socket
D2Clock generatorCK505
5CHardware MonitorLM87
18CPU Temperature SensorLM95235
4ETPMSLB9635
9CWDTF75111RG
ACEEPROM Backup24C02
# 8 BIOS Setup The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility. # 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL or Delete to run Setup > 3. After you press the < Delete > key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST38410A 007A](.express-mc800-50-1j017-1000-200-1/66228ed15baeeb5955cd5bf645f6b7d0153e30366d4fa52a292b88c32dc80acb.jpg) ![The image displays a graphic of a white document sheet featuring a large red checkmark. Beneath this icon, the text 'NOTE:' is printed in black capital letters.](.express-mc800-50-1j017-1000-200-1/d6eff2379549b28bf76807453e0b0e17645564ad3ac823b448ddbae83a6259f6.jpg) In most cases, the < Delete > key is used to invoke the setup screen. There are several cases that use other keys, such as < F1 >, < F2 >, and so on. # 8.1.1 Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.
BIOS SETUP UTILITY
MainAdvancedPowerBootSecurity Exit
System OverviewUse [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use $\left\lbrack +\right\rbrack$ or [-] to configure system Time.
AMIBIOS Version :08.00.14 Build Date:08/04/08 ID :MC800001 Processor Speed :255MHz Count :255 System Memory Size :2040MB System Time [00:27:46] System Date [Tue 01/01/2002]
← Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit
# 8.1.2 Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on. ![The flowchart is organized hierarchically from top to bottom.\n\n1. **Top Level:** A box labeled **BIOS Setup Utility** sits at the top center. An arrow points downward from it to the text **Screens**.\n2. **Screen Navigation:** To the left of the screen sequence, a box labeled **Left and Right Keys to Select a Setup Screen** has a dotted arrow pointing toward a horizontal row of five boxes connected by double-headed arrows: **Screen 1**, **Screen 2**, **Screen 3**, **Screen 4**, and **Screen 5**.\n3. **Items Level:** An arrow points downward from **Screens** to the text **Items**.\n4. **Item Selection (Fields):** Below **Items**, there is a block of boxes labeled **±**.\n * A box labeled **Tab Key to Select Fields** has a dotted arrow pointing to the first **±** box in the top row.\n * The **±** boxes are arranged in two rows (top and bottom) of three boxes each.\n * A box labeled **± To Change Field Values** has a dotted arrow pointing to the third **±** box in the top row.\n * Vertical arrows (one pointing down, one pointing up) are placed between the top and bottom rows of **±** boxes.\n * A box labeled **Up and Down Keys to Select a Setup Item** has a dotted arrow pointing to the vertical arrows.\n * To the far left, the text **Fields** is accompanied by a bracket pointing to the group of **±** boxes.](.express-mc800-50-1j017-1000-200-1/615f70a54e17ed3e20922d05942bead47e374759db197181a05d45043c8c6b39.jpg) ![The image displays a white document icon with the top right corner folded down. A large red checkmark is centered on the document. Below the icon, the text 'NOTE:' appears in black, capitalized letters.](.express-mc800-50-1j017-1000-200-1/c861e2215bea68ce09f67e1d821db9e93390a16dfa6f32a597ae07fc9a520c64.jpg) There is a hot key legend located in the right frame on most setup screens.
Hot KeyDescription
→←Left/Right The Left and Right < Arrow > keys allow you to select a setup screen.For example: Main screen, Advanced screen, Chipset screen, and so on.
↑↓Up/Down The Up and Down < Arrow > keys allow you to select a setup item or sub-screen.
+-Plus/Minus The Plus and Minus < Arrow > keys allow you to change the field value of a particular setup item.For example: Date and Time.
TabThe < Tab > key allows you to select setup fields.
![An icon depicting a white document with a folded top-right corner. A large red checkmark is centered on the upper half. Below the checkmark, the text 'NOTE:' is written in bold black capital letters.](.express-mc800-50-1j017-1000-200-1/91d5131c5239535568b53b86d65cd91e92a54d0687afb9c9f64276c6829f5bfe.jpg) The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings. # Hot Key Description F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen. General Help
←→Select Screen↓↑Select Item
+-Change ScreenEnterGo to Sub Screen
PGDNNext PagePGUPPrevious Page
HomeGo to Top of the ScreenEndGo to Bottom of Screen
F2/F3Change ColorsF7Discard Changes
F8Load Failsafe DefaultsF9Load Optimal Defaults
F10Save and ExitESCExit
[ok] F10 The < F10 > key allows you to save any changes you have made and exit Setup. Press the < F10 > key to save your changes. The following screen will appear: Save configuration changes and exit now? [ok] [Cancel] Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the < Esc > key to exit the setup without saving your changes. The following screen will appear: Discard changes and exit setup now? [ok] [Cancel] Press the < Enter > key to discard changes and exit. You can also use the < Arrow > key to select Cancel and then press the < Enter > key to abort this function and return to the previous screen. Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. # 8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.
BIOS SETUP UTILITY
MainAdvancedPCIPnPBootSecurityChipset Exit
System OverviewUse [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use $\left\lbrack +\right\rbrack$ or $\left\lbrack -\right\rbrack$ to configure system Time.
AMIBIOS Version :08.00.14 Build Date:04/08/08 ID :MC800001 Processor Speed :255MHz Count :255 System Memory Size :511MB System Time [00:55:48] System Date [Tue 01/01/2002]
← Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit
# 8.2.1 System Time/System Date Use this option to change the system time and date. Highlight System Time or System Date using the < Arrow > keys. Enter new values using the keyboard. Press the < Tab > key or the < Arrow > keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. ![The image displays a graphic of a white document with horizontal gray lines, resembling a notepad. A large, bold red checkmark is drawn diagonally across the document. Below the document, the text 'NOTE:' is written in black capital letters.](.express-mc800-50-1j017-1000-200-1/e125c86bbd3e660f955744b61e04be63a00a1bb5ecfbfe1cb3b5dcbf350b0814.jpg) The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00. # 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the < Arrow > keys. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages.
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Advanced SettingsConfigure CPU.
CPU Configuration Chipset Configuration Video Function Configuration IDE Configuration Onboard Devices Configuration USB Configuration PCI Express Configuration PCIPnP Configuration Remote Access Configuration Trusted ComputingSelect Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
![The image displays a standard safety warning sign. It features a red triangle containing a large black exclamation point in the center. Directly below the triangle is a white rectangular box with the text 'WARNING!' printed in bold, black, capital letters.](.express-mc800-50-1j017-1000-200-1/c657a5fd6bbde62c03d06225acf546e75949bc2cb325d8aaacb8931eefe55961.jpg) Setting incorrect or conflicting values in Advanced BIOS Setup may cause system malfunctions. # 8.3.1 CPU Configuration # CPU Configuration Settings You can use this screen to select options for the CPU Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. An example of the CPU Configuration screen is shown below.
BIOS SETUP UTILITY
Advanced
Configure advanced CPU settings Module Version:3F.03When disabled, force the XD feature flag to always return 0.
Manufacturer:Intel
Frequency :255MHz FSB Speed :92MHz Cache L1 :0 KB Cache L2 :0 KB Ratio Actual Value:11
Execute-Disable Bit Capability [Enabled] Core Multi-Processing [Enabled] Intel(R) SpeedStep(tm) tech [Enabled] MPS Revision [1.4]← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Execute-Disable Bit Capability This item allows you to Enable/Disable the “Execute-Disable Bit” function. Intel’s Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the process disables code execution, preventing damage and worm propagation. To use Execute Disable bit you must have a PC or server with a processor with Execute Disable Bit capability and a supporting operating system. # Core Multi-Processing This item is visible depending on the CPU being used on the board. Multi-core capability of the CPU is enabled/disabled by this setting if the CPU supports this feature. # Intel® SpeedStep™ tech This item allows you to Enable/Disable Intel® SpeedStep™ Technology. This function switches both voltage and frequency in tandem between high and low levels in response to processor load. # MPS Revision This item allows you to select which MPS revision to use for the operating system. # 8.3.2 Chipset Configuration # Chipset Configuration Settings Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the < Arrow > keys. The Chipset BIOS Setup screen is shown below.
BIOS SETUP UTILITY Advanced
Advanced Chipset SettingsOptions
DRAM Frequency [Auto] Configure DRAM Timing by SPD [Enabled] Memory Hole [Disabled] POST code Route [PCI]Auto 400 MHz 533 MHz ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# MCH Thermal Management This item allows you to enable or disable the MCH thermal management function. # Thermal Management on DIMM This item allows you to enable or disable the thermal management function for DIMMs. # DRAM Frequency This item allows you to set the DRAM frequency. You can let the frequency be set by BIOS automatically or configure it manually. # Memory Hole Decide whether to open a memory hole or not. Memory hole will locate at 15MB-16MB of system memory. # ACPI APIC support This item is used to enable or disable the APIC (Advanced Programmable Interrupt Controller). Enabling APIC mode will expand available IRQ resources for the system. # APIC ACPI SCI IRQ This item allows you to enable or disable the APIC ACPI SCI interrupt. # HDA Controller Set this value to enable or disable the HDA Controller. # 8.3.3 Video Function Configuration # Video Function Configuration Settings You can use this screen to select options for Video Function configuration settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The video function BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Advanced
Video Function ConfigurationSelect which graphics controller to use as the primary boot device.
Boots Graphic Adapter Priority [PEG/PCI] Internal Graphics Mode Select [Enabled, 8MB] DUMT Mode Select [DUMT Model] DUMT/FIXED Memory [256MB]
Boot Display Device [CRT] Local Flat Panel Scaling [Auto] Flat Panel Type [800x600 18Bit] TV Standard [VBIOS-Default]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Boots Graphic Adapter Priority Selects which graphics controller to use as the primary boot display device. IGD=Integrated Graphic device. PEG/PCI means external PCI/express graphic device. # Internal Graphics Mode Select Select amount of system memory which used by the internal graphics device. # DVMT Mode Select DVMT mode is memory that is dynamically allocated based on memory requests made by application and that are released back to the system once the requesting application has been terminated. Fixed mode is non-contiguous page locked memory allocated during driver initialization to provide a static amount of memory # DVMT Mode Select DVMT mode is memory that is dynamically allocated based on memory requests made by application and that are released back to the system once the requesting application has been terminated. Fixed mode is non-contiguous page locked memory allocated during driver initialization to provide a static amount of memory # DVMT/FIXED Memory Allows you to select the maximum amount of graphics memory to be shared with the system memory. # Boot Display Device This item allows the user to configure the type of external display used. # Local Flat Panel Scaling Allows you to determine how various resolutions appear on your LCD display.
OptionDescription
AutoThe scaling unit on your graphics card will rescale the image before it reaches your LCD display. This option results in the best image quality.
Forced ScalingThis option will maintain the original aspect ratio of the chosen resolution and display it with black bars to the sides/above/below the on-screen image as required.
DisabledThe image isn't scaled at all, but instead your LCD display will run at its maximum resolution and the image will display in the centre of your LCD display. This may result in a black border around the sides of the image.
# Flat Panel Type When LVDS is selected from Boot Display Device, this option allows you to set the resolution and timing settings for output to the LVDS interface. Options: 640x480 18-bit, 800x600 18-bit, 1024x768 18-bit, 1280x1024 18-bit, 640x480 24-bit, 800x600 24-bit, 1024x768 24-bit, 1280x1024 24-bit # TV Standard This field allows you to set the appropriate standard for your TV. Options: VBIOS-Default, NTSC, PAL # 8.3.4 IDE Configuration # IDE Configuration Settings You can use this screen to select options for the IDE Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. An example of the IDE Configuration screen is shown below.
BIOS SETUP UTILITY Advanced
IDE ConfigurationOptions
ATA/IDE Configuration Legacy IDE Channels[Compatible] [SATA Pri, PATA Sec]Disabled Compatible Enhanced
► Primary IDE Master: [Not Detected]
► Primary IDE Slave: [Not Detected]
► Secondary IDE Master: [Not Detected]
► Secondary IDE Slave: [Not Detected]
► Third IDE Master: [Not Detected]
► Third IDE Slave: [Not Detected]
► Fourth IDE Master: [Not Detected]
► Fourth IDE Slave: [Not Detected]
Hard Disk Write Protect[Disabled]← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
IDE Detect Time Out (Sec)[35]
ATA(PI) 80Pin Cable Detection[Host & Device]
# ATA/IDE Configuration This item specifies whether the IDE channels should be initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced. # Legacy IDE Channels When running in compatible mode, the SATA channel can be configured as a legacy IDE channel. The location of the IDE channel is selectable. # Primary, Secondary, ... IDE Master/Slave Select one of the hard disk drives to configure it. Press < Enter > to access its sub menu. # Hard Disk Write Protect Set this value to Enabled to prevent the hard disk drive from being overwritten. # IDE Detect Time Out This field allows you to set the time to stop searching for IDE devices within the specified number of seconds. # ATA(PI)80Pin Cable Detection Selects the method used to detect the type of IDE cable used. # 8.3.5 Onboard Device Configuration # Onboard Device Configuration Settings You can use this screen to specify options for the onboard device configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The screen is shown below.
BIOS SETUP UTILITY
Advanced
Onboard Devices ConfigurationOptions
GbE LAN Boot [Disabled] GbE Wake Up From S5 [Disabled] ► SuperIO ConfigurationEnabled Disabled
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# GBE LAN Boot Set this option to enable/disable the onboard LAN’s PXE ROM to enable boot from LAN. Setting to Disabled can shorten the POST time by not initializing the LAN PXE ROM if boot from LAN is not needed. Enable if boot from LAN function is required. # GBE Wake up From S5 Set this option to enable remote wake up of the system by LAN. # SuperIO Configuration The SuperIO Configuration screen is a sub-menu of Onboard Device Configuration. You can use this screen to select options for the Super IO settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The screen is shown below. ![The image displays a graphic icon featuring a white document with faint horizontal lines and a large red checkmark overlaid on it. Below the document icon is the text 'NOTE:' in capital letters.](.express-mc800-50-1j017-1000-200-1/df910d4b8ba21623b8b799e21860af73e3b267c43bb7668d00f95e5f55fe4f3c.jpg) This item visible only when a SuperIO device is present on the carrier board.
BIOS SETUP UTILITY
Advanced
Configure Win627 Super IO ChipsetFloppy A [Disabled]OnBoard Floppy Controller [Enabled]Serial Port1 Address [3F8/IRQ4]Serial Port2 Address [Disabled]Parallel Port Address [378]Parallel Port Mode [Normal]Parallel Port IRQ [IRQ7]► Hardware Health ConfigurationSelect the type offloppy driveconnected to thesystem.< Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Floppy Drive A: Move the cursor to these fields via up and down < arrow > keys. Select the floppy type. The Optimal and Fail-Safe settings for floppy drive A: is 1.44 MB 3½”.
OptionDescription
DisabledSet this value to prevent the use of the selected floppy disk drive channel. This option should be set if no floppy disk drive is installed on the specified channel.
360 KB 5 1⁄4"Set this value if the floppy disk drive attached to the corresponding channel is a 360 KB 51⁄4" floppy disk drive.
1.2 MB 5 1⁄4"Set this value if the floppy disk drive attached to the corresponding channel is a 1.2 MB 51⁄4" floppy disk drive.
720 KB 3 1⁄2"Set this value if the floppy disk drive attached to the corresponding channel is a 720 KB 31⁄2" floppy disk drive.
1.44 MB 3 1⁄2"Set this value if the floppy disk drive attached to the corresponding channel is a 1.44 MB 31⁄2" floppy disk drive. This is the default setting for Floppy Drive A.
2.88 MB 3 1⁄2"Set this value if the floppy disk drive attached to the corresponding channel is a 2.88 MB 31⁄2" floppy disk drive.
# Onboard Floppy Controller Set this value to Enable/Disable the onboard floppy controller function. # Serial Port1 Address This option specifies the base I/O port address and Interrupt Request address of serial port 1.
OptionDescription
DisabledSet this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable.
3F8/IRQ4Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt address.
3E8/IRQ4Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 4 for the interrupt address.
2F8/IRQ3Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 3 for the interrupt address.
2E8/IRQ3Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 3 for the interrupt address.
# Serial Port2 Address This option specifies the base I/O port address and Interrupt Request address of Serial Port2. The settings of Serial Port2 are the same as Serial Port1. However, the setting used by Serial Port1 will not be available for Serial Port2. For example, if Serial Port1 uses 3F8/IRQ4, the option, the 3F8/IRQ4 will not appear in the options of Serial Port2. # Parallel Port Address This option specifies the base I/O port address request of the parallel port. # Parallel Port Mode This option specifies the parallel port mode.
OptionDescription
NormalSet this value to allow the standard parallel port mode to be used.
EPPThe parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data transfer driven by the host device.
ECPThe parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per second. ECP provides symmetric Bidirectional communication.
EPP+ECPAllows the parallel port to support both the ECP and EPP modes simultaneously.
# Parallel Port IRQ This option specifies the IRQ used by the parallel port.
OptionDescription
IRQ5Set this value to allow the serial port to use Interrupt 5.
IRQ7Set this value to allow the serial port to use Interrupt 7. The majority of parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.
# Hardware Health Configuration This screen displays the current fan speed.
Hardware Health Event Monitoring
Fan1 Speed :0 RPM Fan2 Speed :6750 RPM Fan3 Speed :2766 RPM
# 8.3.6 USB Configuration # USB Configuration Settings You can use this screen to specify options for the USB Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The screen is shown below.
BIOS SETUP UTILITY Advanced
USB ConfigurationOptions
Module Version - 2.24.3-13.4Disabled 2 USB Ports 4 USB Ports 6 USB Ports 8 USB Ports
USB Devices Enabled : 1 Keyboard, 1 Drive
USB Functions [8 USB Ports]
USB 2.0 Controller [Enabled]
USB 2.0 Controller Mode [HiSpeed]
Legacy USB Support [Enabled]
USB Keyboard Legacy Support [Enabled]
USB Mouse Legacy Support [Enabled]← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
USB Storage Device Support [Enabled]
USB Beep Message [Enabled]
BIOS EHCI Hand-Off [Enabled]
► USB Mass Storage Device Configuration
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# USB Functions The item determines the number of functional USB ports. # USB 2.0 Controller The option allows you to enable/disable the EHCI (USB 2.0) controller. # USB 2.0 Controller Mode The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps). # Legacy USB Support Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is not enabled, any attached USB mouse or keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or keyboard can control the system even when there are no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB Support (see below).
OptionDescription
DisabledSet this value to prevent the use of any USB device in DOS or during system boot.
EnabledSet this value to allow the use of USB devices during boot and while using DOS.
AutoThis option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS.
# USB Storage Device Support Allows you to enable or disable the USB storage device support. # USB Beep Message Allows you to enable/disable the beep during USB device enumeration. # BIOS EHCI hand-off Allows you to enable support for operating systems without EHCU hand-off feature. # USB Mass Storage Reset Delay This item allows you to set the reset delay for USB mass storage devices. # USB Mass Storage Device Configuration This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on the USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). ). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.
BIOS SETUP UTILITY
Advanced
USB Mass Storage Device Configuration USB Mass Storage Reset Delay [20 Sec] Device #1 USB Flash Disk Emulation Type [Auto]Number of seconds POST waits for the USB mass storage device after start unit command. ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.3.7 PCI Express Configuration You can use this screen to specify options for the PCI Express Configuration settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The screen is shown below.
PCI Express ConfigurationEnable/Disable PCI Express L0s and L1 link power states.
Active State Power-Management[Disabled]
PEG Port[Auto]
PEG Force x1[Disabled]
PCIE Ports 0-3 Configuration[Four x1 Ports]
PCIE Port 0[Auto]
PCIE Port 1[Auto]
PCIE Port 2[Auto]
PCIE Port 3[Auto]
PCIE Port 4[Auto]
PCIE Port 5[Disabled]
PCIE High Priority Port[Disabled]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
PCIE Port 0 IOxAPIC Enable[Disabled]
PCIE Port 1 IOxAPIC Enable[Disabled]
PCIE Port 2 IOxAPIC Enable[Disabled]
PCIE Port 3 IOxAPIC Enable[Disabled]
PCIE Port 4 IOxAPIC Enable[Disabled]
PCIE Port 5 IOxAPIC Enable[Disabled]
# Active State Power-Management This option allows you to enable/disable the Active State Power Management (ASPM) function. ASPM is a PCIe power management specification. # PEG Port Configuration # PEG Port This option allows you to select whether to use the onboard graphics processor or the PCI Express graphics card.
OptionDescription
DisabledThe system boots up using the onboard graphics processor.
EnabledIf BIOS detects that a PEG card is installed, the system boots up using that card. Otherwise, it defaults to the onboard graphics processor.
# PEG Force x1 When using a PCI Express x16 graphics card, disable this function. When using a PCEe x1 board on this interface, enable this function. # PCIE Ports 0-3 Configuration Allows you to configure the PCIE0\~PCIE3 of the South Bridge as one x4 slot or four x1 slots. # PCIE High Priority Port This function is used to select a PCIE port as high priority port. Transactions on this port have higher priority than other ports. # PCIE Port (0-5) IOxAPIC Enable This function is used to control the availability of the PCIE Port 0\~5 IOxAPIC. # 8.3.8 PCIPnP Configuration # PCIPnP Configuration Settings You can display a Plug and Play BIOS Setup option by highlighting it using the < Arrow > keys to select an item. The Plug and Play BIOS Setup screen is shown below. ![BIOS SETUP UTILITY\nAdvanced\nAdvanced PCI/PnP Settings\nWARNING: Setting wrong values in below sections\nmay cause system to malfunction.\nClear NURAM (No)\nPlug & Play O/S (No)\nPCI Latency Timer (64)\nAllocate IRQ to PCI VGA (Yes)\nIRQ3 (Reserved)\nIRQ4 (Reserved)\nIRQ5 (Available)\nIRQ7 (Reserved)\nIRQ9 (Available)\nIRQ10 (Available)\nIRQ11 (Available)\nIRQ14 (Available)\nIRQ15 (Available)\nClear NURAM during\nSystem Boot.\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.express-mc800-50-1j017-1000-200-1/61789df8d4d8253699addfec16f75bef92bd07738173232b99169aa1ca29ea1a.jpg) # Clear NVRAM This option clears ESCD (Extended System Configuration Data) information in NVRAM. # Plug & Play O/S When set to "Yes" and a Plug and Play operating system is installed, the operating system configures the Plug and Play devices not required for boot. # PCI Latency Timer Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of all PCI devices on the PCI bus. # Allocate IRQ to PCI VGA When set to "Yes", the BIOS will assign an IRQ for a PCI VGA card. # IRQ Set this value to allow the IRQ settings to be modified. Available - This setting allows the specified IRQ to be used by a PCI/PnP device. Reserved - This setting allows the specified IRQ to be used by a legacy ISA device. # 8.3.9 Remote Access Configuration Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access. ![The image displays a white document icon with a large red checkmark superimposed on the upper portion. Faint horizontal lines run across the document. Below the icon, the word 'NOTES' appears in black capital letters.](.express-mc800-50-1j017-1000-200-1/dd929cea385e39d8a32f3b3e44fedfa7fe33ace94265bcc4fd27f7b5897a057d.jpg) This item visible only when a SuperIO device is present on the carrier board.
BIOS SETUP UTILITY
Advanced
Configure Remote Access type and parameters
Remote Access[Enabled]
Serial port number[COM1]
Base Address, IRQ[3F8h, 4]
Serial Port Mode[115200 8,n,1]
Flow Control[None]
Redirection After BIOS POST[Always]
Terminal Type[ANSI]
VT-UTF8 Combo Key Support[Enabled]
Sredir Memory Display Delay[No Delay]
Select Remote Access type.
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
# Remote Access Select this option to Enable or Disable the BIOS remote access feature. ![The image shows a digital icon of a white document with faint horizontal lines and a large red checkmark in the center. Below the document icon is the text 'NOTE:' in bold, black capital letters.](.express-mc800-50-1j017-1000-200-1/afbf53a19ad4ac54867818efcc3c18b2325a93f3329aedefd234ede7e514afda.jpg) Enabled Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot. # Serial Port Number Select the serial port you want to use for the remote access interface. You can set the value for this option to either COM1 or COM2. ![The image displays a digital icon of a white document with a folded upper-right corner. A large red checkmark is superimposed over the document. Below the document graphic, the text 'NOTE:' appears in black, uppercase letters.](.express-mc800-50-1j017-1000-200-1/389a0acbf6bea6ed25232a3d850a0f0287594f39b006320fd0134bf3b357c414.jpg) If you have changed the resource assignment of the serial ports in Advanced>Onboard Device Configuration>SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the available Remote Access options. # Serial Port Mode Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1. # Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software. # Redirection After BIOS POST This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.
OptionDescription
DisabledSet this value to turn off the redirection after POST
Boot LoaderSet this value to allow the redirection to be active during POST and Boot Loader.
AlwaysSet this value to allow the redirection to be always active.
# Terminal Type This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8. # VT-UTF8 Combo Key Support This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled. # Sredir Memory Display Delay This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec. # 8.3.10 Trusted Computing Trusted computing is an industry standard to make personal computers more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support.
BIOS SETUP UTILITY
Advanced
Trusted ComputingEnable/Disable TPM TCG (TPM 1.1/1.2) supp in BIOS
TCG/TPM SUPPORT [Yes]
TPM Enable/Disable Status [No State]
TPM Owner Status [No State]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.4 Power Management Select the Power tab from the setup screen to enter the power management BIOS Setup screen. You can select any of the items in the left frame of the screen, such as ACPI Configuration, to go to the sub menu for that item. The power management BIOS Setup screen is shown below.
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Power Management SettingsSection for Advanced ACPI Configuration.
ACPI Configuration APM Configuration Hardware Health ConfigurationSelect Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.4.1 ACPI Configuration # Advanced ACPI Configuration You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. The screen is shown below.
BIOS SETUP UTILITY
Power
ACPI SettingsEnable RSDP pointers to 64-bit Fixed System Description Tables. Di ACPI version has some
ACPI Version Features [ACPI v2.0]
ACPI APIC support [Enabled]
AMI OEMB table [Enabled]
Suspend mode [S3 (STR)]
Repost Video on S3 Resume [No]
USB Device Wakeup From S3/S4 [Disabled]
Headless mode [Disabled]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# ACPI Version Features The item allows you to select the ACPI version. # ACPI APIC Support This option is used to enable or disable the Advanced Programmable Interrupt Controller (APIC) for PC2001 compliance. Enabling APIC mode will expand available IRQs resources for the system. # AMI OEMB Table Include the OEMB table pointer to R(X)SDT pointer lists. # Suspend mode This item allows you to select the APCI state to be used for system suspend. # Repost Video on S3 Resume Determines whether to invoke VGA BIOS POST on S3/STR resume. This setting is only visible when Suspend Mode is set to S3 (STR). # USB Device Wakeup from S3/S4 This option allows a USB device to wake up the system from S3/S4. # Headless Mode This is a server-specific feature. A headless server is one that operates without a keyboard, monitor or mouse. To run in headless mode, both BIOS and operating system (e.g. Windows Server 2003) must support headless operation # 8.4.2 APM Configuration Select the Advanced tab from the setup screen to enter the APM Configuration Setup screen. You can display a Power Management/APM Setup option by highlighting it using the < Arrow > keys.
BIOS SETUP UTILITY
Power
APM ConfigurationEnable or disable APM.
Power Management/APM [Enabled]
Video Power Down Mode [Suspend]
Hard Disk Power Down Mode [Suspend]
Suspend Time Out [Disabled]
Power Button Mode [On/Off]
Restore on AC Power Loss [Last State]
Advanced Resume Event Controls
Resume On Ring [Disabled]← Select Screen
Resume On LAN [Disabled]↑↓ Select Item
Resume On PME# [Disabled]+- Change Option
Resume On RTC Alarm [Disabled]F1 General Help
F10 Save and Exit
ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Power Management/APM Set this value to Enable or Disable Power Management/APM (Advanced Power Management) features. # Video Power Down Mode This option specifies the power management state that the video subsystem enters when the BIOS places it in a power saving state after the period of inactivity specified in Suspend Time Out has expired. The options are Disabled and Suspend. # Hard Disk Drive Power Down Mode This option specifies the power management state that the hard disk drive enters after the period of hard drive inactivity specified in Suspend Time Out has expired. # Suspend Time Out This option specifies the length of time the system waits before it enters suspend mode. The options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min, and 60 Min. # Power Button Mode This feature allows users to configure the Power Button function.
OptionDescription
On/OffTurn the system On/Off when the power button is pressed.
SuspendThe system goes into suspend mode or resumes from suspend mode when power button is pressed.
# Restore on AC Power Loss Determines what state the computer enters when AC power is restored after a power loss. The options for this value are Last State, Power On and Power Off.
OptionDescription
Power OffThe system remains powered off when AC power is restored.
Power OnThe system powers on after AC power is restored.
Last StateThe system will power off/on depending on the last system power state when AC power is restored.
# Advanced Resume Event Controls These settings specify which events will generate a system wake event. The available events are LAN, PME# and RTC Alarm. The options are Enabled and Disabled. # 8.4.3 Hardware Health Configuration
BIOS SETUP UTILITY
Advanced
H/W Health Function [Enabled]Enables Hardware Health Monitoring Device.
Module CPU Temperature Reading :66°C/150°F
VCORE :1.135 V +3.30V :3.206 V +1.8V :1.840 V +5V :4.812 V +12V :12.090 V
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# H/W Health Function This screen displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. The options are Enabled and Disabled. # 8.5 Boot Setup Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display an Boot BIOS Setup option by highlighting it using the < Arrow > keys. The Boot Settings screen is shown below:
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Boot SettingsConfigure Settings during System Boot.
► Boot Settings Configuration
1st Boot Device [Removable Dev.]
2nd Boot Device [CD/DVD]
3rd Boot Device [Hard Drivel]
4th Boot Device [USB:USB Flash Disk]
5th Boot Device [Network]
► Hard Disk Drives
► Removable Drives
► CD/DVD Drives
► USB Drives
► Network Drives← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Boot Device Priority Set the boot device options to determine the sequence in which the computer checks which device to boot from. # Boot Device Groups The Boot devices are listed in groups by device type. First press <Enter> to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or <PageUp>, <PageDown> key to move it up/down in the priority list. For example, USB storage disks will be listed as “USB Drives” in the sub-menu. Only the first device in each device group will be available for selection in the Boot Device Priority option. # Boot Settings Configuration Use this screen to select options for the Boot Settings Configuration. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The screen is shown below.
BIOS SETUP UTILITYBoot
Boot Settings Configuration
Quick Boot[Enabled]
Quiet Boot[Disabled]
AddOn ROM Display Mode[Force BIOS]
Bootup Num-Lock[On]
PS/2 Mouse Support[Auto]
Wait For 'F1' If Error[Enabled]
Hit 'DEL' Message Display[Enabled]
Interrupt 19 Capture[Disabled]
# Quick Boot Disabled - Set this value to allow the BIOS to perform all POST tests. Enabled - Set this value to allow the BIOS to skip certain POST tests to boot faster. # Quiet Boot Disabled - Set this value to allow the computer system to display the POST messages. Enabled - Set this value to allow the computer system to display the OEM logo. # AddOn ROM Display Mode This feature controls the display of ROM messages from the BIOS of add-on devices like graphics cards or SATA controllers during the boot sequence. When set to Force BIOS, AddOn ROM messages will be forced to display during the boot sequence. When set to Keep Current, AddOn ROM messages will only be displayed if the third-party manufacturer had set the add-on device to do so. # Bootup Num-Lock Set this value to allow the Number Lock setting to be modified during boot up. Off - This option does not enable the keyboard Number Lock automatically. To use the 10-keys on the keyboard, press the Number Lock key located on the upper left-hand corner of the 10-key pad. The Number Lock LED on the keyboard will light up when the Number Lock is engaged. On - Set this value to allow the Number Lock on the keyboard to be enabled automatically when the computer system is boot up. This allows the immediate use of 10-keys numeric keypad located on the right side of the keyboard. To confirm this, the Number Lock LED light on the keyboard will be lit. # PS/2 Mouse Support Allows you to enable/disable PS/2 mouse support. # Wait for ‘F1’ If Error If this option is set to Disabled, AMIBIOS does not wait for you to press the <F1> key after an error message. # Hit ‘DEL’ Message Display When set to Enabled, the system displays the message "Press DEL to run Setup during POST". # Interrupt 19 Capture Interrupt 19 is the software interrupt that handles the boot disk function. When enabled, this feature allows the AddOn ROM of these host adaptors to “capture” Interrupt 19 during the boot process so that drives attached to these adaptors can function as bootable disks. In addition, it allows you to gain access to the host adaptor’s AddOn ROM setup utility, if one is available. When disabled, the AddOn ROM of these host adaptors will not be able to “capture” Interrupt 19. Therefore, you will not be able to boot operating systems from any bootable disks attached to these host adaptors. Nor will you be able to gain access to their AddOn ROM utilities. # 8.6 Security Setup
BIOS SETUP UTILITY
Main Advanced Power Boot Security Exit
Security SettingsInstall or Change the password.
Supervisor Password :Not Installed User Password :Not Installed
Change Supervisor Password Change User Password Clear User Password
Select Screen ↑↓ Select Item Enter Change F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.6.1 Password Support # Two Levels of Password Protection The BIOS provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password. The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure. # Remember the Password Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM. Select Security Setup from the Setup main BIOS setup menu. Security Setup options, such as password protection and virus protection, are described in this section. To access the sub menu for the following items, select the item and press < Enter >: - Change Supervisor Password - Change User Password - Clear User Password # Supervisor Password Indicates whether a supervisor password has been set. # User Password Indicates whether a user password has been set. # Change Supervisor Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the supervisor password. # Change User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the user password. # Clear User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to clear the user password. # 8.6.2 Change Supervisor Password Select Change Supervisor Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.3 Change User Password Select Change User Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 8.6.4 Clear User Password Select Clear User Password from the Security Setup menu and press < Enter >. Clear New Password [Ok] [Cancel] Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes. # 9 BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMIBIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMIBIOS checkpoints. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2001 American Megatrends, Inc.\nBIOS Date: 10/01/01 12:39:39 Ver: 08.00.03\nPentium (R) III Processor, 933MHz\nPress DEL to run Setup\nsplay CHECKING: 09560-5\nCheckpoint Di\nEVALUATION COPY, NOT FOR SALE\n(C) American Megatrends Inc.,\n63-0100-000001-00101111-100101-015-0AAXT004-Y2KC\n6B38](.express-mc800-50-1j017-1000-200-1/215bb13b2c29748d462a0a6ee1ffaf52a7283e5f4fa4a4ac8baecc3bd9159604.jpg) # 9.1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS: ![The image displays an icon of a white document with a folded top-right corner and faint horizontal lines representing text. A large red checkmark is superimposed over the document. Below the document, the text 'NOTE:' is written in bold, black capital letters.](.express-mc800-50-1j017-1000-200-1/c89420ffbf25a6c27959e871202f1b20ca568f7a79ec97faa348ac4ce0ac0520.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.
CheckpointDescription
Before D0If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point. Stack will be enabled from this point.
D0Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU critical initialization. Early chipset initialization is done.
D1Early super I/O initialization is done including RTC and keyboard controller. Serial port is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled.
D2Verify the boot block checksum. System will hang here if checksum is bad.
D3Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing module not executed, start memory refresh and do memory sizing in Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly.
D6Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.
D7Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.
D8The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.
DARestore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.
DCSystem is waking from ACPI S3 state
E1-E8, EC-EEOEM memory detection/configuration error. This range is reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.
# 9.2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS: ![The image displays an icon of a white document with a folded corner and a large red checkmark. Below the document, the text 'NOTE:' appears in black capital letters.](.express-mc800-50-1j017-1000-200-1/11cc8cbc650b5b1d9cd974a8d94d48d3a98816dbeced97ca9e67887fdf988094.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.
CheckpointDescription
E0Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9Set up floppy controller and data. Attempt to read from floppy.
EAEnable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EBDisable ATAPI hardware. Jump back to checkpoint E9.
EFRead error occurred on media. Jump back to checkpoint EB.
F0Search for pre-defined recovery file name in root directory.
F1Recovery file not found.
F2Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3Start reading the recovery file cluster by cluster.
F5Disable L1 cache.
FACheck the validity of the recovery file configuration to the current configuration of the flash part.
FBMake flash write enabled through chipset and OEM specific method. Detect proper flash part.Verify that the found flash part size equals the recovery file size.
F4The recovery file size does not equal the found flash part size.
FCErase the flash part.
FDProgram the flash part.
FFThe flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware.Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
# 9.3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS: ![The image displays a white document icon with horizontal lines representing text, featuring a large red checkmark overlaid on the right side.](.express-mc800-50-1j017-1000-200-1/5be1ecc54ef99873cb001029427e33bea28da1107ffa38a7dc809525c980f3ff.jpg) NOTE: Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.
CheckpointDescription
03Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system
05Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
07Fixes CPU POST interface calling pointer.
08Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.
C0Early CPU Init Start -- Disable Cache - Init Local APIC
C1Set up boot strap processor Information
C2Set up boot strap processor for POST
C5Enumerate and set up application processors
C6Re-enable cache for boot strap processor
C7Early CPU Init Exit
OAInitializes the 8042 compatible Key Board Controller.
OBDetects the presence of PS/2 mouse.
OCDetects the presence of Keyboard in KBC port.
OETesting and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
13Early POST initialization of chipset registers.
20Relocate System Management Interrupt vector for all CPU in the system.
24Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this checkpoint.
2AInitializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
2CInitializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2EInitializes all the output devices.
POST Code Checkpoints cont’d:
CheckpointDescription
31Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33Initializes the silent boot module. Set the window for displaying text information.
37Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point.
39Initializes DMAC-1 & DMAC-2.
3AInitialize RTC date/time.
3BTest for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.
3CMid POST initialization of chipset registers.
40Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA...etc.
52Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.
60Initializes NUM-LOCK status and programs the KBD typematic rate.
75Initialize Int-13 and prepare for IPL detection.
78Initializes IPL devices controlled by BIOS and option ROMs.
7CGenerate and write contents of ESCD in NVRam.
84Log errors encountered during POST.
85Display errors to the user and gets the user response for error.
87Execute BIOS setup if needed / requested. Check boot password if installed.
8CLate POST initialization of chipset registers.
8DBuild ACPI tables (if ACPI is supported)
8EProgram the peripheral parameters. Enable/Disable NMI as selected
90Initialization of system management interrupt by invoking all handlers. Please note this checkpoint comes right after checkpoint 20h
A1Clean-up work needed before booting to OS.
A2Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.
A4Initialize runtime language module. Display boot option popup menu.
A7Displays the system configuration screen if enabled. Initialize the CPU's before boot, which includes the programming of the MTRR's.
A9Wait for user input at config display if needed.
AAUninstall POST INT1Ch vector and INT09h vector.
ABPrepare BBS for Int 19 boot. Init MP tables.
ACEnd of POST initialization of chipset registers. De-initializes the ADM module.
B1Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.
00Passes control to OS Loader (typically INT19h).
# 9.4 OEM POST Error Checkpoints Checkpoints from the range 61h to 70h are reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next. # 9.5 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed: ![The image features a white document icon with a folded upper-right corner and faint horizontal lines representing text. A large red checkmark is superimposed on the left side of the document. Below the icon, the text 'NOTE:' is displayed in bold, black capital letters.](.express-mc800-50-1j017-1000-200-1/92e64cbba2dc58f26c5b9f5bf8c8543f5d2c9728a997d97990f14a4095fc43d5.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.
CheckpointDescription
2AInitialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI- PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.
38Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.
While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: # HIGH BYTE XY The upper nibble ‘X’ indicates the function number that is being executed. ‘X’ can be from 0 to 7. 0 = func#0, disable all devices on the BUS concerned. 1 = func#1, static devices initialization on the BUS concerned. 2 = func#2, output device initialization on the BUS concerned. 3 = func#3, input device initialization on the BUS concerned. 4 = func#4, IPL device initialization on the BUS concerned. 5 = func#5, general device initialization on the BUS concerned. 6 = func#6, error reporting for the BUS concerned. 7 = func#7, add-on ROM initialization for all BUSes. 8 = func#8, BBS ROM initialization for all BUSes. The lower nibble ‘Y’ indicates the BUS on which the different routines are being executed. ‘Y’ can be from 0 to 5. 0 = Generic DIM (Device Initialization Manager). 1 = Onboard System devices. 2 = ISA devices. 3 = EISA devices. 4 = ISA PnP devices. 5 = PCI devices. # 9.6 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events: ![The image shows a white document icon with a folded top-left corner and faint horizontal lines. A large red checkmark is superimposed on the document. Below the icon is the text 'NOTE:' in black capital letters.](.express-mc800-50-1j017-1000-200-1/ecd246028a68171658a125ede2fef94469811f1c4c5dd1210f53a8ab974f15be.jpg) Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices. # 9.7 Boot Block Beep Codes
No. of BeepsDescription
1Insert diskette in floppy drive A:
2‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3Base Memory error
4Flash Programming successful
5Floppy read error
6Keyboard controller BAT command failed
7No Flash EPROM detected
8Floppy controller failure
9Boot Block BIOS checksum error
10Flash Erase error
11Flash Program error
12‘AMIBOOT.ROM’ file size error
13BIOS ROM image mismatch (file layout does not match image present in flash device)
# 9.8 POST BIOS Beep Codes
No. of BeepsDescription
1Memory refresh timer error.
2Parity error in base memory (first 64KB block)
3Base memory read/write test error
4Motherboard timer not operational
5Processor error
68042 Gate A20 test error (cannot switch to protected mode)
7General exception error (processor exception interrupt error)
8Display memory error (system video adapter)
9AMIBIOS ROM checksum error
10CMOS shutdown register read/write error
11Cache memory test failed
# 9.9 Troubleshooting POST BIOS Beep Codes
No. of BeepsDescription
1, 2 or 3Reseat the memory, or replace with known good modules.
4-7, 9-11Fatal error indicating a serious problem with the system. Consult your system manufacturer.Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.- If beep codes are generated when all other expansion cards are absent, consult your system manufacturer's technical support.- If beep codes are not generated when all other expansion cards are absent, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem happens again. This will reveal the malfunctioning card.
8If the system video adapter is an add-in card, replace or reseat the video adapter. If the video adapter is an integrated part of the system board, the board may be faulty.
# Important Safety Instructions For user safety, please read and follow all instructions, warnings, cautions, and notes marked in this manual and on the associated equipment before handling/operating the equipment. f Read these safety instructions carefully. f Keep this user’s manual for future reference. f Read the specifications section of this manual for detailed information on the operating environment of this equipment. f When installing/mounting or uninstalling/removing equipment: \- Turn off power and unplug any power cords/cables. f To avoid electrical shock and/or damage to equipment: - Keep equipment away from water or liquid sources; - Keep equipment away from high heat or high humidity; - Keep equipment properly ventilated (do not block or cover ventilation openings); - Make sure to use recommended voltage and power source settings; - Always install and operate equipment near an easily accessible electrical socket-outlet; - Secure the power cord (do not place any object on/over the power cord); - Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and, - If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. f Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. f A Lithium-type battery may be provided for uninterrupted, backup or emergency power. ![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the sign, the text 'CAUTION:' is printed in black, uppercase letters.](.express-mc800-50-1j017-1000-200-1/676dcb4dc63259cd6668e9e4de9992f8002f0631bf9f0e4cfd4fcb75a55b3487.jpg) Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries according to the instructions. f Equipment must be serviced by authorized technicians when: - The power cord or plug is damaged; - Liquid has penetrated the equipment; - It has been exposed to high humidity/moisture; - It is not functioning or does not function according to the user’s manual; - It has been dropped and/or damaged; and/or, - It has an obvious sign of breakage. # Getting Service Contact us should you require any service or assistance. # ADLINK Technology Inc. Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan ؀קᗼխࡉؑ৬ԫሁ166ᇆ 9ᑔ Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com # Ampro ADLINK Technology Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology Beijing Address: ࣫ҀᏖ⍋⎔ऎϞഄϰ䏃 1োⲜ߯ ࡯ࡼ ໻ॺ Eᑻ 801ᅸ (100085) Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing 100085, China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com # ADLINK Technology Shanghai Address: Ϟ⍋Ꮦⓩ⊇⋒催⾥ᡔᓔথऎ䩺∳䏃 333 ো 39 ᐶ 4 ሖ (200233) Tel: +86-21-6495-5210 Fax: +86-21-5450-0414 Email: market@adlinktech.com # ADLINK Technology Shenzhen Address: ⏅ഇᏖफቅऎ⾥ᡔುफऎ催ᮄफϗ䘧᭄ᄫᡔᴃು A1 ᷟ 2 ὐ C ऎ (518057) 2F, C Block, Bld. A1, Cyber-Tech Zone, Gao Xin Ave. Sec 7, High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com # ADLINK Technology Inc. (German Liaison Office) Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: emea@adlinktech.com # ADLINK (French Liaison Office) Address: 15 rue Emile Baudot, 91300 MASSY Cedex, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com # ADLINK Technology Japan Corporation Address: 151-0072 ᧲੩ㇺᷦ⼱඙ᐈ䊱⼱ 1-1-2 ᦺᣣ↢๮ᐈ䊱⼱䊎䊦 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan Tel: +81-3-4455-3722 Fax: +81-3-5333-6040 Email: japan@adlinktech.com # ADLINK Technology Inc. (Korean Liaison Office) Address: 昢殾柢 儛單割 嚂笊壟 60-12 壟昷捒娯 4 猻 402 笾 No.402, Dongsung B/D, 60-12, Nonhyeon-Dong Gangnam-gu, Seoul, 135-010, Korea. Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com # ADLINK Technology Singapore Pte Ltd. Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com # ADLINK Technology Singapore Pte Ltd. (Indian Liaison Office) Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email: india@adlinktech.com ![The image displays a black circle containing the universal recycling symbol. Inside the circle are three white arrows arranged in a triangular formation, each arrow pointing clockwise and appearing to chase the next in a continuous loop. The arrows have a stylized design with parallel lines near their tails. There is no text present.](.express-mc800-50-1j017-1000-200-1/4132aa8766a9b38ee36d2995265266ba7fc0a865356acbf36e4dab81e1cfbbc0.jpg) [🔗 Link to the original document](.express-mc800-50-1j017-1000-200-1/express-mc800-50-1j017-1000-200-1.pdf)