# Express-RLP User’s Guide intel ![Close-up of a green printed circuit board with integrated circuits and memory chips (no readable text or symbols)](.express-rlp-manual-230411/bdfc9ac6176770eecae4a899d561bf604df026e0ec420f65c184e00dec179c44.jpg) Revision History

Revision	Description	Date	Author
1.0	Initial release	2023-04-11	CC

# Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![The image displays a standard yellow triangular warning sign with a thick black border. Centered inside the triangle is a large black exclamation mark. The sign is set against a white background, flanked by vertical black bars on either side.](.express-rlp-manual-230411/ff24f63baa5dd7610ce56779f445ff8511ebfc21b19e90a0be1e30e757f16b11.jpg) California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. ![The image displays a black line drawing of a wheeled trash bin. A large black 'X' is superimposed over the bin. At the bottom of the image is a solid black rectangle. No legible text is present.](.express-rlp-manual-230411/7dda0b8e2f8cfce2ce41f871ad61a0422ca988856bece6e99f03c08f5496d4e9.jpg) # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. # Copyright © 2023 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image displays a digital icon of a document. It features a red outline shaped like a piece of paper with a folded bottom-right corner. Inside the outline, there are three horizontal red lines stacked vertically, centered within the page area. The background is white.](.express-rlp-manual-230411/8d17d3aa1fe58b2f7c04353f092ca68891ed4205fb6aad44730e0ab9615e21bd.jpg) Note: This information adds clarity or specifics to text and illustrations. ![A yellow triangular warning sign featuring a black exclamation point in the center.](.express-rlp-manual-230411/6b9df858808f290dba66ceca1e90d835b2c5f8f6d5ea65107bb67102737f7bd7.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image displays a red, triangular warning sign containing a centered white exclamation mark.](.express-rlp-manual-230411/9ddacb1ab3e5578dc6621c608300c8b57db479a05b4e49fdec895cfc00ed41dc.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Getting Service Ask an Expert: http://askanexpert.adlinktech.com # ADLINK Technology, Inc. No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5706 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. # Table of Contents Revision History .. Preface . Table of Contents.. List of Figures ... . 9 1. Introduction .. .10 2. Specifications... .11 2.1. Core System... .11 2.2. Video .. ... 12 2.2.1 Display Interface Support .... ..13 2.3. Audio .... ... 13 2.4. Expansion Busses .. ... 14 2.5. Ethernet .... ... 15 2.6. Multi I/O and Storage .. .15 2.7. Trusted Platform Module (TPM).. ... 16 2.8. SEMA Board controller.. ..17 2.9. Debug... ..17 2.10. Power.... ... 17 2.11. Mechanical and Environmental... ... 18 3. Block Diagram... .19 4. Pinout and Signal Descriptions ....... ...20 4.1. Pin Summary.... ..20 4.2. Signal Terminology Descriptions .. ..25 4.3. AB Connector Signal Descriptions.. ..26 4.3.1 Audio.. ..26 4.3.2 Analog VGA... ..27 4.3.3 LVDS or eDP .. ..28 4.3.4 Gigabit Ethernet ... ..31 4.3.5 SATA .. ..32 4.3.6 PCI Express .. ..33 4.3.7 LPC Bus ... ..35 4.3.8 USB.... ..36 4.3.9 SPI Bus (BIOS only). ..37 4.3.10 Miscellaneous... .... 38 4.3.11 SMBus ... ..39 4.3.12 I2C Bus... ..39 4.3.13 General Purpose I/O (GPIO)... .... 40 4.3.14 Serial Interface Signals.. .... 40 4.3.15 Power and System Management... .... 41 4.3.16 Power and Ground . .... 42 4.4. CD Connector Signal Descriptions .. ... 43 4.4.1 USB 3.0 Extensions .. .... 43 4.4.2 PCI Express .. .... 44 4.4.3 DDI1 Port ... .... 45 4.4.4 DDI2 Port ... .... 48 4.4.5 DDI3 Port .. ..51 4.4.6 PCIe Graphics Port (PEG)... ..54 4.4.7 Module Type Definition... ..57 4.4.8 Power and Ground .. ..58 5. Additional Features.. ...59 5.1. Module Feature Locations. ..59 5.2. Debug Connector ... ..60 5.3. Status LEDs... ..61 5.4. Exception Codes.. ..62 5.5. Fan Connector... ..63 5.6. BIOS Default Reset Button.. ..64 5.7. BIOS Boot Select .. ..65 6. BIOS Checkpoints, Beep Codes .... ...66 7. Software Support .......... ...67 7.1. Windows 10 IoT Enterprise 64-bit .. ..67 7.2. Yocto Linux 64-bit.... ..67 8. Mechanical and Thermal.. ..68 8.1. Module Dimensions.. ..68 8.2. Thermal Solutions... ..69 8.2.1 Heatspreader: HTS.. ... 69 8.2.2 Heatsink: THS ... ..70 8.2.3 Heatsink High Profile: THSH .. ..71 8.2.4 Heatsink with Fan: THSF..... ..... 72 # List of Figures Figure 1 – Module function diagram... ..19 Figure 2 - Module rear side row and pin numbering ....... ...20 Figure 3 – Module feature locations (top side) ... ..59 Figure 5 – Express-RLP and Debug Module .... ..60 Figure 6 – Module mechanical dimensions ... ..68 Figure 7 – Heatspreader: HTS.. ...69 Figure 8 – Heatsink: THS... ...70 Figure 9 – Heatsink High Profile: THSH .. .71 Figure 10 – Heatsink with Fan: THSF.... ...72 # 1. Introduction The Express-RLP is a COM.0 R3.1 compliant COM Express® Basic Size Type 6 module based on 13th Gen Intel® Core™ and Intel® Celeron® SoC utilizing Intel’s advanced hybrid architecture (formerly “Raptor Lake-P”). It features up to 6 Performance-cores (P-cores) for IoT workloads, maximum responsiveness and 8 Efficient-cores (E-cores) for offload multi-tasking at background, and is integrated with up to 96 Intel® Iris® Xe high performance graphics cores that boost productivity and fueling IoT innovation across a wide variety of deployments. Typical industries in need of such high performance, low power characteristics include industrial automation and control, medical ultra sound, image processing and analysis, high-speed video encoding and streaming, predictive traffic analysis, and multi camera-based AI. The Express-RLP supports up to 64GB (2x 32GB) DDR5 memory, maximum 4800 MT/s memory frequency at two SODIMM sockets, and suits power envelopes ranging across 15, 28, and 45W, making it well suited for mission-critical applications for both stationary and mobile edge use cases. The integrated Intel® Iris® Xe Graphics includes features such as OpenGL 4.5, DirectX 12, OpenCL 2.1/2.0/1.2, Intel® Clear Video HD Technology, and DirectX Video Acceleration (DXVA) support for full H.265/HEVC 10-bit, VP9 hardware codecs. In addition, High Dynamic Range is supported for enhanced picture color and quality, and digital content protection has been upgraded to HDCP 2.3. Graphics outputs include LVDS and three DDI ports supporting HDMI/DVI/DisplayPort and eDP/VGA as a build option, with a maximum of four 4K displays supported. In addition, maximum 2x USB4 that can transfer media and data through a single tunnel is a build option supported by project basis in place of DDI 1/2. The Express-RLP is specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced development time. Adding to the onboard integrated graphics, a multiplexed 16 PCIe Gen4 graphics bus at one x8 plus two x4 configuration is available for discrete graphics expansion. Input/output features include up to eight PCIe Gen3 lanes via PCIe switch that can be used for NVMe SSD, allowing application access to the highest speed storage solutions, as well as a single onboard 2.5Gigabit Ethernet port with optional Time Sensitive Network (TSN) support, four USB 3.2 Gen2/2.0 ports, four USB 2.0 ports, and two SATA 6 Gb/s ports. Optional onboard PCIe NVMe SSD is offered by project basis. Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer. # 2. Specifications # 2.1. Core System # CPU 13th Gen Intel® Core™ Processor (formerly Raptor Lake-P) • Intel® Core™ i7-13800HE, 6P+8E/20T, 24MB, 45W(35W cTDP), Iris Xe 96EU • Intel® Core™ i5-13600HE, 4P+8E/16T, 18MB, 45W(35W cTDP), Iris Xe 80EU • Intel® Core™ i3-13300HE, 4P+4E/12T, 12MB, 45W(35W cTDP), UHD 48EU • Intel® Core™ i7-1370PE, 6P+8E/20T, 24MB, 28W(20W cTDP), Iris Xe 96EU • Intel® Core™ i5-1350PE, 4P+8E/16T, 12MB, 28W(20W cTDP), Iris Xe 80EU • Intel® Core™ i3-1320PE, 4P+4E/12T, 12MB, 28W(20W cTDP), UHD 48EU • Intel® Core™ i7-1365UE, 2P+8E/12T, 12MB, 15W(12W cTDP), Iris Xe 96EU • Intel® Core™ i5-1345UE, 2P+8E/12T, 12MB, 15W(12W cTDP), Iris Xe 80EU • Intel® Core™ i3-1315UE, 2P+4E/8T, 10MB, 15W(12W cTDP), UHD 64EU • Intel® Celeorn™ U300E, 1P+4E/5T, 8MB, 15W(12W cTDP), UHD 48EU • Intel® Core™ i7-13800HRE, 6P+8E/20T, 24MB, 45W(35W cTDP), Iris Xe 96EU (TCC/TSN, IBECC capable) • Intel® Core™ i5-13600HRE, 4P+8E/16T, 18MB, 45W(35W cTDP), Iris Xe 80EU (TCC/TSN, IBECC capable) • Intel® Core™ i3-13300HRE, 4P+4E/12T, 12MB, 45W(35W cTDP), UHD 48EU (TCC/TSN, IBECC capable) • Intel® Core™ i7-1365URE, 2P+8E/12T, 12MB, 15W(12W cTDP), Iris Xe 96EU (TCC/TSN, IBECC capable) • Intel® Core™ i5-1345URE, 2P+8E/12T, 12MB, 15W(12W cTDP), Iris Xe 80EU (TCC/TSN, IBECC capable) • Intel® Core™ i3-1315URE, 2P+4E/8T, 10MB, 15W(12W cTDP), UHD 64EU (TCC/TSN, IBECC capable) Supporting: Intel® VT (including VT-x, VT-d, VT-x with Extended Page Tables), Intel® HT Technology, Intel® SSE4.2, Intel® 64 Architecture, Intel® Turbo Boost Technology 2.0, Intel® AVX512-VNNI, Intel® TXT, Execute Disable Bit, Intel® Data Protection Technology with Intel® Secure Key, Intel® AES-NI (availability of features may vary between processor SKUs) Note: Standard offering will be based on 45W SKU. SKUs with other power envelopes and with TCC/TSN-, IBECC-capabilities will be available by project basis. Please contact your local ADLINK representative for details. # Memory Up to 64GB (2x 32GB) non-ECC DDR5 in two SODIMM sockets (one on top, one on bottom), maximum 32GB per socket, maximum 4800 MT/s. ![The image shows an icon of a white document page with rounded corners and a folded bottom-right corner. It is outlined with a thick red border. Inside the white area, there are two horizontal red lines centered horizontally, resembling text.](.express-rlp-manual-230411/da4b9be9f1a5cf5b9098c173ccbc14fcd9aa4dd69e2df77ac24b942f7794c825.jpg) Note: It is recommended to check that the bottom side specifications are suitable for your application purposes. # Embedded BIOS AMI Aptio V UEFI with CMOS backup in 32 MB SPI BIOS, dual BIOS by build option # 2.2. Video # GPU Intel® Iris Xe Graphics architecture with up to 96 execution units # Feature Support • 4 independent and simultaneous combinations of DisplayPort/HDMI/LVDS/eDP/VGA and display alternative mode through USB4/Thunderbolt4 graphics outputs (4x 4K @60Hz, up to 8K@60Hz) (eDP optional in place of LVDS, VGA optional in place of DDI 3) • Playback of high-definition content including Blu-ray Disc and Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D) • DirectX Video Acceleration (DXVA) support for accelerated video processing • HEVC/H.265, H.264, M/JPEG, MPEG2, AV1, WMV9, VP9 HW decode HEVC/H.265, H.264, JPEG, VP9 HW encode, up to 8K60 HEVC • Advanced Scheduler 2.0, 1.0, XPDM support • DirectX up to 12 • OpenGL up to 4.6 and ES 2.0 support • OpenCL up to 2.1 support ![The image displays a red outline icon resembling a document or memo. It is shaped like a square piece of paper with the bottom right corner folded over. Inside the white background of the shape, there are two horizontal red lines; the top line is shorter than the bottom line.](.express-rlp-manual-230411/cff8031a117d0e6cab08164140fd7a2133ecdd24f5abb38c850c2cb9c03fe77d.jpg) Note: Availability of features is dependent on the operating system used (Windows 10 64-bit, Linux 64-bit). # 2.2.1 Display Interface Support LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, supports DE mode and Hsync/Vsync mode. Max. resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported. eDP: eDP 1.4b up to 4 lane support, in place of LVDS (BOM option), up to 4096x2304@60Hz bpp with DSC DDI x3: Digital Display Ports (DDI) support DisplayPort 1.4a, HDMI 2.0b or DVI VGA: VGA BOM option support in place of DDI 3; max. resolution 1920x1200@60Hz ![The image displays a red-outlined icon of a document or page with a folded bottom-right corner. Inside the white square shape are two horizontal red lines centered vertically.](.express-rlp-manual-230411/3bbed4c2c92362bb35d3701c3be1a62196061015d8cdb8f11b6e220640486bce.jpg) Note: USB4 is a build option (HW and BIOS) supported by project basis in place of DDI channels. Maximum 2x USB4 by using DDI 1 and DDI 2 channels. USB4 support also requires re-timer and PD on carrier. # 2.3. Audio Intel® HD Audio integrated Located on carrier Express-BASE6 or Express-BASE6 R3.1 (ALC886 standard support) # 2.4. Expansion Busses 1 PCI Express x8 Gen4 (45W CPU only): PEG0-7 (configurable to 1 x8). Gen4 support dependent on carrier design. 2 PCI Express x4 Gen4 : PEG8-11 and PEG12-15 (configurable to 2 x4). Gen4 support dependent on carrier design. 8 PCI Express x1 Gen3: Lanes 0-3 (configurable to 4 x1, 2 x2, 1 x4, 1 x2 + 2 x1) and Lanes 4-7 (configurable to 4 x1, via PCIe switch) Other: SMBus (system), I2 C (user), LPC bus (via eSPI to LPC bridge IC) # 2.5. Ethernet 2.5GbE Intel® Ethernet Controller I225 Series (V, IT or LM version) Supports up to 2.5GbE and 1000/100/10 Mbit/s connections IT version supports TSN feature on Linux OS, GbE0\_SDP available if TSN support enabled # 2.6. Multi I/O and Storage # USB 4 2x USB4: build option (HW and BIOS) supported by project basis in place of DDI channels. Maximum 2x USB4 by using DDI 1 and DDI 2 channels. USB4 support also requires re-timer and PD on carrier. ![The image displays a red outline icon of a document. Inside the document shape are two horizontal lines representing text, and the bottom-right corner is curled upward.](.express-rlp-manual-230411/cc4bbcc8f6b74b202669d019453c5f6654950b4d330ebad2c38bf9b4dd3bdc22.jpg) Note: Capable of TBT4. Please contact your local ADLINK representative for details. # USB 4x USB 3.2 Gen2/2.0/1.1 (USB 0,1,2,3), 4x USB 2.0/1.1 (USB 4,5,6,7) SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling ![](.express-rlp-manual-230411/6897fa180faa90a694b7c402eb99a333532c33626adce870157b39ee4681e4e8.jpg) Note: Carrier board must be designed for Gen2 operation. USB 0,1,2,3 are backward compatible with USB 2.0/1.1. # SATA 2x SATA 6Gb/s (SATA 0,1) ![](.express-rlp-manual-230411/f6777e87a13aa22d734098f51a3436d7f9702c8c7a0343793d1e155d3a907dc8.jpg) Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board # GPIO or SD 4 GPO and 4 GPI (GPI with interrupt) # On-board Storage Soldered type PCIe NVMe SSD, available capacities: 60GB/120GB/240GB. Build option support by project basis PCIe NVMe SSD co-lay 1 PCI Express x4 Gen4 : PEG12-15 ![](.express-rlp-manual-230411/6d4e593ddacce4cdff9056e1c6a019d39b51b046ac0914c9007110b29902fc31.jpg) Note: For the NVMe SSD build option, DIMM support is limited to 2 slots. Please contact your local ADLINK representative for details. # UART Two UART interfaces SER0 and SER1 RX/TX on module Console Redirection via COM 1 or COM 2 selectable in BIOS Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

COM Port	Description	IRQ	Address	Console Redirection Support
COM 1	Supported by module (SER0, A98/A99), via embedded controller	4	0x3F8	Yes
COM 2	Supported by module (SER1, A101/A102), via embedded controller	3	0x2F8	Yes
COM 3	Supported by Super I/O (W83627DHG) on carrier board	5	0x240	Yes
COM 4	Supported by Super I/O (W83627DHG) on carrier board	7	0x248	Yes

![](.express-rlp-manual-230411/aa3d96d7fd5d18d02e60ba8065c740dbad995c2c9f3ecca03b5c2e7d726cfb6d.jpg) Note: SER0, SER1 from SoC HSUART are BOM option support by project basis # 2.7. Trusted Platform Module (TPM) Chipset: Infineon solution Type: TPM 2.0 (SPI bus based) # 2.8. SEMA Board controller Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2 C, failsafe BIOS (dual BIOS, opt. support), watchdog timer and fan control. # 2.9. Debug 30-pin flat cable connector for use with DB-30 x86 debug module Supports embedded controller access, SPI BIOS flashing, internal power rail test points, debug LEDs # 2.10. Power Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)

Standard Voltage Input:	ATX: 12V±5% / 5Vsb ±5%	or	AT: 12V±5%
Wide Voltage Input:	ATX: 8.5-20V, 5Vsb ±5%	or	AT: 8.5-20V

Power Management: ACPI 5.0 compliant, Smart Battery support Power States: C1-C6, S0, S1, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5) ECO Mode support for deep S5 for 5Vsb power saving # Power Consumption Please contact your ADLINK representative for the document “COM Express Module Power Consumption”. # 2.11. Mechanical and Environmental # Form Factor and specification PICMG COM Express Rev 3.1 (COM.0 R3.1), Type 6, Basic size 125 x 95 mm # Operating Temperature

Standard	0°C to 60°C (wide voltage input)	Storage: -20°C to 80°C
Extreme Rugged	-40°C to 85°C (selected SKUs, TBC)	Storage: -40°C to 85°C

# Humidity 5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating) # Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# HALT tested Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # 3. Block Diagram PICMG COM.0 R3.1 compliant ![This flowchart centers on a large red block labeled **'13th Gen Intel® Core Processor (Raptor Lake-P)'**.\n\n**Left Column (Memory & Controllers):**\n* **'on-die ECC'** connects to two blocks labeled **'DDR5 SODIMM max. 4800MT/s 8-32GB'**.\n* **'eDP/LVDS'** connects via a dashed box **'eDP x4'** and a blue box **'eDP to LVDS'**.\n* **'VGA'** connects via a dashed box **'DP to VGA'**.\n* **'USB 2.0 Lane 0-7'** connects directly.\n* **'Max. 2.5GbE'** connects via a blue box **'LAN controller i225'**.\n* **'PCIe Lane 0-3'**, **'PCIe Lane 4'**, and **'PCIe Lane 5'** connect via a blue box **'PCIe switch'**.\n* **'SATA 0-1'** and **'SATA 2-3'** connect directly.\n* **'HDA'** connects directly.\n* **'SPI'** connects via a blue box **'BIOS flash'**.\n* **'TPM 2.0'** (blue box) connects to the SPI line, near a dashed box **'BIOS flash'**.\n* **'SMBus'** connects directly.\n* **'I2C'** connects via dashed boxes labeled **'2x I2C'** and **'2x HSUART'**.\n* **'8x GPIO/SDIO'**, **'2x UART/CAN'**, and **'LPC/eSPI'** connect to the bottom section.\n* A dashed box at the bottom reads **'eSPI build option(TBC)'**.\n\n**Right Column (External Ports):**\n* **'TCP 0'** connects to **'DDI/USB4/TBT4 Port 1'**.\n* **'TCP 1'** connects to **'DDI/USB4/TBT4 Port 2'**.\n* **'DDI only Port 3'** connects directly.\n* **'HSIO 0-3'** connects to **'USB 3.x Lane 0'**, **'USB 3.x Lane 1'**, **'USB 3.x Lane 2'**, and **'USB 3.x Lane 3'**.\n* **'1 PCIe Gen3 (HSIO)'** connects to **'PCIe Lane 0-3'**.\n* **'4 PCIe Gen3 (HSIO)'** connects to **'PCIe Lane 4'**.\n* **'1 PCIe Gen3 (HSIO)'** connects to **'PCIe Lane 5'**.\n* **'two x1'** connects to **'PCIe Lane 6-7'**.\n* **'GEN4 x8 (CPU)'** connects to **'PEG Port PCIe 16-23'**.\n* **'GEN4 x4 (CPU)'** connects to **'PCIe 24-27'**.\n* **'GEN4 x4 (CPU)'** connects to **'PCIe 28-31'**.\n* A dashed box at the bottom right reads **'NVMe BGA SSD build option'**.\n\n**Bottom Section:**\n* A blue box labeled **'Embedded Controller'** connects to:\n * A blue box labeled **'eSPI to LPC'**.\n * A blue box labeled **'build option fan connector'**.\n * A blue box labeled **'LM73 (board)'**.](.express-rlp-manual-230411/85d6e661d290b6490beb716faa924de0d30f283d57fca6ae5d219aed5c974cf6.jpg) Figure 1 – Module function diagram # Pinout and Signal Descriptions # 4.1. Pin Summary The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 6 in the PICMG COM.0 R3.1 specification. Signals described in the specification but not supported on the Express-RLP are marked with strikethrough. ![NVMe SSD\noptional\nD1\nCD\nC1\nB1\nAB\nA110\nA1](.express-rlp-manual-230411/79df04c1c7104238518cac4ea61e0c6f94e320cab6ac428b198089c3ffdd7b64.jpg) Figure 2 - Module rear side row and pin numbering

Row A		Row B		Row C		Row D
A1	GND (FIXED)	B1	GND (FIXED)	C1	GND FIXED)	D1	GND FIXED)
A2	GBE0_MDI3-	B2	GBE0_ACT#	C2	GND	D2	GND
A3	GBE0_MDI3+	B3	LPC_FRAME#/ESPI_CS0 $^{1}$	C3	USB_SSRX0-	D3	USB_SSTX0-
A4	GBE0_LINK_MID#	B4	LPC_AD0/ESPI_IO_0 $^{1}$	C4	USB_SSRX0+	D4	USB_SSTX0+
A5	GBE0_LINK_MAX#	B5	LPC_AD1/ESPI_IO_1 $^{1}$	C5	GND	D5	GND
A6	GBE0_MDI2-	B6	LPC_AD2/ESPI_IO_2 $^{1}$	C6	USB_SSRX1-	D6	USB_SSTX1-
A7	GBE0_MDI2+	B7	LPC_AD3/ESPI_IO_3 $^{1}$	C7	USB_SSRX1+	D7	USB_SSTX1+
A8	GBE0_LINK#	B8	LPC_DRQ0#/ESPI_ALERT0#	C8	GND	D8	GND
A9	GBE0_MDI1-	B9	LPC_DRQ1#/ESPI_ALERT1#	C9	USB_SSRX2-	D9	USB_SSTX2-
A10	GBE0_MDI1+	B10	LPC_CLK/ESPI_CK $^{1}$	C10	USB_SSRX2+	D10	USB_SSTX2+
A11	GND (FIXED)	B11	GND (FIXED)	C11	GND (FIXED)	D11	GND (FIXED)
A12	GBE0_MDIO-	B12	PWRBTN#	C12	USB_SSRX3-	D12	USB_SSTX3-
A13	GBE0_MDIO+	B13	SMB_CK	C13	USB_SSRX3+	D13	USB_SSTX3+
A14	GBE0_CTREF	B14	SMB_DAT	C14	GND	D14	GND
A15	SUS_S3#	B15	SMB_ALERT#	C15	USB4_1_LSTX $^{1}$	D15	DDI1_CTRLCLK_AUX+/USB4_1_AUX+ $^{1}$
A16	SATAO_TX+	B16	SATA1_TX+	C16	USB4_1_LSRX $^{1}$	D16	DDI1_CTRLDATA_AUX-/USB4_1_AUX- $^{1}$
A17	SATAO_TX-	B17	SATA1_TX-	C17	USB4_RT_ENA $^{1}$	D17	USB4_PD_I2C_ALERT $^{1}$
A18	SUS_S4#	B18	SUS_STAT#/ESPI_RESET $^{1}$	C18	GND	D18	PMCALERT $^{1}$
A19	SATAO_RX+	B19	SATA1_RX+	C19	PCIE_RX6+ $^{1}$	D19	PCIE_TX6+
A20	SATAO_RX-	B20	SATA1_RX-	C20	PCIE_RX6- $^{1}$	D20	PCIE_TX6-
A21	GND (FIXED)	B21	GND (FIXED)	C21	GND (FIXED)	D21	GND (FIXED)
A22	SATA2_TX+	B22	SATA3_TX+	C22	PCIE_RX7+ $^{1}$	D22	PCIE_TX7+
A23	SATA2_TX-	B23	SATA3_TX-	C23	PCIE_RX7- $^{1}$	D23	PCIE_TX7-
A24	SUS_S5#	B24	PWR_OK	C24	DDI1_HPD	D24	GND
A25	SATA2_RX+	B25	SATA3_RX+	C25	SML0_CLK $^{1}$	D25	GND
A26	SATA2_RX-	B26	SATA3_RX-	C26	SML0_DAT $^{1}$	D26	DDI1_PAIR0+/USB4_1_SSTX0+ $^{1}$
A27	BATLOW#	B27	WDT	C27	SML1_CLK $^{1}$	D27	DDI1_PAIR0-/USB4_1_SSTX0- $^{1}$
A28	(S)ATA_ACT#	B28	HDA_SDIN2/SNDW0_CLK $^{2}$	C28	SML1_DAT $^{1}$	D28	GND
A29	HDA_SYNC	B29	HDA_SDIN1/SNDW0_DAT $^{2}$	C29	USB4_PD_I2C_CLK $^{1}$	D29	DDI1_PAIR1+/USB4_1_SSRX0+ $^{1}$
A30	HDA_RST#	B30	HDA_SDINO	C30	USB4_PD_I2C_DAT $^{1}$	D30	DDI1_PAIR1-/USB4_1_SSRX0- $^{1}$
A31	GND (FIXED)	B31	GND (FIXED)	C31	GND (FIXED)	D31	GND (FIXED)
A32	HDA_BITCLK	B32	SPKR	C32	DDI2_CTRLCLK_AUX+/USB4_2_AUX+1	D32	DDI1_PAIR2+/USB4_1_SSTX1+1
A33	HDA_SDOUT	B33	I2C_CK	C33	DDI2_CTRLDATA_AUX-/USB4_2_AUX-1	D33	DDI1_PAIR2-/USB4_1_SSTX1-1
A34	BIOS_DIS0#/ESPI_SAFS1	B34	I2C_DAT	C34	DDI2_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL
A35	THRMTRIP#	B35	THRM#	C35	USB4_2_LSTX1	D35	USB4_2_LSRX1
A36	USB6-	B36	USB7-	C36	DDI3_CTRLCLK_AUX+	D36	DDI1_PAIR3+/USB4_1_SSRX1+1
A37	USB6+	B37	USB7+	C37	DDI3_CTRLDATA_AUX-	D37	DDI1_PAIR3-/USB4_1_SSRX1-1
A38	USB_6_7_OC#	B38	USB_4_5_OC#	C38	DDI3_DDC_AUX_SEL	D38	GND
A39	USB4-	B39	USB5-	C39	DDI3_PAIR0+	D39	DDI2_PAIR0+/USB4_2_SSTX0+1
A40	USB4+	B40	USB5+	C40	DDI3_PAIR0-	D40	DDI2_PAIR0-/USB4_2_SSTX0-1
A41	GND (FIXED)	B41	GND (FIXED)	C41	GND (FIXED)	D41	GND (FIXED)
A42	USB2-	B42	USB3-	C42	DDI3_PAIR1+	D42	DDI2_PAIR1+/USB4_2_SSRX0+1
A43	USB2+	B43	USB3+	C43	DDI3_PAIR1-	D43	DDI2_PAIR1-/USB4_2_SSRX0-1
A44	USB_2_3_OC#	B44	USB_0_1_OC#	C44	DDI3_HPD	D44	DDI2_HPD
A45	USB0-	B45	USB1-	C45	GP_SPI_CS#2	D45	GND
A46	USB0+	B46	USB1+	C46	DDI3_PAIR2+	D46	DDI2_PAIR2+/USB4_2_SSTX1+1
A47	VCC_RTC	B47	ESPI_EN#1	C47	DDI3_PAIR2-	D47	DDI2_PAIR2-/USB4_2_SSTX1-1
A48	RSMRST_OUT#	B48	USB0_HOST_PRSNT	C48	RSVD	D48	GND
A49	GBE0_SDP1	B49	SYS_RESET#	C49	DDI3_PAIR3+	D49	DDI2_PAIR3+/USB4_2_SSRX1+1
A50	LPC_SERIRQ/ESPI_CS1#1	B50	CB_RESET#	C50	DDI3_PAIR3-	D50	DDI2_PAIR3-/USB4_2_SSRX1-1
A51	GND (FIXED)	B51	GND (FIXED)	C51	GND (FIXED)	D51	GND (FIXED)
A52	PCIE_TX5+1	B52	PCIE_RX5+1	C52	PEG_RX0+	D52	PEG_TX0+
A53	PCIE_TX5-1	B53	PCIE_RX5-1	C53	PEG_RX0-	D53	PEG_TX0-
A54	GPIO	B54	GPO1	C54	TYPE0#	D54	PEG_LANE_RV#
A55	PCIE_TX4+	B55	PCIE_RX4+	C55	PEG_RX1+	D55	PEG_TX1+
A56	PCIE_TX4-	B56	PCIE_RX4-	C56	PEG_RX1-	D56	PEG_TX1-
A57	GND	B57	GPO2	C57	TYPE1#	D57	TYPE2#
A58	PCIE_TX3+	B58	PCIE_RX3+	C58	PEG_RX2+	D58	PEG_TX2+
A59	PCIE_TX3-	B59	PCIE_RX3-	C59	PEG_RX2-	D59	PEG_TX2-
A60	GND (FIXED)	B60	GND (FIXED)	C60	GND (FIXED)	D60	GND (FIXED)
A61	PCIE_TX2+	B61	PCIE_RX2+	C61	PEG_RX3+	D61	PEG_TX3+
A62	PCIE_TX2-	B62	PCIE_RX2-	C62	PEG_RX3-	D62	PEG_TX3-
A63	GPI1	B63	GPO3	C63	GND	D63	GND
A64	PCIE_TX1+	B64	PCIE_RX1+	C64	GND	D64	GND
A65	PCIE_TX1-	B65	PCIE_RX1-	C65	PEG_RX4+	D65	PEG_TX4+
A66	GND	B66	WAKE0#	C66	PEG_RX4-	D66	PEG_TX4-
A67	GPI2	B67	WAKE1#	C67	RAPID_SHUTDOWN	D67	GND
A68	PCIE_TX0+	B68	PCIE_RX0+	C68	PEG_RX5+	D68	PEG_TX5+
A69	PCIE_TX0-	B69	PCIE_RX0-	C69	PEG_RX5-	D69	PEG_TX5-
A70	GND (FIXED)	B70	GND (FIXED)	C70	GND (FIXED)	D70	GND (FIXED)
A71	LVDS_A0+ / eDP_TX2+1	B71	LVDS_B0+	C71	PEG_RX6+	D71	PEG_TX6+
A72	LVDS_A0- / eDP_TX2-1	B72	LVDS_B0-	C72	PEG_RX6-	D72	PEG_TX6-
A73	LVDS_A1+ / eDP_TX1+1	B73	LVDS_B1+	C73	GND	D73	GND
A74	LVDS_A1- / eDP_TX1-1	B74	LVDS_B1-	C74	PEG_RX7+	D74	PEG_TX7+
A75	LVDS_A2+ / eDP_TX0+1	B75	LVDS_B2+	C75	PEG_RX7-	D75	PEG_TX7-
A76	LVDS_A2- / eDP_TX0-1	B76	LVDS_B2-	C76	GND	D76	GND
A77	LVDS_VDD_EN / eDP_VDD_EN1	B77	LVDS_B3+	C77	GND	D77	GND
A78	LVDS_A3+	B78	LVDS_B3-	C78	PEG_RX8+	D78	PEG_TX8+
A79	LVDS_A3-	B79	LVDS_BKLT_EN	C79	PEG_RX8-	D79	PEG_TX8-
A80	GND (FIXED)	B80	GND (FIXED)	C80	GND (FIXED)	D80	GND (FIXED)
A81	LVDS_A_CK+ / eDP_TX3+1	B81	LVDS_B_CK+	C81	PEG_RX9+	D81	PEG_TX9+
A82	LVDS_A_CK- / eDP_TX3-1	B82	LVDS_B_CK-	C82	PEG_RX9-	D82	PEG_TX9-
A83	LVDS_I2C_CK / eDP_AUX+1	B83	LVDS_BKLT_CTRL / eDP_BKLT_CTRL1	C83	GND	D83	GND
A84	LVDS_I2C_DAT / eDP_AUX-1	B84	VCC_5V_SBY	C84	GND	D84	GND
A85	GPI3	B85	VCC_5V_SBY	C85	PEG_RX10+	D85	PEG_TX10+
A86	GP_SPI_MOSI2	B86	VCC_5V_SBY	C86	PEG_RX10-	D86	PEG_TX10-
A87	eDP_HPD	B87	VCC_5V_SBY	C87	GND	D87	GND
A88	PCIE_CK_REF+	B88	BIOS_DIS1#	C88	PEG_RX11+	D88	PEG_TX11+
A89	PCIE_CK_REF-	B89	VGA_RED1	C89	PEG_RX11-	D89	PEG_TX11-
A90	GND (FIXED)	B90	GND (FIXED)	C90	GND (FIXED)	D90	GND (FIXED)
A91	SPI_POWER	B91	VGA_GRN1	C91	PEG_RX12+	D91	PEG_TX12+
A92	SPI_MISO	B92	VGA_BLU1	C92	PEG_RX12-	D92	PEG_TX12-
A93	GPO0	B93	$VGA_HSYNC^1$	C93	GND	D93	GND
A94	SPI_CLK	B94	$VGA_VSYNC^1$	C94	PEG_RX13+	D94	PEG_TX13+
A95	SPI_MOSI	B95	$VGA_I2C_CK^1$	C95	PEG_RX13-	D95	PEG_TX13-
A96	TPM_PP	B96	$VGA_I2C_DAT^1$	C96	GND	D96	GND
A97	TYPE10#	B97	SPI_CS#	C97	GND	D97	GND
A98	SER0_TX	B98	$GP_SPI_MISO^2$	C98	PEG_RX14+	D98	PEG_TX14+
A99	SER0_RX	B99	$GP_SPI_CK^2$	C99	PEG_RX14-	D99	PEG_TX14-
A100	GND (FIXED)	B100	GND (FIXED)	C100	GND (FIXED)	D100	GND (FIXED)
A101	SER1_TX/CAN_TX	B101	FAN_PWMOUT	C101	PEG_RX15+	D101	PEG_TX15+
A102	SER1_RX/CAN_RX	B102	FAN_TACHIN	C102	PEG_RX15-	D102	PEG_TX15-
A103	LID#	B103	SLEEP#	C103	GND	D103	GND
A104	VCC_12V	B104	VCC_12V	C104	VCC_12V	D104	VCC_12V
A105	VCC_12V	B105	VCC_12V	C105	VCC_12V	D105	VCC_12V
A106	VCC_12V	B106	VCC_12V	C106	VCC_12V	D106	$VCC_{12V}^1$
A107	VCC_12V	B107	VCC_12V	C107	VCC_12V	D107	VCC_12V
A108	VCC_12V	B108	VCC_12V	C108	VCC_12V	D108	VCC_12V
A109	VCC_12V	B109	VCC_12V	C109	VCC_12V	D109	VCC_12V
A110	GND (FIXED)	B110	GND (FIXED)	C110	GND (FIXED)	D110	GND (FIXED)

![](.express-rlp-manual-230411/8787f1886b8f5f245132298e8b75db7ee4f234be29bf8ed054dcfc18f286fb5e.jpg) Note: Strike-through entries are not supported functions on this product. PEG 0-7 are available only for 45W CPU SKUs. 1. eDP (in place of LVDS), VGA (in place of DDI 3), eSPI (in place of LPC), PCIe lane5-7 (via PCIe switch), USB4\_1/2 (in place of DDI 1/2), and GBE0\_SDP (for selected LAN controller versions) are BOM options supported by project basis. 2. GP\_SPI and SNDW0 support TBC. # 4.2. Signal Terminology Descriptions Meaning of the terms used for signal description tables

Term	Description
I	Input to the module
O	Output from the module
I/O	Bi-directional Input / Output
OD	Open drain output from the module

I 3.3V	Input 3.3V tolerant
I 5V	Input 5V tolerant
O 3.3V	Output 3.3V signal level
O 5V	Output 5V signal level
I/O 3.3V	Bi-directional signal 3.3V tolerant
I/O 5V	Bi-directional signal 5V tolerant
I/O $3.3V_{SB}$	Input or output 3.3V tolerant active in standby state

DDC	Display Data Channel
PCIE	PCI Express compatible differential signal
PEG	PCI Express Graphics
SATA	Serial ATA specification Revision 2.6 and 3
LVDS	Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal

P	Power Input / Output
REF	Reference voltage output. May be sourced from a Module power plane.
PDS	Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.

PU	PU (pull-up) resistor on module
PD	PD (pull-down) resistor on module

# 4.3. AB Connector Signal Descriptions 4.3.1 Audio

Name	Pin #	Description	I/O	PU / PD	Comment

AC_RST# / HDA_RST#	A30	Reset output to CODEC, active low.	O 3.3VSB
AC_SYNC / HDA_SYNC	A29	Sample-synchronization signal to the CODEC(s).	O 3.3VSB		PCH internal PD 20Kohm
AC_BITCLK / HDA_BITCLK	A32	Serial data clock generated by the external CODEC(s).	I/O 3.3VSB
AC_SDOUT / HDA_SDOUT	A33	Serial TDM data output to the CODEC.	O 3.3VSB		PCH internal PD 20Kohm
AC_SDIN[2:0] / HDA_SDIN[2:0]	B28 B29 B30	Serial TDM data inputs from up to 3 CODECs.	I/O 3.3VSB		PCH internal PD 20Kohm AC_SDNI2/HDA_SDIN2 not supported

4.3.2 Analog VGA

Name	Pin #	Description	I/O	PU / PD	Comment
VGA_RED	B89	Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_GRN	B91	Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_BLU	B92	Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_HSYNC	B93	Horizontal sync output to VGA monitor	O 3.3V
VGA_VSYNC	B94	Vertical sync output to VGA monitor	O 3.3V
VGA_I2C_CK	B95	DDC clock line (I2C port dedicated to identifying VGA monitor capabilities)	I/O OD 3.3V	PU 2k2 3.3V
VGA_I2C_DAT	B96	DDC data line.	I/O OD 3.3V	PU 2k2 3.3V

![](.express-rlp-manual-230411/4b82fa605d79ccbd7390e593e0d0d737566ce95095b1a7681b9ed33894eab2b7.jpg) Note: VGA is BOM option support (in place of DDI 3) by project basis # 4.3.3 LVDS or eDP The module default supports a single or dual channel LVDS display panel with up to 24-bit colors. A BOM option that removes the eDP to LVDS bridge IC and outputs the eDP signals directly is available. eDP vs LVDS pin mapping is described below.

Pin #	LVDS mode	eDP mode
A71	LVDS_A0+	eDP_TX2+
A72	LVDS_A0-	eDP_TX2-
A73	LVDS_A1+	eDP_TX1+
A74	LVDS_A1-	eDP_TX1-
A75	LVDS_A2+	eDP_TX0+
A76	LVDS_A2-	eDP_TX0-
A78	LVDS_A3+	-
A79	LVDS_A3-	-
A81	LVDS_A_CK+	eDP_TX3+
A82	LVDS_A_CK-	eDP_TX3-
B71	LVDS_B0+	-
B72	LVDS_B0-	-
B73	LVDS_B1+	-
B74	LVDS_B1-	-
B75	LVDS_B2+	-
B76	LVDS_B2-	-
B77	LVDS_B3+	-
B78	LVDS_B3-	-
B81	LVDS_B_CK+	-
B82	LVDS_B_CK-	-
A77	LVDS_VDD_EN	eDP_VDD_EN
B79	LVDS_BKLT_EN	eDP_BKLT_EN
B83	LVDS_BKLT_CTRL	eDP_BKLT_CTRL
A83	LVDS_I2C_CK	eDP_AUX+
A84	LVDS_I2C_DAT	eDP_AUX-
A87	-	eDP_HPD

![](.express-rlp-manual-230411/616117ae8394e7e0dfae8b1f971696696da363561de3345f4e1a1c8c993b10ff.jpg) Note: LVDS is the default mode and eDP is a BOM option 4.3.3.1. Single/Dual Channel LVDS (default)

Name	Pin #	Description	I/O	PU / PD	Comment

LVDS_A0+	A71	LVDS Channel A differential pairs	O LVDS
LVDS_A0-	A72
LVDS_A1+	A73
LVDS_A1-	A74
LVDS_A2+	A75
LVDS_A2-	A76
LVDS_A3+	A78
LVDS_A3-	A79
LVDS_A_CK+	A81	LVDS Channel A differential clock	O LVDS
LVDS_A_CK-	A82
LVDS_B0+	B71	LVDS Channel B differential pairs	O LVDS
LVDS_B0-	B72
LVDS_B1+	B73
LVDS_B1-	B74
LVDS_B2+	B75
LVDS_B2-	B76
LVDS_B3+	B77
LVDS_B3-	B78
LVDS_B_CK+	B81	LVDS Channel B differential clock	O LVDS
LVDS_B_CK-	B82
LVDS_VDD_EN	A77	LVDS panel power enable	O 3.3V	PD 100K
LVDS_BKLT_EN	B79	LVDS panel backlight enable	O 3.3V	PD 100K
LVDS_BKLT_CTRL	B83	LVDS panel backlight brightness control	O 3.3V	PD 100K
LVDS_I2C_CK	A83	DDC lines used for flat panel detection and control.	O 3.3V	PU 2k2 3.3V
LVDS_I2C_DAT	A84	DDC lines used for flat panel detection and control.	I/O 3.3V	PU 2k2 3.3V

4.3.3.2. 4-lane eDP

Name	Pin #	Description	I/O	PU / PD	Comment
eDP_TX3+	A81	eDP differential pairs	O PCIE		AC coupled off module
eDP_TX3-	A82
eDP_TX2+	A71
eDP_TX2-	A72
eDP_TX1+	A73
eDP_TX1-	A74
eDP_TX0+	A75
eDP_TX0-	A76
eDP_VDD_EN	A77	eDP power enable	O 3.3V	PD 100K
eDP_BKLT_EN	B79	eDP backlight enable	O 3.3V	PD 100K
eDP_BKLT_CTRL	B83	eDP backlight brightness control	O 3.3V	PD 100K
eDP_AUX+	A83	eDP AUX+	I/O PCIE		AC coupled off module
eDP_AUX-	A84	eDP AUX-	I/O PCIE		AC coupled off module
eDP_HPD	A87	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	PD 100K on this pin when eDP is supported

4.3.4 Gigabit Ethernet

Name	Pin #	Description				I/O	PU / PD	Comment
GBE0_MDI0+	A13	Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:				I/O Analog		Twisted pair signals for external transformer.
GBE0_MDI0-	A12
GBE0_MDI1+	A10
GBE0_MDI1-	A9	1000		100	10
GBE0_MDI2+	A7	MDI[0]+/-	B1_DA+/-	TX+/-	TX+/-
GBE0_MDI2-	A6	MDI[1]+/-	B1_DB+/-	RX+/-	RX+/-
GBE0_MDI3+	A3	MDI[2]+/-	B1_DC+/-
GBE0_MDI3-	A2	MDI[3]+/-	B1_DD+/-
GBE0_ACT#	B2	Gigabit Ethernet Controller 0 activity indicator, active low.				OD 3.3VSB
GBE0_LINK#	A8	Gigabit Ethernet Controller 0 link indicator, active low.				OD 3.3VSB
GBE0_LINK100# *	A4	Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.				OD 3.3VSB
GBE0_LINK1000# *	A5	Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.				OD 3.3VSB
GBE0_CTREF	A14	Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.				REF GND min 3.3V max		Not supported
GBE0_SDP	A49	Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.				IO 3.3VSB	GBE0_SDP	Depends on the selection of LAN controller. i225-IT support this pin

![](.express-rlp-manual-230411/c8dc3a2f87179e67cc4a6a3be0ffdb85cc699e0fe22b3f0f1ff381b07ffbcf87.jpg) Note: This product supports up to 2.5GbE. The LAN LED behavior is optimized for maximum 2.5GbE speed. GBE0\_LINK1000# will be active for 2.5GbE speed indication. GBE0\_LINK100# will be active for 1GbE speed indication or lower. GBE0\_ACT# and GBE0\_LINK# share the same source from the LAN controller. For 100Mbit/sec and 10Mbit/sec speed, the LAN LED will be OFF. 4.3.5 SATA

Name	Pin #	Description	I/O	PU / PD	Comment
SATA0_TX+SATA0_TX-	A16A17	Serial ATA channel 0, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA0_RX+SATA0_RX-	A19A20	Serial ATA channel 0, Receive Input differential pair.	I SATA		AC coupled on Module
SATA1_TX+SATA1_TX-	B16B17	Serial ATA channel 1, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA1_RX+SATA1_RX-	B19B20	Serial ATA channel 1, Receive Input differential pair.	I SATA		AC coupled on Module
SATA2_TX+SATA2_TX-	A22A23	Serial ATA channel 2, Transmit Output differential pair.	O SATA		Not supported
SATA2_RX+SATA2_RX-	A25A26	Serial ATA channel 2, Receive Input differential pair.	I SATA		Not supported
SATA3_TX+SATA3_TX-	B22B23	Serial ATA channel 3, Transmit Output differential pair.	O SATA		Not supported
SATA3_RX+SATA3_RX-	B25B26	Serial ATA channel 3, Receive Input differential pair.	I SATA		Not supported
(S)ATA_ACT#	A28	ATA (parallel and serial) or SAS activity indicator, active low.	O 3.3V	PU 10K3.3V	AC coupled on Module

4.3.5.1. PCH HSIO Lane Assignments

Name	HSIO name on SOC	Comment
SATA0	HSIO 26
SATA1	HSIO 27
SATA2	HSIO 28	Not supported
SATA3	HSIO 29	Not supported

4.3.6 PCI Express

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX0+PCIE_TX0-	A68A69	PCI Express channel 0, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX0+PCIE_RX0-	B68B69	PCI Express channel 0, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX1+PCIE_TX1-	A64A65	PCI Express channel 1, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX1+PCIE_RX1-	B64B65	PCI Express channel 1, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX2+PCIE_TX2-	A61A62	PCI Express channel 2, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX2+PCIE_RX2-	B61B62	PCI Express channel 2, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX3+PCIE_TX3-	A58A59	PCI Express channel 3, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX3+PCIE_RX3-	B58B59	PCI Express channel 3, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX4+PCIE_TX4-	A55A56	PCI Express channel 4, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX4+PCIE_RX4-	B55B56	PCI Express channel 4, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX5+PCIE_TX5-	A52A53	PCI Express channel 5, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX5+PCIE_RX5-	B52B53	PCI Express channel 5, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_CLK_REF+PCIE_CLK_REF-	A88A89	PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.	O PCIE

4.3.6.1. PCH HSIO Lane Assignments

Name	HSIO name on SOC / Switch IC	Comment
PCIE0	HSIO 22
PCIE1	HSIO 23
PCIE2	HSIO 24
PCIE3	HSIO 25
PCIE4	PCIe SW DPE_0
PCIE5	PCIe SW DPE_1
PCIE6	PCIe SW DPE_6
PCIE7	PCIe SW DPE_14

4.3.7 LPC Bus

Name	Pin #	Description	I/O	PU / PD	Comment

LPC_AD0	B4	LPC multiplexed address, command and data bus	I/O 3.3VSB
LPC_AD1	B5
LPC_AD2	B6
LPC_AD3	B7
LPC_FRAME#	B3	LPC frame indicates the start of an LPC cycle	O 3.3VSB
LPC_DRQ0#	B8	LPC serial DMA request	I 3.3V		Not connected
LPC_DRQ1#	B9
LPC_SERIRQ	A50	LPC serial interrupt	I/O 3.3VSB	PU 8.2K3.3VSB
LPC_CLK	B10	LPC clock output -33MHz nominal	O 3.3VSB		The LPC_CLK frequency is 24MHz on this platform

![](.express-rlp-manual-230411/e0f36d4c681e2f876a8ee3b531eaac420253f1f447ef2b3e939e93ece89fe69f.jpg) Note: LPC Bus is supported by an eSPI to LPC bridge IC 4.3.8 USB

Name	Pin #	Description	I/O	PU / PD	Comment

USB0+USB0-	A46A45	USB differential data pairs for Port 0	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB1+USB1-	B46B45	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB2+USB2-	A43A42	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB3+USB3-	B43B42	USB differential data pairs for Port 2	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB4+USB4-	A40A39	USB differential data pairs for Port 3	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB5+USB5-	B40B39	USB differential data pairs for Port 4	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB6+USB6-	A37A36	USB differential data pairs for Port 5	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB7+USB7-	B37B37	USB differential data pairs for Port 6	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB_0_1_OC#	B44	USB over-current sense, USB ports 0 and 1 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_2_3_OC#	A44	USB over-current sense, USB ports 2 and 3 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_4_5_OC#	B38	USB over-current sense, USB ports 4 and 5 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_6_7_OC#	A38	USB over-current sense, USB ports 6 and 7 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB0_HOST_PRSNT	B48	Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.	I 3.3VSB		Not supported

![](.express-rlp-manual-230411/8ad8af909f8826adb720d817c159773ea11c5e1f9a50dca0c6a352b04c2f4f92.jpg) \*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. 4.3.9 SPI Bus (BIOS only)

Name	Pin #	Description	I/O	PU / PD	Comment
SPI_CS#	B97	Chip select for Carrier Board SPI BIOS Flash.	O 3.3VSB	PU 10K3.3VSB
SPI_MISO	A92	Data in to module from carrier board SPI BIOS flash.	I 3.3VSB
SPI_MOSI	A95	Data out from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_CLK	A94	Clock from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_POWER	A91	Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier	O P 3.3VSB
BIOS_DIS0#	A34	Selection strap to determine the BIOS boot device.	I	PU 10K3.3VSB	Carrier shall pull to GND or leave not- connected.
BIOS_DIS1#	B88	Selection strap to determine the BIOS boot device.	I	PU 10K3.3VSB	Carrier shall pull to GND or leave not- connected

4.3.10 Miscellaneous

Name	Pin #	Description	I/O	PU / PD	Comment
SPKR	B32	Output for audio enunciator, the "speaker" in PC-AT systems	O 3.3V
WDT	B27	Output indicating that a watchdog time-out event has occurred.	O 3.3V	PU 10K 3.3V
THRM#	B35	Input from off-module temp sensor indicating an over-temp situation.	I 3.3VSB
THRMTRIP#	A35	Active low output indicating that the CPU has entered thermal shutdown.	O 3.3VSB	PU 100K 3.3VSB
FAN_PWMOUT	B101	Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.	O OD 3.3V		There shall be PD on carrier board
FAN_TACHIN	B102	Fan tachometer input for a fan with a two-pulse output.	I OD 3.3V	PU 47K 3.3V
TPM_PP	A96	Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.	I 3.3V	PD 100K	PD only when TPM on module. Modules implementing a TPM shall pull down

4.3.11 SMBus

Name	Pin #	Description	I/O	PU / PD	Comment

SMB_CK	B13	System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 4.7K3.3VSB
SMB_DAT#	B14	System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 4.7K3.3VSB
SMB_ALERT#	B15	System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.	I 3.3VSB	PU 10K3.3VSB

4.3.12 I 2 C Bus

Name	Pin #	Description	I/O	PU / PD	Comment

I2C_CK	B33	General purpose I2C port clock output/input	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)
I2C_DAT	B34	General purpose I2C port data I/O line	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)

4.3.13 General Purpose I/O (GPIO)

Name	Pin #	Description	I/O	PU / PD	Comment
GPO[0]	A93	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[1]	B54	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[2]	B57	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[3]	B63	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPI[0]	A54	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[1]	A63	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[2]	A67	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[3]	A85	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V

4.3.14 Serial Interface Signals

Name	Pin #	Description	I/O	PU / PD	Comment

SERO_TX	A98	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SERO_RX	A99	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V
SER1_TX	A101	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SER1_RX	A102	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V

4.3.15 Power and System Management

Name	Pin #	Description	I/O	PU / PD	Comment
PWRBTN#	B12	Power button to bring system out of S5 (soft off), active on falling edge.	I 3.3VSB	PU 10K 3.3VSB
SYS_RESET#	B49	Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.	I 3.3VSB	PU 10K 3.3VSB
CB_RESET#	B50	Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.	O 3.3V
PWR_OK	B24	Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.	I 3.3VSB	PU 10K 3.3VSB	Should have weak pull up.
SUS_STAT#	B18	Indicates imminent suspend operation; used to notify LPC devices.	O 3.3VSB
SUS_S3#	A15	Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.	O 3.3VSB	PD 100K
SUS_S4#	A18	Indicates system is in Suspend to Disk state. Active low output.	O 3.3VSB	PD 100K
SUS_S5#	A24	Indicates system is in Soft Off state.	O 3.3VSB	PD 100K
WAKE0#	B66	PCI Express wake up signal.	I 3.3VSB	PU 10K 3.3VSB
WAKE1#	B67	General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.	I 3.3VSB	PU 10K 3.3VSB	Connect to WAKE 0#
BATLOW#	A27	Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.	I 3.3VSB	PU 10K 3.3VSB
LID#	A103	LID button. Low active signal used by the ACPI operating system for a LID switch.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
SLEEP#	B103	Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
RAPID_SHUTDOWN	C67	Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source impedance for ≥20 μs.	I CMOS 5VSB		Not supported

4.3.16 Power and Ground

Name	Pin #	Description	I/O	PU / PD	Comment
VCC_12V	A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109	Primary power input supports wide range 5—20V input. All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
VCC_5V_SBY	B84, B85, B86, B87	Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.	P		5Vsb ±5%
VCC_RTC	A47	Real-time clock circuit-power input. Nominally +3.0V.	P
GND	A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110	Ground - DC power and signal and AC signal return path.	P

# 4.4. CD Connector Signal Descriptions 4.4.1 USB 3.0 Extensions

Name	Pin #	Description	I/O	PU / PD	Comment
USB_SSRX0-USB_SSRX0+	C3C4	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0	I PCIE		AC coupled off module
USB_SSTX0-USB_SSTX0+	D3D4	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0	O PCIE		AC coupled on module
USB_SSRX1-USB_SSRX1+	C6C7	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1	I PCIE		AC coupled off module
USB_SSTX1-USB_SSTX1+	D6D7	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1	O PCIE		AC coupled on module
USB_SSRX2-USB_SSRX2+	C9C10	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2	I PCIE		AC coupled off module
USB_SSTX2-USB_SSTX2+	D9D10	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2	O PCIE		AC coupled on module
USB_SSRX3-USB_SSRX3+	C12C13	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3	I PCIE		AC coupled off module
USB_SSTX3-USB_SSTX3+	D12D13	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3	O PCIE		AC coupled on module

# 4.4.1.1. USB Root Segmentation All USB interfaces are derived from the xHCI controller. 4.4.2 PCI Express

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX6+PCIE_TX6-	D19D20	PCI Express channel 6, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX6+PCIE_RX6-	C19C20	PCI Express channel 6, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX7+PCIE_TX7-	D22D23	PCI Express channel 7, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX7+PCIE_RX7-	C22C23	PCI Express channel 7, Receive Input differential pair.	I PCIE		AC coupled off Module

# 4.4.2.1. PCH HSIO Lane Assignments Refer to Section 4.3.6.1 PCH HSIO Lane Assignments on page 34. # 4.4.3 DDI1 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI1_PAIR0+	D26	DP1_LANE0+	TMDS1_DATA2+
DDI1_PAIR0-	D27	DP1_LANE0-	TMDS1_DATA2-
DDI1_PAIR1+	D29	DP1_LANE1+	TMDS1_DATA1+
DDI1_PAIR1-	D30	DP1_LANE1-	TMDS1_DATA1-
DDI1_PAIR2+	D32	DP1_LANE2+	TMDS1_DATA0+
DDI1_PAIR2-	D33	DP1_LANE2-	TMDS1_DATA0-
DDI1_PAIR3+	D36	DP1_LANE3+	TMDS1_CLK+
DDI1_PAIR3-	D37	DP1_LANE3-	TMDS1_CLK-
DDI1_PAIR4+	C25	-	-
DDI1_PAIR4-	C26
DDI1_PAIR5+	C29	-	-
DDI1_PAIR5-	C30
DDI1_PAIR6+	C15	-	-
DDI1_PAIR6-	C16
DDI1_HPD	C24	DP1_HPD	HDMI1_HPD
DDI1_CTRLCLK_AUX+	D15	DP1_AUX+	HMDI1_CTRLCLK
DDI1_CTRLCLK_AUX-	D16	DP1_AUX-	HMDI1_CTRLDATA
DDI1_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL	DDI1_DDC_AUX_SEL

![The image features a simple red icon representing a document or page. The shape is a square with the bottom-right corner folded upwards (a 'dog-ear'). Inside the red outline, two horizontal red lines are centered in the upper portion, symbolizing text or content.](.express-rlp-manual-230411/aa4048a405129b17961486ab768533ee5af6bb023fce7f9b78f6d573e3362d9f.jpg) Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.3.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP1_LANE0+	D26	DP Port 1, differential pair data lines	O PCIE		AC coupled off Module
DP1_LANE0-	D27				100 nF DC blocking capacitors shall be placed on the Carrier
DP1_LANE1+	D29
DP1_LANE1-	D30
DP1_LANE2+	D32
DP1_LANE2-	D33
DP1_LANE3+	D36
DP1_LANE3-	D37
DP1_HPD	C24	DP Port 1, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP1_AUX+	D15	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP1_AUX-	D16	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.3.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS1_DATA2+	D26	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS1_DATA2-	D27
TMDS1_DATA1+	D29
TMDS1_DATA1-	D30
TMDS1_DATA0+	D32
TMDS1_DATA0-	D33
TMDS1_CLK+	D36	HDMI Port, Differential Pair Clock Lines
TMDS1_CLK-	D37	HDMI Port, Differential Pair Clock Lines
HDMI_HPD	C24	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI1_CTRLCLK	D15	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI1_CTRLDATA	D16	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.4 DDI2 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI2_PAIR0+	D39	DP2_LANE0+	TMDS2_DATA2+
DDI2_PAIR0-	D40	DP2_LANE0-	TMDS2_DATA2-
DDI2_PAIR1+	D42	DP2_LANE1+	TMDS2_DATA1+
DDI2_PAIR1-	D43	DP2_LANE1-	TMDS2_DATA1-
DDI2_PAIR2+	D46	DP2_LANE2+	TMDS2_DATA0+
DDI2_PAIR2-	D47	DP2_LANE2-	TMDS2_DATA0-
DDI2_PAIR3+	D49	DP2_LANE3+	TMDS2_CLK+
DDI2_PAIR3-	D50	DP2_LANE3-	TMDS2_CLK-
DDI2_HPD	D44	DP2_HPD	HDMI2_HPD
DDI2_CTRLCLK_AUX+	C32	DP2_AUX+	HMDI2_CTRLCLK
DDI2_CTRLCLK_AUX-	C33	DP2_AUX-	HMDI2_CTRLDATA
DDI2_DDC_AUX_SEL	C34	DDI2_DDC_AUX_SEL	DDI2_DDC_AUX_SEL

![The image displays a simple, red-outlined icon resembling a document or notepad. It features a rectangular shape with a folded corner at the bottom right. Inside the rectangle, two horizontal lines are centered, suggesting lines of text.](.express-rlp-manual-230411/7ad9e03871ccb484f2817d1f5a8f71fd89022fc3decd49cc4dad4ea2ff529294.jpg) # Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.4.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP2_LANE0+	D39	DP Port 2, differential pair data lines	O PCIE		AC coupled off Module
DP2_LANE0-	D40				100 nF DC blocking capacitors shall be placed on the Carrier
DP2_LANE1+	D42
DP2_LANE1-	D43
DP2_LANE2+	D46
DP2_LANE2-	D47
DP2_LANE3+	D49
DP2_LANE3-	D50
DP2_HPD	D44	DP Port 2, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP2_AUX+	C32	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP2_AUX-	C33	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.4.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS2_DATA2+	D39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS2_DATA2-	D40
TMDS2_DATA1+	D42
TMDS2_DATA1-	D43
TMDS2_DATA0+	D46
TMDS2_DATA0-	D47
TMDS2_CLK+	D49	HDMI Port, Differential Pair Clock Lines
TMDS2_CLK-	D50	HDMI Port, Differential Pair Clock Lines
HDM2_HPD	D44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI2_CTRLCLK	C32	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI2_CTRLDATA	C33	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.5 DDI3 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI3_PAIR0+	C39	DP3_LANE0+	TMDS3_DATA2+
DDI3_PAIR0-	C40	DP3_LANE0-	TMDS3_DATA2-
DDI3_PAIR1+	C42	DP3_LANE1+	TMDS3_DATA1+
DDI3_PAIR1-	C43	DP3_LANE1-	TMDS3_DATA1-
DDI3_PAIR2+	C46	DP3_LANE2+	TMDS3_DATA0+
DDI3_PAIR2-	C47	DP3_LANE2-	TMDS3_DATA0-
DDI3_PAIR3+	C49	DP3_LANE3+	TMDS3_CLK+
DDI3_PAIR3-	C50	DP3_LANE3-	TMDS3_CLK-
DDI3_HPD	C44	DP3_HPD	HDMI3_HPD
DDI3_CTRLCLK_AUX+	C36	DP3_AUX+	HMDI3_CTRLCLK
DDI3_CTRLCLK_AUX-	C37	DP3_AUX-	HMDI3_CTRLDATA
DDI3_DDC_AUX_SEL	C38	DDI3_DDC_AUX_SEL	DDI3_DDC_AUX_SEL

![The image displays a red outline icon of a document or page with a folded bottom-right corner. Inside the square shape, there are two horizontal lines centered horizontally.](.express-rlp-manual-230411/0d26bcf76a55efd79c4784676438628ca5aea752e10446c98eda1c313707e762.jpg) # Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.5.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP3_LANE0+	C39	DP Port 3, differential pair data lines	O PCIE		AC coupled off Module
DP3_LANE0-	C40				100 nF DC blocking capacitors shall be placed on the Carrier
DP3_LANE1+	C42
DP3_LANE1-	C43
DP3_LANE2+	C46
DP3_LANE2-	C47
DP3_LANE3+	C49
DP3_LANE3-	C50
DP3_HPD	C44	DP Port 3, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP3_AUX+	C36	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP3_AUX-	C37	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.5.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS3_DATA2+	C39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS3_DATA2-	C40
TMDS3_DATA1+	C42
TMDS3_DATA1-	C43
TMDS3_DATA0+	C46
TMDS3_DATA0-	C47
TMDS3_CLK+	C49	HDMI Port, Differential Pair Clock Lines
TMDS3_CLK-	C50	HDMI Port, Differential Pair Clock Lines
HDM3_HPD	C44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI3_CTRLCLK	C36	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI3_CTRLDATA	C37	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.6 PCIe Graphics Port (PEG)

Name	Pin #	Description	I/O	PU / PD	Comment
PEG_TX0+PEG_TX0-	D52D53	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX0+PEG_RX0-	C52C53	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX1+PEG_TX1-	D55D56	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX1+PEG_RX1-	C55C56	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX2+PEG_TX2-	D58D59	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX2+PEG_RX2-	C58C59	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX3+PEG_TX3-	D61D62	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX3+PEG_RX3-	C61C62	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX4+PEG_TX4-	D65D66	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX4+PEG_RX4-	C65C66	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX5+PEG_TX5-	D68D69	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX5+PEG_RX5-	C68C69	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX6+PEG_TX6-	D71D72	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX6+PEG_RX6-	C71C72	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX7+PEG_TX7-	D74D75	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX7+PEG_RX7-	C74C75	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX8+PEG_TX8-	D78D79	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX8+PEG_RX8-	C78C79	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX9+PEG_TX9-	D81D82	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX9+PEG_RX9-	C81C82	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX10+PEG_TX10-	D85D86	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX10+PEG_RX10-	C85C86	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX11+PEG_TX11-	D88D89	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX11+PEG_RX11-	C88C89	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX12+PEG_TX12-	D91D92	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX12+PEG_RX12-	C91C92	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX13+PEG_TX13-	D94D95	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX13+PEG_RX13-	C94C95	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX14+PEG_TX14-	D98D99	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX14+PEG_RX14-	C98C99	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX15+PEG_TX15-	D101D102	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX15+PEG_RX15-	C101C102	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_LANE_RV#	D54	PCI Express Graphics lane reversal input strap. Pull low on the Carrier Board to reverse lane order.	I 3.3V

4.4.7 Module Type Definition

Name	Pin #	Description	I/O	PU / PD	Comment

TYPE0#	C54	The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC).			Type 6
TYPE1#	C57
TYPE2#	D57
		For Pin-out Type 1 and Type 10 that lack a CD connector, these pins are not present (X)
		TYPE2# TYPE1# TYPE0#
		X X X Pinout Type 1
		X X X Pinout Type 10
		NC NC NC Pinout Type 2
		NC NC GND Pinout Type 3
		NC GND NC Pinout Type 4
		NC GND GND Pinout Type 5
		GND NC NC Pinout Type 6
		GND NC GND Pinout Type 7
		The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g. deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.
TYPE10#	A97	In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.			No PD

4.4.8 Power and Ground

Name	Pin #	Description	I/O	PU / PD	Comment
VCC_12V	C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109	Primary power input supports wide range 5~20V input. All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
GND	C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110	Ground - DC power and signal and AC signal return path.	P

# 5. Additional Features This chapter describes connectors, LEDs, switches and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as below: ![5.1. Module Feature Locations\nStatus LEDs\nBIOS Default Reset Button\n30-pin Debug connector\nBIOS Boot Select\nADLINK\nFan](.express-rlp-manual-230411/9747e5d223e63095ac4dde2d912f6d290e7b6da01acffe4b75d1327eddbb5a6d.jpg) Figure 3 – Module feature locations (top side) # 5.2. Debug Connector This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: Test points measurement of internal power rails SPI BIOS programming interface Embedded Controller programming interface 30-pin Debug Connector located on bottom side (illustration only) ![Close-up of a green printed circuit board with multiple microchips and connectors (no readable text or symbols)](.express-rlp-manual-230411/fccb9af76750a50c0c69395f39358061ad8a688e6eeba919ca6820757e9d7181.jpg) ![Electronic circuit board with gold contacts and a coiled ribbon, no visible text or symbols](.express-rlp-manual-230411/164540a79e8f25a38b37d26fbd3ae2004342fe7892ecda34801a269b7a8ce3a3.jpg) Figure 4 – Express-RLP and Debug Module # 5.3. Status LEDs Status LED’s are mounted on the module to facilitate easier maintenance. ![LED3 LED2 LED1](.express-rlp-manual-230411/8ff7ed29bb0f4dc656889d537c27e563ce226f54f2b277f75297c122cdabd7dc.jpg)

Name	Color	Connection	Function
LED1	Blue	EC output	Power Sequence Status Code (EC) Power Changes, RESET (see Exception Codes below)
LED2	Green	Power Source 3Vcc	S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3	Red	EC output and same signal as WDT (B27) on BtB connector	Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)

# 5.4. Exception Codes

Exception Code	Error Message
0	NOERROR
3	NO_SLP_S5
4	NO_SLP_S4
5	NO_SLP_S3
6	BIOS_FAIL
7	RESET_FAIL
9	NO_CB_PWROK
10	CRITICAL_TEMP
11	POWER_FAIL
12	VOLTAGE_FAIL
13	RSMRST_FAIL
14	NO_VDDQ_PG
16	NO_VCORE_PG
17	NO_SYS_GD
19	NO_V3P3A
21	NO_PWRSRC_GD

# 5.5. Fan Connector Connector type: JVE 24W1125A-04M00 ![Close-up of a green printed circuit board with various electronic components and a red arrow pointing to component 4 (no readable text or symbols)](.express-rlp-manual-230411/b0227df207604e4ba0913f7e821aac2312db9e85a94fc4375d8baafa154ba126.jpg)

Name	Description
1	FAN_PWMOUT
2	FAN_TACHIN
3	GND
4	12V

# 5.6. BIOS Default Reset Button ![Close-up of a green printed circuit board with electronic components and a red arrow pointing to a component (no visible text or symbols)](.express-rlp-manual-230411/5c0f63dcb7382edca6bf9edd296abc0d49eb0cd746fa0bcda80aa87f91f3f8c6.jpg) To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Keep the BIOS Setup Defaults Reset Button pressed and boot up the system. You can release the button when the BIOS prompt screen appears 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.express-rlp-manual-230411/e2b381eb0722f343cd58bfa76f9ce7559148f954503d9e5b4943294cdc03b7b5.jpg) # 5.7. BIOS Boot Select The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

Mode	Pin 1	Pin 2
Boot from SPI0 (default)	On	-
Boot from SPI1	Off	-
Set BIOS to PICMG mode (default)	-	On
Set BIOS to Failsafe BIOS mode	-	Off

# 6. BIOS Checkpoints, Beep Codes A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. The Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes. Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but the Aptio 5.x core can be configured to send checkpoints to a variety of sources. The Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware. A beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process. ![The image displays a red icon resembling a document or a note. It features a thick red outline with rounded corners. Inside the white space, there are two horizontal red lines centered vertically.](.express-rlp-manual-230411/7570aad20cc39e7b55c148fbf67262e2d8e3c544c658d881c6bfd359cb775511.jpg) Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify the user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes # Viewing Checkpoints Checkpoints generated by the Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-on cards show the value of I/O port 80h on an LED display. # Aptio V Checkpoint and Beep Codes Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes # 7. Software Support 7.1. Windows 10 IoT Enterprise 64-bit 7.2. Yocto Linux 64-bit https://github.com/ADLINK/meta-adlink-x86-64bit (TBC) # 8. Mechanical and Thermal 8.1. Module Dimensions ![95\n91\nYAM 2000\n51.41\n28.41\n4\n0\n0 4\n25.79\n80\n88.79\n121\n125](.express-rlp-manual-230411/bcd03b83eab92f5a3011592c484aa3dc669e4788b6795b6e02ee28815fe32f74.jpg) ![Top View\n5 2 ±0.25\n2\n4 ±0.25\nFront View](.express-rlp-manual-230411/d477ddec9278faea127669d1fb7ac0bdbdeeed1353355306e3fa8688a11a1cb8.jpg) ![Bottom Side RAM\nModule Keepout\n125\n121\n88.79\n85.05\n80\n74.2\n25.79\n16.5\n9.95\n4\n0\n95\n91\n57.195\n51.41\n28.41\n18\n6\n4\n0](.express-rlp-manual-230411/94f9772c22154a885d0ac6bfc0627e1ffed86ec7b81ceea91e55a3dbc8cba35e.jpg) Bottom View All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances on the module connector locating peg holes (dimensions [16.50, 6.00]&[16.50,18.00]) should be ± 0.10mm. Dimensions: mm Figure 5 – Module mechanical dimensions # 8.2. Thermal Solutions 8.2.1 Heatspreader: HTS ![Dimensions: mm\n11\nM2.5*2PCS\nM2.5*5PCS\n95\n125\n89\n94\n125\n41\n87](.express-rlp-manual-230411/4434f5525fac3bef7d990a1a9b90c1fd56f10e560d0672b85c8bc37ce2d28116.jpg) Heatspreader:HTS Figure 6 – Heatspreader: HTS # 8.2.2 Heatsink: THS ![The image displays a technical engineering drawing of a component labeled at the bottom center as 'Heatsink: THS'. The top right corner indicates 'Dimensions: mm'.\n\nThe diagram presents six views of the object:\n* **Top Left:** A side profile view with a vertical dimension of **16.39**.\n* **Top Middle:** An isometric view showing screw holes labeled **'M2.5*2PCS'** and **'M2.5*5PCS'**.\n* **Top Right:** An isometric view showing the array of cooling fins.\n* **Bottom Left:** A front view showing the fins, with a width dimension of **95** and a height dimension of **125**.\n* **Bottom Middle:** A thin side profile view.\n* **Bottom Right:** A rear view featuring a gold-colored mounting plate, with dimensions labeled **125** (total height), **41** (vertical offset), and **87** (width).](.express-rlp-manual-230411/6dec7a5451d7d2a4efe59f45f6572accc097183d162f74eefa985ef8a29b5f5a.jpg) Figure 7 – Heatsink: THS # 8.2.3 Heatsink High Profile: THSH Dimensions: mm ![This image displays technical CAD renderings and orthographic projections of a grey heatsink assembly. Six views are arranged in two rows.\n\n* **Top Left:** A side profile view with a height dimension labeled **31.41**.\n* **Top Middle:** An isometric top view showing a mounting plate with screws, annotated with **M2.5*2PCS** and **M2.5*5PCS**.\n* **Top Right:** An isometric view highlighting the vertical cooling fins.\n* **Bottom Left:** A front view showing the fins, with a width dimension of **95** and a height dimension of **125**.\n* **Bottom Middle:** A thin side profile view.\n* **Bottom Right:** A bottom view showing the mounting plate, with dimensions labeled **125**, **41**, and **87**.\n\nCentered at the very bottom is the text **Heatsink: THSH**.](.express-rlp-manual-230411/9bfb7aa5baf26144cd57415cf34e334e689265288e71e2546280a2c668275b08.jpg) Figure 8 – Heatsink High Profile: THSH # 8.2.4 Heatsink with Fan: THSF Dimensions: mm ![The image displays a technical CAD rendering of a computer heatsink from multiple angles, accompanied by dimensions and labels.\n\n**Top Row:**\n* **Left:** A side profile view with a vertical dimension labeled **43.6**.\n* **Center:** A top-down isometric view highlighting screw placements with labels pointing to them: **M2.5*2PCS** and **M2.5*5PCS**.\n* **Right:** An angled view showcasing the fin structure and hexagonal cutouts.\n\n**Bottom Row:**\n* **Left:** A front view displaying the fin array and hexagonal pattern, with dimensions **95** (width) and **125** (height).\n* **Center:** A thin side profile view.\n* **Right:** A rear view showing mounting holes and a central rectangular area, with dimensions **125** (height), **41** (hole spacing), and **87** (width).\n\n**Bottom Caption:**\nThe text at the very bottom reads: **Heatsink with Fan: THSF**](.express-rlp-manual-230411/52ea49e9222b731fd9647aedeca0d6f7b70e34d46d45c27eecfe8324c8520f6f.jpg) Figure 9 – Heatsink with Fan: THSF [🔗 Link to the original document](.express-rlp-manual-230411/express-rlp-manual-230411.pdf)