# Express-TL User’s Guide intel ![Close-up of a green printed circuit board with multiple microchips and electronic components (no readable text or symbols)](.express-tl-50m-72138-1050-15/a1fee9099333415bdec36dde51eee31093255554534586eb3ede2361f8e773b1.jpg) Revision History

Revision	Description	Date	Author
1.0	Initial release	2021-12-16	JC
1.1	Pin definitions and I/O, LED specifications updated	2022-03-16	CC
1.2	Operating temperature specifications updated	2022-08-10	CC
1.3	BIOS tables added	2024-06-07	AL
1.4	Block diagram updated	2024-11-07	AL
1.5	Pinout and signal descriptions updated	2025-05-29	AL

# Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![The image displays a standard yellow triangular warning sign with a thick black border. Inside the triangle, centered, is a black exclamation mark.](.express-tl-50m-72138-1050-15/18c38eeb0bd13aea90d6e16a59695544b46958e7046f754497e2648822f73514.jpg) California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. ![The image displays a line drawing of a wheeled trash bin with a large 'X' crossed over it. Below the bin is a solid black rectangular block. There is no other visible text.](.express-tl-50m-72138-1050-15/1ebfe205ca901f0edfe2632eac613afb523e4c0f43fcc9473e967ab0d0bf1f1c.jpg) # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. # Copyright © 2025 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: • Keep equipment away from water or liquid sources; • Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image shows a simple icon depicting a document or memo. It consists of a red outline of a rectangular piece of paper with the bottom-right corner folded upwards (a 'dog-ear'). Inside the white space, there are two horizontal red lines, resembling text or a list.](.express-tl-50m-72138-1050-15/15ba31f51994c88b7c8705f39dea69a9ba2dda62383719bfd8b7fe3d089aec18.jpg) Note: This information adds clarity or specifics to text and illustrations. ![The image displays a yellow triangle with a black outline pointing upwards. Inside the triangle is a black exclamation point.](.express-tl-50m-72138-1050-15/d911fc09a655c46a071a94c9743a8151395a4faf4a446d8907795d4d9b33605a.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image displays a standard caution symbol: a red triangle with rounded corners containing a white exclamation point in the center, set against a white background.](.express-tl-50m-72138-1050-15/ae408244ea318d253d4d5d96bc05a3639fc9f7f3391eb2efd3b4087194f0dcca.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Getting Service Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5706 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. # Table of Contents Revision History .. Preface . List of Figures ... .10 1. Introduction ... .11 2. Specifications.. .12 2.1. Core System... . 12 2.2. Video.... ... 13 2.2.1 Display Interface Support.. . 14 2.3. Audio .. .. 14 2.4. Expansion Busses... ... 14 2.5. Ethernet ... ... 15 2.6. Multi I/O and Storage... .. 15 2.7. Trusted Platform Module (TPM)... ... 16 2.8. SEMA Board controller... ... 16 2.9. Debug... .. 17 2.10. Power.... ... 17 2.11. Mechanical and Environmental . ... 17 3. Block Diagram .. .19 4. Pinout and Signal Descriptions ... ..20 4.1. Pin Summary .. . 20 4.2. Signal Terminology Descriptions.. . 25 4.3. AB Connector Signal Descriptions .. ... 26 4.3.1 Audio... ... 26 4.3.2 Analog VGA.. . 27 4.3.3 LVDS or eDP.... ... 28 4.3.4 Gigabit Ethernet... . 31 4.3.5 SATA .. ... 32 4.3.6 PCI Express... ... 33 4.3.7 LPC Bus... ... 35 4.3.8 USB.... ... 36 4.3.9 SPI Bus (BIOS only).. . 37 4.3.10 Miscellaneous.. ... 38 4.3.11 SMBus ... ... 39 4.3.12 I 2C Bus... ... 39 4.3.13 General Purpose I/O (GPIO) .. . 40 4.3.14 Serial Interface Signals.. .... 40 4.3.15 Power and System Management . . 41 4.3.16 Power and Ground .. .... 42 4.4. CD Connector Signal Descriptions.. .. 43 4.4.1 USB 3.0 Extensions . ... 43 4.4.2 PCI Express.. .... 44 4.4.3 DDI1 Port... .... 45 4.4.4 DDI2 Port... .... 48 4.4.5 DDI3 Port... . 51 4.4.6 PCIe Graphics Port (PEG)... . 54 4.4.7 Module Type Definition .. . 57 4.4.8 Power and Ground .. . 58 5. Additional Features ... ..59 5.1. Module Feature Locations. . 59 5.2. Debug Connector.. . 61 5.3. Status LEDs.. . 62 5.4. Exception Codes.. . 63 5.5. Fan Connector.... . 64 5.6. BIOS Default Reset Button.. . 65 5.7. PCI Express Configuration Switch.. . 66 5.8. BIOS Boot Select.. . 67 6. BIOS Setup... ..68 6.1. Menu Structure... . 68 6.2. Main ... ... 69 6.2.1 Main > BIOS Information . .... 69 6.2.2 Main > System Information... ... 69 6.2.3 Main > Board Information .. . 70 6.2.4 Main > System Date/Time .. ... 70 6.2.5 Main > Access Level .. . 70 6.3. Advanced .. ... 71 6.3.1 Advanced > CPU Configuration .. . 71 6.3.2 Advanced > Power & Performance... . 72 6.3.3 Advanced > TCC Platform Setting.... . 80 6.3.4 Advanced > Intel(R) Time Coordinated Computing .. .... 80 6.3.5 Advanced > Graphics Configuration ...... .... 82 6.3.6 Advanced > Power Management .. ... 83 6.3.7 Advanced > System Management .. . 85 6.3.8 Advanced > Thermal Management .. . 85 6.3.9 Advanced > Watchdog Timer.... .. 88 6.3.10 Advanced > Super IO Configuration . ... 88 6.3.11 Advanced > Miscellaneous.. .. 90 6.3.12 Advanced > AMT Configuration.. . 91 6.3.13 Advanced > USB Configuration.. . 91 6.3.14 Advanced > AMI Graphic Output Protocol Policy ... . 92 6.3.15 Advanced > Serial Port Console Redirection .. .. 92 6.3.16 Advanced > Network Stack Configuration .. .. 94 6.3.17 Advanced > NVMe Configuration.. .. 95 6.3.18 Advanced > Trusted Computing. . 95 6.4. Chipset . ... 96 6.4.1 Chipset > System Agent (SA) Configuration.. .. 96 6.4.2 Chipset > PCH-IO Configuration.. ...101 6.5. Security Menu... ...114 6.5.1 Security > Password Description... ..114 6.6. Boot Menu... ...115 6.6.1 Boot > Boot Configuration... ...115 6.6.2 Boot > FIXED BOOT ORDER Priorities.. ...116 6.7. Save & Exit Menu .. ..117 6.7.1 Save and Exit... ..117 7. BIOS Checkpoints, Beep Codes .. . 118 8. Software Support ... . 119 8.1. Windows 10 IoT Enterprise 64-bit.. ..119 8.2. Yocto Linux 64-bit ... ...119 9. Mechanical and Thermal... . 120 9.1. Module Dimensions .. ..120 9.2. Thermal Solutions . ...121 9.2.1 Heatspreader: HTS.. ...121 9.2.2 Heatsink: THS.. ...122 9.2.3 Heatsink High Profile: THSH... ...123 9.2.4 Heatsink with Fan: THSF... ...124 # List of Figures Figure 1 – Module function diagram... ....19 Figure 2 - Module rear side row and pin numbering ....... ...20 Figure 3 – Module feature locations (top side) ... ..59 Figure 4 – Module feature locations (bottom side).... ..60 Figure 5 – Express-TL and Debug Module .... ...61 Figure 6 – Module mechanical dimensions .... .. 120 Figure 7 – Heatspreader: HTS... .. 121 Figure 8 – Heatsink: THS.... .. 122 Figure 9 – Heatsink High Profile: THSH ... .. 123 Figure 10 – Heatsink with Fan: THSF..... .. 124 # 1. Introduction The Express-TL is a COM Express® COM.0 R3.0 Basic Size Type 6 module based on the Intel® Xeon®, 11th Generation Intel® Core™, and Intel® Celeron® 6000 processors (formerly “Tiger Lake-H”) with up to 8 cores (16 threads) at maximum 4.7GHz boost frequency, features a brand new Intel® Iris® Xe high performance graphics core, and supports AVX512-VNNI (Vector Neural Network Instructions) that almost triples AI inferencing performance. Typical industries in need of such high performance, low power characteristics are industrial automation and control, medical ultra sound, image processing and analysis, high speed video encoding and streaming, predictive traffic analysis, and multi camera-based AI. The Express-TL has up to four SODIMM sockets supporting up to 128GB (4x 32GB) of DDR4 memory. Memory frequency is up to 3200 MT/s dependent on configuration. Modules equipped with the Intel® Xeon® processor and Intel® RM590E Chipset support both ECC and non-ECC SODIMMs. The integrated Intel® Iris® Xe Graphics (Gen12) includes features such as OpenGL 4.5, DirectX 12, OpenCL 2.1/2.0/1.2, Intel® Clear Video HD Technology, and DirectX Video Acceleration (DXVA) support for full H.265/HEVC 10-bit, VP9 hardware codecs. In addition, High Dynamic Range is supported for enhanced picture color and quality, and digital content protection has been upgraded to HDCP 2.3. Graphics outputs include LVDS and three DDI ports supporting HDMI/DVI/DisplayPort and eDP/VGA as a build option, with a maximum of four 4K displays supported. In addition, USB4 that can transfer media and data through single tunnel is a build option supported by project basis in place of DDI 1/2. The Express-TL is specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced development time. In addition to the onboard integrated graphics, a multiplexed PCIe x16 Gen4 graphics bus is available for discrete graphics expansion. Input/output features include up to eight PCIe Gen3 lanes that can be used for NVMe SSD, allowing application access to the highest speed storage solutions, as well as a single onboard 2.5Gigabit Ethernet port with optional Time Sensitive Network (TSN), four USB 3.2 Gen2 ports, four USB 2.0 ports, and two SATA 6 Gb/s ports. Optional onboard PCIe Gen3 NVMe SSD is offered by project basis. Support is provided for SMBus and I2 C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer. # 2. Specifications # 2.1. Core System # CPU 11th Gen Intel® Core™, Intel® Xeon®, and Intel® Celeron® Processor (formerly “Tiger Lake-H”) • Intel® Xeon® W-11865MRE, 2.6(4.7) GHz, 24MB, 45W(35W cTDP), 8C/16T • Intel® Xeon® W-11865MLE, 1.5(4.5) GHz, 24MB, 25W, 8C/16T • Intel® Core™ i7-11850HE, 2.6(4.7) GHz, 24MB, 45W(35W cTDP), 8C/16T • Intel® Xeon® W-11555MRE, 2.6(4.5) GHz, 12MB, 45W(35W cTDP), 6C/12T • Intel® Xeon® W-11555MLE, 1.9(4.4) GHz, 12MB, 25W, 6C/12T • Intel® Core™ i5-11500HE, 2.6(4.5) GHz, 12MB, 45W(35W cTDP), 6C/12T • Intel® Xeon® W-11155MRE, 2.4(4.4) GHz, 8MB, 45W(35W cTDP), 4C/8T • Intel® Xeon® W-11155MLE, 1.8(3.1) GHz, 8MB, 25W, 4C/8T • Intel® Core™ i3-11100HE, 2.4(4.4) GHz, 8MB, 45W(35W cTDP), 4C/8T Intel® Celeron® 6600HE, 2.6GHz, 8MB, 35W, 2C/2T Supporting: Intel® VT, Intel® VT-d, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.0, Intel® AVX-512, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure Key, Intel® TSX-NI (availability of features may vary between processor SKUs) # Memory Up to 128GB DDR4 in four SODIMM sockets (two on top, two on bottom), maximum 32GB per socket, maximum 3200 MT/s. Xeon® processors paired with RM590E Chipset can support both of ECC and non-ECC memory. Other processor/chipset combinations support non-ECC memory. Fourth SODIMM on bottom side is supported by build option. ![The image displays a reddish-orange icon resembling a document or piece of paper. It features a square shape with the bottom-right corner folded over. Inside the outline, there are two horizontal parallel lines centered vertically, representing text. This is the standard logo for Google Docs.](.express-tl-50m-72138-1050-15/490e078c4a60fcbf5e45fc904da0eed78de761f3ae117cbe79d0344eeb34fb4e.jpg) Note: Top SODIMM sockets must be populated first. Make sure to check that the bottom-side specs are suitable for your application purposes. # Chipset Intel® RM590E, QM580E and HM570E # Embedded BIOS AMI Aptio V UEFI with CMOS backup in 32 (or 16, TBC) MB SPI BIOS, dual BIOS by build option # 2.2. Video # GPU Intel® UHD Graphics integrated, up to 32 execution units # Feature Support • 4 independent and simultaneous combinations of DisplayPort/HDMI/LVDS graphics outputs (4x 4K @60Hz) • (eDP optional in place of LVDS, VGA optional in place of DDI 3) • Encode/transcode HD content • Playback of high-definition content including Blu-ray Disc and Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D) • DirectX Video Acceleration (DXVA) support for accelerated video processing • HEVC/H.265, H.264, M/JPEG, MPEG2, AV1, WMV9, VP9 HW decode HEVC/H.265, H.264, JPEG, VP9 HW encode • Advanced Scheduler 2.0, 1.0, XPDM support DirectX up to 12 • OpenGL up to 4.5 and ES 2.0 support • OpenCL up to 2.1 support ![The image shows a red outline icon resembling a document or page with its bottom-right corner folded over. Inside the white square, there are two horizontal red bars centered vertically.](.express-tl-50m-72138-1050-15/d7b9873f503ab616847e156867c0d91b0c4b56f53f5bf5c8ee3760d9b7d29114.jpg) Note: Availability of features is dependent on the operating system (Windows 10 64-bit, Linux 64-bit). # 2.2.1 Display Interface Support LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, supports DE mode and Hsync/Vsync mode. Max. resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported. eDP: eDP 1.4b up to 4 lane support, in place of LVDS (BOM option), up to 4096x2304@60Hz bpp with DSC DDI x3: Digital Display Ports (DDI) support DisplayPort 1.4a, HDMI 2.0b or DVI VGA: VGA BOM option support in place of DDI 3; max. resolution 1920x1200@60Hz ![The image displays a red icon on a white background. It is shaped like a document or page with a folded upper-right corner. Inside the red outline, there are three thick, horizontal red bars arranged vertically, resembling lines of text.](.express-tl-50m-72138-1050-15/c84a3f4da23303e6574f5a1c7f66d3f3e41c6933004b00230f5d2a946eb2a2bc.jpg) Note: USB4 is a build option (HW and BIOS) supported by project basis in place of DDI channels. Maximum 2x USB4 by using DDI 1 and DDI 2 channels. USB4 support also requires re-timer and PD on carrier. # 2.3. Audio Intel® HD Audio integrated Located on carrier Express-BASE6 (ALC886 standard support) # 2.4. Expansion Busses 1 PCI Express x16 Gen4: PEG0-15 (configurable to 1 x16, 2 x8 or 1 x8 + 2 x4). Gen4 support dependent on carrier design. 8 PCI Express x1 Gen3: Lanes 0-3 (configurable to 4 x1, 2 x2, 1 x4, 1 x2 + 2 x1) and Lanes 4-7 (configurable to 4 x1, 2 x2, 1 x4, 1 x2 + 2 x1) Other: SMBus (system), I2 C (user), LPC bus (via eSPI to LPC bridge IC) # 2.5. Ethernet 2.5GbE Intel® Ethernet Controller I225 Series (V, IT or LM version) Supports up to 2.5GbE and 1000/100/10 Mbit/s connections IT version supports TSN feature on Linux OS, GbE0\_SDP available if TSN support enabled Intel® Core™ and Celeron® processors pair with I225-V, Intel® Xeon® processor pairs with I225-IT by default, other combinations supported by project basis # 2.6. Multi I/O and Storage # USB 4x USB 3.2 Gen2 (USB 0,1,2,3), 4x USB 2.0/1.1 (USB 4,5,6,7) SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling ![The image displays a square icon with a thick red outline resembling a piece of paper with the top-right corner folded down. Inside the shape, two horizontal red lines are centered vertically, resembling an equals sign.](.express-tl-50m-72138-1050-15/1bcdc84dd9bc709e96dcaf14e524ae7c86b7e8eb2a53525351b11e686d8b8a6e.jpg) Note: Carrier board must be designed for Gen2 operation. USB 0,1,2,3 are backward compatible with USB 2.0/1.1. # SATA 4x SATA 6Gb/s (SATA 0,1,2,3) ![The image displays a simple icon of a document. It features a red outline of a piece of paper with a folded corner at the top right. Inside the white interior, there are two horizontal red lines centered on the page.](.express-tl-50m-72138-1050-15/3300476375fb6c2647cebafae9679bcf05253c2a311638aa72cb21ff439d59b0.jpg) Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board # GPIO or SD 4 GPO and 4 GPI (GPI with interrupt) # On-board Storage Soldered type PCIe NVMe SSD, available capacities: 60GB/120GB/240GB. Build option support by project basis ![The image displays a red icon representing a document or page against a white background. It features a thick red outline with a folded top-right corner. Inside the white interior, there are two horizontal red lines of varying lengths, resembling text or a list.](.express-tl-50m-72138-1050-15/5c0a95378de5c33fdbbd34ce9afde4e1b45ad8804fc09c14ce39555b2ee08382.jpg) Note: For the NVMe SSD build option, DIMM support is limited to 3 slots. Please contact your local ADLINK representative for details. # UART Two UART interfaces SER0 and SER1 RX/TX on module Console Redirection via COM 1 or COM 2 selectable in BIOS Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

COM Port	Description	IRQ	Address	Console Redirection Support
COM 1	Supported by module (SER0, A98/A99), via embedded controller	4	0x3F8	Yes
COM 2	Supported by module (SER1, A101/A102), via embedded controller	3	0x2F8	Yes
COM 3	Supported by Super I/O (W83627DHG) on carrier board	5	0x240	Yes
COM 4	Supported by Super I/O (W83627DHG) on carrier board	7	0x248	Yes

![The image displays a red outline icon resembling a document or piece of paper with the top-right corner curled inward. Inside the outline, there are three horizontal lines: two shorter lines near the top and one longer line below them, suggesting text or a list.](.express-tl-50m-72138-1050-15/d186898121ed95f83d29345dcb31a5b5a61af92de55a36171b8d71945c1b118e.jpg) Note: SER0, SER1 from SoC HSUART are BOM option support by project basis # 2.7. Trusted Platform Module (TPM) Chipset: Infineon solution Type: TPM 2.0 (SPI bus based) # 2.8. SEMA Board controller Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2 C, failsafe BIOS (dual BIOS, opt. support), watchdog timer and fan control # 2.9. Debug 30-pin flat cable connector for use with DB-30 x86 debug module Supports embedded controller access, SPI BIOS flashing, internal power rail test points, debug LEDs # 2.10. Power Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller) Standard Voltage Input: ATX: 12V±5% / 5Vsb ±5% or AT: 12V±5% Wide Voltage Input: ATX: 8.5-20V, 5Vsb ±5% or AT: 8.5-20V Power Management: ACPI 5.0 compliant, Smart Battery support Power States: C1-C6, S0, S1, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5) ECO Mode support for deep S5 for 5Vsb power saving # Power Consumption Please contact your ADLINK representative for the document “COM Express Module Power Consumption”. # 2.11. Mechanical and Environmental # Form Factor and specification PICMG COM Express Rev 3.0 (COM.0 R3.0), Type 6, Basic size 125 x 95 mm # Operating Temperature Standard 0°C to 60°C (wide voltage input) Storage: -20°C to 80°C Extreme Rugged -40°C to 85°C (selected SKUs, up to 2933MT/s memory frequency) Storage: -40°C to 85°C (selected SKUs) # Humidity 5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # HALT tested Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # 3. Block Diagram ![Based on the provided block diagram, here is the accurate and concise description of the labeled blocks and their connections:\n\n**1. Processor Block**\n* **Main Block:** 'Intel® Xeon® 11th Gen Intel® Core™ / Celeron® Processor (Tiger Lake-H)'\n* **Connections:**\n * **Inputs (Left):** Connected to two blocks labeled 'DDR4 SODIMM up to 3200 MT/s' (one labeled '3rd, 4th socket dependent on SKU' and the other 'ECC, non-ECC dependent on CPU/chipset config.'). Connected to 'eDP x4' (via a block labeled 'eDP to LVDS'). Connected via dashed line to 'DP to VGA'.\n * **Outputs (Right):** 'TCP 0' connects to 'DDI 1 / USB4'. 'TCP 1' connects to 'DDI 2 / USB4'. 'TCP 2' connects to 'DDI 3'. '16 PCIe Gen4' connects to '1 x16 or 2 x8 or 1 x8 + 2 x4' which then connects to 'PEG Port PCIe 16-31'.\n * **Downward Connection:** 'DMI (x8, Gen3)' connects to the Chipset Block.\n * **Internal Label:** 'DDI 8 (eDP 4lanes)'.\n\n**2. Chipset Block**\n* **Main Block:** 'Mobile Intel Next Series Chipset RM590E/QM580E/HM570E'\n* **Connections:**\n * **Inputs (Left):**\n * 'USB 2.0 Lane 0-7'\n * 'SATA Port 0-3' (labeled 'SATA 6Gb/s')\n * 'Max. 2.5GbE' (via 'LAN Controller Intel I225' labeled 'TSN dependent on controller SKU')\n * 'PCIe Lane 0-3' (labeled '1 x4, 2 x2, 4 x1', '1 PCIe Gen3', '4 PCIe Gen3')\n * 'PCIe Lane 4-5' (labeled '2 x1, 1 x2', '2 PCIe Gen3', '1 x4 (Lane 4-7)')\n * 'HDA'\n * 'SPI' (via 'BIOS Flash' labeled 'TPM 2.0')\n * 'SMBus'\n * 'I2C'\n * **Outputs (Right):**\n * Four lines labeled 'USB 3.2 Gen2 x1' connect to 'USB 3.0 Lane 3', 'USB 3.0 Lane 2', 'USB 3.0 Lane 1', and 'USB 3.0 Lane 0'.\n * '2 PCIe Gen3' connects to '2 x1, 1 x2'.\n * '2 PCIe Gen3' connects to '1 x4 (Lane 4-7)' which then connects to 'PCIe Lane 6-7'.\n * '2 PCIe Gen3' connects via 'x2' to 'build option BGA SSD'.\n * 'DB30 x86 Connector' (connected via dashed line).\n * **Other Connections:**\n * 'HSUART' connects to the Embedded Controller.\n * 'eSPI' connects to 'eSPI to LPC' which connects to the Embedded Controller.\n\n**3. Embedded Controller Block**\n* **Main Block:** 'Embedded Controller'\n* **Connections:**\n * **Inputs:** Connected to '8xGPIO/SDIO', '2xUART/CAN', and 'LPC/eSPI'. Also receives connections from 'eSPI to LPC' and 'HSUART' (from the Chipset).\n * **Outputs:** Connects to 'Fan Connector' and 'LM73 (board)'.](.express-tl-50m-72138-1050-15/7869998c8ff7cef64f8fa6b7cb5802cc15f465b6e9f581dafb7f14c6ae5661ad.jpg) Figure 1 – Module function diagram # 4. Pinout and Signal Descriptions # 4.1. Pin Summary The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 6 in the PICMG COM.0 R3.0 specification. Signals described in the specification but not supported on the Express-TL are marked with strike-through. ![3rd, 4th socket depends on SKUs\nNVMe SSD optional\nD1\nCD\nC1\nB1\nAB\nA1 10\nA1](.express-tl-50m-72138-1050-15/31a2780d72e5c1469151e58fa03e458e52bb551de8016a201121ceb92dd7b251.jpg) Figure 2 - Module rear side row and pin numbering

Row A		Row B		Row C		Row D
A1	GND (FIXED)	B1	GND (FIXED)	C1	GND FIXED)	D1	GND FIXED)
A2	GBE0_MDI3-	B2	GBE0_ACT#	C2	GND	D2	GND
A3	GBE0_MDI3+	B3	LPC_FRAME#/ESPI_CS0#	C3	USB_SSRX0-	D3	USB_SSTX0-
A4	GBE0_LINK100# *	B4	LPC_AD0/ESPI_IO_0	C4	USB_SSRX0+	D4	USB_SSTX0+
A5	GBE0_LINK1000# *	B5	LPC_AD1/ESPI_IO_1	C5	GND	D5	GND
A6	GBE0_MDI2-	B6	LPC_AD2/ESPI_IO_2	C6	USB_SSRX1-	D6	USB_SSTX1-
A7	GBE0_MDI2+	B7	LPC_AD3/ESPI_IO_3	C7	USB_SSRX1+	D7	USB_SSTX1+
A8	GBE0_LINK#	B8	LPC_DRQ0#/ESPI_ALERT0#	C8	GND	D8	GND
A9	GBE0_MDI1-	B9	LPC_DRQ1#/ESPI_ALERT1#	C9	USB_SSRX2-	D9	USB_SSTX2-
A10	GBE0_MDI1+	B10	LPC_CLK/ESPI_CK	C10	USB_SSRX2+	D10	USB_SSTX2+
A11	GND (FIXED)	B11	GND (FIXED)	C11	GND (FIXED)	D11	GND (FIXED)
A12	GBE0_MDI0-	B12	PWRBTN#	C12	USB_SSRX3-	D12	USB_SSTX3-
A13	GBE0_MDI0+	B13	SMB_CK	C13	USB_SSRX3+	D13	USB_SSTX3+
A14	GBE0_CTREF	B14	SMB_DAT	C14	GND	D14	GND
A15	SUS_S3#	B15	SMB_ALERT#	C15	DDI1_PAIR6+	D15	DDI1_CTRLCLK_AUX+
A16	SATAO_TX+	B16	SATA1_TX+	C16	DDI1_PAIR6-	D16	DDI1_CTRLDATA_AUX-
A17	SATAO_TX-	B17	SATA1_TX-	C17	RSVD	D17	RSVD
A18	SUS_S4#	B18	SUS_STAT#/ESPI_RESET#	C18	RSVD	D18	RSVD
A19	SATAO_RX+	B19	SATA1_RX+	C19	PCIE_RX6+	D19	PCIE_TX6+
A20	SATAO_RX-	B20	SATA1_RX-	C20	PCIE_RX6-	D20	PCIE_TX6-
A21	GND (FIXED)	B21	GND (FIXED)	C21	GND (FIXED)	D21	GND (FIXED)
A22	SATA2_TX+	B22	SATA3_TX+	C22	PCIE_RX7+	D22	PCIE_TX7+
A23	SATA2_TX-	B23	SATA3_TX-	C23	PCIE_RX7-	D23	PCIE_TX7-
A24	SUS_S5#	B24	PWR_OK	C24	DDI1_HPD	D24	RSVD
A25	SATA2_RX+	B25	SATA3_RX+	C25	DDI1_PAIR4+	D25	GND
A26	SATA2_RX-	B26	SATA3_RX-	C26	DDI1_PAIR4-	D26	DDI1_PAIR0+
A27	BATLOW#	B27	WDT	C27	RSVD	D27	DDI1_PAIR0-
A28	(S)ATA_ACT#	B28	AC/HDA_SDIN2	C28	RSVD	D28	GND
A29	AC/HDA_SYNC	B29	AC/HDA_SDIN1	C29	DDI1_PAIR5+	D29	DDI1_PAIR1+
A30	AC/HDA_RST#	B30	AC/HDA_SDIN0	C30	DDI1_PAIR5-	D30	DDI1_PAIR1-
A31	GND (FIXED)	B31	GND (FIXED)	C31	GND (FIXED)	D31	GND (FIXED)
A32	AC/HDA_BITCLK	B32	SPKR	C32	DDI2_CTRLCLK_AUX+	D32	DDI1_PAIR2+
A33	AC/HDA_SDOUT	B33	I2C_CK	C33	DDI2_CTRLDATA_AUX-	D33	DDI1_PAIR2-
A34	BIOS_DIS0#/ESPI_SAFS	B34	I2C_DAT	C34	DDI2_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL
A35	THRMTRIP#	B35	THRM#	C35	RSVD	D35	RSVD
A36	USB6-	B36	USB7-	C36	DDI3_CTRLCLK_AUX+	D36	DDI1_PAIR3+
A37	USB6+	B37	USB7+	C37	DDI3_CTRLDATA_AUX-	D37	DDI1_PAIR3-
A38	USB_6_7_OC#	B38	USB_4_5_OC#	C38	DDI3_DDC_AUX_SEL	D38	GND
A39	USB4-	B39	USB5-	C39	DDI3_PAIR0+	D39	DDI2_PAIR0+
A40	USB4+	B40	USB5+	C40	DDI3_PAIR0-	D40	DDI2_PAIR0-
A41	GND (FIXED)	B41	GND (FIXED)	C41	GND (FIXED)	D41	GND (FIXED)
A42	USB2-	B42	USB3-	C42	DDI3_PAIR1+	D42	DDI2_PAIR1+
A43	USB2+	B43	USB3+	C43	DDI3_PAIR1-	D43	DDI2_PAIR1-
A44	USB_2_3_OC#	B44	USB_0_1_OC#	C44	DDI3_HPD	D44	DDI2_HPD
A45	USB0-	B45	USB1-	C45	RSVD	D45	GND
A46	USB0+	B46	USB1+	C46	DDI3_PAIR2+	D46	DDI2_PAIR2+
A47	VCC_RTC	B47	ESPI_EN#	C47	DDI3_PAIR2-	D47	DDI2_PAIR2-
A48	RSVD	B48	USB0_HOST_PRSNT	C48	RSVD	D48	GND
A49	GBE0_SDP	B49	SYS_RESET#	C49	DDI3_PAIR3+	D49	DDI2_PAIR3+
A50	LPC_SERIRQ/ESPI_CS1#	B50	CB_RESET#	C50	DDI3_PAIR3-	D50	DDI2_PAIR3-
A51	GND (FIXED)	B51	GND (FIXED)	C51	GND (FIXED)	D51	GND (FIXED)
A52	PCIE_TX5+	B52	PCIE_RX5+	C52	PEG_RX0+	D52	PEG_TX0+
A53	PCIE_TX5-	B53	PCIE_RX5-	C53	PEG_RX0-	D53	PEG_TX0-
A54	GPIO	B54	GPO1	C54	TYPE0#	D54	PEG_LANE_RV#
A55	PCIE_TX4+	B55	PCIE_RX4+	C55	PEG_RX1+	D55	PEG_TX1+
A56	PCIE_TX4-	B56	PCIE_RX4-	C56	PEG_RX1-	D56	PEG_TX1-
A57	GND	B57	GPO2	C57	TYPE1#	D57	TYPE2#
A58	PCIE_TX3+	B58	PCIE_RX3+	C58	PEG_RX2+	D58	PEG_TX2+
A59	PCIE_TX3-	B59	PCIE_RX3-	C59	PEG_RX2-	D59	PEG_TX2-
A60	GND (FIXED)	B60	GND (FIXED)	C60	GND (FIXED)	D60	GND (FIXED)
A61	PCIE_TX2+	B61	PCIE_RX2+	C61	PEG_RX3+	D61	PEG_TX3+
A62	PCIE_TX2-	B62	PCIE_RX2-	C62	PEG_RX3-	D62	PEG_TX3-
A63	GPI1	B63	GPO3	C63	RSVD	D63	RSVD
A64	PCIE_TX1+	B64	PCIE_RX1+	C64	RSVD	D64	RSVD
A65	PCIE_TX1-	B65	PCIE_RX1-	C65	PEG_RX4+	D65	PEG_TX4+
A66	GND	B66	WAKE0#	C66	PEG_RX4-	D66	PEG_TX4-
A67	GPI2	B67	WAKE1#	C67	RAPID_SHUTDOWN	D67	GND
A68	PCIE_TX0+	B68	PCIE_RX0+	C68	PEG_RX5+	D68	PEG_TX5+
A69	PCIE_TX0-	B69	PCIE_RX0-	C69	PEG_RX5-	D69	PEG_TX5-
A70	GND (FIXED)	B70	GND (FIXED)	C70	GND (FIXED)	D70	GND (FIXED)
A71	LVDS_A0+ / eDP_TX2+	B71	LVDS_B0+	C71	PEG_RX6+	D71	PEG_TX6+
A72	LVDS_A0- / eDP_TX2-	B72	LVDS_B0-	C72	PEG_RX6-	D72	PEG_TX6-
A73	LVDS_A1+ / eDP_TX1+	B73	LVDS_B1+	C73	GND	D73	GND
A74	LVDS_A1- / eDP_TX1-	B74	LVDS_B1-	C74	PEG_RX7+	D74	PEG_TX7+
A75	LVDS_A2+ / eDP_TX0+	B75	LVDS_B2+	C75	PEG_RX7-	D75	PEG_TX7-
A76	LVDS_A2- / eDP_TX0-	B76	LVDS_B2-	C76	GND	D76	GND
A77	LVDS_VDD_EN / eDP_VDD_EN	B77	LVDS_B3+	C77	RSVD	D77	RSVD
A78	LVDS_A3+	B78	LVDS_B3-	C78	PEG_RX8+	D78	PEG_TX8+
A79	LVDS_A3-	B79	LVDS_BKLT_EN	C79	PEG_RX8-	D79	PEG_TX8-
A80	GND (FIXED)	B80	GND (FIXED)	C80	GND (FIXED)	D80	GND (FIXED)
A81	LVDS_A_CK+ / eDP_TX3+	B81	LVDS_B_CK+	C81	PEG_RX9+	D81	PEG_TX9+
A82	LVDS_A_CK- / eDP_TX3-	B82	LVDS_B_CK-	C82	PEG_RX9-	D82	PEG_TX9-
A83	LVDS_I2C_CK / eDP_AUX+	B83	LVDS_BKLT_CTRL / eDP_BKLT_CTRL	C83	RSVD	D83	RSVD
A84	LVDS_I2C_DAT / eDP_AUX-	B84	VCC_5V_SBY	C84	GND	D84	GND
A85	GPI3	B85	VCC_5V_SBY	C85	PEG_RX10+	D85	PEG_TX10+
A86	RSVD	B86	VCC_5V_SBY	C86	PEG_RX10-	D86	PEG_TX10-
A87	eDP_HPD	B87	VCC_5V_SBY	C87	GND	D87	GND
A88	PCIE0_CK_REF+	B88	BIOS_DIS1#	C88	PEG_RX11+	D88	PEG_TX11+
A89	PCIE0_CK_REF-	B89	VGA_RED *	C89	PEG_RX11-	D89	PEG_TX11-
A90	GND (FIXED)	B90	GND (FIXED)	C90	GND (FIXED)	D90	GND (FIXED)
A91	SPI_POWER	B91	VGA_GRN *	C91	PEG_RX12+	D91	PEG_TX12+
A92	SPI_MISO	B92	VGA_BLU *	C92	PEG_RX12-	D92	PEG_TX12-
A93	GPO0	B93	VGA_HSYNC *	C93	GND	D93	GND
A94	SPI_CLK	B94	VGA_VSYNC *	C94	PEG_RX13+	D94	PEG_TX13+
A95	SPI_MOSI	B95	VGA_I2C_CK *	C95	PEG_RX13-	D95	PEG_TX13-
A96	TPM_PP	B96	VGA_I2C_DAT *	C96	GND	D96	GND
A97	TYPE10#	B97	SPI_CS#	C97	RSVD	D97	RSVD
A98	SER0_TX	B98	RSVD	C98	PEG_RX14+	D98	PEG_TX14+
A99	SER0_RX	B99	RSVD	C99	PEG_RX14-	D99	PEG_TX14-
A100	GND (FIXED)	B100	GND (FIXED)	C100	GND (FIXED)	D100	GND (FIXED)
A101	SER1_TX/CAN_TX	B101	FAN_PWMOUT	C101	PEG_RX15+	D101	PEG_TX15+
A102	SER1_RX/CAN_RX	B102	FAN_TACHIN	C102	PEG_RX15-	D102	PEG_TX15-
A103	LID#	B103	SLEEP#	C103	GND	D103	GND
A104	VCC_12V	B104	VCC_12V	C104	VCC_12V	D104	VCC_12V
A105	VCC_12V	B105	VCC_12V	C105	VCC_12V	D105	VCC_12V
A106	VCC_12V	B106	VCC_12V	C106	VCC_12V	D106	VCC_12V
A107	VCC_12V	B107	VCC_12V	C107	VCC_12V	D107	VCC_12V
A108	VCC_12V	B108	VCC_12V	C108	VCC_12V	D108	VCC_12V
A109	VCC_12V	B109	VCC_12V	C109	VCC_12V	D109	VCC_12V
A110	GND (FIXED)	B110	GND (FIXED)	C110	GND (FIXED)	D110	GND (FIXED)

![The image features a red outline of a document icon with a folded upper-right corner. Inside the outline are three horizontal red lines stacked vertically, resembling text.](.express-tl-50m-72138-1050-15/3f39d08a64c61d92251410292f79c47affbbbf592ce5b924e7bdd7c556e306f7.jpg) Note: Strike-through entries are not supported functions on this product. eDP (in place of LVDS) and VGA (in place of DDI 3) are BOM option support by project basis. Ethernet support up to 2.5GbE. LAN LED behavior (GBE0\_LINK 100#, GBE0\_LINK1000#) is optimized based on maximum 2.5GbE speed (see 4.3.4 Gigabit Ethernet on page 31). Maximum 2x USB4 is a build option in place of DDI 1, DDI 2 channels by project basis. Please contact your local representative for details. # 4.2. Signal Terminology Descriptions Meaning of the terms used for signal description tables

Term	Description
I	Input to the module
O	Output from the module
I/O	Bi-directional Input / Output
OD	Open drain output from the module

I 3.3V	Input 3.3V tolerant
I 5V	Input 5V tolerant
O 3.3V	Output 3.3V signal level
O 5V	Output 5V signal level
I/O 3.3V	Bi-directional signal 3.3V tolerant
I/O 5V	Bi-directional signal 5V tolerant
I/O $3.3V_{SB}$	Input or output 3.3V tolerant active in standby state

DDC	Display Data Channel
PCIE	PCI Express compatible differential signal
PEG	PCI Express Graphics
SATA	Serial ATA specification Revision 2.6 and 3
LVDS	Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal

P	Power Input / Output
REF	Reference voltage output. May be sourced from a Module power plane.
PDS	Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.

PU	PU (pull-up) resistor on module
PD	PD (pull-down) resistor on module

# 4.3. AB Connector Signal Descriptions 4.3.1 Audio

Name	Pin #	Description	I/O	PU / PD	Comment

AC_RST# / HDA_RST#	A30	Reset output to CODEC, active low.	O3.3VSB
AC_SYNC / HDA_SYNC	A29	Sample-synchronization signal to the CODEC(s).	O3.3VSB		PCH internal PD 20Kohm
AC_BITCLK / HDA_BITCLK	A32	Serial data clock generated by the external CODEC(s).	I/O3.3VSB
AC_SDOUT / HDA_SDOUT	A33	Serial TDM data output to the CODEC.	O3.3VSB		PCH internal PD 20Kohm
AC_SDIN[2:0] / HDA_SDIN[2:0]	B28B29B30	Serial TDM data inputs from up to 3 CODECs.	I/O3.3VSB		PCH internal PD 20KohmAC_SDNI2/HDA_SDIN2 not supported

4.3.2 Analog VGA

Name	Pin #	Description	I/O	PU / PD	Comment

VGA_RED	B89	Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_GRN	B91	Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_BLU	B92	Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R
VGA_HSYNC	B93	Horizontal sync output to VGA monitor	O 3.3V
VGA_VSYNC	B94	Vertical sync output to VGA monitor	O 3.3V
VGA_I2C_CK	B95	DDC clock line (I2C port dedicated to identifying VGA monitor capabilities)	I/O OD 3.3V	PU 2k2 3.3V
VGA_I2C_DAT	B96	DDC data line.	I/O OD 3.3V	PU 2k2 3.3V

![The image displays a red icon of a folded document or note. It features a white square shape with the bottom-right corner folded down. Inside the white area, there are two horizontal red lines stacked vertically.](.express-tl-50m-72138-1050-15/5423ad94090666fd14b759c7ef82ef7e3bbe7932e1b5c8ef23cc759a390f664b.jpg) Note: VGA is BOM option support (in place of DDI 3) by project basis # 4.3.3 LVDS or eDP The module default supports a single or dual channel LVDS display panel with up to 24-bit colors. A BOM option that removes the eDP to LVDS bridge IC and outputs the eDP signals directly is available. eDP vs LVDS pin mapping is described below.

Pin #	LVDS mode	eDP mode
A71	LVDS_A0+	eDP_TX2+
A72	LVDS_A0-	eDP_TX2-
A73	LVDS_A1+	eDP_TX1+
A74	LVDS_A1-	eDP_TX1-
A75	LVDS_A2+	eDP_TX0+
A76	LVDS_A2-	eDP_TX0-
A78	LVDS_A3+	-
A79	LVDS_A3-	-
A81	LVDS_A_CK+	eDP_TX3+
A82	LVDS_A_CK-	eDP_TX3-
B71	LVDS_B0+	-
B72	LVDS_B0-	-
B73	LVDS_B1+	-
B74	LVDS_B1-	-
B75	LVDS_B2+	-
B76	LVDS_B2-	-
B77	LVDS_B3+	-
B78	LVDS_B3-	-
B81	LVDS_B_CK+	-
B82	LVDS_B_CK-	-
A77	LVDS_VDD_EN	eDP_VDD_EN
B79	LVDS_BKLT_EN	eDP_BKLT_EN
B83	LVDS_BKLT_CTRL	eDP_BKLT_CTRL
A83	LVDS_I2C_CK	eDP_AUX+
A84	LVDS_I2C_DAT	eDP_AUX-
A87	-	eDP_HPD

![The image displays a red icon resembling a notepad or memo. It features a white square shape with rounded corners and a folded top-right corner. Inside the white area, there are two horizontal red lines stacked vertically near the center.](.express-tl-50m-72138-1050-15/06236157a58d05182a4e281fdeb8e7fa50332ac10366dc011118ba8dcc06a249.jpg) Note: LVDS is the default mode and eDP is a BOM option 4.3.3.1. Single/Dual Channel LVDS (default)

Name	Pin #	Description	I/O	PU / PD	Comment

LVDS_A0+	A71	LVDS Channel A differential pairs	O LVDS
LVDS_A0-	A72
LVDS_A1+	A73
LVDS_A1-	A74
LVDS_A2+	A75
LVDS_A2-	A76
LVDS_A3+	A78
LVDS_A3-	A79
LVDS_A_CK+	A81	LVDS Channel A differential clock	O LVDS
LVDS_A_CK-	A82
LVDS_B0+	B71	LVDS Channel B differential pairs	O LVDS
LVDS_B0-	B72
LVDS_B1+	B73
LVDS_B1-	B74
LVDS_B2+	B75
LVDS_B2-	B76
LVDS_B3+	B77
LVDS_B3-	B78
LVDS_B_CK+	B81	LVDS Channel B differential clock	O LVDS
LVDS_B_CK-	B82
LVDS_VDD_EN	A77	LVDS panel power enable	O 3.3V	PD 100K
LVDS_BKLT_EN	B79	LVDS panel backlight enable	O 3.3V	PD 100K
LVDS_BKLT_CTRL	B83	LVDS panel backlight brightness control	O 3.3V	PD 100K
LVDS_I2C_CK	A83	DDC lines used for flat panel detection and control.	O 3.3V	PU 2k2 3.3V
LVDS_I2C_DAT	A84	DDC lines used for flat panel detection and control.	I/O 3.3V	PU 2k2 3.3V

4.3.3.2. 4-lane eDP

Name	Pin #	Description	I/O	PU / PD	Comment

eDP_TX3+	A81	eDP differential pairs	O PCIE		AC coupled off module
eDP_TX3-	A82
eDP_TX2+	A71
eDP_TX2-	A72
eDP_TX1+	A73
eDP_TX1-	A74
eDP_TX0+	A75
eDP_TX0-	A76
eDP_VDD_EN	A77	eDP power enable	O 3.3V	PD 100K
eDP_BKLT_EN	B79	eDP backlight enable	O 3.3V	PD 100K
eDP_BKLT_CTRL	B83	eDP backlight brightness control	O 3.3V	PD 100K
eDP_AUX+	A83	eDP AUX+	I/O PCIE		AC coupled off module
eDP_AUX-	A84	eDP AUX-	I/O PCIE		AC coupled off module
eDP_HPD	A87	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	PD 100K on this pin when eDP is supported

4.3.4 Gigabit Ethernet

Name	Pin #	Description				I/O	PU / PD	Comment

GBE0_MDI0+	A13	Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:				I/O Analog		Twisted pair signals for external transformer.
GBE0_MDI0-	A12
GBE0_MDI1+	A10
GBE0_MDI1-	A9	1000		100	10
GBE0_MDI2+	A7	MDI[0]+/-	B1_DA+/-	TX+/-	TX+/-
GBE0_MDI2-	A6	MDI[1]+/-	B1_DB+/-	RX+/-	RX+/-
GBE0_MDI3+	A3	MDI[2]+/-	B1_DC+/-
GBE0_MDI3-	A2	MDI[3]+/-	B1_DD+/-
GBE0_ACT#	B2	Gigabit Ethernet Controller 0 activity indicator, active low.				OD 3.3VSB
GBE0_LINK#	A8	Gigabit Ethernet Controller 0 link indicator, active low.				OD 3.3VSB
GBE0_LINK100# *	A4	Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.				OD 3.3VSB
GBE0_LINK1000# *	A5	Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.				OD 3.3VSB
GBE0_CTREF	A14	Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.				REF GND min 3.3V max		Not supported
GBE0_SDP	A49	Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.				IO 3.3VSB	GBE0_SDP	Depends on the selection of LAN controller. i225-IT support this pin

![The image displays a red icon resembling a document or file with a folded bottom-right corner. Inside the document's outline, there are two horizontal lines.](.express-tl-50m-72138-1050-15/b41d1d47f3ee501c06391998812483d22c2604c450c6abc6589d0630eeb36068.jpg) Note: This product supports up to 2.5GbE. The LAN LED behavior is optimized for maximum 2.5GbE speed. GBE0\_LINK1000# will be active for 2.5GbE speed indication. GBE0\_LINK100# will be active for 1GbE speed indication or lower. GBE0\_ACT# and GBE0\_LINK# share the same source from the LAN controller. For 100Mbit/sec and 10Mbit/sec speed, the LAN LED will be OFF. 4.3.5 SATA

Name	Pin #	Description	I/O	PU / PD	Comment

SATA0_TX+SATA0_TX-	A16A17	Serial ATA channel 0, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA0_RX+SATA0_RX-	A19A20	Serial ATA channel 0, Receive Input differential pair.	I SATA		AC coupled on Module
SATA1_TX+SATA1_TX-	B16B17	Serial ATA channel 1, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA1_RX+SATA1_RX-	B19B20	Serial ATA channel 1, Receive Input differential pair.	I SATA		AC coupled on Module
SATA2_TX+SATA2_TX-	A22A23	Serial ATA channel 2, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA2_RX+SATA2_RX-	A25A26	Serial ATA channel 2, Receive Input differential pair.	I SATA		AC coupled on Module
SATA3_TX+SATA3_TX-	B22B23	Serial ATA channel 3, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA3_RX+SATA3_RX-	B25B26	Serial ATA channel 3, Receive Input differential pair.	I SATA		AC coupled on Module
(S)ATA_ACT#	A28	ATA (parallel and serial) or SAS activity indicator, active low.	O 3.3V	PU 10K3.3V	AC coupled on Module

4.3.5.1. PCH HSIO Lane Assignments

Name	HSIO name on SOC	Comment

SATA0	HSIO 26
SATA1	HSIO 27
SATA2	HSIO 28
SATA3	HSIO 29

4.3.6 PCI Express

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX0+PCIE_TX0-	A68A69	PCI Express channel 0, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX0+PCIE_RX0-	B68B69	PCI Express channel 0, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX1+PCIE_TX1-	A64A65	PCI Express channel 1, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX1+PCIE_RX1-	B64B65	PCI Express channel 1, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX2+PCIE_TX2-	A61A62	PCI Express channel 2, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX2+PCIE_RX2-	B61B62	PCI Express channel 2, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX3+PCIE_TX3-	A58A59	PCI Express channel 3, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX3+PCIE_RX3-	B58B59	PCI Express channel 3, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX4+PCIE_TX4-	A55A56	PCI Express channel 4, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX4+PCIE_RX4-	B55B56	PCI Express channel 4, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX5+PCIE_TX5-	A52A53	PCI Express channel 5, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX5+PCIE_RX5-	B52B53	PCI Express channel 5, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_CLK_REF+PCIE_CLK_REF-	A88A89	PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.	O PCIE

4.3.6.1. PCH HSIO Lane Assignments

Name	HSIO name on SOC	Comment

PCIE0	HSIO 22
PCIE1	HSIO 23
PCIE2	HSIO 24
PCIE3	HSIO 25
PCIE4	HSIO 30
PCIE5	HSIO 31
PCIE6	HSIO 32
PCIE7	HSIO 33

4.3.7 LPC Bus

Name	Pin #	Description	I/O	PU / PD	Comment

LPC_AD0	B4	LPC multiplexed address, command and data bus	I/O 3.3VSB
LPC_AD1	B5
LPC_AD2	B6
LPC_AD3	B7
LPC_FRAME#	B3	LPC frame indicates the start of an LPC cycle	O 3.3VSB
LPC_DRQ0#	B8	LPC serial DMA request	I 3.3V		Not connected
LPC_DRQ1#	B9
LPC_SERIRQ	A50	LPC serial interrupt	I/O 3.3VSB	PU 8.2K3.3VSB
LPC_CLK	B10	LPC clock output -33MHz nominal	O 3.3VSB		The LPC_CLK frequency is 24MHz on this platform

![The image features a red icon depicting a document or page with a folded bottom-right corner. Inside the white area, there are two horizontal red lines centered vertically.](.express-tl-50m-72138-1050-15/564c8982bf08f3ff9e0e57711c8669f09e4a5f8cfcc93b48a0d0484708f484a2.jpg) Note: LPC Bus is supported by an eSPI to LPC bridge IC 4.3.8 USB

Name	Pin #	Description	I/O	PU / PD	Comment

USB0+USB0-	A46A45	USB differential data pairs for Port 0	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB1+USB1-	B46B45	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB2+USB2-	A43A42	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB3+USB3-	B43B42	USB differential data pairs for Port 2	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB4+USB4-	A40A39	USB differential data pairs for Port 3	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB5+USB5-	B40B39	USB differential data pairs for Port 4	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB6+USB6-	A37A36	USB differential data pairs for Port 5	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB7+USB7-	B37B37	USB differential data pairs for Port 6	I/O 3.3VSB		USB 1.1/ 2.0 compliant
USB_0_1_OC#	B44	USB over-current sense, USB ports 0 and 1 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_2_3_OC#	A44	USB over-current sense, USB ports 2 and 3 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_4_5_OC#	B38	USB over-current sense, USB ports 4 and 5 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB_6_7_OC#	A38	USB over-current sense, USB ports 6 and 7 (see *Note)	I 3.3VSB	PU 10K 3.3VSB	Do not pull high on carrier
USB0_HOST_PRSNT	B48	Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.	I 3.3VSB		Not supported

![The image displays a red icon of a document or paper. It features a thick red outline of a rectangular sheet with the bottom-right corner folded over. Inside the outline, there are two horizontal red lines centered vertically, suggesting lines of text.](.express-tl-50m-72138-1050-15/118d4f814e9d0baf5a4a40cd3e2b9d2db3827ce74a7916eb5592fae46ed2fe16.jpg) \*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. 4.3.9 SPI Bus (BIOS only)

Name	Pin #	Description	I/O	PU / PD	Comment
SPI_CS#	B97	Chip select for Carrier Board SPI BIOS Flash.	O 3.3VSB	PU 10K3.3VSB
SPI_MISO	A92	Data in to module from carrier board SPI BIOS flash.	I 3.3VSB
SPI_MOSI	A95	Data out from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_CLK	A94	Clock from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_POWER	A91	Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier	O P 3.3VSB
BIOS_DIS0#	A34	Selection strap to determine the BIOS boot device.	I	PU 10K3.3VSB	Carrier shall pull to GND or leave not- connected.
BIOS_DIS1#	B88	Selection strap to determine the BIOS boot device.	I	PU 10K3.3VSB	Carrier shall pull to GND or leave not- connected

4.3.10 Miscellaneous

Name	Pin #	Description	I/O	PU / PD	Comment
SPKR	B32	Output for audio enunciator, the "speaker" in PC-AT systems	O 3.3V
WDT	B27	Output indicating that a watchdog time-out event has occurred.	O 3.3V	PU 10K 3.3V
THRM#	B35	Input from off-module temp sensor indicating an over-temp situation.	I 3.3VSB
THRMTRIP#	A35	Active low output indicating that the CPU has entered thermal shutdown.	O 3.3VSB	PU 100K 3.3VSB
FAN_PWMOUT	B101	Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.	O OD 3.3V		There shall be PD on carrier board
FAN_TACHIN	B102	Fan tachometer input for a fan with a two-pulse output.	I OD 3.3V	PU 47K 3.3V
TPM_PP	A96	Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.	I 3.3V	PD 100K	PD only when TPM on module. Modules implementing a TPM shall pull down

4.3.11 SMBus

Name	Pin #	Description	I/O	PU / PD	Comment

SMB_CK	B13	System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 2.2K3.3VSB
SMB_DAT#	B14	System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 2.2K3.3VSB
SMB_ALERT#	B15	System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.	I 3.3VSB	PU 4.7K3.3VSB

4.3.12 I2 C Bus

Name	Pin #	Description	I/O	PU / PD	Comment

I2C_CK	B33	General purpose I2C port clock output/input	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)
I2C_DAT	B34	General purpose I2C port data I/O line	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)

4.3.13 General Purpose I/O (GPIO)

Name	Pin #	Description	I/O	PU / PD	Comment

GPO[0]	A93	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[1]	B54	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[2]	B57	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPO[3]	B63	General purpose output pins.	O 3.3V	PD 10K	After hardware RESET output low
GPI[0]	A54	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[1]	A63	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[2]	A67	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[3]	A85	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V

4.3.14 Serial Interface Signals

Name	Pin #	Description	I/O	PU / PD	Comment

SERO_TX	A98	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SERO_RX	A99	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V
SER1_TX	A101	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SER1_RX	A102	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V

4.3.15 Power and System Management

Name	Pin #	Description	I/O	PU / PD	Comment
PWRBTN#	B12	Power button to bring system out of S5 (soft off), active on falling edge.	I 3.3VSB	PU 10K 3.3VSB
SYS_RESET#	B49	Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.	I 3.3VSB	PU 10K 3.3VSB
CB_RESET#	B50	Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.	O 3.3V
PWR_OK	B24	Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.	I 3.3VSB	PU 10K 3.3VSB	Should have weak pull up.
SUS_STAT#	B18	Indicates imminent suspend operation; used to notify LPC devices.	O 3.3VSB
SUS_S3#	A15	Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.	O 3.3VSB	PD 100K
SUS_S4#	A18	Indicates system is in Suspend to Disk state. Active low output.	O 3.3VSB	PD 100K
SUS_S5#	A24	Indicates system is in Soft Off state.	O 3.3VSB	PD 100K
WAKE0#	B66	PCI Express wake up signal.	I 3.3VSB	PU 10K 3.3VSB
WAKE1#	B67	General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.	I 3.3VSB	PU 10K 3.3VSB	Connect to WAKE 0#
BATLOW#	A27	Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.	I 3.3VSB	PU 10K 3.3VSB
LID#	A103	LID button. Low active signal used by the ACPI operating system for a LID switch.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
SLEEP#	B103	Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
RAPID_SHUTDOWN	C67	Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source impedance for ≥20 μs.	I CMOS 5VSB		Not supported

4.3.16 Power and Ground

Name	Pin #	Description	I/O	PU / PD	Comment
VCC_12V	A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109	Primary power input supports a wide range of 5 to 20V input. All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
VCC_5V_SBY	B84, B85, B86, B87	Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.	P		5Vsb ±5%
VCC_RTC	A47	Real-time clock circuit-power input. Nominally +3.0V.	P
GND	A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110	Ground - DC power and signal and AC signal return path.	P

# 4.4. CD Connector Signal Descriptions 4.4.1 USB 3.0 Extensions

Name	Pin #	Description	I/O	PU / PD	Comment
USB_SSRX0-USB_SSRX0+	C3C4	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0	I PCIE		AC coupled off module
USB_SSTX0-USB_SSTX0+	D3D4	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0	O PCIE		AC coupled on module
USB_SSRX1-USB_SSRX1+	C6C7	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1	I PCIE		AC coupled off module
USB_SSTX1-USB_SSTX1+	D6D7	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1	O PCIE		AC coupled on module
USB_SSRX2-USB_SSRX2+	C9C10	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2	I PCIE		AC coupled off module
USB_SSTX2-USB_SSTX2+	D9D10	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2	O PCIE		AC coupled on module
USB_SSRX3-USB_SSRX3+	C12C13	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3	I PCIE		AC coupled off module
USB_SSTX3-USB_SSTX3+	D12D13	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3	O PCIE		AC coupled on module

# 4.4.1.1. USB Root Segmentation All USB interfaces are derived from the xHCI controller. 4.4.2 PCI Express

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX6+PCIE_TX6-	D19D20	PCI Express channel 6, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX6+PCIE_RX6-	C19C20	PCI Express channel 6, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX7+PCIE_TX7-	D22D23	PCI Express channel 7, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX7+PCIE_RX7-	C22C23	PCI Express channel 7, Receive Input differential pair.	I PCIE		AC coupled off Module

# 4.4.2.1. PCH HSIO Lane Assignments Refer to Section 4.3.6.1 PCH HSIO Lane Assignments on page 34. 4.4.3 DDI1 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI1_PAIR0+	D26	DP1_LANE0+	TMDS1_DATA2+
DDI1_PAIR0-	D27	DP1_LANE0-	TMDS1_DATA2-
DDI1_PAIR1+	D29	DP1_LANE1+	TMDS1_DATA1+
DDI1_PAIR1-	D30	DP1_LANE1-	TMDS1_DATA1-
DDI1_PAIR2+	D32	DP1_LANE2+	TMDS1_DATA0+
DDI1_PAIR2-	D33	DP1_LANE2-	TMDS1_DATA0-
DDI1_PAIR3+	D36	DP1_LANE3+	TMDS1_CLK+
DDI1_PAIR3-	D37	DP1_LANE3-	TMDS1_CLK-
DDI1_PAIR4+	C25	-	-
DDI1_PAIR4-	C26
DDI1_PAIR5+	C29	-	-
DDI1_PAIR5-	C30
DDI1_PAIR6+	C15	-	-
DDI1_PAIR6-	C16
DDI1_HPD	C24	DP1_HPD	HDMI1_HPD
DDI1_CTRLCLK_AUX+	D15	DP1_AUX+	HMDI1_CTRLCLK
DDI1_CTRLCLK_AUX-	D16	DP1_AUX-	HMDI1_CTRLDATA
DDI1_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL	DDI1_DDC_AUX_SEL

![The image displays a red icon on a white background. It depicts a stylized document or piece of paper with a folded bottom-right corner. Inside the document shape, there are three horizontal red lines stacked vertically, representing lines of text or a list.](.express-tl-50m-72138-1050-15/d262a8114ace6829e53217971e3c12652f21fea9a69efdf44d332b3f457b9ef2.jpg) Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.3.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP1_LANE0+	D26	DP Port 1, differential pair data lines	O PCIE		AC coupled off Module
DP1_LANE0-	D27				100 nF DC blocking capacitors shall be placed on the Carrier
DP1_LANE1+	D29
DP1_LANE1-	D30
DP1_LANE2+	D32
DP1_LANE2-	D33
DP1_LANE3+	D36
DP1_LANE3-	D37
DP1_HPD	C24	DP Port 1, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP1_AUX+	D15	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP1_AUX-	D16	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.3.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS1_DATA2+	D26	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS1_DATA2-	D27
TMDS1_DATA1+	D29
TMDS1_DATA1-	D30
TMDS1_DATA0+	D32
TMDS1_DATA0-	D33
TMDS1_CLK+	D36	HDMI Port, Differential Pair Clock Lines
TMDS1_CLK-	D37	HDMI Port, Differential Pair Clock Lines
HDMI_HPD	C24	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI1_CTRLCLK	D15	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI1_CTRLDATA	D16	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.4 DDI2 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI2_PAIR0+	D39	DP2_LANE0+	TMDS2_DATA2+
DDI2_PAIR0-	D40	DP2_LANE0-	TMDS2_DATA2-
DDI2_PAIR1+	D42	DP2_LANE1+	TMDS2_DATA1+
DDI2_PAIR1-	D43	DP2_LANE1-	TMDS2_DATA1-
DDI2_PAIR2+	D46	DP2_LANE2+	TMDS2_DATA0+
DDI2_PAIR2-	D47	DP2_LANE2-	TMDS2_DATA0-
DDI2_PAIR3+	D49	DP2_LANE3+	TMDS2_CLK+
DDI2_PAIR3-	D50	DP2_LANE3-	TMDS2_CLK-
DDI2_HPD	D44	DP2_HPD	HDMI2_HPD
DDI2_CTRLCLK_AUX+	C32	DP2_AUX+	HMDI2_CTRLCLK
DDI2_CTRLCLK_AUX-	C33	DP2_AUX-	HMDI2_CTRLDATA
DDI2_DDC_AUX_SEL	C34	DDI2_DDC_AUX_SEL	DDI2_DDC_AUX_SEL

![The image features a red icon on a white background. It is shaped like a square with a curled bottom-right corner, resembling a piece of paper, a document, or a chat bubble. Inside the red outline, there are two horizontal red lines centered vertically, resembling an equals sign or lines of text.](.express-tl-50m-72138-1050-15/291b1616d4e2168c05aaa2cbae6a3062bece1be166ad5f45b74538f96c5c5a1c.jpg) # Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.4.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP2_LANE0+	D39	DP Port 2, differential pair data lines	O PCIE		AC coupled off Module
DP2_LANE0-	D40				100 nF DC blocking capacitors shall be placed on the Carrier
DP2_LANE1+	D42
DP2_LANE1-	D43
DP2_LANE2+	D46
DP2_LANE2-	D47
DP2_LANE3+	D49
DP2_LANE3-	D50
DP2_HPD	D44	DP Port 2, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP2_AUX+	C32	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP2_AUX-	C33	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.4.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS2_DATA2+	D39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS2_DATA2-	D40
TMDS2_DATA1+	D42
TMDS2_DATA1-	D43
TMDS2_DATA0+	D46
TMDS2_DATA0-	D47
TMDS2_CLK+	D49	HDMI Port, Differential Pair Clock Lines
TMDS2_CLK-	D50	HDMI Port, Differential Pair Clock Lines
HDM2_HPD	D44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI2_CTRLCLK	C32	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI2_CTRLDATA	C33	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.5 DDI3 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI3_PAIR0+	C39	DP3_LANE0+	TMDS3_DATA2+
DDI3_PAIR0-	C40	DP3_LANE0-	TMDS3_DATA2-
DDI3_PAIR1+	C42	DP3_LANE1+	TMDS3_DATA1+
DDI3_PAIR1-	C43	DP3_LANE1-	TMDS3_DATA1-
DDI3_PAIR2+	C46	DP3_LANE2+	TMDS3_DATA0+
DDI3_PAIR2-	C47	DP3_LANE2-	TMDS3_DATA0-
DDI3_PAIR3+	C49	DP3_LANE3+	TMDS3_CLK+
DDI3_PAIR3-	C50	DP3_LANE3-	TMDS3_CLK-
DDI3_HPD	C44	DP3_HPD	HDMI3_HPD
DDI3_CTRLCLK_AUX+	C36	DP3_AUX+	HMDI3_CTRLCLK
DDI3_CTRLCLK_AUX-	C37	DP3_AUX-	HMDI3_CTRLDATA
DDI3_DDC_AUX_SEL	C38	DDI3_DDC_AUX_SEL	DDI3_DDC_AUX_SEL

![The image displays a red icon resembling a piece of paper or a document. It features a folded top-right corner and contains two horizontal lines in the center, representing text.](.express-tl-50m-72138-1050-15/d8f48ffb2b4316a0c13248005b25101b277e4adec3e6f82b53c56d359209eb05.jpg) # Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function. 4.4.5.1. DisplayPort (DP) Mode

Name	Pin #	Description	I/O	PU / PD	Comment

DP3_LANE0+	C39	DP Port 3, differential pair data lines	O PCIE		AC coupled off Module
DP3_LANE0-	C40				100 nF DC blocking capacitors shall be placed on the Carrier
DP3_LANE1+	C42
DP3_LANE1-	C43
DP3_LANE2+	C46
DP3_LANE2-	C47
DP3_LANE3+	C49
DP3_LANE3-	C50
DP3_HPD	C44	DP Port 3, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP3_AUX+	C36	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP3_AUX-	C37	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K	AC coupled on Module
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.5.2. HDMI Mode

Name	Pin #	Description	I/O	PU / PD	Comment
TMDS3_DATA2+	C39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS3_DATA2-	C40
TMDS3_DATA1+	C42
TMDS3_DATA1-	C43
TMDS3_DATA0+	C46
TMDS3_DATA0-	C47
TMDS3_CLK+	C49	HDMI Port, Differential Pair Clock Lines
TMDS3_CLK-	C50	HDMI Port, Differential Pair Clock Lines
HDM3_HPD	C44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI3_CTRLCLK	C36	I2C_CLK Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
HDMI3_CTRLDATA	C37	I2C_DAT Line for HDMI	I/O PCIE	PU 2.2K	AC couple on Module
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.6 PCIe Graphics Port (PEG)

Name	Pin #	Description	I/O	PU / PD	Comment
PEG_TX0+PEG_TX0-	D52D53	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX0+PEG_RX0-	C52C53	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX1+PEG_TX1-	D55D56	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX1+PEG_RX1-	C55C56	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX2+PEG_TX2-	D58D59	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX2+PEG_RX2-	C58C59	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX3+PEG_TX3-	D61D62	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX3+PEG_RX3-	C61C62	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX4+PEG_TX4-	D65D66	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX4+PEG_RX4-	C65C66	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX5+PEG_TX5-	D68D69	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX5+PEG_RX5-	C68C69	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX6+PEG_TX6-	D71D72	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX6+PEG_RX6-	C71C72	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX7+PEG_TX7-	D74D75	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX7+PEG_RX7-	C74C75	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX8+PEG_TX8-	D78D79	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX8+PEG_RX8-	C78C79	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX9+PEG_TX9-	D81D82	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX9+PEG_RX9-	C81C82	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX10+PEG_TX10-	D85D86	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX10+PEG_RX10-	C85C86	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX11+PEG_TX11-	D88D89	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX11+PEG_RX11-	C88C89	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX12+PEG_TX12-	D91D92	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX12+PEG_RX12-	C91C92	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX13+PEG_TX13-	D94D95	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX13+PEG_RX13-	C94C95	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX14+PEG_TX14-	D98D99	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX14+PEG_RX14-	C98C99	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX15+PEG_TX15-	D101D102	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX15+PEG_RX15-	C101C102	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_LANE_RV#	D54	PCI Express Graphics lane reversal input strap. Pull low on the Carrier Board to reverse lane order.	I 3.3V

4.4.7 Module Type Definition

Name	Pin #	Description	I/O	PU / PD	Comment

TYPE0#	C54	The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC).			Type 6
TYPE1#	C57
TYPE2#	D57
		For Pin-out Type 1 and Type 10 that lack a CD connector, these pins are not present (X)
		TYPE2# TYPE1# TYPE0#
		X X X Pinout Type 1
		X X X Pinout Type 10
		NC NC NC Pinout Type 2
		NC NC GND Pinout Type 3
		NC GND NC Pinout Type 4
		NC GND GND Pinout Type 5
		GND NC NC Pinout Type 6
		GND NC GND Pinout Type 7
		The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g. deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.
TYPE10#	A97	In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.			No PD

4.4.8 Power and Ground

Name	Pin #	Description	I/O	PU / PD	Comment

VCC_12V	C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109	Primary power input supports a wide range of 5 to 20V input. All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
GND	C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110	Ground - DC power and signal and AC signal return path.	P

# 5. Additional Features This chapter describes connectors, LEDs, switches and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as below: ![5.1. Module Feature Locations\nStatus LEDs\nBIOS Default Reset Button\nBIOS Boot Select\nFan 12V](.express-tl-50m-72138-1050-15/c33ac27fa56022f802e96a08a8898ecb3816f9e8b2064d6722675f500d25478e.jpg) Figure 3 – Module feature locations (top side) ![30-pin Debug Connector\nPCI Express Configuration\nSwitch](.express-tl-50m-72138-1050-15/6e1d907f39362d9958b34f5588699e1fe6bef867075079299e61ef7b2301931e.jpg) Figure 4 – Module feature locations (bottom side) # 5.2. Debug Connector This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: • Test points measurement of internal power rails • SPI BIOS programming interface Embedded Controller programming interface 30-pin Debug Connector located on bottom side ![Close-up of a green printed circuit board with multiple microchips and connectors (no readable text or symbols)](.express-tl-50m-72138-1050-15/0a0f98b8aaf998e0687879a2f42c1433df1071cff3ba968423fec6a8b4616b34.jpg) ![Electronic circuit board with gold contacts and a coiled cable, no visible text or symbols](.express-tl-50m-72138-1050-15/d358daa3aaa0d789495c8f0be59cc31420e099ed672318b77a383fe7ec219d59.jpg) Figure 5 – Express-TL and Debug Module # 5.3. Status LEDs Status LEDs are mounted on the module to facilitate easier maintenance. LED3 LED2 LED1 ![Close-up of a green printed circuit board with various electronic components and a gold circular component (no visible text or symbols)](.express-tl-50m-72138-1050-15/554abceaa909c8ed0bc5177cfbc54bce0917e0a969ac34c88501a5534c6f783f.jpg)

Name	Color	Connection	Function
LED1	Blue	BMC output	Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes below)
LED2	Green	Power Source 3Vcc	S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3	Red	BMC output and same signal as WDT (B27) on BtB connector	Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)

# 5.4. Exception Codes

Exception Code	Error Message
0	NOERROR
3	NO_SLP_S5
4	NO_SLP_S4
5	NO_SLP_S3
6	BIOS_FAIL
7	RESET_FAIL
9	NO_CB_PWROK
10	CRITICAL_TEMP
11	POWER_FAIL
12	VOLTAGE_FAIL
13	RSMRST_FAIL
14	NO_VDDQ_PG
16	NO_VCORE_PG
17	NO_SYS_GD
19	NO_V3P3A
21	NO_PWRSRC_GD

# 5.5. Fan Connector Connector type: JVE 24W1125A-04M00 ![Close-up of a green printed circuit board with visible components and a red arrow pointing to component 4 (no text or symbols on the board itself)](.express-tl-50m-72138-1050-15/a529fab66cdcab81ddabf0a4d750083b4ff0192ee462fae4d1273e04f0e168ce.jpg)

Name	Description

1	FAN_PWMOUT
2	FAN_TACHIN
3	GND
4	12V

# 5.6. BIOS Default Reset Button ![This image displays a close-up section of a green printed circuit board (PCB). A red arrow points horizontally from the left side towards a white, rectangular connector socket mounted on the edge of the board. Above the arrow, several small surface-mount components are visible. Below the arrow, there is a large circular via pad and a smaller yellow component. A portion of a larger black integrated circuit is visible in the upper right corner.](.express-tl-50m-72138-1050-15/7b563fe022fc7263026dd336b008c4681dbc7dddf5c320a0e036b3af540561f4.jpg) To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Keep the BIOS Setup Defaults Reset Button pressed and boot up the system. You can release the button when the BIOS prompt screen appears 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.express-tl-50m-72138-1050-15/d97b8ec1b686e8ed41b1be9aa47c49439dd73cf747dc8cb72bc5bdc7057ee446.jpg) # 5.7. PCI Express Configuration Switch The PCI Express Configuration Switch allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4. ![Close-up of a green circuit board with black components and gold connectors (no readable text or symbols)](.express-tl-50m-72138-1050-15/a3cc5c1a59b5247b4d78788b66c56661d52640112e4f974c71d5bcdf8b360a8b.jpg)

Mode	Pin 1	Pin 2
1 PCIe x16 (default)	Off	Off
2 PCIe x8	Off	On
1 PCIe x8 + 2 PCIe x4	On	On
Reserved	On	Off

# 5.8. BIOS Boot Select The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

Mode	Pin 1	Pin 2
Boot from SPI0 (default)	On	-
Boot from SPI1	Off	-
Set BIOS to PICMG mode (default)	-	On
Set BIOS to Failsafe BIOS mode	-	Off

# 6. BIOS Setup # 6.1. Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

Main	Advanced	Chipset	Security	Boot	Save & Exit
BIOS InformationSystem InformationBoard InformationSystem Date and TimeAccess Level	CPU ConfigurationPower & PerformanceTCSS Platform SettingsIntel(R) Time Coordinated Computing Graphics ConfigurationPower ManagementSystem ManagementThermal ManagementWatchdog TimerSuper IO ConfigurationMiscellaneousAMT ConfigurationUSB ConfigurationAMI Graphic Output Protocol PolicySerial Port Console RedirectionNetwork Stack ConfigurationNVMe ConfigurationTrusted Computing	System Agent (SA)ConfigurationPCH-IO Configuration	Setup AdministratorPasswordUser PasswordSecure Boot	Boot ConfigurationFIXED BOOT ORDER PrioritiesUEFI USB Key Drive BBS Priorities	Save Change and ExitDiscard Changes and ExitSave Changes and ResetDiscard Changes and ResetSave OptionsBoot Override

# 6.2. Main 6.2.1 Main > BIOS Information

Feature	Options	Description
BIOS Vendor	Info only	American Megatrends
BIOS Version	Info only	ADLINK BIOS Version
Build Date	Info only	ADLINK BIOS Build Date
MRC Version	Info only	Display MRC Version
GOP Version	Info only	Display GOP Version
ME FW Version	Info only	Display ME FW Version
BIOS Boot Source	Info only	Display BIOS Boot Source

6.2.2 Main > System Information

Feature	Options	Description
Project Name	Info only	Display Project Name
CPU Board version	Info only	Display CPU Board Version
CPU Board String	Info only	Display CPU Board String
CPU Frequency	Info only	Display CPU Frequency
Total Memory	Info only	Display Installed Memory Size
Memory Frequency	Info only	Display Memory Frequency
PCH SKU	Info only	Display PCH SKU Version

6.2.3 Main > Board Information

Feature	Options	Description
Board Information	Info only
Serial Number	Info only	Display SEMA Serial Number.
Manufacturing Date	Info only	Display SEMA Manufacturing Date.
Last Repair Date	Info only	Display SEMA Last Repair Date.
MAC ID	Info only	Display SEMA MAC ID.
Runtime Statistics	Info only
Total Runtime	Info only	The returned value specifies the total time in minutes the system is running in S0 state.
Current Runtime	Info only	The returned value specifies the time in seconds the system is running in S0 state. This counter is cleared when the system is removed from the external power supply.
Power Cycles	Info only	The returned value specifies the number of times the external power supply has been shut down
Boot Cycles	Info only	The Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
Boot Reason	Info only	The boot reason is the event which causes the reboot of the system.

6.2.4 Main > System Date/Time

Feature	Options	Description
System Date	Info only
System Time	Info only

6.2.5 Main > Access Level

Feature	Options	Description
Access Level	Info only

# 6.3. Advanced This menu contains the settings for most of the user interfaces in the system. 6.3.1 Advanced > CPU Configuration

Feature	Options	Description
CPU Configuration	Info only
Type	Info only	Socket Specific CPU Information.
Speed	Info only	Display Max CPU speed.
ID	Info only	Display Microcode Patch.
Stepping	Info only	Display Min CPU stepping.
Number of Processors	Info only	Display CPU number of cores
GT Info	Info only	Display GT information
eDRAM Size	Infor only	Display eDRAM size if support
L1 Data Cache	Info only	Display cache info.
L1 Instruction Cache	Info only	Display cache info.
L2 Cache	Info only	Display cache info.
L3 Cache	Info only	Display cache info.
L4 Cache	Info only	Display cache info.
VMX	Info only	Display VMX support info.
SMX/TXT	Info only	Display SMX/TXT support info.
Intel Virtualization Technology	Disabled Enabled	When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.
Active Processor Cores	ALL123	Number of cores to enable in each processor package.
Hyper-Threading	DisabledEnabled	Enable or Disable Hyper-Threading Technology.

# 6.3.2 Advanced > Power & Performance

Feature	Options	Description
CPU – Power Management Control	Submenu	CPU- Power Management Control Options
GT – Power Management Control	Submenu	GT- Power Management Control

# 6.3.2.1. Advanced > Power & Performance > CPU – Power Management

Feature	Options	Description
CPU – Power Management Control	Info only
Boot performance mode	Max BatteryMax Non-TurboPerformanceTurbo Performance	Select the performance state that the BIOS will set starting from reset vector.
Intel(R) SpeedStep(tm)	DisabledEnabled	Allows more than two frequency ranges to be supported.
Race To Halt (RTH)	DisabledEnabled	Enable/Disable Race to Halt features. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
Intel(R) Speed Shift Technology	DisabledEnabled	Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.
Per Core P State OS control mode	DisabledEnabled	Enable/Disable Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.
HwP Autonomous Per Core P State	DisabledEnabled	Disable Autonomous PCPS (Bit 30 = 1, command 0x11) Autonomous will request the same value for all cores all the time. Enable PCPS (default Bit 30 = 0, command 0x11)
HwP Autonomous EPP Grouping	DisabledEnabled	Enable EPP grouping (default Bit 29 =0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (Bit 29 =1 , command 0x11) autonomous will not necessarily request same values for all cores with same EPP.
EPB override over PECI	DisabledEnabled	Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b , subcommand 0x3 to 1. This will allow OOB EPB PECI override control
HwP Fast MSR Support	DisabledEnabled	Enable/Disable HwP Fast MSR Support for IA32_HWP_REQUEST MSR.
HDC Control	DisabledEnabled	This option allows HDC configuration.\n Disabled: Disable HDC\n Enabled: Can be enabled by OS if OS native support is available.
View/Configure Turbo Options	Submenu	View/Configure Turbo Options
Config TDP Configurations	Submenu	Config TDP Configurations
CPU VR Settings	Submenu	CPU VR Settings
Platform PL1 Enable	DisabledEnabled	Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.
Platform PL2 Enable	DisabledEnabled
Power Limit 4 override	DisabledEnabled	Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.
C states	DisabledEnabled	Enable/Disable CPU Power Management. It allows CPU to go to C states when it's not 100% utilized.
Thermal Monitor	DisabledEnabled	Enable/Disable Thermal Monitor
Interrupt Redirection Mode Selection		Interrupt Redirection Mode Select for Logical Interrupts
Timed MWAIT	DisabledEnabled	Enable/Disable Timed MWAIT Support
Custom P-State Table	Submenu	Add Custom P-state Table
EC Turbo Control Mode		Enable/Disable EC Turbo Control Mode
Energy Performance Gain		Enable/Disable Energy Performance Gain.
EPG DIMM ldd3N	Info only
EPG DIMM ldd3P	Info only
Power Limit 3 Settings	Submenu	Power Limit 3 Settings
CPU Lock Configuration	Submenu	CPU Lock Configuration

6.3.2.2. Advanced > Power & Performance > CPU – Power Management Control > View/Configure Turbo Options

Feature	Options	Description
Current Turbo Settings	Info only
Max Turbo Power Limit	Info only
Min Turbo Power Limit	Info only
Package TDP Limit	Info only
Power Limit 1	Info only
Power Limit 2	Info only
1-core Turbo Ratio Limit Ratio	Info only
2-core Turbo Ratio Limit Ratio	Info only
3-core Turbo Ratio Limit Ratio	Info only
4-core Turbo Ratio Limit Ratio	Info only
Energy Efficient P-state	DisabledEnabled	Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1, it will enable access to ENERGY_PERFORMANCE_BIAS MSR.
Package Power Limit MSR Lock	DisabledEnabled	Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.
1-Core Ratio Limit Override	44	1-Core Ratio Limit ranges from 0 to 83. The Minimum range may vary between Processors. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
2-Core Ratio Limit Override	42	2-Core Ratio Limit ranges from 0 to 83. The Minimum range may vary between Processors. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
3-Core Ratio Limit Override	41	3-Core Ratio Limit ranges from 0 to 83. The Minimum range may vary between Processors. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
4-Core Ratio Limit Override	40	4-Core Ratio Limit ranges from 0 to 83. The Minimum range may vary between Processors. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
Energy Efficient Turbo	DisabledEnabled	Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.

6.3.2.2.1. Advanced > Power & Performance > CPU – Power Management Control > Config TDP Configurations

Feature	Options	Description
Config TDP Configurations	Info only
Enable Configurable TDP	Applies to non-cTDPApplies to cTDP	Applies TDP initialization settings based on non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and BIOS will bypass cTDP initialization flow.
Configurable TDP Boot Mode	NormalDownDeactivate	Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.
Configurable TDP Lock	EnabledDisabled	Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL.Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.
CTDP BIOS control	EnabledDisabled	Enables CTDP control via runtime ACPI BIOS methods. This "BIOS only" feature does not require EC or driver support.
ConfigTDP Levels	Info only
ConfigTDP Turbo Activation Ratio	Info only
Power Limit1	Info only
Power Limit2	Info only
Custom Settings NominalConfigTDP Nominal	Info only
Power Limit1	0	Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: The value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP Limit. If value is 0, BIOS will program TDP value.
Power Limit2	0	Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. If the value is 0, BIOS will program this value as 1.25*TDP. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.
Power Limit 1 Time Window	0	Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.
ConfigTDP Turbo Activation Ratio	0	Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.
Custom Settings DownConfigTDP Level1	Info only
Power Limit1	0	Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: The value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TPD Limit. If value is 0, BIOS will program TDP value.
Power Limit2	0	Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. If the value is 0, BIOSwill program this value as 1.25*TDP. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.
Power Limit 1 Time Window	0	Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.
ConfigTDP Turbo Activation Ratio	0	Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.

6.3.2.2.2. Advanced > Power & Performance > CPU – Power Management Control > CPU VR Settings

Feature	Options	Description
CPU VR Settings	Info only
PSYS Slope	0	PSYS Slope defined in 1/100 increments. The range is from 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9."
PSYS Offset	0	PSYS Offset defined in 1/1000 increments. The range is from 0-63999. For an offset of 25.348, enter 25348. PSYS Uses BIOS VR mailbox command 0x4.
PSYS Prefix	+ -	Sets the offset value as positive or negative.
PSYS PMax Power	0	PSYS PMax power, defined in 1/8 watt increments. The range is from 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.
Acoustic Noise Settings	Submenu	Configure Acoustic Noise Settings for IA, GT and SA domains
VccIn VR Settings	Submenu	VccIn VR Settings
RFI Settings	Submenu	RFI Settings

6.3.2.2.3. Advanced > Power & Performance > CPU – Power Management Control > Custom P-state Table

Feature	Options	Description
Custom P-state Table	Info only
Number of P states	0	Sets the number of custom P-states. At least 2 states must be present.

6.3.2.2.4. Advanced > Power & Performance > CPU – Power Management Control >Power Limit 3 Setting

Feature	Options	Description
CFG Lock	DisabledEnabled	Configure MSR 0xE2[15], CFG Lock bit
Overclocking Lock	DisabledEnabled	Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR

6.3.2.2.5. Advanced > Power & Performance > CPU – Power Management Control >CPU Lock Configuration

Feature	Options	Description
CFG Lock	DisabledEnabled	Configure MSR 0xE2[15], CFG Lock bit
Overclocking Lock	DisabledEnabled	Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR

6.3.2.3. Advanced > Power & Performance > GT – Power Management Control

Feature	Options	Description
GT – Power Management Control	Info only
RC6(Render Standby)	DisabledEnabled
Maximum GT frequency	Default Max Frequency100Mhz150Mhz200Mhz250Mhz300Mhz350Mhz400Mhz450Mhz500Mhz550Mhz600Mhz650Mhz700Mhz750Mhz800Mhz850Mhz900Mhz950Mhz1000Mhz1050Mhz1100Mhz1150Mhz1200Mhz	Maximum GT frequency limited by the user. Choose between 400MHz (RPN) and 400MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU
Disable Turbo GT frequency	EnabledDisabled	Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited

6.3.3 Advanced > TCC Platform Setting

Feature	Options	Description
TCC Platform Setting	Info only
Control IOMMU Pre-Boot Behavior	Disable IOMMUEnable IOMMU during boot	Enable IOMMU in Pre-boot environment (If DMAR table is installed in DXE and If VTD_INFO_PPI is installed in PEI.)

6.3.4 Advanced > Intel(R) Time Coordinated Computing

Feature	Options	Description
Intel(R) Time Coordinated Computing (Intel(R) TCC)	Info only
#AC Split Lock	EnabledDisabled	Enable or Disable Alignment Check Exception (#AC). When enabled, this will assert an #AC when any atomic operation has an operand that crosses two cache lines.
Intel(R) TCC Mode	EnabledDisabled	Enable or Disable Intel(R) TCC Mode. When enabled, this will modify system settings to improve real-time performance. The full list of settings and their current state are displayed below when Intel(R) TCC mode is enabled.
Intel(R) TCC Mode Affected Settings	Info only
IO Fabric Low Latency	EnabledDisabled	Enable or Disable IO Fabric Low Latency. This will turn off some power management in the PCH IO fabrics. This option provides the most aggressive IO Fabric performance setting. S3 state is NOT supported.
GT CLOS	EnabledDisabled	Enable or Disable Graphics Technology (GT) Class of Service. Enable will reduce Gfx LLC allocation to minimize impact of Gfx workload on LLC.
OPIO Recentering	EnabledDisabled	Enable or Disable Opio Recentering to improve Pcie latency.
C states	EnabledDisabled	Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.
Intel(R) Speed Shift Technology	EnabledDisabled	Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow forhardware-controlled P-states.
Intel(R) SpeedStep(tm)	EnabledDisabled	Allows more than two frequency ranges to be supported.
Hyper-Threading	EnabledDisabled	Enable or Disable Hyper-Threading Technology.
ACPI D3Cold Support	EnabledDisabled	Enable/Disable ACPI D3Cold support to be executed on D3 entry and exit
Low Power S0 Idle Capability	EnabledDisabled	This variable determines if we enable ACPI Lower Power S0 Idle Capability (Mutually exclusive with Smart connect). While this is enabled, it also disables 8254 timer for SLP_S0 support.
SA GV	EnabledDisabled	System Agent Geyserville. Can disable, fix to a specific point, or enable frequency switching.
WRC Feature	EnabledDisabled	Enable/Disable SA WRC (Write Cache) Feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.
Page Close Idle Timeout	EnabledDisabled	Page Close Idle Timeout Control
Power Down Mode	AutoNo Power DownAPDPPD-DLLoff	CKE Power Down Mode Control
RC6(Render Standby)	EnabledDisabled	Check to enable render standby support.
DMI Link ASPM Control	EnabledDisabled	The control of Active State Power Management of the DMI Link.
PCI Express Clock Gating	EnabledDisabled	PCI Express Clock Gating Enable/Disable for each root port.
Legacy IO Low Latency	EnabledDisabled	Set to enable low latency of legacy IO. Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.

6.3.5 Advanced > Graphics Configuration

Feature	Options	Description
NXP Configuration	Info Only
Data format and Color Depth	VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp	Data format and Color Depth select
LVDS Output Mode	Dual LVDS busSingle LVDS bus	Single/Dual mode select
DE Polarity	Active HighActive Low	DE Polarity select
Vsync Polarity	Active HighActive Low	Vsync Polarity select
Hsync Polarity	Active HighActive Low	Hsync Polarity select
Spreading Depth	No Spreading0.5%1.0%1.5%2.0%2.5%	Clock frequency center spreading depth.
Integrated Display Configuration	Info only
eDP/LVDS	DisabledEnabled	Enable/Disable eDP/LVDS
DDI Port 1	No DeviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatibility	DDI port 1 function choose to Display Port or HDMI
DDI Port 2	No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatibility	DDI port 2 function choose to Display Port or HDMI
DDI Port 3	No DeviceDisplay PortHDMIDisplayPort With HDMI/DVI Compatibility	DDI port 3 function choose to Display Port or HDMI

6.3.6 Advanced > Power Management

Feature	Options	Description
Power Management	Info Only
Enable ACPI Auto Configuration	DisabledEnabled	Enables or Disables BIOS ACPI Auto Configuration
Enable Hibernation	DisabledEnabled
ACPI Sleep State	Suspend DisabledS3 (Suspend to RAM)
LID Function	DisabledEnabled
Sleep Function	DisabledEnabled
ECO Mode	DisabledEnabled
Power-Up Mode	Turn OnRemain OffLast State
ATTENTION: The Power-Up Mode only has effect, if the module is in ATX-Mode	Info Only
Power Consumption	Submenu

6.3.6.1. Advanced > Power Management > Power Consumption

Feature	Options	Description
Power Consumption	Info only
Main Current	Info only	Display Main Current information
Current Input Power	Info only	Display Current Input Power information
RTC	Info only	Display RTC information
5VSB	Info only	Display 5VSB information
VIN	Info only	Display VIN information
3.3V	Info only	Display 3.3V information
VMEM	Info only	Display VMEM information
3.3VSB	Info only	Display 3.3VSB information
VCORE	Info only	Display VCORE information

6.3.7 Advanced > System Management

Feature	Options	Description
System Management	Info Only
Version	Info Only	Display SEMA Module Version
SEMA Firmware	Info Only	Display SEMA Firmware Version
SEMA Flags	Submenu	Display SEMA Flags
SEMA Features	Info	Display SEMA Supported Features

6.3.7.1. Advanced > System Management > SEMA Flags

Feature	Options	Description
SEMA Flags	Info Only
SEMA Flags	Info Only	Display SEMA Flags
BIOS Select	Info Only	Display BIOS Select type
ATX/AT-Mode	Info Only	Display ATX or AT mode

6.3.8 Advanced > Thermal Management

Feature	Options	Description
Thermal Management	Info Only
Critical Trip Point	Disabled80 C90 C95 C	The value is the temperature threshold of the Critical Trip Point.
Passive Cooling Trip Point	Disabled70 C80 C90 C	The value is the temperature threshold of the Passive Cooling Trip Point.
Active Cooling Trip Point	40 C50 C60 C70 CRefer to BMC	This value is the temperature threshold of the active cooling trip point.
Watchdog ACPI Event Shutdown	DisabledEnabled	Watchdog ACPI Event Shutdown Enabled/Disabled
Temperature and Fan Speed	Submenu

6.3.8.1. Advanced > Thermal Management > Thermal and Fan Speed

Feature	Options	Description
Temperatures and Fan Speed	Info Only
CPU Temperature	Info Only
Current	Info Only	Display Current CPU Temperature
Startup	Info Only	Display Startup Board Temperature
Min	Info Only	Display Min Board Temperature
Max	Info Only	Display Max Board Temperature
Board Temperatures	Info Only
Current	Info Only	Display Current CPU Temperature
Startup	Info Only	Display Startup Board Temperature
Min	Info Only	Display Min Board Temperature
Max	Info Only	Display Max Board Temperature
CPU Fan Speed	Info Only	Display CPU Fan Speed
Smart Fan	Submenu

6.3.8.1.1. Advanced > Thermal Management > Thermal and Fan Speed > Smart Fan

Feature	Options	Description
Smart Fan	Info Only
CPU Smart FanTemperature Source	CPU Sensor Board Sensor	CPU Smart FanTemperature Source
CPU Fan Mode	Auto Off On Soft	CPU Fan Mode
Trigger Point1	Info Only
Trigger Temperature	45	Trigger Temperature
PWM Level	25	PWM Level
Trigger Point2	Info Only
Trigger Temperature	60	Trigger Temperature
PWM Level	50	PWM Level
Trigger Point3	Info Only
Trigger Temperature	75	Trigger Temperature
PWM Level	75	PWM Level
Trigger Point4	Info Only
Trigger Temperature	90	Trigger Temperature
PWM Level	100	PWM Level

6.3.9 Advanced > Watchdog Timer

Feature	Options	Description
Watchdog Timer	Info only
Power-Up Watchdog	Disabled Enabled	The Power Up Watchdog resets the system after a certain amount of time after power up. Pressing F12 during start-up disables the Power Up Watchdog.
Timeout	65535	Here you can enter the time the Power Up Watchdog should wait until it resets the system. The value range starts by 24 and ends by 65535
RunTime Watchdog	Disabled Enabled	The RunTime Watchdog resets the system after a certain period following a power up.
Timeout	24	Here you can enter the time the Runtime Watchdog should wait until it resets the system. The value range starts from 30 and ends at 65535.

6.3.10 Advanced > Super IO Configuration

Feature	Options	Description
Super IO Configuration	Info only
IT5121E Super IO Configuration	Submenu	System Super IO Chip Parameters.
W83627DHGSEC Super IO Configuration	Submenu	System Super IO Chip Parameters.

6.3.10.1.Advanced > Super IO Configuration > IT5121E Super IO Configuration

Feature	Options	Description
IT5121E Super IO Configuration	Info only
Serial Port 1/2 Configuration	Submenu	Set Parameters of Serial Port 1/2
Serial Port 1/2 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=3F8h/2F8h; IRQ=4;IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.
Change Settings	NormalHigh Speed	Select an optimal setting for Super IO Device

6.3.10.2.Advanced > Super IO Configuration > W83627DHGSEC Super IO Configuration

Feature	Options	Description
Serial Port 1/2 Configuration	Submenu	Set Parameters of Serial Port 2 (COMB).
Serial Port 1/2 Configuration	Info only
Serial Port	DisabledEnabled	Enable or Disable Serial Port (COM).
Device Settings	Info Only	Display IO / IRQ information of COM Port.
Change Settings	AutoIO=248h; IRQ=11;IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12	Select an optimal setting for Super IO Device.

6.3.11 Advanced > Miscellaneous

Feature	Options	Description
Miscellaneous	Info Only
Power Supply Unit	Emulate AT ModeATX Mode	Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions (S3 & S4) to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. ATX: OS will turn off system power when shutdown.
I2C Speed Control	100 kbps400 kbps	I2C Speed Control
WOL From S5	OFFON	This Config to control power on/off LAN in S5 State by SEMA(EC)
Smart Battery Function	DisabledEnabledAuto	Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.
SMBUS Select	From PCHFrom EC	Select SMBUS Routine

6.3.12 Advanced > AMT Configuration

Feature	Options	Description
MEBx hotkey Pressed	DisabledEnabled

6.3.13 Advanced > USB Configuration

Feature	Options	Description
USB Configuration	Info Only
USB Module Version	Info Only	Display USB Module Version
USB Controllers:	Info Only	Display USB Controllers is XHCI or EHCI.
USB Devices:	Info Only	Display attachment USB devices.
Legacy USB Support	EnabledDisabledAuto	Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.
XHCI Hand-off	EnabledDisabled	This is a workaround for OSs without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.
USB Mass Storage Driver Support	DisabledEnabled	Enable / Disable USB Mass Storge Driver Support.
USB hardware delays and time-outs:	Info Only
USB transfer rime-out	1 sec5sec10sec20 sec	The time-out value for Control, Bulk, and Interrupt transfers.
Device reset time-out	10 sec20 sec30 sec40 sec	USB mass storage device Start Unit command time-out.
Device power-up delay	AutoManual	Maximum time the device will take before it properly reports itself to the Hot Controller.'Auto' uses default value: for a Root po\rt it is 100ms, for a Hub port the delay is taken form Hub descriptor.

# 6.3.14 Advanced > AMI Graphic Output Protocol Policy

Feature	Options		Description
Intel (R) Graphics Controller	Info Only
Intel (R) GOP Driver	Info Only
Output Select	[ACTIVE Current]	Output Interface

# 6.3.15 Advanced > Serial Port Console Redirection

Feature	Options	Description
COM 0/1/2/3	Info only
Console Redirection	EnabledDisabled	Console Redirection Enable or Disable.
Console Redirection Settings	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.

6.3.15.1.Advanced > Serial Console Redirection > Console Redirection Settings (if COM 0/1/2/3 enabled)

Feature	Options	Description
COM1	Info only
Console Redirection Settings	Info only
Teriminal Type	VT100VT100+VT-UTF8ANSI	Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors.Even: The parity bit is 0 if thenumof 1's in the data bits is even.Odd: The parity bit is 0 ifnumof 1's in the data bits is odd.Mark: The parity bit is always 1.Space: The parity bit is always 0. Mark and Space parity bits do not allow for error detection. They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key Support	EnabledDisabled	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnabled	With this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31	EnabledDisabled	On Legacy OS, the Number of Rows and Columns supported redirection
Legacy OS Redirection Resolution	80x2480x25	On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad	VT100Intel LinuxXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

6.3.16 Advanced > Network Stack Configuration

Feature	Options	Description
Network Stack	DisableEnable	Enables/Disables UEFI Network Stack.
IPv4 PXE Support	DisableEnable	Enables/Disables IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.
IPv4 HTTP Support	DisableEnable	Enables/Disables IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.
IPv6 PXE Support	DisableEnable	Enables/Disables IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.
IPv6 HTTP Support	DisableEnable	Enables/Disables IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.
PXE boot wait time	0	Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.
Media detect count	1	Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.

# 6.3.17 Advanced > NVMe Configuration

Feature	Options	Description
NVMe Controller and Drive information	Info Only
Display NVMe device information	Info Only

# 6.3.18 Advanced > Trusted Computing

Feature	Options	Description
TPM20 Device Found	Info Only
Security Device Support	DisableEnable	Enables or Disables BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.

# 6.4. Chipset 6.4.1 Chipset > System Agent (SA) Configuration

Feature	Options	Description
Memory Configuration	Submenu	Memory Configuration Parameters
Graphics Configuration	Submenu	Graphics Configuration
PEG Port Feature Configuration	Submenu
VMD setup menu	Submenu
PCI Express Configuration	Submenu
Stop Grant Configuration	AutoManual	Automatic/Manual stop grant configuration
VT-d	DisabledEnabled	VT-d capability
X2APIC Opt Out	DisabledEnabled	Enable/Disable X2APIC_OPT_OUT
DMA Control Guarantee	DisabledEnabled	Enable/Disable DMA_CONTROL_GRARANTEE bit
Above 4GB MMIO BIOS assignment	DisabledEnabled	Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB.

6.4.1.1. Chipset > System Agent (SA) Configuration > Memory Configuration

Feature	Options	Description
Memory Configuration	Info Only
Memory RC Version	Info Only
Memory Speed	Info Only
Memory Timings (tCL-tRCD-tRP-tRAS)	Info Only
Controller 0 Channel 0 Slot 0	Info Only
Controller 0 Channel 0 Slot 1	Info Only
Controller 1 Channel 0 Slot 0	Info Only
Controller 0 Channel 0 Slot 1	Info Only
Memory Test on Warm Boot	DisabledEnabled
Maximum Memory Frequency	Auto10671200133314671733186721332267253326672933306716002000240028003200
Max TOLUD	Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB	Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller
Controller 0,Channel 0 DIMM Control	Enable both DIMMsDisable DIMM0Disable DIMM1Disable both DIMMs	Controller 0, Channel 0 DIMM Control Support - Enable or Disable Dimms on Controller 0, Channel 0.
Controller 1,Channel 0 DIMM Control	Enable both DIMMsDisable DIMM0Disable DIMM1Disable both DIMMs	Controller 1, Channel 0 DIMM Control Support - Enable or Disable Dimms on Controller 1, Channel 0.
In-Band ECC Support	DisabledEnabled	Enable/Disable In-Band ECC. Either the IBECC or the TME can be enabled.

6.4.1.2. Chipset > System Agent (SA) Configuration > Graphics Configuration

Feature	Options	Description
Graphics Configuration	Info Only
Primary Display	AutoIGFXPEGPCIe	Select which of IGFX/PEG/PCIe Graphics device should be Primary Display Or select HG for Hybrid Gfx.
Select PCIE Card	AutoElk Creek 4PEG Eval	Select the card used on the platformAuto : Skip GPIO based Power Enable to dGPUElk Creek 4: DGPU Power Enable = ActiveLowPEG Eval : DGPU Power Enable = ActiveHigh
Internal Graphics	AutoDisabledEnabled	Keep IGFX enabled based on the setup options.
GTT Size	2MB4MB8MB	Select the GTT Size
Aperture Size	128MB256MB512MB1024MB2048MB	Select the Aperture Size
DVMT Pre-Allocated	0M32M46M96M128M......60M	Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.
DVMT Total Gfx Mem	128256MAX	Select DVMT5.0 Total Graphic Memory size used bythe Internal Graphics Device.
Intel Graphics Pei Display Peim	EnabledDisabled	Enable/Disable Pei (Early) Display

6.4.1.3. Chipset > System Agent (SA) Configuration > PEG Port Feature Configuration

Feature	Options	Description
PEG Port Feature Configuration	Info Only
Detect Non-Compliance Device	DisabledEnabled	Detect Non-Compliance PCI Express Device in PEG

6.4.1.4. Chipset > System Agent (SA) Configuration > VMD Configuration

Feature	Options	Description
VMD Configuration	Info Only
Enable VMD controller	DisabledEnabled	Enable/Disable to VMD controller

6.4.1.5. Chipset > System Agent (SA) Configuration > PCI Express Configuration

Feature	Options	Description
PCI Express Configuration	Info Only
PCI Express Clock Gating	DisabledEnabled	PCI Express Clock Gating Enable/Disable for each root port.
PCI Express Power Gating	DisabledEnabled	PCI Express Power Gating Enable/Disable for eachroot port.
PCIe function swap	DisabledEnabled	When Disabled, prevents PCIE rootport function swap.If any function other than $0^{th}$ is enabled, $0^{th}$ will become visible.
PCI Express Root Port 1/2/3/4	Submenu

6.4.2 Chipset > PCH-IO Configuration

Feature	Options	Description
PCH-IO Configuration	Info Only	Memory Configuration Parameters
PCI Express Configuration	Submenu	PCI Express Configuration setting
SATA and RST Configuration	Submenu	SATA Device Options Settings
USB Configuration	Submenu	USB Configuration settings
Security Configuration	Submenu	Security Configuration setting
HD Audio Configuration	Submenu	HD Audio Subsystem Configuration Settings
Serial I/O Configuration	Submenu	Serial I/O Configuration Settings
PCH LAN Controller	Info Only
Enable TCO Timer	DisabledEnabled	Enable/Disable TCO timer. When disabled, it disables PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.
Pcie Ref PII SSC	Auto	Pcie Ref PII SSC Percentage. AUTO - Keep hw default, no BIOS override. The range is from 0.0%-0.5%
SPD Write Disable	TRUEFALSE	Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.

6.4.2.1. Chipset > PCH-IO Configuration > PCIE Express Configuration

Feature	Options	Description
PCI Express Configuration	Info Only
DMI Link ASPM Control	DisabledL0sL1L0sL1Auto	The control of Active State Power Management of the DMI Link.
Port8xh Decode	DisabledEnabled	PCI Express Port8xh Decode Enable/Disable
Peer Memory Write Enable	DisabledEnabled	Peer Memory Write Enable/Disable
Compliance Test Mode	DisabledEnabled	Enable when using Compliance Load Board
PCIe function swap	DisabledEnabled	When disabled, prevents PCIE rootport function swap.If any function other than 0th is enabled, 0th will become visible.
PCIE Ports 1-4 Configuration	4x1 Port1x2 2x1 Port2x2 Port1x4 Port	Note:Please make sure the system boots completed after changing the configuration.Do not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.
PCIE Ports 5-8 Configuration	4x1 Port1x2 2x1 Port2x2 Port1x4 Port	Note:Please make sure the system boots completed after changing the configuration.Do not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.
PCIe EQ settings	Submenu	This form contains options for controlling PCIe EQ process.
PCI Express Root Port9/10/11/12/16/17/18/19	Submenu
PCIE clocks	Submenu

6.4.2.1.1. Chipset > PCH-IO Configuration > PCI Express Configuration > PCIe EQ settings

Feature	Options	Description
PCIe EQ override	DisabledEnabled	Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process

6.4.2.1.2. Chipset > PCH-IO Configuration > PCI Express Configuration > PCIe Express Root Port 9/10/11/12/17/18/19/20

Feature	Options	Description
PCI Express Root Port9/10/11/12/17/18/19/20	DisabledEnabled	Control the PCI Express Root Port.
Connection Type	Build-inSlot	Built-In: a built-in device is connected to this root port. Slot Implemented bit will be clear. Slot: this root port connects to user-accessible slot. Slot Implemented bit will be set.
ASPM	DisabledL0sL1L0sL1Auto	Set the ASPM Level:Force L0s – Force all links to L0s StateAuto – BIOS auto configureDISABLE – Disables ASPM
L1 Substates	DisabledL1.1L1.1 & L1.2	PCI Express L1 Substates settings.
ACS	DisabledEnabled	Enable/Disable Access Control Services Extended Capability
PTM	DisabledEnabled	Enable/Disable Precision Time Measurement
DPC	DisabledEnabled	Enable/Disable Downstream Port Containment
EDPC	DisabledEnabled	Enable/Disable Rootport extensions for Downstream Port Containment
URR	DisabledEnabled	PCI Express Unsupported Request Reporting Enable/Disable.
FER	DisabledEnabled	PCI Express Device Fatal Error Reporting Enable/Disable.
NFER	DisabledEnabled	PCI Express Device Non-Fatal Error Reporting Enable/Disable.
CER	DisabledEnabled	PCI Express Device Correctable Error Reporting Enable/Disable.
SEFE	DisabledEnabled	Root PCI Express System Error on Fatal Error Enable/Disable.
SENFE	DisabledEnabled	Root PCI Express System Error on Non-Fatal Error Enable/Disable.
SECE	DisabledEnabled	Root PCI Express System Error on Correctable Error Enable/Disable.
PME SCI	DisabledEnabled	PCI Express PME SCI Enable/Disable.
Hot Plug	DisabledEnabled	PCI Express Hot Plug Enable/Disable.
Advanced Error Reporting	DisabledEnabled	Advanced Error Reporting Enable/Disable.
PCIe Speed	AutoGen1Gen2Gen3	Configure PCIe Speed
Transmitter Halt Swing	DisabledEnabled	Transmitter Half Swing Enable/Disable.
Detect Timeout	0	The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
Extra Bus Reserved	0	Extra Bus Reserved (0-7) for bridges behind this Root Bridge.
Reserved Memory	10	Reserved Memory for this Root Bridge (1-20) MB
Reserved I/O	4	Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.
PCH PCIe LTR Configuration	Info Only
LTR	DisabledEnabled	PCH PCIE Latency Reporting Enable/Disable
Snoop Latency Override	DisabledManualAuto	Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.
Non-Snoop Latency Override	DisabledManualAuto	Non-Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manual enter override values.Auto (default): Maintain default bios flow.
Force LTR Override	DisabledEnabled	Force LTR Override for PCH PCIE.
LTR Lock	DisabledEnabled	PCIE LTR Configuration Lock

6.4.2.1.3. Chipset > PCH-IO Configuration > PCI Express Configuration > PCIE clocks

Feature	Options	Description
Clock0-15 assignment	Platform-POREnabledDisabled	Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.
ClkReq for Clock0-15	Platform-PORDisabled	Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.

6.4.2.2. Chipset > PCH-IO Configuration > SATA And RST Configuration

Feature	Options	Description
SATA and RST Configuration	Info Only
SATA Controller	EnabledDisabled	Enable/Disable SATA Device.
SATA Mode Selection	AHCIIntel RST Premium with Intel Optane SystemAcceleration	Determines how SATA controller(s) operate.
SATA Test Mode	EnabledDisabled	Test Mode Enable/Disable (Loop Back).
Software Feature Mask Configuration	Submenu	RST Legacy OROM/RST UEFI driver will refer to the SWFM configuration to enable/disable the storage features.
Aggressive LPM Support	DisabledEnabled	Enable PCH to aggressively enter link power state.
SATA Controller Speed	DefaultGen1Gen2Gen3
Serial ATA Port x	Info Only
Software Preserve	Info Only
Port x	DisabledEnabled	Enable or Disable SATA Port
Hot Plug	DisabledEnabled	Designates this port as Hot Pluggable.
Configured as eSATA	Info Only
External	DisabledEnabled	Marks this port as external.
Spin Up Device	DisabledEnabled	If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.
SATA Device Type	Hard Disk DriveSolid State Drive	Identify the SATA port is connected to Solid State Drive or Hard Disk Drive
Topology	UnknownISATADirect ConnectFlexM2	Identify the SATA Topology if it is Default or ISATA or Flex or Direct Connect or M2
SATA Portx DevSlp	DisabledEnabled	Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.
DITO Configuration	DisabledEnabled	Enable/Disable DITO Configuration
DITO value	Info Only
DM Value	Info Only

6.4.2.2.1. Chipset > PCH-IO Configuration > SATA Configuration > Software Feature Mask Configuration

Feature	Options	Description
Software Feature Mask Configuration	Info Only
HDD Unlock	DisabledEnabled	If enabled, indicates that the HDD password unlock in the OS is enabled.
LED Locate	DisabledEnabled	If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.

6.4.2.3. Chipset > PCH-IO Configuration > USB Configuration

Feature	Options	Description
USB2 PHY Sus Well Power Gating	GEN1GEN2	Select 'Enabled' to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H
USB3 Link Speed Selection	DisabledEnabled	This option is to select USB3 Link Speed GEN1 or GEN2
USB PD0 Programming	DisabledEnabled	Select 'Enabled' if Port Disable Override functionality is used.
XHCI LTR Mode	DisabledEnabled	Enable/Disable XHCI LTR Mode
USB Overcurrent	DisabledEnabled	Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.
USB Overcurrent Lock	DisabledEnabled	Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data
USB Port Disable Override	DisabledSelect Per-Pin	Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.

6.4.2.4. Chipset > PCH-IO Configuration > Security Configuration

Feature	Options	Description
Security Configuration	Info Only
RTC Memory Lock	DisabledEnabled	Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM
BIOS Lock	DisabledEnabled	Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.
Force unlock on all GPIO pads	DisabledEnabled	If Enabled BIOS will force all GPIO pads to be in unlocked state

6.4.2.5. Chipset > PCH-IO Configuration > HD Audio Configuration

Feature	Options	Description
HD Audio Subsystem Configuration Settings	Info Only
HD Audio	DisabledEnabled	Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled.

6.4.2.6. Chipset > PCH-IO Configuration > Serial I/O Configuration

Feature	Options	Description
Serial I/O Configuration	Info Only
I2C0 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C1 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C2 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C3 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C4 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C5 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C6 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
I2C7 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
SPI0 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
SPI1 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
SPI2 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
SPI3 Controller	DisabledEnabled	Enables/Disables Serial I/O Controller
UART0 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
UART1 Controller	DisabledEnabledCommunication port(COM)	Enables/Disables Serial I/O Controller
UART2 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
UART3 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
UART4 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
UART5 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
UART6 Controller	DisabledEnabledCommunication port (COM)	Enables/Disables Serial I/O Controller
Serial I/O D3 State	DisabledEnabled	Enable/Disable Serial I/O D3 State
GPIO IRQ Route	IRQ14IRQ15	Route all GPIOs to one of the IRQ.
Serial I/O I2C0 Settings	Submenu	Configure Serial I/O Controller
Serial I/O I2C2 Settings	Submenu	Configure Serial I/O Controller
Serial I/O I2C3 Settings	Submenu	Configure Serial I/O Controller
Serial I/O I2C4 Settings	Submenu	Configure Serial I/O Controller
Serial I/O I2C5 Settings	Submenu	Configure Serial I/O Controller
WITT/MITT I2C Test Device	DisabledEnabled	Enable SIO I2C WITT Device and select which are all controller used it
UART Test Device	DisabledEnabled	Enable SIO UART Test Device and select which are all controller used it
Additional Serial I/O devices	DisabledEnabled	When enabled, ACPI will report additional devices connected to Serial I/O.
Serial I/O timing parameters	DisabledEnabled	Enables additional timing parameters for all Serial I/O controllers.

6.4.2.6.1. Chipset > PCH-IO Configuration > Serial I/O Configuration > Serial I/O I2C0/I2C2/I2C3/I2C4/I2C5 Settings

Feature	Options	Description
Serial io I2C0/I2C2/I2C3/I2C4/I2C5 Settings	Info Only
Serial IO Touch Pad Settings	Submenu
Timing parameters	Info Only

6.4.2.6.1.1. Chipset > PCH-IO Configuration > Serial I/O Configuration > Serial I/O I2C0/I2C2/I2C3/I2C4/I2C5 Settings > Serial I/O Touch Pad Settings

Feature	Options	Description
Touch Pad	DisabledSynaptics Precision TouchpadSynaptics ForcepadALPS Precision Touchpad ClickPadCustom Device	Indicates what type of I2C Touch Pad is connected to this Serial I/O controller

# 6.5. Security Menu 6.5.1 Security > Password Description

Feature	Options	Description
Password Description	Info only
Setup Administrator Password	Enter Password	Set Setup Administrator Password
User Password	Enter Password	Set User Password
Secure Boot	Submenu	Customizable Secure Boot settings.
System Mode	Info only
Secure Boot	Info only
Secure Boot Control	DisabledEnabled	Secure Boot activated when Platform Key (PK) is en-rolled, System mode is User / Deployed, and CSM function is disabled

# 6.6. Boot Menu 6.6.1 Boot > Boot Configuration

Feature	Options	Description
Boot Configuration	Info only
Setup Prompt Timeout	1	Number of seconds to wait for setup activation key.65535(0xFFFF) means indefinite waiting.
Bootup NumLock State	OnOff	Select the keyboard Number state.
Quiet Boot	DisabledEnabled	Select the keyboard NumLock state.
Fast Boot	DisabledEnabled	Enable or Disable FastBoot features.Most probes are skipped to reduce time cost during boot.
SATA Support	Last Boot SATA Devices OnlyAll SATA Devices	If Last Boot SATA Devices Only, only last boot SATA device will be available in Post.If All SATA Devices, all SATA devices will be available in OS and Post.
VGA Support	AutoEFI Driver	If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. Efi driver will still be installed with EFI OS.
PS2 Devices Support	DisabledEnabled	If disabled, PS2 devices will be skipped.
Network Stack Driver Support	DisabledEnabled	If disabled, the Network Stack Driver will be skipped.
Redirection Support	DisabledEnabled	If disabled, the Redirection function will be disabled.

6.6.2 Boot > FIXED BOOT ORDER Priorities

Feature	Options	Description
Boot Option #1	Hardware	Set the system boot order.
Boot Option #2	CD/DVD	Set the system boot order.
Boot Option #3	USB Hard Disk	Set the system boot order.
Boot Option #4	USB CD/DVD	Set the system boot order.
Boot Option #5	USB Key	Set the system boot order.
Boot Option #6	USB Floppy	Set the system boot order.
Boot Option #7	USB Lan	Set the system boot order.
Boot Option #8	Network	Set the system boot order.

# 6.7. Save & Exit Menu 6.7.1 Save and Exit

Feature	Options	Description
Save Changes and Exit		Exit system setup after saving the changes.
Discard Changes and Exit		Exit system setup without saving any changes.
Save Change and Reset		Reset the system after saving the changes.
Discard Changes and Reset		Reset system setup without saving any changes.
Save Options	Info only
Save Changes		Save Changes done so far to any of the setup options.
Save as User Defaults		Save the changes done so far as User Defaults.
Restore User Defaults		Restore the User Defaults to all the setup options.
Boot Override	Info only

# 7. BIOS Checkpoints, Beep Codes A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. The Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes. Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but the Aptio 5.x core can be configured to send checkpoints to a variety of sources. The Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware. A beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process. ![A red icon on a white background depicting a document or file symbol with a folded top-right corner, featuring three horizontal red lines centered inside.](.express-tl-50m-72138-1050-15/8952fb40cbd5ed7498f4d9dedf14726f10ecb2c2dec6e5ce96e01d6da8c3a595.jpg) Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify the user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes # Viewing Checkpoints Checkpoints generated by the Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-on cards show the value of I/O port 80h on an LED display. # Aptio V Checkpoint and Beep Codes Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes # 8. Software Support 8.1. Windows 10 IoT Enterprise 64-bit 8.2. Yocto Linux 64-bit https://github.com/ADLINK/meta-adlink-x86-64bit (TBC) # 9. Mechanical and Thermal 9.1. Module Dimensions ![95\n91\n90.73\n26.56\n4\n0\n0 4\n50.24\n72.68\n80\n121\n125\n91\n4](.express-tl-50m-72138-1050-15/21d93ff658ae958b94d2eaeb69c4817f9c4c857456f3e7d1033597146474eea1.jpg) ![Top View\n9.25 ±0.25\n2\n8.05 ±0.25\nFront View](.express-tl-50m-72138-1050-15/efead611370ee85201f72291a0946b13956784e8ca2d4c6e4d7ea055cc5bb493.jpg) ![91\n87.25\nBottom Side RAM\nModule Keepout\n8.35\n125\n121\n86.94\n80\n74.2\n72.676\n50.235\n16.5\n4\n0\n95\n91\n90.73\n26.56\n18\n6\n4\n0](.express-tl-50m-72138-1050-15/d7b36e1cff5f194c576102af03bffc0da29c5b3ad219eb17c049dd058645a6d4.jpg) Bottom View All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances on the module connector locating peg holes (dimensions [16.50, 6.00]&[16.50,18.00]) should be ± 0.10mm. Dimensions: mm Figure 6 – Module mechanical dimensions # 9.2. Thermal Solutions # 9.2.1 Heatspreader: HTS ![The image displays a technical 3D model and orthographic drawing of a mechanical assembly, with the label 'Dimensions: mm' in the top right corner.\n\n**Top Section:**\n* **Left:** A side profile view showing vertical dimensions of 11 and 5.\n* **Center:** An isometric view of a grey plate assembly featuring a central orange and blue rectangular component. Callouts indicate screw specifications: 'M2.5*2pcs' and 'M2.5*4pcs'.\n* **Right:** A top-down view of the main grey plate.\n\n**Bottom Section:**\n* **Left:** A top-down view of the plate with overall dimensions of 95 (vertical) and 95 (horizontal).\n* **Center:** A thin side profile view.\n* **Right:** A front view showing the plate with mounting holes and the central component, annotated with dimensions 87 (top width), 65 (vertical height), and 76 (bottom width).](.express-tl-50m-72138-1050-15/39aef0052b89b6abdda7cf1a21ecd34cf0f1622824191144da7b53b3bb5b3591.jpg) Figure 7 – Heatspreader: HTS # 9.2.2 Heatsink: THS Dimensions: mm ![The image displays a multi-view technical rendering of a heatsink assembly.\n\n* **Top Left:** A side profile view with vertical dimensions labeled **16.4** and **5**.\n* **Top Center:** An isometric view of the base plate featuring a central component, annotated with **M2.5*2pcs** pointing to screws and **M2.5*4pcs** pointing to mounting posts.\n* **Top Right:** An isometric view showing the array of cooling fins.\n* **Bottom Left:** A front view of the fins with overall dimensions labeled **95** vertically and **95** horizontally.\n* **Bottom Center:** A side profile view showing the fin thickness and base.\n* **Bottom Right:** A rear view of the base plate with mounting holes, annotated with dimensions **87** vertically and **76** horizontally.](.express-tl-50m-72138-1050-15/689c7a64e1d3fc28c06601f2b931fc216960f868599145c27e6595a6db2d7d8f.jpg) Figure 8 – Heatsink: THS # 9.2.3 Heatsink High Profile: THSH Dimensions: mm ![M2.5*2pcs\nM2.5*4pcs\n25.1\n5](.express-tl-50m-72138-1050-15/9a9a8f6ba0a2d67ef03728ec42e5fe4cb951fc4052f4effc90d37a94337a2534.jpg) ![Technical drawing of a mechanical component with horizontal grooves and mounting holes, dimensioned at 95 units (no text or symbols)](.express-tl-50m-72138-1050-15/5d6a09a893250482c873b50cf888d0206bc9d0f615c81cd7646c81d597cdef74.jpg) ![Pure mechanical component diagram without any text, numbers, or symbols](.express-tl-50m-72138-1050-15/e8d5e138a65c7a559efed38c58e0810df282fe7a8639eb2137825b8230d000eb.jpg) ![87\n76](.express-tl-50m-72138-1050-15/cc44f3fb42aa376662edcb92807faf8c130375071b8ccd2f74853564c190e258.jpg) Figure 9 – Heatsink High Profile: THSH # 9.2.4 Heatsink with Fan: THSF Dimensions: mm ![M2.5*x4pcs\nM2.5*2pcs\n39.4\n5](.express-tl-50m-72138-1050-15/02928f72d6af63fcb9817bd83d3a71425d60e6e573c395ae17dffd75b191af50.jpg) ![Technical diagram of a hexagonal grid pattern on a rectangular base, with dimension annotations (95) shown for both sides.](.express-tl-50m-72138-1050-15/85765572d837754ef4cbea46e3a843b0867d25f2b9f72f0808724c2e39192977.jpg) ![Pure mechanical component diagram without any text, numbers, or symbols](.express-tl-50m-72138-1050-15/5077721994f2fc79ec44d37ab4b26837da42f4fbaaffa6c75f9a84fa54c664db.jpg) ![87\n76](.express-tl-50m-72138-1050-15/ce20e45ea8a521a308d13fced9d04f4d1efe3d1d2d252b478c25efb6aefff416.jpg) Figure 10 – Heatsink with Fan: THSF [🔗 Link to the original document](.express-tl-50m-72138-1050-15/express-tl-50m-72138-1050-15.pdf)