# Express-VR7

User’s Guide

AMDD

![Green printed circuit board with visible components and connectors (no readable text or symbols)](.express-vr7-50m-72140-1000-01-240516/63d75ec6378f9b020794c6b864b66a5bd9ae76ebfde9013c5ee1a20a986081e9.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2024-05-16</td><td>CC</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard yellow triangular warning sign with a thick black border. Inside the triangle is a large, black exclamation point centered vertically. The sign is set against a plain white background, appearing as a cropped vertical section.](.express-vr7-50m-72140-1000-01-240516/fb88fee2f86382494c4917884a6a8514baced4bf3c06d67bb80ab837c73d226e.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black line drawing of a wheeled trash bin that is crossed out by a large black 'X'. Below the bin is a solid black rectangular shape.](.express-vr7-50m-72140-1000-01-240516/015497b9636af2ff0d249f453ec53900aafb2cb9f6ceda6c2b38d6eee3e3f4d9.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2024 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a simple icon of a document or page. It features a thick red outline in the shape of a rectangle with the bottom-right corner folded over. Inside the white space, there are two horizontal red lines centered vertically, representing text.](.express-vr7-50m-72140-1000-01-240516/cb458759a81acfa95f371febe0eb7c79639cdd154dbabc0021c3f3dbd59d7fa1.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow triangular warning sign with a white exclamation point centered within it.](.express-vr7-50m-72140-1000-01-240516/5206c24d8d933be99b60622aef2d7043e64a8a5b1385108dce10fbb1c61dba96.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image features a standard warning symbol consisting of a red equilateral triangle pointing upwards with a white exclamation mark centered inside it, set against a white background.](.express-vr7-50m-72140-1000-01-240516/be15eee25c0300ecbdad14bf129c18f161e310df4a5a148d8b64fb30d48a7f28.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

List of Figures ... ..10

1. Introduction ...
2. Specifications... .12

2.1. Core System... . 12
2.2. Expansion Buses.. ... 13
2.3. 10G-KR Ethernet .. ... 14
2.4. GbE Ethernet.. ... 15
2.5. Multi I/O and Storage.. .. 15
2.6. Trusted Platform Module (TPM).. .. 16
2.7. SEMA Board Controller ... ... 16
2.8. IPMB (Intelligent Platform Management Bus)... .. 17
2.9. Debug... .. 17
2.10. Power... ... 17
2.11. Mechanical and Environmental . .. 18

3. Block Diagram... .19
4. Pinout and Signal Descriptions .. ..20

4.1. Pin Summary .. . 20
4.2. Signal Terminology Descriptions.. . 25
4.3. AB Connector Signal Descriptions .. ... 26

4.3.1 Network Controller Sideband Interface (NC-SI) .. . 26
4.3.2 Gigabit Ethernet... . 27
4.3.3 SATA . . 28
4.3.4 PCI Express... ... 29
4.3.5 LPC Bus... ... 33
4.3.6 USB.... ... 34
4.3.7 SPI Bus (BIOS only).. . 35
4.3.8 Miscellaneous . ... 36

4.3.9 SMBus. . 37

4.3.10 I2C Bus... . 37

4.3.11 General Purpose I/O (GPIO) .. .. 38

4.3.12 Serial Interface Signals.. ... 38

4.3.13 IPMB (Optional) .. ... 39

4.3.14 Power and System Management . ... 40

4.3.15 Power and Ground . . 42

4.4. CD Connector Signal Descriptions.. .. 43

4.4.1 USB 3.0 Extensions .. .... 43

4.4.2 PCI Express... .... 44

4.4.3 10G-KR Ethernet.. .... 45

4.4.4 PCI Express... . 47

4.4.5 GP\_SPI .... .... 49

4.4.6 Module Type Definition .. . 50

4.4.7 Power and Ground .. . 51

5. Additional Features ...... ..52

5.1. Debug Connector.. . 53

5.2. Status LEDs... . 54

5.3. Exception Codes.. . 55

5.4. Fan Connector... . 56

5.5. BIOS Default Reset Button... . 57

5.6. BIOS Boot Select.. . 58

6. BIOS Checkpoints, Beep Codes .. .59

7. Software Support ......... ..60

7.1. Yocto Linux.. . 60

7.2. Ubuntu 20.04.3 LTS.. . 60

7.3. SEMA API ... . 60

8. Mechanical and Thermal.. ...61

8.1. Module Dimensions – Top View ... . 61

8.2. Module Dimensions – Bottom View.. . 62

8.3. Module Dimensions – Side View .. . 63

8.4. Height of Processor and Static Compressive Load . . 63

8.5 Thermal Solutions . . 64

8.5.1 HTS-B .. .... 64

8.5.2 HTS-BT... .... 65

8.5.3 THS-B ... .... 66

8.5.4 THS-BT... . 67
8.5.5 THSF-B.. .... 68
8.5.6 THSH-B.. .... 69
8.6. Board to Board Connectors.. ... 70
8.7. Mounting Method... ... 72
8.8. Standoff Types... ... 73
8.9. Installation ... ... 74

# List of Figures

Figure 1 – Module functional block diagram. ..19
Figure 2 - Module rear side row and pin numbering ....... ...20
Figure 3 – Module feature locations........ ..52
Figure 4 – Express-VR7 and Debug Module... .53

# 1. Introduction

![The image displays a standard warning symbol consisting of a red equilateral triangle with rounded corners containing a white exclamation mark in the center.](.express-vr7-50m-72140-1000-01-240516/1b12e72dc39d8b13ec2d2a79b177b46e671fec00800786e64152d7e822452238.jpg)

Warning: this is an EA (early available) engineering manual, meaning contents might not properly reflect the actual/final version of the product

The Express-VR7 is a COM Express® COM.0 R3.1 Basic Size Type 7 module based on the new-generation and data-communication-focused AMD® Ryzen Embedded processors (formerly “V3000”) supporting up to 8 cores (Zen3) at maximum 45W TDP, up to 2x DDR5 SO-DIMMs supporting a maximum of 64GB memory capacity at up to 4800 MT/s. All-around PCIe Gen4 support and integrated 10G Ethernet connectivity makes it suit for highperformance, low-power-consumption, and fast-response-required applications, including, but not limited to, edge networking equipment, 5G infrastructure at the edge, video storage analytics, intelligent surveillance, and industrial automation and control.

Additional extended operating temperature SKUs at 15W TDP (10W configurable), combined with dual-channel ECC memory features makes it fitting for fanless architecture and mission-critical applications in extreme environments.

An integrated AMD® 10G Ethernet controller supports two 10GBASE-KR interfaces, with relevant sideband signals effectively reducing hardware and firmware complexity for system integration. The Express-VR7 is designed to serve customers requiring optimized computing capability per watt and high speed connectivity who want to outsource the custom core logic of their systems for reduced development time.

Input/output features include 14 PCIe Gen4 lanes, a single onboard 2.5-Gigabit Ethernet port, 4x USB 3.0/2.0 ports up to 10Gb/s, and 2x SATA 6 Gb/s ports. Additional General Purpose SPI (GP\_SPI) and remoted management dedicated IPMB are offered by project basis. Support for SMBus and I2C is also provided. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer.

# 2. Specifications

# 2.1. Core System

# CPU

AMD® Zen3 based Ryzen Embedded Processor (formerly “V3000”)

AMD® V3C48 3.3/3.8GHz, 45W with 35-54W cTDP (8C/16T)
AMD® V3C44 3.5/3.8GHz, 45W with 35-54W cTDP (4C/8T)
AMD® V3C18I 1.9/3.8GHz, 15W with 10-25W cTDP (8C/16T) (eTEMP)
AMD® V3C18 1.9/3.8GHz, 15W with 10-25W cTDP (8C/16T)
AMD® V3C16 2.0/3.8GHz, 15W with 10-25W cTDP (6C/12T)
AMD® V3C14 2.3/3.8GHz, 15W with 10-25W cTDP (4C/8T)

# Memory

Up to 64GB DDR5, dual memory channel in 2x SODIMM sockets, maximum 32GB per socket, ECC or non-ECC

Up to 4800 MT/s memory speed (dependent on SKUs)

2x SODIMM sockets on top side

# Cache (L3)

16MB: V3C48, V3C18I, V3C18, V3C16

8MB: V3C44, V3C14

# Embedded BIOS

AMI Aptio V UEFI with CMOS backup in 32 MB SPI BIOS, dual BIOS by build option

# 2.2. Expansion Buses

8 PCI Express Gen4: Lane 16-23 (two controllers, configurable to 1 x8 or 2 x4)

PCIe reference clock can be PCIE\_CK\_REF1 (pin B29/B30) or PCIE\_CK\_REF (pin A88/A89). PCIE\_CK\_REF1 recommended

4 PCI Express Gen4: Lanes 0-3 (four controllers, configurable to 1 x4, 2 x2/x1) (4 x1 usage supported but requires prior inquiries)

2 PCI Express Gen4: Lane 4-5 (one controller only, configurable to 1 x2/x1)

![The image features a red icon on a white background, depicting a document with a folded upper-right corner. Inside the shape are two horizontal red lines centered vertically.](.express-vr7-50m-72140-1000-01-240516/3a848ea88f7a699843998cacadffe59268e98e12375cff2b051d2b2338171684.jpg)

Note: Preferred Link Configuration on PCIE 0-3 defined by PICMG is 1 x4 or 1 x2 or 1 x1. PCIe Gen4 support also depends on carrier board design

Other: SMBus (system), I2 C (user), LPC bus (via eSPI to LPC bridge IC).

I 2 C from CPU is supported by BOM option and project basis

SMBus from EC (embedded controller) is supported by BOM option and project basis

Additional GP\_SPI (general purpose SPI by project basis)

# 2.3. 10G-KR Ethernet

AMD® Ethernet Controller integrated on CPU

2x 10GBASE-KR and sideband signals

PHY on carrier and PHY firmware are required for 10G SFP+ and Copper 10GBASE-T applications

The recommended PHY for SFP+ is InPhi CS4227, for 10GBASE-T is Marvell AQR113C. The enablement of other PHY may require platform supplier support. The reference 10G adapter card ADLINK offering are named as CEI-CS4227-2x10G-SFP+ and CEI-AQR113C-2x10GBASE-T

10G Ethernet Controller firmware is combined into BIOS code and stored on the same SPI ROM, on COM Express module

10G Ethernet Controller firmware has three type

one for SFP+ (CS4227 on carrier)
one for 10GBASE-T (AQR113C on carrier)
one for KR only usage (no PHY on carrier)

The default setting is TBC. Different type can be selected on BIOS menu (advance -> AMD PBS section)

10G\_SDP 0-3 are supported by project basis. 10G\_SDP 0-1 optionally works as PPS input and 10G\_SDP 2-3 optionally works as PPS output

![The image features a red outline of a document icon with a folded top-right corner. Inside the outline, there are two horizontal red lines centered in the middle.](.express-vr7-50m-72140-1000-01-240516/2ad55cb60f15c92f0bbb8c521d15906de5bf9703c4dc30c853fdad89d9f483c4.jpg)

Note: please contact our local ADLINK representative for information below. (1) Detailed information about circuit design between the Ethernet controller, Optical Fiber/Copper PHY and firmware. (2) Additional MDC/MDIO is offered for specific use case based on 10GBASE-T, by project basis. (3) SGMII offering for specific use case and by project basis. (TBC) (4) 10G\_SDP support is by project basis

# 2.4. GbE Ethernet

Intel® Ethernet Controller I226 Series

Up to 2.5GbE, 1000/100/10 Mbit/s connections

GBE0\_SDP are supported on select SKU and by project basis (TBC)

# 2.5. Multi I/O and Storage

# USB

4x USB 3.0/2.0/1.1 (USB 0, 1, 2, 3)

SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling

Up to 10Gb/s and also depends on carrier board design

USB\_OC pins share the same source, from SoC.

# SATA

2x SATA 6Gb/s (SATA 0,1)

# UART

2x UART interfaces SER0 and SER1 RX/TX on module

Console Redirection COM 1 or COM 2 selectable in BIOS

SER0, SER1 from CPU UART are supported by BOM option and project basis

Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via embedded controller</td><td>4</td><td>0x3F8</td><td>Yes</td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via embedded controller</td><td>3</td><td>0x2F8</td><td>Yes</td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>5</td><td>0x240</td><td>Yes</td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>7</td><td>0x248</td><td>Yes</td></tr></table>

# GPIO or SD

4 GPO and 4 GPI (GPI with interrupt, TBC)

GPI and GPO from CPU GPIO are supported by BOM option and project basis

# 2.6. Trusted Platform Module (TPM)

Chipset: Infineon solution

Type: TPM 2.0 (SPI bus-based)

TPM chip is supported by project basis

# 2.7. SEMA Board Controller

Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2C, failsafe BIOS (dual BIOS, opt. support), watchdog timer and fan control

# 2.8. IPMB (Intelligent Platform Management Bus)

An IPMB (“Intelligent Platform Management Bus”) port is defined for platform management functions. The IPMB is used (optionally) with a Carrier based BMC (Board Management Controller) Master. On the Module, the IPMB should be routed to and used with a MMC (Module Management Controller). The Module IPMB is a slave port and uses I2C signaling.

IPMB through a MMC is build option support and by project basis

The conjunction between Module MMC and Carrier BMC is still in developing (TBC)

# 2.9. Debug

40-pin flat cable connector for use with DB40-HPC debug module

Supports embedded controller access, SPI BIOS flashing, internal power rail test points, debug LEDs, and BIOS POST code LED

# 2.10. Power

Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)

Standard Voltage Input: AT: 12V±5% or ATX: 12V±5% / 5Vsb ±5%

Wide Voltage Input: AT: 8.5-20V or ATX: 8.5-20V / 5Vsb ±5% (only for standard operating temperature)

Power Management: ACPI 5.0 compliant

Power States: C0-C3, S0, S5, S5 ECO mode (Wake-on-USB S3, WoL S3/S5)

ECO Mode support for deep S5 for 5Vsb power saving

# Power Consumption

Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.

# 2.11. Mechanical and Environmental

# Form Factor and specification

PICMG COM Express Rev 3.1 (COM.0 R3.1), Type 7, Basic size 125 x 95 mm

# Operating Temperature

Standard 0°C to 60°C Storage: -20°C to 80°C

Extreme Rugged -40°C to 85°C Storage: -40°C to 85°C (build option by project basis, selected SoC SKUs)

# Humidity

5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# HALT tested

Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

# 3. Block Diagram

![This block diagram illustrates the connectivity of the **AMD Embedded Ryzen V3000** processor.\n\n**Central Block**\n*   **AMD Embedded Ryzen V3000**: A large reddish square labeled with 'GEN4' at the top left, top center, and top right.\n    *   Near the bottom edge, it lists interfaces: **I2C**, **2x UART**, **4x GPI**, **4x GPO**, and **eSPI**.\n\n**Left Column Connections**\n*   **PCIe Lane 0-3**: Connects to the central block via a line labeled **x4, x2, x1 (four controller)**.\n*   **PCIe Lane 4-5**: Connects to the central block via a line labeled **x2 (one controller)**.\n*   **USB 2.0 Lane 0-3**: Connects directly to the central block.\n*   **SATA Port 0-1**: Connects directly to the central block.\n*   **Up to 2.5GbE NCSI**: Connects to a box labeled **i226**, which then connects to the central block.\n*   **SPI**, **GP_SPI (OEM)**, and **SMBus**: Connect directly to the central block.\n*   **I2C**, **UART 0-1**, **4x GPI Interrupt**, and **4x GPO**: Lines from these labels go downward to connect to the **Embedded Controller**.\n*   **LPC/eSPI**: Connects to the **Embedded Controller**.\n*   **IPMB**: Connects via a dashed line to a box labeled **MMC**.\n\n**Right Column Connections**\n*   **PCIe Lane 16-23**: Connects to the central block via a line labeled **x8, x4 (two controller)**.\n*   **USB 3.x Lane 0-3 (high speed lanes)**: Connects directly to the central block.\n*   **10G_SDP 0-1**: Connects directly to the central block.\n*   **10G_SDP 2-3**: Connects directly to the central block.\n*   **10G_KR 0-1 & sideband signals (additional MDIO/MDC, OEM)**: Connects directly to the central block.\n\n**Bottom Section & Intermediary Blocks**\n*   **Embedded Controller**: A large light blue box connected to:\n    *   **LPC/eSPI** (from left column).\n    *   **I2C**, **UART 0-1**, **4x GPI Interrupt**, **4x GPO** (from left column).\n    *   **eSPI to LPC Bridge IC**: Connected via a solid line.\n    *   **Thermal sensor (TBC)** and **Thermal sensor (board)**: Connected via solid lines.\n    *   **I2C**, **2x UART**, **4x GPI**, **4x GPO**: Lines connecting upward to the central block.\n*   **eSPI to LPC Bridge IC**: A smaller box connected between the **Embedded Controller** and the **eSPI** label on the central block.\n*   **TPM** and **BIOS**: Small boxes connected via dashed lines to the central block area (near SPI/I2C).\n*   **MMC**: A small box connected via a dashed line to the central block area (near I2C).\n*   **DDR5 SODIMM ECC/non-ECC**: Two boxes connected via vertical lines to the bottom of the central block.](.express-vr7-50m-72140-1000-01-240516/02775c5d52a1fc23678d0b068509dfb8115819009c42c194556496043dc130b6.jpg)

Figure 1 – Module functional block diagram

# 4. Pinout and Signal Descriptions

# 4.1. Pin Summary

The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 7 in the PICMG COM.0 R3.1 specification. Signals described in the specification but not supported on the Express-VR7 are strikethrough STRIKETHROUGH

![D1\nCD\nC1\nB1\nAB\nA1 10\nA1](.express-vr7-50m-72140-1000-01-240516/e24bbb1465c77e72fc5938bfe9062d9c9e200ef5849660085ad32dc8356b90f1.jpg)

Figure 2 - Module rear side row and pin numbering

![The image displays a red outline icon resembling a document or note with a folded top-right corner. Inside the white interior, there are two horizontal red lines centered within the shape.](.express-vr7-50m-72140-1000-01-240516/30953e9e20f6adc0e403a903bb75e25ee1948ba148b9f0a1057d2786910b7c72.jpg)

Note: The 2x SO-DIMM sockets (grey color) are located on top side.

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>GND (fixed)</td><td></td><td>B1</td><td>GND (fixed)</td><td></td><td>C1</td><td>GND (fixed)</td><td></td><td>D1</td><td>GND (fixed)</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td></td><td>B2</td><td>GBE0_ACT#</td><td></td><td>C2</td><td>GND</td><td></td><td>D2</td><td>GND</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td></td><td>B3</td><td>LPC_FRAME#</td><td></td><td>C3</td><td>USB_SSRX0-</td><td></td><td>D3</td><td>USB_SSTX0-</td></tr><tr><td>A4</td><td>GBE0_LINK_MID#</td><td></td><td>B4</td><td>LPC_AD0</td><td></td><td>C4</td><td>USB_SSRX0+</td><td></td><td>D4</td><td>USB_SSTX0+</td></tr><tr><td>A5</td><td>GBE0_LINK_MAX#</td><td></td><td>B5</td><td>LPC_AD1</td><td></td><td>C5</td><td>GND</td><td></td><td>D5</td><td>GND</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td></td><td>B6</td><td>LPC_AD2</td><td></td><td>C6</td><td>USB_SSRX1-</td><td></td><td>D6</td><td>USB_SSTX1-</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td></td><td>B7</td><td>LPC_AD3</td><td></td><td>C7</td><td>USB_SSRX1+</td><td></td><td>D7</td><td>USB_SSTX1+</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td></td><td>B8</td><td>LPC_DRQ0#</td><td></td><td>C8</td><td>GND</td><td></td><td>D8</td><td>GND</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td></td><td>B9</td><td>LPC_DRQ1#</td><td></td><td>C9</td><td>USB_SSRX2-</td><td></td><td>D9</td><td>USB_SSTX2-</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td></td><td>B10</td><td>LPC_CLK</td><td></td><td>C10</td><td>USB_SSRX2+</td><td></td><td>D10</td><td>USB_SSTX2+</td></tr><tr><td>A11</td><td>GND (fixed)</td><td></td><td>B11</td><td>GND (fixed)</td><td></td><td>C11</td><td>GND (fixed)</td><td></td><td>D11</td><td>GND (fixed)</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td></td><td>B12</td><td>PWRBTN#</td><td></td><td>C12</td><td>USB_SSRX3-</td><td></td><td>D12</td><td>USB_SSTX3-</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td></td><td>B13</td><td>SMB_CK</td><td></td><td>C13</td><td>USB_SSRX3+</td><td></td><td>D13</td><td>USB_SSTX3+</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td></td><td>B14</td><td>SMB_DAT</td><td></td><td>C14</td><td>GND</td><td></td><td>D14</td><td>GND</td></tr><tr><td>A15</td><td>SUS_S3#</td><td></td><td>B15</td><td>SMB_ALERT#</td><td></td><td>C15</td><td>RSVD10G</td><td></td><td>D15</td><td>RSVD10G</td></tr><tr><td>A16</td><td>SATAO_TX+</td><td></td><td>B16</td><td>SATA1_TX+</td><td></td><td>C16</td><td>RSVD10G</td><td></td><td>D16</td><td>RSVD10G</td></tr><tr><td>A17</td><td>SATAO_TX-</td><td></td><td>B17</td><td>SATA1_TX-</td><td></td><td>C17</td><td>10G_SDP2*</td><td></td><td>D17</td><td>10G_SDP3*</td></tr><tr><td>A18</td><td>SUS_S4#</td><td></td><td>B18</td><td>SUS_STAT#</td><td></td><td>C18</td><td>GND</td><td></td><td>D18</td><td>GND</td></tr><tr><td>A19</td><td>SATAO_RX+</td><td></td><td>B19</td><td>SATA1_RX+</td><td></td><td>C19</td><td>PCIE_RX6+</td><td></td><td>D19</td><td>PCIE_TX6+</td></tr><tr><td>A20</td><td>SATAO_RX-</td><td></td><td>B20</td><td>SATA1_RX-</td><td></td><td>C20</td><td>PCIE_RX6-</td><td></td><td>D20</td><td>PCIE_TX6-</td></tr><tr><td>A21</td><td>GND (fixed)</td><td></td><td>B21</td><td>GND (fixed)</td><td></td><td>C21</td><td>GND (fixed)</td><td></td><td>D21</td><td>GND (fixed)</td></tr><tr><td>A22</td><td>PCIE_TX15+</td><td></td><td>B22</td><td>PCIE_RX15+</td><td></td><td>C22</td><td>PCIE_RX7+</td><td></td><td>D22</td><td>PCIE_TX7+</td></tr><tr><td>A23</td><td>PCIE_TX15-</td><td></td><td>B23</td><td>PCIE_RX15-</td><td></td><td>C23</td><td>PCIE_RX7-</td><td></td><td>D23</td><td>PCIE_TX7-</td></tr><tr><td>A24</td><td>SUS_S5#</td><td></td><td>B24</td><td>PWR_OK</td><td></td><td>C24</td><td>RSVD10G</td><td></td><td>D24</td><td>RSVD10G</td></tr><tr><td>A25</td><td>PCIE_TX14+</td><td></td><td>B25</td><td>PCIE_RX14+</td><td></td><td>C25</td><td>GND</td><td></td><td>D25</td><td>GND</td></tr><tr><td>A26</td><td>PCIE_TX14-</td><td></td><td>B26</td><td>PCIE_RX14-</td><td></td><td>C26</td><td>10G_KR_RX3+</td><td></td><td>D26</td><td>10G_KR_TX3+</td></tr><tr><td>A27</td><td>BATLOW#</td><td></td><td>B27</td><td>WDT</td><td></td><td>C27</td><td>10G_KR_RX3-</td><td></td><td>D27</td><td>10G_KR_TX3-</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td></td><td>B28</td><td>GND</td><td></td><td>C28</td><td>GND</td><td></td><td>D28</td><td>GND</td></tr><tr><td>A29</td><td>RSVD</td><td></td><td>B29</td><td>PCIE_CK_REF1+</td><td></td><td>C29</td><td>10G_KR_RX2+</td><td></td><td>D29</td><td>10G_KR_TX2+</td></tr><tr><td>A30</td><td>RSVD</td><td></td><td>B30</td><td>PCIE_CK_REF1-</td><td></td><td>C30</td><td>10G_KR_RX2-</td><td></td><td>D30</td><td>10G_KR_TX2-</td></tr><tr><td>A31</td><td>GND (fixed)</td><td></td><td>B31</td><td>GND (fixed)</td><td></td><td>C31</td><td>GND (fixed)</td><td></td><td>D31</td><td>GND (fixed)</td></tr><tr><td>A32</td><td>IPMB_CLK*</td><td></td><td>B32</td><td>SPKR</td><td></td><td>C32</td><td>RSVD10G</td><td></td><td>D32</td><td>RSVD10G / GP_SPI_CLK*</td></tr><tr><td>A33</td><td>IPMB_DAT*</td><td></td><td>B33</td><td>I2C_CK</td><td></td><td>C33</td><td>RSVD10G</td><td></td><td>D33</td><td>RSVD10G / GP_SPI_MOSI*</td></tr><tr><td>A34</td><td>BIOS_DIS0#</td><td></td><td>B34</td><td>I2C_DAT</td><td></td><td>C34</td><td>RSVD10G</td><td></td><td>D34</td><td>RSVD10G / GP_SPI_MISO*</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td></td><td>B35</td><td>THRM#</td><td></td><td>C35</td><td>CEI_RST#</td><td></td><td>D35</td><td>CEI_PRSNT#</td></tr><tr><td>A36</td><td>PCIE_TX13+</td><td></td><td>B36</td><td>PCIE_RX13+</td><td></td><td>C36</td><td>RSVD10G</td><td></td><td>D36</td><td>RSVD / GP_SPI_CS#*</td></tr><tr><td>A37</td><td>PCIE_TX13-</td><td></td><td>B37</td><td>PCIE_RX13-</td><td></td><td>C37</td><td>RSVD10G</td><td></td><td>D37</td><td>RSVD</td></tr><tr><td>A38</td><td>GND</td><td></td><td>B38</td><td>GND</td><td></td><td>C38</td><td>RSVD10G</td><td></td><td>D38</td><td>RSVD10G</td></tr><tr><td>A39</td><td>PCIE_TX12+</td><td></td><td>B39</td><td>PCIE_RX12+</td><td></td><td>C39</td><td>CEI_SDA</td><td></td><td>D39</td><td>CEI_SCL</td></tr><tr><td>A40</td><td>PCIE_TX12-</td><td></td><td>B40</td><td>PCIE_RX12-</td><td></td><td>C40</td><td>10G_SDP0*</td><td></td><td>D40</td><td>10G_SDP1*</td></tr><tr><td>A41</td><td>GND (fixed)</td><td></td><td>B41</td><td>GND (fixed)</td><td></td><td>C41</td><td>GND (fixed)</td><td></td><td>D41</td><td>GND (fixed)</td></tr><tr><td>A42</td><td>USB2-</td><td></td><td>B42</td><td>USB3-</td><td></td><td>C42</td><td>10G_KR_RX1+</td><td></td><td>D42</td><td>10G_KR_TX1+</td></tr><tr><td>A43</td><td>USB2+</td><td></td><td>B43</td><td>USB3+</td><td></td><td>C43</td><td>10G_KR_RX1-</td><td></td><td>D43</td><td>10G_KR_TX1-</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td></td><td>B44</td><td>USB_0_1_OC#</td><td></td><td>C44</td><td>GND</td><td></td><td>D44</td><td>GND</td></tr><tr><td>A45</td><td>USB0-</td><td></td><td>B45</td><td>USB1-</td><td></td><td>C45</td><td>RSVD10G / 10G_PHY_MDC_SCL1*</td><td></td><td>D45</td><td>RSVD10G / 10G_PHY_MDIO_SDA1*</td></tr><tr><td>A46</td><td>USB0+</td><td></td><td>B46</td><td>USB1+</td><td></td><td>C46</td><td>CEI_MDC</td><td></td><td>D46</td><td>CEI_MDIO</td></tr><tr><td>A47</td><td>VCC_RTC</td><td></td><td>B47</td><td>ESPI_EN#</td><td></td><td>C47</td><td>CEI_INT#</td><td></td><td>D47</td><td>ETH_PHY_INT#</td></tr><tr><td>A48</td><td>RSMRST_OUT#</td><td></td><td>B48</td><td>USB0_HOST_PRSNT</td><td></td><td>C48</td><td>GND</td><td></td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GBEO_SDP*</td><td></td><td>B49</td><td>SYS_RESET#</td><td></td><td>C49</td><td>10G_KR_RX0+</td><td></td><td>D49</td><td>10G_KR_TX0+</td></tr><tr><td>A50</td><td>LPC_SERIRQ</td><td></td><td>B50</td><td>CB_RESET#</td><td></td><td>C50</td><td>10G_KR_RX0-</td><td></td><td>D50</td><td>10G_KR_TX0-</td></tr><tr><td>A51</td><td>GND (fixed)</td><td></td><td>B51</td><td>GND (fixed)</td><td></td><td>C51</td><td>GND (fixed)</td><td></td><td>D51</td><td>GND (fixed)</td></tr><tr><td>A52</td><td>PCIE_TX5+</td><td></td><td>B52</td><td>PCIE_RX5+</td><td></td><td>C52</td><td>PCIE_RX16+</td><td></td><td>D52</td><td>PCIE_TX16+</td></tr><tr><td>A53</td><td>PCIE_TX5-</td><td></td><td>B53</td><td>PCIE_RX5-</td><td></td><td>C53</td><td>PCIE_RX16-</td><td></td><td>D53</td><td>PCIE_TX16-</td></tr><tr><td>A54</td><td>GPIO</td><td></td><td>B54</td><td>GPO1</td><td></td><td>C54</td><td>TYPE0#</td><td></td><td>D54</td><td>GND</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td></td><td>B55</td><td>PCIE_RX4+</td><td></td><td>C55</td><td>PCIE_RX17+</td><td></td><td>D55</td><td>PCIE_TX17+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td></td><td>B56</td><td>PCIE_RX4-</td><td></td><td>C56</td><td>PCIE_RX17-</td><td></td><td>D56</td><td>PCIE_TX17-</td></tr><tr><td>A57</td><td>GND</td><td></td><td>B57</td><td>GPO2</td><td></td><td>C57</td><td>TYPE1#</td><td></td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td></td><td>B58</td><td>PCIE_RX3+</td><td></td><td>C58</td><td>PCIE_RX18+</td><td></td><td>D58</td><td>PCIE_TX18+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td></td><td>B59</td><td>PCIE_RX3-</td><td></td><td>C59</td><td>PCIE_RX18-</td><td></td><td>D59</td><td>PCIE_TX18-</td></tr><tr><td>A60</td><td>GND (fixed)</td><td></td><td>B60</td><td>GND (fixed)</td><td></td><td>C60</td><td>GND (fixed)</td><td></td><td>D60</td><td>GND (fixed)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td></td><td>B61</td><td>PCIE_RX2+</td><td></td><td>C61</td><td>PCIE_RX19+</td><td></td><td>D61</td><td>PCIE_TX19+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td></td><td>B62</td><td>PCIE_RX2-</td><td></td><td>C62</td><td>PCIE_RX19-</td><td></td><td>D62</td><td>PCIE_TX19-</td></tr><tr><td>A63</td><td>GPIO1</td><td></td><td>B63</td><td>GPIO3</td><td></td><td>C63</td><td>GND</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td></td><td>B64</td><td>PCIE_RX1+</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>GND</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td></td><td>B65</td><td>PCIE_RX1-</td><td></td><td>C65</td><td>PCIE_RX20+</td><td></td><td>D65</td><td>PCIE_TX20+</td></tr><tr><td>A66</td><td>GND</td><td></td><td>B66</td><td>WAKE0#</td><td></td><td>C66</td><td>PCIE_RX20-</td><td></td><td>D66</td><td>PCIE_TX20-</td></tr><tr><td>A67</td><td>GPIO2</td><td></td><td>B67</td><td>WAKE1#</td><td></td><td>C67</td><td>RAPID_SHUTDOWN</td><td></td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td></td><td>B68</td><td>PCIE_RX0+</td><td></td><td>C68</td><td>PCIE_RX21+</td><td></td><td>D68</td><td>PCIE_TX21+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td></td><td>B69</td><td>PCIE_RX0-</td><td></td><td>C69</td><td>PCIE_RX21-</td><td></td><td>D69</td><td>PCIE_TX21-</td></tr><tr><td>A70</td><td>GND (fixed)</td><td></td><td>B70</td><td>GND (fixed)</td><td></td><td>C70</td><td>GND (fixed)</td><td></td><td>D70</td><td>GND (fixed)</td></tr><tr><td>A71</td><td>PCIE_TX8+</td><td></td><td>B71</td><td>PCIE_RX8+</td><td></td><td>C71</td><td>PCIE_RX22+</td><td></td><td>D71</td><td>PCIE_TX22+</td></tr><tr><td>A72</td><td>PCIE_TX8-</td><td></td><td>B72</td><td>PCIE_RX8-</td><td></td><td>C72</td><td>PCIE_RX22-</td><td></td><td>D72</td><td>PCIE_TX22-</td></tr><tr><td>A73</td><td>GND</td><td></td><td>B73</td><td>GND</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>PCIE_TX9+</td><td></td><td>B74</td><td>PCIE_RX9+</td><td></td><td>C74</td><td>PCIE_RX23+</td><td></td><td>D74</td><td>PCIE_TX23+</td></tr><tr><td>A75</td><td>PCIE_TX9-</td><td></td><td>B75</td><td>PCIE_RX9-</td><td></td><td>C75</td><td>PCIE_RX23-</td><td></td><td>D75</td><td>PCIE_TX23-</td></tr><tr><td>A76</td><td>GND</td><td></td><td>B76</td><td>GND</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>PCIE_TX10+</td><td></td><td>B77</td><td>PCIE_RX10+</td><td></td><td>C77</td><td>GND</td><td></td><td>D77</td><td>GND</td></tr><tr><td>A78</td><td>PCIE_TX10-</td><td></td><td>B78</td><td>PCIE_RX10-</td><td></td><td>C78</td><td>PCIE_RX24+</td><td></td><td>D78</td><td>PCIE_TX24+</td></tr><tr><td>A79</td><td>GND</td><td></td><td>B79</td><td>GND</td><td></td><td>C79</td><td>PCIE_RX24-</td><td></td><td>D79</td><td>PCIE_TX24-</td></tr><tr><td>A80</td><td>GND (fixed)</td><td></td><td>B80</td><td>GND (fixed)</td><td></td><td>C80</td><td>GND (fixed)</td><td></td><td>D80</td><td>GND (fixed)</td></tr><tr><td>A81</td><td>PCIE_TX11+</td><td></td><td>B81</td><td>PCIE_RX11+</td><td></td><td>C81</td><td>PCIE_RX25+</td><td></td><td>D81</td><td>PCIE_TX25</td></tr><tr><td>A82</td><td>PCIE_TX11-</td><td></td><td>B82</td><td>PCIE_RX11-</td><td></td><td>C82</td><td>PCIE_RX25-</td><td></td><td>D82</td><td>PCIE_TX25-</td></tr><tr><td>A83</td><td>GND</td><td></td><td>B83</td><td>GND</td><td></td><td>C83</td><td>GND</td><td></td><td>D83</td><td>GND</td></tr><tr><td>A84</td><td>NCSI_TX_EN</td><td></td><td>B84</td><td>VCC_5V_SBY</td><td></td><td>C84</td><td>GND</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3</td><td></td><td>B85</td><td>VCC_5V_SBY</td><td></td><td>C85</td><td>PCIE_RX26+</td><td></td><td>D85</td><td>PCIE_TX26+</td></tr><tr><td>A86</td><td>RSVD</td><td></td><td>B86</td><td>VCC_5V_SBY</td><td></td><td>C86</td><td>PCIE_RX26-</td><td></td><td>D86</td><td>PCIE_TX26-</td></tr><tr><td>A87</td><td>GND</td><td></td><td>B87</td><td>VCC_5V_SBY</td><td></td><td>C87</td><td>GND</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE0_CK_REF+</td><td></td><td>B88</td><td>BIOS_DIS1#</td><td></td><td>C88</td><td>PCIE_RX27+</td><td></td><td>D88</td><td>PCIE_TX27+</td></tr><tr><td>A89</td><td>PCIE0_CK_REF-</td><td></td><td>B89</td><td>NSCI_RX_ER</td><td></td><td>C89</td><td>PCIE_RX27-</td><td></td><td>D89</td><td>PCIE_TX27-</td></tr><tr><td>A90</td><td>GND (fixed)</td><td></td><td>B90</td><td>GND (fixed)</td><td></td><td>C90</td><td>GND (fixed)</td><td></td><td>D90</td><td>GND (fixed)</td></tr><tr><td>A91</td><td>SPI_POWER</td><td></td><td>B91</td><td>NCSI_CLK_IN</td><td></td><td>C91</td><td>PCIE_RX28+</td><td></td><td>D91</td><td>PCIE_TX28+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td></td><td>B92</td><td>NCSI_RXD1</td><td></td><td>C92</td><td>PCIE_RX28-</td><td></td><td>D92</td><td>PCIE_TX28-</td></tr><tr><td>A93</td><td>GPO0</td><td></td><td>B93</td><td>NCSI_RXD0</td><td></td><td>C93</td><td>GND</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td></td><td>B94</td><td>NCSI_CRS_DV</td><td></td><td>C94</td><td>PCIE_RX29+</td><td></td><td>D94</td><td>PCIE_TX29+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td></td><td>B95</td><td>NCSI_TXD1</td><td></td><td>C95</td><td>PCIE_RX29-</td><td></td><td>D95</td><td>PCIE_TX29-</td></tr><tr><td>A96</td><td>TPM_PP</td><td></td><td>B96</td><td>NCSI_TXD0</td><td></td><td>C96</td><td>GND</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td></td><td>B97</td><td>SPI_CS#</td><td></td><td>C97</td><td>GND</td><td></td><td>D97</td><td>GND</td></tr><tr><td>A98</td><td>SER0_TX</td><td></td><td>B98</td><td>NCSI_ARB_IN</td><td></td><td>C98</td><td>PCIE_RX30+</td><td></td><td>D98</td><td>PCIE_TX30+</td></tr><tr><td>A99</td><td>SER0_RX</td><td></td><td>B99</td><td>NCSI_ARB_OUT</td><td></td><td>C99</td><td>PCIE_RX30-</td><td></td><td>D99</td><td>PCIE_TX30-</td></tr><tr><td>A100</td><td>GND (fixed)</td><td></td><td>B100</td><td>GND (fixed)</td><td></td><td>C100</td><td>GND (fixed)</td><td></td><td>D100</td><td>GND (fixed)</td></tr><tr><td>A101</td><td>SER1_TX</td><td></td><td>B101</td><td>FAN_PWMOUT</td><td></td><td>C101</td><td>PCIE_RX31+</td><td></td><td>D101</td><td>PCIE_TX31+</td></tr><tr><td>A102</td><td>SER1_RX</td><td></td><td>B102</td><td>FAN_TACHIN</td><td></td><td>C102</td><td>PCIE_RX31-</td><td></td><td>D102</td><td>PCIE_TX31-</td></tr><tr><td>A103</td><td>LID#</td><td></td><td>B103</td><td>SLEEP#</td><td></td><td>C103</td><td>GND</td><td></td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td></td><td>B104</td><td>VCC_12V</td><td></td><td>C104</td><td>VCC_12V</td><td></td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td></td><td>B105</td><td>VCC_12V</td><td></td><td>C105</td><td>VCC_12V</td><td></td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td></td><td>B106</td><td>VCC_12V</td><td></td><td>C106</td><td>VCC_12V</td><td></td><td>D106</td><td>VCC_12V</td></tr><tr><td>A107</td><td>VCC_12V</td><td></td><td>B107</td><td>VCC_12V</td><td></td><td>C107</td><td>VCC_12V</td><td></td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td></td><td>B108</td><td>VCC_12V</td><td></td><td>C108</td><td>VCC_12V</td><td></td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td></td><td>B109</td><td>VCC_12V</td><td></td><td>C109</td><td>VCC_12V</td><td></td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND (fixed)</td><td></td><td>B110</td><td>GND (FIXED)</td><td></td><td>C110</td><td>GND (FIXED)</td><td></td><td>D110</td><td>GND (FIXED)</td></tr></table>

![The image displays a simple red icon on a white background. It depicts a square shape resembling a piece of paper with a folded bottom-right corner (a 'dog-ear'). Inside the outline are two horizontal red lines stacked vertically, centered within the shape.](.express-vr7-50m-72140-1000-01-240516/13fa9187d8ae57f2ebfb48f95d5701e4cadf672bb26b2f4e8236554f663cbb2f.jpg)

# Note:

1. 10G SFP+ or 10GBASE-T support is based on CEI mode (sideband signal arrangement related) and requires PHY (CS4227 or AQR113C) along with on-carrier firmware, for SFP+ or 10GBASE-T applications. A reference design will be offered. Please contact our ADLINK representative for availability.
2. Another PCIe clock (PCIE\_CK\_REF1) defined by PICMG COM.0 R3.1 can be used for PCIe lane 16-23. Check pin B29, B30.
3. Features listed below are supported by project basis (1) IPMB function (2) GBE0\_SDP with specific LAN controller (3) 10G\_SDP 0-3. (4) GP\_SPI, general purpose SPI. (5) Additional MDC/MDIO (10G\_PHY\_MDC\_SCL1, 10G\_PHY\_MDIO\_SDA1). All these project basis support features are still in development stage.

# 4.2. Signal Terminology Descriptions

Meaning of the terms used for signal description tables

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional Input / Output</td></tr><tr><td>OD</td><td>Open drain output from the module</td></tr><tr><td></td><td></td></tr><tr><td>I 3.3V</td><td>Input 3.3V tolerant</td></tr><tr><td>I 5V</td><td>Input 5V tolerant</td></tr><tr><td>O 3.3V</td><td>Output 3.3V signal level</td></tr><tr><td>O 5V</td><td>Output 5V signal level</td></tr><tr><td>I/O 3.3V</td><td>Bi-directional signal 3.3V tolerant</td></tr><tr><td>I/O 5V</td><td>Bi-directional signal 5V tolerant</td></tr><tr><td>I/O  $3.3V_{SB}$ </td><td>Input or output 3.3V tolerant active in standby state</td></tr><tr><td></td><td></td></tr><tr><td>DDC</td><td>Display Data Channel</td></tr><tr><td>PCIE</td><td>PCI Express compatible differential signal</td></tr><tr><td>PEG</td><td>PCI Express Graphics</td></tr><tr><td>SATA</td><td>Serial ATA specification Revision 2.6 and 3</td></tr><tr><td>LVDS</td><td>Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal</td></tr><tr><td></td><td></td></tr><tr><td>P</td><td>Power Input / Output</td></tr><tr><td>REF</td><td>Reference voltage output. May be sourced from a Module power plane.</td></tr><tr><td>PDS</td><td>Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.</td></tr><tr><td></td><td></td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr></table>

# 4.3. AB Connector Signal Descriptions

4.3.1 Network Controller Sideband Interface (NC-SI)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>NCSI_CLK_IN</td><td>B91</td><td>Clock reference for receive, transmit and control interface</td><td>I-3.3VSB</td><td>PD-10K</td><td>Not supported</td></tr><tr><td rowspan="2">NCSI_RXD[1:0]</td><td>B92</td><td rowspan="2">Receive Data (from NC to BMC)</td><td rowspan="2">∅3.3VSB</td><td rowspan="2">PU-10K3.3VSB</td><td rowspan="2">Not supported</td></tr><tr><td>B93</td></tr><tr><td rowspan="2">NCSI_TXD[1:0]</td><td>B95</td><td rowspan="2">Transmit Data (from BMC to NC)</td><td rowspan="2">I-3.3VSB</td><td rowspan="2">PU-10K3.3VSB</td><td rowspan="2">Not supported</td></tr><tr><td>B96</td></tr><tr><td>NCSI_CRS_DV</td><td>B94</td><td>Carrier Sense/Receive Data valid to MC, indicating that the transmitted data from NC to BMC is valid</td><td>∅3.3VSB</td><td>PD-10K</td><td>Not supported</td></tr><tr><td>NCSI_TX_EN</td><td>A84</td><td>Transmit enable</td><td>I-3.3VSB</td><td>PD-10K</td><td>Not supported</td></tr><tr><td>NCSI_RX_ER</td><td>B89</td><td>Receive error</td><td>∅3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>NCSI_ARB_IN</td><td>B98</td><td>Network Controller hardware arbitration input</td><td>I-3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>NCSI_ARB_OUT</td><td>B99</td><td>Network Controller hardware arbitration output</td><td>∅3.3VSB</td><td></td><td>Not supported</td></tr></table>

4.3.2 Gigabit Ethernet

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GBE0_MD10+</td><td>A13</td><td rowspan="3">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="8">I/O Analog</td><td rowspan="8"></td><td rowspan="8">Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_MD10-</td><td>A12</td></tr><tr><td>GBE0_MD11+</td><td>A10</td></tr><tr><td>GBE0_MD11-</td><td>A9</td><td>1000 100 10</td></tr><tr><td>GBE0_MD12+</td><td>A7</td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td></tr><tr><td>GBE0_MD12-</td><td>A6</td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td></tr><tr><td>GBE0_MD13+</td><td>A3</td><td>MDI[2]+/- B1_DC+/-</td></tr><tr><td>GBE0_MD13-</td><td>A2</td><td>MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td>Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td>Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK_MID#</td><td>A4</td><td>Gigabit Ethernet Controller MID Speed Link indicator. Active low. If active, the link is established but at a speed lower than the maximum speed supported by the Ethernet controller. Note that based on capabilities of the Ethernet controller used this signal might not be active for all possible lower link speeds. Was GBE0_LINK100# in COM Express Rev. 3.0.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK_MAX#</td><td>A5</td><td>Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.Gigabit Ethernet Controller MAX Speed Link Indicator. Active low. If active, the link is established at the maximum link speed supported by the controller. Was GBE0_LINK1000# in COM Express Rev. 3.0.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td>Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>REFGND min3.3V max</td><td></td><td>Not supported</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td>Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.</td><td>IO 3.3VSB</td><td></td><td>Depends on the selection of LAN controller, project basis</td></tr></table>

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Note: GBE0\_ACT# and GBE0\_LINK# share the same pin from LAN controller.

4.3.3 SATA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

4.3.3.1. I/O Assignments

<table><tr><td>Name</td><td>Physical Lane on CPU</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>SATA0</td><td>Lane 10</td><td></td></tr><tr><td>SATA1</td><td>Lane 11</td><td></td></tr></table>

4.3.4 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX4+PCIE_TX4-</td><td>A55A56</td><td>PCI Express channel 4, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX4+PCIE_RX4-</td><td>B55B56</td><td>PCI Express channel 4, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX5+PCIE_TX5-</td><td>A52A53</td><td>PCI Express channel 5, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX5+PCIE_RX5-</td><td>B52B53</td><td>PCI Express channel 5, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX8+PCIE_TX8-</td><td>A71A72</td><td>PCI Express channel 8, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX8+PCIE_RX8-</td><td>B71B72</td><td>PCI Express channel 8, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX9+PCIE_TX9-</td><td>A74A75</td><td>PCI Express channel 9, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX9+PCIE_RX9-</td><td>B74B75</td><td>PCI Express channel 9,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX10+PCIE_TX10-</td><td>A77A78</td><td>PCI Express channel 10,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX10+PCIE_RX10-</td><td>B77B78</td><td>PCI Express channel 10,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX11+PCIE_TX11-</td><td>A81A82</td><td>PCI Express channel 11,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX11+PCIE_RX11-</td><td>B81B82</td><td>PCI Express channel 11,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX12+PCIE_TX12-</td><td>A39A40</td><td>PCI Express channel 12,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX12+PCIE_RX12-</td><td>B39B40</td><td>PCI Express channel 12,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX13+PCIE_TX13-</td><td>A36A37</td><td>PCI Express channel 13,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX13+PCIE_RX13-</td><td>B36B37</td><td>PCI Express channel 13,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX14+PCIE_TX14-</td><td>A25A26</td><td>PCI Express channel 14,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX14+PCIE_RX14-</td><td>B25B26</td><td>PCI Express channel 14,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX15+PCIE_TX15-</td><td>A22A23</td><td>PCI Express channel 15,Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX15+PCIE_RX15-</td><td>B22B23</td><td>PCI Express channel 15,Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O-PCIE</td><td></td><td></td></tr><tr><td>PCIE_CLK_REF1+PCIE_CLK_REF1-</td><td>B29B30</td><td>Second reference clock output for higher speed PCI Express implementation on Lanes 16 to 31,for Type 7 implementations only</td><td>O-PCIE</td><td></td><td></td></tr></table>

Note: Both of PCIE\_CLK\_REF1 and PCIE\_CLK\_REF can be used for PCIe lane 16-23 but PCIE\_CLK\_REF1 preferred

PCI Express lane configuration as below

<table><tr><td rowspan="2">Connector</td><td rowspan="2">PCIe Lanes #</td><td colspan="2">Ref. Clk #</td><td rowspan="2" colspan="3">Preferred Link Configurations</td></tr><tr><td>Preferred</td><td>Optional</td></tr><tr><td rowspan="6">A / B</td><td>0</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td>x1</td><td rowspan="2">x2</td><td rowspan="4">x4</td></tr><tr><td>1</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td>x1*</td></tr><tr><td>2</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td>x1*</td><td rowspan="2">x2*</td></tr><tr><td>3</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td>x1*</td></tr><tr><td>4</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td>x1</td><td rowspan="2">x2</td><td></td></tr><tr><td>5</td><td>Ref_0</td><td>Ref_0 / Ref_1</td><td></td><td></td></tr><tr><td rowspan="8">C / D</td><td>16</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td>x1</td><td rowspan="2">x2</td><td rowspan="4">x4</td></tr><tr><td>17</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td></tr><tr><td>18</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td><td></td></tr><tr><td>19</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td><td></td></tr><tr><td>20</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td>x1</td><td rowspan="2">x2</td><td rowspan="4">x4</td></tr><tr><td>21</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td></tr><tr><td>22</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td><td></td></tr><tr><td>23</td><td>Ref_1</td><td>Ref_0 / Ref_1</td><td></td><td></td></tr></table>

![A red icon of a document with a curled bottom-right corner, featuring two horizontal lines inside.](.express-vr7-50m-72140-1000-01-240516/0fcb428c16f45e13501e7699bfd20f4bc0eef59414201a2f8f0bce9f2e1f990b.jpg)

Note: PCIe Lane 1, 2, 3 can be used as x1 but requires prior inquiries. PCIe Lane 2-3 can be used as one x2 but requires prior inquiries

4.3.4.1. I/O Assignments

<table><tr><td>Name</td><td>Physical Lane on CPU</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>PCIE0</td><td>Lane 12</td><td></td></tr><tr><td>PCIE1</td><td>Lane 13</td><td></td></tr><tr><td>PCIE2</td><td>Lane 14</td><td></td></tr><tr><td>PCIE3</td><td>Lane 15</td><td></td></tr><tr><td>PCIE4</td><td>Lane 16</td><td></td></tr><tr><td>PCIE5</td><td>Lane 17</td><td></td></tr><tr><td>PCIE16</td><td>Lane 7</td><td></td></tr><tr><td>PCIE17</td><td>Lane 6</td><td></td></tr><tr><td>PCIE18</td><td>Lane 5</td><td></td></tr><tr><td>PCIE19</td><td>Lane 4</td><td></td></tr><tr><td>PCIE20</td><td>Lane 3</td><td></td></tr><tr><td>PCIE21</td><td>Lane 2</td><td></td></tr><tr><td>PCIE22</td><td>Lane 1</td><td></td></tr><tr><td>PCIE23</td><td>Lane 0</td><td></td></tr></table>

4.3.5 LPC Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LPC_AD0</td><td>B4</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_AD1</td><td>B5</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD2</td><td>B6</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD3</td><td>B7</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_DRQ0#</td><td>B8</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>Not supported</td></tr><tr><td>LPC_DRQ1#</td><td>B9</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O 3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3VSB</td><td></td><td>The LPC_CLK frequency is 24MHz on this platform</td></tr></table>

4.3.6 USB

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 2</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr></table>

![The image displays a red icon resembling a document or memo. It features a thick red outline of a piece of paper with a folded bottom-right corner. Inside the outline, two horizontal red lines are centered, representing text lines.](.express-vr7-50m-72140-1000-01-240516/597691f00d57688df361eee70efc88a29e8a59dc3fb158f61c621fbd2eb5cf33.jpg)
\*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

4.3.7 SPI Bus (BIOS only)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>O P 3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not connected</td></tr></table>

4.3.8 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the &quot;speaker&quot; in PC-AT systems</td><td>O 3.3V</td><td>PU 10K3.3V</td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>THRMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan&#x27;s RPM.</td><td>O OD 3.3V</td><td></td><td>There shall be PD on carrier board</td></tr><tr><td>FAN_TACHIN</td><td>B102</td><td>Fan tachometer input for a fan with a two-pulse output.</td><td>I OD 3.3V</td><td>PU 47K 3.3V</td><td></td></tr><tr><td>TPM_PP</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100K</td><td>PD only when TPM on module. Modules implementing a TPM shall pull down Not Supported</td></tr></table>

4.3.9 SMBus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td>Equivalent resistor is 2.2K</td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td>Equivalent resistor is 2.2K</td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr></table>

![The image displays a red icon on a white background. It depicts a stylized document or memo pad outline with a folded bottom-right corner. Inside the main rectangular area of the document, there are two horizontal red lines centered within the shape. There is no text in the image.](.express-vr7-50m-72140-1000-01-240516/f54abb18d06f9b6aeb1baf25825d4702efeead9a6e1d5ce546be0c8a8e12579c.jpg)
Note: SMBus source from SoC’s SMBus is default setting. SMBus source from EC is by build option supported by project basis.

4.3.10 I2C Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td></td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td></td></tr></table>

![The image displays a red icon representing a document or file against a white background. The icon is shaped like a piece of paper with a folded top-right corner. Inside the red border, two horizontal red lines are centered, suggesting text content. There is no text present in the image.](.express-vr7-50m-72140-1000-01-240516/299c82d41deedf47eb0d3a61a1cc570c3595e127b6e097df9288c07b6d45030d.jpg)
Note: I2C source from EC is default setting. I2C source from SoC’s I2C is by build option supported by project basis.

4.3.11 General Purpose I/O (GPIO)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

![The image displays a simple icon featuring a white rectangle with a folded top-right corner (a 'dog-ear'), outlined in red. Inside the shape, centered vertically, are two horizontal red bars stacked one above the other. There is no text present in the image.](.express-vr7-50m-72140-1000-01-240516/2ba2f0894e0407cddb5d559a4ac537532c8c1451bb9761aa6fcc5645a284a0fe.jpg)
Note: GPI/GPO source from EC is default setting. GPI/GPO source from SoC’s GPIOs is by build option supported by project basis.

4.3.12 Serial Interface Signals

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SER0_TX</td><td>A98</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER0_RX</td><td>A99</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr></table>

![A red outline icon of a document. It depicts a white square with a red border, featuring a folded bottom-right corner and two horizontal red lines inside to represent text.](.express-vr7-50m-72140-1000-01-240516/0cfce3a29769c9f02eafc859fe767521b891d29e40a5435865c1c4d6678483aa.jpg)

Note: SER0, SER1 source from EC is default setting. SER0, SER1 source from SoC’s HSUART is by build option by supported by project basis. HSUART has driver support limitation.

4.3.13 IPMB (Optional)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>IPMB_CLK</td><td>A32</td><td>Clock I/O line for the multi-master IPMB port. If the IPMB interface is used, an additional lower value pull-up is located on the Carrier.</td><td>I/O OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td></td></tr><tr><td>IPMB_DAT</td><td>A33</td><td>Data I/O line for the multi-master IPMB port. If the IPMB interface is used, an additional lower value pull-up is located on the Carrier.</td><td>I/O OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td></td></tr></table>

![The image displays a red outline icon of a document or memo. The shape resembles a piece of paper with the bottom right corner folded upwards. Inside the outline, there are two horizontal lines representing text.](.express-vr7-50m-72140-1000-01-240516/4122debc94b01a2f992f26b0a436e1af8f64563ccbeb9ade91b032ae9aa25a8e.jpg)

Note: IPMB via a Module MMC is supported by project basis and it is still in development (TBC)

# 4.3.14

4.3.14 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Should have weak pull up.</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates imminent suspend operation; used to notify LPC devices.</td><td>O 3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as "PS_ON") may be used to enable the non-standby power on a typical ATX power supply.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates system is in Suspend to Disk state. Active low output.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates system is in Soft Off state.</td><td>O 3.3VSB</td><td></td><td>Connect to SUS_S4#</td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake up signal.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal used by the ACPI operating system for a LID switch.</td><td>I OD 3.3VSB</td><td></td><td></td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>I OD 3.3VSB</td><td></td><td></td></tr><tr><td>RAPID_SHUTDOWN</td><td>€67</td><td>Trigger for Rapid Shutdown. Must be driven to 5V though a &lt;=50-ohm source impedance for ≥20 μs.</td><td>LCMOS5VSB</td><td></td><td>Not supported</td></tr><tr><td>RSMRST_OUT</td><td>A48</td><td>USB devices that are to be powered in the S5 / S4 / S3 Suspend states should not have their 5V VBUS power enabled before RSMRST_OUT# transitions to the hi state.</td><td>O CMOS3.3VSB</td><td></td><td></td></tr></table>

4.3.15 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109</td><td>Primary power input supports wide range 5 – 20V input. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20V</td></tr><tr><td>VCC_5V_SBY</td><td>B84, B85, B86, B87</td><td>Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A38, A41, A51, A57, A60, A66, A70, A73, A76, A79, A80, A83, A87, A90, A100, A110, B1, B11, B21, B28, B31, B38, B41, B51, B60, B70, B73, B76, B79, B80, B83, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 4.4. CD Connector Signal Descriptions

4.4.1 USB 3.0 Extensions

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>C3C4</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>D3D4</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>C6C7</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>D6D7</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX2-USB_SSRX2+</td><td>C9C10</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX2-USB_SSTX2+</td><td>D9D10</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX3-USB_SSRX3+</td><td>C12C13</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX3-USB_SSTX3+</td><td>D12D13</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr></table>

4.4.2 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX6+PCIE_TX6-</td><td>D19D20</td><td>PCI Express channel 6, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX6+PCIE_RX6-</td><td>C19C20</td><td>PCI Express channel 6, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX7+PCIE_TX7-</td><td>D22D23</td><td>PCI Express channel 7, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX7+PCIE_RX7-</td><td>C22C23</td><td>PCI Express channel 7, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr></table>

4.4.3 10G-KR Ethernet

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>10G_KR_RX0+</td><td>C49</td><td>10GBASE-KR ports, Receive Input differential pairs</td><td>I KR</td><td></td><td>AC coupled on Module</td></tr><tr><td>10G_KR_RX0-</td><td>C50</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_RX1+</td><td>C42</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_RX1-</td><td>C43</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX0+</td><td>D49</td><td>10GBASE-KR ports, Transmit Output differential pairs</td><td>O KR</td><td></td><td>AC coupled on Carrier</td></tr><tr><td>10G_KR_TX0-</td><td>D50</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX1+</td><td>D42</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX1-</td><td>D43</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_RX2+</td><td>C29</td><td>10GBASE-KR ports, Receive Input differential pairs</td><td>I_KR</td><td></td><td>Not supported</td></tr><tr><td>10G_KR_RX2-</td><td>C30</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_RX3+</td><td>C26</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_RX3-</td><td>C27</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX2+</td><td>D29</td><td>10GBASE-KR ports, Transmit Output differential pairs</td><td>O_KR</td><td></td><td>Not supported</td></tr><tr><td>10G_KR_TX2-</td><td>D30</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX3+</td><td>D26</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_KR_TX3-</td><td>D27</td><td></td><td></td><td></td><td></td></tr><tr><td>CEI_INT#</td><td>C47</td><td>Active low interrupt input to Module from Carrier based I2C I/O expander</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>CEI_MDIO</td><td>D46</td><td>MDIO data - for PHY setup</td><td>I/O 3.3VSB</td><td>PU 1K 3.3VSB</td><td>TBD, it will be fine tune during development stage</td></tr><tr><td>CEI_MDC</td><td>C46</td><td>MDIO clock - for PHY setup</td><td>O 3.3VSB</td><td>PU 1K 3.3VSB</td><td>TBD, it will be fine tune during development stage</td></tr><tr><td>10G_SDP0</td><td>C40</td><td>Software-Definable Pins</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>10G_SDP1</td><td>D40</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_SDP2</td><td>C17</td><td></td><td></td><td></td><td></td></tr><tr><td>10G_SDP3</td><td>D17</td><td></td><td></td><td></td><td></td></tr><tr><td>CEI_SDA</td><td>C39</td><td>I2C data – for SFP setup, serialized status LEDs and miscellaneous serialized signals</td><td>I/O OD 3.3VSB</td><td>PU 10K 3.3VSB</td><td>TBD, it will be fine tune during development stage</td></tr><tr><td>CEI_SCL</td><td>D39</td><td>I2C clock for CEI I2C port</td><td>O OD 3.3VSB</td><td>PU 10K 3.3VSB</td><td>TBD, it will be fine tune during development stage</td></tr><tr><td>CEI_RST#</td><td>C35</td><td>Active low reset output from Module to Carrier based I/O expander</td><td>O 3.3VSB</td><td>PD 10K</td><td></td></tr><tr><td>CEI_PRSNT#</td><td>D35</td><td>Input signal from Carrier indicating presence of CEI compliant hardware on the Carrier</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>ETH_PHY_INT#</td><td>D47</td><td>Second active low interrupt input to Module from Carrier based I2C I/O expander</td><td>I 3.3VSB</td><td>PU 2K 3.3VSB</td><td></td></tr></table>

Several RSVD10G pins listed on pin-out summary table should be left not connected

![The image features a red icon resembling a document or piece of paper with a folded bottom-right corner. Inside the white area, there are two horizontal red lines centered vertically.](.express-vr7-50m-72140-1000-01-240516/2395580d5ca3981cb550050e831fef18e86835258e399503b2836b719db36a3f.jpg)
Note: Please contact our local ADLINK representative for information below. (1) Detailed information about circuit design between the Ethernet controller, Optical Fiber/Copper PHY and firmware. (2) Additional MDC/MDIO is offered for specific use case based on 10GBASE-T, by project basis. (3) SGMII offering for specific use case and by project basis. (4) 10G\_SDP support is by project basis.

4.4.4 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX16+PCIE_TX16-</td><td>D52D53</td><td>PCI Express channel 16, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX16+PCIE_RX16-</td><td>C52C53</td><td>PCI Express channel 16, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX17+PCIE_TX17-</td><td>D55D56</td><td>PCI Express channel 17, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX17+PCIE_RX17-</td><td>C55C56</td><td>PCI Express channel 17, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX18+PCIE_TX18-</td><td>D58D59</td><td>PCI Express channel 18, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX18+PCIE_RX18-</td><td>C58C59</td><td>PCI Express channel 18, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX19+PCIE_TX19-</td><td>D61D62</td><td>PCI Express channel 19, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX19+PCIE_RX19-</td><td>C61C62</td><td>PCI Express channel 19, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX20+PCIE_TX20-</td><td>D65D66</td><td>PCI Express channel 20, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX20+PCIE_RX20-</td><td>C65C66</td><td>PCI Express channel 20, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX21+PCIE_TX21-</td><td>D68D69</td><td>PCI Express channel 21, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX21+PCIE_RX21-</td><td>C68C69</td><td>PCI Express channel 21, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX22+PCIE_TX22-</td><td>D71D72</td><td>PCI Express channel 22, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX22+PCIE_RX22-</td><td>C71C72</td><td>PCI Express channel 22, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX23+PCIE_TX23-</td><td>D74D75</td><td>PCI Express channel 23, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX23+PCIE_RX23-</td><td>C74C75</td><td>PCI Express channel 23, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX24+PCIE_TX24-</td><td>D78D79</td><td>PCI Express channel 24, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX24+PCIE_RX24-</td><td>C78C79</td><td>PCI Express channel 24, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX25+PCIE_TX25-</td><td>D81D82</td><td>PCI Express channel 25, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX25+PCIE_RX25-</td><td>C81C82</td><td>PCI Express channel 25, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX26+PCIE_TX26-</td><td>D85D86</td><td>PCI Express channel 26, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX26+PCIE_RX26-</td><td>C85C86</td><td>PCI Express channel 26, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX27+PCIE_TX27-</td><td>D88D89</td><td>PCI Express channel 27, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX27+PCIE_RX27-</td><td>C88C89</td><td>PCI Express channel 27, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX28+PCIE_TX28-</td><td>D91D92</td><td>PCI Express channel 28, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX28+PCIE_RX28-</td><td>C91C92</td><td>PCI Express channel 28, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX29+PCIE_TX29-</td><td>D94D95</td><td>PCI Express channel 29, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX29+PCIE_RX29-</td><td>C94C95</td><td>PCI Express channel 29, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX30+PCIE_TX30-</td><td>D98D99</td><td>PCI Express channel 30, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX30+PCIE_RX30-</td><td>C98C99</td><td>PCI Express channel 30, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_TX31+PCIE_TX31-</td><td>D101D102</td><td>PCI Express channel 31, Transmit Output differential pair.</td><td>O-PCIE</td><td></td><td>Not supported</td></tr><tr><td>PCIE_RX31+PCIE_RX31-</td><td>C101C102</td><td>PCI Express channel 31, Receive Input differential pair.</td><td>I-PCIE</td><td></td><td>Not supported</td></tr></table>

![The image shows a red line-art icon representing a document or page. It features a rounded rectangular outline with the top-right corner folded down. Inside the outline, there are two horizontal red lines centered horizontally, resembling text or a list. There is no text in the image.](.express-vr7-50m-72140-1000-01-240516/42372d6d1a3ff0846acfd11b5994bad0d4217ee347bf0b8a6beb1a5b3feb3815.jpg)

Note: Both of PCIE\_CLK\_REF1 and PCIE\_CLK\_REF can be used for PCIe lane 16-23 but PCIE\_CLK\_REF1 preferred.

# 4.4.4.1. I/O Assignments

Please refer to 4.3.4.1

4.4.5 GP\_SPI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GP_SPI_CS#</td><td>D36</td><td>Chip select from Module SPI Master to Carrier SPI Slave</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>GP_SPI_MISO</td><td>D34</td><td>Data in to Module SPI Master from Carrier SPI Slave “Master In Slave Out”</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>GP_SPI_MOSI</td><td>D33</td><td>Data out from Module SPI Master to Carrier SPI Slave “Master Out Slave In”</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>GP_SPI_CLK</td><td>D32</td><td>Clock from Module SPI Master to Carrier SPI Slave</td><td>O 3.3VSB</td><td></td><td></td></tr></table>

![The image displays a simple, flat icon representing a document or memo pad. It features a thick red outline forming a square shape with rounded corners. The bottom right corner is curled upward, resembling a page. Inside the red border, there are two horizontal red lines centered in the upper portion, simulating text lines on the page. The background is white.](.express-vr7-50m-72140-1000-01-240516/6bb97a88ba27740d07bc7fc48d7f050ffa96d913bfb6c87598fc63051f1c521f.jpg)
Note: GP\_SPI supported by project basis

# 4.4.6

4.4.6 Module Type Definition

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TYPE0#</td><td>C54</td><td rowspan="3">The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC).</td><td rowspan="3"></td><td rowspan="3"></td><td rowspan="3">Type 7</td></tr><tr><td>TYPE1#</td><td>C57</td></tr><tr><td>TYPE2#</td><td>D57</td></tr><tr><td></td><td></td><td>For Pin-out Type 1 and Type 10 that lack a CD connector, these pins are not present (X)</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>TYPE2# TYPE1# TYPE0#</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>X X X Pinout Type 1</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>X X X Pinout Type 10</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC NC NC Pinout Type 2</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC NC GND Pinout Type 3</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC GND NC Pinout Type 4</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC GND GND Pinout Type 5</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>GND NC NC Pinout Type 6</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>GND NC GND Pinout Type 7</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>The Carrier Boardshouldimplement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.</td><td></td><td></td><td></td></tr><tr><td>TYPE10#</td><td>A97</td><td>In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.</td><td></td><td></td><td>No PD</td></tr></table>

4.4.7 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109</td><td>Primary power input supports wide range 5~20V input. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20V</td></tr><tr><td>GND</td><td>C1, C2, C5, C8, C11, C14, C18, C21, C25, C28, C31, C41, C44, C48, C51, C60, C63, C64, C70, C73, C76, C77, C80, C83, C84, C87, C90, C93, C96, C97, C100, C103, C110, D1, D2, D5, D8, D11, D14, D18, D21, D25, D28, D31, D41, D44, D48, D51, D54, D60, D63, D64, D67, D70, D73, D76, D77, D80, D83, D84, D87, D90, D93, D96, D97, D100, D103, D110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are shown below:

![40-pin Debug\nConnector\nStatus\nLEDs\nFan\n12V\nBIOS Default\nReset Button\nBIOS Boot\nSelect](.express-vr7-50m-72140-1000-01-240516/798a5ad84be445f32441831e9de07a4041c1899a2a82c3ccddad1afa08347bde.jpg)

Figure 3 – Module feature locations

# 5.1. Debug Connector

This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module:

 Test points measurement of internal power rails
 I2C bus for BIOS POST code readout
 SPI BIOS programming interface
 Embedded Controller programming interface

The debug board for Express-VR7 usage is DB40-HPC

![Two electronic circuit boards: one with ADLINK chip and COM Express, the other with ADLINK DB40-HPC connector and cable (no readable text or symbols)](.express-vr7-50m-72140-1000-01-240516/4e8310bf0742ca8676475b8efb318f07c671514722024509f35fbeb220238b7e.jpg)

Figure 4 – Express-VR7 and Debug Module

# 5.2. Status LEDs

Status LED’s are mounted on the module to facilitate easier maintenance.

LED3 LED2 LED1

![The image displays a series of horizontal red lines of varying lengths stacked vertically against a white background. There is no text present.](.express-vr7-50m-72140-1000-01-240516/ff66e26e54452f587f5716c5ccc88a42d3c5ca006597dc70431222ef1b7d4efe.jpg)

![Close-up of a green printed circuit board with electronic components and a circular component (no readable text or symbols)](.express-vr7-50m-72140-1000-01-240516/5a445ce7a9f989c60ce7e59056495739d24a80dcfa73d24a73d1c8e5a5176348.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC output</td><td>Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>BMC output and same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: Only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

# 5.3. Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>7</td><td>RESET_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr></table>

# 5.4. Fan Connector

Connector type: JVE 24W1125A-04M00

![4321\nFAN1\n+\nSW1](.express-vr7-50m-72140-1000-01-240516/11a4cf436b602294abcc905e218e4c08c93c1acebdc23945244d57b64ba84928.jpg)

<table><tr><td>Name</td><td>Description</td></tr><tr><td colspan="2"></td></tr><tr><td>1</td><td>FAN_PWMOUT</td></tr><tr><td>2</td><td>FAN_TACHIN</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>12V</td></tr></table>

# 5.5. BIOS Default Reset Button

![The image displays a close-up view of a green printed circuit board (PCB). A red arrow points from the right towards a small, white rectangular component. Surrounding this central component are several small black surface-mount components, with some located above it and a larger black component to its right. Below the white component, there is a yellow circular ring and a small yellow dot.](.express-vr7-50m-72140-1000-01-240516/05aa45bd44eb29fe780633542a728f394cfbf30614ba6809ad924b5f82292d31.jpg)

To perform a hardware reset of BIOS default settings, perform the following steps:

1. Shut down the system.
2. Keep the BIOS Setup Defaults Reset Button pressed and boot up the system. You can release the button when the BIOS prompt screen appears
3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.express-vr7-50m-72140-1000-01-240516/c79eb1fc7e7d545d10ee90bbcd31b22a29889befb495cae24ca7cb7f9f52934d.jpg)

# 5.6. BIOS Boot Select

The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2.

Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.

In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (default)</td><td>On</td><td>-</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>-</td></tr><tr><td>Set BIOS to PICMG mode (default)</td><td>-</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode</td><td>-</td><td>Off</td></tr></table>

# 6. BIOS Checkpoints, Beep Codes

A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. The Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes. Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but the Aptio 5.x core can be configured to send checkpoints to a variety of sources. The Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware. A beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process.

![The image displays a red icon on a white background. It depicts a square shape with a folded top-right corner, resembling a document or file. Inside the red border, there are two horizontal red lines centered within the shape.](.express-vr7-50m-72140-1000-01-240516/70a47cfe034f3adf7131f3a8cd4d7d6c97458eba52c70f22823d33182f385f6e.jpg)

Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify the user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes

# Viewing Checkpoints

Checkpoints generated by the Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-on cards show the value of I/O port 80h on an LED display.

# Aptio V Checkpoint and Beep Codes

Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes

# 7. Software Support

# 7.1. Yocto Linux

https://github.com/ADLINK/meta-adlink-amd

# 7.2. Ubuntu 20.04.3 LTS

# 7.3. SEMA API

# 8. Mechanical and Thermal

All dimensions are shown in mm with a tolerance of +/- 0.25mm unless otherwise noted.

# 8.1. Module Dimensions – Top View

![| Dimension | Value |\n| --------- | ----- |\n| Top Left   | 95    |\n| Top Right | 91    |\n| Bottom Left | 75.57 |\n| Bottom Right | 26.56 |\n| Bottom Right | 46.25 |\n| Bottom Right | 72.17 |\n| Bottom Right | 80    |\n| Bottom Right | 121   |\n| Bottom Right | 125   |](.express-vr7-50m-72140-1000-01-240516/6290fc7ab4ea661929a9ef1081c18d1f4332f2a1597db0c112d7e21758c4d0d2.jpg)

8.2. Module Dimensions – Bottom View
![| Dimension | Value  |\n| --------- | ------ |\n| Top Left   | 95     |\n| Top Right  | 91     |\n| Bottom Left| 75.57  |\n| Bottom Right| 26.56 |\n| Bottom Right| 18   |\n| Bottom Right| 6    |\n| Bottom Right| 4    |\n| Bottom Right| 0    |](.express-vr7-50m-72140-1000-01-240516/4c74c06b66871938e521f96b7484a9c868bf89fcee9090df87634c7d95e700b2.jpg)

# 8.3. Module Dimensions – Side View

![9.4 ±0.25\n3.25 ±0.25\n2](.express-vr7-50m-72140-1000-01-240516/b7342a26f2988bd3b0aa22e632604d557cd79d3da21ce7ba6e84e446f7b1618f.jpg)

# 8.4. Height of Processor and Static Compressive Load

# Processor Height Tolerance

The tolerance of the processor height is one of the key factors to consider when designing your thermal solution, as illustrated below. Please contact our ADLINK representative for further details.

![Die\nDie\nSubstrate\nModule PCB\nh](.express-vr7-50m-72140-1000-01-240516/9699749a196e6ad18760c49cb773e2d609a7afd0fb63d8432fbf03ca4941dd3a.jpg)

<table><tr><td></td><td>Typical</td><td>Tolerance</td></tr><tr><td>h</td><td>1.28 mm</td><td>+/- 0.1mm</td></tr></table>

# Static Compressive Load

Another key factor to consider is the static compressive load. The Express-VR7 module exhibits a processor maximum pressure die of 40 lbf.

# 8.5. Thermal Solutions

8.5.1 HTS-B
![The image displays technical drawings of a mechanical assembly from six different perspectives.\n\n**Top Row:**\n*   **Left:** A side profile view showing vertical dimensions labeled '11' and '5'.\n*   **Center:** An isometric view of an assembly plate featuring a central square component and peripheral mounting pillars. A label reads 'M2.5*7pcs' pointing to one of the pillars.\n*   **Right:** An isometric view of a flat rectangular plate with mounting holes in the corners and small feet underneath.\n\n**Bottom Row:**\n*   **Left:** A top-down orthographic view. A horizontal dimension is labeled '95'. A vertical dimension on the left edge is partially cut off but shows the number '25'.\n*   **Center:** A side profile view showing the edge of the assembly.\n*   **Right:** A front-facing orthographic view with dimensions labeled '87' (width) and '117' (height). It features a central square cutout, two small circular holes, corner mounting holes, and a rectangular outline at the bottom.](.express-vr7-50m-72140-1000-01-240516/6f5dbb9b5a80f0ccc06bc2cbc17c0209a635ddc825c750651988b713db466652.jpg)

8.5.2 HTS-BT
![The image displays a technical drawing of a rectangular metal plate or heatsink component, presented in six different views (three in the top row, three in the bottom row).\n\n**Top Row:**\n*   **Left:** A side profile view (cross-section) showing dimensions **11** (total thickness) and **5** (inner block height).\n*   **Middle:** An isometric view of the top surface featuring mounting posts, with a callout label **M2.5*7pcs**.\n*   **Right:** An isometric view of the bottom surface.\n\n**Bottom Row:**\n*   **Left:** A front orthographic view. The horizontal width is dimensioned as **95**. A vertical dimension on the left edge reads **115** (partially obscured by the bottom frame).\n*   **Middle:** A side profile view (edge-on).\n*   **Right:** A back orthographic view showing a square cutout. The vertical height is **117** and the horizontal width is **87**.](.express-vr7-50m-72140-1000-01-240516/a2830f68a7e5ab921784a1471afede5e8996701ef98ba58f6493eb511377b36d.jpg)

# 8.5.3 THS-B

![18\n5](.express-vr7-50m-72140-1000-01-240516/5b0b7debdac716f6836a603ad7990cee9d5a7b545c7da14a5f044bca2276833b.jpg)

![M2.5*7pcs](.express-vr7-50m-72140-1000-01-240516/0c13f1ba0102a1b94f92a14cb79eecf59f61cf6b257837ca5b0bdfd198778855.jpg)

![3D rendering of a heat sink component with ribbed top and mounting base (no text or symbols)](.express-vr7-50m-72140-1000-01-240516/60bc56f023e5d5834a52f801f00569a7acf9dd7488c7a79e4554441e4b14d610.jpg)

![Pure geometric diagram of a rectangular grid with vertical stripes and dimension labels (125 and 95), no text or symbols present.](.express-vr7-50m-72140-1000-01-240516/5196b9deb7439937e4ab7007c8e87f8f5fef171927124ec68ab2c1f4c4773df8.jpg)

![Pure diagram of a vertical structure with no text, numbers, or symbols](.express-vr7-50m-72140-1000-01-240516/d5eb5be23af9af9e8e03802d7359cd67f81b5c16277095519896b38e2a76475d.jpg)

![Technical drawing of a rectangular frame with a central square and side holes, dimensioned as 87x87 (no text or symbols)](.express-vr7-50m-72140-1000-01-240516/cfff555081f9ec9d09726a847dada760215c89d4a4fa6f19bfc15605519979da.jpg)

8.5.4 THS-BT
![This image displays a technical drawing of a heatsink assembly, presenting six distinct views of the component arranged in two rows.\n\nThe top row features:\n*   **Top Left:** A side profile view with vertical dimension lines indicating a height of **18** and a thickness of **5**.\n*   **Top Center:** An isometric view of the mounting plate showing a central processor interface and mounting posts, with an arrow pointing to a post labeled '**M2.5*7pcs**'.\n*   **Top Right:** An isometric view of the finned heatsink block.\n\nThe bottom row features:\n*   **Bottom Left:** A front view of the heatsink fins with a height dimension of **125** and a width dimension of **95**.\n*   **Bottom Center:** A thin side profile view.\n*   **Bottom Right:** A rear view of the mounting plate showing mounting holes and a processor interface, with a height dimension of **117** and a width dimension of **87**.](.express-vr7-50m-72140-1000-01-240516/c71cbdcae390f0f7f429a4ad9ce645e85eda5627d99b6d72f926eb32841b4f63.jpg)

8.5.5 THSF-B
![37\n5](.express-vr7-50m-72140-1000-01-240516/9537762acdac0d696d6f68b3a6f41f396aa497b230385fae95692a234ab2f013.jpg)

![M2.5*7pcs](.express-vr7-50m-72140-1000-01-240516/2628ce976f3cd2dec01ee59e8bf94000b322ba93749cc97ed0f78a94701cae21.jpg)

![3D rendering of a heat sink with a black fan blade (no text or symbols)](.express-vr7-50m-72140-1000-01-240516/0163b982dd17671170556d25ab9e84372af9e66ea503957b5caeeed94602657f.jpg)

![Close-up of a black CPU fan blade mounted on a striped metal panel, with dimension annotations (125 and 95) shown for scale.](.express-vr7-50m-72140-1000-01-240516/626aea2069c65fd2522618ce0947fcd25f2badbb4496a451a5b3660183da80fb.jpg)

![Pure diagram of a vertical cabinet or elevator shaft without any text, labels, or symbols](.express-vr7-50m-72140-1000-01-240516/4b6d2409404993e53a495c937284887cda0ff761bf51a4e1cb3b159ca24f4a2c.jpg)

![117\n87](.express-vr7-50m-72140-1000-01-240516/6cb7deb56bf1320ab0a8a3c4e89d5d92805857b5eeb1fc33ec0e9d0a29de7f0d.jpg)

8.5.6 THSH-B
![This image displays a technical 3D model of a heatsink assembly from six different angles, arranged in a two-by-three grid.\n\n**Top Row:**\n*   **Left:** A side profile view showing vertical fins. Dimensions are marked as 37 (total height) and 5 (top section thickness). A label reads 'M2.5*7pcs' pointing to a mounting screw.\n*   **Center:** An isometric view showing the top plate with a central square cutout and corner mounting posts. The label 'M2.5*7pcs' points to a corner hole.\n*   **Right:** An isometric view focusing on the dense array of vertical cooling fins.\n\n**Bottom Row:**\n*   **Left:** A front view showing the full array of fins. Dimensions are marked as 125 (height) and 95 (width). Mounting holes are visible at the corners and sides.\n*   **Center:** A side profile view showing the thickness of the assembly.\n*   **Right:** A top-down plan view showing the mounting layout and central cutout. Dimensions are marked as 117 (height) and 87 (width).](.express-vr7-50m-72140-1000-01-240516/c9e09c3d230e10eb6b5ef1ac9c0b1c9ce202dc21b5115eebbd2dcc5382e92cef.jpg)

# 8.6. Board to Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5-mm receptacles are chosen, the carrier board should be free of components.

Tyco 3-1827253-6, Tyco 2357787-1

ept 401-51101-51, ept 401-51103-51

Foxconn QT002206-2141-3H, Foxconn QT5GB26-44703-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
• This connector can be used with 5-mm through-hole standoffs (SMT type).

Tyco 3-6318491-6, Tyco 2357798-1

ept 401-55101-51, ept 401-55103-51

Foxconn QT002206-4141-3H, Foxconn QT5GB26-74703-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
• This connector can be used with 8-mm through-hole standoffs (SMT type).

# Common Specifications

Current capacity: 0.5A per pin
Rated voltage: 50V AC
Insulation resistance: 100M or greater @ 500 VDC
Temperature rating: -40°C to 85°C
UL certification (ECBT2.E28476)
Copper alloy (contacts)
Housing: thermo-plastic molded compound (L.C.P.)

# 8.7. Mounting Method

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the 5-mm or 8-mm board-to-board connectors, there are also top and bottom mounting. In top mounting, the threaded standoffs are on the carrier board and the thermal solution is attached with through-hole standoffs. In bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

![| Component | Top Mounting with 5 mm connectors | Bottom Mounting with 5 mm connectors |\n| --- | --- | --- |\n| M2.5 : 18 mm with spring / washer | M2.5 : 18 mm with spring / washer | M2.5 : 18 mm with spring / washer |\n| 2 mm heatsprader with 9 mm through-hole standoffs | 9 mm through-hole standoffs | 9 mm through-hole standoffs |\n| COM Express Module ~ 2 mm | COM Express Module ~ 2 mm | COM Express Module ~ 2 mm |\n| 5 mm threaded standoff (DIP) | 5 mm threaded standoff (DIP) | 5 mm through hole standoff (SMT) |\n| Carrier Board ~ 2 mm | Carrier Board ~ 2 mm | Carrier Board ~ 2 mm |\n| M2.5 : 14 mm with spring / washer | M2.5 : 14 mm with spring / washer | M2.5 : 14 mm with spring / washer |\n| M2.5 : 18 mm with spring / washer | M2.5 : 18 mm with spring / washer | Bottom Mounting with 8 mm connectors |\n| 2 mm heatsprader with 9 mm through-hole standoffs | 9 mm through-hole standoffs | 9 mm heatsprader with 9 mm threaded standoffs |\n| COM Express Module ~ 2 mm | COM Express Module ~ 2 mm | COM Express Module ~ 2 mm |\n| 8 mm threaded standoff (DIP) | 8 mm threaded standoff (DIP) | 8 mm through hole standoff (SMT) |\n| Carrier Board ~ 2 mm | Carrier Board ~ 2 mm | Carrier Board ~ 2 mm |\n| M2.5 : 16 mm with spring / washer | M2.5 : 16 mm with spring / washer | Bottom Mounting with 8 mm connectors |](.express-vr7-50m-72140-1000-01-240516/2b6b8e1b29e9f9015887afc49270d103b5cda32bf4fe248d3685874952dcb42b.jpg)

# 8.8. Standoff Types

The standoffs available for top and bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type) P/N: 33-72000-0050
![Ø5.5\nØ2,8\n7\n5\n4.1](.express-vr7-50m-72140-1000-01-240516/c17767189e86e32b13bc7d3f89c9bd644c9ed83428b151eb7aaadbe2a0b06a6a.jpg)

5mm threaded standoff (DIP type) P/N: 33-72016-0050
![M2.5\nØ5.5\n7\n5\n4.1](.express-vr7-50m-72140-1000-01-240516/ff50bd996f48daf7140a25c118cf66075eb8f8e91cc32cd71c3e9517f8b06fb9.jpg)

8mm through-hole standoff (SMT type) P/N: 33-72000-0080
![Ø5,5\nØ2,6\n9,6\n8\n4,1](.express-vr7-50m-72140-1000-01-240516/efb08a439f352cc598801256a51618b5e7811a72589100656018c9d5535084dc.jpg)

8mm threaded standoff (DIP type) P/N: 33-72015-0050
![M2.5\nØ5.5\n10\n8\n5,7\n4.1](.express-vr7-50m-72140-1000-01-240516/e50daa0921b37d17aee19e8496edd0aab812307e2db5f25d79d6fcca48c1d41d.jpg)

# 8.9. Installation

Install a heat spreader or heat sink using the following instructions. The images below are for illustration purpose only.

1. Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.

![Close-up of hands holding a green printed circuit board with visible memory chips and connectors (no readable text or symbols)](.express-vr7-50m-72140-1000-01-240516/07517d9e127d2401ab3015b4a6135389578e0024f8eb52c4ed2085cd0784ae8c.jpg)

2. Remove the protective membranes from the thermal pads. All thermal pads have a protective membrane (module dependent)

![Close-up of a small electronic component with green textured surface being processed by tweezers (no visible text or symbols)](.express-vr7-50m-72140-1000-01-240516/5b95dad0a546ba1e0ba5c64b598937d94dfa8601c0d11ec810f254f1f1358446.jpg)

3. Assemble the heatsink onto the COM Express module. Use the 3x M2.5, L=6mm screws provided to fasten the heatsink to the module. The number of screw holes and screws are module dependent, picture below is for illustration only

![Close-up of a green printed circuit board with visible components and soldering tips (no text or symbols)](.express-vr7-50m-72140-1000-01-240516/de1d1dda9d50ae0d546fd20686642294f44944f165ece7f2d7c83873edfb408a.jpg)

![Four identical silver screws are arranged in a horizontal row on a plain white background. Each screw is oriented vertically with its rounded, knurled head facing upward.](.express-vr7-50m-72140-1000-01-240516/ac02d9e8d00d1e35d5ed3941b940403e4ef9568c23ac8038bd316b94a497858b.jpg)

4. Place the COM Express module and heatsink assembly onto the connectors on the carrier board as exemplified below.

![Close-up of a computer motherboard with a gloved hand installing or adjusting a heatsink component (no visible text or symbols)](.express-vr7-50m-72140-1000-01-240516/fe5d5cd282f797e15d429dee59bf84f540caeb6b0be5270138a7a5c2631d50db.jpg)

Then press down on the module until it is firmly seated on the carrier board.

5. Use the 5x M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.

![Close-up of a green printed circuit board with multiple electronic components and red circular annotations (no readable text or symbols)](.express-vr7-50m-72140-1000-01-240516/86a9a6a8ea50711b1ae5231cbe7ee0cf30fb5d3c30677e58b95ecca8bd9d0dfd.jpg)

![Five metallic screw fasteners arranged horizontally on a plain background (no text or symbols visible)](.express-vr7-50m-72140-1000-01-240516/6531bb70528895db07472e9c280e365906d660bf21636b8ac1c8647767828480.jpg)

6. If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.

![Close-up of a CPU board with a hexagonal heat sink and wiring, being handled by gloved hands (no visible text or symbols)](.express-vr7-50m-72140-1000-01-240516/86a5599d312ec3f5c1df9da2cade009c14616738d3c436291cb29476a802b226.jpg)
[🔗 Link to the original document](.express-vr7-50m-72140-1000-01-240516/express-vr7-50m-72140-1000-01-240516.pdf)