# High Speed Link System # Master-Slave Distributed Solution # User's Manual Manual Rev. 2.05 Revision Date: October 15, 2007 Part No: 50-12100-2040 ![The image displays a black circle containing the universal recycling symbol. The symbol consists of three white arrows arranged in a triangular, circular formation, with each arrowhead pointing to the tail of the next. The tail section of each arrow features three horizontal stripes.](.hsl-ai16ao2-m-vv-av-manual-4/b542efdac6f6ef08e1884ea63daba571116a7a59da9775c29c26599cb5183866.jpg) Recycled Paper Copyright 2007 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Trademarks NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK TECHNOLOGY INC. Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Getting Service from ADLINK Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance. # ADLINK TECHNOLOGY INC. Web Site: http://www.adlinktech.com Sales & Service: Service@adlinktech.com TEL: +886-2-82265877 FAX: +886-2-82265717 Address: 9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan Please email or FAX this completed service form for prompt and satisfactory service.
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Please give a detailed description of the problem(s): # Table of Contents # Table of Contents...... i # List of Tables...... iv # List of Figures ...... v # 1 Introducing HSL 1 1.1 The HSL System.... 1 Product Overview 2 Product Highlights 2 HSL Applications 5 1.2 HSL System Specifications.... 9 1.3 HSL Series Products 12 1.4 Technical Information 14 HSL Technology Introduction 14 HSL Terminology 19 System Configurations 20 Wiring 22 Networking Topology 24 I/O refreshing rate of an HSL system 25 Communication error handling 26 1.5 Software Support 27 # 2 HSL Master Controller 29 2.1 Board Overview 29 2.2 Specifications.... 30 PCI-7853/7854 Layout 31 PMC-7852/G Layout 32 2.3 Configuration 34 SW1 (PMC-7852/G only) 34 JP 1, 2, 3, 6 / JP 4, 5 (PMC-7852/G only) .... 34 2.4 PIN Assignment (female) 35 2.5 Software Architecture Description 36 Functional Block Diagram 36 2.6 Installation.... 37 Hardware Installation 37 Software Installation 37 # 3 HSL Slave Module.... 39 3.1 Slave I/O Module 40 Discrete I/O Module 40 Analog I/O Module 41 Motion Control 41 General Specifications 42 DIP Switch Setting: 44 Wiring Diagram 45 3.2 Terminal Base.... 51 General Description 51 Jumper Settings 52 HSL-TB32-MD Jumper Settings 53 Dimensions 54 3.3 HSL-HUB/Repeater 56 General Description 56 Jumper Setting 57 Dimensions 58 3.4 Managing Slave Index in an HSL Network 59 Before you proceed 59 Examples 61 # 4 HSL LinkMaster Utility.... 65 4.1 Software Installation.... 66 4.2 ADLINK HSL LinkMaster Utility 67 Launching the LinkMaster Utility 67 Before you proceed 67 LinkMaster Utility Introduction 68 HSL-DI16DO16 Utility 71 HSL-DI32 and HSL-DO32 Utility 72 HSL-DI8/HSL-DO8/HSL-DI4DO4 Utility 73 HSL-R8DI16 Utility 74 HSL-AI16AO2 Utility 75 HSL-4XMO Utility 76 # 5 HSL Function Library 77 5.1 List of Functions.... 77 5.2 Initialization and System Information 81 5.3 Timer Control 86 5.4 Discrete I/O 90 5.5 Analog I/O 99 5.6 Pulse Stretcher Function (HSL-DI16-UL Only) 105 # 6 How to Program with HSL Function Library...... 109 6.1 Programming with HSL DLL 109 DIO Operation 109 AI/O Operation 110 Motion Operation: 111 # Appendix A Scan Time Table 113 A.1 Full Duplex Mode 113 A.2 Half Duplex Mode 114 # Appendix B Mapping Table.... 115 B.1 Initialization and System Information 115 B.2 Timer Control 3 115 B.3 Discrete I/O 116 B.4 Analog I/O 116 # Appendix C HSL-AI16AO2 Calibration.... 117 C.1 Before you proceed 117 C.2 Calibrating the modules.... 118 # Appendix D HSL-HUB/Repeater Information...... 119 D.1 Recommended transfer rates, total extension distance, and number of installed HSL-HUB/Repeater.... 119 D.2 Scan time table 119 Full duplex/12 Mbps 119 Full duplex/6 Mbps 120 Full duplex/3 Mbps 120 Half duplex/12 Mbps 121 Half duplex/6 Mbps 121 # Warranty Policy.... 123 # List of Tables Table 1-1: Remote Operation 10 Table 1-2: Slave I/O modules 12 Table 1-3: Remote Motion modules 12 Table 1-4: Terminal Base 13 Table 1-5: Polling cycle time of HSL (Full Duplex Mode) ..... 25 # List of Figures Figure 1-1: HSL topology 2 Figure 1-2: Traditional distributed PLC architecture .... 5 Figure 1-3: Networking PLC....6 Figure 1-4: HSL as distributed PLC 7 Figure 1-5: Time-deterministic DAQ using HSL....8 Figure 1-6: HSL technology brief -1 14 Figure 1-7: HSL technology brief-2 15 Figure 1-8: HSL I/O polling cycle 17 Figure 1-9: Master-slave communication architecture .... 18 Figure 1-10: Multiple master cards in one IPC.... 20 Figure 1-11: HSL system layout example-serial wiring.... 21 Figure 1-12: HSL wiring – RS-422 with multi-drop.... 23 Figure 1-13: HSL networking topology – Serial 24 Figure 2-1: PCI-7854 front view 29 Figure 2-2: PCI-7853/7854 Layout.... 31 Figure 2-3: PMC-7852/G Layout.... 32 Figure 2-4: SW1 – Transmission Rate Setting.... 34 Figure 2-5: Top View of PMC-7852/G, for JP 1, 2, 3, 4, 5, 6 jumper settings. 34 Figure 2-6: Functional Block diagram of HSL master 36 Figure 5-1: Type 1....92 Figure 5-2: Type 2....92 Figure 5-3: Type 3.... 93 Figure 6-1: Programming Flow 109 # How to Use This Manual This manual helps you in configuring, installing, and using the HSL series products, and describes the functions and the operational theorem of the high-speed link technology. This manual is divided into the following chapters: Chapter 1 - HSL Introduction: Provides an overview of the HSL system, including the system features, specifications, and communication technology. Chapter 2 - HSL Master Controller: Presents detailed information on the HSL master. Chapter 3 - HSL Slave Module: Presents detailed information on the HSL slave modules. Chapter 4 - HSL LinkMaster Utility: Provides instructions on how to install and use the ADLINK LinkMaster utility for testing and debugging the slave modules. Chapter 5 - HSL Function Library: Presents the function library usage and syntax. Chapter 6 - Programming with HSL Function Library: Provides a broad concept and knowledge of how to implement the application with the HSL library. Appendix A - Scan Time Table: Presents the HSL cycle time based on different transmission speeds and modes. Appendix B - Mapping Table: Provides a comparison table between old and new functions. Appendix C - HSL-AI16AO2 Calibration: Outlines the calibration procedures for HSL-AI16AO2-M-VV and HSL-AI16AO2-M-AV. Appendix D - HSL-HUB/Repeater information: Presents the adding time information and extension limitations. # References Master board. HSL is a master-slave communication system. In host side, we call the control board as master board. Slave module. HSL is a master-slave communication system. In remote side, the slave module can connect a variety of sensors. Slave index. The basic unit in HSL system. One HSL slave module may occupy 1, 2 or 4 slave indexes. This depends on the design of slave modules. Full duplex. Data transmission and receiving at the same scanning time. Half duplex. Data transmission and receiving at the consecutive scanning time. HSL master controller. One HSL ASIC plays the role of master controller. For example, PCI-7853 has one on-board HSL ASIC; it can connect a maximum of 63 slave indexes. For convenient connection, the HSL master has two ports. Using the same technology, the PCI-7854 can connect a maximum 126 slave indexes and has four ports. ![HSL master controller\n2 ports inside\nHSL master controller](.hsl-ai16ao2-m-vv-av-manual-4/505095eb4988374fa08cf10013fa10450592801c585157163906c8dc98e847fa.jpg) Transmission speed. The data speed is between master board and slave modules. The unit is bit per second. # 1 Introducing HSL # 1.1 The HSL System The HSL is an innovative distributed I/O technology that enables time-deterministic scanning of thousands of I/O points in milliseconds using master-slave architecture. The HSL master board comes in PCI or PMC form factors. The PMC board is used in embedded controllers. By using commercial Ethernet cable with RJ-45 connector, you can easily set up the HSL slave modules as close as possible to the sensor devices, reducing wiring effort. Aside from the I/O modules, ADLINK provides the remote motion control module with 4-axis pulse train type. The HSL network suits a variety of machine-making applications as it integrates discrete I/O, analog I/O, thermocouple module, and motion control. This local network delivers rapid response time, time-deterministic scanning and multiple-axis control. With PMC module, you may also integrate the HSL network with embedded solution platforms. # The HSL system features: ▶ Distributed solution based on PC architecture or embedded platform ▶ Convenient wiring for remote distributed I/O modules, including discrete I/Os and analog I/Os ▶ Space-saving and discrete low-profile U-series form factor ▶ Hundreds of discrete I/O points ▶ Time-deterministic, fast scanning ▶ High-speed data acquisition ▶ Up to 120 axes of remote motion control with two HSL master controller of master board ▶ Motion control features point table management and motion script download to enhance execution efficiency # 1.1.1 Product Overview The illustration shows the basic HSL system topology. ![**System Architecture**\n\n**Top Section:**\n* **PCI Master Controller Board** has an arrow pointing to the **Host Computer**.\n* The flow continues to the **HSL-HUB/Repeater** and text reading **The other HSL Network**.\n\n**Middle Section:**\n* The flow continues to the **Motion Control Device** and then to the **Digital I/O Module**.\n\n**Bottom Section:**\n* The flow continues to the **Low Profile Digital I/O Module**.\n* Next to it is the **Relay Control Module**.\n* An arrow points from the path to the **Analog I/O Module**.\n\n**Callout:**\n* A bracket connects the **Digital I/O Module** to a box labeled **Terminal base for HSL**.](.hsl-ai16ao2-m-vv-av-manual-4/5dd413f4ed9ab3a6c284de360f666edc3f3938ba699ece721f2a523db4b458fc.jpg) Figure 1-1: HSL topology # 1.1.2 Product Highlights # High-speed performance With scanning speed as high as 1000 points per ms, it takes only 1.895 ms for an HSL master to scan all the discrete I/O points of slave modules under 6 Mbps. For example, a distributed control system with 63 slave I/O modules of HSL-DI16DO16-DB-NN with 2016 discrete I/O points can be scanned or updated within 1.895 ms. # Time-deterministic scanning The HSL master controller implements a deterministic time period when scanning all slave I/O modules. The total scanning cycle time is exactly proportional to the number of slave indexes. At 6 Mbps, every 30.33 $\mu$ s is added for another slave index. For an HSL system with 30 discrete I/O slave modules (where every discrete I/O module occupies one slave index), the scanning time period is precisely 30 X 30.33 $\mu$ s = 909.9 $\mu$ s. The scan time unit based on transmission rate is illustrated below.
3 Mbps6 Mbps12 Mbps
Full Duplex60.67 μs30.33 μs15.17 μs
Half Duplex118 μs59 μs29.5 μs
# Convenient wiring The HSL master controller connects to all slave I/O modules using Ethernet cables. This dramatically reduces the wiring costs and effort. With Ethernet cables, hundreds or even thousands of I/O data can transmitted between the HSL master and slave I/O modules. The HSL wiring is the easiest and most cost-effective solution to date. For low profile series, you can make the connection by direct wiring. # Multiple I/O points The PCI-7853 offers one HSL master controller while the PCI-7854 offers two HSL master controllers. For maximum installation, users can have eight PCI-7853 and PCI-7854 in one system. That means users can have 1512 slave indexes in HSL network system. If choosing all connected modules as HSL-DI16DO16-DB-NN, a total of 24,192 digital input and 24,192 digital output points are supported. For embedded solution, users can choose the PMC-7852/G. # Easy I/O expansion Expanding I/O points for centralized configuration requires more I/O boards and available PCI or ISA slots. Problems occur when system needs more I/O points while there are no available slot. In contrast with centralized configuration, the distributed I/O configuration eliminates this limitation of a centralized I/O configuration. With the HSL system, adding more I/O points only requires one more slave I/O module and an Ethernet cable for communication link. # Self-diagnostic function The HSL provides a self-diagnostic function that eliminates communication failures. This function continuously monitors the network status while a status register keeps the accumulated slave-no-response count for every individual slave I/O module. Also, the HSL system features the CRC12 to eliminate any communication error. # Modular design of slave I/O ADLINK offers a variety of slave module types Including the metal-cased M series, non-metal DB series, and U series for compact systems. The M and DB series require a terminal board for connection. Terminal boards act as carrier of slave I/O module with wiring function. The Ethernet port and screw terminal on the terminal boards make it easier to replace I/O modules without turning and wiring off the system. # Remote motion control compatibility ADLINK also offers remote motion control solution based on the HSL network Including the HSL-4XMO-CG-N/P and HSL-4XMO-CD-N/P that could connect up to four axes. The HSL-4XMO-CG-N/P features a general-type interface for use with stepper or linear motors, while the HSL-4XMO-CD-N/P has a D-sub interface. By using a transfer cable, you can connect to specific servo amplifier. You can easily make a distributed control application that includes discrete I/O, analog I/O, and remote motion control. # Easy to program Every HSL master card comes with 32 KB SRAM that carries all the I/O status information of the HSL system. The ASIC on the HSL master board communicates with all remote slave I/O modules at fixed scanning period and keeps the most updated I/O status information on the SRAM. You may read and write the data in the 32 KB SRAM on HSL master card through the PCI or PMC bus. You can easily read/write the most updated I/O information and never worry with the HSL protocol. # 1.1.3 HSL Applications # HSL as a Distributed PLC The distributed PLC is an important system in the field of industry automation. Via communication modules, such as RS232, RS485, PLC also performs distributed control. The traditional architecture of distributed PLC application is shown in Figure 1.2. In this setup, the MPC (Monitoring PC) takes over as the medium for data transmission from field to MIS. ![The diagram illustrates a network topology connecting computers to Programmable Logic Controllers (PLCs).\n\n**Blocks:**\n* **Network:** A horizontal bar at the top.\n* **MPC:** Two desktop computer setups (monitor and tower) below the network bar.\n* **PLC:** Five rectangular device blocks. Three are grouped under the left MPC, and two are grouped under the right MPC.\n\n**Connections:**\n* **Network:** Connects to the top of both **MPC** units.\n* **Left MPC:** Connects via a vertical line labeled **RS-485** to a bus line. This bus connects to three **PLC** blocks (one to the left, one above, and one below).\n* **Right MPC:** Connects via two separate lines, each labeled **RS232**, to two **PLC** blocks located below and to the right of the computer.](.hsl-ai16ao2-m-vv-av-manual-4/15a0cfef12f2be723c4a2b411cde6694010e09760b8e3b7975829bffca6503d5.jpg) Figure 1-2: Traditional distributed PLC architecture With the development of communication technology and popularity of networking, networking modules with Ethernet interface became available. This improvement evolved as shown in the architecture below. The medium character of the MPC was replaced. ![The diagram depicts a system architecture with three main sections:\n\n**Top Row (Computer Systems):**\nThree computer setups are shown, each consisting of a monitor and a tower. They are labeled:\n* **SCADA**\n* **Web Server**\n* **HMI**\n\n**Middle Section (Infrastructure):**\nA horizontal grey bar labeled **Network** runs beneath the computers. Vertical lines connect the SCADA, Web Server, and HMI units directly to this Network bus.\n\n**Bottom Row (Controllers):**\nFour separate blocks are arranged below the network. Each block is labeled **PLC**. Vertical lines extend from the Network bus down to connect to each of the four PLC units.](.hsl-ai16ao2-m-vv-av-manual-4/2da728b2c1e08b02d10b6c7171b0d9c996ff7657818f5b98a0c710c3ef7b2b1f.jpg) Figure 1-3: Networking PLC PLCs that are capable of network communications are usually very expansive. And since the PLC is not an open architecture, only hardware vendors are capable of producing it. The HSL distributed control architecture is illustrated in Figure 1.4. With HSL, there is no need for an extra PC for Ethernet communication. You may use only one IPC to control the entire system. ![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n* **IPC**: A large rectangular device on the right side.\n* **HSL Master**: A label pointing to a specific port or section on the top of the IPC.\n* **RJ45/10BaseT**: A label above a horizontal line connecting multiple devices.\n* **Slave I/O Module**: A label with arrows pointing to the smaller rectangular devices.\n\n**Connections:**\n* A long horizontal grey bar at the top connects vertically to the top of the **IPC**.\n* The **IPC** connects horizontally to the left side of a line labeled **RJ45/10BaseT**.\n* Three vertical lines drop down from the **RJ45/10BaseT** line, connecting to three identical **Slave I/O Module** blocks.\n* A curved line connects the right side of the **IPC** to a **Slave I/O Module** block.\n* A second curved line connects that first right-side **Slave I/O Module** to a second **Slave I/O Module** block below it.\n* The label **Slave I/O Module** has an arrow pointing to the third block on the left and another arrow pointing to the first block on the right.](.hsl-ai16ao2-m-vv-av-manual-4/b923854e39db9118c7ce68dddfd39135c3b7a073144aaec382403be95cd3ea91.jpg) Figure 1-4: HSL as distributed PLC Comparison between traditional PLC systems and HSL as distributed PLC ▶ The MPC is replaced by a PC with HSL Master ▶ The HSL slave I/O module is replaced by a remote side PLC ▶ The RS485 or RS232 cable is replaced by simple Ethernet cable ▶ The protocol handling is replaced by simple memory read/write. # HSL as Remote Time-deterministic DAQ The HSL system, with high-speed performance and deterministic time-deterministic scanning, is also applicable for remote time-deterministic data acquisition. The time-deterministic characteristic of an HSL system is an important factor when implementing a DAQ application. With an HSL system, all I/O data are refreshed in time-deterministic. The sampling rate (or scan rate) is linearly dependent on the number of slave indexed occupied, ranging from 91 $\mu$ s (less than three slave indexes) to 1.911 ms (63 slave indexes) under 6 Mbps. These two features go with HSL's remote capability to make it suitable for remote DAQ applications, especially when time-deterministic is of utmost concern. ![This block diagram depicts a control system with a central unit and three peripheral modules.\n\n**Labeled Blocks:**\n* **Slave I/O Module:** There are three identical blocks with this label, arranged horizontally across the middle of the diagram.\n* **HSL Master:** A larger block located at the bottom center, identified by an arrow pointing to it.\n* **RJ45/10BaseT:** A label on the far left of the horizontal connection line.\n\n**Connections:**\n* **Top Inputs:** Vertical lines connect specific input devices to each 'Slave I/O Module':\n * The left module connects to two red thermometers.\n * The middle module connects to a blue cylinder (resembling a tank or database).\n * The right module connects to a hand pressing a red button.\n* **System Bus:** A horizontal line connects the bottom of the three 'Slave I/O Module' blocks to the 'HSL Master' block. This line is labeled 'RJ45/10BaseT'.](.hsl-ai16ao2-m-vv-av-manual-4/3475f05012bd3a391c9c649d00da95d392a24103d1de1352b21c4d6d9c4fcd54.jpg) Figure 1-5: Time-deterministic DAQ using HSL # 1.2 HSL System Specifications # Platform ▶ Hardware platform: Industrial PC with PCI Bus/Embedded SBC with PMC connector ▶ Operating system platform: Windows® 98/2000/NT/XP or Linux Redhat # Software support ▶ Windows XP/2k library ▶ Linux: Kernel 2.4.x # HSL Master Board PCI -7853 single HSL master controller board with two ports PCI -7854 dual-HSL master controller board with four ports ▶ PMC-7852/G dual-HSL master controller board with four ports and PMC connector # Remote operation One master controller has two ports. One port uses the RJ-45 phone jack as connector. One phone jack can drive a maximum 32 modules at maximum. One master controller can connect maximum 63 slave indexes. The maximum wiring distance for each RJ-45 connector (one port) is 200 m @ 6 Mbps (serial wiring from master to last slave module). The maximum length of port connection may be 400 m @ 6 Mbps since both sides are 200 m in length. ![L\nL](.hsl-ai16ao2-m-vv-av-manual-4/63b5b7b13fedd869dced4c2355e7a3498745020c916e0905f4763d1790047978.jpg)
Transmission SpeedL (m)
3 Mbps300
6 Mbps200
12 Mbps100
Table 1-1: Remote Operation # Supports maximum 2.4 km wiring via seven HSL-HUB/Repeater modules HSL extension possibility using HSL-HUB3/Repeater (in 3 Mbps speed) ![Without HSL-HUB3\n300m\nX8\nWith HSL-HUB3\n2400m](.hsl-ai16ao2-m-vv-av-manual-4/c98863e7514849a6c8ab2e87705f465df1255b397231784edc82084d8b434be1.jpg)
Without HUBHUBX1HUBX2HUBX5HUBX7
12 Mbps100 m200 m300 m600 m800 m
6 Mbps200 m400 m600 m1200 m1600 m
3 Mbps300 m600 m900 m1800 m2400 m
# Wiring ▶ Connector: RJ-45 (on master controller and some of slave modules) ▶ Cable: Cat-5 100 Base/TX Ethernet cable with shielding # Communications ▶ Multi-drop full-duplex RS-422 with transformer isolation scheme ▶ Transmission speed: 3/6/12 Mbps (6 Mbps is factory default setting). ▶ I/O refresh rate: scan time unit × numbers of slave indexes (minimum is 3; maximum is 63)
3 Mbps6 Mbps12 Mbps
Full Duplex60.67 μs30.33 μs15.17 μs
Half Duplex118 μs59 μs29.5 μs
▶ Communication model: single master to multi-slave - Communication method: command/response type hand-shaking ▶ CRC12 and dedicated protocol for eliminating communication errors # 1.3 HSL Series Products # HSL Master controller boards See HSL Master Board on the previous section. At least one master controller card is needed for an HSL system. With PCI-7854 or PMC-7852/G, two master controllers are available. A maximum of 12 cards are supported for a single computer system. # Slave I/O modules A variety of HSL slave I/O modules are available.
SeriesModelDiscrete InputDiscrete OutputAnalog InputAnalog OutputStart Index Setting RangeSlave Index Occupation
DBHSL-DI32-DB-N/P32(1,3, 5, ...,61)2
HSL-DO32-DB-N/P32(1,3, 5, ...,61)2
HSL-DI16DO16-DB-N/P16161-631
MHSL-DI32-M-N/P32(1,3,...,61)2
HSL-DO32-M-N/P32(1,3,...,61)2
HSL-DI16DO16-M-NN/NP/PN//PP16161-631
HSL-R8DI16-M-N/P168 relay1-631
HSL-AI16AO2-M-VV1621-612
HSL-AI16AO2-M-AV1621-612
UHSL-DI16DO16-US/UJ16161-631
HSL-DI16-UL161-631
HSL-AO441-622
Table 1-2: Slave I/O modules Note: Start Index Setting Range means range of the start index address of DIP switch setting. Full duplex and half duplex mode have different ranges. The following remote motion control modules are also supported:
SeriesModelAxesInterfaceStart Index Setting RangeSlave Index Occupation
MotionHSL-4XMO-CG-N/P4General series1~60 for Half Duplex 1~57 for Full Duplex4
HSL-4XMO-CD-N/P4D-sub
Table 1-3: Remote Motion modules Note: Start Index Setting Range means range of the start index address of DIP switch setting. Full duplex and half duplex mode have different ranges. # Terminal Base A variety of HSL terminal base are also available.
Model NumbersModule Type SupportModule Number Support
HSL-TB64-DINAll the HSL DB series2
HSL-TB32-U-DINAll the HSL DB series1
HSL-TB32-M-DINAll the HSL M series1
HSL-TB32-MDAll the HSL M series1
Table 1-4: Terminal Base # 1.4 Technical Information # 1.4.1 HSL Technology Introduction Inside an HSL system, a single master controller communicates with multi-slave through a command-response. The master controller sends commands to slave I/O modules for setting output values and requesting input information. Every slave module responds after receiving commands with address ID. The responses may either be to set output according to the received values or to reply requested input information to the master controller. The illustration below shows the HSL working theory as regards the setting of output values. ![Based on the provided image, here is the description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n* **Memory:** A grey rectangle at the top center.\n* **NO 1:** A small rectangle on the left.\n* **NO 2:** A small rectangle next to 'NO 1'.\n* **NO 45:** A small rectangle in the lower-left section.\n* **Output value of every slave:** A large rectangle on the right side.\n* **No 45. Your output values are....:** An oval shape located at the bottom left, overlaying the dashed lines.\n* **Master:** A stick figure icon at the bottom right.\n\n**Connections:**\n* A curved arrow originates from the oval labeled '**No 45. Your output values are....**' and points towards the stick figure labeled '**Master**'.](.hsl-ai16ao2-m-vv-av-manual-4/f5edc5ffde5cdf8616987035ec5f81c9eaa1f573ff64684181a7cd87c4a84066.jpg) ![Group of identical black human figures arranged in two rows (no text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/8a6445dea854e58b07828e54db6afe4b48e76e7925a109e17324e21f56357370.jpg) Slaves I/O Modules Figure 1-6: HSL technology brief -1 The teacher (master) sends message “ID.#, your output values are XXX” to all students (slave I/O modules). Every student (with ID.#) then sets its output channels according to the values heard. The values that the teacher announced to the students are written on the blackboard (RAM on master cards), and can be easily modified. The following illustration shows the working theory for gathering input information. ![This diagram illustrates a master-slave communication process involving memory and I/O modules.\n\n**Labeled Blocks:**\n* **Memory:** A large rectangular block at the top containing smaller boxes labeled 'NO 1', 'NO 2', and 'NO 45', along with a larger box on the right labeled 'Output value of every slaves'.\n* **Master:** A central figure labeled 'Master'.\n* **Slaves I/O Modules:** A group of stick figures at the bottom labeled 'Slaves I/O Modules'.\n\n**Connections and Text:**\n* An arrow originates from the **Master** figure pointing towards the **Slaves I/O Modules** group. This connection is associated with the text bubble: 'NO 45,what's your input status,no'.\n* An arrow originates from a specific figure within the **Slaves I/O Modules** group pointing back to the **Master**. This connection is associated with the text bubble: 'I, No 45. My input status is ......'.](.hsl-ai16ao2-m-vv-av-manual-4/27c95cfe3491635e50680de569e5ef2329d8606dc2ba02abcb52c9a82fbca679.jpg) Figure 1-7: HSL technology brief-2 The teacher (master) sends the message “ID.#, what is your latest input status” to all students (slave I/O modules). Every student (with ID.#) then gives his answer. The teacher writes the answers on the blackboard (RAM on master cards). When someone (user's AP) wants to know the students' answers, he refers to the blackboard. All input information are saved in the memory. These two procedures take turn and repeat on every slave module. After each cycle, each slave module sets its newest output status and the master gathers all these information from the memory. We simulate the polling communication cycle through a teacher-student conversation: Teacher: Student No. 1, your output vales are ##, what's your latest input status? Student No. 1: My input status is ## Teacher writes the answer on the blackboard. Teacher: Student No. 2, your output vales are ##, what's your latest input status? Student No. 2: My input status is ## Teacher writes the answer on the blackboard. Until... Teacher: Student No. 63, your output vales are ##, what's your latest input status? Student No. 63: My input status is ## Teacher writes the answer on the blackboard. The polling cycle is now complete. The process repeats from Student No. 1.) Set output Values to slave 1 Gather input information from slave 1 Set output Values to slave 2 Gather input information from slave Set output Values to slave 3 Gather input information from slave Set output Values to slave 63 Gather input information from slave Figure 1-8: HSL I/O polling cycle The HSL master-slave communication architecture is illustrated below: ![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n* **Master Site:** Contains an orange block labeled 'HSL Master Board'. Inside this board are two blue blocks: 'Memory' and 'Master IC'.\n* **Remote Site:** Contains three stacked blue blocks labeled 'Slave Module 1', 'Slave Module 2', and 'Slave Module N'. Each block contains smaller white boxes labeled 'ID' (one in Module 1, two in Module 2, and four in Module N).\n* **Center:** A green icon with curved arrows labeled 'Polling Cycle'.\n* **Bottom Left:** Text reading 'Note: ID is slave index'.\n\n**Connections:**\n* **Internal Master Connection:** A yellow double-headed arrow connects 'Memory' and 'Master IC' within the HSL Master Board.\n* **System Loop (Red Dashed Lines):** Red dashed lines with arrows indicate a sequential connection loop:\n * From 'Master IC' to the 'ID' block inside 'Slave Module 1'.\n * From 'Slave Module 1' down to 'Slave Module 2'.\n * From 'Slave Module 2' down to 'Slave Module N'.\n * From 'Slave Module N' looping back to the 'Master IC'.](.hsl-ai16ao2-m-vv-av-manual-4/1de2e974112a1e818b5fc4158a040c1598bf24548a242a75844f53f91a3caf85.jpg) Figure 1-9: Master-slave communication architecture # 1.4.2 HSL Terminology In addition to the input/output polling mechanism shown above, here are some HSL-related syntax for your reference. HSL Master. Master is defined as the teacher in Figure 1.9 and 1.10. The master takes charge of giving commands, including output value announcements and latest input status requests. Slave I/O Module. Slave I/O modules are defined are the students in Figure 1.9 and 1.10. Slave I/O modules are passive components in an HSL system. They receive commands from the master, then respond by telling their newest input status or by setting output values. The slave I/O modules may take one or two address indexes depending on the I/O module type. Polling Cycle. When communicating with slave I/O modules, the master takes turn setting the output for and gathering input from every slave module. When all slave modules are updated, a polling cycle is completed. The polling cycle infinitely repeats when the master is working properly. I/O Refreshing Rate. The time needed to complete an I/O updating cycle. This may also be the longest time needed for any digital I/O channel to obtain its latest status. The refreshing rate is decided linearly by the total number of slaves used in an HSL system, therefore no interference occurs between any two HSL systems or PC/IPC at the same time. Transmission Speed. May refer to the speed of digital signal transfer or I/O refreshing rate. When referring to the speed of digital signal transfer inside the cable, the transmission speed is known as data rate. The unit of transmission speed is bits per second (bps). The unit of I/O refreshing rate speed is expressed in mini-second (ms). # 1.4.3 System Configurations To develop an HSL application, you must know how to configure the HSL cards and slave I/O modules. The following sections describe the configuration concepts for an HSL system. For detailed information, refer to individual chapters. Master Card Index (card\_ID). You can install one or more HSL master boards in an IPC system. The PCI BIOS assigns the card index for each HSL master board. You need to specify the card index for programming purposes. The card index is starts from 0. ![PCI-7854\nIPC](.hsl-ai16ao2-m-vv-av-manual-4/f92f933c83131df52f078b54701590f0b1229670b4e022041c6574253585b7f1.jpg) Figure 1-10: Multiple master cards in one IPC Refer to Chapter 2: HSL Master Controller for more information. HSL Connect Index (connect\_index). The PCI-7853 provides only one HSL master controller (connect\_index=0), while PCI-7854 or PMC-7852/G provides two HSL master controllers (connect\_index=0 or 1). Connect index distinguishes the master controllers. Ports. Port refers to the RJ-45 connector on the HSL master board. A connector is a loop of wiring that starts from the master card and connects to up to 32 slave I/O modules. There are two ports in one HSL master controller, both carrying the same signals sent from the master. Slave Index. A complete HSL system is composed of one master and 1 to 63 slave indexes. The following diagram illustrates an HSL system. ![The diagram illustrates a system architecture centered around a central control unit.\n\n**Labeled Blocks:**\n* **Top Group:** A dashed box labeled **Slave I/O Module (Up to 32 slave modules)**. Inside are three units, each pointed to by an arrow labeled **Slave I/O Module**.\n* **Center Unit:** A card labeled **Master**.\n* **Bottom Group:** A dashed box labeled **Slave I/O Module (Up to 32 slave modules)**. Inside are three units, each pointed to by an arrow labeled **Slave I/O Module**.\n* **Left Label:** A vertical double-headed arrow labeled **Circuit**.\n\n**Connections:**\n* A thick black cable connects the three modules in the top group in a daisy-chain fashion.\n* A cable connects the rightmost module of the top group to the **Master**.\n* A cable connects the **Master** to the rightmost module of the bottom group.\n* A thick black cable connects the three modules in the bottom group in a daisy-chain fashion.\n* The **Circuit** label indicates the link between the top and bottom module groups.](.hsl-ai16ao2-m-vv-av-manual-4/851048f1415771bb337239e13e713023febcc407548df289182a4c44848263d6.jpg) Figure 1-11: HSL system layout example-serial wiring Every master circuit can support up to 32 slaves. However, since the slave address is assigned by a 6-bit DIP-switch on the I/O module's termination board with the value '0' reserved, the maximum number of slaves is 63, not 64. The slave I/O modules in an HSL system must have different slave index. Though the slave index may not necessarily continue from 1, continuous addressing is more efficient. When an HSL system has only two slave modules addressed 1 and 63, the I/O refreshing rate is the same with an HSL system with 63 slave modules addressed from 1 to 63. Refer to Chapter 3: HSL Slave I/O Module for procedures on how to set the addresses of slave I/O modules. # 1.4.4 Wiring The HSL network follows a modified RS-422 electrical specification. # Wiring The wire cables of an HSL system are carefully selected for installation convenience and standardization without sacrificing communication quality. A 100BaseTX cable with RJ-45 connectors is used on HSL systems. # Full-duplex RS-422 with multi-drop The typical RS-422 is not a networking specification. However, HSL modified the specification to suit network applications. The TXD of the master is connected to the RXD of every slave I/O modules, while all TXD of slaves are connected to the RXD of the master. Only the master uses TXD (of master) to RXD (of slave) channel. Through design, only one slave at a time sends message with TXD (of slave) to RXD (of master) channel. This kind of networking solution is called RS-422 with multi-drop. # Ports An HSL master supports a 2-port segment. Inside the ports, the TXD (of master) to RXD (of slave) channels are of the same signal sent by master. In contrast, the TXD (of slave) to RXD (of master) channels are isolated from each circuit and signals inside do not pass through the master from one circuit to another. The diagram below illustrates RS-422 with multi-drop: ![This diagram illustrates a communication network topology.\n\n**Labeled Blocks:**\n* **Left:** A large block labeled 'Controller' containing two sections labeled 'MASTER 0' and 'MASTER 1'.\n* **Top:** Two blocks labeled 'Slave I/O module'.\n* **Bottom:** Three blocks labeled 'Slave I/O module'.\n\n**Connections:**\n* **From MASTER 0:** A connector block labeled 'RL48' has outputs labeled 'TXD' and 'RXD'. These connect via wavy lines to the two top 'Slave I/O module' blocks.\n* **From MASTER 1:** A connector block labeled 'RL48' has outputs labeled 'TXD' and 'RXD'. These connect via wavy lines to the three bottom 'Slave I/O module' blocks.\n* **Inside Slave Modules:** In each 'Slave I/O module' block (both top and bottom), vertical lines labeled 'TXD' and 'RXD' connect to a port labeled 'RJ45'.](.hsl-ai16ao2-m-vv-av-manual-4/ef9357867b8933c186015ddb528515d4b13623a65a25afaf55bb18f9a5b15dd8.jpg) Figure 1-12: HSL wiring – RS-422 with multi-drop There are two RJ-45 notches in each master. Each notch supports one port of wiring. ▶ Only four lines of the RJ-45 cable are used: two for transmission and two for reception. ▶ All slave modules are connected in parallel. The isolation between connection cable and individual slave I/O modules protects the signals from interference by other slaves. # 1.4.5 Networking Topology Base on the RS-422/RS-485 architecture, a variety of topologies are available for an HSL circuit, including serial, multi-drop, star, etc. The following sections illustrate some applicable network topologies for your reference. # Serial wiring All slave I/O modules are connected using a twin-head 100BaseTX cables. ![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n* **IPC**: A computer chassis (Industrial Personal Computer) with a front panel labeled 'IPC'. Inside, there is a specific card labeled **'PCI-7853/54'** and other slots labeled **'Other PCI cards'**.\n* **2M/160**: A small rectangular module connected to the PCI card.\n* **16B/160**: A small rectangular module. Below it is a label box reading **'Slave I/O Module'**.\n* **16M**: A small rectangular module.\n\n**Connections:**\n* A line connects the **'PCI-7853/54'** card to the **'2M/160'** module.\n* A line connects the **'2M/160'** module to the **'16B/160'** module.\n* A line connects the **'16B/160'** module to the **'16M'** module. The text **'RJ45/10BaseT'** is positioned above this connecting line.\n* A line extends from the **'16M'** module to the right, ending in a dotted line to indicate a continuation of the chain.](.hsl-ai16ao2-m-vv-av-manual-4/005924df426bba1de4d469bb820a3cea61b6c20a154a971a0103e2395974ea32.jpg) Figure 1-13: HSL networking topology – Serial Since two notches of any slave I/O module's termination board are short circuit, this type of wiring provides the most convenient and intuitive way to form a HSL network. The longest wiring length is 200 m with under 6 Mbps. # 1.4.6 I/O refreshing rate of an HSL system The scan time unit for one slave index is set in 3/6/12 Mbps transmission rate. Once the maximum slave address is set, the polling cycle time of the HSL system is using the following formula: Polling cycle time = maximum-address-of-slave \* scan time unit
Maximum addressCycle Time under 3 MbpsCycle Time under 6 MbpsCycle Time under 12 Mbps
5303.33 μs151.67 μs75.83 μs
10606.67μs303.33 μs151.67 μs
201.213 ms606.67 μs303.33 μs
301.820 ms910.00 μs455.00 μs
402.427 ms1.213 ms606.67 μs
503.033 ms1.516 ms758.33 μs
603.640 ms1.820 ms910.00 μs
633.822 ms1.911 ms955.50 μs
Table 1-5: Polling cycle time of HSL (Full Duplex Mode) Note: Regardless of the transmission rate you select, the minimum polling cycle time is 3×scan time unit, even when the maximum address is less than 3. Refer to Appendix A. # 1.4.7 Communication error handling The HSL communication protocol is designed to eliminate any error, there may be some chances of communication errors such as light striking, sudden off-line, etc. In an HSL system, the master holds an accumulated slave-no-response count for every individual slave I/O module. The count value is updated for each slave module in every polling cycle. ▶ If communication with certain slave I/O module is successful, the no-response count value for this slave is set to 0. ▶ If the communication failed, the no-response count value increases by 1. ▶ When the count is larger than or equal to 3, a binary flag indexing communication error is set to True. The maximum value of no-response count is 7. The value is retained even if the error continues to occur. The no-response count value and the communication error flag status may be obtained by software function call. These error handling data are also returned every time the user wants to set or get the I/O values. In addition, the HSL, through a software communication error-handling driver, supports a self-diagnosis function that detects off-line or out-of-communication slave modules. In a programmed period of time (default 20 ms), the master sends an IRQ to trigger the driver to check the slave's no-response count value. If the count value is 7, the driver informs the system that the slave module is off-line. # 1.5 Software Support # Window® 2000/XP DLL The provided Windows® 2K/XP DLL (Dynamic Link Library) is a programming interface for systems using Microsoft® Windows®. The driver works with any Windows® programming language that integrates DLL such as Visual C/C++ (6.0 or above), Borland C++(5.0 or above), or Visual Basic (6.0 or above). # Linux Driver The HSL Linux driver includes device drivers and shared library for Linux-based systems. The developing environment can be GNU C/C++ or any programming language that allows linking to a shared library. The Linux driver is included in the ADLINK All-in-one CD. # 2 HSL Master Controller The HSL master is the key component in charge of communicating with slave I/O modules. The master sets output values to and gathers input information from slaves. ADLINK presents four types of HSL master cards: PCI-7853, PCI-7854 and PMC-7852, and PMC-7852/G. The main difference between these cards is the number of supported HSL master. PCI-7853: Single HSL Master Controller Interface Card PCI-7854: Dual-HSL Master Controller Interface Card ▶ PMC-7852/G: Dual-HSL Master Controller Interface Card with PMC connector # 2.1 Board Overview ![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/e9d862723061d1dc9b9160014dc2195d7a855b79c6d00d4436209ec395cb360d.jpg) Figure 2-1: PCI-7854 front view # 2.2 Specifications # PCI Bus ▶ PCI local bus specification Rev. 2.1-compliant # Master Controller ▶ HSL ASIC master controller ▶ 48 MHz external clock # Interface ▶ RS-422/RS-485 with transformer isolation ▶ Half/Full duplex communication ▶ 3/6/12 Mbps transmission rate through a S/W function setting (default is 6 Mbps) ▶ Two ports for each master controller # Connector ▶ RJ-45 connector x 2 (CN1 for PCI-7853) ▶ RJ-45 connector x 4 (CN1, CN2 for PCI-7854; H1A, H1B, H2A, H2B for PMC-7852/G) # Interrupt ▶ 16-bit programmable timer with 5μs resolution # LED Indicator ▶ Link status # Dimension ▶ PCI-7853/7854: 122 (L) × 107 (W) mm ▶ PMC-7852/G: 74 (W) × 149 (W) mm Operating Temperature: 0°C to 70°C Storage Temperature: -20°C to 80°C Power Consumption: +5V @ 500 mA typical 2.2.1 PCI-7853/7854 Layout ![121.69\n119.9\nLED1\nCN1\nCN2\n100.33\n126.35\nPCI-7854\nMASTER\nController\nS1\nADDRESS\nDECODER\nPCI\nController\n108.68](.hsl-ai16ao2-m-vv-av-manual-4/438c7376439c30c1ecabf4e70515e07a56b7f568480e2ff575f493700f6ffb5b.jpg) Figure 2-2: PCI-7853/7854 Layout CN1: RJ-45 connector with first HSL master controller CN2: RJ-45 connector with second HSL master controller (PCI-7854 only) S1: Card ID switch selection 2.2.2 PMC-7852/G Layout ![124\n74\n(1M)\nJP5\nJP6\nJP1\nJP2\nJP4\nJP5\nJP1\nJP7\nJP8\nQW\nDVJ](.hsl-ai16ao2-m-vv-av-manual-4/29f08950742343412a65c49575507dbece6e679da6337562013abff7ffd7ea5b.jpg) ![152\n51-24006-183\n7852G-Ex1\nCN1\nH2B\nH2A\nH1B\nH1A\nLEDI\n32\n16.84\nPNC-7852G\nLINK\nH1A\nH1B\nH2A\nH2B\n183](.hsl-ai16ao2-m-vv-av-manual-4/0e93dbd464c4c8741025bbd064810595d53179978f00501aa478645d78933511.jpg) Figure 2-3: PMC-7852/G Layout ▶ H1A, H1B: RJ-45 connector with first HSL master controller ▶ H2A, H2B: RJ-45 connector with second HSL master controller (PMC-7852 only) JP1, 2, 3, 6: Full/Half duplex mode with first master controller (Default: Full duplex mode) JP4, 5: Full/Half duplex mode with second master controller (Default: Full duplex mode) ▶ SW1: Transmission speed option. (Default: 6 Mbps) # 2.3 Configuration # 2.3.1 SW1 (PMC-7852/G only) ![Four vertical rectangular blocks with white borders, arranged horizontally (no text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/456c235b3b70ec20dfad08e41b13874bfee500585da82b7fc271ff18f14e73c2.jpg) Figure 2-4: SW1 – Transmission Rate Setting
No.Set transmission rate
1OFFONOFFON1st Master Controller
2OFFOFFONON
3OFFONOFFON2nd Master Controller
4OFFOFFONON
Rate12M6M3MEXC
Default: 6 Mbps. # 2.3.2 JP 1, 2, 3, 6 / JP 4, 5 (PMC-7852/G only) ![FD HD](.hsl-ai16ao2-m-vv-av-manual-4/8a4f6e966afe9c3f6f5978a2d08a0efcc137cfeb0f281829b79862e7ec3fc8fc.jpg) Figure 2-5: Top View of PMC-7852/G, for JP 1, 2, 3, 4, 5, 6 jumper settings. # 2.4 PIN Assignment (female) ![1\n8](.hsl-ai16ao2-m-vv-av-manual-4/7a3c217cb56699a3ed2409740d260de79e6a687ba7d433be23639c369c1912b7.jpg) RJ45 Female Connector for PCI-7851 / 7852 / 7853 / 7854 ![1\n8](.hsl-ai16ao2-m-vv-av-manual-4/8fb5a0431c0d12ccd2f1acbd10645117336aa7cea0cfa26997d4a4e1022da2d5.jpg) RJ45 Female Connector for HSL-TB64-DIN, HSL-TB32-U-DIN, HSL-TB32-DIN, HSL-TB32-DO-DIN, HSL-TB32-M-DIN, HSL-TB32-MD
PIN No.PINOUT
1NC
2NC
3RX+
4TX-
5TX+
6RX-
7NC
8NC
PIN No.PINOUT
1NC
2NC
3TX+
4RX-
5RX+
6TX-
7NC
8NC
# 2.5 Software Architecture Description The PCI-7853/PCI-7854/PMC-7852/G comes with one or two HSL master ASICs that control the HSL communication. The purpose of communicating with HSL I/O modules is to gather input data from or set output value to them. To achieve this purpose, each HSL master controller manages a 2Kbyte SRAM on PCI-7853/PCI-7854 boards for data storage. For every polling cycle, the master refreshes all input data from the I/O modules and sets the latest output data to the I/O modules. The SRAM keeps these data for the software drivers to read/write I/O information. 2.5.1 Functional Block Diagram ![This diagram illustrates a system architecture divided into two main sections: **SOFTWARE LAYER** and **HARDWARE LAYER**.\n\n**Labeled Blocks:**\n\n**SOFTWARE LAYER:**\n* User Application\n* DLL\n* Driver\n* PCI Bus\n\n**HARDWARE LAYER:**\n* Slave Scan Controller\n* Memory Bus\n* Parallel to Serial Controller\n* Trans / Receiver\n* TXD\n* RXD\n\n**Connections:**\n\n* **Slave Scan Controller** and **Memory Bus** are connected by a horizontal double-headed arrow.\n* **Slave Scan Controller** and **Parallel to Serial Controller** are connected by a vertical double-headed arrow.\n* **Parallel to Serial Controller** and **Trans / Receiver** are connected bidirectionally: a red arrow points down from the controller to the transceiver, and a red arrow points up from the transceiver to the controller.\n* **Trans / Receiver** connects to **TXD** via a downward-pointing red arrow.\n* **RXD** connects to **Trans / Receiver** via an upward-pointing red arrow.](.hsl-ai16ao2-m-vv-av-manual-4/3038cb1043219a6e3024baf8344d4b30a4206e59b8330e4bb813cc952d056804.jpg) Figure 2-6: Functional Block diagram of HSL master The diagram above shows how the HSL communicates with the user's AP. The SRAM acts with a buffer-like characteristic. # 2.6 Installation # 2.6.1 Hardware Installation The PCI-7853/PCI-7854 is a plug and play device, with the system BIOS automatically assigning the interrupt channel and memory mapping address. You only need to adjust the SW1 to the desired transmission speed. For PMC-7852/G, refer to GEME user manual for details. # 2.6.2 Software Installation Refer to chapter 4.1. # 3 HSL Slave Module The HSL is a master-slave network system that features an innovative distributed architecture that modularizes the communication, I/O functions and signal termination. ADLINK provides a complete line of slave I/O modules and terminal bases including discrete I/O, analog I/O, and motion control to meet your application requirements. For motion control modules, refer to the HSL-4XMO user's manual. Slave I/O Module. There are three groups of slave I/O modules with varied dimensions. The slave I/O modules provide the terminal base with different levels of I/O capability. To identify each slave I/O module in an HSL network, an electronic data sheet is embedded in the module, and each module is identified by an address ID configurable via the 6-bit DIP switch. Depending on the I/O support, each slave I/O module may be assigned one or two address IDs. Since the highest ID number in an HSL master is 63 (6-bit and '0' reserved for master), up to 63 slave I/O modules are supported in one HSL master. Terminal Base. Offers an easy wiring media. Both power and signal wiring go from the terminal base to the slave I/O modules. Also, master links to all slave I/O modules via the terminal base using an RJ-45 cable. The TB makes the slave I/O modules hot-swappable without interfering other modules in the same HSL network. HUB/Repeater. Provides sub-system support for various network topologies. Wiring Cable. The cables connecting the HSL master and slave I/O modules are standard 100 Base/TX with RJ-45 connectors. These are exactly the same with commercial Ethernet cables. # 3.1 Slave I/O Module # 3.1.1 Discrete I/O Module ADLINK provides three I/O module series: DB, M and L. ▶ DB: Daughterboard form factor ▶ M: Daughterboard form factor with aluminum cover ▶ U: U-series
SeriesModelDiscrete InputDiscrete OutputRelay OutputSlave Index Occupation
DBHSL-DI32-DB-N/P322 (Consecutive from odd number)
HSL-DO32-DB-N/P322 (Consecutive from odd number)
HSL-DI16DO16-DB-N/P16161
MHSL-DI32-M-N/P322 (Consecutive from odd number)
HSL-DO32-M-N/P322 (Consecutive from odd number)
HSL-DI16DO16-M-NN/NP/PN//PP16161
HSL-R8DI16-M-N/P1681
UHSL-DI16DO16-US/UJ-NN/NP/PN/PP16161
HSL-DI16-UL161
Below is the selection guide. ![The flowchart is a linear, horizontal sequence of four rectangular blocks connected by hyphens. The blocks contain the following text, from left to right:\n\n1. **HSL**\n2. **D1xDOx**\n3. **x**\n4. **XY**\n\nThe connections between the blocks are single hyphens ( - ) linking them sequentially.](.hsl-ai16ao2-m-vv-av-manual-4/27805e7b29f088a99e16bdee2addd25107ed829e56bda070b7e189c239afbca7.jpg) # Discrete I/O Type: DI16DO16: 16 discrete inputs and 16 discrete outputs DI32: 32 discrete inputs DO32: 32 discrete outputs R8DI16: 8 relay outputs and 16 discrete inputs # Series: DB: Daughter board form factor M: Daughter board with aluminum cover U: U-Series # Signal Type: X: Input Signal Type: NPN sinking and PNP sourcing support Y: Output Signal Type: NPN sinking and PNP sourcing support # 3.1.2 Analog I/O Module ADLINK provides M series analog I/O module.
SeriesModelAnalog InputAnalog OutputSlave Index Occupation
MHSL-AI16AO2-M-VV1622 (Leap number)
HSL-AI16AO2-M-AV1622 (Leap number)
UHSL-AO442
Below is the selection guide. HSL - AlxAOx - x - XY Discrete I/O Type: AI16AO16: 16 analog inputs and 2 analog outputs Series: M: Daughter board with aluminum cover Signal Type: X: Input signal type, V means voltage and A means current. Y: Output signal type, V means voltage. # 3.1.3 Motion Control ADLINK provides the HSL-4XMO-CG-N/P and HSL-4XMO-CD-N/P remote motion control cards. Below is the selection guide. HSL - 4XMO - Cx - X Controllable Axes: 4XMO: 4-axis pulse train type motion control Series: CG: The connection interface is general type. CD: The connection interface is D-sub 25. Signal Type: X: Output Signal Type: NPN sinking and PNP sourcing support The HSL-4XMO-CG-N/P is suitable for applications using stepper and linear motors. For HSL-4XMO-CD-N/P, ADLINK provides the accessories and transfer cable for direct connection to a servo amplifier. For details, refer to the HSL-4XMO user's manual. # 3.1.4 General Specifications Discrete I/O Module
Discrete InputPhoto couple isolation2500 $V_{RMS}$
Input impedance4.7 kΩ
Input Voltage+24 V *
Input CurrentFor NPN(1)-10 mA
For PNP(2)+10 mA
Operation Voltage(@ 24 $V_{DC}$ Power Supply)For NPN(1)ON: 11.4 $V_{DC}$ (max)OFF: 14.3 $V_{DC}$ (min)
For PNP(2)ON: 12.6 $V_{DC}$ (min)OFF: 9.8 $V_{DC}$ (max)
Response TimeON: 8.8 μs(Typical) ; OFF: 42 μs(Typical)
Discrete OutputSwitch capacityFor NPN(3)All channels(5): -50mA/ch at 24 $V_{DC}$
For PNP(4)All channels: +50mA/ch at 24 $V_{DC}$
Response TimeON to OFF: 68 μs
OFF to ON: 1.1 μs
RelayRelay TypeSPST, normally open, non-latching
Rating30 $V_{DC}/2$ A; 250 $V_{AC}/2$ A
Switching Frequency20 times/minute at rated load
Response TimeON to OFF: 3 μs (max)
OFF to ON: 6 μs (max)
(1): NPN sinking type sensor input module (2): PNP sourcing type sensor input modules (3): NPN sinking type sensor output module (4): PNP sourcing type sensor output modules (5): U-series all channels: -90 mA at 24 $v_{DC}$ \*Note: The HSL-DI16-UL supports 5 V, 12 V, and 24 V, selected by a jumper for each channel: ▶ JDI0 - JDI15 (input voltage setting) ![The image displays a black and white line drawing of a rectangular panel. A thick vertical black bar runs along the left edge. To the right of the bar is a grid of symbols. The top two rows each contain a square on the left and a circle on the right. The bottom row is enclosed in a rectangular border and contains two circles side-by-side. The number '1' is located at the top left, the number '2' is at the top right, the number '5' is at the bottom left, and the number '6' is at the bottom right.](.hsl-ai16ao2-m-vv-av-manual-4/220e4a7ef3c78b9591a6eaca87118ad04559aeed3bb3099a0765b30bfbb911f1.jpg) 5 V 12 V 24 V (default)
Discrete InputInput impedance4.7 kΩ (@24 VDC, 2.74 k (@12 VDC), 1.1 k (@5 VDC)
Operation VoltageDI_COM @ 24 VDCON: 14.0 VDC (max)OFF: 18.0 VDC (min)
DI_COM @ 12 VDCON: 6.0 VDC (min)OFF: 8.0 VDC (max)
DI_COM @ 5 VDCON: 1.0 VDC (min)OFF: 3.0 VDC (max)
Analog I/O Module
Analog InputA/D Resolution16-bit (14-bit guaranteed)
Input RangeFor VV type: ±10, ±5, ±2.5, ±1.25 V
For AV type: 20 mA, 10 mA, 5 mA
A/D Conversion10 μs
Signal Type16-CH single-ended; 8-CH differential
Analog OutputD/A Resolution16-bit
DA Settling Time10 μs
# Motion Control Refer to the HSL-4XMO user's manual. # 3.1.5 DIP Switch Setting: ![ON\n1 2 3 4 5 6](.hsl-ai16ao2-m-vv-av-manual-4/0d93f0079a774fce99d7999b9060d348724d2aed4b92ca1c6e9f15195f2e69e2.jpg) ![ON = 1\n100000 address 1\n010000 address 2\n... ... \n011111 address 62\n111111 address 63\nOFF = 0](.hsl-ai16ao2-m-vv-av-manual-4/48845d1f749299c6715499bb8b2f95d4efc64a74517995598507d0327f42dcd1.jpg) # Notes (1) The address (or slave index) 0 is reserved. (2) The HSL-DI32-M, HSL-DO32-M, HSL-DI32-DB, and HSL-DO32-DB require two consecutive addresses starting from an odd number. For example, if the DIP switch is set to 3, it occupies slave index 3 and 4. (3) The HSL-AI16AO2-M-VV/AV requires two leap addresses at full duplex mode. For example, if the DIP switch is set to 2, the module occupies addresses 2 and 4. (4) The HSL-4XMO-CG-N/P and HSL-4XMO-CD-N/P require four leap addresses at full duplex mode. For example, if the DIP switch is set to 2, these modules occupy 2, 4, 6, and 8. At half duplex mode, it requires 4 consecutive addresses. # 3.1.6 Wiring Diagram -N NPN Sinking type sensor Input ![Circuit\nv+\nIN\nG\n4.7kΩ\nLED\nInternal Circuits](.hsl-ai16ao2-m-vv-av-manual-4/d8eeb6708525bec0b9fa883241e32281aea563a56ae8eaf67a91de6855d376b7.jpg) -N Dry Contact Input ![v+\nIN\nG\n4.7kΩ\nLED\nInternal Circuits](.hsl-ai16ao2-m-vv-av-manual-4/cead34dced97ec1391ec20f124bc778ee92325a2301f1ace4f98b84631bd8c2f.jpg) -P PNP Sourcing type sensor Input ![Circuit\nV+\nIN\nG\n4.7kΩ\nLED\nInternal Circuits](.hsl-ai16ao2-m-vv-av-manual-4/e758dd3317ec90f53f7f7f273370770c3066e44f7d4e8b8a5d04b4685bc1214b.jpg) -P Wet Contact Input ![v+\nIN\n4.7kΩ\nG\nLED\nInternal\nCircuits](.hsl-ai16ao2-m-vv-av-manual-4/318857f2ba862732570dc8446aa7ae44a520e7645e02b4aea22d4c380a5eb5dd.jpg) -N NPN Sinking Output ![LED\nInternal Circuits\nV+\nLoad\nOut\nG](.hsl-ai16ao2-m-vv-av-manual-4/be97ec9d9bfb1db7f41eca2e37b0b91bb7c728cb114b04c969d7cd389e69b107.jpg) -P PNP Sourcing Output ![LED\nInternal\nCircuits\nV+\nOut\nLoad\nG](.hsl-ai16ao2-m-vv-av-manual-4/e75974c3a33ea2fbbacd0501af760182aa3dee2fd02c2462b13cd0c860a32f85.jpg) -R Relay Output ![The diagram illustrates a block diagram for a Solid State Relay (SSR) and its associated load circuit.\n\n**Labeled Blocks:**\n* **LED**\n* **Internal Circuit**\n* **SSR**\n* **NO.n**\n* **COM.n**\n* **Load**\n\n**Connections:**\n* An **LED** is connected across the top of the **Internal Circuit** block.\n* The **Internal Circuit** is connected to the **SSR** block via two parallel lines.\n* The **SSR** block connects to two output terminals labeled **NO.n** (top) and **COM.n** (bottom).\n* The **NO.n** terminal connects to the left side of the **Load** block.\n* The right side of the **Load** block connects to the top of a vertical branch containing a capacitor symbol.\n* The bottom of this vertical branch connects to the **COM.n** terminal.\n* An AC source symbol (circle with a tilde) is connected via a dotted line to the **COM.n** terminal and is connected in parallel to the capacitor branch at the top.](.hsl-ai16ao2-m-vv-av-manual-4/3934ecf905ab8d8a439fe932f895e050701e3195735e1934afff843e0df5b227.jpg) Analog Input (Differential Voltage Input) ![The diagram shows a 'Differential' 'Signal' 'Source' connected to an 'ADC' (Analog-to-Digital Converter).\n\n**Labeled Blocks and Components:**\n* **Differential Signal Source**: Located at the top left, associated with an AC voltage source symbol (a circle with a sine wave inside).\n* **Ground Reference**: The bottom of the signal source connects to a battery symbol, which connects to a ground triangle labeled **AGND**. The text **(30V** appears next to the battery.\n* **Input Terminals**: Inside a large dotted rectangular box, there are two input terminals. The top one is labeled **IN(+)** and the bottom one is labeled **IN(-)**.\n* **ADC**: A rounded rectangle on the right side inside the dotted box labeled **ADC**.\n\n**Connections:**\n* A line from the top of the AC source connects to the **IN(+)** terminal.\n* A line from the bottom of the AC source connects to the **IN(-)** terminal.\n* Two arrows point from the **IN(+)** terminal to the **ADC** block.\n* Two arrows point from the **IN(-)** terminal to the **ADC** block.](.hsl-ai16ao2-m-vv-av-manual-4/9858eae40e50e07eff789b0943668252255be805c4c6e0ce426f33978c315378.jpg) Analog Input (Single-End Voltage Input) ![This diagram illustrates a connection between a signal source and an analog-to-digital converter.\n\n**Text and Components:**\n* On the far left, the text 'Ground Signal Source' is stacked vertically.\n* Below the text is an AC voltage source symbol (a circle with a sine wave inside), which connects to a ground symbol (an inverted triangle).\n* Inside a large dotted rectangular boundary, there are two input terminals represented by hexagons with diagonal hatching:\n * The top terminal is labeled **IN(+)**.\n * The bottom terminal is labeled **AGND**.\n* To the right, within the same dotted boundary, is a rounded rectangular block labeled **ADC**.\n\n**Connections:**\n* A line extends from the top of the AC source to the **IN(+)** terminal.\n* A line extends from the bottom of the AC source to the **AGND** terminal.\n* An arrow points from the **IN(+)** terminal to the **ADC** block.\n* An arrow points from the **AGND** terminal to the **ADC** block.](.hsl-ai16ao2-m-vv-av-manual-4/4af90c300d220144da7ea1f7999fd086058420a1ddb3a63fabb3d3311d03fbb2.jpg) Analog Input (Current Measure) ![The image displays a block diagram illustrating an analog input circuit. On the left side, a component labeled 'Current Source' (represented by a circle with an upward arrow) is connected in parallel across a resistor labeled 'R'. Text below the resistor specifies 'R=125 Ohm' and '%1 accuracy'.\n\nThe top and bottom rails of this resistor circuit connect to a bracketed input section enclosed within a dotted box. This section features two hexagonal input terminals: the top one is labeled 'IN(+)' and the bottom one is labeled 'IN(-)'. Two arrows extend from these input terminals to the left side of a rectangular block on the right labeled 'ADC'.](.hsl-ai16ao2-m-vv-av-manual-4/249640e9b41a4fb43c18d396f9e8772b3bbc947b9bea0290a5b770465179ac63.jpg) Thermocouple Measurement ![This block diagram illustrates a signal processing circuit with the following components and connections:\n\n**Left Section (Signal Source and Biasing):**\n* A **circle** (signal source) is connected to a **triangle** (amplifier).\n* From the triangle, two horizontal lines extend to the right.\n * The **top line** passes through an **oval shape** (capacitor).\n * The **bottom line** runs parallel below the top line.\n* A **vertical line** drops down from the top line (after the oval shape).\n * This vertical line passes through a **battery symbol**. Next to it is the text **'(30V'**.\n * The line continues down to a **ground symbol** (triangle with horizontal lines). Next to it is the text **'AGND'**.\n * The vertical line connects to the bottom line.\n\n**Input Section (Dotted Box):**\n* The top line (after the oval) enters a large **dotted rectangular box** at a terminal labeled **'IN(+)'**.\n* The bottom line enters the same box at a terminal labeled **'IN(-)''.\n\n**ADC Section:**\n* Inside the dotted box, arrows point from the **'IN(+)'** terminal and the **'IN(-)'** terminal to a rectangular block labeled **'ADC'**.](.hsl-ai16ao2-m-vv-av-manual-4/cae5dd981ce19c6744de1d2a7351ab53e2679a89943e8f29f83919311e9ecd4c.jpg) # Dimension -DB Daughterboard form factor (100 mm X 78.2 mm) ![100\n94\nφ3.2 47L\n75\n78.2\n2.235\n4.2\n46.43\n28\n9\n82\n92\n4\n5\n4.5](.hsl-ai16ao2-m-vv-av-manual-4/6baab4a6582fad8fbeefa54bf94d773ea6e9047e2feb7af48a466ecf9fb47575.jpg) -M Daughterboard with aluminum cover (125 mm X 80 mm) ![The image displays a technical line drawing with three views of a rectangular electronic device, accompanied by dimensional annotations.\n\n**Top View:**\n* Shows a faceplate with a large central connector featuring a grid of pin holes arranged in five rows.\n* Mounting holes are visible on the far left and right edges.\n* **Dimensions:** Width is **125**; Height is **22.4**.\n\n**Middle View:**\n* Shows the main body of the device.\n* **Dimensions:** Width is **108**; Height is **80**.\n* At the bottom, a mounting bracket extends slightly wider than the main body.\n* **Dimensions:** Bracket width is **116**; Bracket height is **0.7**.\n* A panel of six DIP switches is visible at the bottom center, labeled **666666**.\n\n**Right View:**\n* Shows the side profile of the device.\n* **Dimensions:** The bottom mounting base width is **13.4**.\n* Two screw heads are visible on the side face, and mounting slots are visible at the bottom.](.hsl-ai16ao2-m-vv-av-manual-4/12b88d85f9982464f5445a241414758518162f2fc8a29c0152992930df06001d.jpg) -U U-series slave I/O module (71.8 mm X 138 mm) ![](.hsl-ai16ao2-m-vv-av-manual-4/704ea94b91002c1d71f27f15c297384e8584b0e8ea1024a3e17e7344bf4cddaf.jpg) # 3.2 Terminal Base # Available terminal bases include: ▶ HSL-TB32-U-DIN ▶ HSL-TB64-DIN ▶ HSL-TB32-M-DIN ▶ HSL-TB32-MD # Features ▶ Field I/O wiring connection for HSL I/O modules ▶ Screw- or spring-type terminal for easy field wiring ▶ Power and ground connections for each signal channel ▶ Interlocking design for installation in rugged environments ▶ Power LED indicator ▶ DIN rail mounting ▶ Onboard terminator resistor # 3.2.1 General Description
Model NameSpecificationsSupports
For DB SeriesHSL-TB32-U(1): 32 channels direct connected terminal baseAll HSL DB-series modules
(2): One DB slot
HSL-TB64(1): 64 channels direct connected terminal baseAll HSL DB-series modules
(2): Two DB slots
For M SeriesHSL-TB32-M32 channels direct connected terminal base for HSL M-series moduleAll HSL M-series modules
HSL-TB32-MD
# 3.2.2 Jumper Settings Since HSL is a serial transmission system, a terminator must be placed at the end of the cable. Each TB has an onboard jumper selectable terminator. The terminator must be enable only by the last module. Not the last module (Default) ![5 3 1\nOFF ON\n6 4 2](.hsl-ai16ao2-m-vv-av-manual-4/f62c041356b5199e8b6b9e3e05090dd75f690b2368ecb99c789951b8fc42594f.jpg) The last module ![5 3 1\nOFF ON\n6 4 2](.hsl-ai16ao2-m-vv-av-manual-4/5d1c908b0a0199ffb65b11a6921fb1ea7cb8d319cb302bb66b8bf342d00a4655.jpg) # 3.2.3 HSL-TB32-MD Jumper Settings JP1,2 (External Power Option) ![1 2 3\n1 2 3](.hsl-ai16ao2-m-vv-av-manual-4/fe4ef785918c689c1d23ca7b797dbaa8ff7433a7a9c3dd84b91d57bcb66ccd05.jpg) 1, 2 short: Different Power (Default) 2, 3 short: Common Power JP3 (Tx Terminal Resistor) ![ON\n3\n2\n1\nOFF\nOFF is default setting](.hsl-ai16ao2-m-vv-av-manual-4/5446e9652b31b226ebb6187feff74c6a451c1b119ab8eacb5d77f93ec9fac4f1.jpg) JP4 (Rx Terminal Resistor) ![ON\n3\n2\n1\nOFF\nF is default setting](.hsl-ai16ao2-m-vv-av-manual-4/2e5e0879195d804ccc08d6748131dc1d6cad34b23b873a54959d646dd95208dc.jpg) JP5 (Fuse Option) ![1 2 3\nON OFF](.hsl-ai16ao2-m-vv-av-manual-4/8d4ad13be0c59c3d4c9aaefcc802bba2e86ad2abb8aabec482f330159bd77bcc.jpg) 1, 2 short: With Fuse 2, 3 short: Without Fuse (Default) # 3.2.4 Dimensions -DB with HSL-TB32-U-DIN (126 mm x 120.1 mm x 107.3 mm) ![126\n120](.hsl-ai16ao2-m-vv-av-manual-4/7d4890649124a60241d3c8655ec41cfb57c721f0f7d72127df49c66181cb2945.jpg) ![Technical line drawing of a mechanical assembly with spring-loaded components (no text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/6516b18b92b1d625e7d8163a478282ba8f6306e6b6c89d788cb5851236737441.jpg) ![10.5\n6.4](.hsl-ai16ao2-m-vv-av-manual-4/0068f9e1d633a514505adf20d878ce5faf6a09a16e5fdefa9ee24c54872115b7.jpg) -DB with HSL-TB64-DIN (168.7 mm x 120.1 mm x 107.3 mm) ![168.7\n120.1](.hsl-ai16ao2-m-vv-av-manual-4/469b60614e1fee39eef674fa43e9d926900559c7a5348c9f31bf81eae4072806.jpg) ![Technical line drawing of a mechanical assembly with spring-loaded components and a 107.1 dimension label (no text or symbols beyond measurement)](.hsl-ai16ao2-m-vv-av-manual-4/3f2b708baf294ea55dbc5d02b070c29d2185f8910db46f4341daf83040ac60ef.jpg) ![6.51\n8.3](.hsl-ai16ao2-m-vv-av-manual-4/903d22b885aa20131637681a97e6554ac1cc9e37bc2934a0d7ae860dddcacd0e.jpg) -M module with HSL-TB32-M-DIN (128.5 mm x 85.5 mm x 108 mm) ![128.5\n85.5](.hsl-ai16ao2-m-vv-av-manual-4/5e7aa8d1e92dec009459eb3632161c6d46bf7f4fd5d5b046d159f1375896c62a.jpg) ![Pure technical line drawing of a mechanical assembly without any text, numbers, or symbols](.hsl-ai16ao2-m-vv-av-manual-4/9190f04aa9e3ccc1c33d54a6e59200a92a736404040858fef7e9898842e632b4.jpg) ![95.7\n108](.hsl-ai16ao2-m-vv-av-manual-4/157ebbe818c105267c3cab7f6cdbf486123cc35e506dd05a8383882270c2f2b1.jpg) -HSL-TB32-MD (129 mm x 107 mm) ![107\n129](.hsl-ai16ao2-m-vv-av-manual-4/7dbc9f42c78648d9fbef6c91f6c25e9281bac24d60bf82447b35ce2355dca8aa.jpg) # 3.3 HSL-HUB/Repeater # Available HSL-HUB/Repeater includes: ▶ HSL-HUB ▶ HSL-Repeater # Features ▶ Master to HUB, HUB to HUB, HUB to Slave link styles ▶ Supports T-bracing connection/Star connection (subsystem concept) ▶ Supports up to 2.4 km wiring distance via seven HSL-HUB/Repeater modules ▶ One input port with three output segment ports ▶ Jumper configurable 3/6/12 Mbps transmission speed ▶ Jumper configurable full and half duplex transmission modes ▶ RJ-45 phone jack for easy installation ▶ 24 VDC input # 3.3.1 General Description ![The image presents a comparison diagram illustrating two different configurations for a battery system.\n\n**Top Section:**\n* **Text:** 'Without HSL-HUB'\n* **Left Label:** 'Master Controller' (yellow box) connected via a complex network of blue pipes to the battery modules.\n* **Right Label:** An orange box labeled 'Add One More' sits near the end of the piping run.\n* **Annotations:** Purple dashed lines labeled 'B' and 'A' indicate connection points near the 'Add One More' box.\n\n**Bottom Section:**\n* **Text:** 'With HSL-HUB'\n* **Left Label:** 'Master Controller' (yellow box) connected via orange pipes and blue hub components to the battery modules.\n* **Right Label:** An orange box labeled 'Add One More'.\n* **Right Annotation:** A blue starburst graphic containing the text 'Excellent' is connected by a red dashed line to the 'With HSL-HUB' text.](.hsl-ai16ao2-m-vv-av-manual-4/c614f0aeea1af9d14fa91622408f2e82b76620c1cf086e9df42ba7fdadda28de.jpg) # 3.3.2 Jumper Setting FD/HD setting JP\*(0 to 3), JFH1 Full Duplex (default) ![FD HD\nJP*\nFD HD\nJFH1](.hsl-ai16ao2-m-vv-av-manual-4/e638325e8d89812d76280816dd8bc253303ce9f3d07f717b41470c0e33866f5c.jpg) Half Duplex ![FD HD\nJP*\nFD HD\nJFH1](.hsl-ai16ao2-m-vv-av-manual-4/2e864ccf946d01ae0d80e2e7727c98c342bd79025c16ee02f87ece74987926c4.jpg) 3/6/12 Mbps setting: JBPS1 ![Abstract geometric pattern with black rectangles and white outlines on a white background (no text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/1e8951c1b4b168e599a8416806eef2fda1dfaa472cf5856b291fe3754e2a2859.jpg)
1 – 3 and 2 – 412 Mbps
1 – 3 and 4 – 66 Mbps (default)
3 – 5 and 2 – 43 Mbps
3 – 5 and 4 – 6EXC
# 3.3.3 Dimensions HSL-HUB ![72\n80](.hsl-ai16ao2-m-vv-av-manual-4/e376300ba25fd91f1d6f0c4c91e874aa8b5489e14ec2a9c40dd494364efd0de6.jpg) HSL-Repeater ![72\n48](.hsl-ai16ao2-m-vv-av-manual-4/01f1184f44408e38879c3960107d0eec69b3a4f159e569ee06bd12509c513080.jpg) # 3.4 Managing Slave Index in an HSL Network # 3.4.1 Before you proceed Before powering on the slave modules, you have to adjust the DIP switch. For more information, refer to section 3.1.6. Take note of the following: 1. A master controller can connect up to 63 slave indexes. For example, the PCI-7852 has two master controllers. Therefore, it supports a maximum 126 slave indexes. 2. The more compact the slave addresses are in an HSL network, the greater efficiency. 3. Observe the discrete I/O and relay module rule.
ModuleSlave Index OccupationTransmission ModeTransmission Speed
HSL-DI16DO16-M-NN/NP/PN/PP1 (Any address)Full Duplex (Fixed)6 Mbps (Fixed)
HSL-DI16DO16-DB-NN/NP/PN/PP
HSL-R8DI16-M-N/P
HSL-DI8-L-N/P
HSL-DO8-L-N/P
HSL-DI4DO4-L-NN/NP/PN/PP
HSL-DI16-UL
HSL-DI16DO16-UJ/US
HSL-DI32-M-N/P2 (Consecutive from odd number)
HSL-DI32-DB-N/P
HSL-DO32-M-N/P
HSL-DO32-DB-N/P
4. Observe the analog I/O and thermocouple module rule.
ModuleSlave Index OccupationTransmission ModeTransmission Speed
HSL-AI16AO2-M-VV2 (Leap number)Full Duplex (Fixed)3/6/12 Mbps Selectable
HSL-AI16AO2-M-AV
HSL-AO4-U
# Observe the motion control module rule
ModuleSlave Index OccupationTransmission ModeTransmission Speed
HSL-4XMO-CG-N/P4 (Leap) / 4(Consecutive)Full Duplex / Half Duplex3/6/12 Mbps Selectable
HSL-4XMO-CD-N/P
# 5. Special rules ▷ If you will install only one HSL-AI16AO2-M-VV or HSL-AI16AO2-M-AV and the DIP switch is set to 1 (HSL-AI16AO2-M-VV/AV only supports full duplex mode), the occupied indexes will be 1 and 3. You must assign the parameter “max\_slave\_No” of HSL\_start(...) as 4 to ensure correct communication. You may ignore this rule when using the HSL\_auto\_start function. If you will install only one HSL-4XMO-CG-N/P or HSL-4XMO-CD-N/P and the DIP switch is set as to 1 and full duplex mode, the occupied indexes will be 1, 3, 5, and 7. You must assign the parameter "max\_slave\_No" of HSL\_start(...) as 8 to ensure correct communication. You may ignore this rule when using the HSL\_auto\_start function. In half duplex mode, these modules occupy 1, 2, 3 and 4. Therefore, you must assign the "max\_slave\_No" of HSL\_start(...) as 4 or call the HSL\_auto\_start function. # 3.4.2 Examples The following examples are provided for user reference. All modules used are set in full duplex mode. # Example 1 Provided you installed two HSL-DI16DO16, two HSL-DI32-M-N, and an HSL-AI16AO2-VV with all slave modules in full duplex mode, you can have two conditions as follows: Condition 1: HSL-AI16AO2-VV operates at 6 Mbps. We recommended that you use the provided slave index configuration.
ItemDIP SwitchIndex Occupation in HSL
HSL-DI32-M-N #111, 2
HSL-DI32-M-N #233, 4
HSL-AI16AO2-VV55, 7
HSL-DI16DO16 #166
HSL-DI16DO16 #288
This is an example of a compact composition. The scan time needs 30.33 $\mu$ s x 8 at 6 Mbps, full duplex mode. Users can connect the modules with one master controller. Condition 2: HSL-AI16AO2-VV operates at 12 Mbps. We recommended that you use the provided slave index configuration.
ItemDIP SwitchIndex Occupation in HSL
HSL-DI32-M-N #111, 2
HSL-DI32-M-N #233, 4
HSL-DI16DO16 #155
HSL-DI16DO16 #266
Another example of a compact composition. The scan time needs 30.33 $\mu$ s x 6 at 6 Mbps, full duplex mode. You may connect these modules with one master controller. The HSL-AI16AO2-M-VV module connects to another master controller. The DIP switch of HSL-AI6AO2-M-VV is assigned as 1. Because of the special rule, users have to assign the "max\_slave\_No" of HSL\_start(...) as 3 or call HSL\_auto\_start by connect\_index #1. The illustration below explains this. HSL-DI16DO16x2, HSL-DI32-M-Nx2 HSL-AI16AO2-M-VV 6 Mbps ![The image displays four horizontal red lines, each featuring arrowheads at both ends pointing outward. These lines are arranged in a vertical stack, parallel to one another.](.hsl-ai16ao2-m-vv-av-manual-4/6e8f46b8445355e2ca77705ccb5a0c808333d8b97ad1aae24c05ea4186dd8241.jpg) 12 Mbps ![Close-up of a green printed circuit board with various electronic components (no visible text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/e78cb2aac3ffd0bd41255eed6383623d3a99d1635910761197b382bb6ddf28e7.jpg) Consequently, the cycle time of the first master controller is $30.33\mu s \times 6$ and the cycle time of the second master controller is $45.5\mu s$ at 12 Mbps, full duplex mode. # Example 2 Provided you installed two HSL-DI16DO16-UJ, one HSL-DI16DO16-M-NN, two HSL-DO32-M-N, one HSL-AI16AO2-VV, and two HSL-4XMO-CG-N with all slave modules in full duplex mode, you can have the following conditions: Condition 1: The HSL-AI16AO2-VV and two HSL-4XMO-CG-N operate in 6 Mbps. We recommended that you use the provided slave index configuration.
ItemDIP SwitchIndex Occupation in HSL
HSL-4XMO-CG-N #111, 3, 5, 7
HSL-4XMO-CG-N #222, 4, 6, 8
HSL-DO32-M-N #199, 10
HSL-DO32-M-N #21111, 12
HSL-AI16AO2M-VV1313, 15
HSL-DI16DO16-UJ #11414
HSL-DI16DO16-UJ #21616
HSL-DI16DO16-M-NN1717
The scan time needs 30.33 $\mu$ x 17 at 6 Mbps, full duplex mode. You can connect these modules with one master controller. Condition 2: An HSL-AI16AO2-VV and two HSL-4XMO-CG-N modules operate at 12 Mbps. We recommended that you use the provided slave index configuration.
Group 1DIP SwitchIndex Occupation in HSL
HSL-DO32-M-N #111, 2
HSL-DO32-M-N #233, 4
HSL-DI16DO16-UJ #155
HSL-DI16DO16-UJ #266
HSL-DI16DO16-M-NN77
The scan time needs 30.33 $\mu$ s x 7. You may connect these modules with one master controller. The HSL-AI16AO2-M-VV and two HSL-4XMO-CG-N modules connect to another master controller. The management table below is for reference.
Group 2DIP SwitchIndex Occupation in HSL
HSL-4XMO-CG-N #111, 3, 5, 7
HSL-4XMO-CG-N #222, 4, 6, 8
HSL-AI16AO2-M-VV99, 11
Refer to the illustration below. Group 1 Group 2 6 Mbps ![The image displays three horizontal red lines stacked vertically. Each line features arrowheads at both ends pointing outward. There is no text in the image.](.hsl-ai16ao2-m-vv-av-manual-4/82e6a97dd11a4a2d5f50b701bd80e1f0c813217e22aa9891da5c8d1373be47b1.jpg) ![Close-up of a green printed circuit board with various electronic components (no visible text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/037fc9ef4006f1d9f92e5fb2e7aeeb2be5ffaff25acaab10da451f56ac4c0ec9.jpg) 12 Mbps The cycle time of the first master controller is $30.33\mu s \times 7$ , while the cycle time of second master controller is $15.17\mu s \times 11$ at 12 Mbps, full duplex mode. # 4 HSL LinkMaster Utility After installing the master controller and slave modules, you are now ready to install the HSL driver and the LinkMaster utility for system testing and debugging. This utility features a user-friendly interface that enables you to easily test I/O statuses, including read/write the I/O data, calibration and motion control. It is recommended that you use this utility before implementing the whole system. # 4.1 Software Installation You can install the HSL drivers from the ADLINK All-in-One CD that comes with the package or you may download the drivers from the ADLINK website. The latest driver version are available from the website. To install the HSL drivers: 1. Locate, then double-click the SETUP.exe file from the All-in-One CD. The installation window appears. Click Next. ![ADLINK PCI-7851/52 for Windows 9x/NT/2000/XP v3.43\nWelcome\nWelcome to the PCI-7852 Setup program. This program will install PCI-7852 on your computer.\nIt is strongly recommended that you exit all Windows programs before running this Setup program.\nClick Cancel to quit Setup and then close any programs you have running. Click Next to continue with the Setup program.\nWARNING: This program is protected by copyright law and international treaties.\nUnauthorized reproduction or distribution of this program, or any portion of it, may result in severe civil and criminal penalties, and will be prosecuted to the maximum extent possible under law.\n( Back Next ) Cancel](.hsl-ai16ao2-m-vv-av-manual-4/6722ef8db9acdd359f11528b887e27823cf40768e4951fb9c6213047f33485bf.jpg) 2. Follow screen instruction to install. 3. Restart the system when the installation process is completed. # 4.2 ADLINK HSL LinkMaster Utility # 4.2.1 Launching the LinkMaster Utility After installing the drivers, click Start > PCI-7853 > LinkMaster to launch the LinkMaster utility. The main window appears. ![ADLINK HSL Master Utility\nVersion : 3.5\nCard Information :\nCurrent Select Card ID: Card ID 0 Current Select Connect Index: CN 0\nSpeed\n○ 3M\n● 6M\n○ 12M\nAll Slave ID Connection Test Connect status Hub Num Duplex\n0 Full Half\nGeneral Slave Selection DIBDO8\nConnect / Auto Scan Slaves Disconnect Status Msg: Slaves Disconnect !\nAddress Model Description\nTest Slave\nExit\nAbout](.hsl-ai16ao2-m-vv-av-manual-4/694a2d73a8b8787100b7add8b9447d78464e28667fc16ff2b5c930fdaeaffd44.jpg) # 4.2.2 Before you proceed 1. LinkMaster is a testing and debugging program based on VB 6.0 and is only available for Windows® 98/NT/2000/XP environments with a monitor that has a screen resolution of 800x600 or higher. The utility does not support DOS environment. 2. The LinkMaster version control may be found on the top-right corner of the main window. 3. Any slave modules may be tested with this utility, including discrete I/O, analog I/O, thermocouple module, and motion control modules. For motion control utility and manipulation, refer to the HSL-4XMO user's manual. # 4.2.3 LinkMaster Utility Introduction Below is the LinkMaster main user interface labeled according to function. ![ADLINK HSL Master Utility\nVersion : 3.5\nA.\nCard Information :\nCurrent Select Card ID: Card ID 0 Current Select Connect Index: CN 0\nB. All Slave ID Connection Test Connect status C. Hub Num Duplex\nF General Slave Selection DI8DO8 Full Half\nG. Connect / Auto Scan Slaves Disconnect H. Status Msg: Slaves Disconnect !\nAddress Model Description\nI.\nE. Speed\n○ 3M\n○ 6M\n○ 12M\nJ. Test Slave\nExit\nL. About](.hsl-ai16ao2-m-vv-av-manual-4/2650c8b4798aba1340f9380dba52c3d65b2936587dba6c0864d3ca91a3fec89f.jpg) ▶ A. Select card ▶ B. Network quality test ▶ C. Set hub number (Only for 7853/54) ▶ D. Set duplex mode (Only for 7853/54) ▶ E. Set speed mode (Only for 7853/54) ▶ F. General slave selection ▶ G. Auto scan slave modules ▶ H. Show software information ▶ I. Show module information ▶ J. Test slave module ▶ K. Exit motion creator ▶ L. Version information Below are descriptions of the main interface buttons. 1. Current Select Card ID. When LinkMaster is activated, it searches all HSL master control cards installed in the system, such as PCI-7853, PCI-7854 and PMC-7852/G. Every card shows its index (ID) ranging from 0 to?. You can use this function to specify which card you want to operate. 2. Current Select Connect Index. For cards with two master controllers such as PCI-7854 and PMC-7852/G, the connect index ranges from 0 to 1. For single master controller such as PCI-7853, the connect index is 0. Refer to the diagram below. Connect Index 0 Connect Index 1 ![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.hsl-ai16ao2-m-vv-av-manual-4/c1ee81bc7e95e2045a1c2dcce1139d6d2c588a36d2e19ca7cf48a79fdcfb0256.jpg) PCI-7854 3. ALL Slave ID Connection Test. The screen capture below shows a live scan of all I/O modules for network quality test. The LinkMaster lets you check the network environment. Start the test by clicking on the Test button. Press Stop to stop scanning. When you start the test, the utility continuously tests each ID and shows the module type to left-column labels. Right-column labels show the counter for communication error. ![HSL Network Quality Testing\nSlave Live Scan\nTest Stop Exit\nErrors Module Type Errors Module Type Errors Module Type\nID1 ID22 ID43\nID2 ID23 ID44\nID3 ID24 ID45\nID4 ID25 ID46\nID5 ID26 ID47\nID6 ID27 ID48\nID7 ID28 ID49\nID8 ID29 ID50\nID9 ID30 ID51\nID10 ID31 ID52\nID11 ID32 ID53\nID12 ID33 ID54\nID13 ID34 ID55\nID14 ID35 ID56\nID15 ID36 ID57\nID16 ID37 ID58\nID17 ID38 ID59\nID18 ID39 ID60\nID19 ID40 ID61\nID20 ID41 ID62\nID21 ID42 ID63](.hsl-ai16ao2-m-vv-av-manual-4/3da5abf590b5cfa35da002cb69e0f471de6e2560bc5283b36365099d5667871e.jpg) 4. Connect/Auto Scan. Clicking this button allows the utility to scan all slave modules connected to the master card with specified connect index. The utility shows all the slave modules' information including the address and slave type within the 9th block. 5. Slaves Disconnect. Click this to stop the utility from scanning all the slave modules and to disconnect them. 6. Status Msg. Checks if the slave modules are connected or disconnected. Test Slave: While all connected slave modules list in 9th block, you can use this function to activate the testing dialog. For example, when you connect the HSL-DI16DO16-MNN, you will see this module from the screen. Clicking on it will show a window from where you can test and debug the modules. 7. Exit. Click to close the utility. 8. About. Shows the DLL version information. The succeeding sections outline the usage of the slave module utility. # 4.2.4 HSL-DI16DO16 Utility 1. Slave Address. Shows the slave index occupied by the module. 2. Digital Input. A white circle indicates no digital input; a red icon indicates that the digital input is not activated. 3. Digital Output. Click on the icon to activate the digital output. Red icon indicates that the digital output is turned on, and vice-versa. 4. Slave Status: Shows the communication status between the slave module and the master card. The functions definition are enumerated below. ▷ Bit 0 is Data\_Req bit. ▷ Bit 2 is for CHK1. When Bit2 is equal to 1, a communication error occurred once). ▷ Bit 3 is for CHK3. When Bit3 is equal to 1, a communication error occurred three times. ▷ Bit 4, Bit 5 and Bit 6 bits are for CHK7. WhenBit4, Bit5, and Bit6 are all equal to 1, a communication error occurred seven times. # 4.2.5 HSL-DI32 and HSL-DO32 Utility ![HSL DI32 Sample Program\n(( HSL DI32 Module Utility ))\nState Address : 11\nDigital Input\nCH15 CH0\nCH31 CH16\nCommunication Status\n4 Bit7 Bit6 Bit5 Bit4 Bit 3 Bit 2 Bit1 Bit 0\nCHK. NO. Data_Req\nExit](.hsl-ai16ao2-m-vv-av-manual-4/ffb0221a5d6b2c032334c545e3233fa5e25534161f285b3d87759740c8028294.jpg) ![HSL DO32 Sample Program\n(( HSL DO32 Module Utility ))\nStart Address: 5\nDigital Output\nCH15 CH0\nCH31 CH16\nCommunication Status\n4 Bit7 Bit6 Bit5 Bit4 Bit 3 Bit 2 Bit1 Bit 0\nCHK. NO. Data_Req\nExit](.hsl-ai16ao2-m-vv-av-manual-4/1fccec3ad0623170f1ba3c4b80e6170084e738fcb92c40b5e63698bbb2d30850.jpg) 1. Slave Address. Shows the slave index occupied by the module. These modules occupy two slave indexes starting from an odd number. For example, when you adjust the DIP switch to 3, the modules are assigned indexes 3 and 5. 2. Digital Input. A white circle indicates no digital input; a red icon indicates that the digital input is not activated. 3. Digital Output. Click on the icon to activate the digital output. Red icon indicates that the digital output is turned on, and vice-versa. 4. Slave Status: Shows the communication status between the slave module and the master card. The functions definition are enumerated below. ▷ Bit 0 is Data\_Req bit. ▷ Bit 2 is for CHK1. When Bit2 is equal to 1, a communication error occurred once). ▷ Bit 3 is for CHK3. When Bit3 is equal to 1, a communication error occurred three times. ▷ Bit 4, Bit 5 and Bit 6 bits are for CHK7. WhenBit4, Bit5, and Bit6 are all equal to 1, a communication error occurred seven times. # 4.2.6 HSL-DI8/HSL-DO8/HSL-DI4DO4 Utility ![HSL DI6DO16 Module Utility\n(( HSL DI8DO8 Module Utility))\nSlave Address : 1\nDigital Input\n2 Ch 7\nCh 0\nDigital Output\n3 Ch 7\nCh 0\nSlave Status\n4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0\nCHK. NO.\nData_Req\nExit](.hsl-ai16ao2-m-vv-av-manual-4/a9c70fe92eee6e21fcda49405ed8ed03437cb7ab0e5949f9031da4f5d80fa41b.jpg) 1. Slave Address. Shows the slave index occupied by the module. These modules occupy only one slave index. 2. Digital Input. A white circle indicates no digital input; a red icon indicates that the digital input is not activated. 3. Digital Output. Click on the icon to activate the digital output. Red icon indicates that the digital output is turned on, and vice-versa. 4. Slave Status: Shows the communication status between the slave module and the master card. The functions definition are enumerated below. ▷ Bit 0 is Data\_Req bit. ▷ Bit 2 is for CHK1. When Bit2 is equal to 1, a communication error occurred once). ▷ Bit 3 is for CHK3. When Bit3 is equal to 1, a communication error occurred three times. ▷ Bit 4, Bit 5 and Bit 6 bits are for CHK7. WhenBit4, Bit5, and Bit6 are all equal to 1, a communication error occurred seven times. # 4.2.7 HSL-R8DI16 Utility ![HSL R8DI16 Test Module Utility\n(( HSL R8DI16 Module Utility ))\nSlave Address : 7\nDigital Input\nCh 15\nCh 0\nDigital Output\nCh 7\nCh 0\nSlave Status\n4 Bit 7\nBit 6\nBit 5\nBit 4\nBit 3\nCHK3\nBit 2\nCHK1\nBit 1\nBit 0\nData_Req\nCHK. NO.\nExit](.hsl-ai16ao2-m-vv-av-manual-4/606dfe7245c9b4a199d4a1b23fba4a91df657dc314889e947dc1d453b558eb2e.jpg) 1. Slave Address. Shows the slave index occupied by the module. These modules occupy only one slave index. 2. Digital Input. A white circle indicates no digital input; a red icon indicates that the digital input is not activated. 3. Digital Output. Click the icon to activate digital output. This function turns the relay ON or OFF. A red circle indicates that the relay is on, and vice versa. 4. Slave Status: Shows the communication status between the slave module and the master card. The functions definition are enumerated below. ▷ Bit 0 is Data\_Req bit. ▷ Bit 2 is for CHK1. When Bit2 is equal to 1, a communication error occurred once). ▷ Bit 3 is for CHK3. When Bit3 is equal to 1, a communication error occurred three times. ▷ Bit 4, Bit 5 and Bit 6 bits are for CHK7. WhenBit4, Bit5, and Bit6 are all equal to 1, a communication error occurred seven times. # 4.2.8 HSL-AI16AO2 Utility ![HSL AI16AO2-AV Slave Module Utility\nSlave Address: 11\nAttribute Setting\nSignal Type: Single Ended Input\nSignal Range: +10mA\nFirmware Version\n65\nAI Signal Reading Start...\nCH 0 -0.0024 mA CH 8 -0.0014 mA\nCH 1 -0.0003 mA CH 9 -0.0014 mA\nCH 2 -0.0014 mA CH 10 -0.0024 mA\nCH 3 -0.0003 mA CH 11 0.0003 mA\nCH 4 -0.001 mA CH 12 -0.0014 mA\nCH 5 -0.0017 mA CH 13 -0.0017 mA\nCH 6 -0.0007 mA CH 14 -0.0007 mA\nCH 7 -0.0021 mA CH 15 -0.0003 mA\nA2 Function\nAO Value\nCH 0 0.0 V SEND\nCH 1 0.0 V SEND\n6\nConfiguration\nStart Read\nStop Read\nCalibration\nExit\nSlave Status\nBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0\nCHK. NO.\nData_Reg](.hsl-ai16ao2-m-vv-av-manual-4/e8ced1b5361601a20d83dce2871f85d2caab00ae9a01d3c0d6da1b5bc1418be4.jpg) 1. Slave Address. Shows the slave index occupied by the module. The module occupies two consecutive indexes. For example, when you adjust the DIP switch to 4, the module obtains slave indexes 4 and 6. 2. Signal Type. Indicates the module's signal type. 3. Signal Range. Allows selection of the signal range. The utility offers four ranges including ±10V, ±5V, ±2.5V and ±1.25V for HSL-AI16AO2-M-VV. For HSL-AI16AO2-M-AV, the signal ranges are 20 mA, 10 mA, and 5 mA. 4. Firmware Version. Shows the latest firmware version. 5. AO Function. Key in the analog output value in the text box, then press SEND to trigger the AO. The range is $\pm10$ V. 6. Configuration. Allows you to check if the signal range is correct before clicking on the Start Read button. The Configuration button allows you to save the information and complete the configuration task. 7. Start Read. Enables the A/D conversion task to read back the analog input values. The values are shown in the 12th block. 8. Stop Read. Disables the A/D conversion task. 9. Calibration. Calibrates the module. The modules are shipped with correct calibration. Refer to Appendix C if you want to recalibrate the module. 10.Exit. Closes the utility. 11. Slave Status: Shows the communication status between the slave module and the master card. The functions definition are enumerated below. ▷ Bit 0 is Data\_Req bit. ▷ Bit 2 is for CHK1. When Bit2 is equal to 1, a communication error occurred once). ▷ Bit 3 is for CHK3. When Bit3 is equal to 1, a communication error occurred three times. ▷ Bit 4, Bit 5 and Bit 6 bits are for CHK7. WhenBit4, Bit5, and Bit6 are all equal to 1, a communication error occurred seven times. # 4.2.9 HSL-4XMO Utility Refer to the HSL-4XMO user's manual. # 5 HSL Function Library This chapter describes the functions for developing programs in C, C++, or Visual Basic. # 5.1 List of Functions This section presents all the functions. The function prototypes and common data types are declared in HSL.h. It is recommended that you use these data types in your application programs. The following table shows the data type names and their ranges.
Type NameDescriptionRange
U88-bit ASCII character0 to 255
I1616-bit signed integer-32768 to 32767
U1616-bit unsigned integer0 to 65535
I3232-bit signed long integer-2147483648 to 2147483647
U3232-bit unsigned long integer0 to 4294967295
F3232-bit single-precision floating-point-3.402823E38 to 3.402823E38
F6464-bit double-precision floating-point-1.797683134862315E308 to 1.797683134862315E309
BooleanBoolean logic valueTRUE, FALSE
All HSL function calls were revised. Refer to the mapping table in Appendix B. All function calls have the same prefix HSL\_. The function belonging to a system level purpose has the following form: HSL\_{action\_name}. e.g. HSL\_initial(). If they belong to a discrete I/O module purpose, the function is as follows: HSL\_D\_{action\_name}. e.g. HSL\_D\_read\_input() If they belong to an analog I/O module purpose, the function is as follows. HSL\_A\_{action\_name}. e.g. HSL\_A\_write\_output(). If they belong to a motion control module purpose, the function is as follows. HSL\_M\_{action\_name}. e.g. HSL\_M\_start\_tr\_move(). For the motion control library description, refer to the HSL-4XMO function library manual. This section contains the system level function, discrete I/O control, and analog I/O control. Initialization and System Information, Section 5.2
Function NameDescription
HSL_initialMaster card initialization
HSL_intial_swInitialize by system automatically (sw_enable=0) or manually via the S1 dip switch (sw_enable=1) (7853/54 only)
HSL_closeRelease all resources occupied by master card
HSL_startStart to scan all the slave modules connected to master card
HSL_auto_startStart to scan and automatically detect all the slave modules connected to master card
HSL_stopStop scanning the connected slave modules
HSL_set_scan_conditionSet scanning conditions (only for 7853/54)
HSL_get_scan_conditionGet scanning conditions (only for 7853/54)
HSL_connect_statusGet the communication status of the specified slave module
HSL_slave_liveGet the module status of the slave module
HSL_get_irq_channelGet the IRQ occupied by master card
Timer Control, Section 5.3
Function NameDescription
HSL_enable_timer_interruptEnable timer interrupt of master card (For 7851/52)
HSL_disable_timer_interruptDisable timer interrupt of master card (For 7851/52)
HSL_set_timerSet the resolution of timer (For 7851/52)
HSL_set_int_timerSet the timer parameters (For 7853/54)
HSL_set_int_timer_enableEnable/Disable timer interrupt of master card (For 7853/54)
HSL_wait_timer_interruptWait timer event (For 7853/54)
Discrete I/O, Section 5.4
Function NameDescription
HSL_D_read_inputRead back all discrete I/O with unsigned 32-bit
HSL_D_read_channel_inputRead back discrete I/O by channel selection
HSL_D_write_outputWrite all discrete I/O with unsigned 32-bit
HSL_D_write_channel_outputWrite discrete I/O by channel selection
HSL_D_read_ouputRead back the output value stored in RAM
HSL_D_read_all_slave_inputRead back all inputs of slave modules
HSL_D_write_all_slave_outputWrite all outputs of slave modules
HSL_D_set_input_logicSet the logic of digital input
HSL_D_set_output_logicSet the logic of digital output
HSL_D_set_int_renewal_typeSet DI renewal check type (Only for 7853/54)
HSL_D_set_int_renewal_bitSet the data bits of DI renewal check for each slave (Only for 7853/54)
HSL_D_set_int_controlSet DI interrupt enable or disable (Only for 7853/54)
HSL_D_wait_di_interruptWait DI renewal event(Only for 7853/54)
Analog I/O, Section 5.5
Function NameDescription
HSL_A_start_readStart A/D conversion.
HSL_A_stop_readStop A/D conversion
HSL_A_set_signal_rangeSet the signal range of analog input channels
HSL_A_get_signal_rangeGet the signal range of analog input channels
HSL_A_get_input_modeGet the signal input mode
HSL_A_set_last_channelSet the last channel of analog input channels
HSL_A_get_last_channelGet the last channel of analog input channels
HSL_A_read_inputRead back the value of analog input channels
HSL_A_write_outputSend out the analog output
HSL_A_read_outputRead back the analog output data
HSL_A_sync_rwRead and write the data synchronously
HSL_A_get_versionGet the kernel version of analog I/O module
Pulse Stretcher Function (HSL-DI16-UL only), Section 5.6
Function NameDescription
HSL_D_set_di_latch_functionSet DI-ltech function for one channel
HSL_D_set_di_latch_functionASet DI-latch function for all channels
HSL_D_get_di_latch_functionRetrieve DI-latch function
# 5.2 Initialization and System Information # @ Name HSL\_initial - Master board initialization HSL\_close – Release all resource occupied by master board HSL\_start - Start to scan all slave module connected to master board HSL\_auto\_start - Start to scan and automatically detect all the slave modules connected to master card HSL\_stop -Stop scanning the connected slave modules HSL\_set\_scan\_condition - Set scanning conditions (7853/54 only) HSL\_get\_scan\_condition - Get scanning conditions (7853/54 only) HSL\_connect\_status - Get the communication status of the specified slave module HSL\_slave\_live - Get the module status of the slave module HSL\_get\_irq\_channel - Get the IRQ occupied by master card # @ Description HSL\_initial: Initializes the hardware and software states of the HSL master card (PCI-7851/52 or PMC-7852/G). You can check the return code of this function to know if the initialization is successful or not. Since the HSL master card is plug-and-play, the base address and IRQ level are automatically assigned by the BIOS. HSL\_close: Releases the resource occupied by the HSL master card. When terminating the program, do not forget to call this function to release all the resource occupied by the HSL master card. HSL\_start: Scans the total connected slave modules. You can assign the number of slave indexes the HSL master board will scan. # HSL\_auto\_start: Automatically detects the total connected slave modules. Every master controller can connect up to 63 slave indexes. # HSL\_stop: Stops scanning the connected slave modules. # HSL\_set\_scan\_condition: Assigns the scan rate (3/6/12 Mbps) and communication types (full or half duplex). This function needs to be set up between the function HSL\_initial and HSL\_start. # HSL\_get\_scan\_condition: By this function, User can get the settings of communication types and scan rate which are set by "HSL\_set\_scan\_condition". # HSL\_connect\_status: This function is used to check the communication status between master board and slave modules. # HSL\_slave\_live: This function is used to check the status of the slave module (live or die). HSL\_get\_irq\_channel: This function is used to get IRQ assigned by system. # @ Syntax C/C++ (DOS, Windows 98/NT/2K/XP) ```c I16 HSL_initial (U16 card_ID); I16 HSL_close (U16 card_ID); I16 HSL_start (U16 card_ID, U16 connect_index, U16 max_slave_No); I16 HSL_auto_start (U16 card_ID, U16 connect_index); I16 HSL_stop (U16 card_ID, U16 connect_index); I16 HSL_set_scan_condition(I16 card_ID, I16 connect_index, I16 comm_type, I16 transfer_rate, I16 hub_number); ``` ```c I16 HSL_get_scan_condition(I16 card_ID, I16 connect_index, I16 *comm_type, I16 *transfer_rate, I16 *hub_number); I16 HSL_connect_status (U16 card_ID, U16 connect_index, U16 slave_No, U8 *sts_data); I16 HSL_slave_live (U16 card_ID, U16 connect_index, U16 slave_No, U8 *live_data); void HSL_get_irq_channel (I16 card_ID, I16 *irq_no); ``` Visual Basic (Windows 98/NT/2K/XP) ```csv HSL_initial (ByVal card_ID As Integer) As Integer HSL_close (ByVal card_ID As Integer) As Integer HSL_start (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal max_slave_No As Integer) As Integer HSL_auto_start (ByVal card_ID As Integer, ByVal connect_index As Integer) As Integer HSL_stop (ByVal card_ID As Integer, ByVal connect_index As Integer) As Integer HSL_set_scan_condition(ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal comm_type As Integer, ByVal transfer_rate As Integer, ByVal hub_number As Integer); HSL_get_scan_condition((ByVal card_ID As Integer, ByVal connect_index As Integer, comm_type As Integer, transfer_rate As Integer, hub_number As Integer); HSL_connect_status (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, sts_data as Byte) As Integer HSL_slave_live (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No as Integer, live_data as Byte) As Integer HSL_get_irq_channel (ByVal card_ID As Integer, irq_no As Integer) As Integer ``` # @ Argument card\_ID: Specify the HSL master card index. Normally, the board index sequence would be decided by the system. The index is from 0. connect\_index: For PCI-7851, the valid value is 0. For PCI-7852 and PMC-7852/G, the valid value is 0 or 1. max\_slave\_No: The maximum slave index connected to the HSL master card with the connect\_index. The valid value is from 1 to 63. slave\_No: Specify the slave module with slave index which want to perform this function. The valid value is from 1 to 63. comm\_type: Half or Full duplex 0: Half duplex 1: Full duplex transfer\_rate: transfer rate setting 1:3M 2: 6M 3: 12M hub\_number: cascaded Hub number. If no Hub in the system, the value of hub\_number is set to 0. \*sts\_data: The communication status of this slave module. The definition is as follows. ▶ Bit 0 is Data\_Req bit. ▶ Bit 2 is for CHK1. (If Bit2 is 1. It means that there is 1 time communication error). ▶ Bit 3 is for CHK3. (If Bit3 is 1. It means that there are 3 times communication errors). ▶ Bit 4, BIT 5 and BIT 6 bits are for CHK7. (If Bit4, Bit5 and Bit6 all are 1. It means that there are 7 times communication errors). \*live\_data: The module status. ▶ 1: the module is live ▶ 0: the module is die. irq\_no: IRQ occupied by master card. # @ Return Code ```txt ERR_No_Error ERR_Open_Driver_Fail ERR_Invalid_Board_Number ERR_Satellite_Number ERR_Connect_Index ``` # 5.3 Timer Control # @ Name HSL\_enable\_timer\_interrupt (7851/52 only) – Enable timer interrupt of master card HSL\_disable\_timer\_interrupt (7851/52 only) - Disable timer interrupt of master card HSL\_set\_timer (7851/52 only)—Set the resolution of timer HSL\_set\_int\_timer (7853/54 only) – Set the timer parameters HSL\_set\_int\_timer\_enable (7853/54 only) – Enable\Disable timer interrupt of master card( 7853/54 only) HSL\_wait\_timer\_interrupt (7853/54 only) – Wait timer event # @ Description HSL\_enable\_timer\_interrupt (7851/52 only): Enables the hardware timer interrupt of the master card. HSL\_disable\_timer\_interrupt (7851/52 only): Disables the hardware timer interrupt of the master card. HSL\_set\_timer (7851/52 only): This function sets up Timer 1 and Timer 2. Timer 1 and Timer 2 are used as frequency dividers to generate a dedicated constant timer interrupt sampling rate. The highest timer interrupt sampling rate of the master card may not exceed 20 KHz on Windows NT platform because of system limitation. The following example is set at 6 Mbps: If you want to have a sampling rate of 15 kHz, the function must be HSL\_set\_timer (0, 20, 20) If you want to have a sampling rate of 1.2 kHz, the function must be HSL\_set\_timer (0, 100, 50) The formula used is: Transmission speed / (c1 x c2) In addition, the values of c1 and c2 must be greater than 1. When c1=0 or c2=0, the timer interrupt stops. HSL\_set\_int\_timer (7853/54 only): Sets up the Timer parameter p1. The timer is used as frequency divider to generate a dedicated constant timer interrupt sampling rate. $$ \text { The formula is: Frequency(Hz) } = \frac {4 8 M H z}{2 5 6 \cdot (p 1 + 1)} $$ HSL\_set\_int\_timer\_enable (7853/54 only): Enables or disables the hardware timer interrupt of this master card. HSL\_wait\_timer\_interrupt (7853/54 only): Waits for the specific interrupt when you enabled the interrupt function by HSL\_set\_int\_timer\_enable() and set the timer parameter p1 by HSL\_set\_int\_timer(). When this function is running, the process never stops even if it is triggered or the function has timed out. The following codes illustrate this function. ```c I16 ret; HSL_set_int_timer(0, 0xffff); // set the parameter p1 HSL_set_int_timer_enable(0, 1); // enable the timer for(int i = 0; i < 10; i++) { ret = HSL_wait_timer_interrupt(g_cardId, 10000); if(ret == 0) // do something... else // time out } ``` # @ Syntax C/C++ (DOS, Windows 98/NT/2000/XP) ```c I16 HSL_set_timer (I16 card_ID, I16 c1, I16 c2); I16 HSL_enable_timer_interrupt (I16 card_ID, HANDLE *phEvent); I16 HSL_disable_timer_interrupt (I16 card_ID); I16 HSL_set_int_timer(I16 card_ID, U16 p1); I16 HSL_set_int_timer_enable(I16 card_ID, I16 enable); I16 HSL_wait_timer_interrupt(I16 card_ID, I32 time_out_ms); ``` Visual Basic (Windows 98/NT/2000/XP) ```c HSL_set_timer (ByVal card_ID As Integer, ByVal c1 As Integer, ByVal c2 As Integer) As Integer HSL_enable_timer_interrupt (ByVal card_ID As Integer, phEvent As Long) As Integer HSL_disable_timer_interrupt (ByVal card_ID As Integer) As Integer HSL_set_int_timer(ByVal card_ID As Integer, ByVal p1 As Integer) As Integer HSL_set_int_timer_enable(ByVal card_ID As Integer, ByVal enable As Integer) As Integer HSL_wait_timer_interrupt(ByVal card_ID As Integer, ByVal time_out_ms As Integer) As Integer ``` # @ Argument card\_ID: Specifies the HSL master card index. Typically, the board index sequence is assigned by the system. The index starts from 0. \*phEvent: Returns the handle of the timer interrupt event. The interrupt event indicates an interrupt which is generated from the master card's timer. c1: Frequency divider of Timer 1. c2: Frequency divider of Timer 2. p1: Parameter of timer $$ \text { The formula is: Frequency(Hz) } = \frac {4 8 M H z}{2 5 6 \cdot (p 1 + 1)} $$ enable: Enables (1) or disables (0) the timer interrupt time\_out\_ms: Specifies the time-out interval in milliseconds. The function returns if the interval elapses, even if the interrupt is non-signaled. If time\_out\_ms is zero, the function tests the Di state and returns immediately. If time\_out\_ms is -1, the function time-out interval does not elapse (infinite). # @ Return Code ```txt ERR_No_Error ERR_Invalid_Board_Number ERR_Timer_Parameter ERR_Close_Timer ERR_Wait_Timer_Interrupt ``` # 5.4 Discrete I/O # @ Name HSL\_D\_read\_input - Read back all discrete I/O with unsigned 32-bit HSL\_D\_read\_channel\_input - Read back discrete I/O by channel selection HSL\_D\_write\_output – Write all discrete I/O with unsigned 32-bit HSL\_D\_write\_channel\_output – Write discrete I/O by channel selection HSL\_D\_read\_output - Read back the output value stored in RAM HSL\_D\_read\_all\_slave\_input - Read back all inputs of slave modules HSL\_D\_write\_all\_slave\_output - Write all outputs of slave modules HSL\_D\_set\_input\_logic - Set the logic of digital input HSL\_D\_set\_output\_logic - Set the logic of digital output HSL\_D\_set\_int\_renewal\_type (7853/54 only) - Set DI renewal check type HSL\_D\_set\_int\_renewal\_bit (7853/54 only) – Set the data bits of DI renewal check for each DI slave module HSL\_D\_set\_int\_control (7853/54 only) – Set DI interrupt enable or disable HSL\_D\_wait\_di\_interrupt (7853/54 only) – Wait DI renewal event # @ Description HSL\_D\_read\_input: Reads the digital input value of the discrete I/O module. You must specify the connect index and slave index. HSL\_D\_read\_channel\_input: Reads the digital input value of the discrete I/O module at a specified channel. HSL\_D\_write\_output: Writes the digital output value of the discrete I/O module. You must specify the connect index and slave index. HSL\_D\_write\_channel\_output: Writes the digital output value of the discrete I/O module at the specified channel. HSL\_D\_read\_ouput: Writes all digital output values to all connected discrete I/O modules. This function maps all data into memory. With this function, you can write all digital output values to all connected discrete I/O modules at one time. HSL\_D\_read\_all\_slave\_input: Reads the digital input values from all slave I/O modules with set value of connect\_index and card no is card\_ID. This function allows you to read all digital input values from all slave I/O modules at one time. HSL\_D\_write\_all\_slave\_output: Writes the digital output values from all slave I/O modules with set value of connect\_index and card no is card\_ID. This function allows you to write all digital output values from all slave I/O modules at one time. HSL\_D\_set\_input\_logic: Sets the digital input logic to the specified slave I/O module. The slave I/O module's address is slave\_No and set value is connect\_index. HSL\_D\_set\_output\_logic: Sets the digital output logic to the specified slave I/O module. The slave I/O module's address is slave\_No and set value is connect\_index. HSL\_D\_set\_int\_renewal\_type (7853/54 only): Sets the type of hardware interrupt occurrence timing. These are. Type 1: Generates hardware interrupt when any DI data transitions are detected. (Figure 5.1) ![This diagram illustrates a 'Full Duplex Mode' sequence.\n\n**Top Section:**\n* A green arrow labeled 'DI transition' points downward to the second block.\n* A sequence of teal boxes with diagonal hatching is connected by orange arrows moving left to right: 'ID#1', 'ID#2', 'ID#3', 'ID#4', 'ID#1', 'ID#2', followed by ellipses '...'.\n* Beneath each teal box is a grey rectangular block. Below the grey block are two arrows: a red arrow pointing down labeled 'R' and a blue arrow pointing up labeled 'W'.\n\n**Bottom Section (Timing Diagram):**\n* A long purple arrow runs horizontally beneath the blocks.\n* Below that is a timing diagram labeled 'INT' on the left and 'Time' on the right.\n* Two vertical black lines connect the 'ID#4' box down to the 'INT' signal line.\n* A yellow speech bubble labeled 'Driver reset state' points to the rising edge of the 'INT' signal line.](.hsl-ai16ao2-m-vv-av-manual-4/062fced3cd4b60366221e85ad088c683f667f99421a2565cda4959be8a9981c1.jpg) Figure 5-1: Type 1 Type 2: Generates hardware interrupt when any DI data transitions are detected and when the scan cycle is completed. ![This diagram is titled **Full Duplex Mode** in the top right corner.\n\n**Top Section:**\n* A horizontal sequence of teal boxes with diagonal stripes is connected by orange arrows pointing to the right. The sequence reads: **ID#1**, **ID#2**, **ID#3**, **ID#4**, **ID#1**, **ID#2**, followed by a dotted line ending in ellipses (**......**).\n* Above the second box (**ID#2**), a green box labeled **DI transition** has an arrow pointing down towards it.\n\n**Middle Section (Vertical Connections):**\n* Below each teal box, there are two vertical arrows: a red arrow pointing down labeled **R** and a blue arrow pointing up labeled **W**.\n\n**Bottom Section:**\n* A thick purple arrow pointing right represents a timeline, labeled **Time** near the arrowhead.\n* To the left, a thin black line is labeled **INT**.\n* Two vertical black lines cross through the **INT** line and the purple timeline.\n* On the far right, a yellow arrow points to a rectangular outline labeled **Driver reset state**.](.hsl-ai16ao2-m-vv-av-manual-4/449c7aabc976f19cd57b8b19e7a6689812d2d390b351913a5438b468c0e1f956.jpg) Figure 5-2: Type 2 Type 3: Generates hardware interrupt when any DI data transitions are detected and when the scan cycle is completed. When interrupt occurs, the scan pauses until the driver resets the state. ![**Top Section:**\n* Text 'Full Duplex Mode' is in the top right corner.\n* A green box labeled 'DI transition' has an arrow pointing down towards the 'ID#2' block.\n\n**Main Sequence (Left to Right):**\n* Four blocks labeled 'ID#1', 'ID#2', 'ID#3', and 'ID#4' are arranged horizontally and connected by orange arrows pointing right.\n* Below each of these blocks ('ID#1', 'ID#2', 'ID#3', 'ID#4'), there is a red arrow pointing down labeled 'R' and a blue arrow pointing up labeled 'W'.\n* Following 'ID#4', there are double vertical lines leading into a blue box labeled 'Scan Pause'.\n* After the 'Scan Pause' box, there are double vertical lines followed by a block labeled 'ID#1' and then '....' (dotted line).\n* Below this second 'ID#1' block, there is a red arrow pointing down labeled 'R' and a blue arrow pointing up labeled 'W'.\n\n**Bottom Section (Timeline):**\n* A purple bar runs horizontally along the bottom.\n* Below the purple bar is a line labeled 'INT'. It remains solid high initially, then drops to a dotted low line during the 'Scan Pause' and subsequent phase.\n* A yellow arrow points to the dotted section of the 'INT' line, labeled 'Driver reset state'.\n* The bottom right corner is labeled 'Time' with an arrow pointing right.](.hsl-ai16ao2-m-vv-av-manual-4/43688aed9aecf28c179b0810c6c3bdcbdeb392da839824d072d802afb1374be9.jpg) Figure 5-3: Type 3 Caution: Scanning is paused while user choice the type3 of renewal type. This pause time depends on the user system performance. Consequently, when using type3, constancy(always keeping scan cycle constant) will not be maintained between scans. HSL\_D\_set\_int\_renewal\_bit (7853/54 only): Sets the Di data bits of specified modules that you want to monitor. HSL\_D\_set\_int\_control (7853/54 only): Enables or disables the DI interrupt. HSL\_D\_wait\_di\_interrupt (7853/54 only): Waits for the specific interrupt when you enable the Interrupt function by HSL\_D\_set\_int\_control() and set the renewal type and data bits on specified slave DI modules by HSL\_D\_set\_int\_renewal\_bit(), HSL\_D\_set\_int\_renewal\_type(). When this function is running, the process never stops even if triggered or the function timed out. The following codes illustrate this function. ```c I16 ret; HSL_D_set_int_renewal_type(1, 0, 1); // slave id = 1, monitor the states of bit 0 and bit 1 HSL_D_set_int_renewal_bit(1, 0, 1, 0x003); HSL_D_set_int_control(1, 0, 1); // enable ``` ```c ... // start wait ret = HSL_D_wait_di_interrupt(1, 10000); if(ret == ERR_No_Error) { // DI state trainisted and check which bits change states... } else { // time out } ... ``` # @ Syntax C/C++ (DOS, Windows 98/NT/2000/XP) ```c I16 HSL_D_write_output (I16 card_ID, I16 connect_index, I16 slave_No, U32 out_data); I16 HSL_D_write_channel_output(I16 card_ID, I16 connect_index, I16 slave_No, I16 channel, U16 out_data); I16 HSL_D_read_input (I16 card_ID, I16 connect_index, I16 slave_No, U32 *in_data); I16 HSL_D_read_channel_input (I16 card_ID, I16 connect_index, I16 slave_No, I16 channel, U16 *in_data); I16 HSL_D_read_output (I16 card_ID, I16 connect_index, I16 slave_No, U32 *out_data_in_ram); I16 HSL_D_read_all_slave_input (I16 card_ID, I16 connect_index, U16 *in_data); I16 HSL_D_write_all_slave_output (I16 card_ID, I16 connect_index, U16 *out_data); I16 HSL_D_set_input_logic (I16 card_ID, I16 connect_index, I16 slave_No, I16 input_logic); I16 HSL_D_set_output_logic (I16 card_ID, I16 connect_index, I16 slave_No, I16 output_logic); I16 HSL_D_set_int_renewal_type(I16 card_ID, I16 connect_index, I16 type); I16 HSL_D_set_int_renewal_bit(I16 card_ID, I16 connect_index, I16 slave_No, U16 bitsOfCheck); I16 HSL_D_set_int_control(I16 card_ID, I16 connect_index, I16 enable); ``` I16 HSL\_D\_wait\_di\_interrupt(I16 card\_ID, I32 time\_out\_ms); Visual Basic (Windows 98/NT/2000/XP) ```txt HSL_D_write_output (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal out_data As Long) As Integer HSL_D_write_channel_output (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal channel As Integer, ByVal out_data As Integer) As Integer HSL_D_read_input (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, in_data As Long) As Integer HSL_D_read_channel_input (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal channel As Integer, in_data As Integer) As Integer HSL_D_read_output (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, out_data_in_ram As Long) As Integer HSL_D_read_all_slave_input (ByVal card_ID As Integer, ByVal connect_index As Integer, in_data As Integer) As Integer HSL_D_write_all_slave_output (ByVal card_ID As Integer, ByVal connect_index As Integer, out_data As Integer) As Integer HSL_D_set_input_logic (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal input_logic As Integer) As Integer HSL_D_set_output_logic (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal output_logic As Integer) As Integer HSL_D_set_int_renewal_type (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal type As Integer) As Integer HSL_D_set_int_renewal_bit (ByVal card_ID As Integer, ByVal connect_index As Integer, ``` ```c ByVal slave_No As Integer, ByVal bitsOfCheck As Long) As Integer I16 HSL_D_set_int_control(I16 card_ID, I16 connect_index, I16 enable); I16 HSL_D_wait_di_interrupt(I16 card_ID, I32 time_out_ms); ``` # @ Argument card\_ID: Specifies the HSL master card index. Typically, the board index sequence is assigned by the system. The index starts from 0. connect\_index: For PCI-7851, the valid value is 0. For PCI-7852 and PMC-7852/G, the valid value is 0 or 1. slave\_No: Specifies the slave module with slave index that wants to perform this function. The valid value is 1 to 63. out\_data: The digital output of the discrete module ▶ HSL\_D\_write\_output: The data of channel 0 is assigned to bit 0, the data of channel 1 is assigned to bit 1, and so on. ▶ HSL\_D\_write\_channel\_output: The value is the digital output data of the specified channel. \*out\_data: An unsigned short array pointer. You must create an unsigned short array containing 63 cells. The cell index corresponds to the slave index. For example, cell index 0 corresponds to the module with slave index 1. The cell index 2 corresponds to the module with slave index 2, and so on. The last cell index 62 corresponds to the module with slave index 63. <table>Cell index of array (Unsigned short)Corresponding slave index0112............6263 \*in\_data: The input data of slave modules. For HSL\_D\_read\_input: The data of channel 0 is assigned to bit 0, the data of channel 1 is assigned to bit 1, and so on. For HSL\_D\_read\_channel\_input: The value is the digital input data of the specified channel. ▶ oFor HSL\_D\_all\_slave\_index: An unsigned short array pointer. You must create an unsigned short array containing 63 cells. The cell index corresponds to the slave index. For example, cell index 0 corresponds to the module with slave index 1. The cell index 2 corresponds to the module with slave index 2, and so on. The last cell index 62 corresponds to the module with slave index 63.
Cell index of array (Unsigned short)Corresponding slave index
01
12
............
6263
channel: Specifies the channel of the discrete I/O module that wants to perform this function. The valid values are enumerated below. ▶ HSL-R8DI16: 0 to 15 ▶ HSL-DI16DO16: 0 to 15 ▶ HSL-DI32: 0 to 31 ▶ HSL-DO32: 0 to 31 \*out\_data\_in\_ram: The output data stored in RAM. The data of channel 0 is assigned to bit 0; the data of channel 1 is assigned to bit 1 and so on. input\_logic: Sets the input logic to the specified module. output\_logic: Sets the output logic to the specified module. Type: Types of hardward interrupt occurrence timing value (1 to 3). bitsOfCheck: Renews data bits (16 bits). enable: Enables (0) or disables (1) the Di interrupt. time\_out\_ms: Specifies the time-out interval in milliseconds. The function returns if the interval elapses, even when the interrupt is non-signaled. If time\_out\_ms is zero, the function tests the Di state and returns immediately. If time\_out\_ms is -1, the function's time-out interval does not elapses (infinite). # @ Return Code ```txt ERR_No_Error ERR_Invalid_Board_Number ERR_Memory_Mapping ERR_Connect_Index ERR_Satellite_Number ERR_Over_Max_Address ERR_DI_Renewal_Type ERR_Wait_Di_Interrupt ERR_Di_Event_Open_Already ERR_Di_Event_Disable ``` # 5.5 Analog I/O @ Name HSL\_A\_start\_read - Start A/D conversion HSL\_A\_stop\_read - Stop A/D conversion HSL\_A\_set\_signal\_range - Set the signal range of analog input channels HSL\_A\_get\_signal\_range - Get the signal range of analog input channels HSL\_A\_get\_input\_mode - Get the signal input mode HSL\_A\_set\_last\_channel - Set the last channel of analog input channels HSL\_A\_get\_last\_channel - Get the last channel of analog input channels HSL\_A\_read\_input - Read back the value of analog input channels HSL\_A\_write\_output - Send out the analog output HSL\_A\_read\_output - Read back the analog output data HSL\_A\_sync\_rw - Read and write the data synchronously HSL\_A\_get\_version - Get the kernel version of analog I/O module # @ Description HSL\_A\_start\_read: Initializes the reading operation of the analog input channels of all HSL AI/O modules that are connected to the master card. Before using HSL\_A\_read\_input(), HSL\_A\_write\_output() and HSL\_A\_sync\_rw(), the functions must be executed to start the A/D conversion. HSL\_A\_stop\_read: Stops the reading operation of analog input channels of all HSL AI/O modules that are connected to the master card. Use this function to stop the A/D conversion. HSL\_A\_set\_signal\_range: Sets the input range of the specified HSL AI/O modules. HSL\_A\_get\_signal\_range: Obtains the input range of the specified HSL AI/O modules. HSL\_A\_get\_input\_mode: Obtains the signal input mode of HSL AI/O modules. This is determined by hardware jumper setting. HSL\_A\_set\_last\_channel: Sets the last number of analog input channels of HSL AI/O modules. For example, the HSL-AI16AO2 has 16 analog inputs with single-ended wiring. If you want to read back the first four analog input data, assign the last channel as 3. The analog input channel index starts from 0. The AI channel 0 to 4 are enabled while the rest are disabled. HSL\_A\_get\_last\_channel: Retrieves the last number of analog input channels of HSL AI/O modules. For example, if you use HSL\_A\_set\_last\_channel and set the last channel as 5, then you can read the value of the last channel using this function. HSL\_A\_read\_input: Reads the specified AI channel of the slave module. HSL\_A\_write\_output: Writes the specified AO channel of the slave module. HSL\_A\_read\_output: Reads back the analog output data from the HSL AI/O modules with the specified analog output channel. HSL\_A\_sync\_rw: Synchronously reads AI data and writes AO data at the specified channel of the HSL AIO module. It allows simultaneous data read/write. HSL\_A\_get\_version: Reads the kernel version of the HSL AI/O modules. # @ Syntax C/C++ (DOS, Windows 98/NT/2000/XP) I16 HSL_A_start_read (I16 card_ID, I16 connect_index); I16 HSL_A_stop_read (I16 card_ID, I16 connect_index); I16 HSL_A_set_signal_range (I16 card_ID, I16 connect_index, I16 slave_No, I16 signal_range); I16 HSL_A_get_signal_range (I16 card_ID, I16 connect_index, I16 slave_No, I16 *signal_range); I16 HSL_A_get_input_mode (I16 card_ID, I16 connect_index, I16 slave_No, I16 *mode); I16 HSL_A_set_last_channel (I16 card_ID, I16 connect_index, I16 slave_No, I16 last_channel); I16 HSL_A_get_last_channel (I16 card_ID, I16 connect_index, I16 slave_No, I16 *last_channel); I16 HSL_A_read_input (I16 card_ID, I16 connect_index, I16 slave_No, I16 ai_channel, F64 *ai_data); I16 HSL_A_write_output (I16 card_ID, I16 connect_index, I16 slave_No, I16 ao_channel, F64 ao_data); I16 HSL_A_read_output (I16 card_ID, I16 connect_index, I16 slave_No, I16 ao_channel, F64 *ao_data); I16 HSL_A_sync_rw (I16 card_ID, I16 connect_index, I16 slave_No, I16 ai_channel, F64 *ai_data, I16 ao_channel, F64 ao_data); I16 HSL_A_get_version (I16 card_ID, I16 connect_index, I16 slave_No, I16 *ver); Visual Basic (Windows 98/NT/2000/XP) HSL_A_start_read (ByVal card_ID As Integer, ByVal connect_index As Integer) As Integer HSL_A_stop_read (ByVal card_ID As Integer, ByVal connect_index As Integer) As Integer HSL_A_set_signal_range (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal ```txt slave_No As Integer, ByVal signal_range As Integer) As Integer HSL_A_get_signal_range (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, signal_range As Integer) As Integer HSL_A_get_input_mode (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, mode As Integer) As Integer HSL_A_set_last_channel (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal last_channel As Integer) As Integer HSL_A_get_last_channel (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, Last_channel As Integer) As Integer HSL_A_read_input (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal ai_channel As Integer, ai_data As Double) As Integer HSL_A_write_output (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal ao_channel As Integer, ByVal ao_data As Double) As Integer HSL_A_read_output (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal ao_channel As Integer, ao_data As Double) As Integer HSL_A_sync_rw (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal ai_channel As Integer, ai_data As Double, ByVal ao_channel As Integer, ByVal ao_data As Double) As Integer HSL_A_get_version (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, Ver As Integer) As Integer ``` # @ Argument card\_ID: Specifies the HSL master card index. Typically, the system assigns the board index sequence. The index starts from 0. connect\_index: For PCI-7851, the valid value is 0. For PCI-7852 and PMC-7852/G, the valid value is 0 or 1. slave\_No: Specifies the slave module with slave index that wants to perform this function. The valid value is 1 to 63. signal\_range: The single range of analog input setting. For HSL-AI16AO2-M-VV ```txt 0: ± 1.25 V 1: ± 2.5 V 2: ± 5 V 3: ± 10 V ``` For HSL-AI16AO2-M-AV ```yaml 0: ± 5 mA 1: ± 10 mA 2: ± 20 mA 3: ± 20 mA ``` \*signal\_range: Reads back the single range of analog input setting. For HSL-AI16AO2-M-VV ```txt 0: ± 1.25 V 1: ± 2.5 V 2: ± 5 V 3: ± 10 V ``` For HSL-AI16AO2-M-AV ```yaml 0: ± 5 mA 1: ± 10 mA 2: ± 20 mA 3: ± 20 mA ``` \*mode: 0: differential type; 1: single-ended input. last\_channel: For single-ended setting, the maximum last channel is 15. For differential setting, the maximum last channel is 7. \*last\_channel: You can get the last channel depending on what you set previously. For single-ended setting, the maximum last channel is 15. For differential setting, the maximum last channel is 7. ai\_channel: Specifies the AI channel of the slave module that wants to perform this function. The valid value is described as follows. HSL-AI16AO2-M-VV/AV Differential: 0 - 15 Single-ended: 0 - 7 ao\_channel: Specifies the AI channel of the slave module that wants to perform this function. For HSL-AI16AO2-M-VV/AV, the valid value is 0 and 1. \*ai\_data: The AI data of the specified channel. The unit is Volt for HSL-AI16AO2-M-VV module and mA for HSL-AI16AO2-M-AV module. ao\_data: The AO data of the specified channel in Volt. \*ver: kernel version number. # @ Return Code ```txt ERR_No_Error ERR_Invalid_Board_Number ERR_Connect_Index ERR_Time_Out ERR_Memory_Mapping ERR_Satellite_Number ERR_Satellite_Type ERR_Over_Max_Address ERR_AI16AO2_Signal_Range ``` # 5.6 Pulse Stretcher Function (HSL-DI16-UL Only) # @ Name HSL\_D\_set\_di\_latch\_function - Set DI latch function for a specified DI channel HSL\_D\_set\_di\_latch\_functionA - Set DI latch function for all DI channels HSL\_D\_get\_di\_latch\_function - Get DI latch function for a specified DI channel # @ Description HSL\_D\_set\_di\_latch\_function: The DI-latch function can be set for one single channel by this function. Note that when this function is executing, it will disable the Di input signal, and the Di state is unknown. HSL\_D\_set\_di\_latch\_functionA: Set the same parameters of DI-latch function to all channels by this function. Note that when this function is executing, it will disable the Di input signal, and the Di state is unknown. HSL\_D\_get\_di\_latch\_function: Retrieve DI-latch settings. This function is used to confirm the setting which you set previously. Note that when this function is executing, it will disable the Di input signal, and the Di state is unknown. # @ Syntax C/C++ (DOS, Windows 98/NT/2K/XP) ```c I16 HSL_D_set_di_latch_function(I16 card_ID, I16 connect_index, I16 slave_No, I16 channel, I16 active_mode, I16 duration); I16 HSL_D_set_di_latch_functionA(I16 card_ID, I16 connect_index, I16 slave_No, I16 active_mode, I16 duration); ``` ```txt I16 HSL_D_get_di_latch_function(I16 card_ID, I16 connect_index, I16 slave_No, I16 channel, I16 * active_mode, I16 *duration); ``` Visual Basic (Windows 98/NT/2K/XP) ```txt HSL_D_set_di_latch_function (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal channel As Integer, ByVal active_mode As Integer, ByVal duration As Integer) As Integer HSL_D_set_di_latch_functionA (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal active_mode As Integer, ByVal duration As Integer) As Integer HSL_D_get_di_latch_function (ByVal card_ID As Integer, ByVal connect_index As Integer, ByVal slave_No As Integer, ByVal channel As Integer, active_mode As Integer, duration As Integer) As Integer ``` # @ Argument card\_ID: Specify the HSL master card index. Normally, the board index sequence would be decided by the system. The index is from 0. connect\_index: For the PCI-7851, the valid value is 0. For the PCI-7852 and PMC-7852/G, the valid value is 0 or 1. slave\_No: Specify the slave module with slave index which want to perform this function. The valid value is from 1 to 63. channel: Specify the DI channel. The valid value is from 0 to 15. active\_mode: Latch the DI signal 0: active ON 1: active OFF duration: Latch time, unit: millisecond. The valid value is from 0 to 127 @ Return Code ```txt ERR_Invalid_Board_Number ERR_Connect_Index ERR_Satellite_Number ERR_Board_No_Init ERR_Channel_Number ERR_Slave_Number ERR_Set_Di_Latch_Failed ERR_Di_Latch_time ERR_No_Error ``` # 6 How to Program with HSL Function Library This chapter describes how to create a program with HSL C library using a flow chart. The C library supports Windows and Redhat Linux platforms. # 6.1 Programming with HSL DLL The programming flow chart illustrates the program creation with HSL DLL. ![The flowchart begins with a block labeled **HSL_initial**, which points downward to a block labeled **HSL_start or HSL_auto_start**. This block branches into three parallel paths leading to three separate blocks: **DI/O Operation**, **AI/O Operation**, and **Motion Operation(*)**.\n\nAn orange box labeled **Scan in loop** with left and right arrows is positioned over the first two operation blocks. Dashed lines extend downward from the bottom of all three operation blocks and converge into a single path. This path leads via a solid arrow to a block labeled **HSL_stop**, which finally points downward to the terminal block labeled **HSL_close**.](.hsl-ai16ao2-m-vv-av-manual-4/7471776b7a3f4fca997647a515c76b8b5c5a95226870e2dcf652e208b3569d02.jpg) Figure 6-1: Programming Flow # 6.1.1 DIO Operation Inside DI/O Operation, the following function calls are for users' reference. HSL\_slave\_live(...): Detects the status of the slave module (live or die). ```txt HSL_connect_status(...): Detect the communication status of the slave module. HSL_D_read_input(...) HSL_D_read_channel_input(....) HSL_D_read_all_slave_input(....) Functions for the digital input operation of slave modules. HSL_D_write_output(...) HSL_D_write_channel_output(....) HSL_D_write_output(....) Functions for the digital output operation of slave modules HSL_D_read_output(....) Reads the output data in memory. HSL_D_set_input_logic(....) HSL_D_set_output_logic(....) Functions for setting the DIO logic. ``` All functions may be executed in a loop to obtain the latest information from the slave modules. # 6.1.2 AI/O Operation Inside AI/O Operation, the following function calls are provided for user reference. ```c 1. If the module needs to be calibrated, refer to Appendix C. 2. To set the AI/O configuration of the slave module, use HSL_A_set_signal_range(...) HSL_A_set_last_channel(...). If you want to check AI/O configuration, use HSL_A_get_signal_range(...) HSL_A_get_input_mode(...) HSL_A_get_last_channel(...) ``` 3. Use HSL\_A\_start\_read(...) to initialize the AIO channels reading operation. 4. After activating the HSL AD conversion, use these functions for the HSL operation. HSL\_slave\_live(...) Detects the status of the slave module(Live or Die). HSL\_connect\_status(...) Detects the communication status of the slave module. HSL\_A\_read\_input(...) Function for analog value reading operation of the slave modules. HSL\_A\_write\_output(...) Function for analog value writing operation of the slave modules. HSL\_A\_sync\_rw(...) Function for synchronous analog input and output. 5. Use HSL\_A\_stop\_read(....) to stop the AIO channels reading operation. All steps may be executed in a loop to get the latest information from the slave modules. # 6.1.3 Motion Operation: Refer to HSL-4XMO user's manual. # Appendix A Scan Time Table A.1 Full Duplex Mode
Slave Index NumberCycle Time under 3 MbpsCycle Time under 6 MbpsCycle Time under 12 Mbps
Base Unit60.67 μs30.33 μs15.17 μs
< 3(*)182.00μs91.00 μs45.50 μs
5303.33 μs151.67 μs75.83 μs
10606.67μs303.33 μs151.67 μs
201.213 ms606.67 μs303.33 μs
301.820 ms910.00 μs455.00 μs
402.427 ms1.213 ms606.67 μs
503.033 ms1.516 ms758.33 μs
603.640 ms1.820 ms910.00 μs
633.822 ms1.911 ms955.50 μs
(\*) The minimum scan time for full duplex mode at different transmission speeds. # A.2 Half Duplex Mode
Slave Index NumberCycle Time under 3 MbpsCycle Time under 6 MbpsCycle Time under 12 Mbps
Base Unit118 μs59 μs29.5 μs
< 3(*)354 μs177 μs88.5 μs
5590 μs295 μs147.5 μs
101.180 ms590 μs295 μs
202.360 ms1.180 ms590 μs
303.540 ms1.770 ms885 μs
404.720 ms2.360 ms1.180 ms
505.900 ms2.950 ms1.475 ms
607.080 ms3.540 ms1.770 ms
637.434 ms3.717 ms1.859 ms
(\*) The minimum scan time for half duplex mode at different transmission speeds. # Appendix B Mapping Table HSL has two types of function library in the HSL.h. The following is the mapping table for new and old versions of the codes. # B.1 Initialization and System Information
New VersionOld Version
HSL_initialW_HSL_Initial
HSL_closeW_HSL_Close
HSL_startW_HSL_Start
HSL_auto_startW_HSL_Auto_Start
HSL_stopW_HSL_Stop
HSL_connect_statusW_HSL_Connect_Status
HSL_slave_liveW_HSL_Slave_Live
HSL_get_irq_channelW_HSL_Get_IRQ_Channel
# B.2 Timer Control 3
New VersionOld Version
HSL_enable_timer_interruptW_HSL_TMRINT_Enable
HSL_disable_timer_interruptW_HSL_TMRINT_Disable
HSL_set_timerW_HSL_Timer_Set
# B.3 Discrete I/O
New VersionOld Version
HSL_D_read_inputW_HSL_DIO_In
HSL_D_read_channel_inputW_HSL_DIO_Channel_In
HSL_D_write_outputW_HSL_DIO_Out
HSL_D_write_channel_outputW_HSL_DIO_Channel_Out
HSL_D_read_ouputW_HSL_Read_DIO_Out
HSL_D_read_all_slave_inputW_HSL_DIO_Memory_In
HSL_D_write_all_slave_outputW_HSL_DIO_Memory_Out
HSL_D_set_input_logicW_HSL_Set_In_Out_Logic
HSL_D_set_output_logic
# B.4 Analog I/O
New VersionOld Version
HSL_A_start_readW_HSL_AI_Start_Read
HSL_A_stop_readW_HSL_AI_Stop_Read
HSL_A_set_signal_rangeW_HSL_AI_SetConfig
HSL_A_get_signal_rangeW_HSL_AI_GetConfig
HSL_A_get_input_mode
HSL_A_set_last_channelW_HSL_AI_Set_Last_Channel
HSL_A_get_last_channelW_HSL_AI_Get_Last_Channel
HSL_A_read_inputW_HSL_AI_Channel_In
HSL_A_write_outputW_HSL_AO_Channel_Out
HSL_A_read_outputW_HSL_AO_Channel_In
HSL_A_sync_rwW_HSL_AIO_Channel_InOut
HSL_A_get_versionW_HSL_AI_Get_Version
# Appendix C HSL-AI16AO2 Calibration # C.1 Before you proceed Before calibrating the HSL-AI16AO2-M-VV and HSL-AI16AO2-M-AV, take note of the following: 1. Make sure that the signal type is single-ended. You may set this via the jumper. 2. Use a precise calibrator that can generate a precise 5 V. 3. Check the status text to know if the calibration is successful or not. 4. Refer to the analog input field configuration below.
Single-ended mode
Terminal No.0123456789101112131415
Signal NameAI0AI1AI2AI3AI4AI5AI6AI7AI8AI9AI10AI11AI12AI13AI14AI15
Terminal No.16171819202122232425262728293031
Signal NameAO0AO1AGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGND
# C.2 Calibrating the modules To calibrate the modules: 1. Press the Calibration button from the HSL-AI16AO2 utility. A dialog box appears. ![AI16AO2-VV Slave Module Calibration\nStep 1 : AI Offset Calibration\nPlease connect A/D channel 1 into AGND, and then press 'AI Calibration' button to\nexecute AI offset calibration.\nAI Offset Calibration AI Span Calibration AD Offset Calibration AD Gain Calibration\nStatus](.hsl-ai16ao2-m-vv-av-manual-4/f3987677d10c06125e859c643c26440d6a0881ef43de65a5bda26aea1f54123e.jpg) 2. Connect AI channel 1 to AGND. The AI channel index is from 0 to 15. Take note of the index. After wiring, press the AI Offset Calibration button. 3. Connect AI channel 0 to the calibrator, then, press the AI Span Calibration button. 4. Connect AI channel 12 to AO channel 0, and AI channel 14 to AO channel 1, then press the AO Offset Calibration button. 5. If the previous step is successful, press the AO Gain Calibration button to finish the calibration. If calibration is successful, the module is ready for use. If not, check the wiring and calibrator, then repeat the calibration procedures. # Appendix D HSL-HUB/Repeater Information # D.1 Recommended transfer rates, total extension distance, and number of installed HSL-HUB/Repeater
Transmission rateNumber of inserted Hubs (Repeater)
Basic configuration1234567
3Mbps300 m600 m900 m1.2 km1.5 km1.8 km2.1 km2.4 km
6Mbps200 m400 m600 m800 m1 km1.2 km1.4 km1.6 km
12Mbps100 m200 m300 m400 m500 m600 m700 m800 m
# D.2 Scan time table # D.2.1 Full duplex/12 Mbps
Number of inserted Hubs (Repeater)Slave Index Number
3 (Min.)3063 (max)
Basic configuration (0)45.50 us455.00 us955.50 us
182.00 us820.00 us1722.00 us
2118.00 us1180.00 us2478.00 us
3154.00 us1540.00 us3234.00 us
4190.00 us1900.00 us3990.00 us
5226.00 us2260.00 us4746.00 us
6262.00 us2620.00 us5502.00 us
7298.00 us2980.00 us6258.00 us
# D.2.2 Full duplex/6 Mbps
Number of inserted Hubs (Repeater)Slave Index Number
3 (Min.)3063 (max)
Basic configuration (0)91.00 us910.00 us1911.00 us
1164.00 us1640.00 us3444.00 us
2236.00 us2360.00 us4956.00 us
3308.00 us3080.00 us6468.00 us
4380.00 us3800.00 us7980.00 us
5452.00 us4520.00 us9492.00 us
6524.00 us5240.00 us11004.00 us
7596.00 us5960.00 us12516.00 us
# D.2.3 Full duplex/3 Mbps
Number of inserted Hubs (Repeater)Slave Index Number
3 (Min.)3063 (max)
Basic configuration (0)182.00 us1820.00 us3822.00 us
1328.00 us3280.00 us6888.00 us
2472.00 us4720.00 us9912.00 us
3616.00 us6160.00 us12936.00 us
4760.00 us7600.00 us15960.00 us
5904.00 us9040.00 us18984.00 us
61048.00 us10480.00 us22008.00 us
71192.00 us11920.00 us25032.00 us
# D.2.4 Half duplex/12 Mbps
Number of inserted Hubs (Repeater)Slave Index Number
1 (Min.)3063 (max)
Basic configuration (0)29.50 us885.00 us1858.50 us
139.33 us1180.00 us2478.00 us
251.33 us1540.00 us3234.00 us
363.33 us1900.00 us3990.00 us
475.33 us2260.00 us4746.00 us
587.33 us2620.00 us5502.00 us
699.33 us2980.00 us6258.00 us
7111.33 us3340.00 us7014.00 us
# D.2.5 Half duplex/6 Mbps
Number of inserted Hubs (Repeater)Slave Index Number
1 (Min.)3063 (max)
Basic configuration (0)59.00 us1770.00 us3717.00 us
178.67 us2360.00 us4956.00 us
2102.67 us3080.00 us6468.00 us
3126.67 us3800.00 us7980.00 us
4150.67 us4520.00 us9492.00 us
5174.67 us5240.00 us11004.00 us
6198.67 us5960.00 us12516.00 us
7222.67 us6680.00 us14028.00 us
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