# I-Pi SMARC

User’s Guide

![Close-up of a blue printed circuit board with various electronic components and connectors (no readable text or symbols)](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/26a2019d185b6addeed92b55c55ca0ea58bf65edde62d29192dcc9b912bffb09.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2024-03-26</td></tr><tr><td>0.2</td><td>Pin definitions updated</td><td>2024-05-14</td></tr><tr><td>0.3</td><td>Images updated</td><td>2024-06-14</td></tr><tr><td>0.4</td><td>Illustrations and labels updated</td><td>2024-07-05</td></tr><tr><td>0.5</td><td>Fan pin definitions added</td><td>2024-07-10</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangular warning sign with a thick black border and a black exclamation point in the center.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/cb22638f63f2ba4aea092021f9566685767e16a0c5483d635329d9a44ed71728.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black line drawing of a wheeled trash bin. A large 'X' is superimposed over the bin, crossing it out. Below the bin is a solid black rectangular block.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/d1758dfe54838734ff8985cd2e8a0713743da6edc6470dd118e759ed8e7aeb03.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2024 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a graphic icon resembling a document or page. It features a red outline of a white square with the top-right corner folded down. Inside the outline, there are two horizontal black lines centered vertically, suggesting lines of text.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/4865a60322f9e7d1854b936670b18ffd0396c6e41832f020c1784fa623278492.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow triangular warning sign with a white exclamation point centered inside it. The bottom tip of the triangle is cut off, leaving a straight horizontal edge. The background is white. There is no text.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/d1704844dec7e534925cebe698216b3d33cd0360b7b6b7b5c40448e9d74ef611.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard warning symbol: a red triangle pointing upwards containing a white exclamation point in its center.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/83a3c95895cde185785d5f718b4e171c6bd42cf326fee4149c1b6e18262ec89f.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ...

Preface ..

1. Introduction ...

1.1 The SMARC Formfactor .. .2

2. Specifications...

2.1 Boot Modes .. ..3

2.2 Power Supply .. ..3

2.3 Mechanical and Environmental . ..3

3. Block Diagram... . 4

3.1 Pin header Summary.... .5

4. Connector Pinout and Signal Descriptions..... . 6

5. Connectors and Signal Descriptions .. .10

5.1 HDMI... ... 10

5.2 LVDS... ... 11

5.3 DSI.... ... 12

5.4 MIPI Camera support... ... 13

5.4.1 MIPI CSI0 ... .13

5.4.2 MIPI CSI1 (Camera) . .14

5.5 Audio ... ... 15

5.5.1 I2S.. .. 15

5.5.2 HDA... ... 16

5.6 USB Ports .. . 17

5.7 PCIe Ports... ... 19

5.8 LAN Ports .. ... 20

5.8.1 1st LAN . .20

5.8.2 2nd LAN ... .21

5.9 SDIO .... ... 22

5.10 SPI & ESPI ... . 23

5.10.1 SPI0 .... .23

5.10.2 ESPI ... .24

5.11 General Purpose I2C. . 25

5.12 GPIO ... ... 26

5.13 UART... ... 27

5.14 CAN Bus... ... 28

5.15 Miscellaneous.. . 28

5.16 Power and System Management.. . 29

5.16.1 Boot Select... .31

5.16.2 Power .. .32

6. Mechanical... ..33

# 1. Introduction

# 1.1 The SMARC Formfactor

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer-on-Module (COM) definition targeting applications that require low power, low costs, and high performance. SMARC modules typically use Arm SoCs similar to those used in handheld devices such as tablet computers and smart phones. Other low-power SoCs and CPUs, such as tablet-oriented x86 devices and other RISC CPUs may be used as well. SMARC modules’ power envelope is typically under 6W.

SMARC has two sizes defined: 82x50 mm and 82x80 mm.

SMARC module PCBs have 314 edge fingers that mate with a low-profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321-pin connector, where 7 pins are used by the key).

Computer-on-Modules are used as building blocks for portable and stationary embedded systems. The core elements, including CPU, DRAM, boot flash, power sequencing, CPU power supplies, GbE, and a single channel LVDS display transmitter are concentrated on the module, which is used along with an application-specific carrier board that implements other features, such as audio codecs, touch controllers, wireless devices, etc. The modular approach allows scalability, accelerated time-to-market and upgradability while still maintaining low costs, low power, and small physical size.

![The image displays a logo featuring the text 'SGeT'. The letters 'S' and 'G' are large and yellow. The lowercase letter 'e' is pink and overlaps the yellow uppercase letter 'T' on the right.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/a103abe3cbb77cde10216f537e2e70fa890e52b4703d5ba504f36ea6d8929c56.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

SMARC module and carrier specifications are available online at https://www.sget.org/standards/smarc.html

# 2. Specifications

# 2.1 Boot Modes

The standard boot mode of the I-Pi SMARC Plus is configured as an SD-card boot. Other boot options are supported by a boot-selector switch located on the carrier.

# 2.2 Power Supply

The I-Pi SMARC Plus is powered by a 5.5 mm barrel connector, the supply voltage is 19V DC.

# 2.3 Mechanical and Environmental

# Form Factor

SGET SMARC Specifications 2.1

# Dimension

110 x 110 mm

# Operating Temperature

Standard: 0°C to 60°C Rugged: -40°C to 85°C

# Humidity

5-90% RH operating, non-condensing

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I,

Condition A and Method 214A, Table 214-I, Condition D

# 3. Block Diagram

![The flowchart depicts the **SMARC 2.1** module (labeled **MXM 3.0** in the central pink block) and its connections to various interfaces.\n\n**Central Block:**\n*   SMARC 2.1\n*   MXM 3.0\n\n**Left Column (Connectors & Inputs):**\n*   **Connectors** (vertical label)\n    *   **30 pin Hirose connector** connects to **LVDS0**, **eDP0**, **DSI0**\n    *   **30 pin Hirose connector** connects to **LVDS1**, **eDP1**, **DSI1**\n    *   **15 pin FPC CSI0** and **22 pin FPC CSI1** connect to **MIPI CSI0 2-lanes** and **MIPI CSI1 4-lanes**\n    *   **HDMI connector** connects to **HDMI**\n    *   **Micro USB OTG** connects to **USB 2.0 OTG**\n    *   **USB 2.0 Host** (x2) connect to **USB1 - 2.0 Host** and **USB4 - 2.0 Host**\n    *   **USB 3.0 Host** (x2) connect to **USB3 - 3.0 Host** and **USB2 - 3.0 Host** (Note: A **MUX** label is present near these lines)\n    *   **RJ45** (x2) connect to **GBE0** and **GBE1**\n    *   **Micro SD** connects to **SDIO**\n*   **PCB / Jack** (vertical label)\n    *   **Audio expansion** connects to **I2S0**, **HDA**\n\n**Right Column (Headers & Sockets):**\n*   **40 pin Plus Pin header** (labeled **Pin Header**) connects to **CAN0**, **CAN1**, **UART**, **I2C**, **SPI**\n*   **40 pin RPI comp. Pin header** (labeled **Pin Header**) connects to **GPIO**, **I2C**, **UART**, **SPI**\n*   **M.2 E-Key** (labeled **Socket**) connects to **PCIe-A**, **USB5**\n*   **M.2 B-Key** (labeled **Socket**) connects to **PCIe-B**, **MUX USB2**, and **USIM**\n\n**Small/Intermediate Blocks:**\n*   **MUX** (located near USB 3.0 Host connections)\n*   **MUX USB2** connects to **M.2 B-Key**\n*   **USIM** connects to **M.2 B-Key**\n\n**Bottom Right Blocks:**\n*   **Reset Power** (text displayed on two lines: 'Reset' and 'Power') connects to the central block\n*   **Boot-Select** connects to the central block](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/04b435fe0fe0b2b0db762330530fcfcac48ef3033f3730a1fc7b50fa5f63b6f3.jpg)

# 3.1 Pin Header Summary

1- 40 pin I/O header (RPI compatible)

2- 40 pin Plus header

<table><tr><td>3.3V</td><td>1</td><td>2</td><td>5V</td></tr><tr><td>I2C_DAT</td><td>3</td><td>4</td><td>5V</td></tr><tr><td>I2C_CK</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GPIO06</td><td>7</td><td>8</td><td>UART0_TX</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>UART0_RX</td></tr><tr><td>GPIO08</td><td>11</td><td>12</td><td>GPIO07</td></tr><tr><td>GPIO09</td><td>13</td><td>14</td><td>GND</td></tr><tr><td>GPIO10</td><td>15</td><td>16</td><td>GPIO11</td></tr><tr><td>3.3V</td><td>17</td><td>18</td><td>GPIO12</td></tr><tr><td>SPI0_MOSI (TX)</td><td>19</td><td>20</td><td>GND</td></tr><tr><td>SPI0_MISO (RX)</td><td>21</td><td>22</td><td>GPIO13</td></tr><tr><td>SPI0_SCLK</td><td>23</td><td>24</td><td>SPI_0_CS0#</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>SPI_0_CS1#</td></tr><tr><td>I2C_DAT</td><td>27</td><td>28</td><td>I2C_CK</td></tr><tr><td>GPIO1_0 / PWM</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>GPIO1_1 / PWM</td><td>31</td><td>32</td><td>GPIO1_2 / PWM</td></tr><tr><td>GPIO1_3 / PWM</td><td>33</td><td>34</td><td>GND</td></tr><tr><td>GPIO1_4 / PWM</td><td>35</td><td>36</td><td>GPIO1_5 / PWM</td></tr><tr><td>GPIO1_6 / PWM</td><td>37</td><td>38</td><td>GPIO1_7 / PWM</td></tr><tr><td>GND</td><td>39</td><td>40</td><td>GPIO2_8 / PWM</td></tr></table>

1
![Close-up of a blue printed circuit board with various electronic components and connectors (no readable text or symbols)](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/cecbd566c7a93b5355b687ac55772e1d0af5408b1d2eb8cc0e5cebdb16dc434f.jpg)

<table><tr><td>SER1 RX</td><td>1</td><td>2</td><td>SER3 RX</td></tr><tr><td>SER1 TX</td><td>3</td><td>4</td><td>SER3 TX</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>SER2 RX</td><td>7</td><td>8</td><td>SER2 RTS#</td></tr><tr><td>SER2 TX</td><td>9</td><td>10</td><td>SER2 CTS#</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>CAN0_H</td><td>13</td><td>14</td><td>CAN1_H</td></tr><tr><td>CAN0_L</td><td>15</td><td>16</td><td>CAN1_L</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>SPI1_HOLD_N</td><td>19</td><td>20</td><td>SPI1_WP_N</td></tr><tr><td>SPI1_CS0_N</td><td>21</td><td>22</td><td>SPI1_CS1_N</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>VCC_SPI1</td></tr><tr><td>SPI1_CLK</td><td>25</td><td>26</td><td>GND</td></tr><tr><td>SPI1_IO0_MOSI</td><td>27</td><td>28</td><td>SPI1_IO1_MISO</td></tr><tr><td>SPI1_IO3</td><td>29</td><td>30</td><td>SPI1_IO2</td></tr><tr><td>ESPI_ALERTO #</td><td>31</td><td>32</td><td>ESPI_ALERT1#</td></tr><tr><td>ESPI RESET_N</td><td>33</td><td>34</td><td>GND</td></tr><tr><td>HDMI#_SEL_H</td><td>35</td><td>36</td><td>M.2 USB3.0MUX SEL_H</td></tr><tr><td>HDMI#_SEL</td><td>37</td><td>38</td><td>M.2 USB 3.0MUX SEL</td></tr><tr><td>GND</td><td>39</td><td>40</td><td>GND</td></tr></table>

# 4. Connector Pinout and Signal Descriptions

LVDS/eDP/DSI pin-headers

<table><tr><td>PNLPWR</td><td>2</td><td>1</td><td>LVDS1_EDP1_DSI1_D0_CN_P</td></tr><tr><td>PNLPWR</td><td>4</td><td>3</td><td>LVDS1_EDP1_DSI1_D0_CN_N</td></tr><tr><td>+VDD_PANEL1_EDID</td><td>6</td><td>5</td><td>GND</td></tr><tr><td>+VDD_PANEL1</td><td>8</td><td>7</td><td>LVDS1_EDP1_DSI1_D1_CN_P</td></tr><tr><td>+VDD_PANEL1</td><td>10</td><td>9</td><td>LVDS1_EDP1_DSI1_D1_CN_N</td></tr><tr><td>GND</td><td>12</td><td>11</td><td>GND</td></tr><tr><td>LVDS_BKLT1_CTRL</td><td>14</td><td>13</td><td>LVDS1_EDP1_DSI1_D2_CN_P</td></tr><tr><td>LVDS_BKLT1_EN</td><td>16</td><td>15</td><td>LVDS1_EDP1_DSI1_D2_CN_N</td></tr><tr><td>GND</td><td>18</td><td>17</td><td>GND</td></tr><tr><td>LVDS_BKLT1_EN</td><td>20</td><td>19</td><td>LVDS1_EDP1_DSI1_D3_CN_P</td></tr><tr><td>LCD1_VDD_EN_3V3</td><td>22</td><td>21</td><td>LVDS1_EDP1_DSI1_D3_CN_N</td></tr><tr><td>eDP1_HPD_DSI1_TE_3V3</td><td>24</td><td>23</td><td>GND</td></tr><tr><td>DDC1_DAT</td><td>26</td><td>25</td><td>LVDS1_EDP1_DSI1_CK_CN_P</td></tr><tr><td>DDC1_CK</td><td>28</td><td>27</td><td>LVDS1_EDP1_DSI1_CK_CN_N</td></tr><tr><td>GND</td><td>30</td><td>29</td><td>GND</td></tr></table>

![Labeled electronic circuit board with component annotations and pinouts, showing blue PCB and gold contacts](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/255ed1da2dcab8318b9b2add8fbae4fb47dc8f12ff09f7a28bb999be72b90f43.jpg)

1-3  5V backlight 3-5  3.3V backlight Default setting  5V

<table><tr><td>PNLPWR</td><td>2</td><td>1</td><td>LVDSO_EDPO_DSIO_D0_CN_P</td></tr><tr><td>PNLPWR</td><td>4</td><td>3</td><td>LVDSO_EDPO_DSIO_D0_CN_N</td></tr><tr><td>+VDD_PANELO_EDID</td><td>6</td><td>5</td><td>GND</td></tr><tr><td>+VDD_PANELO</td><td>8</td><td>7</td><td>LVDSO_EDPO_DSIO_D1_CN_P</td></tr><tr><td>+VDD_PANELO</td><td>10</td><td>9</td><td>LVDSO_EDPO_DSIO_D1_CN_N</td></tr><tr><td>GND</td><td>12</td><td>11</td><td>GND</td></tr><tr><td>LVDS_BKLTO_CTRL</td><td>14</td><td>13</td><td>LVDSO_EDPO_DSIO_D2_CN_P</td></tr><tr><td>LVDS_BKLTO_EN</td><td>16</td><td>15</td><td>LVDSO_EDPO_DSIO_D2_CN_N</td></tr><tr><td>GND</td><td>18</td><td>17</td><td>GND</td></tr><tr><td>LVDS_BKLTO_EN</td><td>20</td><td>19</td><td>LVDSO_EDPO_DSIO_D3_CN_P</td></tr><tr><td>LCDO_VDD_EN_3V3</td><td>22</td><td>21</td><td>LVDSO_EDPO_DSIO_D3_CN_N</td></tr><tr><td>eDP0_HPD_DSIO_TE_3V3</td><td>24</td><td>23</td><td>GND</td></tr><tr><td>DDCO_DAT</td><td>26</td><td>25</td><td>LVDSO_EDPO_DSIO_CK_CN_P</td></tr><tr><td>DDCO_CK</td><td>28</td><td>27</td><td>LVDSO_EDPO_DSIO_CK_CN_N</td></tr><tr><td>GND</td><td>30</td><td>29</td><td>GND</td></tr></table>

Both connectors use the same pin-out, connector 1 on the left, connector 0 on the right.

# CSI connectors

![MRAA\nBOOT\n12 4\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\n01 10 50 (on)\nVH721\nCSI0\nCSI1](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/735995cfbefeb1a3fbca2e7174d5a776c63032056190b49dfc4a4961f4bfac3f.jpg)

CSI0

<table><tr><td>Pin#</td><td>Name</td><td>Type</td><td>Description</td></tr><tr><td>1</td><td>CAM_3V3</td><td>Power</td><td>3.3V Power</td></tr><tr><td>2</td><td>CAM0_I2C_DAT_3V</td><td>Bidirection</td><td>I2C SDA</td></tr><tr><td>3</td><td>CAM0_I2C_CK_3V</td><td>Bidirection</td><td>I2C SCL</td></tr><tr><td>4</td><td>CAM0_MCK_3V_R</td><td>Input</td><td>Camera Main Clock</td></tr><tr><td>5</td><td>CAM0_GPIO_3V</td><td>Input</td><td>GPIO for LED</td></tr><tr><td>6</td><td>CAM0_GPIO2_3V</td><td>Input</td><td>GPIO for Enable</td></tr><tr><td>7</td><td>CSI0_CK_P</td><td>Output</td><td>MIPI Clock Lane Positive</td></tr><tr><td>8</td><td>CSI0_CK_N</td><td>Output</td><td>MIPI Clock Lane Negative</td></tr><tr><td>9</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>10</td><td>CSI1_D1_P</td><td>Output</td><td>MIPI Data Lane 1 Positive</td></tr><tr><td>11</td><td>CSI1_D1_N</td><td>Output</td><td>MIPI Data Lane 1 Negative</td></tr><tr><td>12</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>13</td><td>CSI1_D0_P</td><td>Output</td><td>MIPI Data Lane 0 Positive</td></tr><tr><td>14</td><td>CSI1_D0_N</td><td>Output</td><td>MIPI Data Lane 0 Negative</td></tr><tr><td>15</td><td>GND</td><td>Power</td><td>Ground</td></tr></table>

CSI1

<table><tr><td>Pin#</td><td>Name</td><td>Type</td><td>Description</td></tr><tr><td>1</td><td>CAM_3V3</td><td>Power</td><td>3.3V Power</td></tr><tr><td>2</td><td>CAM1_12C_DAT_3V</td><td>Bidirection</td><td>I2C SDA</td></tr><tr><td>3</td><td>CAM1_12C_OK_3V</td><td>Bidirection</td><td>I2C SCL</td></tr><tr><td>4</td><td>CAM1_MCK_3V_R</td><td>Input</td><td>Camera Main Clock</td></tr><tr><td>5</td><td>CAM1_GPIO3_3V</td><td>Input</td><td>GPIO for LED</td></tr><tr><td>6</td><td>CAM1_GPIO1_3V</td><td>Input</td><td>GPIO for Enable</td></tr><tr><td>7</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>8</td><td>CSI1_D3_P</td><td>Output</td><td>MIPI Data Lane 3 Positive</td></tr><tr><td>9</td><td>CSI1_D3_N</td><td>Output</td><td>MIPI Data Lane 3 Negative</td></tr><tr><td>10</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>11</td><td>CSI1_D2_P</td><td>Output</td><td>MIPI Data Lane 2 Positive</td></tr><tr><td>12</td><td>CSI1_D2_N</td><td>Output</td><td>MIPI Data Lane 2 Negative</td></tr><tr><td>13</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>14</td><td>CSI1_CK_P</td><td>Output</td><td>MIPI Clock Lane Positive</td></tr><tr><td>15</td><td>CSI1_CK_N</td><td>Output</td><td>MIPI Clock Lane Negative</td></tr><tr><td>16</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>17</td><td>CSI1_D1_P</td><td>Output</td><td>MIPI Data Lane 1 Positive</td></tr><tr><td>18</td><td>CSI1_D1_N</td><td>Output</td><td>MIPI Data Lane 1 Negative</td></tr><tr><td>19</td><td>GND</td><td>Power</td><td>Ground</td></tr><tr><td>20</td><td>CSI1_D0_P</td><td>Output</td><td>MIPI Data Lane 0 Positive</td></tr><tr><td>21</td><td>CSI1_D0_N</td><td>Output</td><td>MIPI Data Lane 0 Negative</td></tr><tr><td>22</td><td>GND</td><td>Power</td><td>Ground</td></tr></table>

# Jumper settings

![Can Bus Termination\nLVDS-EL\n3.3-5V\nSPI1\n1.8-3.3V\nUSB\nmux\nHDMI\ncoupling\nSMARC 2.0/2.1\nPower sequence](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/6be23a8072aa8ddaf4d508929aa4dc00448410a2ea4ecaa569571ca02fbd96ff.jpg)

<table><tr><td>Interface</td><td>Setting</td></tr><tr><td>Can bus</td><td>On = Terminated 120 Ohm</td></tr><tr><td>LVDS backlight</td><td>1-3 = 5V | 3-5 = 3.3V</td></tr><tr><td>SPI1 voltage</td><td>1-2 = 1.8V | 2-3 = 3.3V</td></tr><tr><td>USB mux</td><td>36-38 = M.2 | 38-40 = USB</td></tr><tr><td>HDMI coupling</td><td>35-37 = AC | 37-39 = DC</td></tr><tr><td>SMARC power sequence</td><td>On = 2.1 | Off = 2.0</td></tr></table>

# Audio codec mezzanine

![Fan\n120Hz\n3000\ndF\n2014K\nB10\nB10\nOK4\n575 576\nVANZI\nCS1 ZLone\nCS1 ALone 22\nA3SL\nC51 ZLone\nC51 ALone 22\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR10\nR15](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/f9d81c1398661a59435137145d163de92a3a908db211ab9650b8e6fc4478ae8b.jpg)

Fan

<table><tr><td>Pin#</td><td>Setting</td></tr><tr><td>1</td><td>P_VBUS_V5</td></tr><tr><td>2</td><td>GND</td></tr></table>

The I-Pi SMARC Plus is equipped with an interchangeable audio codec.

Multiple codecs are available in I2S, HDA or SoundWire.

The board uses a one-screw fixation that sits the codecs in a boardto-board connector.

# 5. Connectors and Signal Descriptions

5.1 HDMI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>HDMI_D2+</td><td>P92</td><td rowspan="6">HDMI port, differential pair data lines</td><td rowspan="6">O TMDS HDMI</td><td rowspan="6"></td><td rowspan="6">Runtime</td><td rowspan="6"></td><td rowspan="6">AC coupled off module</td></tr><tr><td>HDMI_D2-</td><td>P93</td></tr><tr><td>HDMI_D1+</td><td>P95</td></tr><tr><td>HDMI_D1-</td><td>P96</td></tr><tr><td>HDMI_D0+</td><td>P98</td></tr><tr><td>HDMI_D0-</td><td>P99</td></tr><tr><td>HDMI_CK+</td><td>P101</td><td rowspan="2">HDMI port, differential pair clock lines</td><td rowspan="2">O TMDS HDMI</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>HDMI_CK-</td><td>P102</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2</td><td>Level shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>I/O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>Level shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.</td></tr><tr><td>HDMI_HPD</td><td>P104</td><td>HDMI Hot plug active high detection signal that serves as an interrupt request</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr></table>

5.2 LVDS

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>LVDS0_0+</td><td>S125</td><td rowspan="8">Primary LVDS channel differential pair data lines</td><td rowspan="8">O LVDS LCD</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>LVDS0_0-</td><td>S126</td></tr><tr><td>LVDS0_1+</td><td>S128</td></tr><tr><td>LVDS0_1 -</td><td>S129</td></tr><tr><td>LVDS0_2+</td><td>S131</td></tr><tr><td>LVDS0_2-</td><td>S132</td></tr><tr><td>LVDS0_3+</td><td>S137</td></tr><tr><td>LVDS0_3-</td><td>S138</td></tr><tr><td>LVDS0_CK+</td><td>S134</td><td rowspan="2">Primary LVDS channel differential pair clock lines</td><td rowspan="2">O LVDS LCD</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>LVDS0_CK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary LVDS channel power enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary LVDS channel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary LVDS channel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>LVDS1_0+</td><td>S111</td><td rowspan="8">Secondary LVDS channel differential pair data lines</td><td rowspan="8">O LVDS LCD</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">Not supported</td></tr><tr><td>LVDS1_0-</td><td>S112</td></tr><tr><td>LVDS1_1+</td><td>S114</td></tr><tr><td>LVDS1_1 -</td><td>S115</td></tr><tr><td>LVDS1_2+</td><td>S117</td></tr><tr><td>LVDS1_2-</td><td>S118</td></tr><tr><td>LVDS1_3+</td><td>S120</td></tr><tr><td>LVDS1_3-</td><td>S121</td></tr><tr><td>LVDS1_CK+</td><td>S108</td><td rowspan="2">Secondary LVDS channel differential pair clock lines.</td><td rowspan="2">O LVDS LCD</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">Not supported</td></tr><tr><td>LVDS1_CK-</td><td>S109</td></tr><tr><td>LCD1_VDD_EN</td><td>S116</td><td>Secondary panel power enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Not supported</td></tr><tr><td>LCD1_BKLT_EN</td><td>S107</td><td>Secondary panel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Not supported</td></tr><tr><td>LCD1_BKLT_PWM</td><td>S122</td><td>Secondary panel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Not supported</td></tr></table>

<table><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if 2 LVDS panels are used</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if 2 LVDS panels are used</td></tr></table>

5.3 DSI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>DSI0_D0+</td><td>S125</td><td rowspan="8">Primary DSI panel differential pair data lines</td><td rowspan="8">O LVDSD-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>DSI0_D0-</td><td>S126</td></tr><tr><td>DSI0_D1+</td><td>S128</td></tr><tr><td>DSI0_D1-</td><td>S129</td></tr><tr><td>DSI0_D2+</td><td>S131</td></tr><tr><td>DSI0_D2-</td><td>S132</td></tr><tr><td>DSI0_D3+</td><td>S137</td></tr><tr><td>DSI0_D3-</td><td>S138</td></tr><tr><td>DSI0_CLK+</td><td>S134</td><td rowspan="2">Primary DSI panel differential pair clock lines.</td><td rowspan="2">O LVDSD-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>DSI0_CLK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary panel power enable, active high</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary panel backlight enable, active high</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary panel brightness control through pulse width modulation (PWM)</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>DSI0_TE</td><td>S144</td><td>Primary DSI panel tearing effect signal</td><td>ICMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

# 5.4 MIPI Camera support

5.4.1 MIPI CSI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>CSI0_RX0+CSI0_RX0-CSI0_RX1+CSI0_RX1-</td><td>S11S12S14S15</td><td>CSI0 differential input (point to point)</td><td>I LVDS D-PHY/I LVDS M-PHY</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>CSI0_CK+CSI0_CK-</td><td>S8S9</td><td>CSI0 differential clock input (point to point)</td><td>I LVDS D-PHY</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>I2C_CAM0_DAT/CSI0_TX-</td><td>S7</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS/O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DATMIPI-CSI 3.0 uses CSIO_TX-</td></tr><tr><td>I2C_CAM0_CK/CSI0_TX+</td><td>S5</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS/O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CKMIPI-CSI 3.0 uses CSIO_TX+</td></tr><tr><td>CAM0_PWR# / GPIO0</td><td>P108</td><td>Camera 0 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAM0_RST# / GPIO2</td><td>P110</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>This signal is used by both CSI0 and CSI1</td></tr></table>

5.4.2 MIPI CSI1 (Camera)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI1_RX0+</td><td>P7</td><td rowspan="8">CSI1 differential input (point to point)</td><td rowspan="8">I LVDS D-PHY / I LVDS M-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>CSI1_RX0-</td><td>P8</td></tr><tr><td>CSI1_RX1+</td><td>P10</td></tr><tr><td>CSI1_RX1-</td><td>P11</td></tr><tr><td>CSI1_RX2+</td><td>P13</td></tr><tr><td>CSI1_RX2-</td><td>P14</td></tr><tr><td>CSI1_RX3+</td><td>P16</td></tr><tr><td>CSI1_RX3-</td><td>P17</td></tr><tr><td>CSI1_CK+</td><td>P3</td><td rowspan="2">CSI1 differential clock input (point to point)</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI1_CK-</td><td>P4</td></tr><tr><td>I2C_CAM1_DAT / CSI1_TX-</td><td>S2</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM1_DAT MIPI-CSI 3.0 mode uses CSI1_TX-</td></tr><tr><td>I2C_CAM1_CK / CSI1_TX+</td><td>S1</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM1_CK MIPI-CSI 3.0 mode uses CSI1_TX+</td></tr><tr><td>CAM1_PWR# / GPIO1</td><td>P109</td><td>Camera 0 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>CAM1_PWR# is default, GPIO1 can be enabled through DVT</td></tr><tr><td>CAM1_RST# / GPIO3</td><td>P111</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>CAM1_PWR# is default, GPIO3 can be enabled through DVT</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>This signal is used by both CSI0 and CSI1</td></tr></table>

# 5.5 Audio

5.5.1 I2S

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>I2S0_LRCK</td><td>S39</td><td>I2S0 Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td>I2S0_SDOUT</td><td>S40</td><td>I2S0 Digital audio Output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_SDIN</td><td>S41</td><td>I2S0 Digital audio Input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_CK</td><td>S42</td><td>I2S0 Digital audio clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td colspan="8"></td></tr><tr><td>I2S2_LRCK</td><td>S50</td><td>I2S2 Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td>I2S2_SDOUT</td><td>S51</td><td>I2S2 Digital audio Output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S2_SDIN</td><td>S52</td><td>I2S2 Digital audio Input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S2_CK</td><td>S53</td><td>I2S2 Digital audio clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td colspan="8"></td></tr><tr><td>AUDIO_MCK</td><td>S38</td><td>Master clock output to I2S codec(s)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

![The image displays a red icon resembling a document or piece of paper. It is roughly square-shaped with the bottom-right corner curled upwards (a 'dog-ear'). Inside the red shape, centered vertically, are two thick, horizontal black lines stacked one above the other, resembling an equals sign.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/e63f964f8a5a2796d60091e7436363cf8b9b0779a66c8b68d950d6517b9bd081.jpg)

# Note:

1. I2S signals are routed to the Audio Expansion Board pin header.
2. Support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification.

5.5.2 HDA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>HDA_SYNC / I2S2_LRCK</td><td>S50</td><td>High Definition Audio Sample synchronization clock to codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td><td rowspan="5">SMARC HDA Audio signalling supports 1.5V or 1.8V.Please check with your module vendor if 1.5V or 1.8V is supported and use an audio codec that is capable to support the regarding I/O voltage. This specification ignores the discrepancy between the 1.5V and 1.8V signalling, as the chance of damage in mismatched systems is negligible.The SMARC HD Audio pins are shared with the I2S2 pins, which are defined to be 1.8V only.</td></tr><tr><td>HDA_SDO / I2S2_SDOUT</td><td>S51</td><td>High Definition Audio data out to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_SDI / I2S2_SDIN</td><td>S52</td><td>High Definition Audio data in from codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_CK / I2S2_CK</td><td>S53</td><td>High Definition Audio clock to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_RST# / GPIO4</td><td>P112</td><td>High Definition Audio reset output to codec, low active.</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr></table>

![The image shows a red icon of a document with a folded bottom-right corner. Inside the white document shape, there are two horizontal red lines in the center.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/d2cfc10f06f0f27832af2d3a904c117bb210c5e6ef79870ad496818cfd53cffd.jpg)
Note: HDA signals are routed to the Audio Expansion Board pin header.

5.6 USB Ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>USB0+ USB0-</td><td>P60 P61</td><td>USB differential data pairs for port 0</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB0_EN_OC#</td><td>P62</td><td>USB over-current sense for port 0</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB0_VBUS_DET</td><td>P63</td><td>USB port 0 host power detection, when this port is used as a device.</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td>Can be connected to a USB client port VBUS pin</td></tr><tr><td>USB0_OTG_ID</td><td>P64</td><td>Input pin to announce OTG device insertion on USB 2.0 port</td><td>I CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>USB1+ USB1-</td><td>P65 P66</td><td>USB differential data pairs for port 1</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB1_EN_OC#</td><td>P67</td><td>USB over-current sense for port 1</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td colspan="8"></td></tr><tr><td>USB2+ USB2-</td><td>P69 P70</td><td>USB differential data pairs for port 2</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB2_SSRX+ USB2_SSRX-</td><td>S74 S75</td><td>Receive signal differential pairs for SuperSpeed on port 2</td><td>I USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for RX pairs are on the USB Device</td></tr><tr><td>USB2_SSTX+ USB2_SSTX-</td><td>S71 S72</td><td>Transmit signal differential pairs for SuperSpeed on port 2</td><td>O USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for TX pairs are on the Module</td></tr><tr><td>USB2_EN_OC#</td><td>P71</td><td>USB over-current sense for port 2</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td colspan="8"></td></tr><tr><td>USB3+ USB3-</td><td>S68 S69</td><td>USB differential data pairs for port 3</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_SSRX+ USB3_SSRX-</td><td>S65 S66</td><td>Receive signal differential pairs for SuperSpeed on port 3</td><td>I USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for RX pairs are on the USB Device</td></tr><tr><td>USB3_SSTX+USB3_SSTX-</td><td>S62S63</td><td>Transmit signal differential pairs for SuperSpeed on port 3</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for TX pairs are on the Module</td></tr><tr><td>USB3_EN_OC#</td><td>P74</td><td>USB over-current sense for port 3</td><td>I/O ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB3_VBUS_DET</td><td>S37</td><td>USB port 3 host power detection, when this port is used as a device.</td><td>IUSB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_OTG_ID</td><td>S104</td><td>Input pin to announce OTG device insertion on USB 3.0 port</td><td>ICMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td></td><td></td></tr></table>

<table><tr><td>USB4+USB4-</td><td>S35S36</td><td>USB differential data pairs for port 4</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB4_EN_OC#</td><td>P76</td><td>USB over-current sense for port 4</td><td>I/O ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr></table>

![A white square icon with a thick red border. Inside are three horizontal red lines stacked vertically. The bottom right corner is folded over.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/8faa76f7b72461d0352d12a0b06a8d16fccc70789fbaae2b2a40d75e5b705bac.jpg)
Note: USB0 is directly connected to the SoC, USB1/2/3/4 might come over a USB hub on the SMARC module.

# 5.7 PCIe Ports

two PCIe Gen 2.1 ports (PCIE\_A and PCIE\_B).

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>PCIE_A_TX+PCIE_A_TX-</td><td>P89P90</td><td>Differential PCIe link A transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_A_RX+PCIE_A_RX-</td><td>P86P87</td><td>Differential PCIe link A receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_A_REFCK+PCIE_A_REFCK-</td><td>P83P84</td><td>Differential PCIe Link A reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_RST#</td><td>P75</td><td>PCIe Port A reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_CKREQ#</td><td>P78</td><td>PCIe Port A clock request</td><td>I ODCMOS</td><td>3.3V</td><td>Runtime</td><td>-</td><td>No need for this signal because module provides onboard PCIe clock</td></tr><tr><td colspan="8"></td></tr><tr><td>PCIE_B_TX+PCIE_B_TX-</td><td>S90S91</td><td>Differential PCIe link B transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_B_RX+PCIE_B_RX-</td><td>S87S88</td><td>Differential PCIe link B receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_B_REFCK+PCIE_B_REFCK-</td><td>S84S85</td><td>Differential PCIe Link B reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_RST#</td><td>S76</td><td>PCIe Port B reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_CKREQ#</td><td>P77</td><td>PCIe Port B clock request</td><td>I ODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>No need for this signal because module provides onboard PCIe clock</td></tr><tr><td colspan="8"></td></tr><tr><td>PCIE_WAKE#</td><td>S146</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td><td>I ODCMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td></td></tr></table>

![The image displays a simple icon of a document or note. It features a white square shape with a thick red outline. The bottom-right corner is folded upwards (a 'dog-ear'). Inside the shape, centered horizontally, are two parallel red horizontal lines.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/681d477318d8c18eb4c86268854e827d997f005a40089b99d0c7dc2337632c70.jpg)

Note: The module provides PCIe clock generators for PCIE\_A and PCIE\_B, thus not external clock source on the carrier is needed.

# 5.8 LAN Ports

5.8.1 1st LAN

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>GBE0_MDI0+</td><td>P30</td><td rowspan="5">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="10">GBE MDI</td><td rowspan="10"></td><td rowspan="10">Runtime</td><td rowspan="10"></td><td rowspan="10">Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_MDI0-</td><td>P29</td></tr><tr><td>GBE0_MDI1+</td><td>P27</td></tr><tr><td>GBE0_MDI1-</td><td>P26</td></tr><tr><td>GBE0_MDI2+</td><td>P24</td></tr><tr><td>GBE0_MDI2-</td><td>P23</td><td>1000 100 10</td></tr><tr><td>GBE0_MDI3+</td><td>P20</td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td></tr><tr><td>GBE0_MDI3-</td><td>P19</td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td></tr><tr><td></td><td></td><td>MDI[2]+/- B1_DC+/-</td></tr><tr><td></td><td></td><td>MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_LINK100#</td><td>P21</td><td>Link Speed Indication LED for GBE 0 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_LINK1000#</td><td>P22</td><td>Link Speed Indication LED for GBE 0 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_LINK_ACT#</td><td>P25</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_CTREF</td><td>P28</td><td>Center Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>GBE0_SDP</td><td>P6</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr></table>

5.8.2 2nd LAN

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>GBE1_MDI0+</td><td>S17</td><td rowspan="5">Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="8">GBE MDI</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">Twisted pair signals for external transformer.</td></tr><tr><td>GBE1_MDI0-</td><td>S18</td></tr><tr><td>GBE1_MDI1+</td><td>S20</td></tr><tr><td>GBE1_MDI1-</td><td>S21</td></tr><tr><td>GBE1_MDI2+</td><td>S23</td></tr><tr><td>GBE1_MDI2-</td><td>S24</td><td rowspan="3">1000 100 10MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE1_MDI3+</td><td>S26</td></tr><tr><td>GBE1_MDI3-</td><td>S27</td></tr><tr><td>GBE1_LINK100#</td><td>S19</td><td>Link Speed Indication LED for GBE 1 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK1000#</td><td>S22</td><td>Link Speed Indication LED for GBE 1 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK_ACT#</td><td>S31</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_CTREF</td><td>S28</td><td>Center Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Runtime</td><td></td><td></td></tr><tr><td>GBE1_SDP</td><td>P5</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr></table>

![The image displays a red square icon with rounded corners. The bottom-right corner is folded upward, resembling a piece of paper. Inside the white area of the icon, there are two horizontal red lines centered vertically.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/8cef3bc52811e6cb05ea8ff17ade6f5c436a9275e706b2bc4a2a097744306521.jpg)

Note: The number of functional LAN ports is dependent on the module used.

5.9 SDIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SDIO_D0</td><td>P39</td><td rowspan="4">SDIO Data lines. These signals operate in push-pull mode.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V or 3.3V</td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4">SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_D1</td><td>P40</td></tr><tr><td>SDIO_D2</td><td>P41</td></tr><tr><td>SDIO_D3</td><td>P42</td></tr><tr><td>SDIO_WP</td><td>P33</td><td>SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CMD</td><td>P34</td><td>SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td>SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_CD#</td><td>P35</td><td>SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CK</td><td>P36</td><td>SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SDIO_PWR_EN</td><td>P37</td><td>SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>should be driven low in STB Mode by the module</td></tr></table>

# 5.10 SPI & ESPI

5.10.1 SPI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SPI0_CS0#</td><td>P43</td><td>SPI0 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>This signal can be used to select carrier SPI as boot device</td></tr><tr><td>SPI0_CS1#</td><td>P31</td><td>SPI0 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CK</td><td>P44</td><td>SPI0 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_DIN</td><td>P45</td><td>SPI0 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MISO</td></tr><tr><td>SPI0_DO</td><td>P46</td><td>SPI0 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MOSI</td></tr><tr><td colspan="8"></td></tr><tr><td>SPI1_CS0#</td><td>P54</td><td>SPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>See ESPI</td></tr><tr><td>SPI1_CS1#</td><td>P55</td><td>SPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>See ESPI</td></tr><tr><td>SPI1_CK</td><td>P56</td><td>SPI1 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>See ESPI</td></tr><tr><td>SPI1_DIN</td><td>P57</td><td>SPI1 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>See ESPI</td></tr><tr><td>SPI1_DO</td><td>P58</td><td>SPI1 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>See ESPI</td></tr></table>

![This image shows a red icon on a white background. It is a square shape with rounded corners and a folded bottom-right corner, resembling a document or memo. Inside the shape, there are two thick, horizontal red bars centered vertically.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/2cfa9fdf6db15dcb3476f81d9b7b000e52cb6c5890a93a64ec193a408630e2f9.jpg)
Note: SPI0 on RPI header, SPI1 on plus header. See jumper settings for SPI voltage.

5.10.2 ESPI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>ESPI_CS0#</td><td>P54</td><td>ESPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CS1#</td><td>P55</td><td>ESPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CK</td><td>P56</td><td>ESPI Master Clock output</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_RESET#</td><td>S58</td><td>ESPI Reset</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves</td></tr><tr><td>ESPI_ALERT0#ESPI_ALERT1#</td><td>S43S44</td><td>ESPI ALERT</td><td>I ODCMOS</td><td>1.8V</td><td>Standby</td><td></td><td>This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave.This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.</td></tr><tr><td>ESPI_IO_0ESPI_IO_1ESPI_IO_2ESPI_IO_3</td><td>P58P57S56S57</td><td>ESPI Master Data Input / Output.</td><td>I/O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>ESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO).</td></tr></table>

# 5.11 General Purpose I2C

The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels or I2C for PMIC. Just one I2C bus is for general purpose.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>I2C_GP_DAT</td><td>S49</td><td>General purpose I2C data signal</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_GP_CK</td><td>S48</td><td>General purpose I2C clock signal</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr></table>

Most of the other I2C busses are described in their designated function tables rather than in a single big list.

Below is an overview of all I2C busses and where to find them.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>Where to find</td></tr><tr><td colspan="4"></td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>I2C_CAM0_DAT</td><td>S7</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM0_CK</td><td>S5</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_DAT</td><td>S2</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_CK</td><td>S1</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA (SMBus for x86)</td><td>Power and System Management</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK (SMBus for x86)</td><td>Power and System Management</td></tr></table>

5.12 GPIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>GPIO0 / CAM0_PWR#</td><td>P108</td><td>General purpose I/O pin 0.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module.</td><td>Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS</td></tr><tr><td>GPIO1 / CAM1_PWR#</td><td>P109</td><td>General purpose I/O pin 1.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS</td></tr><tr><td>GPIO2 / CAM0_RST#</td><td>P110</td><td>General purpose I/O pin 2.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS</td></tr><tr><td>GPIO3 / CAM1_RST#</td><td>P111</td><td>General purpose I/O pin 3.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS</td></tr><tr><td>GPIO4 / HDA_RST#</td><td>P112</td><td>General purpose I/O pin 4.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO5 / PWM_OUT</td><td>P113</td><td>General purpose I/O pin 5.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO6</td><td>P114</td><td>General purpose I/O pin 6.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO7</td><td>P115</td><td>General purpose I/O pin 7.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO8</td><td>P116</td><td>General purpose I/O pin 8.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO9</td><td>P117</td><td>General purpose I/O pin 9.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO10</td><td>P118</td><td>General purpose I/O pin 10.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO11</td><td>P119</td><td>General purpose I/O pin 11.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO12</td><td>S142</td><td>General purpose I/O pin 12</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO13</td><td>S123</td><td>General purpose I/O pin 13</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr></table>

![The image shows a red icon representing a document or page set against a white background. The icon features a thick red outline in the shape of a piece of paper with a folded top-right corner. Inside the outline, there are two horizontal red lines centered within the shape, resembling lines of text.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/e1c514508b79e2816a89a745de6a095d28bf1a3f69f8aad8ec51be1eb54f7e29.jpg)
Note: All GPIO are on RPI header.

5.13 UART

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SER0_TX</td><td>P129</td><td>Asynchronous serial data output port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RX</td><td>P130</td><td>Asynchronous serial data input port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RTS#</td><td>P131</td><td>&quot;Request to Send&quot; handshake line for port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_CTS#</td><td>P132</td><td>&quot;Clear to Send&quot; handshake line for port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>SER1_TX</td><td>P134</td><td>Asynchronous serial data output port 1</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER1_RX</td><td>P135</td><td>Asynchronous serial data input port 1</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>SER2_TX</td><td>P136</td><td>Asynchronous serial data output port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_RX</td><td>P137</td><td>Asynchronous serial data input port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_RTS#</td><td>P138</td><td>&quot;Request to Send&quot; handshake line for port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_CTS#</td><td>P139</td><td>&quot;Clear to Send&quot; handshake line for port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td colspan="8"></td></tr><tr><td>SER3_TX</td><td>P140</td><td>Asynchronous serial data output port 3</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER3_RX</td><td>P141</td><td>Asynchronous serial data input port 3</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

![The image displays a red icon on a white background. It features an outline of a document or page with a folded bottom-right corner. Inside the red border, centered within the white space, are two horizontal red lines stacked vertically, resembling an equals sign.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/40df7bc34aeb0a85164aca5073908bc6d446217df8e7c6a5d5db6b881812223c.jpg)
Note: SER0 on RPI header, SER1,2,3 on plus header.

# 5.14 CAN Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr></table>

<table><tr><td>CAN0_TX</td><td>P143</td><td>CAN port 0 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAN0_RX</td><td>P144</td><td>CAN port 0 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

<table><tr><td>CAN1_TX</td><td>P145</td><td>CAN port 1 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAN1_RX</td><td>P146</td><td>CAN port1 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

![The image displays a red icon on a white background. It features a stylized document or page outline with a folded corner (dog-ear) at the bottom right. Inside the red border, there are two horizontal red lines centered vertically, resembling text or a list. There is no text in the image.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/874e1ea72f7859e62f683cdc702bb28ceeb4e924be9cccd49f9c042ebd68e36c.jpg)

Note: Can 0,1 are located on plus header.

# 5.15 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr></table>

<table><tr><td>TEST#</td><td>S157</td><td>Held low by Carrier to invoke Module vendor specific test function(s).</td><td>ICMOS</td><td>1.8V</td><td>Runtime</td><td>PU on Module. Driven by OD on Carrier</td><td>Module must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation</td></tr><tr><td>WDT_TIME_OUT#</td><td>S145</td><td>Watch-Dog-Timer Output, low active.</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Driven only during runtime</td></tr></table>

5.16 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>BATLOW#</td><td>S156</td><td>Battery low indication to Module. Carrier to float the line in inactive state.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CARRIER_PWR_ON</td><td>S154</td><td>Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.</td><td>OCMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td>1.8Vsb is only used for signaling, not a power source to the module</td></tr><tr><td>CARRIER_STBY#</td><td>S153</td><td>The Module shall drive this signal low when the system is in a standby power state.</td><td>OCMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td></td></tr><tr><td>CHARGER_PRSNT#</td><td>S152</td><td>Held low by Carrier if DC input for battery charger is present.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CHARGING#</td><td>S151</td><td>Held low by Carrier during battery charging. Carrier to float the line when charge is complete.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>VIN_PWR_BAD#</td><td>S150</td><td>Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>Driven by OD on Carrier Module must implement PU but actual value is depended on particular module design.</td></tr><tr><td>SLEEP#</td><td>S149</td><td>Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state.Active low, level sensitive. Should be de-bounced on the Module.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>LID#</td><td>S148</td><td>Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.</td><td>IOD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>RESET_OUT#</td><td>P126</td><td>General purpose reset output to Carrier board.</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>RESET_IN#</td><td>P127</td><td>Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.</td><td>I ODCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA</td><td>I/OODCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB DATA.Pulled up on module.</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK</td><td>O ODCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB CLK.Pulled up on module.</td></tr><tr><td>SMB_ALERT_1V8#</td><td>P1</td><td>SMBus Alert# (interrupt) signal</td><td>I ODCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>only used on x86 design</td></tr></table>

5.16.1 Boot Select

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>BOOT_SEL0#</td><td>P123</td><td rowspan="3">Input straps determine the Module boot</td><td rowspan="3">I OD CMOS</td><td rowspan="3">1.8Vsb</td><td rowspan="3">Standby</td><td rowspan="3">PU 4.7K</td><td rowspan="3">Driven by OD on Carrier.Pulled up on module.Only booting from EMMc and SDcard is supported</td></tr><tr><td>BOOT_SEL1#</td><td>P124</td></tr><tr><td>BOOT_SEL2#</td><td>P125</td></tr><tr><td>FORCE_RECOV#</td><td>S155</td><td></td><td>I OD CMOS</td><td>1.8Vsb</td><td>Standby</td><td>PU 10K-</td><td>Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode - such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.</td></tr></table>

<table><tr><td colspan="5">Boot select switch</td></tr><tr><td>1</td><td>2</td><td>3</td><td>4</td><td>BOOT</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>SD card</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td><td>SPI</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td><td>Remote Gbe</td></tr><tr><td>1</td><td>0</td><td>0</td><td>0</td><td>eMMC (SoM)</td></tr><tr><td>0</td><td>0</td><td>0</td><td>1</td><td>Force Recovery</td></tr></table>

![The image features a simple, red line-art icon on a white background. It depicts a rectangular shape with a folded top-right corner, resembling a document or page. Inside the red outline, there are three horizontal red lines centered vertically, which represent text or a list.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/f532d9f117c10abbee8d4d1be463693ddf739f1f52c27578501d6416c368ca84.jpg)

Note: Boot selector switch is located between the SoM and LAN ports.

5.16.2 Power

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>Power Rail / Tolerance</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="7"></td></tr><tr><td>VDD_IN</td><td>P147, P148, P149, P150, P151, P152, P153, P154, P155, P156</td><td>Module power input voltage 4.75 min to 5.25V max</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>3 to 5.25V / 5V</td><td></td><td></td></tr><tr><td>GND</td><td>P2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158</td><td>Module signal and power return, and GND reference</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>Ground</td><td></td><td></td></tr><tr><td>VDD_RTC</td><td>S147</td><td>Low current RTC circuit backup power—3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>[2 to 3.25] / 3.25V</td><td></td><td></td></tr></table>

![The image features a red-outlined icon resembling a document or a piece of paper with a folded bottom-right corner (a 'dog-ear'). Inside the white space of the shape, there are two horizontal red lines centered vertically. There is no text present.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/1d1135594ba96856c7d36b3634e4956b83a6cfa1a65b72fead1a0e9f4d5efda8.jpg)
Note: The DC jack’s input voltage level is19V DC.

# 6. Mechanical

![Technical line drawing of a mechanical assembly with no visible text or symbols](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/63d851aa3cf8177dddc95577d30fea9ef2c078bcafffd4f3b0e13190557eff41.jpg)

![110 (4330.7)\n1.2 (47.2)\n110 (4330.7)](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/55fbbf07f4d374b426d79e8ddfb8dafcb392f27daaec6fb813c94f3165e4f675.jpg)

![A red icon on a white background showing a square shape with rounded corners and a folded bottom-right corner, resembling a document. Inside the shape are two horizontal red lines stacked vertically.](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/911f9a48c6068bd75daf571a39e56cf23f557bcf675a1fd5896e0a24e8230a0b.jpg)
Note: Carrier fixation holes are made for M3 screws. SMARC modules are fixed by M3 screws, with lengths dependent on the heatsink used.
[🔗 Link to the original document](.i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710/i-pi-smarc-prelim-manual-50m-77a07-1000-05-240710.pdf)