# IMB-C46

# User’s Manual

ATX Motherboard with 11th/10th Gen Intel® Core™ i9/i7/i5/i3 Processors and Intel® Q470E Chipset

![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.imb-c46-50m-13017-1030-13/7db9a349dfdfe551e74457499caa03e58a6b4eb25bed7e8ebdb4f4d77888a024.jpg)

Manual Rev.: Rev. 1.3

Revision Date: February 24, 2026

Part Number: 50M-13017-1030

# Preface

# Copyright

Copyright 2026 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines and a solid rectangle below (no text or labels)](.imb-c46-50m-13017-1030-13/5a00dd3f139b4a4a3bb286280e4771231a872933ad42df42c5cb9708d101bf8e.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin crossed out by two diagonal lines (no text or symbols)](.imb-c46-50m-13017-1030-13/e2dbbe97eecc73eb6fe940aa1c5df7994d6df32885d0a8a5ed1caf48a07a3679.jpg)

![The image displays a black square outline containing the standard recycling symbol, characterized by three arrows chasing each other in a triangular formation. Directly beneath the square is the bold text 'Li-ion' in black.](.imb-c46-50m-13017-1030-13/79afcccce23dcbc8c8fb112efc5268f924200345be962cd917ef878dadf16eba.jpg)

![RECYCLF\nRBRC\nLi-ion\n1.800.822.8837](.imb-c46-50m-13017-1030-13/c14408a8546f259d28e4429a2d3585a183872a8dfe0bd6f365b822fd2893dea2.jpg)

![廢電池請回收](.imb-c46-50m-13017-1030-13/95f5184f8f0ee98bbdbe530d93fbf07e5cb3312bf3180e5687c820744a736ae7.jpg)

# California Proposition 65 Warning

![The image displays a yellow triangular warning sign with a thick black border containing a large black exclamation point in the center.](.imb-c46-50m-13017-1030-13/0408a6b44aadd794da568b1f667c04d814153211e49c11c0f4a991681eeef457.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2024-10-08</td><td>AL</td></tr><tr><td>1.1</td><td>Connector pinouts updated</td><td>2025-07-22</td><td>AL</td></tr><tr><td>1.2</td><td>Connector pinouts updated</td><td>2025-07-28</td><td>AL</td></tr><tr><td>1.3</td><td>Introduction and specifications updated</td><td>2026-02-24</td><td>AL</td></tr></table>

# Table of Contents

# Preface...

# List of Figures .... ..vi

# List of Tables...... ..vi

# 1 Introduction....

1.1 Packing List ..
1.2 Optional Accessories .

# 2 Specifications ....

2.1 Core System .. ..3
2.2 I/O Interface .. .3
2.3 Video .4
2.4 Audio .4
2.5 LAN.. .4
2.6 Temperatures . .4
2.7 Humidity... .4
2.8 Certificate (EMC) .. .4
2.9 Form Factor .. .5
2.10 Operating Systems . .5
2.11 Functional Block Diagram 6

# 3 Mechanical Layout ..

3.1 IO Panel Connector Locations
3.2 Mechanical Dimensions . .11

# 4 Connector Pinouts .. .13

4.1 Rear IO Connectors . .13
4.2 Onboard Headers / Connectors . .15
4.3 Jumper and Switch Settings. ..19
4.4 Expansion Slots .. ..23

# 5 Driver Installation .............. .25

# 6 BIOS Setup............ .27

6.1 Menu Structure . .27
6.2 Main Menu. ..28
6.3 Advanced.. ..28
6.4 Chipset .. ..38
6.5 Security.. ..43
6.6 Boot . ..44

6.7 Save & Exit .. ...45

Safety Instructions.... ..46

Getting Services... .47

# List of Figures

Figure 1: Functional Block Diagram.. .6
Figure 2: IO Panel Connector Locations.
Figure 3: Onboard Connector – Header and Jumper Locations .8
Figure 4: Mechanical Dimensions. ..11
Figure 5: Mechanical Dimensions - IO Panel. .11

# List of Tables

Table 1:IO Panel Connector Definitions
Table 2: Onboard Connector Definitions – Header and Jumper Definitions .. .9

# 1 Introduction

ADLINK IMB-C46 ATX is an industrial motherboard supporting 10th/11th Generation Intel® Core™ i9/i7/i5/i3 desktop processors, an Intel® Q470E Chipset, and 5 PCIe expansion slots to provide a cost-competitive embedded computing solution. It includes high-speed data transfer interfaces such as PCIe 3.0, USB 3.0, and SATA 6 Gb/s (SATA III), and quad-channel DDR4 2400/2666/2933 MHz RAM for industrial automation applications. With industrial-grade I/O port design, the IMB-C46 offers a significant competitive advantage for embedded computing applications in terms of device compatibility, durable connectivity, and extreme environment readiness.

# 1.1 Packing List

IMB-C46 ATX motherboard
• Rear I/O shield
M.2 screws kits
• 1pcs SATA cable
• 1pcs COM cable (1port)

# 1.2 Optional Accessories

CPU cooler for 65W CPU, Part Number: 32-20495-0000
• CPU cooler for 35W CPU, Part Number: 32-20530-0010
• COM Cable(2port), Part Number: 30-25003-3000
• USB2.0 Cable(2port), Part Number: 30-25010-3010
• USB2.0 Cable(4port), Part Number: 30-25009-3000
• USB3.0 Cable(2port), Part Number: 30-25046-0100
• SATA Cable, Part Number: 30-10057-700

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# 2 Specifications

# 2.1 Core System

#  CPU:

• Intel® Core™ i9-10900E, 4.7GHz, 10 Core, 20M Cache, DDR4 2933MHz support, 65W
• Intel® Core™ i9-10900TE, 4.5GHz, 10 Core, 20M Cache, DDR4 2933MHz support, 35W
• Intel® Core™ i7-10700E, 4.5GHz, 8 Core, 16M Cache, DDR4 2933MHz support, 65W
• Intel® Core™ i7-10700TE, 4.4GHz, 8 Core, 16M Cache, DDR4 2933MHz support, 35W
• Intel® Core™ i5-10500E, 4.2GHz, 6 Core, 12M Cache, DDR4 2666MHz support, 65W
• Intel® Core™ i5-10500TE, 3.7GHz, 6 Core, 12M Cache, DDR4 2666MHz support, 35W
• Intel® Core™ i3-10100E, 3.8GHz, 4 Core, 6M Cache, DDR4 2666MHz support, 65W
• Intel® Core™ i3-10100TE, 3.6GHz, 4 Core, 6M Cache, DDR4 2666MHz support, 35W
• Intel® Pentium® Gold G6400, 3.2GHz, 2 Core, 4M Cache, DDR4 2400MHz support, 35W
• Intel® Pentium® Gold G6400, 3.8GHz, 2 Core, 4M Cache, DDR4 2400MHz support, 58W
• Intel® Celeron® Processor G5900TE, 3.0GHz, 2M Cache, DDR4 2666MHz support, 35W
• Intel® Celeron® Processor G5900E, 3.2GHz, 2M Cache, DDR4 2666MHz support, 58W

Chipset: Intel® Q470E Express Chipset
 Memory: 4x 288-pin Non-ECC U-DIMM slot, DDR4 2400/2666/2933 MHz, up to 128 GB
. BIOS: AMI® UEFI BIOS, 256 Mb SPI Flash Memory
Hardware Monitor: CPU voltage

+3.3V voltage

+5V voltage

+12V voltage

CPU temperature

System temperature

CPU fan speed

System fan speed

# 2.2 I/O Interface

# Expansion slots:

• 1x PCIe Gen3 x16 (or 2x PCIe Gen3 x8)
3x PCIe x4 Gen3
2xPCI

 SATA: 4x SATA 6.0 Gb/s connectors, Intel® software RAID 0/1/5/10 support

# USB:

4x USB 3.0 (rear I/O)
• 2x USB 2.0 (rear I/O)
• 2x USB 3.0 (by pin header)
• 4x USB 2.0 (by pin header)
1x USB 2.0 (Vertical TYEP-A, Internal)

#  COM:

1x RS-232/422/485 (by pin header)
1x RS-232/485 (by pin header)
4x RS-232 (COM1 by DB9, others by pin headers)

 PS/2 Combo Port: 1x PS/2 keyboard/mouse pin header

DIO: 8-bit GPIO

Mini-PCIe slot: 1x Mini PCI-E Slot (WIFI+4G/3G, with 1x Full-Size SIM Card Slot)

M.2 connectors:

• 1x M.2 M-Key, 2242/2280 (PCIe Gen3 x4 NVMe / SATA SSD, Auto Detect)

# 2.3 Video

 Interfaces: Supports three independent displays

1x DVI: Support DVI-D, max resolution up to 1920x1200@60Hz
1x HDMI 1.4b (TYPE-A): up to 4096x2160@30Hz
1x VGA (DB15/F): max resolution up to 1920x1200@60Hz
1x eDP (Header): max resolution up to 4096x2304@60Hz

# 2.4 Audio

Audio Codec: Realtek® ALC897

Interfaces: 1x Mic-in, 1x Line-in, and 1x Line-out connectors (rear)

# 2.5 LAN

 LAN1: Intel® I219-LM GbE, via RJ45 connector
 LAN2: Intel® I210-AT GbE, via RJ45 connector

# 2.6 Temperatures

Operating Temperature: 0°C to $6 0 ^ { \circ } \mathsf { C }$
Storage Temperature: -20°C to 75°C

# 2.7 Humidity

60° C at 95% RH, non-condensing

# 2.8 Certificate (EMC)

CE/FCC Class A

# 2.9 Form Factor

 ATX: 305 mm x 244 mm (W x L)

# 2.10 Operating Systems

Microsoft® Windows® 10, 64-bit

# 2.11 Functional Block Diagram

![**Main Blocks:**\n*   10/11th Gen Intel Processor\n*   Intel PCH Q470\n*   Converter\n*   Level Shifter\n*   AUDIO CODEC\n*   I219-LM\n*   I210-AT\n*   PCI Bridge\n*   Super I/O\n*   2x DDR4 U-DIMM (two blocks)\n*   PCIE x16 Port (two blocks)\n*   4x USB3.0\n*   USB2.0 Vertical-TYPE-A\n*   4x USB2.0 Header\n*   2x USB3.0\n*   2x USB2.0 +PS2 Port\n*   COM1 DB9M\n*   COM2/5/6 Header\n*   COM3 Header\n*   COM4 Header\n*   FAN Header x3\n*   GPIO Header\n*   CASE OPEN Header\n*   AT/ATX MODE Jumper\n*   TPM (option)\n*   VGA DB9/F Port\n*   HDMI\n*   DVI-D Port\n*   eDP Header\n*   L-OUT+MIC Header\n*   L-OUT/IN/MIC Phone Jack\n*   SPDIF Header\n*   4x SATA Port\n*   RJ45 Port (two blocks)\n*   PCIE x4 Port (three blocks)\n*   Mini-PCIE\n*   SIM CARD\n*   M.2 Key-M Port\n*   2x PCI Port\n*   SMBus Header\n*   F-PANEL\n\n**Connections:**\n\n**From 10/11th Gen Intel Processor:**\n*   VGA DB9/F Port (--) Converter (--) DDID (--) 10/11th Gen Intel Processor\n*   HDMI (--) Level Shifter (--) DDIC (--) 10/11th Gen Intel Processor\n*   DVI-D Port (--) DDIB (--) 10/11th Gen Intel Processor\n*   eDP Header (--) 4Lanes eDP (--) 10/11th Gen Intel Processor\n*   10/11th Gen Intel Processor (--) DIMM0 (--) 2x DDR4 U-DIMM\n*   10/11th Gen Intel Processor (--) DIMM1 (--) 2x DDR4 U-DIMM\n*   10/11th Gen Intel Processor (--) PEGx16 (--) PCIE x16 Port\n*   10/11th Gen Intel Processor (dotted line) (--) PEGx8 (--) PCIE x16 Port\n*   10/11th Gen Intel Processor (--) DMI (--) Intel PCH Q470\n\n**From Intel PCH Q470 (Left Side):**\n*   L-OUT+MIC Header --) AUDIO CODEC\n*   L-OUT/IN/MIC Phone Jack (--) AUDIO CODEC (--) HDA (--) Intel PCH Q470\n*   SPDIF Header --) AUDIO CODEC\n*   4x SATA Port (--) SATAx4 (--) Intel PCH Q470\n*   RJ45 Port (--) I219-LM (--) PCIE1 (--) Intel PCH Q470\n*   RJ45 Port (--) I210-AT (--) PCIE1 (--) Intel PCH Q470\n*   PCIE x4 Port (--) PCIEx4 (--) Intel PCH Q470 (repeated 3 times)\n*   Mini-PCIE (--) PCIEx1 (--) Intel PCH Q470 (also labeled USB2.0x1)\n*   Mini-PCIE (--) SIM CARD\n*   M.2 Key-M Port (--) NVMe PCIEx4 or SATA Auto Detect (--) Intel PCH Q470\n*   2x PCI Port (--) PCI Bridge (--) PCIEx1 (--) Intel PCH Q470\n*   SMBus Header (--) SMBus (--) Intel PCH Q470\n*   F-PANEL (--) PWR-ON,RESET,HDD LED (--) Intel PCH Q470\n\n**From Intel PCH Q470 (Right Side - USB):**\n*   Intel PCH Q470 (--) USB3.0/USB2.0 x4 (--) 4x USB3.0\n*   Intel PCH Q470 (--) USB2.0x1 (--) USB2.0 Vertical-TYPE-A\n*   Intel PCH Q470 (--) USB2.0x4 (--) 4x USB2.0 Header\n*   Intel PCH Q470 (--) USB3.0/2.0x2 (--) 2x USB3.0\n*   Intel PCH Q470 (--) USB2.0x2 (--) 2x USB2.0 +PS2 Port\n\n**From Super I/O (connected to PCH via LPC):**\n*   Intel PCH Q470 (--) LPC (--) Super I/O\n*   Super I/O (--) KB+MS (--) 2x USB2.0 +PS2 Port\n*   Super I/O (--) COM1 RS232 (--) COM1 DB9M\n*   Super I/O (--) COM2/5/6 RS232 (--) COM2/5/6 Header\n*   Super I/O (--) COM3 RS232/485/422 (--) COM3 Header\n*   Super I/O (--) COM4 RS232/485 (--) COM4 Header\n*   Super I/O (--) FAN1~3 (--) FAN Header x3\n*   Super I/O (--) GPIOx8 (--) GPIO Header\n*   Super I/O (--) CASE OPEN Header\n*   Super I/O (--) AT/ATX MODE Jumper\n*   Intel PCH Q470 (--) SPI (--) TPM (option)](.imb-c46-50m-13017-1030-13/b5f4657e3df70bc5c29750acc04aa42a5bad655c18afa0a4c1d1154287b4daed.jpg)

Figure 1: Functional Block Diagram

RJ45\_USB1 (RJ45) I219-LM supports Intel AMT 12.0 and Intel vPro competent. RJ45\_USB2 (RJ45) supports I210 by default.
PCIEX16\_SLOT1-2 slot support PCIE 16x or dual PCIE 8x is selected by ‘PCI-E Signal Select Jumper’ (J\_PEG\_CFG1).

# 3 Mechanical Layout

# 3.1 IO Panel Connector Locations

![A\nB\nC\nD-2\nD\nI-1\nE\nF\nG\nH-4\nH-2\nH-3\nH-1\nI-3\nI-2\nE-1](.imb-c46-50m-13017-1030-13/32d58b32f81ca83dd7b38d57844396cb6ebc5f63e37e1e6eadb809bd93dd7d76.jpg)

Figure 2: IO Panel Connector Locations

Table 1:IO Panel Connector Definitions

<table><tr><td>Item</td><td>Location</td><td>Description</td></tr><tr><td>A</td><td>PS/2_USB1 (PS/2)</td><td>PS/2 Connector (Keyboard &amp; Mouse)</td></tr><tr><td>B</td><td>DVI_VGA1 (DVI-D)</td><td>DVI-I 24+4P/F Connector (Support DVI-D)</td></tr><tr><td>C</td><td>COM1</td><td>COM1 DB9/M Connector</td></tr><tr><td>D-1</td><td>RJ45_USB1 (LAN1)</td><td>GBE LAN RJ45 Connector1</td></tr><tr><td>D-2</td><td>RJ45_USB2 (LAN2)</td><td>GBE LAN RJ45 Connector2</td></tr><tr><td>E-1</td><td>PS/2_USB1 (USB1)</td><td>USB2.0 TYPE-A Connector</td></tr><tr><td>E-2</td><td>PS/2_USB1 (USB2)</td><td>USB2.0 TYPE-A Connector</td></tr><tr><td>F</td><td>DVI_VGA1 (VGA)</td><td>VGA DB15/F Connector</td></tr><tr><td>G</td><td>HDMI1</td><td>HDMI TYPE-A Connector</td></tr><tr><td>H-1</td><td>RJ45_USB1 (USB1)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-2</td><td>RJ45_USB1 (USB2)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-3</td><td>RJ45_USB2 (USB3)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-4</td><td>RJ45_USB2 (USB4)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>I-1</td><td>AUDIO1 (BLUE)</td><td>Line-In 3.5mm Jack</td></tr><tr><td>I-2</td><td>AUDIO1 (GREEN)</td><td>Line-Out 3.5mm Jack</td></tr><tr><td>I-3</td><td>AUDIO1 (PINK)</td><td>MIC-In 3.5mm Jack</td></tr></table>

![37 36 35 34\n33\n32-1 31-1\n32-2 31-2\n30\n38\n39\n29\n40\n28\n41\n27\n26\n25\n42\n24\n43\n22\n23-1 (Lower)\n23-2 (Upper)\n44\n45\n21\n46\n20\n47\n23-3 (Lower)\n23-4 (Upper)\n48\n19\n18\n17\n49\n50\n1 2 3 4 5 6 7 8-1 8-2 8-3 8-4 8-5\nADLINK IMB-C46](.imb-c46-50m-13017-1030-13/b26a48fb7e7e8532b7f4a802e49fa7305db4491117b49f03925f0048c1faf5fd.jpg)

Figure 3: Onboard Connector – Header and Jumper Locations

Table 2: Onboard Connector Definitions – Header and Jumper Definitions

<table><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>1</td><td>SYS_FAN1</td><td>System FAN Header1</td></tr><tr><td>2</td><td>SYS_FAN2</td><td>System FAN Header2</td></tr><tr><td>3</td><td>J_GPIO1</td><td>GPIO Header</td></tr><tr><td>4</td><td>F_USB2_2</td><td>Front USB2.0 Header2</td></tr><tr><td>5</td><td>F_USB2_1</td><td>Front USB2.0 Header1</td></tr><tr><td>6</td><td>F_PANEL1</td><td>Front Panel Header</td></tr><tr><td>7</td><td>JP12</td><td>COM2 DCD/RI Select Jumper</td></tr><tr><td>8-1</td><td>COM2</td><td>COM2 Header</td></tr><tr><td>8-2</td><td>COM3</td><td>COM3 Header</td></tr><tr><td>8-3</td><td>COM4</td><td>COM4 Header</td></tr><tr><td>8-4</td><td>COM5</td><td>COM5 Header</td></tr><tr><td>8-5</td><td>COM6</td><td>COM6 Header</td></tr><tr><td>9</td><td>JP8</td><td>COM3 DCD/RI Select Jumper</td></tr><tr><td>10</td><td>J_LPC1</td><td>Port80 Debug Header</td></tr><tr><td>11</td><td>J_ME1</td><td>ME Flash Jumper</td></tr><tr><td>12</td><td>JP9</td><td>COM4 DCD/RI Select Jumper</td></tr><tr><td>13</td><td>JP7</td><td>COM4 RS232/485 Select Jumper</td></tr><tr><td>14</td><td>J_AT/ATX1</td><td>AT or ATX Select Jumper</td></tr><tr><td>15</td><td>JP10</td><td>COM5 DCD/RI Select Jumper</td></tr><tr><td>16</td><td>JP11</td><td>COM6 DCD/RI Select Jumper</td></tr><tr><td>17</td><td>SMBUS1</td><td>SMBUS Header</td></tr><tr><td>18</td><td>M.2_PCIESSD_M1</td><td>M.2 (NGFF) Key-M Slot (PCIe x4 NVMe/SATA SSD, 2242/2280)</td></tr><tr><td>19</td><td>MPCIE1</td><td>Mini PCI-E Slot (WIFI+4G/3G)</td></tr><tr><td>20</td><td>J_COPEN1</td><td>Case Open Header</td></tr><tr><td>21</td><td>SIM1</td><td>Full-Size SIM Card Slot</td></tr><tr><td>22</td><td>JP1</td><td>CMOS Clear Jumper</td></tr><tr><td>23-1</td><td>SATA1</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>23-2</td><td>SATA2</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>23-3</td><td>SATA3</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>23-4</td><td>SATA4</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>24</td><td>JP6</td><td>COM3 RS232/422/485 Select Jumper3</td></tr><tr><td>25</td><td>JP5</td><td>COM3 RS232/422/485 Select Jumper2</td></tr><tr><td>26</td><td>JP4</td><td>COM3 RS232/422/485 Select Jumper1</td></tr><tr><td>27</td><td>J2</td><td>Data Burning Header</td></tr><tr><td>28</td><td>F_USB3_1</td><td>Front USB3.0 Header</td></tr><tr><td>29</td><td>USB2_1</td><td>USB2.0 Internal Vertical TYPE-A Connector</td></tr><tr><td>30</td><td>ATX1</td><td>ATX 24P Power Input Connector</td></tr><tr><td>31-1</td><td>DIMM2</td><td>DDR4 CHB DIMM Slot2</td></tr><tr><td>31-2</td><td>DIMM4</td><td>DDR4 CHB DIMM Slot4</td></tr><tr><td>32-1</td><td>DIMM1</td><td>DDR4 CHA DIMM Slot1</td></tr><tr><td>32-2</td><td>DIMM3</td><td>DDR4 CHA DIMM Slot3</td></tr><tr><td>33</td><td>CPU_FAN1</td><td>CPU FAN Header</td></tr><tr><td>34</td><td>ATX2</td><td>ATX 8P CPU Power Input Connector</td></tr><tr><td>35</td><td>ATX3</td><td>ATX 4P CPU Power Input Connector</td></tr><tr><td>36</td><td>EDP_P1</td><td>eDP Backlight Control Header</td></tr><tr><td>37</td><td>JP2</td><td>eDP VDD Select Jumper</td></tr><tr><td>38</td><td>EDP1</td><td>eDP Signal Header</td></tr><tr><td>39</td><td>JP3</td><td>COM1 DCD/RI Select Jumper</td></tr><tr><td>40</td><td>F_AUDIO1</td><td>Front Audio Header (Line-Out + MIC)</td></tr><tr><td>41</td><td>PCIE_16X_SLOT1</td><td>PCI-E 16x Slot1 (PCIe 16X GEN3) [1]</td></tr><tr><td>42</td><td>PCIE_4X_SLOT1</td><td>PCI-E 4x Slot1 (PCIe 4X GEN3)</td></tr><tr><td>43</td><td>JP13</td><td>SPDIF Out Header</td></tr><tr><td>44</td><td>PCI1</td><td>PCI Slot1</td></tr><tr><td>45</td><td>PCIEX16_SLOT2</td><td>PCI-E 16x Slot2 (PCIe 8X GEN3) [1]</td></tr><tr><td>46</td><td>JP14</td><td>PCI CLK 66MHz Enable/Disable Select Jumper</td></tr><tr><td>47</td><td>J_PEG_CFG1</td><td>PCI-E Signal Select Jumper</td></tr><tr><td>48</td><td>PCIE_4X_SLOT2</td><td>PCI-E 4x Slot2 (PCIe 4X GEN3)</td></tr><tr><td>49</td><td>PCI2</td><td>PCI Slot2</td></tr><tr><td>50</td><td>PCIE_4X_SLOT3</td><td>PCI-E 4x Slot3 (PCIe 4X GEN3)</td></tr></table>

Note: [1] When PCIEX16\_SLOT2 accesses the device, PCIE\_16X\_SLOT1 will automatically switch to PCIe 8X (Auto detected). This configuration can also be enforced by the ‘PCI-E Signal Select Jumper’ (J\_PEG\_CFG1).

# 3.2 Mechanical Dimensions

Top View
![243.84\n237.49\n165.10\n33.02\n10.16\n0.00\n0.00\n6.35\n163.83\n209.55\n288.29\n304.80](.imb-c46-50m-13017-1030-13/cc8d97c8e45013a2a88509818bb5a87a5b6fad2a73fb35c148653c39cd609d86.jpg)

Dimensions: mm

Figure 4: Mechanical Dimensions
Side View
![Diagram of various computer ports and connectors (no text or labels)](.imb-c46-50m-13017-1030-13/f4b07b9438ff9f9cf67db983abef0a0500540bb1fa9b74bbbf25b752d84ffbd2.jpg)

Dimensions: mm

Figure 5: Mechanical Dimensions - IO Panel

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# 4 Connector Pinouts

See 3.1 Connector Locations on page 7 for connector locations.

# 4.1 Rear IO Connectors

# 4.1.1 HDMI

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDMI1_CON_DP2</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>HDMI1_CON_DN2</td><td>4</td><td>HDMI1_CON_DP1</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>HDMI1_CON_DN1</td></tr><tr><td>7</td><td>HDMI1_CON_DP0</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>HDMI1_CON_DN0</td><td>10</td><td>HDMI1_CON_CKP</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>HDMI1_CON_CKN</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>HDMI1_DDC_CLK</td><td>16</td><td>HDMI1_DDC_DATA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5V_HDMI</td></tr><tr><td>19</td><td>HDMI1_CON_HPD</td><td></td><td></td></tr></table>

![This image displays a black-and-white schematic diagram of a connector, likely a D-sub connector, enclosed in a rounded rectangular outline. Inside, there are two rows of small squares representing pins.\n\nText labels indicate pin positions:\n*   **'19 17'** is located above the left side of the top row.\n*   **'3 1'** is located above the right side of the top row.\n*   **'18'** is located below the left side of the bottom row.\n*   **'4 2'** is located below the right side of the bottom row.\n\nA thick black horizontal bar runs beneath the bottom row of pins.](.imb-c46-50m-13017-1030-13/366c28b5043f497e8e5e9b405d9ae5450c8c3971d93efa656382c0d5a2c2639c.jpg)

# 4.1.2 VGA Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VGA_CON_RED</td><td>2</td><td>VGA_CON_GREEN</td></tr><tr><td>3</td><td>VGA_CON_BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>+5V_HDMI</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>VGA_DDCDAT</td></tr><tr><td>13</td><td>VGA_CON_HS</td><td>14</td><td>VGA_CON_VS</td></tr><tr><td>15</td><td>VGA_DDCCLK</td><td></td><td></td></tr></table>

![This is a black-and-white technical line drawing of a 15-pin D-sub connector. It features a rectangular outer shell with hexagonal mounting holes on the left and right sides. The central connector body contains three rows of five circular pins. The number '5' is positioned above the left side of the top row, and '1' is above the right side. The numbers '15' and '11' are located below the left and right sides of the bottom row, respectively.](.imb-c46-50m-13017-1030-13/7be92f6d4ba14be2a5d04d9db1c668bf60ad684b72a2c08cf8756132389cc7e9.jpg)

# 4.1.3 COM 1 (COM1 DB9/M Connector)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>COM1_PIN1 [1]</td><td>6</td><td>COM1_DSR</td></tr><tr><td>2</td><td>COM1_RXD</td><td>7</td><td>COM1_RTS</td></tr><tr><td>3</td><td>COM1_TXD</td><td>8</td><td>COM1_CTS</td></tr><tr><td>4</td><td>COM1_DTR</td><td>9</td><td>COM1_PIN9 [1]</td></tr><tr><td>5</td><td>GND</td><td></td><td></td></tr></table>

![The image displays a line drawing of a rectangular connector with rounded corners. Inside the outline, there are nine circular holes arranged in two staggered rows. The top row consists of five holes labeled with the numbers 1, 2, 3, 4, and 5 positioned above each respective hole. The bottom row consists of four holes labeled with the numbers 6, 7, 8, and 9 positioned below each respective hole. Small vertical slots are depicted on the far left and right sides of the rectangle.](.imb-c46-50m-13017-1030-13/cc41573979d0f975815d3337792a82b72ffa1c1540c6f3e5612dd3be9803921a.jpg)

Note: PIN1 of COM1 can be DCD (default) /5V and Pin9 of COM1 can be RI(Default) / 12V, selectable by “COM1 DCD/RI Select Jumper”. (JP3)

# 4.1.4 Ethernet Connectors (LAN1, LAN2)

RJ45\_USB2 (RJ45) \* (GBE LAN RJ45 Connector2 8Pin)

<table><tr><td>Pin</td><td colspan="2">Signal</td><td>Pin</td><td colspan="2">Signal</td></tr><tr><td>1</td><td colspan="2">MDI0_2+</td><td>5</td><td colspan="2">MDI2_2+</td></tr><tr><td>2</td><td colspan="2">MDI0_2-</td><td>6</td><td colspan="2">MDI2_2-</td></tr><tr><td>3</td><td colspan="2">MDI1_2+</td><td>7</td><td colspan="2">MDI3_2+</td></tr><tr><td>4</td><td colspan="2">MDI1_2-</td><td>8</td><td colspan="2">MDI3_2-</td></tr><tr><td rowspan="3">LED1</td><td rowspan="3">Speed LED</td><td>1000M: Turn Orange</td><td rowspan="3">LED2</td><td rowspan="3">Active LED</td><td>ACT: Blinking Yellow</td></tr><tr><td>100M: Turn Green</td><td>Only LINK: Lights On</td></tr><tr><td>10M: Lights Off</td><td>Stop: Lights Off</td></tr></table>

![The image displays a technical diagram of an RJ45 connector. At the top, the text '**LED1**' is positioned on the left and '**LED2**' is on the right. At the bottom, the number '**8**' is on the left and the number '**1**' is on the right. The central graphic shows a rectangular outline representing the connector housing with grey blocks inside indicating the pin contacts. Thin black lines connect the label '**8**' to the far left pin and the label '**1**' to the far right pin.](.imb-c46-50m-13017-1030-13/769c8aaf1858d0ff298a9adbdb5a74c5db94382c66beb5484ae6f9904dbffdba.jpg)
Note: RJ45\_USB2(RJ45) can support Wake-On-LAN.

RJ45\_USB1 (RJ45) \* (GBE LAN RJ45 Connector1 8Pin)

<table><tr><td>Pin</td><td colspan="2">Signal</td><td>Pin</td><td colspan="2">Signal</td></tr><tr><td>1</td><td colspan="2">MDI0_1+</td><td>5</td><td colspan="2">MDI2_1+</td></tr><tr><td>2</td><td colspan="2">MDI0_1-</td><td>6</td><td colspan="2">MDI2_1-</td></tr><tr><td>3</td><td colspan="2">MDI1_1+</td><td>7</td><td colspan="2">MDI3_1+</td></tr><tr><td>4</td><td colspan="2">MDI1_1-</td><td>8</td><td colspan="2">MDI3_1-</td></tr><tr><td rowspan="3">LED1</td><td rowspan="3">Speed LED</td><td>1000M: Turn Orange</td><td rowspan="3">LED2</td><td rowspan="3">Active LED</td><td>ACT: Blinking Yellow</td></tr><tr><td>100M: Turn Green</td><td>Only LINK: Lights On</td></tr><tr><td>10M: Lights Off</td><td>Stop: Lights Off</td></tr></table>

Note: RJ45\_USB1(RJ45) can support AMT and Wake-On-LAN.

# 4.2 Onboard Headers / Connectors

# 4.2.1 FAN Header (CPU\_FAN1, SYS\_FAN1, SYS\_FAN2)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>+12 V</td><td>FAN Power</td></tr><tr><td>3</td><td>Tach</td><td>FAN Tachometer</td></tr><tr><td>4</td><td>PWM</td><td>FAN PWM</td></tr></table>

![The image displays the number '1' on the left side. Next to it is a vertical rectangle containing a column of four circles; the top three circles are solid black, while the bottom circle is white with a black border and a small black dot inside it. To the right of the rectangle is the number '4'. A small black speck is visible just outside the bottom right corner of the rectangle.](.imb-c46-50m-13017-1030-13/50c76293db9aca2939c9ebe11c8669844331c1f57ed24c43abee040d8ffe4e36.jpg)

# 4.2.2 Front Panel Header (F\_PANEL1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDD 3.3V LED+</td><td>2</td><td>POWER 3.3V LED+</td></tr><tr><td>3</td><td>HDD 3.3V LED-</td><td>4</td><td>POWER 3.3V LED-</td></tr><tr><td>5</td><td>RESET-</td><td>6</td><td>POWER+</td></tr><tr><td>7</td><td>RESET+</td><td>8</td><td>POWER-</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr></table>

# 4.2.3 COM Header (COM 2/3/4/5/6)

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM2 RS232</td><td>1</td><td>COM2_DCD</td><td>2</td><td>COM2_DSR</td></tr><tr><td>3</td><td>COM2_RXD</td><td>4</td><td>COM2_RTS</td></tr><tr><td>5</td><td>COM2_TXD</td><td>6</td><td>COM2_CTS</td></tr><tr><td>7</td><td>COM2_DTR</td><td>8</td><td>COM2_RI</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

![1\n2](.imb-c46-50m-13017-1030-13/847382c62940fc6e294e321472ab08b1e5eafb78d82369f19558abf043ffa365.jpg)

Note: COM3 can be RS232 (default) / RS422 / RS485 by selecting JP4, JP5, JP6.

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM3 RS232 [2]</td><td>1</td><td>COM3_DCD</td><td>2</td><td>COM3_DSR</td></tr><tr><td>3</td><td>COM3_RXD</td><td>4</td><td>COM3_RTS</td></tr><tr><td>5</td><td>COM3_TXD</td><td>6</td><td>COM3_CTS</td></tr><tr><td>7</td><td>COM3_DTR</td><td>8</td><td>COM3_RI</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">COM3 RS422 [2]</td><td>1</td><td>RS422_TX-</td><td>2</td><td>N/C</td></tr><tr><td>3</td><td>RS422_TX+</td><td>4</td><td>N/C</td></tr><tr><td>5</td><td>RS422_RX+</td><td>6</td><td>N/C</td></tr><tr><td>7</td><td>RS422_RX-</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr><tr><td rowspan="2">COM3 RS485 [2]</td><td>1</td><td>RS485-</td><td>2</td><td>N/C</td></tr><tr><td>3</td><td>RS485+</td><td>4</td><td>N/C</td></tr><tr><td rowspan="3"></td><td>5</td><td>N/C</td><td>6</td><td>N/C</td></tr><tr><td>7</td><td>N/C</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr></table>

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM4 RS232 [2]</td><td>1</td><td>COM4_DCD</td><td>2</td><td>COM4_DSR</td></tr><tr><td>3</td><td>COM4_RXD</td><td>4</td><td>COM4_RTS</td></tr><tr><td>5</td><td>COM4_TXD</td><td>6</td><td>COM4_CTS</td></tr><tr><td>7</td><td>COM4_DTR</td><td>8</td><td>COM4_RI</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">COM4 RS485 [2]</td><td>1</td><td>RS485-</td><td>2</td><td>N/C</td></tr><tr><td>3</td><td>RS485+</td><td>4</td><td>N/C</td></tr><tr><td>5</td><td>N/C</td><td>6</td><td>N/C</td></tr><tr><td>7</td><td>N/C</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr></table>

Note: When COM4 is RS232, COM4 can be RS232 (default) / RS485 selecting by “COM4 RS232/RS485 Select Jumper”. (JP7).

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM5 RS232</td><td>1</td><td>COM5_DCD</td><td>2</td><td>COM5_DSR</td></tr><tr><td>3</td><td>COM5_RXD</td><td>4</td><td>COM5_RTS</td></tr><tr><td>5</td><td>COM5_TXD</td><td>6</td><td>COM5_CTS</td></tr><tr><td>7</td><td>COM5_DTR</td><td>8</td><td>COM5_RI</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

<table><tr><td></td><td>Pin</td><td>Definition</td><td>Pin</td><td>Definition</td></tr><tr><td rowspan="5">COM6 RS232</td><td>1</td><td>COM6_DCD</td><td>2</td><td>COM6_DSR</td></tr><tr><td>3</td><td>COM6_RXD</td><td>4</td><td>COM6_RTS</td></tr><tr><td>5</td><td>COM6_TXD</td><td>6</td><td>COM6_CTS</td></tr><tr><td>7</td><td>COM6_DTR</td><td>8</td><td>COM6_RI</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

4.2.4 SATA Connector (SATA 1-2/3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>5</td><td>RXN</td><td>Receive diff data – negative</td></tr><tr><td>2</td><td>TXP</td><td>Transmit diff data – positive</td><td>6</td><td>RXP</td><td>Receive diff data – positive</td></tr><tr><td>3</td><td>TXN</td><td>Transmit diff data – negative</td><td>7</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>GND</td><td>Ground</td><td></td><td></td><td></td></tr></table>

![This image is a black-and-white technical line drawing showing a vertical rectangular outline. Inside this outline is a long, narrow vertical strip with alternating black and white sections. To the right of the drawing, separated by a vertical line, are the numbers 1 and 7.](.imb-c46-50m-13017-1030-13/f97f5378705a09b57fe4e61c13d4d6e5442782de2aee600f8d706adc12fdfa26.jpg)

# 4.2.5 USB Connectors

USB 2.0 Header (F\_USB2\_1, F\_USB2\_2)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+ 5V</td><td>2</td><td>+ 5V</td></tr><tr><td>3</td><td>USB2_P-</td><td>4</td><td>USB2_P-</td></tr><tr><td>5</td><td>USB2_P+</td><td>6</td><td>USB2_P+</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td></td><td></td><td>10</td><td>DUMMY</td></tr></table>

![The image shows a vertical stack of five rounded rectangles. The top four rectangles each contain two small squares on the left side and two small squares on the right side. The bottom rectangle contains one small square on the right side, with the left side empty. To the left of the top rectangle is the number '1', and to the right is the number '2'.](.imb-c46-50m-13017-1030-13/7d088c29dd07fb76d510cba4f544a677f402a6628bfacb04e34fa1f1a23698ec.jpg)

USB 3.0 Header (F\_USB3\_1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td></td><td></td><td>1</td><td>+ 5V</td></tr><tr><td>19</td><td>+ 5V</td><td>2</td><td>USB3_RXD5-</td></tr><tr><td>18</td><td>USB3_RXD6-</td><td>3</td><td>USB3_RXD5+</td></tr><tr><td>17</td><td>USB3_RXD6+</td><td>4</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>5</td><td>USB3_TXD5-</td></tr><tr><td>15</td><td>USB3_TXD6-</td><td>6</td><td>USB3_TXD5+</td></tr><tr><td>14</td><td>USB3_TXD6+</td><td>7</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>8</td><td>USB2_11-</td></tr><tr><td>12</td><td>USB2_10-</td><td>9</td><td>USB2_11+</td></tr><tr><td>11</td><td>USB2_10+</td><td>10</td><td>N/C</td></tr></table>

![19\n1\n2](.imb-c46-50m-13017-1030-13/605727b47820c6e10c1913cfd7ec24bb4c10dacaddbc52dde19d41f13f303adb.jpg)

4.2.6 Front Panel Audio Header (F\_AUDIO1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>MIC_IN2_L</td><td>2</td><td>GND_AUD</td></tr><tr><td>3</td><td>MIC_IN2_R</td><td>4</td><td>+ 3.3V</td></tr><tr><td>5</td><td>LINE_OUT2_R</td><td>6</td><td>MIC2_RET</td></tr><tr><td>7</td><td>GND_AUD</td><td></td><td></td></tr><tr><td>9</td><td>LINE_OUT2_L</td><td>10</td><td>LINE_OUT2_RET</td></tr></table>

![The image displays a vertical stack of four rounded rectangular outlines. To the left of the top rectangle is the number '1' and to the right is the number '2'. Inside each of the four rectangles, there are two smaller rectangular outlines arranged side-by-side. In the top, second, and bottom rectangles, these smaller outlines contain small central dots. The third rectangle from the top contains two empty rectangular outlines.](.imb-c46-50m-13017-1030-13/55424ab87d399f00b9dec63d2e5a14c026988ea021ff2403661b9c802b396574.jpg)

# 4.2.7 ATX1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3 V</td><td>13</td><td>+3.3 V</td></tr><tr><td>2</td><td>+3.3 V</td><td>14</td><td>-12 V</td></tr><tr><td>3</td><td>Ground</td><td>15</td><td>Ground</td></tr><tr><td>4</td><td>+5 V</td><td>16</td><td>PS-ON# (power supply remote on/off)</td></tr><tr><td>5</td><td>Ground</td><td>17</td><td>Ground</td></tr><tr><td>6</td><td>+5 V</td><td>18</td><td>Ground</td></tr><tr><td>7</td><td>Ground</td><td>19</td><td>Ground</td></tr><tr><td>8</td><td>PWRGD (Power Good)</td><td>20</td><td>No connect</td></tr><tr><td>9</td><td>+5 V (Standby)</td><td>21</td><td>+5 V</td></tr><tr><td>10</td><td>+12 V</td><td>22</td><td>+5 V</td></tr><tr><td>11</td><td>+12 V</td><td>23</td><td>+5 V</td></tr><tr><td>12</td><td>3.3V</td><td>24</td><td>Ground</td></tr></table>

![1\n2\n24](.imb-c46-50m-13017-1030-13/110a198715cd20d0c66cd33efda8651dfbcdbb0e9c7e8e0e044eeffb10d9672a.jpg)

# 4.2.8 ATX2

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>Ground</td><td>5</td><td>+12V</td></tr><tr><td>2</td><td>Ground</td><td>6</td><td>+12V</td></tr><tr><td>3</td><td>Ground</td><td>7</td><td>+12V</td></tr><tr><td>4</td><td>Ground</td><td>8</td><td>+12V</td></tr></table>

![The image displays a schematic pinout diagram of a connector. It features a rectangular outline containing two columns of three circular pads. The bottom-left pad is depicted as a square.\n\nText labels indicate specific pins:\n- The number **2** is positioned to the left of the top-left pad.\n- The number **1** is positioned to the left of the bottom-left pad, accompanied by a small arrow pointing right towards the square pad.\n- The number **5** is positioned to the right of the bottom-right pad.](.imb-c46-50m-13017-1030-13/1286f5e88498dc329bf88cd435289b25b675d7dc9ca5fd5dac6ecd06188b1bd0.jpg)

# 4.2.9 ATX3

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>Ground</td></tr><tr><td>2</td><td>Ground</td></tr><tr><td>3</td><td>+12V</td></tr><tr><td>4</td><td>+12V</td></tr></table>

![The image displays a schematic diagram of a 4-pin connector layout. It features a large square outline enclosing four smaller rectangular pads arranged in a 2x2 grid. Inside each pad is a smaller solid square.\n\nThe pins are numbered as follows:\n*   The top-left pad is labeled **3** to its left.\n*   The bottom-left pad is labeled **4** to its left.\n*   The top-right pad is labeled **1** to its right.\n*   The bottom-right pad is labeled **2** to its right.\n\nThe outer rectangular outlines for the top-left (pin 3) and bottom-right (pin 2) pads appear to have small notches or cutouts on their corners.](.imb-c46-50m-13017-1030-13/db067cf2d9ab567ad98940d12f44c3babdb798c4fc384f7a9ba74fda64812a2a.jpg)

# 4.2.10 GPIO Header (J\_GPIO1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>SIO_GPI70(0xA06 Bit0, H [1])</td><td>2</td><td>SIO_GPI71(0xA06 Bit1, H)</td></tr><tr><td>3</td><td>SIO_GPI72(0xA06 Bit2, H)</td><td>4</td><td>SIO_GPI73(0xA06 Bit3, H)</td></tr></table>

![1 2](.imb-c46-50m-13017-1030-13/9813795ac9c35db75a6c418f4e04471c44b551d4be7ee4f246cabb5d3e6bdfe3.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>SIO_GPO74(0xA06 Bit4, H)</td></tr><tr><td>7</td><td>SIO_GPO75(0xA06 Bit5, H)</td><td>8</td><td>SIO_GPO76(0xA06 Bit6, H)</td></tr><tr><td>9</td><td>SIO_GPO77(0xA06 Bit7, H)</td><td>10</td><td>+ 5V</td></tr><tr><td></td><td></td><td>12</td><td>N/C</td></tr></table>

Note: “H” or “L” means the default voltage is High or Low level. (5V GPIO).

# 4.2.11 Port80 Debug Header (J\_LPC1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>LFRAME_N</td><td>6</td><td>GND</td></tr><tr><td>2</td><td>LPC_AD3</td><td>7</td><td>SIO_PCIRST1_N</td></tr><tr><td>3</td><td>LPC_AD2</td><td>8</td><td>CLK_LPC0</td></tr><tr><td>4</td><td>LPC_AD1</td><td>9</td><td>+ 3.3V</td></tr><tr><td>5</td><td>LPC_AD0</td><td></td><td></td></tr></table>

![The image features the number '1' in the top left corner. To its right is a vertical column of eight identical white rectangular shapes. Each shape has rounded corners, a black outline, and contains two small black squares stacked vertically inside.](.imb-c46-50m-13017-1030-13/61c7cbbac560b337410fb63b33302443838d8110c62b8e26eddf852503e04689.jpg)

# 4.2.12 SPDIF Header (JP13)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+ 5V</td><td>3</td><td>SPDIF_OUT</td></tr><tr><td></td><td></td><td>4</td><td>GND</td></tr></table>

![The image displays the number 1 on the left side. To the right is a vertical column of four rounded rectangular outlines stacked on top of one another. Inside each rectangle is a small icon resembling a square with a smaller square inside.](.imb-c46-50m-13017-1030-13/ccf864cdb3f80cdf509e2b210bfb7b779a5c5f3eb0b9b49491b4fe6d5c82e8d6.jpg)

# 4.2.13 SMBUS Header (SMBUS1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+ 5V [1]</td><td>3</td><td>SMB_DATA_MAIN</td></tr><tr><td>2</td><td>SMB_CLK_MAIN</td><td>4</td><td>GND</td></tr></table>

![The image displays a schematic line drawing of a USB Type-A connector. To the left of the connector is the number '1'. Inside the connector housing, there are four pairs of small rectangular contacts stacked vertically.](.imb-c46-50m-13017-1030-13/87bef6307c9e9b7fb83f696fbafddd4a1fedf887dff429dd0dad12beae860a0d.jpg)

# 4.3 Jumper and Switch Settings

# 4.3.1 Clear CMOS Jumper (JP1)

![The image shows the text '1_2' at the top. Below it are three square icons. The first two are dark grey squares with white circles inside. The third is a white square with a black border and a black circle inside.](.imb-c46-50m-13017-1030-13/ce7ce93ceec7c6a8d54a1fb41b1ff5f8cb3993896a1fc4df6471bd8a9a958398.jpg)
Default

![The image displays a close-up of a digital interface element, likely a pagination indicator. At the top, the text '2_3' is visible in black font. Below this text is a horizontal row of three square indicators. The leftmost square is white with a black border and contains a white circle. The middle and rightmost squares are dark grey, each containing a small white dot in the center.](.imb-c46-50m-13017-1030-13/128bf815e794416ee4855ee22071f448a8014c294e0e519a4bce45db8e5e16ba.jpg)
Clear CMOS

1-2 : Normal
2-3 : Clear CMOS

# 4.3.2 COM1 DCD/RI Select Jumper (JP3)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM1_PIN1: DCDCOM1_PIN9: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM1_PIN1: + 5VCOM1_PIN9: RI</td></tr></table>

# 4.3.3 COM2 DCD/RI Select Jumper (JP12)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM2_PIN1: DCDCOM2_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM2_PIN1: + 5VCOM2_PIN8: RI</td></tr></table>

# 4.3.4 COM3 DCD/RI Select Jumper $( \mathsf { J P 8 } )$

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM3_PIN1: DCDCOM3_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM3_PIN1: + 5VCOM3_PIN8: RI</td></tr></table>

# 4.3.5 COM4 DCD/RI Select Jumper (JP9)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM4_PIN1: DCDCOM4_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM4_PIN1: + 5VCOM4_PIN8: RI</td></tr></table>

# 4.3.6 COM5 DCD/RI Select Jumper $( \mathsf { J P 1 0 } )$

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM5_PIN1: DCDCOM5_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM5_PIN1: + 5VCOM5_PIN8: RI</td></tr></table>

![The image displays the number '1' on the left and '2' on the right. Between these numbers are two columns of white rounded rectangular icons, each containing a smaller grey square inside. A red rectangular outline highlights the top two icons in the left column, and another red rectangular outline highlights the bottom two icons in the right column.](.imb-c46-50m-13017-1030-13/a1797339435fe8c2d9da6364a5cb849059ac99b5538ff7a5702c238a78d63bc4.jpg)

![The image displays the number 1 on the far left and the number 2 on the far right. Between these numbers are two vertical columns of the number 1, arranged in three rows, with each digit enclosed in a rounded rectangle. A red rectangular outline highlights the entire left column of three 1s, and a second red rectangular outline highlights the bottom two 1s of the right column.](.imb-c46-50m-13017-1030-13/08760051eee9daf6960e78af676c9b779926b8dfae570a67b687952d195aa096.jpg)

![The image displays the numbers '1' and '2' in black text at the top. Below each number is a vertical column of three light grey, rounded rectangular buttons, each containing a small square icon in the center. A red rectangular outline highlights the top two buttons in the left column (under the '1'), and another red rectangular outline highlights the bottom two buttons in the right column (under the '2').](.imb-c46-50m-13017-1030-13/1872187fe20b482250d84d89af2f251c5cc9f7c345f47414e486efd25798dcb2.jpg)

![The image displays the number '1' on the left and the number '2' on the right. Between these numbers is a grid of icons, each consisting of a square shape containing a smaller square in its center.\n\nTwo red rectangular outlines highlight specific icons:\n*   On the left side, a red box encloses the top two icons in the column.\n*   On the right side, a red box encloses the middle and bottom icons in that column.\n\nThe top-right icon and the bottom-left icon are unhighlighted.](.imb-c46-50m-13017-1030-13/3646b5e021b0a72389b363d39fca19a4eeb6b5958fb0f97df4b50efd908613e6.jpg)

![The image displays the numbers '1' and '2' in black at the top. Below these numbers are four square icons, each containing a smaller square in the center, arranged in two columns. The top icon in the left column (under the '1') and the bottom icon in the right column (under the '2') are enclosed in red rectangular outlines, while the remaining two icons have faint grey outlines.](.imb-c46-50m-13017-1030-13/2ac5a4a0257cc2d05e956d0bf5b0a46aedd1d7cc4a0f286e142835f893f175ea.jpg)

# 4.3.7 COM6 DCD/RI Select Jumper (JP11)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM6_PIN1: DCDCOM6_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM6_PIN1: + 5VCOM6_PIN8: RI</td></tr></table>

![The image shows the numbers '1' and '2' at the top. Below are two columns of boxes. A red rectangle outlines the left column of three boxes, and another red rectangle outlines the lower two boxes of the right column. Each box contains a small grey square.](.imb-c46-50m-13017-1030-13/c79ca3a7036d2b0a51193dfcca03835f6f9921c6ec7550b5d1f640f42ab2f5c4.jpg)

# 4.3.8 COM4 RS232/485 Select Jumper (JP7)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM4: RS485(COM4_PIN1: RS485-COM4_PIN3: RS485+)</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM4: RS232(COM4_PIN1: DCDCOM4_PIN3: RXD)</td></tr></table>

![The image displays the number '1' on the left and the number '2' on the right. Centered between them is a schematic diagram of a window. The window features a top section with two small square panes side-by-side, and a lower section divided into two vertical columns, each containing two stacked panes. The lower section, comprising four panes, is outlined in blue.](.imb-c46-50m-13017-1030-13/2ce45e5a2e5475997d10670bcdca7a6d366b42ae3cb200d4c6fda689b1f46d04.jpg)

# 4.3.9 COM3 RS232/485 Select Jumpers (JP4/JP5/JP6)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>JP4 (1-2, Default)JP5 (3-5, 4-6, Default)JP6 (3-5, 4-6, Default)</td><td>COM3: RS232(COM3_PIN1: DCDCOM3_PIN3: RXDCOM3_PIN5: TXDCOM3_PIN7: DTR)</td></tr><tr><td>JP4 (3-4)JP5 (1-3, 2-4)JP6 (1-3, 2-4)</td><td>COM3: RS422(COM3_PIN1: RS422_TX-COM3_PIN3: RS422_TX+COM3_PIN5:RS422_RX+COM3_PIN7:RS422_RX-)</td></tr><tr><td>JP4 (5-6)JP5(1-3, 2-4)JP6 (No Effect)</td><td>COM3: RS485(COM3_PIN1: RS485-COM3_PIN3: RS485+)</td></tr></table>

![The image shows a cropped view of a digital interface. At the very top, centered, is the text 'JP4'. Below this, there are three rectangular boxes stacked vertically. The top box has a blue border and is flanked by the number '1' on the left and '2' on the right. Inside the top box are two small square icons side-by-side. Below it are two more boxes with white borders, each also containing two small square icons.](.imb-c46-50m-13017-1030-13/ed864d213c1356dc7a0f7f82127539a0e8087deaa12efabd4deb050188984b0c.jpg)

![The image displays a schematic symbol for an electronic connector.\n\n**Text:**\n*   'JP5' is centered at the top.\n*   '1' is positioned to the left of the connector.\n*   '2' is positioned to the right of the connector.\n\n**Graphic:**\n*   The central graphic depicts a 2x3 pin header (6 pins total).\n*   **Top Section:** A white rectangular outline with rounded top corners containing two small square pins side-by-side.\n*   **Bottom Section:** A blue rectangular area divided into two vertical columns. Each column contains two small square pins stacked vertically. This section sits directly below the white top section.](.imb-c46-50m-13017-1030-13/d841e0c5714bd2cd58afd1f2658d418767b7bab9f3ca9982df14281a35d77bd8.jpg)

![The image displays a schematic symbol for an electronic connector. At the top center, the text 'JP6' appears in black. Below this, large grey numbers '1' and '2' flank the left and right sides of the connector component. The connector itself is depicted as a rectangular block divided horizontally. The upper section is white and contains two square pads side-by-side. The lower section is blue and is divided vertically into two columns, with each column containing four square pads arranged in a vertical stack.](.imb-c46-50m-13017-1030-13/0b3cbdcff1d65c51366ee1506e58f37374b1ff7c2a859448a69eb37e5649cfab.jpg)

# 4.3.10 ME Flash Jumper (J\_ME1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Open (Default)</td><td>ME Protect Enable</td></tr><tr><td>1-2: Connected</td><td>ME Protect Disable</td></tr></table>

![The image displays the number '18'. On the far left is a thick vertical black bar. Next to it is the digit '1'. To the right is the digit '8'. Inside the upper section of the '8', there is a small square containing a smaller square. Inside the lower section of the '8', there is a similar small square containing a smaller square.](.imb-c46-50m-13017-1030-13/c70feb919a5336f98df47ab57be875d463454ec1ef56bf11e9c111a216bc650e.jpg)

# 4.3.11 AT or ATX Select Jumper (J\_AT/ATX1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>ATX Mode</td></tr><tr><td>2-3</td><td>AT Mode</td></tr></table>

![The image displays a large number '1' on the left side. To the right is a vertical column of three rounded rectangular buttons. The top two buttons are enclosed within a blue outline. Inside each button is a small icon resembling a table or grid symbol.](.imb-c46-50m-13017-1030-13/151964121c1d2726f884ad5043df85e7d878d1d664ae855ef3ff1f8858ca0e63.jpg)

# 4.3.12 Case Open Header (J\_COPEN1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Connected</td><td>Active Case Open</td></tr><tr><td>1-2: Open</td><td>Normal</td></tr></table>

![The image displays the number **18**. The digits are rendered in a large, black, segmented font style on a white background. The digit '1' is positioned on the left and the digit '8' is on the right.](.imb-c46-50m-13017-1030-13/c6349859f1398762602c31d7a6543219a67f38cc7ff7e9e68bef22c4ae607299.jpg)

# 4.3.13 Data Burning Header (J2)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GP3.0_RXD</td><td>3</td><td>GND</td></tr><tr><td>2</td><td>GP3.1_TXD</td><td></td><td></td></tr></table>

# 4.3.14 eDP Backlight Control Header (EDP\_P1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>4</td><td>EDP_BKLT_EN</td></tr><tr><td>2</td><td>GND</td><td>5</td><td>+ 12V</td></tr><tr><td>3</td><td>EDP_BKLT_CTL</td><td>6</td><td>+ 12V</td></tr><tr><td>1</td><td>GND</td><td>4</td><td>EDP_BKLT_EN</td></tr></table>

# 4.3.15 eDP Signal Header (EDP1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VDD_PANEL [1]</td><td>2</td><td>VDD_PANEL [1]</td></tr><tr><td>3</td><td>VDD_PANEL [1]</td><td></td><td></td></tr><tr><td>5</td><td>GND</td><td>6</td><td>EDP_HPD</td></tr><tr><td>7</td><td>N/C</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td>10</td><td>N/C</td></tr><tr><td>11</td><td>N/C</td><td>12</td><td>N/C</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>N/C</td><td>16</td><td>N/C</td></tr><tr><td>17</td><td>N/C</td><td>18</td><td>N/C</td></tr><tr><td>19</td><td>EDP_TX0-</td><td>20</td><td>EDP_TX0+</td></tr><tr><td>21</td><td>EDP_TX1-</td><td>22</td><td>EDP_TX1+</td></tr></table>

![The image displays a large number '1' on the left side, aligned with a vertical column of three identical rectangular icons on the right. Each rectangular icon features a small document or file symbol inside.](.imb-c46-50m-13017-1030-13/2dd89a5ad1f11d68b332c4ff96e4108097306ec6af231a1a8d47bcf9b772212f.jpg)

![The image features a vertical column of five small squares enclosed within a larger rectangular outline. To the left of the lower section of the rectangle is the number '1'. Small, L-shaped lines are visible near the top-left and bottom-left interior corners of the rectangle.](.imb-c46-50m-13017-1030-13/d085ad870ee10840dc3bc016c0bb4a14e56d0228b8aa41eaece9c68fb00fa9b0.jpg)

![1\n2](.imb-c46-50m-13017-1030-13/5025dee6c3bd9d6a4b754908a81593e1abd7db92ab4a2497cf53fe48d40a38ca.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>23</td><td>EDP_TX2-</td><td>24</td><td>EDP_TX2+</td></tr><tr><td>25</td><td>GND</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>EDP_TX3-</td><td>28</td><td>EDP_TX3+</td></tr><tr><td>29</td><td>EDP_AUX-</td><td>30</td><td>EDP_AUX+</td></tr></table>

Note: Panel Power VDD can be 3.3V (default) /5V selectable by eDP VDD Select Jumper” (JP2).

# 4.3.16 PCI CLK 66MHz Enable/Disable Select Jumper (JP14)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>Disable PCI CLK 66MHz</td></tr><tr><td>2-3</td><td>Enable PCI CLK 66MHz</td></tr></table>

![A large number '1' is shown next to a vertical column of three rectangular boxes. Each box contains a small icon resembling a list or document. The top two boxes are enclosed in a blue outline, indicating they are selected, while the bottom box is unselected.](.imb-c46-50m-13017-1030-13/29181f8cbefc8b6c3eb1309035ac8836be7605271f22dfe4cd2a3998af698030.jpg)

# 4.3.17 PCIE Signal Select Jumper (J\_PEG\_CFG1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>PCIE_16X_SLOT1: PCIe 16XPCIE_16X_SLOT2: No resources</td></tr><tr><td>2-3</td><td>PCIE_16X_SLOT1: PCIe 8XPCIE_16X_SLOT2: PCIe 8X</td></tr></table>

![The image displays the number 1 on the left side. To its right is a vertical column of three stacked rectangular boxes. The top two boxes are enclosed in a blue outline, and each box contains a small icon resembling a face or user symbol.](.imb-c46-50m-13017-1030-13/3659c4927949683cd88514a40d4db04153d00a1f7541c4591f1a638070b18129.jpg)

# 4.4 Expansion Slots

There are 5 PCI Express slots, 2 PCI slots, 1 M.2 sockets, 1 mini-PCIe slot, and 1 SIM socket on this motherboard.

PCIe and PCI slots:

<table><tr><td></td><td>Slot 1 (PCIe1)</td><td>Slot 2 (PCIe2)</td><td>Slot 3 (PCI1)</td><td>Slot 4 (PCIe3)</td><td>Slot 5 (PCIe4)</td><td>Slot 6 (PCI2)</td><td>Slot 7 (PCIe5)</td></tr><tr><td>Source</td><td>CPU</td><td>PCH</td><td>PCI bridge</td><td>CPU</td><td>PCH</td><td>PCI bridge</td><td>PCH</td></tr><tr><td>Bandwidth</td><td>PCIe 3.0</td><td>PCIe 3.0</td><td>PCI</td><td>PCIe 3.0</td><td>PCIe 3.0</td><td>PCI</td><td>PCIe 3.0</td></tr><tr><td>Lane Config 1</td><td>X16</td><td rowspan="2">X4</td><td rowspan="2">PCI</td><td>N/A</td><td rowspan="2">X4</td><td rowspan="2">PCI</td><td rowspan="2">X4</td></tr><tr><td>Lane Config 2</td><td>X8</td><td>X8</td></tr></table>

SIM socket: 1 x SIM socket connected to Mini PCIe

# M.2 sockets:

• M.2 Key-M (M\_2\_PCIESSD\_M1)

<table><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>GND</td><td>+3.3V</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>+3.3V</td><td>4</td></tr><tr><td>5</td><td>PERn3</td><td>NA</td><td>6</td></tr><tr><td>7</td><td>PERp3</td><td>NA</td><td>8</td></tr><tr><td>9</td><td>GND</td><td>SATA_LED</td><td>10</td></tr><tr><td>11</td><td>PETn3</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>PETp3</td><td>+3.3V</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>16</td></tr><tr><td>17</td><td>PERn2</td><td>+3.3V</td><td>18</td></tr><tr><td>19</td><td>PERp2</td><td>NA</td><td>20</td></tr><tr><td>21</td><td>GND</td><td>NA</td><td>22</td></tr><tr><td>23</td><td>PETn2</td><td>NA</td><td>24</td></tr><tr><td>25</td><td>PETp2</td><td>NA</td><td>26</td></tr><tr><td>27</td><td>GND</td><td>NA</td><td>28</td></tr><tr><td>29</td><td>PERn1</td><td>NA</td><td>30</td></tr><tr><td>31</td><td>PERp1</td><td>NA</td><td>32</td></tr><tr><td>33</td><td>GND</td><td>NA</td><td>34</td></tr><tr><td>35</td><td>PETn1</td><td>NA</td><td>36</td></tr><tr><td>37</td><td>PETp1</td><td>DEVSLP</td><td>38</td></tr><tr><td>39</td><td>GND</td><td>SMB_CLK</td><td>40</td></tr><tr><td>41</td><td>PERn0/ SATA-B+</td><td>SMB_DATA</td><td>42</td></tr><tr><td>43</td><td>PERp0/ SATA-B-</td><td>NA</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>NA</td><td>46</td></tr><tr><td>47</td><td>PETn0/ SATA-A-</td><td>NA</td><td>48</td></tr><tr><td>49</td><td>PETPO/ SATA-A+</td><td>PERST#</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>CLKREQ#</td><td>52</td></tr><tr><td>53</td><td>PEFCLKn</td><td>WAKE#</td><td>54</td></tr><tr><td>55</td><td>PEFCLKp</td><td>NA</td><td>56</td></tr><tr><td>57</td><td>GND</td><td>NA</td><td>58</td></tr><tr><td colspan="4"></td></tr><tr><td>67</td><td>NA</td><td>NA</td><td>68</td></tr><tr><td>69</td><td>PEDET</td><td>+3.3V</td><td>70</td></tr><tr><td>71</td><td>GND</td><td>+3.3V</td><td>72</td></tr><tr><td>73</td><td>GND</td><td>+3.3V</td><td>74</td></tr><tr><td>75</td><td>GND</td><td></td><td></td></tr></table>

# 5 Driver Installation

Download the requisite drivers for your system from the IMB-C46 product page at:

https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/ATXMotherboards/IMB-C46

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# 6 BIOS Setup

# 6.1 Menu Structure

This section presents the primary menus of the BIOS (UEFI) Setup Utility. Use the following table as a quick reference forthe contents of the UEFI Setup Utility. The subsections describe the submenus and options for each menu item.

Options to enter BIOS Setup Utility:

• Press [F2] or [Del] during POST (Power-On-Self-Test)
• Press [Ctl] + [Alt] + [Del] after POST

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td></tr><tr><td>Sets up the system time/date and displays the system information:- BIOS Information- Memory Information- System Date- System Time</td><td>Contains advanced system configurations, including:► CPU Configuration► Power and Performance► PCH-FW Configuration► Trusted Computing► ACPI Settings► Super IO Configuration► Hardware Monitor► OEM Flavor► Power Control► S5 RTC Wake Settings► USC Configuration► Network Stack Configuration► CSM Configuration► NVME Configuration</td><td>Displays Hardware Status info, including:► System Agent (SA) Configuration► PCH-IO Configuration</td></tr><tr><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>Changes or clears the supervisor/user password for the system:- Administrator Password- User Password► Secure Boot</td><td>Configures the boot settings and boot priority for available devices:- Setup Prompt Timeout- Bootup Num Lock State- Full Screen Logo- Fast Boot- Boot Mode Select- Boot Option #X</td><td>Exits the BIOS Setup Utility while saving or discard the changes made:- Save/Discard Changes and Exit- Save/Discard Changes and Reset- Save/Discard Changes- Default Options- Restore Defaults- Save as User Defaults- Restore User Defaults- Boot Override- BIOS: Built-in EFI shell-</td></tr></table>

# 6.2 Main Menu

Upon entering the UEFI Setup Utility, the Main Menu is displayed, providing read-only information about your system and also allows you to set the System Date and Time. Refer to the screenshots and tables below for details of the submenus and settings.

<table><tr><td>Feature</td><td>Options</td></tr><tr><td colspan="2">BIOS Information</td></tr><tr><td>BIOS Vendor</td><td>Info only</td></tr><tr><td>Core Version</td><td>Info only</td></tr><tr><td>Compliancy</td><td>Info only</td></tr><tr><td>Project Version</td><td>IMB-C46_xxxxx</td></tr><tr><td>Build Date and Time</td><td>Info only</td></tr><tr><td>Access Level</td><td>Info only</td></tr><tr><td colspan="2">Memory Information</td></tr><tr><td>Total Memory</td><td>Info only</td></tr><tr><td>Memory Frequency</td><td>Info only</td></tr><tr><td>System Date</td><td>xxx mm/dd/yyyy</td></tr><tr><td>System Time</td><td>hh:mm:ss</td></tr></table>

# 6.3 Advanced

This menu contains the following information:

<table><tr><td colspan="2">Feature</td></tr><tr><td>▶ CPU Configuration</td><td>▶ OEM Flavor</td></tr><tr><td>▶ Power &amp; Performance</td><td>▶ Power Control</td></tr><tr><td>▶ PCH-FW Configuration</td><td>▶ S5 RTC Wake Settings</td></tr><tr><td>▶ Trusted Computing</td><td>▶ USB Configuration</td></tr><tr><td>▶ ACPI Settings</td><td>▶ Network Stack Configuration</td></tr><tr><td>▶ Super IO Configuration</td><td>▶ CSM Configuration</td></tr><tr><td>▶ Hardware Monitor</td><td>▶ NVME Configuration</td></tr></table>

# 6.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Type</td><td>Displays the Processor Type.</td></tr><tr><td>ID</td><td>Displays the Processor ID.</td></tr><tr><td>Speed</td><td>Displays the Processor Speed.</td></tr><tr><td>L1 Data Cache</td><td>Displays the Processor L1 Data Cache size.</td></tr><tr><td>L1 Instruction Cache</td><td>Displays the Processor L1 Instruction Cache size.</td></tr><tr><td>L2 Cache</td><td>Displays the Processor L2 Data Cache size.</td></tr><tr><td>L3 Cache</td><td>Displays the Processor L3 Data Cache size.</td></tr><tr><td>L4 Cache</td><td>Displays the Processor L4 Data Cache size.</td></tr><tr><td>VMX</td><td>VMX Supported or Not.</td></tr><tr><td>SMX/TXT</td><td>SMX/TXT Supported or Not.</td></tr><tr><td>Turbo Mode</td><td>Enable or disable processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled)</td></tr><tr><td>Intel (VWX) Virtualization Technology</td><td>When enabled, a VWX can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr></table>

# 6.3.2 Power and Performance

Power and performance option.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>▶ CPU - Power Management Control</td><td>CPU - Power Management Control Options.</td></tr><tr><td>▶ GT - Power Management Control</td><td>GT - Power Management Control Options.</td></tr></table>

6.3.2.1 CPU-Power Management Control

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Boot performance mode</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) Speed Step(tm)</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Race To Halt (RTH)</td><td>Enables or disables Race to Halt feature. RTH will dynamically increase CPU frequency to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20).</td></tr><tr><td>Intel(R) Speed Shift technology</td><td>Enables or disables Intel(R) Speed Shift technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Intel(R) adaptive Boost technology</td><td>Enables or disables IABT to improve performance by allowing higher multi-core turbo frequencies.</td></tr><tr><td>Per Core P State OS control mode</td><td>For RKL only. Enables or disables Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.</td></tr><tr><td>HwP Autonomous Per Core P State</td><td>For RKL only. Disables Autonomous PCPS (Bit 30 = 1, command 0x11). Autonomous will request the same value for all cores all the time. Enables PCPS (default Bit 30 = 0, command 0x11).</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>For RKL only. Enables EPP grouping (default Bit 29=0, command 0x11). Autonomous will request the same value for all cores with same EPP. Disables EPP grouping (Bit 29 = 1, command 0x11). Autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>For RKL only. Enables or disables EPB override over PECI. Enabled by sending pcode command 0x2b, subcommand 0x3 to 1. This will allow 00B EPB PECI override control.</td></tr><tr><td>Hwp Fast MSR Support</td><td>For RKL only. Enables or disables Hwp Fast MSR Support for IA32_HWP_REQUEST MSR.</td></tr><tr><td>HDC Control</td><td>This option allows HDC configuration:Disabled: Disables HDC.Enabled: Can be enabled by OS if OS native support is available.</td></tr><tr><td>Turbo Mode</td><td>Enables or disables processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled).</td></tr><tr><td>► View/Configure Turbo options</td><td>View/Configure Turbo options.</td></tr><tr><td>Config TDP Configurations</td><td>Config TDP Configurations.</td></tr><tr><td>► CPU VR Settings</td><td>CPU VR Settings.</td></tr><tr><td>Platform PL1 Enable</td><td>Enables or disables Platform Power Limit 1 programming.If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of a given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>Enables or disables Platform Power Limit 2 programming.If this option is disabled, BIOS will program the default values for Platform Power Limit 2.</td></tr><tr><td>Power Limit 4 override</td><td>Enables or disables Power Limit 4 override.If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>Enables or disables CPU Power Management.Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Thermal Monitor</td><td>Enables or disables Thermal Monitor.</td></tr><tr><td>Timed MWAIT</td><td>Enables or disables Timed MWAIT Support.</td></tr><tr><td>► Custom P-state Table</td><td>Adds Custom P-state Table.</td></tr><tr><td>Energy Performance Gain</td><td>Enables or disables Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>Displays EPG DIMM ldd3N.</td></tr><tr><td>EPG DIMM ldd3P</td><td>Displays EPG DIMM ldd3P.</td></tr><tr><td>► Power Limit 3 Settings</td><td>Power Limit 3 Settings.</td></tr><tr><td>► CPU Lock Configuration</td><td>CPU Lock Configuration.</td></tr><tr><td>Dual Tau Boost</td><td>Enables Dual Tau Boost feature. This is only applicable for CMLS 35W/65W/125W SKU. When DPTF is enabled, this feature is ignored.</td></tr></table>

6.3.2.1.1 View/Configuration Turbo Options

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Energy Efficient P-state</td><td>Enable or disable the Energy Efficient P-state feature. When set to 0, access to ENERGY_PERFORMANCE_BIAS MSR is disabled, and CPUID Function 6 ECX[3] will read 0, indicating no support for Energy Efficient policy setting. When set to 1, access to ENERGY_PERFORMANCE_BIAS MSR 1B0h is enabled, and CPUID function 6 ECX[3] will read 1, indicating Energy Efficient policy setting is supported.</td></tr><tr><td>Package Power Limit MSR Lock</td><td>Enable or disable locking of Package Power limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked, and a reset will be required to unlock the register.</td></tr><tr><td>Power Limit 1 Override</td><td>Enable or disable Power Limit 1 override. If this option is disabled, the BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.</td></tr><tr><td>Power Limit 2 Override</td><td>Enable or disable Power Limit 2 override. If this option is disabled, the BIOS will program the default values for Power Limit 2.</td></tr><tr><td>Power Limit 2</td><td>The Power Limit 2 value is in milliwatts. The BIOS will round it to the nearest 1/8W during programming. If the value is 0, the BIOS will program this value as 1.25 * TDP. For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Turbo Ratio Limit Core0 (TRLC)</td><td>Turbo Ratio Limit Core0. This Turbo Ratio Limit Core0 must be less than the Turbo Ratio Limit Core1.</td></tr><tr><td>Turbo Ratio Limit Core1 (TRLC)</td><td>Turbo Ratio Limit Core1. This Turbo Ratio Limit Core1 must be less than the Turbo Ratio Limit Core2.</td></tr><tr><td>Turbo Ratio Limit Core2 (TRLC)</td><td>Turbo Ratio Limit Core2. This Turbo Ratio Limit Core2 must be less than the Turbo Ratio Limit Core3.</td></tr><tr><td>Turbo Ratio Limit Core3 (TRLC)</td><td>Turbo Ratio Limit Core3. This Turbo Ratio Limit Core3 must be less than the Turbo Ratio Limit Core4.</td></tr><tr><td>Turbo Ratio Limit Core4 (TRLC)</td><td>Turbo Ratio Limit Core4. This Turbo Ratio Limit Core4 must be less than the Turbo Ratio Limit Core5.</td></tr><tr><td>Turbo Ratio Limit Core5 (TRLC)</td><td>Turbo Ratio Limit Core5. This Turbo Ratio Limit Core5 must be less than Turbo Ratio Limit Core6.</td></tr><tr><td>Turbo Ratio Limit Core6 (TRLC)</td><td>Turbo Ratio Limit Core6. This Turbo Ratio Limit Core6 must be less than Turbo Ratio Limit Core7.</td></tr><tr><td>Turbo Ratio Limit Core7 (TRLC)</td><td>Turbo Ratio Limit Core7. This Turbo Ratio Limit Core7 must be the greatest of all Turbo Ratio Limits.</td></tr><tr><td>Turbo Ratio Limit Ratio0 (TRLR)</td><td>Turbo Ratio Limit Ratio0 (TRLR) with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio. Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit0 is paired with Turbo Ratio NumCores0 and must be greater than or equal to all other ratio values. If this value is invalid, then set all other active cores to minimum. Otherwise, align the Ratio Limit to 0. Please check each active core.</td></tr><tr><td>Turbo Ratio Limit Ratio1 (TRLR)</td><td>Turbo Ratio Limit Ratio1 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit1 is paired with Turbo Ratio NumCores1 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio2 (TRLR)</td><td>Turbo Ratio Limit Ratio2 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit2 is paired with Turbo Ratio NumCores2 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio3 (TRLR)</td><td>Turbo Ratio Limit Ratio3 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit3 is paired with Turbo Ratio NumCores3 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio4 (TRLR)</td><td>Turbo Ratio Limit Ratio4 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit4 is paired with Turbo Ratio NumCores4 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio5 (TRLR)</td><td>Turbo Ratio Limit Ratio5 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit5 is paired with Turbo Ratio NumCores5 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio6 (TRLR)</td><td>Turbo Ratio Limit Ratio6 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit6 is paired with Turbo Ratio NumCores6 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio7 (TRLR)</td><td>Turbo Ratio Limit Ratio7 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit7 is paired with Turbo Ratio NumCores7 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Energy Efficient Turbo</td><td>Enable or disable the Energy Efficient Turbo feature. This feature will opportunistically lower the turbo frequency to increase efficiency. It is recommended to disable it only in overclocking situations where the turbo frequency must remain constant. Otherwise, leave it enabled.</td></tr></table>

6.3.2.1.2 CPU VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Power Delivery Design</td><td>Specifies the CML-S board design used for the VR settings override values. By default, the BIOS will override the default CML-S VR settings based on the board design. A value of AUTO (0) will use the board ID to determine the board design. Any other value will override the board ID logic to provide a custom VR Power Delivery Design value. This feature is intended primarily for validation.</td></tr><tr><td>PSYS Slope</td><td>PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9.</td></tr><tr><td>PSYS Offset</td><td>PSYS Offset defined in 1/4 increments. Range is 0-255. For an offset of 25, enter 100. Uses BIOS VR mailbox command 0x9.</td></tr><tr><td>PSYS PMax Power</td><td>PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.</td></tr><tr><td>▶ Acoustic Noise Setting</td><td>Configure Acoustic Noise Settings for IA, GT, and SA domains.</td></tr><tr><td>► Core/IA VR Settings</td><td>Core/IA VR Settings.</td></tr><tr><td>► GT VR Settings</td><td>GT VR Settings.</td></tr><tr><td>Intersil VR Command</td><td>VR Mailbox command to fix Intersil VR C-state issues. Disabled- No Mailbox command sent. Default is Disabled.</td></tr></table>

6.3.2.1.2.1 Acoustic Noise Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Acoustic Noise Mitigation</td><td>Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state. This needs to be enabled to program PreWake, Ramp Up, and Ramp Down times.</td></tr></table>

6.3.2.1.2.2 Core/IA VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Config Enable</td><td>VR Config Enable</td></tr><tr><td>AC Loadline</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS3 Enable</td><td>Enable or Disable PS3. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS4 Enable</td><td>Enable or Disable PS4. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Regulator Limit</td><td>Voltage Regulator Current Limit (Icc Max). This value represents the maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. Uses BIOS VR mailbox command 0x6.</td></tr><tr><td>TDC Enable</td><td>TDC Enable. 0- Disable, 1 - Enable.</td></tr><tr><td>TDC Current Limit</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = Auto/Intel Default. Uses the BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.</td></tr><tr><td>TDC Lock</td><td>Enabled or Disabled TDC Lock.</td></tr></table>

6.3.2.1.2.3 GT VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Config Enable</td><td>VR Config Enable.</td></tr><tr><td>AC Loadline</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS3 Enable</td><td>Enable or Disable PS3. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command0x3.</td></tr><tr><td>PS4 Enable</td><td>Enable or Disable PS4. 0 - Disabled, 1 - Enabled. It uses the BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. It uses the BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Regulator Limit</td><td>Voltage Regulator Current limit (Icc Max). This value represents the maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. It uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. It uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>TDC Enable</td><td>TDC Enable. 0 - Disable, 1 - Enable.</td></tr><tr><td>TDC Current Limit</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = Auto/Intel Default. It uses the BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.</td></tr><tr><td>TDC Lock</td><td>Enabled or Disabled TDC Lock.</td></tr></table>

# 6.3.2.1.3 Custom P-State Table Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Number of P states</td><td>Sets the number of custom P-states. At least 2 states must be present.</td></tr></table>

# 6.3.2.1.4 Power Limit 3 Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Power Limit 3 Override</td><td>Enable or disable Power Limit 3 Override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr></table>

# 6.3.2.1.5 CPU Lock Configuration Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>CFG Lock</td><td>Configure MSR 0xE2[15], CFG Lock bit.</td></tr><tr><td>Overclocking Lock</td><td>Enable or Disable Overclocking Lock (BIT 20) in FLEX_RATIO (194) MSR.</td></tr></table>

# 6.3.2.2 GT-Power Management Control

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>RC6 (Render Standby)</td><td>Check to enable render standby support.</td></tr><tr><td>Maximum GT frequency</td><td>Maximum GT frequency limited by the user. Choose between 350MHz (RPN) and 1200MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU.</td></tr><tr><td>Disable Turbo GT frequency</td><td>Enabled: Disables Turbo GT frequency.Disable: GT frequency is not limited.</td></tr></table>

# 6.3.3 PCH-FW Configuration

Configure management engine technology parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>ME State</td><td>When disabled, ME will be put into ME Temporarily disabled Mode.</td></tr><tr><td>Firmware Update Configuration</td><td>Configure Management</td></tr></table>

# 6.3.3.1 Firmware Update Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>ME FW Image Re-Flash</td><td>Enables or disables ME FW Image Re-Flash function.</td></tr><tr><td>FW Update</td><td>Enables or disables ME FW Update function.</td></tr></table>

# 6.3.4 Trusted Computing

Trusted computing settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Firmware Version</td><td>Displays TPM Firmware Version.</td></tr><tr><td>Vendor</td><td>Displays TPM Vendor.</td></tr><tr><td>Security Device Support</td><td>Enables or disables Security Device. NOTE: Your computer will reboot during restart in order to change State of the Device.</td></tr><tr><td>Active PCR Banks</td><td>Displays Active PCR banks.</td></tr><tr><td>Available PCR Banks</td><td>Displays Available PCR banks.</td></tr><tr><td>SHA256 PCR Bank</td><td>Enables or disables SHA256 PCR Bank.</td></tr><tr><td>Pending Operation</td><td>Schedule an Operation for the Security Device. NOTE: Your computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Platform Hierarchy</td><td>Enables or disables Platform Hierarchy.</td></tr><tr><td>Storage Hierarchy</td><td>Enables or disables Storage Hierarchy.</td></tr><tr><td>Endorsement Hierarchy</td><td>Enables or disables Endorsement Hierarchy.</td></tr><tr><td>Physical Presence Spec Version</td><td>Select to inform the O.S. to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.</td></tr><tr><td>TPM 2.0 Interface Type</td><td>Selects the Communication Interface to TPM 2.0 device.</td></tr><tr><td>Device Select</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated.</td></tr></table>

# 6.3.5 ACPI Settings

Set ACPI (Advanced Configuration and Power Management Interface) parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Enables or disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Enables or disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Select the highest ACPI sleep state that the system will enter when the SUSPEND button is pressed.</td></tr></table>

# 6.3.6 Super IO Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>COM1-6</td><td>Set Parameters of Serial Port 1-6.The options after entering the interface settings above are as follows.Serial Port: Enables or Disables Serial Port (COM).Device Settings: Displays the Current Device Settings.Change Settings: If the board supported, this menu shows. Select an optimal setting for Super IO Device.</td></tr><tr><td>CHASSIS OPEN</td><td>Enable or disable CHASSIS OPEN Function.</td></tr></table>

# Set Up Chassis Open Detection：

1. Select “Advanced – Super IO Configuration - CHASSIS OPEN” (This menu shows only that this function is supported).
2. Set the item to “Enabled”. Sound the alarm if the chassis is opened; stop it when closed.

When the open-box detection cap is shorted, the chassis is considered compromised. The post interface will prompt for intrusion alarms, and the status record needs to be cleared to close the alarm.

# Clear Chassis Open Status：

In the BIOS Setup Utility, press the F3 key and then the Enter key to load the optimized default value. After that, save and exit to clear the out-of-box status record.

# 6.3.7 Hardware Monitor

Monitor the hardware status.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Fan function</td><td>FAN1 Mode: FAN1 Mode Select. Full on Mode; Automatic Mode; Manual Mode.</td></tr><tr><td>CPU Temp</td><td>Displays CPU Temperature.</td></tr><tr><td>SYS Temp</td><td>Displays System Temperature.</td></tr><tr><td>CPU_FAN1</td><td>Displays CPU FAN Speed.</td></tr><tr><td>SYS_FAN1</td><td>Displays System FAN1 Speed.</td></tr><tr><td>SYS_FAN2</td><td>Displays System FAN2 Speed.</td></tr><tr><td>VCC_CPU</td><td>Displays CPU Core Voltage Value.</td></tr><tr><td>VCC_DDR</td><td>Displays Memory Voltage Value.</td></tr><tr><td>+12</td><td>Displays +12 Voltage Value.</td></tr><tr><td>+5</td><td>Displays +5 Voltage Value.</td></tr><tr><td>+3.3</td><td>Displays +3.3 Voltage Value.</td></tr></table>

# Set Up Fan Control:

1. Select “Advanced - Hard Monitor - Fan Function” (This menu shows only that this function is supported);
2. Select the fan to set up, such as “CPU\_FAN1 Mode”. Select the operating mode for this fan: Full On Mode, Automatic Mode, and Manual Mode.
3. After selecting the manual mode and manual speed mode, the Manual PWM Setting inputs PWM value (sets the range from 0 to 255) to specify the fan speed.
4. After selecting Automatic Mode, there will have options to set up fan off temperature limit, fan start temperature limit, fan start PWM, and PWM SLOPE SETTING.

Generally, due to differences in fan performance, the actual performance of smart fans may vary from the set value. It is generally recommended to set the PWM SLOPE SETTING to 8PWM to ensure that the fan speed adjusts appropriately with temperature changes.

# 6.3.8 OEM Flavor

PXE boot LAN select.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PXE Boot Lan Select</td><td>PXE Boot LAN Select.</td></tr><tr><td>PCIE OOR FIXED Enabled</td><td>Enables or disables PCIE OOR FIXED.</td></tr></table>

# 6.3.9 Power Control

<table><tr><td>Power button control settings.Feature</td><td>Description</td></tr><tr><td>PowerOn After PowerFail</td><td>Specify what state to go to when power is re-applied after a power failure (G3 state).</td></tr><tr><td>Soft-Off by PWR-BTTN</td><td>Soft-Off by PWR-BTTN.</td></tr><tr><td>ME Function Ctrl</td><td>ME Function Ctrl.</td></tr></table>

# Set Up Power-on Self:

1. Select “Advanced - Power Control - PowerOn After PowerFail”.
2. Change “Power On After Power Fail” value: Power Off, Power On, Last State.

# 6.3.10 S5 RTC Wake Settings

Enable the system to wake from S5 using RTC alarm.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Wake system from S5</td><td>Enables or disables the system wake on alarm event. Select Fixed Time, system will wake on the hr::min::sec specified. Select Dynamic Time, System will wake on the current time + Increase minute(s).</td></tr></table>

# Set Up Timed Power On:

1. Select “Advanced - S5 RTC Wake Settings - Wake system from S5.”
2. Change it from Disabled to Fixed Time.
3. Set the time for customizing the boot settings in “Wake up day, Wake up hour, Wake up minute, wake up second”. For example, setting day: 2, hour: 13, minute:0, second:0 means the system will boot on the 2nd of each month at 13:00. Setting day as 0 means that the system is will boot at the given specified time every day.

# 6.3.11 USB Configuration

USB configuration parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Displays USB Configuration.</td></tr><tr><td>Legacy USB Support</td><td>Enables Legacy USB Support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-Off</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>Enables or disables USB Mass Storage Driver Support.</td></tr><tr><td>USB Transfer Time-Out</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device Reset Time-Out</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device Power-Up Delay</td><td>Maximum time the device will take before it properly reports itself to the Host Controller. ‘Auto’ uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.</td></tr></table>

# 6.3.12 Network Stack Configuration

Network Stack Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Network Stack</td><td>Enables or disables UEFI Network Stack</td></tr></table>

# Open UEFI PXE:

1. Please select “Advanced - Network Stack Configuration.”
2. Set Network Stack or UEFI PXE to Enable.

# 6.3.13 CSM Configuration

CSM (Compatibility Support Module) configuration: Enable/disable, option ROM execution settings, etc.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>CSM Support</td><td>Enables or Disables CSM Support.</td></tr><tr><td>CSM16 Module Version</td><td>CSM16 Module Version.</td></tr><tr><td>GateA20 Active</td><td>UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>INT19 Trap Response</td><td>BIOS reaction on INT19 trapping by Option ROM: IMMEDIATE - execute the trap right away; POSTPONED - execute the trap during legacy boot.</td></tr><tr><td>HDD Connection Order</td><td>Some OS require HDD handled to be adjusted, i.e., OS is installed on drive 80h.</td></tr><tr><td>Boot Option Filter</td><td>This option controls Legacy/UEFI ROMs priority.</td></tr><tr><td>Network</td><td>Controls the execution of UEFI and Legacy Network OpROM.</td></tr><tr><td>Storage</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI Devices</td><td>Determines OpROM execution policy for devices other than Network, Storage, or Video.</td></tr></table>

# Open Legacy PXE:

1) Please select “Advanced - CSM configuration.”
2) Change network item to legacy.

# 6.3.14 NVMe Configuration

NVMe device option settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>NVMe Devices</td><td>Displays information about NVMe devices.</td></tr><tr><td>Self-Test Option</td><td>Select either short or extended self-test. Short option will take a couple of minutes and extended option will take several minutes to complete.</td></tr><tr><td>Self-Test Action</td><td>Select either to test controller alone or controller and namespace. Selecting controller and namespace option will take longer to complete the test.</td></tr><tr><td>Run Device Self-Test</td><td>Perform device self-test for the corresponding option and action selected by user. Pressing ‘ESC’ key will abort the test. Result shown below is the recent result logged in the device.</td></tr></table>

# 6.4 Chipset

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► System Agent (SA) Configuration</td><td>System Agent (SA) Parameters.</td></tr><tr><td>► PCH-IO Configuration</td><td>PCH Parameters.</td></tr></table>

# 6.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>▶ Memory Configuration</td><td>Memory Configuration Parameters.</td></tr><tr><td>▶ Graphics Configuration</td><td>Graphics Configuration.</td></tr></table>

# 6.4.1.1 Memory Configuration Parameters

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► Memory Thermal Configuration</td><td>Memory Thermal Configuration Options.</td></tr><tr><td>► Memory Training Algorithms</td><td>Enables or disables Memory Training Algorithms.</td></tr><tr><td>Memory Configuration</td><td>Memory Configuration Parameters.</td></tr><tr><td>MRC ULT Safe Config</td><td>MRC ULT Safe Config for PO.</td></tr><tr><td>Safe Mode Support</td><td>Safe Mode enable support. Option will be used for changes/WAs that may affect a stable MRC.</td></tr><tr><td>Memory Test on Warm Boot</td><td>Enable or disable Base Memory Test Run on Warm Boot.</td></tr><tr><td>Maximum Memory Frequency</td><td>Maximum Memory Frequency Selections in MHz. Valid values should match the refclk, i.e. divide by 133 or 100.</td></tr><tr><td>HOB Buffer Size</td><td>Size to set HOB Buffer.</td></tr><tr><td>ECC Support</td><td>Enables or disables DDR Ecc Support.</td></tr><tr><td>Max TOLUD</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on the largest MMIO length of the installed graphic controller.</td></tr><tr><td>DDR Speed Control</td><td>DDR Frequency and Gear1 / Gear2 control for all SAGV points.</td></tr><tr><td>Retrain on Fast Fail</td><td>Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled.</td></tr><tr><td>RMT on Fast</td><td>Runs RMT on Fast flow.</td></tr><tr><td>BER Support</td><td>Enables or disables the Rank Margin Tool interpolation/extrapolation.</td></tr><tr><td>Enable RH Prevention</td><td>Actively prevent Row Hammer.</td></tr><tr><td>Row Hammer Solution</td><td>Type of method used to prevent Row Hammer.</td></tr><tr><td>RH Activation Probability</td><td>Used to adjust MC for Hardware RHP.</td></tr><tr><td>Refresh Watermarks</td><td>Sets Refresh Panic Watermark and Refresh High-Profile Watermark to HIGH or LOW values.</td></tr><tr><td>Exit On Failure (MRC)</td><td>Exit On Failure for MRC training steps.</td></tr><tr><td>Probeless Trace</td><td>Enables or disables capacity to activate Probeless Trace feature.</td></tr><tr><td>Enable or disable IED (Intel Enhanced Debug)</td><td>Intel Enhanced Debug requires 4MB Runtime memory.</td></tr><tr><td>Ch Hash Support</td><td>Enables or disables Channel Hash Support. 0 is Default (Auto) value - programs 2 in HASH_LSB_MASK, HASK_MASK value of 0x2094 for LPDDR4 and 0x30CC for NON-LPDDR4. NOTE: ONLY if Memory interleaved Mode.</td></tr><tr><td>Ch Hash Mask</td><td>Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6].</td></tr><tr><td>Ch Hash Interleaved Bit</td><td>Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interleave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8.</td></tr><tr><td>Per Bank Refresh</td><td>Enable and disable the per bank refresh. This only impacts memory technologies that support PBR: LPDDR3, LPDDR4.</td></tr><tr><td>Strong Weak Leaker</td><td>Value for StrongWkLeaker.</td></tr><tr><td>Memory Scrambler</td><td>Enable or disable Memory Scrambler support.</td></tr><tr><td>Force ColdReset</td><td>Force ColdReset OR Choose MrcColdBoot mode, when Coldboot is required during MRC execution. Note: If ME 5.0MB is present, ForceColdReset is required.</td></tr><tr><td>Channel A DIMM Control</td><td>Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.</td></tr><tr><td>Channel B DIMM Control</td><td>Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.</td></tr><tr><td>Force Single Rank</td><td>When enabled, only Rank 0 will be used in each DIMM.</td></tr><tr><td>Memory Remap</td><td>Enables or disables Memory Remap above 4GB.</td></tr><tr><td>Time Measure</td><td>Enables or disables printing of the time it takes to execute MRC.</td></tr><tr><td>DLL Weak Lock Support</td><td>Enables or disables Dll Weaklock support.</td></tr><tr><td>Pwr Down Idle Timer</td><td>The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo.</td></tr><tr><td>Fast Boot</td><td>Enables or disables fast path thru the MRC.</td></tr><tr><td>Train On Warm boot</td><td>Enables or disables training on warm boot.</td></tr><tr><td>Rank Margin Tool Per Task</td><td>Enables or disables RMT running at every major training step.</td></tr><tr><td>Training Tracing</td><td>Enables or disables printing of the current trained state at every major training step.</td></tr><tr><td>Lpddr Mem WL Set</td><td>Only applicable to LPDDR, Memory Write Latency Set selection (A is default, B will be used if memory devices support it).</td></tr><tr><td>BDAT ACPI Table Support</td><td>Enables support for the BDAT ACPI table.</td></tr><tr><td>BDAT Memory Test Type</td><td>Indicates the type of Memory Training data to populate into the BDAT ACPI table.</td></tr><tr><td>Rank Margin Tool Loop Count</td><td>Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO.</td></tr></table>

6.4.1.1.1 Memory Thermal Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► Memory Power and Thermal Throttling</td><td>Memory Power and Thermal Throttling Configuration</td></tr><tr><td>Memory Thermal Management</td><td>Enable or disable Memory Thermal Management.</td></tr><tr><td>PECI Injected Temperature</td><td>Enable or disable memory temperatures to be injected to the processor via PECI.</td></tr><tr><td>EXTT# via TS-on-Board</td><td>Enable or disable routing TS-on-Board&#x27;s ALERT# and THERM# to EXTTS# pins on the PCH.</td></tr><tr><td>EXTT# via TS-on-DIMM</td><td>Enable or disable routing TS-on-DIMM&#x27;s ALERT# to EXTTS# pin on the PCH.</td></tr></table>

6.4.1.1.1.1 Memory Power and Thermal Throttling

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>DDR PowerDown and idle counter</td><td>BIOS: BIOS is in control of DDR CKE mode and idle timer value. PCODE: pcode will manage the modes.</td></tr><tr><td>For LPDDR Only: DDR PowerDown and idle counter</td><td>For LPDDR Only: BIOS is in control of DDR CKE mode and idle timer value. PCODE: pcode will manage the modes.</td></tr><tr><td>REFRESH_2X_MODE</td><td>0- Disabled, 1- iMC enables 2xRef when Warm and Hot, 2- iMC enables 2xRef when Hot.</td></tr><tr><td>LPDDR Thermal Sensor</td><td>When enabled, MC uses MR4 to read LPDDR thermal sensors.</td></tr><tr><td>SelfRefresh Enable</td><td>Enable, disable (Enable= Def).</td></tr><tr><td>SelfRefresh IdleTimer</td><td>Self Refresh idle timer in nCK units: 0 = Auto (default), or value in range [512 .. 65535].</td></tr><tr><td>Throttler CKEMin Defeature</td><td>Enable or disable Throttler CKEMin Defeature.</td></tr><tr><td>Throttler CKEMin Timer</td><td>Timer value for CKEMin, range [255;0]. Required min of SC_ROUND_T + BYTE_LENGTH (4).</td></tr><tr><td>► Dram Power Meter</td><td>Dram Power Meter Configuration</td></tr><tr><td>► Memory Thermal Reporting</td><td>Memory Thermal Reporting Configuration</td></tr><tr><td>► Memory RAPL</td><td>Memory RAPL Configuration</td></tr></table>

6.4.1.1.1.1.1 DRAM Power Meter

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Use user provided power weights, scale factor, and channel power floor values</td><td>Enabled: User provided power weights, scale factor, and channel power floor values are used. Disabled: BIOS sets power weights, scale factor, and channel power floor values based on the DIMMs present in the system.</td></tr></table>

6.4.1.1.1.1.2 Memory Thermal Reporting

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Lock Thermal Management Registers</td><td>Enabled: lock several PCU registers related to DDR power/thermal management</td></tr><tr><td>Extern Therm Status</td><td>Enabled: The value from EXTTS is used; Disabled: Pcode ignores the EXTTS.</td></tr><tr><td>Closed Loop Therm Manage</td><td>Enabled: CLTM pcode algorithm will be used. Note: CLTM will precede OLTM.</td></tr><tr><td>Open Loop Therm Manage</td><td>Enabled: OLTM pcode algorithm will be used. Note: CLTM will precede OLTM.</td></tr><tr><td>Warm/Hot Threshold/Budget Ch0/1 Dimm0/1</td><td>range [255;0] = [31.875;0] in W for OLTM, [127.5;0] in C for CLTM.</td></tr></table>

6.4.1.1.1.1.3 Memory RAPL

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>RAPL PL Lock</td><td>Enable = lock Rapl Limit register, Disable (Disable = Default)</td></tr><tr><td>RAPL PL 1/2 Enable</td><td>Enable = enable, Disable (Disable = Default)</td></tr><tr><td>RAPL PL 1/2 Power</td><td>range [0; 2^14-1] = [2047.875; 0] in W, (0 = Default)</td></tr><tr><td>RAPL PL 1/2 WindowX</td><td>Power PL 1/2 time window X value, (1/1024) * (1 + (x/4)) * (2^y) (0 = Default)</td></tr><tr><td>RAPL PL 1/2 WindowY</td><td>Power PL 1/2 time window Y value, (1/1024) * (1 + (x/4)) * (2^y) (0 = Default)</td></tr></table>

6.4.1.1.2 Memory Training Algorithms

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Early Command Training</td><td>Early Command Training.</td></tr><tr><td>SenseAmp Offset Training</td><td>SenseAmp Offset Training.</td></tr><tr><td>Early ReadMPR Timing Centering 2D</td><td>Enabled or disabled Early ReadMPR Timing.</td></tr><tr><td>Read MPR Training</td><td>Read MPR Training.</td></tr><tr><td>Receive Enable Training</td><td>Receive Enable Training.</td></tr><tr><td>Jedec Write Leveling</td><td>Jedec Write Leveling.</td></tr><tr><td>LPDDR4 Write DQ DQS Retraining</td><td>LPDDR4 Write DQ DQS Retraining.</td></tr><tr><td>Early Write Time Centering 2D</td><td>Early Write Time Centering 2D.</td></tr><tr><td>Early Read Time Centering 2D</td><td>Early Read Time Centering 2D.</td></tr><tr><td>Write Timing Centering 1D</td><td>Write Timing Centering 1D.</td></tr><tr><td>Write Voltage Centering 1D</td><td>Write Voltage Centering 1D.</td></tr><tr><td>Read Timing Centering 1D</td><td>Read Timing Centering 1D.</td></tr><tr><td>Dimm ODT Training</td><td>Dimm On-Die Termination Training.</td></tr><tr><td>DIMM RON Training</td><td>DIMM RON Training.</td></tr><tr><td>Write Drive Strength/Equalization 2D</td><td>Enabled or disabled Write Drive Strength/Equalization 2D.</td></tr><tr><td>Write Slew Rate Training</td><td>Write Slew Rate Training.</td></tr><tr><td>Read ODT Training</td><td>Read On-Die Termination Training.</td></tr><tr><td>Read Equalization Training</td><td>Read Equalization Training.</td></tr><tr><td>Read Amplifier Training</td><td>Read Amplifier Training.</td></tr><tr><td>Write Timing Centering 2D</td><td>Write Dq-Dqs Timing Centering 2D.</td></tr><tr><td>Read Timing Centering 2D</td><td>Read Dq-Dqs Timing Centering 2D.</td></tr><tr><td>Command Voltage Centering</td><td>Command Voltage Centering.</td></tr><tr><td>Write Voltage Centering 2D</td><td>Write Voltage Centering 2D.</td></tr><tr><td>Read Voltage Centering 2D</td><td>Read Voltage Centering 2D.</td></tr><tr><td>Late Command Training</td><td>Late Command Training.</td></tr><tr><td>Round Trip Latency</td><td>Round Trip Latency Training.</td></tr><tr><td>Turn Around Timing Training</td><td>Turn Around Timing Training.</td></tr><tr><td>Rank Margin Tool</td><td>Rank Margin Tool Training.</td></tr><tr><td>Margin Check Limit</td><td>Checks Margin to Limit to see if next boot memory needs to be retrained.</td></tr><tr><td>Memory Test</td><td>Memory Test Training.</td></tr><tr><td>DIMM SPD Alias Test</td><td>Test to determine if the SPD has been corrupted to cause memory aliasing.</td></tr><tr><td>Receive Enable Centering 1D</td><td>Receive Enable Centering 1D.</td></tr><tr><td>Retrain Margin Check</td><td>Retrain Margin Check.</td></tr><tr><td>Write Drive Strength Up/Dn independently</td><td>Write Drive Strength Up/Dn independently.</td></tr><tr><td>Command Drive Strength and Equalization</td><td>Command Drive Strength and Equalization.</td></tr><tr><td>Command Normalization</td><td>Command Normalization.</td></tr><tr><td>Early DQ Write Drive Strength and Equalization Training</td><td>Early DQ Write Drive Strength and Equalization Training.</td></tr><tr><td>Read Voltage Centering 1D</td><td>Read Voltage Centering 1D.</td></tr><tr><td>Dimm ODT CA Training</td><td>Dimm ODT CA Training.</td></tr><tr><td>Duty Cycle Correction</td><td>Duty Cycle Correction.</td></tr><tr><td>DQ DFE Training</td><td>DQ DFE Training.</td></tr></table>

6.4.1.2 Graphics Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Primary Display</td><td>Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.</td></tr><tr><td>SG Delay After Power Enable</td><td>Delay in milliseconds after power enable.</td></tr><tr><td>SG Delay After Hold Reset</td><td>Delay in milliseconds after hold reset.</td></tr><tr><td>Internal Graphics</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>Select the GTT Size.</td></tr><tr><td>Aperture Size</td><td>Select the Aperture Size. Note: Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM Support.</td></tr><tr><td>DVMT Pre-Allocated</td><td>Select DVMT5.0 Pre-Allocated (Fixed) Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>GOP Config Driver Enable</td><td>Enables or disables GOP Config Driver.</td></tr></table>

6.4.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>PCI Express Configuration settings.</td></tr><tr><td>SATA And RST Configuration</td><td>SATA Device Options Settings.</td></tr><tr><td>USB Configuration</td><td>USB Configuration settings.</td></tr><tr><td>HD Audio Configuration</td><td>HD Audio Configuration Settings.</td></tr></table>

6.4.2.1 PCI Express Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCIE_4X_SLOTX: PCIExpress Root Port Settings</td><td>PCIE_4X_SLOTX: Control the PCI Express Root Port</td></tr></table>

# 6.4.2.2 SATA and RST Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Enables or disables SATA device.</td></tr><tr><td>SATA Mode Selection</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>Serial ATA Port X</td><td>Port X: Enables or disables SATA port.</td></tr></table>

# 6.4.2.3 USB Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>XHCI Compliance Mode</td><td>Option to enable Compliance mode. Default is to disable Compliance mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>USB Port Disable Override</td><td>Selectively enables or disables the corresponding USB port from reporting a device connection to the controller.</td></tr></table>

# 6.4.2.4 HD Audio Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>HD Audio</td><td>Control detection of the HD-audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled.</td></tr></table>

# 6.5 Security

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Set Administrator Password.</td></tr><tr><td>User Password</td><td>Set User Password.</td></tr><tr><td>▶ Secure Boot</td><td>Secure Boot configuration.</td></tr></table>

# 6.5.1 Secure Boot

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Secure Boot</td><td>Secure Boot feature is active if Secure Boot is enabled, Platform Key(PK) is enrolled and the system is in user mode. The mode change requires platform reset.</td></tr><tr><td>Secure Boot mode</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr></table>

When setting up an administrator password, it is recommended to enter it when accessing the BIOS setup program to avoid some BIOS information or settings that are unavailable due to user rights are insufficient (no password is entered as a user).

When setting a user password, you must use the user password to access the BIOS setup program, which means that you need to enter the user password when booting the operating system (using the BIOS boot feature).

# Set/Change the Administrator Password:

1. Select “Security - Administrator Password.”
2. Enter the desired password in the “Create New Password” window and press Enter. You will need to confirm by entering current password before accessing the “Create New Password” window.
3. Re-enter the new password to ensure it is entered correctly.

To delete an administrator password, press the Carriage Return in the “Create New Password” window.

# Set/Change the User Password:

1) Select “Security - User Password.”
2) Enter the password you want to set in the “Create New Password” window and press Enter. You will need to confirm by entering the current password before accessing the “Create New Password” window.
3) Re-enter the new password to ensure it is entered correctly.

To delete a user password, press the carriage return in the “Create New Password” window.

# 6.6 Boot

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Setup Prompt Timeout</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup Num Lock State</td><td>Select the keyboard Num Lock state.</td></tr><tr><td>Full Screen Logo</td><td>Enables or disables Full Screen Logo option.</td></tr><tr><td>Fast Boot</td><td>Enabled or disabled boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot option.</td></tr><tr><td>Boot mode Select</td><td>Select Boot mode LEGACY/UEFI.</td></tr><tr><td>Boot Option #X</td><td>Sets the system boot order.</td></tr></table>

# Set Boot Sequence:

1) Select “Boot” in the menu page.
2) Change “Boot Option #1” to the desired device.
3) If there are more than one similar device, example, more than one hard drive, enter “Hard Disk Drive BBS Priorities” and change the boot order priority between the drives first.

When the Boot page has the Boot Mode option, it is recommended to set it to “dual” so that both Legacy and BIOS boot projects can be booted. UEFI boot items will be filtered when selected for Legacy, and legacy boot items will be filtered when selected as BIOS.

6.7 Save & Exit

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Changes</td><td>Save changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Discard changes done so far to any of the setup options.</td></tr><tr><td>Default Options</td><td>Default Options.</td></tr><tr><td>Restore Defaults</td><td>Restore/Load default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Boot Override.</td></tr><tr><td>UEFI: Built-in EFI shell</td><td>Launch BIOS Built-in UEFI Shell.</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td>Attempts to launch EFI Shell application (Shell.efi) from one of the available filesystem devices.</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

<table><tr><td>Address:</td><td>No. 66, Huaya 1st Road, Guishan DistrictTaoyuan City 333, Taiwan</td></tr><tr><td>Tel:</td><td>+886-3-216-5088</td></tr><tr><td>Fax:</td><td>+886-3-328-5723</td></tr><tr><td>Email:</td><td>service@adlinktech.com</td></tr></table>

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

<table><tr><td>Address:</td><td>300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China</td></tr><tr><td>Tel:</td><td>+86-21-5132-8988</td></tr><tr><td>Fax:</td><td>+86-21-5132-3588</td></tr><tr><td>Email:</td><td>market@adlinktech.com</td></tr></table>

# ADLINK Technology GmbH

<table><tr><td>Address:</td><td>Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany</td></tr><tr><td>Tel:</td><td>+49-621-43214-0</td></tr><tr><td>Fax:</td><td>+49-621 43214-30</td></tr><tr><td>Email:</td><td>emea@adlinktech.com</td></tr></table>

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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