# IMB-C46H

# User’s Manual

ATX Motherboard with 10th Gen Intel® Core™ i9/i7/i5/i3 Processors and Intel® H420E Chipset

![Top-down view of a green printed circuit board with visible CPU socket, RAM slots, and various electronic components (no readable text or symbols)](.imb-c46h-50m-13018-1010-11/c38f331a872391db52094feaf44b4445d6ff911373ea076f98349925f0c32862.jpg)

Manual Rev.: Rev. 1.1

Revision Date: July 28, 2025

Part Number: 50M-13018-1010

# Preface

# Copyright

Copyright 2025 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines and a solid rectangle below (no text or labels)](.imb-c46h-50m-13018-1010-11/85bebb088c71b58828d160bfda0bb08bb1379c712ba8f92252760280a10dc9f3.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin crossed out by two diagonal lines (no text or symbols)](.imb-c46h-50m-13018-1010-11/9041061fbd47fd69a234f9565933d1395704d0990dfa89ce1e5a2ae7b067dfc2.jpg)

![The image displays a black and white graphic. Inside a square border is the universal recycling symbol consisting of three chasing arrows. Below the square, the text 'Li-ion' appears in bold, black, sans-serif font.](.imb-c46h-50m-13018-1010-11/4cd85093a3febd5ac82c78564f4c4d890c2b59b054cf83a27c53333511335d55.jpg)

![RECYCLE\nRBRC\nLi-ion\n1.800.822.8837](.imb-c46h-50m-13018-1010-11/ece42858fb687b56d54269d9bd6b613c471ebcf8c5e8a637d6acf8ed8878abcd.jpg)

![廢電池請回收](.imb-c46h-50m-13018-1010-11/50435d2041edcd012e04c90bb0f8f0c128e509b6ee3588ae9f00c3def3c886cb.jpg)

# California Proposition 65 Warning

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border. Inside the yellow field is a large, black exclamation point centered vertically and horizontally. The background surrounding the triangle is white.](.imb-c46h-50m-13018-1010-11/0bc052e69d0d9b25143757ca5c79aa6f4f5623eed454314ad96d724875be52ee.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2024-10-08</td><td>AL</td></tr><tr><td>1.1</td><td>Connector pinouts updated</td><td>2025-10-08</td><td>AL</td></tr></table>

# Table of Contents

# Preface...

# List of Figures .... ..vi

# List of Tables...... ..vi

# 1 Introduction....

1.1 Packing List ..
1.2 Optional Accessories .

# 2 Specifications ....

2.1 Core System . .3
2.2 I/O Interface .. .3
2.3 Video .4
2.4 Audio .4
2.5 LAN.. .4
2.6 Temperatures . .4
2.7 Humidity... .4
2.8 Certificate (EMC) .. .4
2.9 Form Factor .. .5
2.10 Operating Systems . .5
2.11 Functional Block Diagram 6

# 3 Mechanical Layout ..

3.1 IO Panel Connector Locations .
3.2 Mechanical Dimensions . .11

# 4 Connector Pinouts .. .12

4.1 Rear IO Connectors . .12
4.2 Onboard Headers / Connectors . .13
4.3 Jumper and Switch Settings. .17
4.4 Expansion Slots .. ..20

# 5 Driver Installation .... .23

# 6 BIOS Setup........... .25

6.1 Menu Structure . .25
6.2 Main Menu. ..26
6.3 Advanced.. ..26
6.4 Chipset .. ..35
6.5 Security.. ..37
6.6 Boot . ..38

6.7 Save & Exit .. ..38

Safety Instructions.... .39

Getting Services............... ..40

# List of Figures

Figure 1: Functional Block Diagram.. .6
Figure 2: IO Panel Connector Locations.
Figure 3: Onboard Connectors - Header and Jumper Locations . .8
Figure 4: Mechanical Dimensions. ..11
Figure 5: Mechanical Dimensions - IO Panel. .11

# List of Tables

Table 1: IO Panel Connector Locations.
Table 2: OnboardConnectors – Header and Jumper Definitions . .9

# 1 Introduction

ADLINK IMB-C46H ATX is an industrial motherboard supporting 10th Generation Intel® Core™ i9/i7/i5/i3 desktop processors, an Intel® H420E Chipset, and 3 PCIe expansion slots to provide a cost-competitive embedded computing solution. It includes high-speed data transfer interfaces such as PCIe 3.0, USB 3.0, and SATA 6 Gb/s (SATA III), and dual-channel DDR4 2400/2666/2933 MHz RAM for industrial automation applications. With industrial-grade I/O port design, the IMB-C46H offers a significant competitive advantage for embedded computing applications in terms of device compatibility, durable connectivity, and extreme environment readiness.

# 1.1 Packing List

IMB-C46H ATX motherboard
Rear I/O shield
1pc. SATA cable
• 1pc. COM cable (1port)

# 1.2 Optional Accessories

CPU cooler for 65W CPU, Part Number: 32-20495-0000
CPU cooler for 35W CPU, Part Number: 32-20530-0010
COM Cable(2port), Part Number: 30-25003-3000
• USB2.0 Cable(2port), Part Number: 30-25010-3010
USB2.0 Cable(4port), Part Number: 30-25009-3000
• SATA Cable, Part Number: 30-10057-7000

This page intentionally left blank.

# 2 Specifications

# 2.1 Core System

#  CPU:

• Intel® Core™ i9-10900E, 4.7GHz, 10 Core, 20M Cache, DDR4 2933MHz support, 65W
• Intel® Core™ i9-10900TE, 4.5GHz, 10 Core, 20M Cache, DDR4 2933MHz support, 35W
• Intel® Core™ i7-10700E, 4.5GHz, 8 Core, 16M Cache, DDR4 2933MHz support, 65W
• Intel® Core™ i7-10700TE, 4.4GHz, 8 Core, 16M Cache, DDR4 2933MHz support, 35W
• Intel® Core™ i5-10500E, 4.2GHz, 6 Core, 12M Cache, DDR4 2666MHz support, 65W
• Intel® Core™ i5-10500TE, 3.7GHz, 6 Core, 12M Cache, DDR4 2666MHz support, 35W
• Intel® Core™ i3-10100E, 3.8GHz, 4 Core, 6M Cache, DDR4 2666MHz support, 65W
• Intel® Core™ i3-10100TE, 3.6GHz, 4 Core, 6M Cache, DDR4 2666MHz support, 35W
• Intel® Pentium® Gold G6400, 3.2GHz, 2 Core, 4M Cache, DDR4 2400MHz support, 35W
• Intel® Pentium® Gold G6400, 3.8GHz, 2 Core, 4M Cache, DDR4 2400MHz support, 58W
• Intel® Celeron® Processor G5900TE, 3.0GHz, 2M Cache, DDR4 2666MHz support, 35W
• Intel® Celeron® Processor G5900E, 3.2GHz, 2M Cache, DDR4 2666MHz support, 58W

Chipset: Intel® H420E Express Chipset
 Memory: 2x 288-pin Non-ECC U-DIMM slot, DDR4 2400/2666/2933 MHz, up to 64 GB
. BIOS: AMI® UEFI BIOS, 256 Mb SPI Flash Memory
Hardware Monitor: CPU voltage

+3.3V voltage

+5V voltage

+12V voltage

CPU temperature

System temperature

CPU fan speed

System fan speed

# 2.2 I/O Interface

# Expansion slots:

1x PCIe Gen3 x16
• 1x PCIe x4 slot (PCIe Gen3 x2, co-lay with M.2 M-key 2242/2280)
• 1x PCIe x4 slot (PCIe Gen3 x2, share PCIe x1 with M.2 E key 2230 by BOM change)
4xPCI

. SATA: 3x SATA 6.0 Gb/s connectors

# . USB:

6x USB 3.0 (rear I/O)
• 2x USB 2.0 (pin header)
1x USB 2.0 (Vertical TYEP-A, Internal)

#  COM:

1x RS-232 (COM1, rear I/O)
3x RS-232 (COM2/5/6, by internal header)
• 2x RS-232/RS485 (COM3/4, by internal header)

 PS/2 Combo Port: 1x PS/2 keyboard/mouse

 DIO: 8-bit GPIO

M.2 connectors:

1x M.2 E-Key 2230 (PCIe Gen3 x1, USB 2.0)
1x M.2 M-Key 2242/2280 (PCIe 2x/SATA, default)

# 2.3 Video

Interfaces: Supports two independent displays

• 1x DVI: Support DVI-D, max resolution up to 1920x1200@60Hz
1x HDMI 1.4b (TYPE-A): up to 4096x2160@30Hz
• 1x VGA (DB15/F): max resolution up to 1920x1200@60Hz
• 1x eDP (Header): max resolution up to 4096x2304@60Hz

# 2.4 Audio

Audio Codec: Realtek® ALC897
Interfaces: 1x Mic-in, 1x Line-in, and 1x Line-out connectors (rear)

# 2.5 LAN

 LAN1: Intel® I219-V via RJ45 connector
 LAN2: Intel® I226-V via RJ45 connector

# 2.6 Temperatures

Operating Temperature: $0 ^ { \circ } \mathsf { C }$ to $6 0 ^ { \circ } \mathsf { C }$
Storage Temperature: $\angle 0 ^ { \circ } \mathsf { C }$ to $7 5 ^ { \circ } \mathsf { C }$

# 2.7 Humidity

$6 0 ^ { \circ } \mathsf { C }$ at 95% RH, non-condensing

# 2.8 Certificate (EMC)

CE/FCC Class A

# 2.9 Form Factor

 ATX: 305 mm x 244 mm (W x L)

# 2.10 Operating Systems

Microsoft® Windows® 10, 64-bit

# 2.11 Functional Block Diagram

![Based on the provided flowchart, here are the labeled blocks and their verbatim connections:\n\n**Central Components**\n*   **10th Gen Intel® Processor**\n*   **Intel® PCH H420E**\n    *   Connection: **DMI** (connects the Processor and PCH)\n\n**Processor Connections**\n*   **DVI-D Port** ↔ **DDI** ↔ **10th Gen Intel® Processor**\n*   **HDMI TYPE-A** ↔ **DDI** ↔ **10th Gen Intel® Processor**\n*   **VGA DB9FM Port** ↔ **Converter** ↔ **DDI** ↔ **10th Gen Intel® Processor**\n*   **DIMM0+DIMM1** ↔ **10th Gen Intel® Processor** ↔ **2x DDR4 U-DIMM**\n*   **PEG 16X** ↔ **10th Gen Intel® Processor** ↔ **PCIE x16 Slot**\n*   **eDP** ↔ **10th Gen Intel® Processor** ↔ **eDP Header**\n\n**PCH H420E Connections (Left Side)**\n*   **AUDIO CODEC** ↔ **L-OUT/IN/MIC Phone Jack**\n*   **AUDIO CODEC** ↔ **L-OUT/IN/MIC Header**\n*   **AUDIO CODEC** ↔ **HDA** ↔ **Intel® PCH H420E**\n*   **I219-V** ↔ **RJ45 Port**\n*   **I219-V** ↔ **GbE** ↔ **Intel® PCH H420E**\n*   **I226-V** ↔ **RJ45 Port**\n*   **I226-V** ↔ **PCIE** ↔ **Intel® PCH H420E**\n*   **3x SATA Port** ↔ **SATAx3** ↔ **Intel® PCH H420E**\n*   **M.2 Key M 2280** ↔ **SATA0** ↔ **Intel® PCH H420E**\n*   **PCIE x4 Port1** ↔ **PCIE 2X** ↔ **Intel® PCH H420E**\n*   **PCIE x4 Port** ↔ **PCIE 2X** ↔ **Intel® PCH H420E**\n*   **M.2 Key E 2230** ↔ **PCIE 1X** (branch from the PCIE 2X line)\n*   **M.2 Key E 2230** ↔ **USB2.0** ↔ **Intel® PCH H420E**\n*   **Dual USB3.0 TYPE-A** ↔ **USB3.0x2 + USB2.0x2** ↔ **Intel® PCH H420E**\n*   **Dual USB3.0 TYPE-A** ↔ **USB3.0x2 + USB2.0x2** ↔ **Intel® PCH H420E**\n*   **4x PCI Port** ↔ **PCI Bridge** ↔ **PCIE** ↔ **Intel® PCH H420E**\n*   **SMBus Header** ↔ **SMBus** ↔ **Intel® PCH H420E**\n\n**PCH H420E Connections (Right Side)**\n*   **USB2.0 Dual-Header** ↔ **USB2.0x2** ↔ **Intel® PCH H420E**\n*   **USB2.0 Vertical-TYPE-A** ↔ **USB2.0** ↔ **Intel® PCH H420E**\n*   **Dual USB3.0 TYPE-A(+PS2)** ↔ **2x USB3.0 + 2x USB2.0** ↔ **Intel® PCH H420E** (Connection label: **KB+MS**)\n\n**Super I/O Connections**\n*   **Super I/O** ↔ **LPC** ↔ **Intel® PCH H420E**\n*   **Super I/O** ↔ **RS232** ↔ **COM1 DB9M**\n*   **Super I/O** ↔ **RS232** ↔ **COM2 BOX Header**\n*   **Super I/O** ↔ **RS232/485** ↔ **COM3 BOX Header**\n*   **Super I/O** ↔ **RS232/485** ↔ **COM4 BOX Header**\n*   **Super I/O** ↔ **2x RS232** ↔ **COM5/6 BOX Header**\n*   **Super I/O** ↔ **FAN1~3** ↔ **3x FAN Wafer**\n*   **Super I/O** ↔ **GPIOx8** ↔ **GPIO Header**\n*   **Super I/O** ↔ **CASE OPEN Header**\n*   **Super I/O** ↔ **AT/ATX Jumper**\n*   **Super I/O** ↔ **LPC** ↔ **TPM2.0 (Option)**\n*   **Super I/O** ↔ **LPC** ↔ **Debug Header**\n*   **Super I/O** ↔ **PWR-ON,RESET,HDD LED** ↔ **F-PANEL**](.imb-c46h-50m-13018-1010-11/dfbdfc7851071d27099e192dd6c92c3ce9c8727c9c998f3067bf1feac00b53fa.jpg)

Figure 1: Functional Block Diagram

• PCIE4X\_2 and M2\_E\_WLAN1 share PCIE signal (support M2\_E\_WLAN1 by default)

# 3 Mechanical Layout

# 3.1 IO Panel Connector Locations

![A\nB\nC\nD-2\nD-1\nI-1\nE-2\nE-1\nF\nG\nH-4\nH-3\nH-2\nH-1\nI-3\nI-2](.imb-c46h-50m-13018-1010-11/360eaa43fd1ae207b4abc3fdfed830ccc40cb4ad1d7abedc284727fc7a5e175f.jpg)

Figure 2: IO Panel Connector Locations

Table 1: IO Panel Connector Locations

<table><tr><td>Item</td><td>Location</td><td>Description</td></tr><tr><td>A</td><td>KBMS_USB1 (PS/2)</td><td>PS/2 Connector (Keyboard &amp; Mouse)</td></tr><tr><td>B</td><td>DVI_VGA1 (DVI-D)</td><td>DVI-I 24+4P/F Connector (Support DVI-D)</td></tr><tr><td>C</td><td>COM1</td><td>COM1 DB9/M Connector</td></tr><tr><td>D-1</td><td>RJ45_USB1 (LAN1)</td><td>GBE LAN RJ45 Connector1</td></tr><tr><td>D-2</td><td>RJ45_USB2 (LAN2)</td><td>GBE LAN RJ45 Connector2</td></tr><tr><td>E-1</td><td>KBMS_USB1 (USB1)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>E-2</td><td>KBMS_USB1 (USB2)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>F</td><td>DVI_VGA1 (VGA)</td><td>VGA DB15/F Connector</td></tr><tr><td>G</td><td>HDMI1</td><td>HDMI TYPE-A Connector</td></tr><tr><td>H-1</td><td>RJ45_USB1 (USB1)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-2</td><td>RJ45_USB1 (USB2)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-3</td><td>RJ45_USB2 (USB3)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>H-4</td><td>RJ45_USB2 (USB4)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>I-1</td><td>AUDIO1 (BLUE)</td><td>Line-In 3.5mm Jack</td></tr><tr><td>I-2</td><td>AUDIO1 (GREEN)</td><td>Line-Out 3.5mm Jack</td></tr><tr><td>I-3</td><td>AUDIO1 (PINK)</td><td>MIC-In 3.5mm Jack</td></tr></table>

![28 27 26\n25 24-1 24-2\n23\n22\n29\n30\n21\n20\n19\n18-2\n18-3\n31\n32\nADLINK\nIMB-C46H\n17\n16\n15\n14\n13\n12\n11\n10\n9\n8-1\n8-2\n7-2\n7-1\n35-1\n34\n35-2\n37-1\n36\n37-2\n37-3\n37-4\n1 2 3 4 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 6-5](.imb-c46h-50m-13018-1010-11/821108ed173f81fd3811e01bd537be6c04890b96ceb0fd023a4ac8fbf49ba66e.jpg)

Figure 3: Onboard Connectors - Header and Jumper Locations

Table 2: OnboardConnectors – Header and Jumper Definitions

<table><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>1</td><td>SYS_FAN2</td><td>System FAN2 Headers</td></tr><tr><td>2</td><td>J_GPIO1</td><td>GPIO Header</td></tr><tr><td>3</td><td>F_USB1</td><td>Front USB2.0 Header</td></tr><tr><td>4</td><td>F_PANEL1</td><td>Front Panel Header</td></tr><tr><td>5-1</td><td>J_COM2</td><td>COM2 Headers</td></tr><tr><td>5-2</td><td>J_COM3</td><td>COM3 Headers</td></tr><tr><td>5-3</td><td>J_COM4</td><td>COM4 Headers</td></tr><tr><td>5-4</td><td>J_COM5</td><td>COM5 Headers</td></tr><tr><td>5-5</td><td>J_COM6</td><td>COM6 Headers</td></tr><tr><td>6-1</td><td>JC_COM2</td><td>COM2 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>6-2</td><td>JC_COM3</td><td>COM3 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>6-3</td><td>JC_COM4</td><td>COM4 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>6-4</td><td>JC_COM5</td><td>COM5 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>6-5</td><td>JC_COM6</td><td>COM6 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>7-1</td><td>RS485_LOAD1</td><td>COM3 RS485 Signal 120Ω Resistive Termination Select Jumper</td></tr><tr><td>7-2</td><td>RS485_LOAD2</td><td>COM4 RS485 Signal 120Ω Resistive Termination Select Jumper</td></tr><tr><td>8-1</td><td>JM_COM3</td><td>COM3 RS232/RS485 Select Jumpers</td></tr><tr><td>8-2</td><td>JM_COM4</td><td>COM4 RS232/RS485 Select Jumpers</td></tr><tr><td>9</td><td>M2_M_PCIESSD1</td><td>M.2 Key-M Slot (PCIE 2x/SATA, Default SATA, Support SATA SSD, 2242/2280)</td></tr><tr><td>10</td><td>JP_AT/ATX1</td><td>AT or ATX Select Jumper</td></tr><tr><td>11</td><td>WDT_EN1</td><td>Watch Dog Reset Enable/Disable Select Jumper</td></tr><tr><td>12</td><td>J_ME1</td><td>ME Flash Header</td></tr><tr><td>13</td><td>CLR_CMOS1</td><td>CMOS Clear Select Jumper</td></tr><tr><td>14</td><td>J_DBG1</td><td>LPC Debug Header</td></tr><tr><td>15</td><td>J_PWR_LED1</td><td>Power LED Header</td></tr><tr><td>16</td><td>J_SMBUS1</td><td>SMBus Wafer</td></tr><tr><td>17</td><td>J_COPEN1</td><td>Case Open Header</td></tr><tr><td>18-1</td><td>SATA2</td><td>SATA3.0 Connector2</td></tr><tr><td>18-2</td><td>SATA3</td><td>SATA3.0 Connector3</td></tr><tr><td>18-3</td><td>SATA4</td><td>SATA3.0 Connector4</td></tr><tr><td>19</td><td>SYS_FAN1</td><td>System FAN1 Headers</td></tr><tr><td>20</td><td>R_USB1</td><td>USB2.0 TYPE-A Up-right Connector</td></tr><tr><td>21</td><td>J_PWR1</td><td>Power Expand Wafer</td></tr><tr><td>22</td><td>PSON1</td><td>Power On Wafer</td></tr><tr><td>23</td><td>ATX1</td><td>ATX 24P Power Input Connector</td></tr><tr><td>24-1</td><td>DIMM1</td><td>DDR4 CHA DIMM Slot</td></tr><tr><td>24-2</td><td>DIMM2</td><td>DDR4 CHB DIMM Slot</td></tr><tr><td>25</td><td>CPU_FAN1</td><td>CPU Fan Wafer</td></tr><tr><td>26</td><td>ATX2</td><td>ATX 8P CPU Power Input Connector</td></tr><tr><td>27</td><td>EDP1</td><td>EDP Signal Header</td></tr><tr><td>28</td><td>JC_EDP1</td><td>eDP VDD Select Jumper</td></tr><tr><td>29</td><td>EDP_P1</td><td>eDP Backlight Control Header</td></tr><tr><td>30</td><td>JC_COM1</td><td>COM1 DCD/5V+ RI/12V Select Jumper</td></tr><tr><td>31</td><td>M2_E_WLAN1</td><td>M.2 Key-E Slot (PCIE+USB2.0, Support WIFI+ BlueTooth, 2230)</td></tr><tr><td>32</td><td>F_AUDIO1</td><td>Front Audio Header</td></tr><tr><td>33</td><td>PCIEX16_1</td><td>PCI-E 16x Slot</td></tr><tr><td>34</td><td>F_SPDIF1</td><td>SPDIF Out Header</td></tr><tr><td>35-1</td><td>PCIE4X_2</td><td>PCIE4X Slot1</td></tr><tr><td>35-2</td><td>PCIE4X_3</td><td>PCIE4X Slot2</td></tr><tr><td>36</td><td>JP_PCICLK1</td><td>PCI CLK 66MHz Disable/ Enable Select Jumper</td></tr><tr><td>37-1</td><td>PCI1</td><td>PCI Slot1</td></tr><tr><td>37-2</td><td>PCI2</td><td>PCI Slot2</td></tr><tr><td>37-3</td><td>PCI3</td><td>PCI Slot3</td></tr><tr><td>37-4</td><td>PCI4</td><td>PCI Slot4</td></tr></table>

# 3.2 Mechanical Dimensions

Top View
![243.8\n237.5\n220.0\n105.1\nADLINK\nMB-C4H\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 9 5 9\n5 10.2\n163.8\n209.6\n208.3\n304.8\n0.0\n0.0\n8.4](.imb-c46h-50m-13018-1010-11/a61a71fd372acff383760247c4f734eb071f3613f4f6c26d9310d142bdba8a24.jpg)

Dimensions: mm

Figure 4: Mechanical Dimensions
Side View
![Diagram of various computer ports and connectors without any text or labels](.imb-c46h-50m-13018-1010-11/0f5193b9bed6f9b3412de45448bba97c2ad09331b318e512fce2e6b282871a33.jpg)

Dimensions: mm

Figure 5: Mechanical Dimensions - IO Panel

# 4 Connector Pinouts

See 3.1 Connector Locations on page 7 for connector locations.

# 4.1 Rear IO Connectors

# 4.1.1 HDMI

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDMI1_CON_DP2</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>HDMI1_CON_DN2</td><td>4</td><td>HDMI1_CON_DP1</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>HDMI1_CON_DN1</td></tr><tr><td>7</td><td>HDMI1_CON_DP0</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>HDMI1_CON_DN0</td><td>10</td><td>HDMI1_CON_CKP</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>HDMI1_CON_CKN</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>HDMI1_DDC_CLK</td><td>16</td><td>HDMI1_DDC_DATA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5V_HDMI</td></tr><tr><td>19</td><td>HDMI1_CON_HPD</td><td></td><td></td></tr></table>

![The image is a black and white line drawing of a connector, specifically resembling a D-subminiature connector housing. It shows the outer shell outline with two parallel rows of rectangular pins or contacts inside. Numerical labels are placed near the contacts to identify them.\n\n- On the top row, the numbers **19 17** are visible on the left side, and **3 1** are visible on the right side.\n- On the bottom row, the number **18** is on the left side, and **4 2** is on the right side.](.imb-c46h-50m-13018-1010-11/fcfdedbc704d5b25e98b6acbfb4cea12fc7bbbf5908bc80279ed33ed13cb5d44.jpg)

# 4.1.2 VGA Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VGA_CON_RED</td><td>2</td><td>VGA_CON_GREEN</td></tr><tr><td>3</td><td>VGA_CON_BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>+5V_HDMI</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>VGA_DDCDAT</td></tr><tr><td>13</td><td>VGA_CON_HS</td><td>14</td><td>VGA_CON_VS</td></tr><tr><td>15</td><td>VGA_DDCCLK</td><td></td><td></td></tr></table>

![This is a technical line drawing of a DB9 connector interface. In the center is a rectangular housing with rounded corners containing a 3x3 grid of nine circular holes. Flanking this central housing on the far left and right are two hexagonal shapes with inner circles, representing mounting screws. Above the housing, the number '5' is centered over the left side and the number '1' is centered over the right side.](.imb-c46h-50m-13018-1010-11/14d471ddda2216a12c9661990bb6212d7e1e393e9371c15ff64c14a4f44a5407.jpg)

# 4.1.3 COM 1 (COM1 DB9/M Connector)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>COM1_PIN1 [1]</td><td>6</td><td>COM1_DSR</td></tr><tr><td>2</td><td>COM1_RXD</td><td>7</td><td>COM1_RTS</td></tr><tr><td>3</td><td>COM1_TXD</td><td>8</td><td>COM1_CTS</td></tr><tr><td>4</td><td>COM1_DTR</td><td>9</td><td>COM1_PIN9 [1]</td></tr><tr><td>5</td><td>GND</td><td></td><td></td></tr></table>

![The image displays a schematic outline of a rectangular connector with rounded corners. Inside are two rows of small circles representing pins.\n\nThe top row is labeled with numbers **1 2 3 4 5** from left to right.\nThe bottom row is labeled with numbers **6 7 8 9** from left to right, positioned directly beneath the first four numbers of the top row.](.imb-c46h-50m-13018-1010-11/3c25bb28a5ff91e1e3ba02dc9dd2c1b9f62caa49947865beec302598e66542cc.jpg)

Note: PIN1 of COM1 can be DCD (default) /5V and Pin9 of COM1 can be RI(Default) / 12V, selectable by “COM1 DCD/5V+RI/12V Select Jumper”. (JC\_COM1)

# 4.1.4 Ethernet Connectors (LAN1, LAN2)

RJ45\_USB1-2 (LAN) \* (GBE LAN RJ45 Connector1-2)

<table><tr><td>Pin</td><td colspan="2">Signal</td><td>Pin</td><td colspan="2">Signal</td></tr><tr><td>1</td><td colspan="2">MDI_0+</td><td>5</td><td colspan="2">MDI2_2+</td></tr><tr><td>2</td><td colspan="2">MDI_0-</td><td>6</td><td colspan="2">MDI2_2-</td></tr><tr><td>3</td><td colspan="2">MDI_1+</td><td>7</td><td colspan="2">MDI3_2+</td></tr><tr><td>4</td><td colspan="2">MDI_1-</td><td>8</td><td colspan="2">MDI3_3-</td></tr><tr><td rowspan="3">LED1</td><td rowspan="3">Speed LED</td><td>1000M: Turn Orange</td><td rowspan="3">LED2</td><td rowspan="3">Active LED</td><td>ACT: Twinkling Yellow</td></tr><tr><td>100M: Turn Green</td><td>Only LINK: Lights On</td></tr><tr><td>10M: Lights Off</td><td>Stop: Lights Off</td></tr></table>

![The image displays a schematic diagram of an Ethernet-style connector, likely an RJ45 jack. At the top, the text 'LED1' appears on the left and 'LED2' on the right. Below these labels is a line drawing of the connector housing. At the bottom, the numbers '8' and '1' are labeled near the bottom pins of the connector.](.imb-c46h-50m-13018-1010-11/d5fe6254afe9ddff42f27d46b987830ec5a3a9c0ec4ea0b5d415d6f5d29201b0.jpg)

# 4.2 Onboard Headers / Connectors

# 4.2.1 FAN Header (CPU\_FAN1, SYS\_FAN1, SYS\_FAN2)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>+12 V</td><td>FAN Power</td></tr><tr><td>3</td><td>Tach</td><td>FAN Tachometer</td></tr><tr><td>4</td><td>PWM</td><td>FAN PWM</td></tr></table>

![The image displays the number '1' to the left of a vertical rectangular outline. Inside the rectangle, four circles are stacked vertically. The top and bottom circles are black rings with white centers, while the middle two circles are solid black. A small square is positioned at the bottom right corner of the rectangle, adjacent to the bottom circle.](.imb-c46h-50m-13018-1010-11/39f16b2b9515666b27059ab79b54b95a6a81c7447bcc81599f5223924d2d075c.jpg)

Fan Header 4\*1 Pin 2.54mm

# 4.2.2 Front Panel Header (F\_PANEL1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDD 3.3V LED+</td><td>2</td><td>POWER 3.3V LED+</td></tr><tr><td>3</td><td>HDD 3.3V LED-</td><td>4</td><td>POWER 3.3V LED-</td></tr><tr><td>5</td><td>RESET-</td><td>6</td><td>POWER+</td></tr><tr><td>7</td><td>RESET+</td><td>8</td><td>POWER-</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr></table>

![The image displays the numbers 1 and 2 at the top left and right, flanking a vertical stack of five rectangular tiles with rounded corners. The top four tiles each consist of two sections, with each section containing two small squares arranged diagonally. The bottom tile consists of a left section with a single central small square and an empty right section.](.imb-c46h-50m-13018-1010-11/12e9c44da295a47c2f9f0e240c4e06cfe52ab2d396832b9f07b4a7c48407d53e.jpg)

Fan Header 5\*2 Pin 2.54mm

# 4.2.3 COM Header (J\_COM 2-6)

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">J_COM2</td><td>1</td><td>COM2_PIN1</td><td>2</td><td>COM2_DSR#</td></tr><tr><td>3</td><td>COM2_RXD</td><td>4</td><td>COM2_RTS#</td></tr><tr><td>5</td><td>COM2_TXD</td><td>6</td><td>COM2_CTS#</td></tr><tr><td>7</td><td>COM2_DTR#</td><td>8</td><td>COM2_PIN8</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">J_COM3</td><td>1</td><td>COM3_PIN1</td><td>2</td><td>COM3_DSR#</td></tr><tr><td>3</td><td>COM3_PIN3</td><td>4</td><td>COM3_RTS#</td></tr><tr><td>5</td><td>COM3_TXD</td><td>6</td><td>COM3_CTS#</td></tr><tr><td>7</td><td>COM3_DTR#</td><td>8</td><td>COM3_PIN8</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">J_COM4</td><td>1</td><td>COM4_PIN1</td><td>2</td><td>COM4_DSR#</td></tr><tr><td>3</td><td>COM4_PIN3</td><td>4</td><td>COM4_RTS#</td></tr><tr><td>5</td><td>COM4_TXD</td><td>6</td><td>COM4_CTS#</td></tr><tr><td>7</td><td>COM4_DTR#</td><td>8</td><td>COM4_PIN8</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">J_COM5</td><td>1</td><td>COM5_PIN1</td><td>2</td><td>COM5_DSR#</td></tr><tr><td>3</td><td>COM5_RXD</td><td>4</td><td>COM5_RTS#</td></tr><tr><td>5</td><td>COM5_TXD</td><td>6</td><td>COM5_CTS#</td></tr><tr><td>7</td><td>COM5_DTR#</td><td>8</td><td>COM5_PIN8</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td rowspan="5">J_COM6</td><td>1</td><td>COM6_PIN1</td><td>2</td><td>COM6_DSR#</td></tr><tr><td>3</td><td>COM6_RXD</td><td>4</td><td>COM6_RTS#</td></tr><tr><td>5</td><td>COM6_TXD</td><td>6</td><td>COM6_CTS#</td></tr><tr><td>7</td><td>COM6_DTR#</td><td>8</td><td>COM6_PIN8</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

![1\n2](.imb-c46h-50m-13018-1010-11/47ccf2a8bb068b605811348b2af2aac7d998e420e4392e22fdcb12e14b0e5147.jpg)

Pin Headers 5\*2 Pin 2.54mm
Note:
[1]: COM3 can be RS232 / RS485(default) selecting by “COM3 RS232/RS485 Select Jumper”. (JM\_COM3).
[2]: COM4 can be RS232 / RS485(default) selecting by “COM4 RS232/RS485 Select Jumper”. (JM\_COM4).

# 4.2.4 SATA Connector (SATA 2-4)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>5</td><td>RXN</td><td>Receive diff data – negative</td></tr><tr><td>2</td><td>TXP</td><td>Transmit diff data – positive</td><td>6</td><td>RXP</td><td>Receive diff data – positive</td></tr><tr><td>3</td><td>TXN</td><td>Transmit diff data – negative</td><td>7</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>GND</td><td>Ground</td><td></td><td></td><td></td></tr></table>

![The image displays a technical line drawing of a connector assembly. An outer rectangular housing is labeled with the number **1** on the right side. Inserted within this housing is a narrower inner component labeled with the number **7**. This inner component features a vertical strip of alternating black and white squares running down its right-hand side. The entire illustration is rendered in black and white.](.imb-c46h-50m-13018-1010-11/34191648dd9033cc49e80bdaea366fdcd1e30919ffbb606fcaf81f3da8f55593.jpg)

# 4.2.5 USB Connectors

USB 2.0 Header (F\_USB1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC5</td><td>2</td><td>VCC5</td></tr><tr><td>3</td><td>USB2.0_1-</td><td>4</td><td>USB2.0_2-</td></tr><tr><td>5</td><td>USB2.0_1+</td><td>6</td><td>USB2.0_2+</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td></td><td></td><td>10</td><td>N/C</td></tr></table>

![The image displays the numbers '1' and '2' at the top. Below them is a vertical column of five rounded rectangular cards. From top to bottom, the cards contain small square pips arranged as follows: two pips side-by-side, four pips in a square (2x2), three pips in a triangle (two on top, one below), three pips in a triangle (two on top, one below), and two pips side-by-side.](.imb-c46h-50m-13018-1010-11/40c5e7eb231ebe9af82fc0a8a8cc9d1d11bce832a890c1333c1a393ab6e427f5.jpg)

Pin Header 5\*2 Pin 2.54mm

# 4.2.6 Front Panel Audio Header (F\_AUDIO1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>MIC_IN_L</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>MIC_IN_R</td><td>4</td><td>VCC3.3</td></tr><tr><td>5</td><td>LINE_OUT_R</td><td>6</td><td>MIC_RET</td></tr><tr><td>7</td><td>GND</td><td></td><td></td></tr><tr><td>9</td><td>LINE_OUT_L</td><td>10</td><td>LINE_OUT_RET</td></tr></table>

![The image displays the numbers '1' and '2' at the top left and top right, respectively. Below these numbers is a vertical column of five rounded rectangular outlines. Inside the rectangles are small squares. The top three rectangles and the bottom rectangle each contain two small squares. The fourth rectangle from the top (second from the bottom) contains only one small square on the left side.](.imb-c46h-50m-13018-1010-11/f1045ef35a4792d4817d9b38a090952858c0c3b63e8a2680c3fb965e5e8e663a.jpg)

Pin Header 5\*2 Pin 2.54

# 4.2.7 ATX1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3 V</td><td>13</td><td>+3.3 V</td></tr><tr><td>2</td><td>+3.3 V</td><td>14</td><td>-12 V</td></tr><tr><td>3</td><td>Ground</td><td>15</td><td>Ground</td></tr><tr><td>4</td><td>+5 V</td><td>16</td><td>PS-ON# (power supply remote on/off)</td></tr><tr><td>5</td><td>Ground</td><td>17</td><td>Ground</td></tr><tr><td>6</td><td>+5 V</td><td>18</td><td>Ground</td></tr><tr><td>7</td><td>Ground</td><td>19</td><td>Ground</td></tr><tr><td>8</td><td>PWRGD (Power Good)</td><td>20</td><td>No connect</td></tr><tr><td>9</td><td>+5 V (Standby)</td><td>21</td><td>+5 V</td></tr><tr><td>10</td><td>+12 V</td><td>22</td><td>+5 V</td></tr><tr><td>11</td><td>+12 V</td><td>23</td><td>+5 V</td></tr><tr><td>12</td><td>3.3V</td><td>24</td><td>Ground</td></tr></table>

![1\n2\n24](.imb-c46h-50m-13018-1010-11/dd3007fc194e6f3c968e3992a007cf2e8ee5f034c524a85f2b438aaebc7dd057.jpg)

# 4.2.8 ATX2

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>Ground</td><td>5</td><td>+12V</td></tr><tr><td>2</td><td>Ground</td><td>6</td><td>+12V</td></tr><tr><td>3</td><td>Ground</td><td>7</td><td>+12V</td></tr><tr><td>4</td><td>Ground</td><td>8</td><td>+12V</td></tr></table>

![The image displays a schematic diagram of a rectangular component, likely a DIP switch or connector, featuring 8 circular terminals arranged in two columns and four rows. The bottom-left terminal is enclosed within a small square outline. To the left of the rectangle, the number '2' is aligned with the third row, and the number '1' is aligned with the bottom row. To the right of the rectangle, the number '5' is aligned with the bottom row.](.imb-c46h-50m-13018-1010-11/0bd96a2126d8f62ad9f93762ff47df7c323d1650adfe29d859a19a636b658990.jpg)

# 4.2.9 GPIO Header (J\_GPIO1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>SIO_GPI70(0xA06 Bit0, H [1])</td><td>2</td><td>SIO_GPI71(0xA06 Bit1, H [1])</td></tr><tr><td>3</td><td>SIO_GPI72(0xA06 Bit2, H [1])</td><td>4</td><td>SIO_GPI73(0xA06 Bit3, H [1])</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>SIO_GPO74(0xA06 Bit4, H [1])</td></tr><tr><td>7</td><td>SIO_GPO75(0xA06 Bit5, H [1])</td><td>8</td><td>SIO_GPO76(0xA06 Bit6, H [1])</td></tr><tr><td>9</td><td>SIO_GPO77(0xA06 Bit7, H [1])</td><td>10</td><td>VCC5</td></tr><tr><td></td><td></td><td>12</td><td>N/C</td></tr></table>

Pin Header 6\*2 Pin 2.00mm
Note: “H” or “L” means the default voltage is on high or low level. (5V GPIO).

# 4.2.10 LPC Debug Header (J\_LPC1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>LFRAME_N</td><td>6</td><td>GND</td></tr><tr><td>2</td><td>LPC_DATA3</td><td>7</td><td>N/C</td></tr><tr><td>3</td><td>LPC_DATA 2</td><td>8</td><td>LPC_CLK</td></tr><tr><td>4</td><td>LPC_DATA 1</td><td>9</td><td>VCC3.3</td></tr><tr><td>5</td><td>LPC_DATA 0</td><td></td><td></td></tr></table>

Pin Header 9\*1 Pin 2.00mm

# 4.2.11 SPDIF Header (F\_SPDIF1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+ 5V</td><td>3</td><td>SPDIF_OUT</td></tr><tr><td></td><td></td><td>4</td><td>GND</td></tr></table>

Pin Header 4\*1 Pin 2.54mm

![1 2](.imb-c46h-50m-13018-1010-11/13d464500e96925fe01b7b04348e9eb66d0d003efe765b1a0f25cca84cca24c2.jpg)

![The image displays the number '1' in the upper left corner. To its right is a vertical column of six identical icons. Each icon consists of a vertical rectangle with rounded corners containing two small squares stacked vertically.](.imb-c46h-50m-13018-1010-11/42d101d7a26ad0fa364ec9e9607a1ec2ff7e79c6f721e9e7576bb962c8188e9c.jpg)

![The image displays the number '1' on the left side. To the right of the number is a vertical column of four rounded rectangular shapes, each containing a small square icon in its center.](.imb-c46h-50m-13018-1010-11/c4c4710cfa91a4e13ef0f3d8a563972df9a45b4c0d99ec8138b9ed704eee8472.jpg)

# 4.2.12 SMBUS Header (J\_SMBUS1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>3</td><td>SMB_CLK</td></tr><tr><td>2</td><td>SMB_DATA</td><td>4</td><td>VCC5 [1]</td></tr></table>

![The image displays a vertical rectangular list box containing four small, empty squares stacked vertically. To the right of the top square is a small black triangle pointing upwards, followed immediately by the number **1**.](.imb-c46h-50m-13018-1010-11/e541cece2c5239620c136a94a42ccd77b07a974f3f0ae63e64235f3d8473311b.jpg)
SMB Header 4\*1 Pin 1.25mm
Note: The power on this Pin is 5V by default, 3.3V is available if specified. (resistor selectable)

# 4.3 Jumper and Switch Settings

# 4.3.1 Clear CMOS Jumper (CLR\_CMOS1)

![The image displays a small interface element featuring the text '1_2' at the top. Below this is a row of three square boxes: the first two are dark grey with white circles inside, and the third is white with a thin black border and a white circle inside. Beneath the boxes, the word 'Default' is written in black text.](.imb-c46h-50m-13018-1010-11/708a3899c619bfc10a0cfaab68721df6d060c33ffad082edf06ec5be2a57c511.jpg)

![The image displays a technical diagram snippet. At the top, the text '2_3' is visible. Below that is a graphic showing a square outline with a circle inside, followed by two adjacent grey squares each containing a white circle. At the bottom, the text 'Clear CMOS' is written.](.imb-c46h-50m-13018-1010-11/27352eaded67fb0705ac20ef41dd26bfde0ea9fd0d1c9155159575567271ab7e.jpg)

1-2 : Normal
2-3 : Clear CMOS

# 4.3.2 COM1 DCD/5V+ RI/12V Select Jumper (JC\_COM1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>COM1_PIN1: DCDCOM1_PIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>COM1_PIN1: + 5VCOM1_PIN8: RI</td></tr></table>

Jumper 3\*2 Pin 2.54mm
Note: Jumper 1-3/3-5 select the PIN1 signal. Jumper 2-4/4-6 select the PIN8 signal.

# 4.3.3 COM2-6 DCD/5V+ RI/12V Select Jumper (JC\_COM2-6)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>3-5, 2-4</td><td>PIN1: DCDPIN8: + 12V</td></tr><tr><td>1-3, 4-6(Default)</td><td>PIN1: + 5VPIN8: RI</td></tr></table>

Jumper 3\*2 Pin 2.54mm
Note: Jumper 1-3/3-5 select the PIN1 signal. Jumper 2-4/4-6 select the PIN8 signal.

# 4.3.4 COM3 /4 RS232/RS485 Select Jumpers (JM\_COM3-4)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4(Default)</td><td>RS485(PIN1: RS485-PIN3: RS485+)</td></tr><tr><td>3-5, 4-6</td><td>RS232(PIN1: DCDPIN3: RXD)</td></tr></table>

![1\n2](.imb-c46h-50m-13018-1010-11/3414fa1aee78faa7fe179a421b934951e7d0d93bc19a69d3db357794dcfabc4f.jpg)

# 4.3.5 ME Flash Jumper (J\_ME1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Open (Default)</td><td>ME Protect Enable</td></tr><tr><td>1-2: Connected</td><td>ME Protect Disable</td></tr></table>

Header 2\*1 Pin 2.54mm

![The image displays the number **18** in black on a white background. The digit **1** is a thin vertical line with a small horizontal serif at the top. The digit **8** is stylized, composed of two stacked, rounded rectangular outlines, each containing a smaller, similar inner shape.](.imb-c46h-50m-13018-1010-11/154fa4268a31fc961e857806d1f45af916636090f5374b88bd1fef011568f353.jpg)

# 4.3.6 COM3-4 RS485 Signal 120Ω Resistive Termination Select Jumper (RS485\_LOAD1-2)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>Disable</td></tr><tr><td>2-3</td><td>Enable</td></tr></table>

Header 3\*1 Pin 2.54mm

![The image features a vertical arrangement of items. On the far left is the number '1'. To its right is a red rectangular border enclosing two stacked boxes; the top box contains the text 'R1' and the box below it contains 'R2'. Directly beneath the red outline is a third box containing the text 'R3'.](.imb-c46h-50m-13018-1010-11/6137636a6959bf08e422d5fe7a6738c1a2c856e1137a37e213ac5851d13777d6.jpg)

# 4.3.7 AT or ATX Select Jumper (JP\_AT/ATX1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>ATX Mode</td></tr><tr><td>2-3</td><td>AT Mode</td></tr></table>

Header 3\*2 Pin 2.54mm

![The image displays the number '1' on the left side. To its right is a vertical column of three white rectangular boxes, each outlined in black. Inside each box is a smaller square containing a symbol resembling parentheses or double vertical lines. A thick red outline highlights the top two boxes in the column.](.imb-c46h-50m-13018-1010-11/72417232a0fccbf7340bd08682ce49b96596c21379451fca3ac296412cd44412.jpg)

# 4.3.8 Watchdog Reset Enable/Disable Select Jumper (WDT\_EN1)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1-2 (Default)</td><td>Disable</td></tr><tr><td>2-3</td><td>Enable</td></tr></table>

Header 3\*1 Pin 2.54mm

![The image displays a diagram featuring a large number '1' on the left. To the right is a vertical stack of three rounded rectangular sections. Each section contains a smaller rectangle with the text 'RI' centered inside it. A thick orange outline highlights the top two sections of the stack, while the bottom section remains unhighlighted.](.imb-c46h-50m-13018-1010-11/f83c1b0cff5128f8f824e0f01ea726f868e97bca8c66162ffd8f07422865204b.jpg)

# 4.3.9 Power LED Header (J\_PWR\_LED1)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC3.3</td></tr><tr><td>2</td><td>PWR_LED_N [1]</td></tr><tr><td>3</td><td>GPIO_R</td></tr><tr><td>4</td><td>GND</td></tr></table>

Header 4\*1 Pin 2.54 mm
Note: PWR\_LED is controlled by SIO\_GPIOSB.

![The image displays a large number '1' on the left side. To its right is a vertical column of four rounded rectangular shapes, each containing a small square icon in its center.](.imb-c46h-50m-13018-1010-11/a3e1bf143ba02193a50c78f5dadc682dd045846d1ddd0710a788438d57ce7274.jpg)

# 4.3.10 Power Expand Wafer (J\_PWR1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC5A</td><td>5</td><td>VCC5S</td></tr><tr><td>2</td><td>GND</td><td>6</td><td>VCC3.3S</td></tr><tr><td>3</td><td>GND</td><td>7</td><td>VCC12_N</td></tr><tr><td>4</td><td>VCC5N_S</td><td>8</td><td>VCC12S</td></tr></table>

Wafer 8\*1 Pin 2.00mm

![The image displays a technical line drawing of a rectangular component, likely an integrated circuit or connector, featuring a vertical column of small squares. To the right of the drawing is the large number **1**.](.imb-c46h-50m-13018-1010-11/8634a0d6171c74f13913a5de4eb02ff2dc093551ed674492ed7ac732ac4574b1.jpg)

# 4.3.11 Power on Wafer (P\_SON1)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>PSON_N</td></tr><tr><td>2</td><td>GND</td></tr></table>

![The image displays a technical schematic symbol featuring a vertical rectangle containing two small squares stacked vertically, positioned next to the number 1.](.imb-c46h-50m-13018-1010-11/f8dda970b3ccffea94a63072313eda31d219bb859da616697c3eea09c21156a3.jpg)
Wafer 2\*1 Pin 2.54mm

# 4.3.12 eDP Backlight Control Wafer (EDP\_P1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>4</td><td>EDP_BKLT_EN</td></tr><tr><td>2</td><td>GND</td><td>5</td><td>+ 12V</td></tr><tr><td>3</td><td>EDP_BKLT_CTL</td><td>6</td><td>+ 12V</td></tr></table>

Wafer 6\*1 Pin 2.00mm

![The image displays a tall, vertical rectangular outline containing five small, hollow squares arranged in a single vertical column. To the right of the rectangle is the number 1.](.imb-c46h-50m-13018-1010-11/2b824b7969f681f56d9006fa8a4428194892a42733a2c311a314073d70136f32.jpg)

# 4.3.13 eDP VDD Select Jumper (JC\_EDP1)

<table><tr><td>Setting</td><td>Signal</td></tr><tr><td>1-2 (Default)</td><td>+ 3.3V</td></tr><tr><td>2-3</td><td>+ 5V</td></tr></table>

![The image displays a schematic diagram featuring a vertical column of three rounded rectangular boxes stacked on top of one another. Inside each rounded rectangle is a smaller square containing the lowercase letter 'm'. The top two rounded rectangles are enclosed within a larger, thick orange rectangular outline. To the left of this orange outline is the number '1'. The bottom rounded rectangle sits outside the orange outline, with a faint vertical line extending downward from it.](.imb-c46h-50m-13018-1010-11/4654a5375891658aa15d668fe46b45d42bd1168a986f73c3e64c94c57c12017c.jpg)
Jumper 3\*1 Pin 2.54mm

# 4.3.14 eDP Signal Header (EDP1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VDD_PANEL [1]</td><td>2</td><td>VDD_PANEL [1]</td></tr><tr><td>3</td><td>VDD_PANEL [1]</td><td></td><td></td></tr><tr><td>5</td><td>EDP_HPD</td><td>6</td><td>EDP_HPD</td></tr><tr><td>7</td><td>N/C</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td>10</td><td>N/C</td></tr><tr><td>11</td><td>N/C</td><td>12</td><td>N/C</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>N/C</td><td>16</td><td>N/C</td></tr><tr><td>17</td><td>EDP_TX3-</td><td>18</td><td>EDP_TX3+</td></tr><tr><td>19</td><td>EDP_TX0-</td><td>20</td><td>EDP_TX0+</td></tr><tr><td>21</td><td>EDP_TX1-</td><td>22</td><td>EDP_TX1+</td></tr><tr><td>23</td><td>EDP_TX2-</td><td>24</td><td>EDP_TX2+</td></tr><tr><td>25</td><td>GND</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>N/C</td><td>28</td><td>N/C</td></tr><tr><td>29</td><td>EDP_AUX-</td><td>30</td><td>EDP_AUX+</td></tr></table>

![1\n2](.imb-c46h-50m-13018-1010-11/b6f3cca327cbbecb5e6859291e8c9462ff70ae1f68d8ee843e796f4173ea1675.jpg)

Header 15\*2 Pin 2.00mm
Note: Panel Power VDD can be 3.3V (default) /5V selectable by eDP VDD Select Jumper” (JC\_EDP1).

# 4.3.15 PCI CLK 66MHz Enable/Disable Select Jumper (JP\_PCICLK1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>PCI CLK is 66MHz</td></tr><tr><td>2-3</td><td>PCI CLK is 33MHz</td></tr></table>

![The image displays a vertical diagram. On the far left is a large, light gray number '1'. To its right is a column of three stacked, rounded rectangular blocks. The top block is outlined in orange and contains a smaller box labeled 'B1'. Below it is a middle block containing a box labeled 'B2'. Below that is a bottom block containing a box labeled 'B3'.](.imb-c46h-50m-13018-1010-11/b1781b36f69eed4d4f35ed1161c96c1c6c77a7f382324089782e5bdc74cc446a.jpg)
Jumper 3\*1 Pin 2.54mm

# 4.4 Expansion Slots

There are 3 PCI Express slots, 4 PCI slots, 2 M.2 sockets on this motherboard.

PCIe and PCI slots:

<table><tr><td></td><td>Slot 1 (PCIe1)</td><td>Slot 2 (PCIe2)</td><td>Slot 3 (PCIe3)</td><td>Slot 4 (PCI1)</td><td>Slot 5 (PCI2)</td><td>Slot 6 (PCI3)</td><td>Slot 7 (PCI4)</td></tr><tr><td>Source</td><td>CPU</td><td>PCH</td><td>PCH</td><td>PCI bridge</td><td>PCI bridge</td><td>PCI bridge</td><td>PCI bridge</td></tr><tr><td>Bandwidth</td><td>PCIe 3.0</td><td>PCIe 3.0</td><td>PCIe 3.0</td><td>PCI</td><td>PCI</td><td>PCI</td><td>PCI</td></tr><tr><td>Lane Config</td><td>X16</td><td>x2</td><td>x1</td><td>PCI</td><td>PCI</td><td>PCI</td><td>PCI</td></tr></table>

# 4.4.1 M.2 sockets:

# 4.4.1.1 M.2 Key-M (M\_2\_PCIESSD\_M1)

<table><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>GND</td><td>+3.3V</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>+3.3V</td><td>4</td></tr><tr><td>5</td><td>PERn3</td><td>NA</td><td>6</td></tr><tr><td>7</td><td>PERp3</td><td>NA</td><td>8</td></tr><tr><td>9</td><td>GND</td><td>SATA_LED</td><td>10</td></tr><tr><td>11</td><td>PETn3</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>PETp3</td><td>+3.3V</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>16</td></tr><tr><td>17</td><td>PERn2</td><td>+3.3V</td><td>18</td></tr><tr><td>19</td><td>PERp2</td><td>NA</td><td>20</td></tr><tr><td>21</td><td>GND</td><td>NA</td><td>22</td></tr><tr><td>23</td><td>PETn2</td><td>NA</td><td>24</td></tr><tr><td>25</td><td>PETp2</td><td>NA</td><td>26</td></tr><tr><td>27</td><td>GND</td><td>NA</td><td>28</td></tr><tr><td>29</td><td>PERn1</td><td>NA</td><td>30</td></tr><tr><td>31</td><td>PERp1</td><td>NA</td><td>32</td></tr><tr><td>33</td><td>GND</td><td>NA</td><td>34</td></tr><tr><td>35</td><td>PETn1</td><td>NA</td><td>36</td></tr><tr><td>37</td><td>PETp1</td><td>DEVSLP</td><td>38</td></tr><tr><td>39</td><td>GND</td><td>SMB_CLK</td><td>40</td></tr><tr><td>41</td><td>PERn0/ SATA-B+</td><td>SMB_DATA</td><td>42</td></tr><tr><td>43</td><td>PERp0/ SATA-B-</td><td>NA</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>NA</td><td>46</td></tr><tr><td>47</td><td>PETn0/ SATA-A-</td><td>NA</td><td>48</td></tr><tr><td>49</td><td>PETPO/ SATA-A+</td><td>PERST#</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>CLKREQ#</td><td>52</td></tr><tr><td>53</td><td>PEFCLKn</td><td>WAKE#</td><td>54</td></tr><tr><td>55</td><td>PEFCLKp</td><td>NA</td><td>56</td></tr><tr><td>57</td><td>GND</td><td>NA</td><td>58</td></tr><tr><td colspan="4"></td></tr><tr><td>67</td><td>NA</td><td>NA</td><td>68</td></tr><tr><td>69</td><td>PEDET</td><td>+3.3V</td><td>70</td></tr><tr><td>71</td><td>GND</td><td>+3.3V</td><td>72</td></tr><tr><td>73</td><td>GND</td><td>+3.3V</td><td>74</td></tr><tr><td>75</td><td>GND</td><td></td><td></td></tr></table>

4.4.1.2 M.2 Key-E (M2\_E\_WLAN1)

<table><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>GND</td><td>+3.3V</td><td>2</td></tr><tr><td>3</td><td>USB_D+</td><td>+3.3V</td><td>4</td></tr><tr><td>5</td><td>USB_D-</td><td>NA</td><td>6</td></tr><tr><td>7</td><td>GND</td><td>NA</td><td>8</td></tr><tr><td>9</td><td>CNV_WGR_D1-</td><td>CNV_RF_RESET</td><td>10</td></tr><tr><td>11</td><td>CNV_WGR_D1+</td><td>NA</td><td>12</td></tr><tr><td>13</td><td>GND</td><td>MODEM_CLKREQ</td><td>14</td></tr><tr><td>15</td><td>CNV_WGR_D0-</td><td>NA</td><td>16</td></tr><tr><td>17</td><td>CNV_WGR_D0+</td><td>GND</td><td>18</td></tr><tr><td>19</td><td>GND</td><td>NA</td><td>20</td></tr><tr><td>21</td><td>CNV_WGR_CLK-</td><td>CNV_BRI_RSP</td><td>22</td></tr><tr><td>23</td><td>CNV_WGR_CLK+</td><td colspan="2"></td></tr><tr><td colspan="4"></td></tr><tr><td>33</td><td>GND</td><td>CNV_BGI_DT</td><td>32</td></tr><tr><td>35</td><td>PETp</td><td>CNV_RGI_RSP</td><td>34</td></tr><tr><td>37</td><td>PETn</td><td>CNV_BRI_DT</td><td>36</td></tr><tr><td>39</td><td>GND</td><td>NA</td><td>38</td></tr><tr><td>41</td><td>PERp</td><td>NA</td><td>40</td></tr><tr><td>43</td><td>PERn</td><td>NA</td><td>42</td></tr><tr><td>45</td><td>GND</td><td>NA</td><td>44</td></tr><tr><td>47</td><td>PEFCLKp</td><td>NA</td><td>46</td></tr><tr><td>49</td><td>PEFCLKn</td><td>NA</td><td>48</td></tr><tr><td>51</td><td>GND</td><td>SUSCLK</td><td>50</td></tr><tr><td>53</td><td>CLKREQ#</td><td>PERSTO#</td><td>52</td></tr><tr><td>55</td><td>WAKE#</td><td>W_DISABLE1#</td><td>54</td></tr><tr><td>57</td><td>GND</td><td>W_DISABLE2#</td><td>56</td></tr><tr><td>59</td><td>CNV_WT_D1-</td><td>SMB_DATA</td><td>58</td></tr><tr><td>61</td><td>CNV_WT_D1+</td><td>SMB_CLK</td><td>60</td></tr><tr><td>63</td><td>GND</td><td>NA</td><td>62</td></tr><tr><td>65</td><td>CNV_WT_D0-</td><td>CLKIN_XTAL_LCP</td><td>64</td></tr><tr><td>67</td><td>CNV_WT_D0+</td><td>NA</td><td>66</td></tr><tr><td>69</td><td>GND</td><td>NA</td><td>68</td></tr><tr><td>71</td><td>CNV_WT_CLK-</td><td>NA</td><td>70</td></tr><tr><td>73</td><td>CNV_WT_CLK+</td><td>+3.3V</td><td>72</td></tr><tr><td>75</td><td>GND</td><td>+3.3V</td><td>74</td></tr></table>

# 5 Driver Installation

Download the requisite drivers for your system from the IMB-C46H product page at:

https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/ATXMotherboards/IMB-C46H

This page intentionally left blank.

# 6 BIOS Setup

# 6.1 Menu Structure

This section presents the primary menus of the BIOS (UEFI) Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections describe the submenus and options for each menu item.

Options to enter BIOS Setup Utility:

• Press [F2] or [Del] during POST (Power-On-Self-Test)
• Press [Ctl] + [Alt] + [Del] after POST

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td></tr><tr><td>Sets up the system time/date and displays the system information:- BIOS Information- Memory Information- System Date- System Time</td><td>Contains advanced system configurations, including:► CPU Configuration► Power and Performance► PCH-FW Configuration► Trusted Computing► ACPI Settings► Super IO Configuration► Hardware Monitor► Power Control► S5 RTC Wake Settings► USC Configuration► Network Stack Configuration► CSM Configuration► NVME Configuration</td><td>Displays Hardware Status info, including:► System Agent (SA) Configuration► PCH-IO Configuration</td></tr><tr><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>Changes or clears the supervisor/user password for the system:- Administrator Password- User Password► Secure Boot</td><td>Configures the boot settings and boot priority for available devices:- Setup Prompt Timeout- Bootup Num Lock State- Full Screen Logo- Fast Boot- Boot Mode Select- Boot Option #X</td><td>Exits the BIOS Setup Utility while saving or discard the changes made:- Save/Discard Changes and Exit- Save/Discard Changes and Reset- Save/Discard Changes- Restore Defaults- Save as User Defaults- Restore User Defaults- BIOS: Built-in EFI shell- Launch EFI Shell from a filesystem device</td></tr></table>

# 6.2 Main Menu

Upon entering the BIOS Setup Utility, the Main Menu is displayed, providing read-only information about your system and also allows you to set the system date and time. Refer to the screenshots and tables below for details of the submenus and settings.

<table><tr><td>Feature</td><td>Options</td></tr><tr><td colspan="2">BIOS Information</td></tr><tr><td>BIOS Vendor</td><td>Info only</td></tr><tr><td>Core Version</td><td>Info only</td></tr><tr><td>Compliancy</td><td>Info only</td></tr><tr><td>Project Version</td><td>IMB-C46H_xxxxx</td></tr><tr><td>Build Date and Time</td><td>Info only</td></tr><tr><td>Access Level</td><td>Info only</td></tr><tr><td colspan="2">Memory Information</td></tr><tr><td>Total Memory</td><td>Info only</td></tr><tr><td>Memory Frequency</td><td>Info only</td></tr><tr><td>System Date</td><td>xxx mm/dd/yyyy</td></tr><tr><td>System Time</td><td>hh:mm:ss</td></tr></table>

# 6.3 Advanced

This menu contains the following information:

<table><tr><td colspan="2">Feature</td></tr><tr><td>▶ CPU Configuration</td><td>▶ OEM Flavor</td></tr><tr><td>▶ Power &amp; Performance</td><td>▶ Power Control</td></tr><tr><td>▶ PCH-FW Configuration</td><td>▶ S5 RTC Wake Settings</td></tr><tr><td>▶ Trusted Computing</td><td>▶ USB Configuration</td></tr><tr><td>▶ ACPI Settings</td><td>▶ Network Stack Configuration</td></tr><tr><td>▶ Super IO Configuration</td><td>▶ CSM Configuration</td></tr><tr><td>▶ Hardware Monitor</td><td>▶ NVME Configuration</td></tr></table>

# 6.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Type</td><td>Displays the Processor Type.</td></tr><tr><td>ID</td><td>Displays the Processor ID.</td></tr><tr><td>Speed</td><td>Displays the Processor Speed.</td></tr><tr><td>L1 Data Cache</td><td>Displays the Processor L1 Data Cache size.</td></tr><tr><td>L1 Instruction Cache</td><td>Displays the Processor L1 Instruction Cache size.</td></tr><tr><td>L2 Cache</td><td>Displays the Processor L2 Data Cache size.</td></tr><tr><td>L3 Cache</td><td>Displays the Processor L3 Data Cache size.</td></tr><tr><td>L4 Cache</td><td>Displays the Processor L4 Data Cache size.</td></tr><tr><td>VMX</td><td>VMX Supported or Not.</td></tr><tr><td>SMX/TXT</td><td>SMX/TXT Supported or Not.</td></tr><tr><td>Turbo Mode</td><td>Enable or disable processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled)</td></tr><tr><td>Intel (VWX) Virtualization Technology</td><td>When enabled, a VWX can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr></table>

# 6.3.2 Power and Performance

Power and performance options.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>▶ CPU - Power Management Control</td><td>CPU - Power Management Control Options.</td></tr><tr><td>▶ GT - Power Management Control</td><td>GT - Power Management Control Options.</td></tr></table>

6.3.2.1 CPU-Power Management Control

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Boot performance mode</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) Speed Step(tm)</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Race To Halt (RTH)</td><td>Enables or disables Race to Halt feature. RTH will dynamically increase CPU frequency to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20).</td></tr><tr><td>Intel(R) Speed Shift technology</td><td>Enables or disables Intel(R) Speed Shift technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Per Core P State OS control mode</td><td>For RKL only. Enables or disables Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.</td></tr><tr><td>HwP Autonomous Per Core P State</td><td>For RKL only. Disables Autonomous PCPS (Bit 30 = 1, command 0x11). Autonomous will request the same value for all cores all the time. Enables PCPS (default Bit 30 = 0, command 0x11).</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>For RKL only. Enables EPP grouping (default Bit 29=0, command 0x11). Autonomous will request the same value for all cores with same EPP. Disables EPP grouping (Bit 29 = 1, command 0x11). Autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>For RKL only. Enables or disables EPB override over PECI. Enabled by sending pcode command 0x2b, subcommand 0x3 to 1. This will allow 00B EPB PECI override control.</td></tr><tr><td>Hwp Fast MSR Support</td><td>For RKL only. Enables or disables Hwp Fast MSR Support for IA32_HWP_REQUEST MSR.</td></tr><tr><td>HDC Control</td><td>This option allows HDC configuration:Disabled: Disables HDC.Enabled: Can be enabled by OS if OS native support is available.</td></tr><tr><td>► View/Configure Turbo options</td><td>View/Configure Turbo options.</td></tr><tr><td>► CPU VR Settings</td><td>CPU VR Settings.</td></tr><tr><td>Platform PL1 Enable</td><td>Enables or disables Platform Power Limit 1 programming.If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of a given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>Enables or disables Platform Power Limit 2 programming.If this option is disabled, BIOS will program the default values for Platform Power Limit 2.</td></tr><tr><td>Power Limit 4 override</td><td>Enables or disables Power Limit 4 override.If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>Power Limit 4</td><td>Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. For 12.50W, enter 12500. If the value is 0, BIOS leaves default value.</td></tr><tr><td>Power Limit 4 Lock</td><td>Power Limit 4 MSR 601h Lock. When enabled PL4 configurations are locked during OS. When disabled PL4 configuration can be changed during OS.</td></tr><tr><td>C states</td><td>Enables or disables CPU Power Management.Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Thermal Monitor</td><td>Enables or disables Thermal Monitor.</td></tr><tr><td>Interrupt Redirection Mode Selection</td><td>Interrupt Redirection Mode Select for Logical Interrupts.</td></tr><tr><td>Timed MWAIT</td><td>Enable or disable Timed MWAIT Support.</td></tr><tr><td>► Custom P-state Table</td><td>Add Custom P-state Table.</td></tr><tr><td>Energy Performance Gain</td><td>Enable or disable Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>Display EPG DIMM ldd3N.</td></tr><tr><td>EPG DIMM ldd3P</td><td>Display EPG DIMM ldd3P.</td></tr><tr><td>► Power Limit 3 Settings</td><td>Power Limit 3 Settings.</td></tr><tr><td>► CPU Lock Configuration</td><td>CPU Lock Configuration.</td></tr><tr><td>Dual Tau Boost</td><td>Enable Dual Tau Boost feature. This is only applicable for CMLS 35W/65W/125W SKU. When DPTF is enabled, this feature is ignored.</td></tr></table>

6.3.2.1.1 View/Configuration Turbo Options

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Energy Efficient P-state</td><td>Enable or disable the Energy Efficient P-state feature. When set to 0, access to ENERGY_PERFORMANCE_BIAS MSR is disabled, and CPUID Function 6 ECX[3] will read 0, indicating no support for Energy Efficient policy setting. When set to 1, access to ENERGY_PERFORMANCE_BIAS MSR 1B0h is enabled, and CPUID function 6 ECX[3] will read 1, indicating Energy Efficient policy setting is supported.</td></tr><tr><td>Package Power Limit MSR Lock</td><td>Enable or disable locking of Package Power limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked, and a reset will be required to unlock the register.</td></tr><tr><td>Power Limit 1 Override</td><td>Enable or disable Power Limit 1 override. If this option is disabled, the BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.</td></tr><tr><td>Power Limit 2 Override</td><td>Enable or disable Power Limit 2 override. If this option is disabled, the BIOS will program the default values for Power Limit 2.</td></tr><tr><td>Power Limit 2</td><td>The Power Limit 2 value is in milliwatts. The BIOS will round it to the nearest 1/8W during programming. If the value is 0, the BIOS will program this value as 1.25 * TDP. For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Turbo Ratio Limit Ratio0 (TRLR)</td><td>Turbo Ratio Limit Ratio0 (TRLR) with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio. Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit0 is paired with Turbo Ratio NumCores0 and must be greater than or equal to all other ratio values. If this value is invalid, then set all other active cores to minimum. Otherwise, align the Ratio Limit to 0. Please check each active core.</td></tr><tr><td>Turbo Ratio Limit Ratio1 (TRLR)</td><td>Turbo Ratio Limit Ratio1 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit1 is paired with Turbo Ratio NumCores1 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio2</td><td>Turbo Ratio Limit Ratio2 with a range of (Max Non-Turbo Ratio - 255). Min = Max</td></tr><tr><td>(TRLR)</td><td>Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit2 is paired with Turbo Ratio NumCores2 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio3 (TRLR)</td><td>Turbo Ratio Limit Ratio3 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit3 is paired with Turbo Ratio NumCores3 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio4 (TRLR)</td><td>Turbo Ratio Limit Ratio4 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit4 is paired with Turbo Ratio NumCores4 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Turbo Ratio Limit Ratio5 (TRLR)</td><td>Turbo Ratio Limit Ratio5 with a range of (Max Non-Turbo Ratio - 255). Min = Max Non-Turbo Ratio, Max = fused turbo ratio, or 255 if CPU is unlocked for overclocking. This Core Ratio Limit5 is paired with Turbo Ratio NumCores5 and must be less than or equal to Core Ratio Limit0.</td></tr><tr><td>Energy Efficient Turbo</td><td>Enable or disable the Energy Efficient Turbo feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.</td></tr></table>

6.3.2.1.2 CPU VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Power Delivery Design</td><td>Specifies the CML-S board design used for the VR settings override values. By default, BIOS will override the default CML-S VR settings based on the board design. A value of AUTO (0) will use the board ID to determine the board design. Any other value will override the board ID logic to provide a custom VR Power Delivery Design value. This feature is intended primarily for validation.</td></tr><tr><td>PSYS Slope</td><td>PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9.</td></tr><tr><td>PSYS Offset</td><td>PSYS Offset defined in 1/4 increments. Range is 0-255. For an offset of 25, enter 100. Uses BIOS VR mailbox command 0x9.</td></tr><tr><td>PSYS PMax Power</td><td>PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.</td></tr><tr><td>▶ Acoustic Noise Setting</td><td>Configure Acoustic Noise Settings for IA, GT, and SA domains.</td></tr><tr><td>▶ Core/IA VR Settings</td><td>Core/IA VR Settings.</td></tr><tr><td>▶ GT VR Settings</td><td>GT VR Settings.</td></tr><tr><td>Intersil VR Command</td><td>VR Mailbox command to fix Intersil VR C-state issues. Disabled- No Mailbox command sent. Default is Disabled.</td></tr></table>

6.3.2.1.2.1 Acoustic Noise Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Acoustic Noise Mitigation</td><td>Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state. This needs to be enabled to program PreWake, Ramp Up, and Ramp Down times.</td></tr></table>

6.3.2.1.2.2 Core/IA VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Config Enable</td><td>VR Config Enable</td></tr><tr><td>AC Loadline</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS3 Enable</td><td>Enable or Disable PS3. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command0x3.</td></tr><tr><td>PS4 Enable</td><td>Enable or Disable PS4. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Current Limit</td><td>Voltage Regulator Current Limit (Icc Max). This value represents the maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. Uses BIOS VR mailbox command 0x6.</td></tr><tr><td>TDC Enable</td><td>TDC Enable. 0- Disable, 1 – Enable.</td></tr><tr><td>TDC Current Limit</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = Auto/Intel Default. Uses the BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>TDC Time Window, value in milliseconds. 1ms is default. The range is from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.</td></tr><tr><td>TDC Lock</td><td>Enabled or Disabled TDC Lock.</td></tr></table>

6.3.2.1.2.3 GT VR Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>VR Config Enable</td><td>VR Config Enable.</td></tr><tr><td>AC Loadline</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS3 Enable</td><td>Enable or Disable PS3. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS4 Enable</td><td>Enable or Disable PS4. 0 - Disabled, 1 - Enabled. It uses the BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. It uses the BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Current Limit</td><td>Voltage Regulator Current limit (Icc Max). This value represents the maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. It uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>VR Voltage Limit, defined in mV. Range is 0-7999mV. For a Voltage Limit of 1.25V, enter 1250. 0 = AUTO. It uses the BIOS VR mailbox command 0x6.</td></tr><tr><td>TDC Enable</td><td>TDC Enable. 0 - Disable, 1 - Enable.</td></tr><tr><td>TDC Current Limit</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = Auto/Intel Default. It uses the BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>TDC Time Window, value in milliseconds. 1ms is default. Range from 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.</td></tr><tr><td>TDC Lock</td><td>Enabled or Disabled TDC Lock.</td></tr></table>

6.3.2.1.3 Custom P-State Table Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Number of P states</td><td>Sets the number of custom P-states. At least 2 states must be present.</td></tr></table>

6.3.2.1.4 Power Limit 3 Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Power Limit 3 Override</td><td>Enable or disable Power Limit 3 Override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr></table>

6.3.2.1.5 CPU Lock Configuration Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>CFG Lock</td><td>Configure MSR 0xE2[15], CFG Lock bit.</td></tr><tr><td>Overclocking Lock</td><td>Enable or Disable Overclocking Lock (BIT 20) in FLEX_RATIO (194) MSR.</td></tr></table>

6.3.2.2 GT-Power Management Control

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>RC6 (Render Standby)</td><td>Check to enable render standby support.</td></tr><tr><td>Maximum GT frequency</td><td>Maximum GT frequency limited by the user. Choose between 350MHz (RPN) and 1200MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU.</td></tr><tr><td>Disable Turbo GT frequency</td><td>Enabled: Disables Turbo GT frequency.Disable: GT frequency is not limited.</td></tr></table>

# 6.3.3 PCH-FW Configuration

Configure management engine technology parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>ME Firmware</td><td>Display ME Firmware information.</td></tr></table>

# 6.3.4 Trusted Computing

Trusted computing settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Firmware Version</td><td>Displays TPM Firmware Version.</td></tr><tr><td>Vendor</td><td>Displays TPM Vendor.</td></tr><tr><td>Security Device Support</td><td>Enables or disables Security Device.Note: Your computer will reboot during restart in order to change state of the device.</td></tr><tr><td>Active PCR Banks</td><td>Displays Active PCR banks.</td></tr><tr><td>Available PCR Banks</td><td>Displays Available PCR banks.</td></tr><tr><td>SHA256 PCR Bank</td><td>Enables or disables SHA256 PCR Bank.</td></tr><tr><td>Pending Operation</td><td>Schedule an Operation for the Security Device.Note: Your computer will reboot during restart in order to change the state of the security device.</td></tr><tr><td>Platform Hierarchy</td><td>Enables or disables Platform Hierarchy.</td></tr><tr><td>Storage Hierarchy</td><td>Enables or disables Storage Hierarchy.</td></tr><tr><td>Endorsement Hierarchy</td><td>Enables or disables Endorsement Hierarchy.</td></tr><tr><td>Physical Presence Spec Version</td><td>Select to inform the O.S. to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.</td></tr><tr><td>TPM 2.0 Interface Type</td><td>Selects the Communication Interface to TPM 2.0 device.</td></tr><tr><td>Device Select</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated.</td></tr></table>

# 6.3.5 ACPI Settings

Set ACPI the (Advanced Configuration and Power Management Interface) parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Enables or disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Enables or disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Select the highest ACPI sleep state that the system will enter when the SUSPEND button is pressed.</td></tr></table>

# 6.3.6 Super IO Configuration

System Super IO Chip parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>COM1-6</td><td>Set Parameters of Serial Port 1-6.The options after entering the interface settings above are as follows.Serial Port: Enables or Disables Serial Port (COM).Device Settings: Displays the Current Device Settings.Change Settings: If the board supported, this menu shows. Select an optimal setting for Super IO Device.</td></tr></table>

# 6.3.7 Hardware Monitor

Monitor the hardware status.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► Fan function</td><td>FAN1 Mode: FAN1 Mode Select. Full on Mode; Automatic Mode; Manual Mode.</td></tr><tr><td>CHASSIS OPEN</td><td>Enable or disable CHASSIS OPEN Function.</td></tr><tr><td>LED S3 Function</td><td>Enable or disable LED S3 Blink function.</td></tr><tr><td>CPU Temp</td><td>Displays CPU Temperature.</td></tr><tr><td>SYS Temp</td><td>Displays System Temperature.</td></tr><tr><td>CPU_FAN1</td><td>Displays CPU FAN Speed.</td></tr><tr><td>SYS_FAN1</td><td>Displays System FAN1 Speed.</td></tr><tr><td>SYS_FAN2</td><td>Displays System FAN2 Speed.</td></tr><tr><td>VCC_CPU</td><td>Displays CPU Core Voltage Value.</td></tr><tr><td>VCC_DDR</td><td>Displays Memory Voltage Value.</td></tr><tr><td>+12</td><td>Displays +12 Voltage Value.</td></tr><tr><td>+5</td><td>Displays +5 Voltage Value.</td></tr><tr><td>+3.3</td><td>Displays +3.3 Voltage Value.</td></tr></table>

# Set Up Chassis Open Detection:

1. Select “Advanced - Hard Monitor – CHASSIS OPEN” (This menu shows only that this function is supported).

2. Set the item to “Enabled.”

Sound the alarm if the chassis is opened; stop if it’s closed.

When the open-box detection cap is shorted, the chassis is considered to have been compromised. The post interface will prompt intrusion alarms and the status record need to be cleared to stop the alarm.

# Clear Chassis Open Status:

1) In the BIOS Setup Utility, press the F3 key and the enter key to load the optimization default value. Save & exit to clear the out-of-box status record.

# Set Up Fan Control:

1) Select “Advanced - Hard Monitor - Fan Function” item (This menu shows only this function is supported);
2) Select the fan to set up, such as “CPU\_FAN1 Mode”. Select the operating mode for this fan: full on mode, automatic mode, manual mode.
3) After selecting the manual mode, the manual PWM setting input (set range 0-255) specifies the fan speed.
4) After selecting the automatic mode, there will be a fan off temperature limit, fan start temperature limit, fan start PWM, and PWM SLOPE SETTING options to set up.

Generally, due to the differences in fan performance, the actual performance of smart fans will differ from the set value. It is recommended to set the PWM SLOPE SETTING to 8PWM to ensure that the fan speed increases with the temperature.

# 6.3.8 Power Control

Power button control settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PowerOn After PowerFail</td><td>Specify what state to go to when the power is re-applied after a power failure (G3 state).</td></tr><tr><td>Soft-Off by PWR-BTTN</td><td>Soft-Off by PWR-BTTN.</td></tr><tr><td>ME Function Ctrl</td><td>ME Function Ctrl.</td></tr><tr><td>RJ45_USB1 Power Ctrl</td><td>Select USB power control mode.</td></tr><tr><td>PCIE OOR FIXED Enabled</td><td>Enable or disable PCIE OOR FIXED.</td></tr></table>

# Set Up Power-on Self:

1. Select “Advanced - Power Control - PowerOn After PowerFail.”
2. Change “PowerOn After Power Fail” value: Power Off, Power On, Last State.

# 6.3.9 S5 RTC Wake Settings

Enable the system to wake from S5 using the RTC alarm.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Wake system from S5</td><td>Enables or disables the system wake on alarm event. Select Fixed Time, system will wake on the hr::min::sec specified. Select Dynamic Time, System will wake on the current time + Increase minute(s).Fixed Time:1. Select “Advanced - S5 RTC Wake Settings - Wake system from S5”.2. Change it from disabled status to fixed time;3. Set the point in time to customize the boot settings in the “wake up day, wake up hour, wake up minute, and wake up second” that appears. For example, setting day: 2, hour: 13, minute:0, second:0 means the system will boot on the 2nd of each month at 13:00. Setting day as 0 means that the system is will boot at the given specified time every day.</td></tr></table>

# Set Up Timed Power On:

1. Select “Advanced - S5 RTC Wake Settings - Wake system from S5.”
2. Change it from disabled status to fixed time.
3. Set the time for customizing the boot settings in “wake up day, wake up hour, wake up minute, and wake up second”. For example, setting day: 2, hour: 13, minute:0, second:0 means the system will boot on the 2nd of each month at 13:00. Setting day as 0 means that the system is will boot at the given specified time every day.

# 6.3.10 USB Configuration

USB configuration parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Displays USB Configuration.</td></tr><tr><td>Legacy USB Support</td><td>Enables Legacy USB Support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-Off</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>Enables or disables USB Mass Storage Driver Support.</td></tr><tr><td>USB Transfer Time-Out</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device Reset Time-Out</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device Power-Up Delay</td><td>Maximum time the device will take before it properly reports itself to the Host Controller. ‘Auto’ uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.</td></tr></table>

# 6.3.11 Network Stack Configuration

Network Stack Settings

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Network Stack</td><td>Enables or disables UEFI Network Stack</td></tr><tr><td>IPv4 PXE Support</td><td>Enable or disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv6 PXE Support</td><td>Enable or disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>Pxe Boot Lan Select</td><td>Enable or disable Pxe Boot Lan select.</td></tr></table>

# Open UEFI PXE:

1. Please select “Advanced - Network Stack Configuration.”
2. Set Network Stack or UEFI PXE to Enabled.

# 6.3.12 CSM Configuration

CSM (Compatibility Support Module) configuration: Enable/disable, option ROM execution settings, etc.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>CSM Support</td><td>Enables or Disables CSM Support.</td></tr><tr><td>CSM16 Module Version</td><td>CSM16 Module Version.</td></tr><tr><td>GateA20 Active</td><td>UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>INT19 Trap Response</td><td>BIOS reaction on INT19 trapping by Option ROM: IMMEDIATE - execute the trap right away; POSTPONED - execute the trap during legacy boot.</td></tr><tr><td>HDD Connection Order</td><td>Some OS require HDD handled to be adjusted, i.e., OS is installed on drive 80h.</td></tr><tr><td>Boot Option Filter</td><td>This option controls Legacy/BIOS ROMs priority.</td></tr><tr><td>Network</td><td>Controls the execution of UEFI and Legacy Network OpROM.</td></tr><tr><td>Storage</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI Devices</td><td>Determines OpROM execution policy for devices other than network, storage, or video.</td></tr></table>

# Open Legacy PXE:

1) Please select “Advanced - CSM configuration”.

2) Change network item to legacy.

# 6.3.13 NVMe Configuration

NVMe device option settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>NVMe Devices</td><td>Displays information about NVMe devices.</td></tr><tr><td>Self-Test Option</td><td>Select either short or extended self-test. Short option will take a couple of minutes and extended option will take several minutes to complete.</td></tr><tr><td>Self-Test Action</td><td>Select either to test controller alone or controller and namespace. Selecting controller and namespace option will take longer to complete the test.</td></tr><tr><td>Run Device Self-Test</td><td>Perform device self-test for the corresponding option and action selected by user. Pressing ‘ESC’ key will abort the test. Result shown below is the recent result logged in the device.</td></tr></table>

# 6.4 Chipset

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► System Agent (SA) Configuration</td><td>System Agent (SA) Parameters.</td></tr><tr><td>► PCH-IO Configuration</td><td>PCH Parameters.</td></tr></table>

# 6.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>▶ Memory Configuration</td><td>Memory Configuration Parameters.</td></tr><tr><td>▶ Graphics Configuration</td><td>Graphics Configuration.</td></tr></table>

# 6.4.1.1 Memory Configuration Parameters

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>Memory Configuration Parameters.</td></tr></table>

# 6.4.1.2 Graphics Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Primary Display</td><td>Select which of the IGFX/PEG/PCI Graphics devices should be the primary display or select SG for Switchable Gfx.</td></tr><tr><td>Internal Graphics</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>Select the GTT Size.</td></tr><tr><td>Aperture Size</td><td>Select the Aperture Size. Note: Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM Support.</td></tr><tr><td>DVMT Pre-Allocated</td><td>Select DVMT5.0 Pre-Allocated (Fixed) Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

# 6.4.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>PCI Express Configuration settings.</td></tr><tr><td>SATA And RST Configuration</td><td>SATA Device Options Settings.</td></tr><tr><td>USB Configuration</td><td>USB Configuration Settings.</td></tr><tr><td>HD Audio Configuration</td><td>HD Audio Configuration Settings.</td></tr></table>

# 6.4.2.1 PCI Express Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCIE Port</td><td>PCI Express Root Port Settings</td></tr></table>

# 6.4.2.2 SATA and RST Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Enables or disables SATA device.</td></tr><tr><td>SATA Mode Selection</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>Serial ATA Port X</td><td>Port X: Enables or disables SATA port.</td></tr></table>

# 6.4.2.3 USB Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>XHCI Compliance Mode</td><td>Option to enable Compliance mode. Default is to disable Compliance mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>USB Port Disable Override</td><td>Selectively enables or disables the corresponding USB port from reporting a device connection to the controller.</td></tr></table>

# 6.4.2.4 HD Audio Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>HD Audio</td><td>Control detection of the HD-audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled.</td></tr></table>

# 6.5 Security

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Set Administrator Password.</td></tr><tr><td>User Password</td><td>Set User Password.</td></tr><tr><td>▶ Secure Boot</td><td>Secure Boot configuration.</td></tr></table>

# 6.5.1 Secure Boot

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Secure Boot</td><td>Secure Boot feature is active if Secure Boot is enabled, Platform Key(PK) is enrolled and the system is in user mode. The mode change requires platform reset.</td></tr><tr><td>Secure Boot mode</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr></table>

When setting up an administrator password, it is recommended to enter it when accessing the BIOS setup program to avoid some BIOS information or settings that are unavailable due to user rights are insufficient (no password is entered as a user).

When setting a user password, you must use the user password to access the BIOS setup program, which means that you need to enter the user password when booting the operating system (using the BIOS boot feature).

# Set/Change the Administrator Password:

1. Select “Security - Administrator Password.”
2. Enter the desired password in the “Create New Password” window and press Enter. You will need to confirm by entering current password before accessing the “Create New Password” window.
3. Re-enter the new password to ensure it is entered correctly.

To delete an administrator password, press the Carriage Return in the “Create New Password” window.

# Set/Change the User Password:

1) Select “Security - User Password.”
2) Enter the password you want to set in the “Create New Password” window and press Enter. You will need to confirm by entering the current password before accessing the “Create New Password” window.
3) Re-enter the new password to ensure it is entered correctly.

To delete a user password, press the carriage return in the “Create New Password” window.

# 6.6 Boot

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Setup Prompt Timeout</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup Num Lock State</td><td>Select the keyboard Num Lock state.</td></tr><tr><td>Full Screen Logo</td><td>Enables or disables Full Screen Logo option.</td></tr><tr><td>Fast Boot</td><td>Enabled or disabled boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot option.</td></tr><tr><td>Boot mode Select</td><td>Select Boot mode LEGACY/BIOS.</td></tr><tr><td>Boot Option #X</td><td>Sets the system boot order.</td></tr></table>

# Set Boot Sequence:

1) Select “Boot” in the menu page.
2) Change “Boot Option #1” to the desired device.

3) If there are more than one similar device, example, more than one hard drive, enter “Hard Disk Drive BBS Priorities” and change the boot order priority between the drives first.

When the Boot page has the Boot Mode option, it is recommended to set it to “dual” so that both Legacy and BIOS boot projects can be booted. UEFI boot items will be filtered when selected for Legacy, and legacy boot items will be filtered when selected as BIOS.

# 6.7 Save & Exit

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Changes</td><td>Save changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Discard changes done so far to any of the setup options.</td></tr><tr><td>Default Options</td><td>Default Options.</td></tr><tr><td>Restore Defaults</td><td>Restore/Load default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Boot Override.</td></tr><tr><td>BIOS: Built-in EFI shell</td><td>Launch BIOS Built-in UEFI Shell.</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td>Attempts to launch EFI Shell application (Shell.efi) from one of the available filesystem devices.</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.imb-c46h-50m-13018-1010-11/imb-c46h-50m-13018-1010-11.pdf)