# IMB-M45

# User’s Manual

ATX Motherboard with 8th/9th Gen Intel® Core™ i7/i5/i3 Processors or Xeon™ E Processors and Intel® C246 Chipset

![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.imb-m45-50m-00067-1010/109d279ab4c190d0343692c1fada60d2196d62dff05c0cc01a72fc14504b0ec8.jpg)

Manual Rev.: 1.1

Revision Date: March 7, 2022

Part Number: 50M-00067-1010

# Preface

# Copyright

Copyright 2021 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin with crossed lines indicating no waste or restriction, and a solid black rectangle below (no text or labels)](.imb-m45-50m-00067-1010/b7f807da2f1fa9376ff41d6a20702c1defe5acf29026dd61ce472f8458fe09d2.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin crossed out by two diagonal lines (no text or symbols)](.imb-m45-50m-00067-1010/e8d0b37021e63814f31f826a7caf596893f77cf2642dbad12d624bc9f3d2ab76.jpg)

![The image features a black outline of the universal recycling symbol (three chasing arrows) enclosed in a square border. Below the symbol, the text 'Li-ion' appears in bold black font.](.imb-m45-50m-00067-1010/3e51998a85f7f3520e8146e283e41dc6f9f9cc8d80c6caa0fe316f699f96a17b.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.imb-m45-50m-00067-1010/1cf6ea9db7fb0b3e32aa664af4433ade2c4b2f8014dbb5390e9d25f105b4cba5.jpg)

![廢電池請回收](.imb-m45-50m-00067-1010/b47aa57054e65d6db5dc1fbddd3bd612f88e5dd319fcc4fb4a89a7c4d51efb54.jpg)

# California Proposition 65 Warning

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border. Inside the triangle, centered, is a large black exclamation point.](.imb-m45-50m-00067-1010/711ce0832ec8ccbac6902b3360a417ec993012a11e76bedc569e3fb5774753fe.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2021-01-24</td><td>RA</td></tr><tr><td>1.1</td><td>Update COM connector pin definitions; update addresses</td><td>2022-03-07</td><td>CC</td></tr></table>

# Table of Contents

Preface ....

List of Figures ........ ...vi

List of Tables ...... ..vii

1 Introduction....

1.1 Packing List ..
1.2 Optional Accessories ..

2 Specifications ...

2.1 Core System .. .3
2.2 I/O Interface .. 4
2.3 Video 4
2.4 Audio . 4
2.5 LAN.. 4
2.6 Temperatures . .4
2.7 Humidity... .5
2.8 Certificate (EMC) .. .5
2.9 Form Factor .. .5
2.10 Operating Systems .. 5
2.11 Functional Block Diagram . .6

3 Mechanical Layout ..

3.1 Connector Locations .....
3.2 Mechanical Dimensions . ..10

4 Connector Pinouts ................. .11

4.1 Rear IO Connectors . .11
4.2 Internal Connectors.. .15
4.3 Jumper and Switch Settings... .22

5 Driver Installation ...... .27

6 System Resources ................ .29

6.1 System Memory Map . .29
6.2 I/O Map ... .29
6.3 Interrupt Request (IRQ) Lines .. .31
6.4 PCI Features.. .32
6.5 SMBus Slave Addresses... .33

# 7 BIOS Setup....... .35

7.1 Menu Structure . ..35
7.2 Main Menu . .36
7.3 Advanced Menu.. .37
7.4 Chipset Menu...... ..46
7.5 Security Menu.. .53
7.6 Boot Menu . ..54
7.7 Save & Exit Menu . ..55

# Safety Instructions... .57

# Getting Service..... .58

# List of Figures

Figure 1: Functional Block Diagram . .6
Figure 2: IO Panel Connector Locations ..
Figure 3: Onboard Connector Locations . .8
Figure 4: Mechanical Dimensions .. ...10
Figure 5: Mechanical Dimensions - IO Panel.. ...10

# List of Tables

Table 1: IO Panel Connector Definitions .

Table 2: Onboard Connector Definitions . .8

Table 3: Jumper and Switch Definitions . ..22

Table 4: System Memory Map .. ..29

Table 5: IO Map.. ..29

Table 6: IRQ Lines PIC Mode . ...31

Table 7 IRQ Lines APIC Mode . ...31

Table 8 PCI Configuration Space Map... ...32

Table 9 PCI Interrupt Routing Map.. ...33

Table 10 SMBus Slave Addresses. ..33

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# 1 Introduction

The IMB-M45 is an ATX motherboard supporting Intel® Xeon™ E workstation and 8th and 9th Generation Intel® Core™ i7/i5/i3 desktop processors, an Intel® C246 Chipset, and 5 PCIe expansion slots to provide a costcompetitive embedded computing solution. With high-speed data transfer interfaces such as PCIe 3.0/2.0, USB 3.1 Gen2, and SATA 6 Gb/s (SATA III), dual-channel DDR4 memory up to 128 GB in four DIMM slots for industrial automation applications, the IMB-M45 offers a significant competitive advantage for embedded computing applications. The rugged I/O design enhances system flexibility with robust device compatibility, durable connectivity, and extreme environment readiness.

# 1.1 Packing List

IMB-M45 ATX motherboard
Rear I/O shield

# 1.2 Optional Accessories

 2-port USB 2.0 cable with bracket (Part Number: 30-25010-3010)
4-port USB 2.0 cable with bracket (Part Number: 30-25009-3000)
 2-port USB 3.0 cable with bracket (Part Number: 30-25046-0100)
1-port LPT cable with bracket (Part Number: 30-25019-2000)
 2-port COM cable with bracket (Part Number: 30-25003-3000)
 PS/2 keyboard/mouse cable with bracket from 6P pin-header (Part Number: 30-01019-2010)
 1-port SATA cable (Part Number: 30-10057-7000)
 CPU cooler for &lt;=65W and 35W CPU (Part Number: 32-20113-2000, including CPU cooler backplane)
CPU cooler for &gt;65W CPU (Part Number: 32-20831-0000-A0, Backplane Part Number: 32-50031-0000- A0)

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# 2 Specifications

# 2.1 Core System

 CPU: Intel® Xeon™ E or 8th/9th Generation Intel® Core™ i7/i5/i3 Desktop Processor, LGA1151 socket

 Intel® Xeon™ E-2278GE, 3.3GHz, 16M Cache, 80W TDP, LGA1151, DDR4 2666MHz support, (8C/16T)
 Intel® Xeon™ E-2226GE, 3.4GHz, 12M Cache, 80W TDP, LGA1151, DDR4 2666MHz support, (6C/6T)
 Intel® Xeon™ E-2176G, 3.7GHz, 12M Cache, 80W TDP, LGA1151, DDR4 2666MHz support, (6C/12T)
 Intel® Xeon™ E-2124G, 3.4GHz, 8M Cache, 71W TDP, LGA1151, DDR4 2666MHz support, (4C/4T)
 Intel® Core™ i7-8700, 3.2GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support, (6C/12T)
 Intel® Core™ i7-8700T, 2.4GHz 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support, (6C/12T)
 Intel® Core™ i5-8500, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support, (6C/6T)
 Intel® Core™ i5-8500T, 2.1GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support, (6C/6T)
 Intel® Core™ i3-8100, 3.6GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support, (4C/4T)
 Intel® Core™ i3-8100T, 3.1GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (4C/4T)
 Intel® Pentium® G5400, 3.7GHz, 4M Cache, 58W TDP, LGA1151, DDR4 2400MHz support, (2C/4T)
 Intel® Pentium® G5400T, 3.1GHz, 4M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (2C/4T)
 Intel® Celeron® G4900, 3.1GHz, 2M Cache, 54W TDP, LGA1151, DDR4 2400MHz support, (2C/2T)
 Intel® Celeron® G4900T, 2.9GHz, 2M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (2C/2T)
 Intel® Core™ i7-9700E, 2.6GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (8C/8T)
 Intel® Core™ i7-9700TE, 1.8GHz, 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (8C/8T)
 Intel® Core™ i5-9500E, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T)
 Intel® Core™ i5-9500TE, 2.2GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T)
 Intel® Core™ i3-9100E, 3.1GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (4C/4T)
 Intel® Core™ i3-9100TE, 2.2GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (4C/4T)

Chipset: Intel® C246 Chipset
 Memory: 4x 288-pin DDR4 ECC or NON ECC socket dual-channel DDR4 2400/2666 MHz, up to 128 GB (based on CPU)
 BIOS: AMI® UEFI BIOS, 256 Mb SPI Flash Memory

# 2.2 I/O Interface

# Expansion slots:

# Signals

 If PEG2 is occupied, PEG1 is PCIe x8 Gen3, PEG2 is PCIe x8 Gen3
If PEG2 is not occupied, PEG1 is PCIe x16 Gen3, and PEG2 has no signal
 PCIe1: PCIe x4 Gen3, PCIe2: PCIe x4 Gen3, PCIe3: PCIe x4 Gen3
 PCI1/ PCI2: PCI 2.2

# Physical Slots

PEG1: PCIe x16 slot, PCI1: PCI slot, PEG2: PCIe x16 slot, PCIe1: PCIe x4 slot, PCIe2: PCIe x4 slot, PCIe3: PCIe x4 slot, PCI2: PCI slot

 LAN: LAN1: Intel® I219-LM via RJ45 connector (rear), LAN2: Intel® I210-AT via RJ45 connector (rear)
 SATA: 6x SATA 6.0 Gb/s connectors, Intel® software RAID 0/1/5/10 support
 USB: 4x USB 3.1 Gen2 connectors (rear), 2x USB 3.1 Gen1 pin headers, 6x USB 2.0 pin headers,1x USB 3.1 Gen1 (vertical Type-A connector), 1x USB 2.0 (vertical Type-A connector)
 COM: 2x RS-232/422/485 with auto flow control connector (rear), 4x RS-232 pin headers
 Parallel Port: 1x LPT pin header
 PS/2 Combo Port: 1x PS/2 keyboard/mouse pin header
DIO: 2x 20-pin/2.0mm GPIO pin header: 16 in and 16 out, one ground pin and one power pin

# 2.3 Video

Graphics Engine: Integrated Intel® HD Graphics series (based on CPU)
 Interfaces: 1x VGA connector (rear), resolution up to 1920 x 1200 at 60 Hz, 1x HDMI connector (rear) resolution up to 3840 x 2160 at 30 Hz, 1x DP connector (rear), resolution up to 3840 x 2160 at 60 Hz

# 2.4 Audio

 Audio Codec: Realtek® ALC892-CG or ALC888S
Interfaces: 1x Mic-in and 1x Line-out connector (rear)

# 2.5 LAN

LAN1: Intel® I219-LM via RJ45 connector (rear)
 LAN2: Intel® I210-AT via RJ45 connector (rear)

# 2.6 Temperatures

Operating Temperature: 0°C to $6 0 ^ { \circ } \mathsf { C }$
Storage Temperature: -40°C to 85°C

# 2.7 Humidity

$6 0 ^ { \circ } \mathsf { C }$ at 95% RH, non-condensing

# 2.8 Certificate (EMC)

CE/FCC Class B

# 2.9 Form Factor

ATX: 305 mm x 244 mm (W x L)

# 2.10 Operating Systems

Microsoft® Windows® 10, 64-bit
Microsoft® Windows® Server 2016, 64-bit
OpenSUSE Leap 15.1, 64-bit
Fedora 30, 64-bit
Ubuntu 18.10, 64 bit

# 2.11 Functional Block Diagram

One PCIe Gen3 x16 or Two PCIe Gen3 x8

![**Legend:**\n*   Blue square: Connectors on rear panel\n*   Grey square: Onboard Connectors/Pin Headers\n\n**Top Block: Xeon™ E or 8th/9th Gen Intel® Core™**\n*   **Left Connections:** Outputs to DP, HDMI, and VGA (via PTN3355BS).\n*   **Right Connections:** Outputs to Dual Channel and DDR4-2400/2666.\n*   **Down Connection:** Connects via DMI to the Intel® C246 Chipset.\n\n**Middle Block: Intel® C246 Chipset**\n*   **Up Connection:** Connects via DMI to the Xeon™ E or 8th/9th Gen Intel® Core™.\n*   **Left Connections (Inputs/Outputs):**\n    *   RJ45 (via I219LM, labeled LAN)\n    *   RJ45 (via I210AT, labeled PCIe x1)\n    *   SATA Gen3 x6\n    *   Three PCIe Gen3 x4\n    *   USB 3.1 Gen2 x4\n    *   USB 3.0 x3\n    *   USB 2.0 x7\n*   **Right Connections:**\n    *   ALC892 or ALC888S (to Line out/in, Mic in)\n    *   PCIe x1 (via IT8892E, to PCI 1-2)\n    *   SPI (to SPI ROM)\n    *   32-bit GPIO\n*   **Down Connection:** Connects via LPC to the NCT6106D.\n\n**Bottom Block: NCT6106D**\n*   **Up Connection:** Connects via LPC to the Intel® C246 Chipset.\n*   **Left Connections:** PS/2 KB/MS, RS-232/422/485 x2, RS-232 x4.\n*   **Right Connections:** SYS FAN x2, CPU FAN, Printer Port.](.imb-m45-50m-00067-1010/cd1471f662bfc1ac743e3f14ff031ab8d675567dee0a14f2bd0f50b0544e87bb.jpg)

Figure 1: Functional Block Diagram

# 3 Mechanical Layout

# 3.1 Connector Locations

![A\nD\nF\nH\nJ\nB C E G I K](.imb-m45-50m-00067-1010/ad1dfe2658bbd275b1f76d447b646f5e55a7122042d34a2c137c7d7e55e1d11d.jpg)

Figure 2: IO Panel Connector Locations

Table 1: IO Panel Connector Definitions

<table><tr><td colspan="2">IO Panel Connectors</td></tr><tr><td>Item</td><td>Description</td></tr><tr><td>A</td><td>VGA Port</td></tr><tr><td>B</td><td>HDMI Port</td></tr><tr><td>C</td><td>Display Port</td></tr><tr><td>D</td><td>COM1 RS-232/422/485, RI pin with Power Jumper Select</td></tr><tr><td>E</td><td>COM2 RS-232/422/485</td></tr><tr><td>F</td><td>LAN1</td></tr><tr><td>G</td><td>2x USB3.1 Gen2 port</td></tr><tr><td>H</td><td>LAN2</td></tr><tr><td>I</td><td>2x USB3.1 Gen2 port</td></tr><tr><td>J</td><td>Headphone out</td></tr><tr><td>K</td><td>Mic in</td></tr></table>

![C D E F G H I L\nAZ\nAY\nAX\nAW\nB\nBA\nA\nAD AE\nAF AG\nV AA W X Y Z AB\nAC\nM\nJ\nQ\nAS\nAJ\nN\nO\nP\nS\nT](.imb-m45-50m-00067-1010/9cc2a69523f244a7a8ef3d43108c78fe7d8ba233a76b61c5e0f5f1746fa06581.jpg)

Figure 3: Onboard Connector Locations

Table 2: Onboard Connector Definitions

<table><tr><td colspan="3">Onboard Connectors</td></tr><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>A</td><td>ATX POWER 8-pin</td><td>ATX12V1</td></tr><tr><td>B</td><td>CPU_FAN</td><td>CPU_FAN1</td></tr><tr><td>C</td><td>ATX POWER 24-pin</td><td>EATXPWR1</td></tr><tr><td>D</td><td>SATA12</td><td>SATA1 (TOP) and SATA2</td></tr><tr><td>E</td><td>SATA34</td><td>SATA3 (TOP) and SATA4</td></tr><tr><td>F</td><td>SATA56</td><td>SATA5 (TOP) and SATA6</td></tr><tr><td>G</td><td>SYS_FAN1</td><td>SYS_FAN1</td></tr><tr><td>H</td><td>USB1314</td><td>USB1314</td></tr><tr><td>I</td><td>USB1112</td><td>USB1112</td></tr><tr><td>J</td><td>USB910</td><td>USB910</td></tr><tr><td>K</td><td>USB2.0</td><td>USB8</td></tr><tr><td>L</td><td>Front Panel</td><td>F_PANEL1</td></tr><tr><td>M</td><td>USB3.0</td><td>USB7</td></tr><tr><td>N</td><td>COM6</td><td>COM6</td></tr><tr><td>O</td><td>COM5</td><td>COM5</td></tr><tr><td>P</td><td>COM4</td><td>COM4</td></tr><tr><td>Q</td><td>USB3.0 pin header</td><td>USB56</td></tr><tr><td>S</td><td>COM3</td><td>COM3</td></tr><tr><td>T</td><td>PRINT PORT</td><td>LPT1</td></tr><tr><td>U</td><td>GPIO</td><td>JDIO1</td></tr><tr><td>V</td><td>PEG1</td><td>PCIEx16_1</td></tr><tr><td>W</td><td>PEG2</td><td>PCIEx16_2</td></tr><tr><td>X</td><td>PCIEx4</td><td>PCIEx4_1</td></tr><tr><td>Y</td><td>PCIEx4</td><td>PCIEx4_2</td></tr><tr><td>Z</td><td>PCIEx4</td><td>PCIEx4_3</td></tr><tr><td>AA</td><td>PCI1</td><td>PCI1</td></tr><tr><td>AB</td><td>PCI2</td><td>PCI2</td></tr><tr><td>AC</td><td>FP_AUDIO1</td><td>AAFP1</td></tr><tr><td>AD</td><td>COM1 RS-232/422/485 select</td><td>JSETCOM1</td></tr><tr><td>AE</td><td>COM2 RS-232/422/485 select</td><td>JSETCOM2</td></tr><tr><td>AF</td><td>COM1 master/slave and terminal select</td><td>COM1_S1~4</td></tr><tr><td>AG</td><td>COM2 master/slave and terminal select</td><td>COM2_S1~4</td></tr><tr><td>AH</td><td>DIO no power/+5V/+12V select</td><td>JPW2</td></tr><tr><td>AI</td><td>SMBUS no power/+3.3V/+5V select</td><td>JPW1</td></tr><tr><td>AJ</td><td>I2C no power/+3.3V/+5V select</td><td>JPW3</td></tr><tr><td>AK</td><td>AT/ATX mode header</td><td>JPSON1</td></tr><tr><td>AL</td><td>Case open alarm</td><td>JCASE1</td></tr><tr><td>AS</td><td>I2C header</td><td>JI2C1</td></tr><tr><td>AT</td><td>SMBUS header</td><td>JSMB1</td></tr><tr><td>AU</td><td>Clear CMOS</td><td>JCMOS1</td></tr><tr><td>AV</td><td>KB/MS</td><td>KBMS1</td></tr><tr><td>AW</td><td>DIMM_A1</td><td>DIMM_A1</td></tr><tr><td>AX</td><td>DIMM_A2</td><td>DIMM_A2</td></tr><tr><td>AY</td><td>DIMM_B1</td><td>DIMM_B1</td></tr><tr><td>AZ</td><td>DIMM_B2</td><td>DIMM_B2</td></tr><tr><td>BA</td><td>SYS_FAN2</td><td>SYS_FAN2</td></tr></table>

# 3.2 Mechanical Dimensions

Top View
![| Dimension | Value |\n| --------- | ----- |\n| Top Left   | 243.84 |\n| Top Right  | 237.49 |\n| Bottom Left | 165.1 |\n| Bottom Right | 33.02 |\n| Bottom Center | 22.2 |\n| Bottom Right End | 61.05 |\n| Bottom Center End | 107.59 |\n| Bottom Right End End | 130.2 |\n| Bottom Center End End | 148.2 |\n| Bottom Right End End End | 163.83 |\n| Bottom Center End End End | 209.55 |\n| Bottom Right End End End | 288.29 |\n| Bottom Center End End End | 304.8 |](.imb-m45-50m-00067-1010/167c0dec4a0faa8cac80c1e9f419be76a9bdb3728e03579b051f3bc392a1c615.jpg)

Figure 4: Mechanical Dimensions

Side View
![31.54\nDimensions: mm](.imb-m45-50m-00067-1010/711ce6c5d9412e9d8d6d1c32efd06f97a15185f350f45234ce3453e33d2989e1.jpg)

Figure 5: Mechanical Dimensions - IO Panel

# 4 Connector Pinouts

See 3.1 Connector Locations on page 7 for connector locations.

# 4.1 Rear IO Connectors

# 4.1.1 HDMI

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDMI1_CON_DP2</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>HDMI1_CON_DN2</td><td>4</td><td>HDMI1_CON_DP1</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>HDMI1_CON_DN1</td></tr><tr><td>7</td><td>HDMI1_CON_DP0</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>HDMI1_CON_DN0</td><td>10</td><td>HDMI1_CON_CKP</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>HDMI1_CON_CKN</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>HDMI1_DDC_CLK</td><td>16</td><td>HDMI1_DDC_DATA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5V_HDMI</td></tr><tr><td>19</td><td>HDMI1_CON_HPD</td><td></td><td></td></tr></table>

![The image is a black-and-white line drawing of a connector housing, resembling a D-sub connector. It features two rows of rectangular shapes representing pins. Text labels are positioned around the pins:\n\n*   **Top Left:** '19 17'\n*   **Top Right:** '3 1'\n*   **Bottom Left:** '18'\n*   **Bottom Right:** '4 2'](.imb-m45-50m-00067-1010/570173fb57c6adbe9775a33d42f87c342002e74a4ef4001aada2fd472bc992ae.jpg)

# 4.1.2 Display Port

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CN_DDPx0+</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>CN_DDPx0-</td><td>4</td><td>CN_DDPx1+</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>CN_DDPx1-</td></tr><tr><td>7</td><td>CN_DDPx2+</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>CN_DDPx2-</td><td>10</td><td>CN_DDPx3+</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>CN_DDPx3-</td></tr><tr><td>13</td><td>CN_DDPx_AUX_SEL</td><td>14</td><td>CN_DDPx_CONFIG2</td></tr><tr><td>15</td><td>CN_DDPx_AUX+</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>CN_DDPx_AUX-</td><td>18</td><td>CN_DDPx_HPD</td></tr><tr><td>19</td><td>GND</td><td>20</td><td>+V3.3_DDPx_PWR_CN</td></tr></table>

![The image is a technical line drawing of an electrical connector housing. Inside the outer rectangular outline, there is a single row of smaller rectangular slots representing pin positions. The text '19' appears at the top left, '1' at the top right, '20' at the bottom left, and '2' at the bottom right. Small notches are visible on the top and bottom edges of the outer housing.](.imb-m45-50m-00067-1010/917b8fdb360556220ad2cafdef539740df08760cf8a005caeac9f201df8b9f5d.jpg)

# 4.1.3 VGA Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VGA_CON_RED</td><td>2</td><td>VGA_CON_GREEN</td></tr><tr><td>3</td><td>VGA_CON_BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>+5V_HDMI</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>VGA_DDCDAT</td></tr><tr><td>13</td><td>VGA_CON_HS</td><td>14</td><td>VGA_CON_VS</td></tr><tr><td>15</td><td>VGA_DDCCLK</td><td></td><td></td></tr></table>

![This image is a line drawing of a 15-pin D-sub connector (often used for VGA). It depicts a rectangular housing with two hexagonal mounting screws on the left and right sides. Inside the housing, there is a grid of 15 circular pins arranged in three rows of five.\n\nNumbers indicate the position of specific pins:\n*   **5** is located above the top-left pin.\n*   **1** is located above the top-right pin.\n*   **15** is located below the bottom-left pin.\n*   **11** is located below the bottom-right pin.](.imb-m45-50m-00067-1010/934529fd558342cf95c81d42520601a1d193cc22ebe8c5e4ebad330b84134c20.jpg)

# 4.1.4 USB Connectors

USB 3.1 Gen2, USB 3.0, USB 2.0

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5 VDC</td></tr><tr><td>2</td><td>USB D-</td></tr><tr><td>3</td><td>USB D+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![The image displays a schematic line drawing of a modular connector, likely an RJ45 jack.\n\n*   **Connector Housing:** A rounded rectangle represents the face of the connector. Inside, there are eight vertical parallel lines, representing the contact pins or slots.\n*   **Numbering:** Below the connector, the numbers **1**, **2**, **3**, and **4** are printed in a row.\n*   **Connections:** Thin lines connect each number to a specific contact slot:\n    *   The number **1** connects to the leftmost slot (pin 1).\n    *   The number **2** connects to the second slot from the left (pin 2).\n    *   The number **3** connects to the sixth slot from the left (pin 6).\n    *   The number **4** connects to the seventh slot from the left (pin 7).](.imb-m45-50m-00067-1010/ab12e62fbd87f053e2b69e453a6d195677414cb387791ab37c769ed9ed757aa7.jpg)

USB2.0

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>StdA_SSRX-</td></tr><tr><td>2</td><td>StdA_SSRX+</td></tr><tr><td>3</td><td>GND_DRAIN</td></tr><tr><td>4</td><td>StdA_SSTX-</td></tr><tr><td>5</td><td>StdA_SSTX+</td></tr><tr><td>6</td><td>VUSB</td></tr><tr><td>7</td><td>D-</td></tr><tr><td>8</td><td>D+</td></tr><tr><td>9</td><td>GND</td></tr></table>

![The image is a black and white line drawing featuring two rows of numbers separated by a central graphic.\n\nAt the top, the numbers **9 8 7 6 5** are arranged horizontally.\n\nBelow the numbers is a rectangular shape with a thick black border and a thinner rectangular outline inside it.\n\nAt the bottom, below the rectangular shape, are the numbers **1 2 3 4** arranged horizontally.](.imb-m45-50m-00067-1010/6cdb6d71d680ffb3fa054ca0b68e35c7bc32c85bf16907fb77373b026cacf98e.jpg)

USB 3.1 Gen2

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V_USB12</td></tr><tr><td>2</td><td>USB_CM_N1</td></tr><tr><td>3</td><td>USB_CM_P1</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3_RX_CM_N1</td></tr><tr><td>6</td><td>USB3_RX_CM_P1</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3_TX_CM_N1</td></tr><tr><td>9</td><td>USB3_TX_CM_P1</td></tr></table>

![The image displays the numbers '9 8 7 6 5' arranged horizontally at the top. Below these numbers is a large rectangular frame. Inside the upper part of this frame is a smaller, thinner rectangular outline. At the bottom of the large frame, the numbers '1 2 3 4' are arranged horizontally.](.imb-m45-50m-00067-1010/680f3609dd870169cf11dda8116fda56bcd49ecf6dcc9037baae5ef8e111bba8.jpg)
USB3.0

# 4.1.5 COM 1-2 Connector Stack (Top connector COM1, Bottom connector COM2)

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>Tx-</td><td>Tx/Rx-</td></tr><tr><td>2</td><td>RxD</td><td>Tx+</td><td>Tx/Rx+</td></tr><tr><td>3</td><td>TxD</td><td>Rx+</td><td>N/A</td></tr><tr><td>4</td><td>DTR#</td><td>Rx-</td><td>N/A</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>DSR#</td><td>N/A</td><td>N/A</td></tr><tr><td>7</td><td>RTS#</td><td>N/A</td><td>N/A</td></tr><tr><td>8</td><td>CTS#</td><td>N/A</td><td>N/A</td></tr><tr><td>9</td><td>RI#</td><td>N/A</td><td>N/A</td></tr></table>

![The image displays a schematic line drawing of a D-sub connector, specifically a DB-9 type. Two hexagonal mounting screws are positioned on the far left and right sides. In the center is the connector housing, a rounded rectangle containing two rows of circular pin holes: an upper row of five and a lower row of four. The number **1** is located above the leftmost hole of the top row, and **5** is above the rightmost hole of the top row. Similarly, **6** is located below the leftmost hole of the bottom row, and **9** is below the rightmost hole of the bottom row.](.imb-m45-50m-00067-1010/397e43335bcae6ea4301dbf3337970592b7d517d4de72ff74337d0eecbc59bee.jpg)

# 4.1.6 Ethernet Connectors (LAN1, LAN2)

Dual 10/100/1000Mbit/s LAN Ethernet controllers based on Intel® i219LM/i210AT, support PXE and WOL over both LANs.In BIOS menu only LAN 1 have wake on LAN option

<table><tr><td>Pin</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_MDI0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_MDI0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_MDI1+</td></tr><tr><td>4</td><td>--</td><td>LAN_MDI2+</td></tr><tr><td>5</td><td>--</td><td>LAN_MDI2-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_MDI1-</td></tr><tr><td>7</td><td>--</td><td>LAN_MDI3+</td></tr><tr><td>8</td><td>--</td><td>LAN_MDI3-</td></tr></table>

![The image displays a schematic diagram of an RJ45 connector. At the top, the text 'LED1' is on the left and 'LED2' is on the right. Below these labels, inside the upper portion of a rectangular outline, are two small rectangles. In the center is a gray shape representing the connector housing. At the bottom, the number '8' is on the left and '1' is on the right, with thin lines extending downwards from the bottom of the central shape towards these numbers.](.imb-m45-50m-00067-1010/27ff4d3b361dab7483d779f10f15401d93e969332ca08c3e0ace12017c7aa624.jpg)

<table><tr><td colspan="2">LED1 (Speed)</td><td colspan="2">LED2 (Link/Activity)</td></tr><tr><td>Status</td><td>Description</td><td>Status</td><td>Description</td></tr><tr><td>Off</td><td>10 Mb connection</td><td>Off</td><td>No Link</td></tr><tr><td>Green</td><td>100 Mb connection</td><td>Green</td><td>Linked</td></tr><tr><td>Orange</td><td>1 Gb connection</td><td>Blinking</td><td>Data Activity</td></tr></table>

# 4.2 Internal Connectors

# 4.2.1 PS2 Combo connector

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>KB_DAT</td></tr><tr><td>2</td><td>KB_CLK</td></tr><tr><td>3</td><td>MS_DAT</td></tr><tr><td>4</td><td>MS_CLK</td></tr><tr><td>5</td><td>+5V_DUAL</td></tr><tr><td>6</td><td>GND</td></tr></table>

![The image displays the number 2 at the top left and the number 1 at the bottom left. To the left of a rectangular box, aligned with the bottom row, is the letter p. Inside the box is a grid of two rows and four columns containing symbols. The top row consists of four circles with a central dot. The bottom row consists of a square with a central dot followed by three circles with a central dot.](.imb-m45-50m-00067-1010/22cca9afd12eae8d2e37c24e1afe9c11690a6ab54d514e6374b6b48b782b2aec.jpg)

# 4.2.2 USB5,6

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5 VDC</td><td>2</td><td>Port1_RX-</td></tr><tr><td>3</td><td>Port1_RX+</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>Port1_TX-</td><td>6</td><td>Port1_TX+</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>Port1_D -</td></tr><tr><td>9</td><td>Port1_D +</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>Port2_D +</td><td>12</td><td>Port2_D -</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>Port2_TX+</td></tr><tr><td>15</td><td>Port2_TX-</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>Port2_RX+</td><td>18</td><td>Port2_RX-</td></tr><tr><td>19</td><td>+5 VDC</td><td>20</td><td>KEY (no pin)</td></tr></table>

![The image displays a technical line drawing of a vertical rectangular electronic component, likely an integrated circuit or connector package.\n\n- **Structure:** The component is defined by a double-lined rectangular outline (an outer boundary and a concentric inner boundary).\n- **Internal Elements:** Inside the inner rectangle, there are 20 small squares arranged in two vertical columns of 10 squares each.\n- **Side Features:** On the left and right sides of the inner rectangle, there are small rectangular shapes attached to the sides. There are three such shapes on the left and three on the right, positioned near the top, middle, and bottom sections.\n- **Text/Labels:** At the bottom, the number '**1**' is positioned near the bottom-left corner, and the number '**20**' is positioned near the bottom-right corner, indicating pin numbering.](.imb-m45-50m-00067-1010/f043c76dba98e02051120b74609cb7c5353880d2576fa38db6fdd66e498965bb.jpg)

# 4.2.3 USB 9,10, USB11,12, USB13,14

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VDC</td><td>2</td><td>VDC</td></tr><tr><td>3</td><td>D5 -</td><td>4</td><td>D6 -</td></tr><tr><td>5</td><td>D5 +</td><td>6</td><td>D6 +</td></tr><tr><td>7</td><td>Ground</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>KEY (no pin)</td><td>10</td><td>No Connect/ OC</td></tr></table>

![The image displays a line drawing of a rectangular connector or socket with a notch on its left side. Inside the rectangle, there are ten small shapes arranged in two columns: the left column contains a square at the top followed by four circles, and the right column contains five circles. Numerical labels are visible: the number '1' is to the left of the square, '2' is to the right of the top-right circle, and '10' is to the right of the bottom-right circle.](.imb-m45-50m-00067-1010/441c6eef5db9e9383fe4411d16b7885c863723eb30e1b4d05c9d81a317805706.jpg)

# 4.2.4 SATA1, SATA2, SATA3, SATA4, SATA5, SATA6

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>TXP</td><td>Transmit diff data – positive</td></tr><tr><td>3</td><td>TXN</td><td>Transmit diff data – negative</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr><tr><td>5</td><td>RXN</td><td>Receive diff data – negative</td></tr><tr><td>6</td><td>RXP</td><td>Receive diff data – positive</td></tr><tr><td>7</td><td>GND</td><td>Ground</td></tr></table>

![The image is a black and white technical line drawing of a vertical rectangular slot or connector. Inside the outer rectangular frame, there is a smaller, elongated vertical rectangle containing a central column of alternating black and white squares. The outer frame features L-shaped cutouts or notches at the top and bottom. To the right of the diagram, the number '1' is positioned near the top section, and the number '7' is positioned near the bottom section.](.imb-m45-50m-00067-1010/b7b91a140a592cf6e3dd6eefdc790ac67bd1d05177f7ebc0d5955bb2b701ae88.jpg)

# 4.2.5 COM3, COM4, COM5, COM6

Serial Port is over-current protected.

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DCD#</td><td>Data Carrier Detect</td><td>2</td><td>DSR#</td><td>Data Set Ready</td></tr><tr><td>3</td><td>RXD</td><td>Receive Data</td><td>4</td><td>RTS#</td><td>Request To Send</td></tr><tr><td>5</td><td>TXD#</td><td>Transmit Data</td><td>6</td><td>CTS#</td><td>Clear To Send</td></tr><tr><td>7</td><td>DTR#</td><td>Data Terminal Ready</td><td>8</td><td>RI#</td><td>Ring Indicator</td></tr><tr><td>9</td><td>GND</td><td>GND</td><td>10</td><td>KEY</td><td>No Pin</td></tr></table>

![1\n2\n9](.imb-m45-50m-00067-1010/eca477fb84fc4da51a21926cf2385fdf1c2152be884fd8cb408c0c732224e311.jpg)

# 4.2.6 LPT1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>STB#</td><td>2</td><td>AFD#</td></tr><tr><td>3</td><td>DATA0</td><td>4</td><td>ERR#</td></tr><tr><td>5</td><td>DATA1</td><td>6</td><td>INIT#</td></tr><tr><td>7</td><td>DATA2</td><td>8</td><td>SLIN#</td></tr><tr><td>9</td><td>DATA3</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>DATA4</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>DATA5</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>DATA6</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>DATA7</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>ACK#</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>BUSY</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>PE</td><td>24</td><td>GND</td></tr><tr><td>25</td><td>SLCT</td><td>26</td><td>NC</td></tr></table>

![1\n2\n25\n26](.imb-m45-50m-00067-1010/23b942c144a976ee538a6ce3658141b2961317d5af51c405092b1889f1cb1a2a.jpg)

# 4.2.7 FP\_AUDIO1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>[Port 2] SENSE_RETURN_B</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>Line-In Port2 Left</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>Line-In Port2 Right</td><td>6</td><td>GND_A</td></tr><tr><td>7</td><td>MIC-In Port2 Left</td><td>8</td><td>SIDE OUT Right</td></tr><tr><td>9</td><td>MIC-In Port2 Right</td><td>10</td><td>SIDE OUT Left</td></tr></table>

![The image displays a vertical, rectangular control panel set against a black background. The panel features a grid of buttons arranged in two columns and five rows, totaling ten buttons. Below this grid, there is a single, centered button. Each button is black with a white icon consisting of a square outline containing a circle. To the left of the panel is the number '2', and to the right is the number '1'.](.imb-m45-50m-00067-1010/2e122617649bd9da92cbecdb6defc9796a3349ae798c3678c09ad355c716b19d.jpg)

# 4.2.8 JCASE1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>SIO_CASEOPEN#</td><td>Case open signal</td></tr></table>

![A vertical rectangular outline contains three circular icons stacked vertically. The top icon is a ring. The middle icon is a solid black circle. The bottom icon is a ring with a small black square inside. To the right of the bottom icon is a small right-pointing triangle. To the right of the rectangle is the number 1.](.imb-m45-50m-00067-1010/1905bd817fbcf2b25803ebcf6712da62bcaccbb60e6cc1063d8f48774729df44.jpg)

# 4.2.9 CPU\_FAN1, SYS\_FAN1, SYS\_FAN2

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>+12 V</td><td>FAN Power</td></tr><tr><td>3</td><td>Tach</td><td>FAN Tachometer</td></tr><tr><td>4</td><td>PWM</td><td>FAN PWM</td></tr></table>

![The image displays a simple black and white schematic diagram.\n- In the top left corner, the number '**1**' is visible.\n- In the center, there is a tall vertical rectangle. Inside this rectangle, a column of shapes is arranged vertically: a square at the top, followed by three circles spaced below it.\n- To the right of the rectangle, near the top, is the number '**5**'.\n- Near the bottom right corner, outside the rectangle, there is a single circle with the number '**4**' positioned below it.](.imb-m45-50m-00067-1010/de6685b9fd74773e160ff90c686d511efcf555e5dd3d390c88791d48e465dfe0.jpg)

The fan header supports +12 V at 1 A maximum

# 4.2.10 F\_PANEL1

<table><tr><td>Pin</td><td>Signal</td><td>In/Out</td><td>Description</td><td>Pin</td><td>Signal</td><td>In/Out</td><td>Description</td></tr><tr><td colspan="4">HDD Activity LED</td><td colspan="4">Power LED</td></tr><tr><td>1</td><td>HDD_LED+</td><td>Out</td><td>Hard disk LED pull-up to +3.3 V</td><td>2</td><td>PLED_PWR</td><td>Out</td><td>Power LED pull-up to +3.3_DUAL</td></tr><tr><td>3</td><td>HDD_LED#</td><td>Out</td><td>Hard disk active LED</td><td>4</td><td>SUPLED</td><td>Out</td><td>Front panel active LED</td></tr><tr><td>5</td><td>Ground</td><td></td><td>Ground</td><td>6</td><td>PANSWIN#</td><td>In</td><td>Power switch</td></tr><tr><td>7</td><td>FP_RESET#</td><td>In</td><td>Reset switch</td><td>8</td><td>Ground</td><td></td><td>Ground</td></tr><tr><td>9</td><td>NC</td><td></td><td></td><td>10</td><td>NC</td><td></td><td></td></tr></table>

2

![The image displays a line drawing of a rectangular control panel or keypad. Inside the main rectangular border, there are two rows of buttons arranged horizontally. The top row consists of eight identical circular buttons. The bottom row features a square-shaped button containing a circle on the far left, followed by seven identical circular buttons. On the left exterior edge of the rectangle, there is a small triangle pointing to the right.](.imb-m45-50m-00067-1010/b947209a9bb91ebd03905d0fb695e8f487c4e139947a2261914da6bb94750283.jpg)

1

4.2.11 EATXPWR1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3 V</td><td>13</td><td>+3.3 V</td></tr><tr><td>2</td><td>+3.3 V</td><td>14</td><td>-12 V</td></tr><tr><td>3</td><td>Ground</td><td>15</td><td>Ground</td></tr><tr><td>4</td><td>+5 V</td><td>16</td><td>PS-ON# (power supply remote on/off)</td></tr><tr><td>5</td><td>Ground</td><td>17</td><td>Ground</td></tr><tr><td>6</td><td>+5 V</td><td>18</td><td>Ground</td></tr><tr><td>7</td><td>Ground</td><td>19</td><td>Ground</td></tr><tr><td>8</td><td>PWRGD (Power Good)</td><td>20</td><td>No connect</td></tr><tr><td>9</td><td>+5 V (Standby)</td><td>21</td><td>+5 V</td></tr><tr><td>10</td><td>+12 V</td><td>22</td><td>+5 V</td></tr><tr><td>11</td><td>+12 V</td><td>23</td><td>+5 V</td></tr><tr><td>12</td><td>3.3V</td><td>24</td><td>Ground</td></tr></table>

![12\n24\n1 ▶\n13](.imb-m45-50m-00067-1010/402c6e54582bd16b095878585b0893b8df9cb59e9d2363a5800b2dd0271e8098.jpg)

4.2.12 ATX12V1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>Ground</td><td>5</td><td>+12V</td></tr><tr><td>2</td><td>Ground</td><td>6</td><td>+12V</td></tr><tr><td>3</td><td>Ground</td><td>7</td><td>+12V</td></tr><tr><td>4</td><td>Ground</td><td>8</td><td>+12V</td></tr></table>

![The image displays a schematic diagram of a connector, resembling a DB-9 serial port. It features a vertical rectangle with a small rectangular protrusion on its right side. Inside the rectangle are ten circular shapes arranged in two columns of five rows; the bottom-left shape is a square instead of a circle. To the left of the rectangle, the number '2' appears above the number '1', and next to '1' is a small arrow pointing to the left. To the right of the rectangle, near the bottom, is the number '5'.](.imb-m45-50m-00067-1010/5fc08fb06619ad2c49114b366724f9a3375cc5ecfb7817e4975eb7de94cd418f.jpg)

4.2.13 JLPC1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>VCC3</td></tr><tr><td>3</td><td>LPC_AD3</td><td>4</td><td>PLTRST</td></tr><tr><td>5</td><td>LPC_AD1</td><td>6</td><td>LPC_AD2</td></tr><tr><td>7</td><td>LPC_FRAME#</td><td>8</td><td>LPC_AD0</td></tr><tr><td>9</td><td>KEY</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>CLK33M</td><td>12</td><td>GND</td></tr></table>

![The image displays a black vertical rectangular shape resembling a ladder, featuring a column of horizontal white cutouts. At the bottom, the number '2' is visible on the left side and the number '1' is on the right side against a white background.](.imb-m45-50m-00067-1010/36d8fe2142d585965be1f60798ada448acb7be881a5da64edbdb91dad7e9ab61.jpg)

# 4.2.14 SPI1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC3</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>SPI_CS#</td><td>4</td><td>SPI_CLK</td></tr><tr><td>5</td><td>SPI_MISO</td><td>6</td><td>SPI_MOSI</td></tr><tr><td>7</td><td>HOLD#</td><td>8</td><td>Key</td></tr></table>

![The image displays a close-up of a black and white domino tile. The left side features five vertical pips, and the right side features five pips arranged in a standard pattern. Below the tile, the numbers '2', '4', and '1' are visible.](.imb-m45-50m-00067-1010/e9138de44a0a1e490554a276ad55fb097b1eb4dd4d315af42065b752d2533282.jpg)

# 4.2.15 JPSON1 (Default 2-3)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>PANSWIN#</td><td>Power switch signal</td></tr><tr><td>2</td><td>PSON_AT</td><td>AT mode signal</td></tr><tr><td>3</td><td>GND</td><td></td></tr></table>

![The image displays a rectangular box containing a solid black triangle pointing right, followed by a square outline and two circle outlines. Below the box is a horizontal line and the number 1.](.imb-m45-50m-00067-1010/f0330e9f54200a3d8a1c74da8d691018d0cf15e0c6694c9ebff75cac08273bd6.jpg)

# 4.2.16 JDIO1 (TTL High:3.3V / TTL Low:0V)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DIO1</td><td>2</td><td>DIO17</td></tr><tr><td>3</td><td>DIO2</td><td>4</td><td>DIO18</td></tr><tr><td>5</td><td>DIO3</td><td>6</td><td>DIO19</td></tr><tr><td>7</td><td>DIO4</td><td>8</td><td>DIO20</td></tr><tr><td>9</td><td>DIO5</td><td>10</td><td>DIO21</td></tr><tr><td>11</td><td>DIO6</td><td>12</td><td>DIO22</td></tr><tr><td>13</td><td>DIO7</td><td>14</td><td>DIO23</td></tr><tr><td>15</td><td>DIO8</td><td>16</td><td>DIO24</td></tr><tr><td>17</td><td>DIO9</td><td>18</td><td>DIO25</td></tr><tr><td>19</td><td>DIO10</td><td>20</td><td>DIO26</td></tr><tr><td>21</td><td>DIO11</td><td>22</td><td>DIO27</td></tr><tr><td>23</td><td>DIO12</td><td>24</td><td>DIO28</td></tr><tr><td>25</td><td>DIO13</td><td>26</td><td>DIO29</td></tr><tr><td>27</td><td>DIO14</td><td>28</td><td>DIO30</td></tr><tr><td>29</td><td>DIO15</td><td>30</td><td>DIO31</td></tr><tr><td>31</td><td>DIO16</td><td>32</td><td>DIO32</td></tr><tr><td>33</td><td>NC</td><td>34</td><td>NC</td></tr><tr><td>35</td><td>NC</td><td>36</td><td>NC</td></tr><tr><td>37</td><td>NC</td><td>38</td><td>NC</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>POWER</td></tr></table>

![1\n2\n39\n40](.imb-m45-50m-00067-1010/6d5ebc280f931955579b4b369691c21b5da8da21d7857dbf3bc8bae6892dba1e.jpg)

# 4.2.17 JSETCOM1, JSETCOM2

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>UART1_RXD</td><td>2</td><td>COM1_RXD485</td></tr><tr><td>3</td><td>UART1_RXD</td><td>4</td><td>COM1_RXD422</td></tr><tr><td>5</td><td>UART1_RXD</td><td>6</td><td>COM1_RXD232</td></tr><tr><td>7</td><td>COM1_DCD#</td><td>8</td><td>COM1_TX</td></tr><tr><td>9</td><td>COM1_CN_DCD#</td><td>10</td><td>COM1_CN_TX</td></tr><tr><td>11</td><td>TXD485#1</td><td>12</td><td>RXD485P1</td></tr><tr><td>13</td><td>COM1_RX</td><td>14</td><td>COM1_DTR#</td></tr><tr><td>15</td><td>COM1_CN_RX</td><td>16</td><td>COM1_CN_DTR#</td></tr><tr><td>17</td><td>TXD485P1</td><td>18</td><td>RXD485#1</td></tr></table>

![The image displays a schematic diagram of an integrated circuit pinout. It features a rectangular outline with two rows of oval shapes representing the pins. The number '2' is located at the top left. The number '18' is at the top right. The number '1' is at the bottom left, accompanied by a small triangle indicator. The number '17' is located at the bottom right.](.imb-m45-50m-00067-1010/c80bc7e898fef4ec6b773071c405f6796c4bc8b48ad8f9707cf45080f0cc956c.jpg)

# 4.2.18 JCMOS1 (Default 1-2)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td></td></tr><tr><td>2</td><td>RTCRST#</td><td>Reset CMOS</td></tr><tr><td>3</td><td>GND</td><td></td></tr></table>

![The image displays the number 1 in black on the left. To the right is a vertical rectangular shape with rounded corners, resembling a traffic signal housing. Inside the rectangle, there are three vertically stacked elements. The top element is a square containing a downward-pointing triangle. The middle element is a circle. The bottom element is a circle. Additionally, there is a small downward-pointing triangle just above the top edge of the rectangle.](.imb-m45-50m-00067-1010/a7e6b2f3f7be7f3a7abd228096db702efb5705e1aaf4bd357b726a98f7e83367.jpg)

# 4.2.19 JPW2 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>JDIO1. Pin40</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JDIO1. Pin40</td></tr><tr><td>5</td><td>+12V</td><td>6</td><td>JDIO1. Pin40</td></tr></table>

![The image displays the number **1** on the left and the number **2** on the right. In the center is a vertical rectangular block resembling a domino tile. The top half of the tile contains a single square pip. The bottom half contains six circular pips arranged in two columns of three. A small black triangle points downward just above the top edge of the domino tile.](.imb-m45-50m-00067-1010/7bd35c19197e4b5bfffa37bd493cd82e63866fdcf8ebb0f3485f15f86bc8d2ab.jpg)

# 4.2.20 JPW3 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>JI2C1 Pin1</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JI2C1 Pin1</td></tr><tr><td>5</td><td>+3.3V</td><td>6</td><td>JI2C1 Pin1</td></tr></table>

![The image features the number 1 on the left, a vertical die face displaying six pips arranged in two columns of three in the center, and the number 2 on the right. A small crown symbol is visible at the very top of the die.](.imb-m45-50m-00067-1010/351e1298f1bc266439a2a259409162cf5b0d52f7298b828debccbd1065c53d58.jpg)

# 4.2.21 JPW1 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V_DUAL</td><td>2</td><td>JSMB1 Pin1</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JSMB1 Pin1</td></tr><tr><td>5</td><td>+3.3V_DUAL</td><td>6</td><td>JSMB1 Pin1</td></tr></table>

![The image displays the number 1 on the left, a vertical battery illustration in the center, and the number 2 on the right. The battery is a black outline containing two vertical columns of four black circles each, with a small terminal nub at the top.](.imb-m45-50m-00067-1010/3c221031e50520455d00169c5bb0211b76aaf46c9f549ec5fc90122049e5f1e7.jpg)

# 4.2.22 JSMB1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>NC/+3.3V/+5V select</td></tr><tr><td>2</td><td>SMB_DATA</td><td>SMBUS data</td></tr><tr><td>3</td><td>SMB_CLK</td><td>SMBUS clock</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr></table>

![The image displays the number '1' in the top left corner. Below it is a horizontal rectangular box containing a square followed by four circles. A small triangle points to the left side of the box.](.imb-m45-50m-00067-1010/1e76106caedcdb4387c377dae3f3e208f016312ca96164392d022f17a2044262.jpg)

# 4.2.23 JI2C1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>NC/+3.3V/+5V select</td></tr><tr><td>2</td><td>I2C_DATA</td><td>I2C data</td></tr><tr><td>3</td><td>I2C_CLK</td><td>I2C clock</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr></table>

![The image displays the number '1' centered at the top. Below it is a thick black horizontal bar. Underneath the bar is a white rectangular box containing four icons arranged horizontally. The first icon is a square with a circle inside, followed by three circles. To the left of the white box is a small black triangle pointing to the right.](.imb-m45-50m-00067-1010/3e49dd37d91354e3cf22a97724fa0b9ab981e308d2376f5fca3f1f992d2e8506.jpg)

# 4.3 Jumper and Switch Settings

Table 3: Jumper and Switch Definitions

<table><tr><td colspan="3">Jumper Block</td></tr><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>JCMOS1</td><td>One 1x3 2.54mm pin header1-2 (default) = Normal, 2-3 = Clear CMOS</td><td>Normal (Default)&lt;img src="images/27f14d4da1b21a76bb8c617cd1546c1df6b4e249a82a88f7333129f7792ec32f.jpg"/&gt;Clear CMOS&lt;img src="images/53d92b1e4742dff8621a3883553563e88134d296bd0c268dc42f78908909b813.jpg"/&gt;</td></tr><tr><td>JPSON1</td><td>One 1x3 2.54mm pin header1-2 = AT Mode; 2-3 (default) = ATX mode</td><td>&lt;img src="images/b485cdebf8bef495a7feb89069c05bf84ebd0ab5466837bb309f9810f87823ca.jpg"/&gt;1A&lt;img src="images/87bef5cb914ee06ae9fb539a11c0f220053aa1e8b2aa49ba63b27d1d6f79ee42.jpg"/&gt;1</td></tr><tr><td>JSETCOM1JSETCOM2</td><td>One 2x9 2.0mm pin headerRS232: 5-6, 7-9, 8-10, 13-15, 14-16 (default)RS422: 3-4, 9-11, 10-12, 15-17, 16-18RS485: 1-2, 9-11, 10-12, 15-17, 16-18</td><td>1357&lt;img src="images/924a1da887cdbf6cb1ed13f36d284bc6cc1920bb49ff2e3498f8cb16342d4308.jpg"/&gt;911131517</td></tr></table>

<table><tr><td colspan="7">Jumper Block</td></tr><tr><td rowspan="4">COM1_S1~S4 master/slave and terminal selection</td><td></td><td>S1</td><td>S2</td><td>S3</td><td>S4</td><td rowspan="4">(Default)&lt;img src="images/6100dca40b0a10386313a2bb3514857b676ce85239f880d9d511db3e851f1a91.jpg"/&gt;</td></tr><tr><td>RS-232</td><td>2-3</td><td>2-3</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-485</td><td>1-2</td><td>1-2</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-422</td><td>1-2</td><td>1-2</td><td>1-2</td><td>1-2</td></tr><tr><td rowspan="4">COM2_S1~S4 master/slave and terminal selection</td><td></td><td>S1</td><td>S2</td><td>S3</td><td>S4</td><td rowspan="4">(Default)&lt;img src="images/a2b3defd59d21578ffdf7f4799df1b99d0037882d86acfa23233fd205ace4373.jpg"/&gt;</td></tr><tr><td>RS-232</td><td>2-3</td><td>2-3</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-485</td><td>1-2</td><td>1-2</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-422</td><td>1-2</td><td>1-2</td><td>1-2</td><td>1-2</td></tr></table>

<table><tr><td colspan="3">Jumper Block</td></tr><tr><td>JPW2</td><td>One 2x3 2.0mm pin headerNC (default)/+5V/+12V</td><td>NC (Default)1 2&lt;img src="images/74007433aa0da6f1762bc2b0092c98cee549eb957051e6f1401f9860c93f5a1c.jpg"/&gt;+5V1 2&lt;img src="images/a24342c9d396cfeb4535ea23394783f9b5b602d3769ce94f3b2ed3c5a1d164a7.jpg"/&gt;+12V1 2&lt;img src="images/e21ae5144879a29ba3430e39590cac43795fd055ca83f165b8b2a0554d08b066.jpg"/&gt;</td></tr><tr><td>JPW1</td><td>One 2X3 2.0mm pin headerNC (default)/+5V/+3.3V</td><td>NC (Default)1 2&lt;img src="images/f991bb5600dfacc710e8737b686c3348315a849ab20e6b87f7d3a467c35131fe.jpg"/&gt;+5V1 2&lt;img src="images/eef6e721aa0f716a981174d7415a3262aabe733e4d7f7fe1f6bec051a7750775.jpg"/&gt;+3.3V1 2&lt;img src="images/ef57240ad4895d927507344aec4d0876a1606cfc7f018c902a5acbbbf16d67ee.jpg"/&gt;</td></tr><tr><td>JPW3</td><td>One 2x3 2.0mm pin headerNC (default)/+5V/+3.3V</td><td>NC (Default)1 2&lt;img src="images/574e1bc0378237191daec27bfa9e1410f5ef977e56382d40cf040197dbac739f.jpg"/&gt;+5V1 2&lt;img src="images/72ba5d555c8c97df1f7ff6867307b154f74e3d9542f586d49d387ace76fbc0fd.jpg"/&gt;+3.3V1 2&lt;img src="images/3de5559535e9a60d3b6671a994d2b5090deb3b256f5d49ed76cca53435d80826.jpg"/&gt;</td></tr></table>

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# 5 Driver Installation

Download the requisite drivers for your system from the IMB-M45 product page at:

https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/ATXMotherboards/IMB-M45

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# 6 System Resources

# 6.1 System Memory Map

Table 4: System Memory Map

<table><tr><td>Address Range</td><td>Address Range</td><td>Size</td><td>Description</td></tr><tr><td>(4GB-2MB)</td><td>FFE00000 – FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB-18MB) – (4GB-17MB-1)</td><td>FEE00000 – FEEFFFFF</td><td>1 MB</td><td>MSI Interrupts</td></tr><tr><td>(4GB-20MB) – (4GB-19MB-1)</td><td>FEC00000 – FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB – 16MB</td><td>F00000 – FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>1MB -15MB</td><td>100000 - EFFFFF</td><td>14MB</td><td>Main Memory</td></tr><tr><td>0K –1MB</td><td>00000 – FFFFFFF</td><td>1MB</td><td>DOS Compatibility Memory</td></tr></table>

# 6.2 I/O Map

Table 5: IO Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>0000-0CF7</td><td>PCI Express Root Complex</td></tr><tr><td>0D00-FFFF</td><td>PCI Express Root Complex</td></tr><tr><td>0020-0021</td><td>Programmable interrupt controller</td></tr><tr><td>0024-0025</td><td>Programmable interrupt controller</td></tr><tr><td>0028-0029</td><td>Programmable interrupt controller</td></tr><tr><td>002C-002D</td><td>Programmable interrupt controller</td></tr><tr><td>0030-0031</td><td>Programmable interrupt controller</td></tr><tr><td>0034-0035</td><td>Programmable interrupt controller</td></tr><tr><td>0038-0039</td><td>Programmable interrupt controller</td></tr><tr><td>003C-003D</td><td>Programmable interrupt controller</td></tr><tr><td>00A0-00A1</td><td>Programmable interrupt controller</td></tr><tr><td>00A4-00A5</td><td>Programmable interrupt controller</td></tr><tr><td>00A8-00A9</td><td>Programmable interrupt controller</td></tr><tr><td>00AC-00AD</td><td>Programmable interrupt controller</td></tr><tr><td>00B0-00B1</td><td>Programmable interrupt controller</td></tr><tr><td>00B4-00B5</td><td>Programmable interrupt controller</td></tr><tr><td>00B8-00B9</td><td>Programmable interrupt controller</td></tr><tr><td>00BC-00BD</td><td>Programmable interrupt controller</td></tr><tr><td>04D0-04D1</td><td>Programmable interrupt controller</td></tr><tr><td>04D0-04D1</td><td>Programmable interrupt controller</td></tr><tr><td>002E-002F</td><td>Motherboard resources</td></tr><tr><td>004E-004F</td><td>Motherboard resources</td></tr><tr><td>0061-0061</td><td>Motherboard resources</td></tr><tr><td>0063-0063</td><td>Motherboard resources</td></tr><tr><td>0065-0065</td><td>Motherboard resources</td></tr><tr><td>0067-0067</td><td>Motherboard resources</td></tr><tr><td>0070-0070</td><td>Motherboard resources</td></tr><tr><td>0080-0080</td><td>Motherboard resources</td></tr><tr><td>0092-0092</td><td>Motherboard resources</td></tr><tr><td>00B2-00B3</td><td>Motherboard resources</td></tr><tr><td>0680-069F</td><td>Motherboard resources</td></tr><tr><td>FFFF-FFFF</td><td>Motherboard resources</td></tr><tr><td>1800-18FE</td><td>Motherboard resources</td></tr><tr><td>164E-164F</td><td>Motherboard resources</td></tr><tr><td>0040-0043</td><td>System timer</td></tr><tr><td>0050-0053</td><td>System timer</td></tr><tr><td>0070-0077</td><td>System CMOS/real time clock</td></tr><tr><td>00F0-00F0</td><td>Numeric data processor</td></tr><tr><td>02E0-02E7</td><td>COM5</td></tr><tr><td>02E8-02EF</td><td>COM4</td></tr><tr><td>02F8-02FF</td><td>COM2</td></tr><tr><td>0378-037F</td><td>Printer Port</td></tr><tr><td>03E0-03E7</td><td>COM6</td></tr><tr><td>03E8-03EF</td><td>COM3</td></tr><tr><td>03F8-03FF</td><td>COM1</td></tr><tr><td>E000-EFFF</td><td>Chipset PCI Express Root Port</td></tr><tr><td>E000-EFFF</td><td>PCI-to-PCI Bridge</td></tr><tr><td>F000-F03F</td><td>Intel HD Graphic 630</td></tr><tr><td>F040-F05F</td><td>SMBUS</td></tr><tr><td>F090-F097</td><td>Standard SATA AHCI Controller</td></tr><tr><td>F080-F083</td><td>Standard SATA AHCI Controller</td></tr><tr><td>F060-F07F</td><td>Standard SATA AHCI Controller</td></tr></table>

# 6.3 Interrupt Request (IRQ) Lines

# 6.3.1 IRQ Lines PIC Mode

Table 6: IRQ Lines PIC Mode

<table><tr><td>IRQ#</td><td>Device</td></tr><tr><td>0</td><td>System timer</td></tr><tr><td>3</td><td>COM2</td></tr><tr><td>4</td><td>COM1</td></tr><tr><td>5</td><td>COM3, COM4</td></tr><tr><td>8</td><td>System CMOS/real time clock</td></tr><tr><td>10</td><td>COM5, COM6</td></tr><tr><td>13</td><td>Numeric data processor</td></tr><tr><td>14</td><td>Intel Serial IO GPIO Host Controller</td></tr><tr><td>15</td><td>Intel Chipset Smbus</td></tr><tr><td>16</td><td>HD Audio Controller</td></tr></table>

Note: These IRQs can be used for PCI devices when onboard device is disabled.

# 6.3.2 IRQ Lines APIC Mode

Table 7 IRQ Lines APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>System Counter</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>2</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port3 (COM3)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port4 (COM4)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>7</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>10</td><td>Serial Port5 (COM5)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>10</td><td>Serial Port6 (COM6)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Intel IO GPIO Host Controller</td><td>N/A</td><td>Note (1)</td></tr><tr><td>16</td><td>High Definition Audio Controller</td><td>N/A</td><td></td></tr><tr><td>54-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Note (1)</td></tr></table>

Note: These IRQs can be used for PCI devices when onboard device is disabled.

# 6.4 PCI Features

# 6.4.1 PCI Configuration Space Map

Table 8 PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel VGA Controller</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>Intel USB 3.0 XHCI</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>Intel Data acquisition/signal process</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel Communication device</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Internal</td><td>Intel AHCI 1.0 controller</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Ch</td><td>01h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Ch</td><td>02h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Ch</td><td>03h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Dh</td><td>00h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Dh</td><td>05h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel ISA bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>Intel Multimedia</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>Intel SMBU</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>Intel Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>06h</td><td>Internal</td><td>Intel Ethernet Controller</td></tr><tr><td>02h</td><td>00h</td><td>00h</td><td>Internal</td><td>ITE PCI toPCI Bridge</td></tr><tr><td>04h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller PCIe</td></tr><tr><td>05h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller PCIe</td></tr><tr><td>07h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller PCIe</td></tr></table>

Note: The bus number change if the PEG/PCIE port has a device.

# 6.4.2

Table 9 PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>LpcBridge</td><td>High Definition Audio</td><td>SMBus</td><td>PCIE Root Port #2 (IT8892)</td><td>PCIE Root Port #3 (LAN3)</td><td>PCIE Root Port #4 (LAN4)</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td></td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td></td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td></tr><tr><td>Int3</td><td>INTD:19</td><td></td><td></td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td></tr></table>

<table><tr><td>INT Line</td><td>PCI Slot 1</td><td>PCI Slot 2</td><td>PCIE Root Port #5 (PClex4)</td><td>PCIE Root Port #9 (PClex4)</td><td>PCIE Root Port #13 (LAN1)</td><td>PCIE Root Port #14 (LAN2)</td></tr><tr><td>Int0</td><td>INTA:17</td><td>INTA:18</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTB:17</td></tr><tr><td>Int1</td><td>INTB:18</td><td>INTB:19</td><td>INTB:17</td><td>INTB:17</td><td>INTB:17</td><td>INTC:18</td></tr><tr><td>Int2</td><td>INTC:19</td><td>INTC:16</td><td>INTC:18</td><td>INTC:18</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int3</td><td>INTD:16</td><td>INTD:17</td><td>INTD:19</td><td>INTD:19</td><td>INTD:19</td><td>INTA:16</td></tr></table>

<table><tr><td>INT Line</td><td>PCIE Root Port #21 (PCIex4)</td></tr><tr><td>Int0</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td></tr><tr><td>Int2</td><td>INTC:18</td></tr><tr><td>Int3</td><td>INTD:19</td></tr></table>

# 6.5 SMBus Slave Addresses

Table 10 SMBus Slave Addresses

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMM_A1</td><td>A0h</td></tr><tr><td>DIMM_A2</td><td>A2h</td></tr><tr><td>DIMM_B1</td><td>A4h</td></tr><tr><td>DIMM_B2</td><td>A6h</td></tr></table>

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# 7 BIOS Setup

# 7.1 Menu Structure

This section presents the primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections describe the submenus and options for each menu item. The default options are presented in bold, and the function of each setting is described in the right hand column of the table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td></tr><tr><td>- BIOS Information- System Date- System Time</td><td>- CPU Configuration ▶- PCH-FW Configuration ▶- ACPI Settings ▶- NCT6106D Super IO Configuration ▶- NCT6106D HW Monitor ▶- S5 RTC Wake Settings ▶- Serial Port Console Redirection ▶- Intel TXT Information ▶- USB Configuration ▶- CSM Configuration ▶- NVME Configuration ▶- Network Stack Configuration ▶</td><td>- System Agent (SA) Configuration ▶- PCH-IO Configuration ▶</td></tr><tr><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>- Administrator Password Description- User Password</td><td>- Boot Configuration ▶- Driver Option Priorities ▶- Fixed Boot Oder Priorities ▶</td><td>- Save &amp; Exit ▶- Default Options ▶- Boot Override ▶</td></tr></table>

# Notes:

► indicates a submenu Gray text indicates info only

# 7.2 Main Menu

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.

7.2.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>American Megatrends</td><td></td></tr><tr><td>Core Version</td><td>x.xx</td><td></td></tr><tr><td>Compliancy</td><td>UEFI x.x; PI x.x</td><td></td></tr><tr><td>Project Version</td><td>IMB-M45 x.xx.xx</td><td></td></tr><tr><td>Build Date and Time</td><td>mm/dd/yyyy hh:mm:ss</td><td></td></tr><tr><td>Access Level</td><td>Administrator</td><td></td></tr><tr><td>Memory Information</td><td></td><td></td></tr><tr><td>Total Memory</td><td>xxxx MB</td><td></td></tr><tr><td>Memory Frequency</td><td>xxxx MHz</td><td></td></tr><tr><td>Power Type</td><td>[ATX Mode]</td><td></td></tr><tr><td>System Date</td><td>mm/dd/yyyy</td><td>Sets the system date. Useto switch between elements.</td></tr><tr><td>System Time</td><td>hh:mm:ss</td><td>Sets the system time. Useto switch between elements.</td></tr></table>

# 7.3 Advanced Menu

This menu contains the settings for most of the user interfaces in the system.

7.3.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info Only</td><td>CPU type</td></tr><tr><td>ID</td><td>Info Only</td><td>CPU ID</td></tr><tr><td>Speed</td><td>Info Only</td><td>CPU Speed (xxxx MHz)</td></tr><tr><td>L1 Data Cache</td><td>Info Only</td><td>CPU L1 Data Cache</td></tr><tr><td>L1 Instruction Cache</td><td>Info Only</td><td>CPU L1 Instruction Cache</td></tr><tr><td>L2 Cache</td><td>Info Only</td><td>CPU L2 Cache</td></tr><tr><td>L3 Cache</td><td>Info Only</td><td>CPU L3 Cache</td></tr><tr><td>L4 Cache</td><td>Info Only</td><td>CPU L4 Cache</td></tr><tr><td>VMX</td><td>Info Only</td><td>CPU Virtual Machine Extension</td></tr><tr><td>SMX/TXT</td><td>Info Only</td><td>CPU Safer Mode Extension / Trusted Execution Technology</td></tr><tr><td>C6DRAM</td><td>DisabledEnabled</td><td>Enables or Disables moving of DRAM content to PRM memory wheb CPU is in C6 state</td></tr><tr><td>SW Guard Extensions (SGX)</td><td>Software ControlledEnabledDisabled</td><td>Sets Software Guard Extensions (SGX)</td></tr><tr><td>Select Owner EPOCH input type</td><td>No Change in Owner ECOPHsChange to NewRandom Owner ECOPHsManual User Defined Owner OPCHs</td><td>There are three Owner EPOCH modes (Each EPOCH is 64bit):</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Processor Cores</td><td>All/1/2/3/4/5</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Hyper-Threading</td><td>DisabledEnabled</td><td>Enables or Disables Hyper-Threading</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enables or Disables Turbo Mode</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enables or Disables utilization of additional hardware capabilities provided by Intel Trusted Execution Technology.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>DisabledEnabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enables or Disables CPU Power Management. Allows CPU to go to C States when it's not 100% utilized.</td></tr><tr><td>Enhanced C-state</td><td>DisabledEnabled</td><td>Enables or Disables C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>Package C state limit</td><td>AutoCPU DefaultC10C9C8C7sC7C6C3C2C0/C1</td><td>Maximum Package C State Limit Setting.CPU Default: Leaves to Factory default value.Auto: Initializes to deepest available Package C State Limit.</td></tr></table>

7.3.2 Advanced > PCH-FW Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ME Firmware Version</td><td>Info Only</td><td>PCH Firmware Version</td></tr><tr><td>ME Firmware Mode</td><td>Info Only</td><td>PCH Firmware Mode</td></tr><tr><td>ME Firmware SKU</td><td>Info Only</td><td>PCH Firmware SKU</td></tr><tr><td>ME Firmware Status 1</td><td>Info Only</td><td>PCH Firmware Status</td></tr><tr><td>ME Firmware Status 2</td><td>Info Only</td><td>PCH Firmware Status</td></tr><tr><td>ME State</td><td>DisabledEnabled</td><td>When Disabled ME will be put into ME Temporarily Disabled Mode.</td></tr><tr><td>AMT BIOS Features</td><td>Enabled</td><td></td></tr><tr><td>AMT Configuration</td><td></td><td></td></tr><tr><td>ME Unlock Control</td><td>Lock</td><td></td></tr></table>

7.3.3 Advanced > ACPI Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>S3 Video Repost</td><td>DisabledEnabled</td><td>Enables or Disables S3 Video Repost</td></tr><tr><td>PCIE# Wake from S5</td><td>DisabledEnabled</td><td>Enables or Disables PCIE to wake the system from S5.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables or Disables Hibernation.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend DisabledS3 only(Suspend to RAM)</td><td>Enables or Disables ACPI Sleep State</td></tr><tr><td>Wake on Ring</td><td>DisabledEnabled</td><td>Enables or Disables wake on ring function under ACPI S3/S4/S5.</td></tr></table>

7.3.4 Advanced > NCT6106D SuperIO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 1 (COMA)</td></tr><tr><td>Serial Port 2 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 2 (COMB)</td></tr><tr><td>Serial Port 3 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 3 (COMC)</td></tr><tr><td>Serial Port 4 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 4 (COMD)</td></tr><tr><td>Serial Port 5 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 5 (COME)</td></tr><tr><td>Serial Port 6 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 6 (COMF)</td></tr><tr><td>Parallel Port Configuration▶</td><td>Submenu</td><td>Sets Parameters of Parallel Port (LPT/LPTE)</td></tr><tr><td>WatchDog Count Mode</td><td>SecondMinute</td><td>WatchDog Count Mode Selection</td></tr><tr><td>WatchDog TimeOut Value</td><td>0</td><td>WatchDog Timeout Value, 0 = disabled.</td></tr><tr><td>Chassis Opened Warning</td><td>DisabledEnabled</td><td>Enables or Disables chassis intrusion detection. Note: If chassis tamper occurs, you can only enter setup to clear this error.</td></tr><tr><td>ErP/EuP S5 Support</td><td>DisabledEnabled</td><td>Enables or Disables ErP/EuP S5 support</td></tr></table>

7.3.5 Advanced > NCT6106D SuperIO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>Disabled Enabled</td><td>Enable or Disable Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=3F8hIRQ=4</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal setting for Super IO Device</td></tr><tr><td>RS485 Auto Flow</td><td>Disabled Enabled</td><td>Enables or Disables RS485 Auto Flow Control Function (Make sure to set RS485 on the COM1 jumper header if this setting is enabled.)</td></tr></table>

7.3.6 Advanced > NCT6106D SuperIO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2F8hIRQ=3</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>RS485 Auto Flow</td><td>DisabledEnabled</td><td>Enables or Disables RS485 Auto Flow Control Function (Make sure to set RS485 on the COM2 jumper header if this setting is enabled.)</td></tr></table>

7.3.7 Advanced > NCT6106D SuperIO Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=3E8hIRQ=5</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.8 Advanced > NCT6106D SuperIO Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2E8h; IRQ=5</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.9 Advanced > NCT6106D SuperIO Configuration > Serial Port 5 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2E0h; IRQ=10</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.10 Advanced > NCT6106D SuperIO Configuration > Serial Port 6 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port(COM)</td></tr><tr><td>Device Settings</td><td>IO=3E0h; IRQ=10</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.11 Advanced > NCT6106D SuperIO Configuration > Parallel Port Configuration

<table><tr><td>Parallel Port</td><td>Options</td><td>Note</td></tr><tr><td>Parallel Port</td><td>DisabledEnabled</td><td>Enables or Disables Parallel Port (LPT/LPTE)</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>Device Mode</td><td>STD Printer ModeSPP ModeEPP-1.9 and SPP ModeEPP-1.7 and SPP ModeECP modeECP and EPP 1.9 modeECP and EPP 1.7 mode</td><td>Changes the Printer Port mode.</td></tr></table>

7.3.12 Advanced > NCT6106D HW Monitor

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info Only</td><td>Smart Fan Function Page</td></tr><tr><td>System temperature</td><td>Info Only</td><td>xx C</td></tr><tr><td>CPU temperature (PECI)</td><td>Info Only</td><td>xx C</td></tr><tr><td>SYS_Fan1 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>CPU_Fan1 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>SYS_Fan2 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>VCORE</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>+12V</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>+5V</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>5V_Dual</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>AVCC</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>3VSB</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>3VCC</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>VBAT</td><td>Info Only</td><td>x.xxxV</td></tr></table>

7.3.13 Advanced > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan Function</td><td>DisabledEnabled</td><td>Enables or Disables Smart Fan Function</td></tr><tr><td>Smart Fan Mode Configuration▶</td><td>Submenu</td><td>Smart Fan Mode Configuration</td></tr></table>

7.3.14 Advanced > Smart Fan > Smart Fan Mode Configuration – Manual Mode

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SYS Smart Fan1 Mode</td><td>Manual ModeThermal Cruise Mode</td><td>SYS Smart Fan1 Mode</td></tr><tr><td>SYS expect PWM Output/DC Voltage</td><td>255</td><td>System FAN1 expect PWM Output/DC Voltage</td></tr><tr><td>CPU Smart Fan Mode</td><td>Manual ModeThermal Cruise Mode</td><td>CPU Smart Fan Mode</td></tr><tr><td>CPU expect PWM Output/DC Voltage</td><td>255</td><td>CPU FAN expect PWM Output/DC Voltage</td></tr><tr><td>SYS Smart Fan2 Mode</td><td>Manual ModeThermal Cruise Mode</td><td>SYS Smart Fan2 Mode</td></tr><tr><td>SYS expect PWM Output/DC Voltage</td><td>255</td><td>CHA FAN2 expect PWM Output/DC Voltage</td></tr></table>

7.3.15 Advanced > Smart Fan > Smart Fan Mode Configuration – Thermal Cruise Mode

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xxxFAN Target Temperature</td><td>50</td><td>FAN Target Temperature</td></tr><tr><td>xxxFAN Tolerance of Target Temp</td><td>5</td><td>FAN Tolerance of Target Temperature</td></tr><tr><td>xxxFAN Step Up Time</td><td>10</td><td>FAN step up time, 1 step = 0.1 second</td></tr><tr><td>xxxFAN Step Down Time</td><td>10</td><td>FAN step down time, 1 step = 0.1 second</td></tr><tr><td>xxxFAN Start-Up Value</td><td>127</td><td>FAN Start-Up Value</td></tr><tr><td>xxxFAN Stop Value</td><td>127</td><td>FAN Stop Value</td></tr></table>

7.3.16 Advanced > S5 RTC Wake Setting

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Wake System From S5</td><td>DisabledEnabled</td><td>Enables or Disables System wake on alarm event.</td></tr></table>

7.3.17 Advanced > Serial Port Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Enables or Disables Console Redirection</td></tr><tr><td>Console Redirection Settings▶</td><td>Submenu</td><td>Show when Console Redirection is enabled</td></tr></table>

7.3.18 Advanced > Serial Port Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VY100VT100+VT-UTF8ANSI</td><td>Type Select</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Select serial port transmission speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission error.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enables or Disables VT-UTF8 Combo Key</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled, only a test will be sent.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables or Disables extended terminal resolution.</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Selects FunctionKey and KeyPad on Putty.</td></tr></table>

7.3.19 Advanced > Intel TXT Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Chipset</td><td>Info Only</td><td></td></tr><tr><td>BIOS Acm</td><td>Info Only</td><td></td></tr><tr><td>Chipset Txt</td><td>Info Only</td><td></td></tr><tr><td>CPU Txt</td><td>Info Only</td><td></td></tr><tr><td>Error Code</td><td>Info Only</td><td></td></tr><tr><td>Class Code</td><td>Info Only</td><td></td></tr><tr><td>Major Code</td><td>Info Only</td><td></td></tr><tr><td>Minor Code</td><td>Info Only</td><td></td></tr></table>

7.3.20 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Note</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enables or Disables UEFI Network Stack.</td></tr></table>

7.3.21 Advanced > CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>DisabledEnabled</td><td>Enables or Disables CSM Support</td></tr><tr><td>CSM16 Module Version</td><td></td><td></td></tr><tr><td>Option ROM execution</td><td></td><td></td></tr><tr><td>Network</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI device</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy other device OpROM.</td></tr></table>

7.3.22 Advanced > NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVMe controller and Drive information</td><td>Info Only</td><td>NVMe Device Options Settings</td></tr><tr><td>Show device</td><td>Info Only</td><td></td></tr></table>

7.3.23 Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Devices</td><td>Show current USB devices</td><td></td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables or Disables Legacy USB support.</td></tr><tr><td>XHCI Hand-Off</td><td>DisabledEnabled</td><td>This is a workaround for OSes without XHCI hand-off support.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enables or Disables USB Mass Storage Driver Support</td></tr></table>

# 7.4 Chipset Menu

This menu contains settings for other user interfaces in the system.

7.4.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info Only</td><td></td></tr><tr><td>VT-d Capability</td><td>Info Only</td><td></td></tr><tr><td>Memory Configuration▶</td><td>Submenu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration▶</td><td>Submenu</td><td>Graphics Configuration</td></tr><tr><td>PEG Port Configuration▶</td><td>Submenu</td><td>PEG Port Options</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>VT-d capability</td></tr></table>

7.4.2 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info Only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info Only</td><td></td></tr><tr><td>Memory Timings</td><td>Info Only</td><td></td></tr><tr><td>DIMM_A1</td><td>Info Only</td><td></td></tr><tr><td>DIMM_A2</td><td>Info Only</td><td></td></tr><tr><td>DIMM_B1</td><td>Info Only</td><td></td></tr><tr><td>DIMM_B2</td><td>Info Only</td><td></td></tr><tr><td>Max TOULUD</td><td>Dynamic</td><td>Maximum value of TOULUD</td></tr></table>

7.4.3 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIE</td><td>Selects which of IGFX/PEG/PCIE Graphics device should be Primary Display</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keeps IGFX enabled based on the setup options</td></tr><tr><td>PSMI Support</td><td>DisabledEnabled</td><td>Enables or Disables PSMI Support</td></tr><tr><td>DVMT Pre-Allocated</td><td>0326448121620242832_F736404448525660 M</td><td>Selects DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device</td></tr><tr><td>DVMT Total Gfx Mem</td><td>256M128MMAX</td><td>Selects DVMT 5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

7.4.4 Chipset > System Agent (SA) Configuration > PEG port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG 0:1:0</td><td></td><td></td></tr><tr><td>Enable Root port</td><td>DisabledEnabledAuto</td><td>Enables or Disables the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configures PEG 0:1:0 Max Speed</td></tr><tr><td>PEG 0:1:1</td><td></td><td></td></tr><tr><td>Enable Root port</td><td>DisabledEnabledAuto</td><td>Enables or Disables the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:0 Max Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>DisabledEnabled</td><td>Detect Non-Compliance PCI Express Device in PEG</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>Enables or Disables VT-d capability</td></tr></table>

7.4.5 Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration▶</td><td>Submenu</td><td>PCI Express Configuration settings</td></tr><tr><td>SATA And RST Configuration▶</td><td>Submenu</td><td>SATA Device Options Settings</td></tr><tr><td>USB Configuration▶</td><td>Submenu</td><td>USB Configuration settings</td></tr><tr><td>HD Audio Configuration▶</td><td>Submenu</td><td>HD Audio Subsystem Configuration settings</td></tr><tr><td>Serial IO Configuration▶</td><td>Submenu</td><td>Serial IO Configuration settings</td></tr><tr><td>LAN1 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard NIC.</td></tr><tr><td>LAN Option-ROM</td><td>DisabledEnabled</td><td>Show if Network to Legacy</td></tr><tr><td>Wake on Lan Enable</td><td>DisabledEnabled</td><td>Enables or Disables integrated LAN to wake the system.</td></tr><tr><td>LAN2 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard Lan2</td></tr><tr><td>LAN2 PXE OpROM</td><td>DisabledEnabled</td><td>Shows if Network to Legacy</td></tr><tr><td>LAN3 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard Lan3</td></tr><tr><td>LAN3 PXE Option</td><td>DisabledEnabled</td><td>Shows if Network to Legacy</td></tr><tr><td>LAN4 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard Lan4</td></tr><tr><td>LAN4 PXE Option</td><td>DisabledEnabled</td><td>Shows if Network to Legacy</td></tr><tr><td>Restore AC Power Loss</td><td>Power On/Power off/Last State</td><td>Specifies what state to go to when power is reapplied after a power failure (G3 state)</td></tr><tr><td>GPIO Group Control</td><td>DisabledEnabled</td><td>Configures the digital GPIO pins</td></tr></table>

7.4.6 Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info only</td><td></td></tr><tr><td>PCI Express Root Port 3(LAN3)</td><td>N/A</td><td></td></tr><tr><td>PCI Express Root Port 4(LAN4)</td><td>N/A</td><td></td></tr><tr><td>PCIE Port 2 is assigned to IT8892</td><td>N/A</td><td></td></tr><tr><td>PCI Express Root Port 5( x4, slot 4 )▶</td><td>Submenu</td><td>PCI Express Root Port 5 Settings.</td></tr><tr><td>PCI Express Root Port 9( x4, slot 5 )▶</td><td>Submenu</td><td>PCI Express Root Port 9 Settings.</td></tr><tr><td>PCI Express Root Port 13(LAN1)</td><td>N/A</td><td></td></tr><tr><td>PCI Express Root Port 14(LAN2)</td><td>N/A</td><td></td></tr><tr><td>PCI Express Root Port 21( x4, slot 6 )▶</td><td>Submenu</td><td>PCI Express Root Port 21 Settings.</td></tr></table>

7.4.7 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port 5/9/21

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 5</td><td>DisabledEnabled</td><td>Controls the PCI Express Root Port.</td></tr><tr><td>ASPM Support</td><td>AutoL0sL1L1L0sDisabled</td><td>Sets the ASPM Level: Force L0s – Force all link to L0s StateAUTO – BIOS auto configureDISABLE – Disables ASPM</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configures PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>DisabledEnabled</td><td>Detects Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr></table>

7.4.8 Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>SATA Configuration</td><td>Options</td><td>Note</td></tr><tr><td>SATA Controller(s)</td><td>DisabledEnabled</td><td>Enables or Disables SATA Device</td></tr><tr><td>SATA Mode</td><td>AHCIIntel RST Premium with Intel Optane System Acceleration</td><td>Determines how SATA controllers operate.</td></tr><tr><td>Serial ATA Port 1</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 1</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 2</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 2</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 3</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 3</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 4</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 4</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 5</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 5</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 6</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td>Information</td><td></td></tr><tr><td>Port 6</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr></table>

7.4.9 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Disable Compliance Mode</td><td>DisabledEnabled</td><td>Enables or Disables XHCI Disable Compliance Mode</td></tr><tr><td>USB12 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB34 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB56 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB78 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB910 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB1112 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB1314 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr></table>

7.4.10 Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Controls Detection of the HD-Audio device.</td></tr></table>

7.4.11 Chipset > PCH-IO Configuration > Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>DisabledEnabled</td><td>Enables or Disables Serial IO Controller</td></tr></table>

7.5 Security Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Set Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Set User Password</td></tr></table>

7.6 Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info Only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1 (seconds)</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means infinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or Disables Quiet Boot option</td></tr><tr><td>Support Native Resolution</td><td>Disabled Enabled</td><td>Enables or Disables native resolution support</td></tr><tr><td>Driver Option Priorities</td><td>Info Only</td><td></td></tr><tr><td>Boot mode select</td><td>LEGACY UEFI</td><td>Selects Legacy or UEFI boot mode</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Info Only</td><td></td></tr><tr><td>1st Boot</td><td>Hard Disk</td><td>Sets the system boot order.</td></tr><tr><td>2nd Boot</td><td>NVME</td><td>Sets the system boot order.</td></tr><tr><td>3rd Boot</td><td>CD/DVD</td><td>Sets the system boot order.</td></tr><tr><td>4th Boot</td><td>USB Hard Disk</td><td>Sets the system boot order.</td></tr><tr><td>5th Boot</td><td>USB CD/DVD</td><td>Sets the system boot order.</td></tr><tr><td>6th Boot</td><td>USB Key</td><td>Sets the system boot order.</td></tr><tr><td>7th Boot</td><td>USB Floppy</td><td>Sets the system boot order.</td></tr><tr><td>8th Boot</td><td>Network</td><td>Sets the system boot order.</td></tr></table>

7.7 Save & Exit Menu

<table><tr><td>Save &amp; Exit</td><td>Options</td><td>Note</td></tr><tr><td>Save Changes and Exit</td><td>YesNo</td><td>Exits system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>YesNo</td><td>Exits system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>YesNo</td><td>Resets the system after saving the changes.</td></tr><tr><td>Default Options</td><td>YesNo</td><td></td></tr><tr><td>Restore Defaults</td><td>YesNo</td><td>Restores or Loads Default values for all Setup options.</td></tr><tr><td>Boot Override</td><td></td><td></td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td>Attempts to Launch EFI Shell application (Shell.efi) from one of the available filesystem devices</td></tr></table>

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# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

 Please read these safety instructions carefully.
 Please keep this User‘s Manual for later reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
 To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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