# IMB-M45H

# User’s Manual

ATX Motherboard with 8th/9th Gen Intel® Core™ i7/i5/i3 Processors and Intel® H310 Chipset

![Green printed circuit board with visible components including CPU socket, RAM slots, and memory chips (no readable text or symbols)](.imb-m45h-50m-00068-1010/53e090896af50582318e57e6929632c29b81777971441b0ac4443c89eb382ec0.jpg)

# Preface

# Copyright

Copyright © 2021 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines and a solid rectangle below (no text or labels)](.imb-m45h-50m-00068-1010/f51a37c262121cff4720ae60a03984e91ff146308bfb944848cfdc446e5e9f7c.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.imb-m45h-50m-00068-1010/0ace649961e833bd7bb70f38148c80975514d202212e33eba882dce8003474ec.jpg)

![The image features a recycling symbol consisting of three chasing arrows enclosed within a square outline, with the text 'Li-ion' printed below it in bold black letters.](.imb-m45h-50m-00068-1010/97676ded6ffc1efbc339372b24ab0eaf9ea3f47b54b7996eeb7a731f56c353fc.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.imb-m45h-50m-00068-1010/01f0f4b55405fd02a5fc7fc2bf546d6edccb6b731b5aa92246ac6fd0604fe4f1.jpg)

![廢電池請回收](.imb-m45h-50m-00068-1010/daeb708d36e50f7e03a5a00fe182658706f7fe8338636e5be60162b0bae7b252.jpg)

# California Proposition 65 Warning

![The image displays a yellow triangular warning sign with a thick black border. Centered inside the triangle is a black exclamation mark.](.imb-m45h-50m-00068-1010/0f857bb1e82f8a0ae2057a78e32bb4e478d716716242aaf04599aec63a5a521d.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2021-01-24</td><td></td></tr><tr><td>1.1</td><td>Update COM connector pin definitions; update addresses</td><td>2022-03-07</td><td>CC</td></tr></table>

# Table of Contents

Preface ...

List of Figures ........ ..vi

List of Tables ........ .vii

1 Introduction..........

1.1 Packing List ...
1.2 Optional Accessories .

2 Specifications ..............

2.1 Core System.. .3
2.2 I/O Interface .. .3
2.3 Video.... .. 3
2.4 Audio... .4
2.5 Temperatures . 4
2.6 Humidity... .4
2.7 Certificate (EMC) .. 4
2.8 Form Factor .. 4
2.9 Operating Systems ... 4
2.10 Functional Block Diagram.. 5

3 Mechanical Layout ..

3.1 Connector Locations..
3.2 Mechanical Dimensions.. ..10

4 Connector Pinouts ................. .11

4.1 Rear IO Connectors.. .11
4.2 Internal Connectors . ..14
4.3 Jumper and Switch Settings .. ..20

5 Driver Installation .... .25

6 System Resources .. .27

6.1 System Memory Map.. ..27
6.2 I/O Map .... ..27
6.3 Interrupt Request (IRQ) Lines.. .. 29
6.4 PCI Features.. ..30
6.5 SMBus Slave Addresses .. ..31

# 7 BIOS Setup.......... .33

7.1 Menu Structure . .. 33
7.2 Main Menu... ..34
7.3 Advanced Menu.. .. 35
7.4 Chipset Menu.... .. 43
7.5 Security Menu... .. 48
7.6 Boot Menu . ..49
7.7 Save & Exit Menu . .. 50

# Safety Instructions.... .51

# Getting Service..... .52

# List of Figures

Figure 1: Functional Block Diagram . .5

Figure 2: IO Panel Connector Locations .

Figure 3: Onboard Connector Locations . .8

Figure 4: Mechanical Dimensions .. ...10

Figure 5: Mechanical Dimensions - IO Panel.. ...10

# List of Tables

Table 1: IO Panel Connector Definitions.

Table 2: Onboard Connector Definitions. .8

Table 3: Jumper and Switch Definitions.. ..20

Table 4: System Memory Map .. ..27

Table 5: IO Map ..... ..27

Table 6: IRQ Lines PIC Mode.. ..29

Table 7 IRQ Lines APIC Mode .. ..29

Table 8 PCI Configuration Space Map.. ...30

Table 9 PCI Interrupt Routing Map.. ...31

Table 10 SMBus Slave Addresses.. ...31

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# 1 Introduction

The IMB-M45H is an ATX motherboard supporting 8th and 9th Generation Intel® Core™ i7/i5/i3 processors, an Intel® H310 chipset, and 5 PCI expansion slots to provide a cost-competitive embedded computing solution. With high-speed data transfer interfaces such as PCIe 3.0/2.0, USB 3.0, and SATA 6 Gb/s, dual-channel DDR4 memory up to 64 GB in two DIMM slots for industrial automation applications, the IMB-M45H offers a significant competitive advantage for embedded computing applications. The rugged I/O design enhances system flexibility with robust device compatibility, durable connectivity, and extreme environment readiness.

# 1.1 Packing List

IMB-M45H ATX motherboard
Rear I/O shield

# 1.2 Optional Accessories

• 2-port USB 2.0 cable with bracket (Part Number: 30-25010-3010)
1-port LPT cable with bracket (Part Number: 30-25019-2000)
2-port COM cable with bracket (Part Number: 30-25003-3000)
• 1-port PS/2 cable for keyboard/mouse (Part Number: 30-01016-0000)
1-port SATA cable (Part Number: 30-10057-7000)
• CPU cooler for &lt;=65W and 35W CPU (Part Number: 32-20113-2000, including CPU cooler backplane)
CPU cooler for &gt;65W CPU (Part Number: 32-20831-0000-A0, CPU cooler backplane Part Number: 32- 50031-0000-A0)

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# 2 Specifications

# 2.1 Core System

 CPU: 8th/9th Generation Intel® Core™ i7/i5/i3 Desktop Processor, LGA1151 socket

• Intel® Core™ i7-8700, 3.2GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support, (6C/12T)
• Intel® Core™ i7-8700T, 2.4GHz 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support, (6C/12T)
• Intel® Core™ i5-8500, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support, (6C/6T)
• Intel® Core™ i5-8500T, 2.1GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support, (6C/6T)
• Intel® Core™ i3-8100, 3.6GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support, (4C/4T)
• Intel® Core™ i3-8100T, 3.1GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (4C/4T)
• Intel® Pentium® G5400, 3.7GHz, 4M Cache, 58W TDP, LGA1151, DDR4 2400MHz support, (2C/4T)
• Intel® Pentium® G5400T, 3.1GHz, 4M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (2C/4T)
• Intel® Celeron® G4900, 3.1GHz, 2M Cache, 54W TDP, LGA1151, DDR4 2400MHz support, (2C/2T)
• Intel® Celeron® G4900T, 2.9GHz, 2M Cache, 35W TDP, LGA1151, DDR4 2400MHz support, (2C/2T)
• Intel® Core™ i7-9700E, 2.6GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (8C/8T)
• Intel® Core™ i7-9700TE, 1.8GHz, 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (8C/8T)
• Intel® Core™ i5-9500E, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T)
• Intel® Core™ i5-9500TE, 2.2GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T)
• Intel® Core™ i3-9100E, 3.1GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (4C/4T)
• Intel® Core™ i3-9100TE, 2.2GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (4C/4T)

Chipset: Intel® H310 Chipset
 Memory: 2x 288-pin DDR4 sockets (vertical type), dual-channel DDR4 2400/2666 MHz, up to 64 GB (based on CPU)
 BIOS: AMI® UEFI BIOS, 128 Mb SPI Flash Memory

# 2.2 I/O Interface

 Expansion Slots: 1x PCIe x16 Gen3, 1x PCIe x4 Gen2, 5x PCI 2.2
 LAN: LAN1: Intel® I219-LM via RJ45 connector (rear), LAN2: Intel® I211-AT via RJ45 connector (rear)
SATA: 4x SATA 6.0 Gb/s connectors
USB: 4x USB 3.0 connectors (rear), 2x USB 2.0 connectors (rear), 2x USB 2.0 pin headers, 2x USB 2.0 (vertical type A connector)

 COM: 2x RS-232/422/485 with auto flow control connector (rear), 4x RS-232 pin headers

 Parallel Port: 1x LPT pin header

 PS/2 Combo Port: 1x PS/2 keyboard and mouse connector (rear)

 DIO: 2x 20-pin/2.0mm GPIO pin header: 16 in and 16 out, one ground pin and one power pin

# 2.3 Video

Graphics Engine: Integrated Intel® HD Graphics series (based on CPU)
 Interfaces: 1x VGA connector (rear), resolution up to 1920x1200 at 60Hz, 1x HDMI connector (rear) resolution up to 3840x2160 at 30Hz

# 2.4 Audio

 Audio Codec: Realtek® ALC892-CG or ALC888S
Interfaces: 1x Mic-in and 1x Line-out connector (rear)

# 2.5 Temperatures

Operating Temperature: $0 \%$ to $6 0 ^ { \circ } \mathsf { C }$
Storage Temperature: $\scriptscriptstyle - 4 0 ^ { \circ } \mathsf { C }$ to $8 5 ^ { \circ } \mathrm { C }$

# 2.6 Humidity

$6 0 ^ { \circ } \mathsf { C }$ at 95% RH, non-condensing

# 2.7 Certificate (EMC)

CE/FCC Class B

# 2.8 Form Factor

ATX: 305 mm x 244 mm (W x L)

# 2.9 Operating Systems

Microsoft® Windows® 10, 64-bit
OpenSUSE Leap 15.1, 64-bit
Fedora 30, 64-bit
Ubuntu 18.10, 64-bit

# 2.10 Functional Block Diagram

![Based on the provided block diagram, here is the description of the labeled blocks and connections:\n\n**Top Block: 8th/9th Gen Intel® Core™**\n*   **Left Connections:** Connects to 'PCIe Gen3 x16', 'HDMI', and 'VGA' (the VGA connection goes through a block labeled 'PTN3355BS').\n*   **Right Connections:** Connects to 'Dual Channel' and 'DDR4- 2400/2666'.\n*   **Down Connection:** Connects to the 'H310 Chipset' via a line labeled 'DMI'.\n\n**Middle Block: H310 Chipset**\n*   **Left Connections:**\n    *   'RJ-45' connects via 'I219LM' to 'LAN'.\n    *   'RJ-45' connects via 'I211AT' to 'PCIe x1'.\n    *   'SATA Gen3 x4'.\n    *   'PCIe x4'.\n    *   'USB3.0 x4'.\n    *   'USB2.0 x2'.\n    *   'USB2.0 x4'.\n*   **Right Connections:**\n    *   Connects to 'ALC892-CG/ ALC888S' which leads to 'Line out/in, Mic in'.\n    *   Connects via 'PCIe x1' to 'IT8892E' which leads to 'PCI 3~5'.\n    *   'IT8892E' connects to 'IT8209R' which leads to 'PCI 1~2'.\n    *   Connects via 'SPI' to 'SPI ROM'.\n    *   Connects to '32bit GPIO'.\n*   **Down Connection:** Connects to the 'NCT6106D' via a line labeled 'LPC'.\n\n**Bottom Block: NCT6106D**\n*   **Left Connections:**\n    *   'PS2 KB/MS combo'.\n    *   'RS232/422/485 x2'.\n    *   'RS232 x4'.\n*   **Right Connections:**\n    *   'SYS FAN x2'.\n    *   'CPU FAN'.\n    *   'Printer Port'.\n\n**Legend:**\n*   Blue squares indicate 'Connectors on rear window'.\n*   Grey squares indicate 'On-board connectors/Pin Headers'.](.imb-m45h-50m-00068-1010/24370485e7235488e5f53a4b2e69cfd6c58226700d9631e82723265b3c65626e.jpg)

Figure 1: Functional Block Diagram

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# 3 Mechanical Layout

# 3.1 Connector Locations

![A\nC\nE\nG\nI\nK\nB\nD\nF\nH\nJ\nL](.imb-m45h-50m-00068-1010/c158382878085dc575918ad41c4e25ffe6825c31531d50ce9288c2f335f9817e.jpg)

Figure 2: IO Panel Connector Locations

Table 1: IO Panel Connector Definitions

<table><tr><td colspan="2">IO Panel Connectors</td></tr><tr><td>Item</td><td>Description</td></tr><tr><td>A</td><td>VGA Port</td></tr><tr><td>B</td><td>HDMI Port</td></tr><tr><td>C</td><td>KB/MS Port</td></tr><tr><td>D</td><td>Two USB2.0 ports</td></tr><tr><td>E</td><td>COM1 RS-232/422/485, RI pin with Power Jumper Select</td></tr><tr><td>F</td><td>COM2 RS-232/422/485</td></tr><tr><td>G</td><td>LAN1</td></tr><tr><td>H</td><td>2x USB3.1 Gen1 ports</td></tr><tr><td>I</td><td>LAN2</td></tr><tr><td>J</td><td>2x USB3.1 Gen1 ports</td></tr><tr><td>K</td><td>Headphone out</td></tr><tr><td>L</td><td>Mic in</td></tr></table>

![C\nE G H\nD F\nI J\nK\nL\nM\nAB\nAA\nAU\nAH\nB\nAT\nAS\nAI\nAK\nAJ\nAL\nN\nO\nP\nS\nT\nAC\nA\nAD AE\nAF AG\nU V W X Y\nZ](.imb-m45h-50m-00068-1010/9eb5d1fc07d745ccadb89f15979d6d599403c954a224f2306bc96a66e833df89.jpg)

Figure 3: Onboard Connector Locations

Table 2: Onboard Connector Definitions

<table><tr><td colspan="3">Onboard Connectors</td></tr><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>A</td><td>ATX POWER 8PIN</td><td>ATX12V1</td></tr><tr><td>B</td><td>CPU_FAN</td><td>CPU_FAN1</td></tr><tr><td>C</td><td>ATX POWER 24PIN</td><td>EATXPWR1</td></tr><tr><td>D</td><td>SATA1</td><td>SATA1</td></tr><tr><td>E</td><td>SATA2</td><td>SATA2</td></tr><tr><td>F</td><td>SATA3</td><td>SATA3</td></tr><tr><td>G</td><td>SATA4</td><td>SATA4</td></tr><tr><td>H</td><td>USB 56</td><td>USB 56</td></tr><tr><td>I</td><td>USB9</td><td>USB9</td></tr><tr><td>J</td><td>USB10</td><td>USB10</td></tr><tr><td>K</td><td>SYS_FAN1</td><td>SYS_FAN1</td></tr><tr><td>L</td><td>Front Panel</td><td>F_PANEL1</td></tr><tr><td>M</td><td>GPIO</td><td>JDIO1</td></tr><tr><td>N</td><td>COM6</td><td>COM6</td></tr><tr><td>O</td><td>COM5</td><td>COM5</td></tr><tr><td>P</td><td>COM4</td><td>COM4</td></tr><tr><td>S</td><td>COM3</td><td>COM3</td></tr><tr><td>T</td><td>PRINT PORT</td><td>LPT1</td></tr><tr><td>U</td><td>PCI1</td><td>PCI1</td></tr><tr><td>V</td><td>PCI2</td><td>PCI2</td></tr><tr><td>W</td><td>PCI3</td><td>PCI3</td></tr><tr><td>X</td><td>PCI4</td><td>PCI4</td></tr><tr><td>Y</td><td>PCI5</td><td>PCI5</td></tr><tr><td>Z</td><td>FRONT AUDIO</td><td>FP_AUDIO1</td></tr><tr><td>AA</td><td>DIMMA1</td><td>DIMMA1</td></tr><tr><td>AB</td><td>DIMMB1</td><td>DIMMB1</td></tr><tr><td>AC</td><td>SYS_FAN2</td><td>SYS_FAN2</td></tr><tr><td>AD</td><td>COM1 RS232/422/485 select</td><td>JSETCOM1</td></tr><tr><td>AE</td><td>COM2 RS232/422/485 select</td><td>JSETCOM2</td></tr><tr><td>AF</td><td>COM1 master/slave and terminal select</td><td>COM1_S1~4</td></tr><tr><td>AG</td><td>COM2 master/slave and terminal select</td><td>COM2_S1~4</td></tr><tr><td>AH</td><td>DIO no power/+5V/+12V select</td><td>JPW4</td></tr><tr><td>AI</td><td>SMBUS no power/+3.3V/+5V select</td><td>JPW2</td></tr><tr><td>AJ</td><td>I2C no power/+3.3V/+5V select</td><td>JPW1</td></tr><tr><td>AK</td><td>AT/ATX mode header</td><td>JPSON1</td></tr><tr><td>AL</td><td>Case open alarm</td><td>JCASE1</td></tr><tr><td>AS</td><td>I2C header</td><td>JI2C1</td></tr><tr><td>AT</td><td>SMBUS header</td><td>JSMB1</td></tr><tr><td>AU</td><td>Clear CMOS</td><td>JCMOS1</td></tr></table>

# 3.2 Mechanical Dimensions

Top View
![243.84\n237.49\n165.1\n33.02\n22\n52\n77.54\n105\n127.5\n146\n163.83\n209.55\n288.29\n304.8\nDimensions: mm\n10.16](.imb-m45h-50m-00068-1010/4344b890324e0336c9f11c60e86d8b088204fb1f1ff342ed13690147503feb1f.jpg)

Figure 4: Mechanical Dimensions

Side View
![31.54\nDimensions: mm](.imb-m45h-50m-00068-1010/df2092fe0734af227b9e91c2bb2ce3626a319c422b2793c520de3cc95c96c8b9.jpg)

Figure 5: Mechanical Dimensions - IO Panel

# 4 Connector Pinouts

See 3.1 Connector Locations on page 7 for connector locations.

# 4.1 Rear IO Connectors

# 4.1.1 HDMI Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDMI1_CON_DP2</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>HDMI1_CON_DN2</td><td>4</td><td>HDMI1_CON_DP1</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>HDMI1_CON_DN1</td></tr><tr><td>7</td><td>HDMI1_CON_DP0</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>HDMI1_CON_DN0</td><td>10</td><td>HDMI1_CON_CKP</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>HDMI1_CON_CKN</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>HDMI1_DDC_CLK</td><td>16</td><td>HDMI1_DDC_DATA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5V_HDMI</td></tr><tr><td>19</td><td>HDMI1_CON_HPD</td><td></td><td></td></tr></table>

![The image displays a schematic line drawing of a connector housing with two parallel rows of rectangular terminals. Text labels identify specific pin positions at the ends of the rows.\n\nThe text is arranged as follows:\n*   **Top Row:** The numbers '19 17' appear on the far left, and '3 1' appear on the far right.\n*   **Bottom Row:** The number '18' appears on the far left, and '4 2' appear on the far right.](.imb-m45h-50m-00068-1010/f471c4cf5017296d1983a9f1d9639a4ab3f0c158f453a04d7796725f3c5631c3.jpg)

# 4.1.2 VGA Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VGA_CON_RED</td><td>2</td><td>VGA_CON_GREEN</td></tr><tr><td>3</td><td>VGA_CON_BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>+5V_HDMI</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>VGA_DDCDAT</td></tr><tr><td>13</td><td>VGA_CON_HS</td><td>14</td><td>VGA_CON_VS</td></tr><tr><td>15</td><td>VGA_DDCCLK</td><td></td><td></td></tr></table>

![5\n1\n5\n1\n15\n11\n15\n11](.imb-m45h-50m-00068-1010/392d26ea090ea31b0b608fafed6c295a3fbdb0072f715748ea918dcb7bb994f1.jpg)

# 4.1.3 USB Connectors

USB 3.0, USB 2.0

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5 VDC</td></tr><tr><td>2</td><td>USB D-</td></tr><tr><td>3</td><td>USB D+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![The image displays a line drawing of an RJ45 connector. Inside the rectangular outline, there are vertical lines representing the internal pins. Below the connector, the numbers 1, 2, 3, and 4 are printed in sequence from left to right.](.imb-m45h-50m-00068-1010/81718748c45c4b5e5a3b1c58b0ed092bf145dfd927b06c399484e76a7bd5f65c.jpg)
USB2.0

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V_USB12</td></tr><tr><td>2</td><td>USB_CM_N1</td></tr><tr><td>3</td><td>USB_CM_P1</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3_RX_CM_N1</td></tr><tr><td>6</td><td>USB3_RX_CM_P1</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3_TX_CM_N1</td></tr><tr><td>9</td><td>USB3_TX_CM_P1</td></tr></table>

![The image displays a black and white line drawing. At the top, the numbers '9 8 7 6 5' are arranged horizontally. Below them is a large rectangular border. Inside this border, a smaller, hollow rectangle is centered. At the bottom of the large border, the numbers '1 2 3 4' are arranged horizontally.](.imb-m45h-50m-00068-1010/124a8d2252a55ce057c7f09e7e4a1f8347f4ec7d1e20a40198ed246b7cf5e4ee.jpg)
USB3.0

# 4.1.4 PS/2 Combo Connector

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>KB_DAT</td></tr><tr><td>2</td><td>MS_DAT</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>+5V_DUAL</td></tr><tr><td>5</td><td>KB_CLK</td></tr><tr><td>6</td><td>MS_CLK</td></tr></table>

![6\n4\n2 1\n3\n5](.imb-m45h-50m-00068-1010/31c9a229cc63919bf6e0354e0042ae0176b13ee408f5738fa406999d4430cc0b.jpg)

# 4.1.5 COM 1-2 Stacked Connector

Top connector COM1, bottom connector COM2

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>Tx-</td><td>Tx/Rx-</td></tr><tr><td>2</td><td>RxD</td><td>Tx+</td><td>Tx/Rx+</td></tr><tr><td>3</td><td>TxD</td><td>Rx+</td><td>N/A</td></tr><tr><td>4</td><td>DTR#</td><td>Rx-</td><td>N/A</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>DSR#</td><td>N/A</td><td>N/A</td></tr><tr><td>7</td><td>RTS#</td><td>N/A</td><td>N/A</td></tr><tr><td>8</td><td>CTS#</td><td>N/A</td><td>N/A</td></tr><tr><td>9</td><td>RI#</td><td>N/A</td><td>N/A</td></tr></table>

![The image displays a technical line drawing of a DB9 connector. It is enclosed within a rectangular border. On the left and right sides of the central housing are two hexagonal shapes with circles inside, representing mounting points. The central housing is a rounded rectangle containing two rows of circular pin holes. The top row consists of five holes, and the bottom row consists of four holes. The numbers '1', '5', '6', and '9' are visible near the corners of the pin arrangement: '1' is above the top-left hole, '5' is near the top-right holes, '6' is above the bottom-left hole, and '9' is near the bottom-right holes.](.imb-m45h-50m-00068-1010/53c5cc1863eed7da9bd2e3876626033f360fce0e3cc75f8cff14c4de67cff85f.jpg)

# 4.1.6 Ethernet Connectors (LAN1, LAN2)

Dual 10/100/1000Mbit/s LAN Ethernet controllers based on Intel® i219LM/i211AT, support PXE and WOL over both LANs.

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_MD10+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_MD10-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_MD11+</td></tr><tr><td>4</td><td>--</td><td>LAN_MD12+</td></tr><tr><td>5</td><td>--</td><td>LAN_MD12-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_MD11-</td></tr><tr><td>7</td><td>--</td><td>LAN_MD13+</td></tr><tr><td>8</td><td>--</td><td>LAN_MD13-</td></tr></table>

![The image displays a technical schematic with the text 'LED1' and 'LED2' at the top. Below this is a rectangular outline resembling an RJ45 connector jack with internal contact shapes. At the bottom, the numbers '8' and '1' are shown with lines pointing to the bottom corners of the connector outline.](.imb-m45h-50m-00068-1010/3a078812e76ef77f37b37d55baa35cfc08f331672c96913d43113abdddfc2cd2.jpg)

<table><tr><td colspan="2">LED1 (Speed)</td><td colspan="2">LED2 (Link/Activity)</td></tr><tr><td>Status</td><td>Description</td><td>Status</td><td>Description</td></tr><tr><td>Off</td><td>10 Mb connection</td><td>Off</td><td>No Link</td></tr><tr><td>Green</td><td>100 Mb connection</td><td>Green</td><td>Linked</td></tr><tr><td>Orange</td><td>1 Gb connection</td><td>Blinking</td><td>Data Activity</td></tr></table>

# 4.2 Internal Connectors

# 4.2.1 USB 5-6

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VDC</td><td>2</td><td>VDC</td></tr><tr><td>3</td><td>D5 -</td><td>4</td><td>D6 -</td></tr><tr><td>5</td><td>D5 +</td><td>6</td><td>D6 +</td></tr><tr><td>7</td><td>Ground</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>KEY (no pin)</td><td>10</td><td>No Connect/ OC</td></tr></table>

![The image displays a black-and-white line drawing of an electrical connector pinout.\n\nInside a vertical rectangular outline:\n*   A small square is located at the top left.\n*   Below the square is a column of five circles.\n*   To the right of that column is a second vertical column of five circles.\n*   Below the two columns is a single circle centered at the bottom.\n\nSurrounding the rectangle are numbers and a symbol:\n*   The number '1' is to the left of the top edge.\n*   A small triangle pointing right is near the top left edge.\n*   The number '2' is to the right of the top edge.\n*   The number '10' is to the right of the lower section.](.imb-m45h-50m-00068-1010/a3022a565fce0126f7f88a45fdce02fde9bbdbd4af4b507823a0ca73448d2682.jpg)

# 4.2.2 SATA1, SATA2, SATA3, SATA4

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>TXP</td><td>Transmit diff data – positive</td></tr><tr><td>3</td><td>TXN</td><td>Transmit diff data – negative</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr><tr><td>5</td><td>RXN</td><td>Receive diff data – negative</td></tr><tr><td>6</td><td>RXP</td><td>Receive diff data – positive</td></tr><tr><td>7</td><td>GND</td><td>Ground</td></tr></table>

![This is a black-and-white technical line drawing of a vertical rectangular assembly.\n\n*   **Reference Numerals:** The number **1** is on the right side, pointing to the upper portion of an outer casing or frame. The number **7** is below it, pointing to an inner rectangular component.\n*   **Inner Component (7):** This is a long, narrow rectangle situated centrally. It features a vertical column of alternating black and white squares running down its center and a small horizontal tab protruding from its left side.\n*   **Outer Casing (1):** This structure encloses the inner component. It features a bracket-like shape at the very top and another bracket-like shape at the bottom.](.imb-m45h-50m-00068-1010/a9280cfab2a5ba356a689cd8d198952351f003badc0fa72964c26a8efcbed396.jpg)

# 4.2.3 COM3, COM4, COM5, COM6

Serial Port is over-current protected.

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DCD#</td><td>Data Carrier Detect</td><td>2</td><td>DSR#</td><td>Data Set Ready</td></tr><tr><td>3</td><td>RXD</td><td>Receive Data</td><td>4</td><td>RTS#</td><td>Request To Send</td></tr><tr><td>5</td><td>TXD#</td><td>Transmit Data</td><td>6</td><td>CTS#</td><td>Clear To Send</td></tr><tr><td>7</td><td>DTR#</td><td>Data Terminal Ready</td><td>8</td><td>RI#</td><td>Ring Indicator</td></tr><tr><td>9</td><td>GND</td><td>GND</td><td>10</td><td>KEY</td><td>No Pin</td></tr></table>

![1\n2\n9](.imb-m45h-50m-00068-1010/8f237358023f2ea1d185ae39386de3986818f471e1da21d294193319466f2ccf.jpg)

# 4.2.4 LPT1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>STB#</td><td>2</td><td>AFD#</td></tr><tr><td>3</td><td>DATA0</td><td>4</td><td>ERR#</td></tr><tr><td>5</td><td>DATA1</td><td>6</td><td>INIT#</td></tr><tr><td>7</td><td>DATA2</td><td>8</td><td>SLIN#</td></tr><tr><td>9</td><td>DATA3</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>DATA4</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>DATA5</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>DATA6</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>DATA7</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>ACK#</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>BUSY</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>PE</td><td>24</td><td>GND</td></tr><tr><td>25</td><td>SLCT</td><td>26</td><td>NC</td></tr></table>

![1\n2\n25\n26](.imb-m45h-50m-00068-1010/7121f0c6778aa4fdc533f326ecdcc178a69559117b770489e6076aa504291b69.jpg)

# 4.2.5 FP\_AUDIO1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>[Port 2] SENSE_RETURN_B</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>Line-In Port2 Left</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>Line-In Port2 Right</td><td>6</td><td>GND_A</td></tr><tr><td>7</td><td>MIC-In Port2 Left</td><td>8</td><td>SIDE OUT Right</td></tr><tr><td>9</td><td>MIC-In Port2 Right</td><td>10</td><td>SIDE OUT Left</td></tr></table>

![The image shows a vertical, metallic rectangular panel with rounded corners set against a white background. Inside the panel, there are eleven holes arranged in a grid: five rows of two circular holes each, with a single hole centered at the bottom. The number '2' is positioned in black to the left of the panel, and the number '1' is in black to the right.](.imb-m45h-50m-00068-1010/d9142b084711071fac6948fe79f80b69d8693683557a3e021894f64885636c5b.jpg)

# 4.2.6 JCASE1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>SIO_CASEOPEN#</td><td>Case open signal</td></tr></table>

![The image displays a black-and-white schematic drawing on a white background. On the left, there is a vertical rectangle outlined in black. Inside the left edge of the rectangle is a bracket-like shape. To the right of this bracket are two black circles stacked vertically, with a black square positioned directly below the bottom circle. To the right of the rectangle is a small horizontal dash followed by the number 1.](.imb-m45h-50m-00068-1010/9c8b0b5a156ccadff003a64921e26ed277a2500ac8b4de5749cfed3d2eb8e9f2.jpg)

# 4.2.7 CPU\_FAN1, SYS\_FAN1, SYS\_FAN2

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>+12 V</td><td>FAN Power</td></tr><tr><td>3</td><td>Tach</td><td>FAN Tachometer</td></tr><tr><td>4</td><td>PWM</td><td>FAN PWM</td></tr></table>

![The image displays a close-up of a vertical section, likely a panel or document. On the far left, the number **1** is printed vertically. Next to it is a vertical slot containing a column of shapes: a square at the top, followed by five circles arranged vertically below it. To the right of that is another vertical slot with a similar column of a square and five circles, which is shifted slightly downward relative to the left column. At the very top right edge, the number **4** is partially visible.](.imb-m45h-50m-00068-1010/a5bf7c56166c0307054a7d23bd6be382f9d307a999ee948d6481cf8ab1ad4845.jpg)

The fan header supports +12 V at 1 A maximum

# 4.2.8 F\_PANEL1

<table><tr><td>Pin</td><td>Signal</td><td>In/ Out</td><td>Description</td><td>Pin</td><td>Signal</td><td>In/ Out</td><td>Description</td></tr><tr><td colspan="4">HDD Activity LED</td><td colspan="4">Power LED</td></tr><tr><td>1</td><td>HDD_LED+</td><td>Out</td><td>Hard disk LED pull-up to +3.3 V</td><td>2</td><td>PLED_PWR</td><td>Out</td><td>Power LED pull-up to +3.3_DUAL</td></tr><tr><td>3</td><td>HDD_LED#</td><td>Out</td><td>Hard disk active LED</td><td>4</td><td>SUPLED</td><td>Out</td><td>Front panel active LED</td></tr><tr><td colspan="4"></td><td colspan="4"></td></tr><tr><td>5</td><td>Ground</td><td></td><td>Ground</td><td>6</td><td>PANSWIN#</td><td>In</td><td>Power switch</td></tr><tr><td>7</td><td>FP_RESET#</td><td>In</td><td>Reset switch</td><td>8</td><td>Ground</td><td></td><td>Ground</td></tr><tr><td colspan="4"></td><td colspan="4"></td></tr><tr><td>9</td><td>NC</td><td></td><td></td><td>10</td><td>NC</td><td></td><td></td></tr></table>

![The image displays a schematic diagram of a connector. Above the connector is the number **2**. Below the connector on the left side is the number **1**. Inside the rectangular outline of the connector are two rows of pins. The top row consists of 12 circles, each with a vertical line through its center. The bottom row consists of a square with a vertical line through its center on the far left, followed by 11 circles, each with a vertical line through its center. A small arrow points to the right from the left edge of the connector housing.](.imb-m45h-50m-00068-1010/bc7ec62d1e0fc88117bbd76aafb6c589bc84c58d024c204b7931a0b8e3444046.jpg)

# 4.2.9 EATXPWR1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3 V</td><td>13</td><td>+3.3 V</td></tr><tr><td>2</td><td>+3.3 V</td><td>14</td><td>-12 V</td></tr><tr><td>3</td><td>Ground</td><td>15</td><td>Ground</td></tr><tr><td>4</td><td>+5 V</td><td>16</td><td>PS-ON# (power supply remote on/off)</td></tr><tr><td>5</td><td>Ground</td><td>17</td><td>Ground</td></tr><tr><td>6</td><td>+5 V</td><td>18</td><td>Ground</td></tr><tr><td>7</td><td>Ground</td><td>19</td><td>Ground</td></tr><tr><td>8</td><td>PWRGD (Power Good)</td><td>20</td><td>No connect</td></tr><tr><td>9</td><td>+5 V (Standby)</td><td>21</td><td>+5 V</td></tr><tr><td>10</td><td>+12 V</td><td>22</td><td>+5 V</td></tr><tr><td>11</td><td>+12 V</td><td>23</td><td>+5 V</td></tr><tr><td>12</td><td>3.3V</td><td>24</td><td>Ground</td></tr></table>

![12\n24\n1 ▶\n13](.imb-m45h-50m-00068-1010/474e51f45af31555b63ce2fcffe39be4a9b11d8d99c28bb6f8c8ac6e16669d6b.jpg)

# 4.2.10 ATX12V1

<table><tr><td>Pin</td><td>Signal Name</td><td>Pin</td><td>Signal Name</td></tr><tr><td>1</td><td>Ground</td><td>5</td><td>+12V</td></tr><tr><td>2</td><td>Ground</td><td>6</td><td>+12V</td></tr><tr><td>3</td><td>Ground</td><td>7</td><td>+12V</td></tr><tr><td>4</td><td>Ground</td><td>8</td><td>+12V</td></tr></table>

![The image displays a schematic of a connector, shown as a white rectangle with a notch on the right side. Inside are six circles arranged in two columns and three rows, representing pins. The bottom-left circle contains a smaller square. To the left of the connector, the number **2** is aligned with the top row, and the number **1** is aligned with the bottom row, featuring a small arrow pointing right towards the bottom-left pin. To the right of the connector, the number **5** is aligned with the bottom row.](.imb-m45h-50m-00068-1010/974907162e77fb55f010172c9f51128180a0d0f8c849e8d8b64b8e7081104726.jpg)

# 4.2.11 JLPC1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>VCC3</td></tr><tr><td>3</td><td>LPC_AD3</td><td>4</td><td>PLTRST</td></tr><tr><td>5</td><td>LPC_AD1</td><td>6</td><td>LPC_AD2</td></tr><tr><td>7</td><td>LPC_FRAME#</td><td>8</td><td>LPC_AD0</td></tr><tr><td>9</td><td>KEY</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>CLK33M</td><td>12</td><td>GND</td></tr></table>

![A vertical line drawing of a battery. To its left is the number 2. To its right is the number 1 followed by a right-pointing arrow.](.imb-m45h-50m-00068-1010/57a0b6a4d6b023c4fe18d3de217d04fbafb8aca2c01e53525235ebb01d2a65ec.jpg)

# 4.2.12 SPI1

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC3</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>SPI_CS#</td><td>4</td><td>SPI_CLK</td></tr><tr><td>5</td><td>SPI_MISO</td><td>6</td><td>SPI_MOSI</td></tr><tr><td>7</td><td>HOLD#</td><td>8</td><td>Key</td></tr></table>

![The image displays a vertical rectangular outline containing a stack of eight objects. From top to bottom, there are five white circles with black outlines, followed by two black circles, and finally a black square at the very bottom. To the left of the container is the number '2'. To the right of the container are the numbers '4' and '1', stacked vertically with the '4' above the '1'.](.imb-m45h-50m-00068-1010/d9b9976865084af5cc6b6a68c6373c4ebe1bfbc41f00171007ddd363eaa75126.jpg)

# 4.2.13 JPSON1 (Default 2-3)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>PANSWIN#</td><td>Power switch signal</td></tr><tr><td>2</td><td>PSON_AT</td><td>AT mode signal</td></tr><tr><td>3</td><td>GND</td><td></td></tr></table>

![The image displays a black outline icon on a white background. On the left is a right-pointing triangle. To its right is a rectangle containing three shapes arranged horizontally: a square with a smaller square inside, a circle, and a second circle.](.imb-m45h-50m-00068-1010/c7dba12ec6b090bc79cbe15cedcce04b747c7136030da88901f9906b2fbb5e01.jpg)

1

# 4.2.14 JDIO1 (TTL High:3.3V / TTL Low:0V)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DIO1</td><td>2</td><td>DIO17</td></tr><tr><td>3</td><td>DIO2</td><td>4</td><td>DIO18</td></tr><tr><td>5</td><td>DIO3</td><td>6</td><td>DIO19</td></tr><tr><td>7</td><td>DIO4</td><td>8</td><td>DIO20</td></tr><tr><td>9</td><td>DIO5</td><td>10</td><td>DIO21</td></tr><tr><td>11</td><td>DIO6</td><td>12</td><td>DIO22</td></tr><tr><td>13</td><td>DIO7</td><td>14</td><td>DIO23</td></tr><tr><td>15</td><td>DIO8</td><td>16</td><td>DIO24</td></tr><tr><td>17</td><td>DIO9</td><td>18</td><td>DIO25</td></tr><tr><td>19</td><td>DIO10</td><td>20</td><td>DIO26</td></tr><tr><td>21</td><td>DIO11</td><td>22</td><td>DIO27</td></tr><tr><td>23</td><td>DIO12</td><td>24</td><td>DIO28</td></tr><tr><td>25</td><td>DIO13</td><td>26</td><td>DIO29</td></tr><tr><td>27</td><td>DIO14</td><td>28</td><td>DIO30</td></tr><tr><td>29</td><td>DIO15</td><td>30</td><td>DIO31</td></tr><tr><td>31</td><td>DIO16</td><td>32</td><td>DIO32</td></tr><tr><td>33</td><td>NC</td><td>34</td><td>NC</td></tr><tr><td>35</td><td>NC</td><td>36</td><td>NC</td></tr><tr><td>37</td><td>NC</td><td>38</td><td>NC</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>POWER</td></tr></table>

![1\n2\n39\n40](.imb-m45h-50m-00068-1010/4ba4f27eb723c2cb394a575a7a93c2bc1f4385dce8252a28027330d17fc726f0.jpg)

# 4.2.15 JSETCOM1, JSETCOM2

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>UART1_RXD</td><td>2</td><td>COM1_RXD485</td></tr><tr><td>3</td><td>UART1_RXD</td><td>4</td><td>COM1_RXD422</td></tr><tr><td>5</td><td>UART1_RXD</td><td>6</td><td>COM1_RXD232</td></tr><tr><td>7</td><td>COM1_DCD#</td><td>8</td><td>COM1_TX</td></tr><tr><td>9</td><td>COM1_CN_DCD#</td><td>10</td><td>COM1_CN_TX</td></tr><tr><td>11</td><td>TXD485#1</td><td>12</td><td>RXD485P1</td></tr><tr><td>13</td><td>COM1_RX</td><td>14</td><td>COM1_DTR#</td></tr><tr><td>15</td><td>COM1_CN_RX</td><td>16</td><td>COM1_CN_DTR#</td></tr><tr><td>17</td><td>TXD485P1</td><td>18</td><td>RXD485#1</td></tr></table>

![The image displays a schematic diagram of a dual in-line package (DIP) integrated circuit. It features a central rectangular outline representing the IC body, with two parallel rows of small, vertical ovals inside representing the pins.\n\nAt the corners of the rectangle, numbers indicate specific pin positions:\n*   **Top left:** '2'\n*   **Top right:** '18'\n*   **Bottom left:** '1'\n*   **Bottom right:** '17'\n\nA small triangular marker is visible at the bottom left corner to indicate the orientation of pin 1.](.imb-m45h-50m-00068-1010/def9f6764619fa655a985f501ec94e346db1b0c3ce48939e913f33065baace49.jpg)

# 4.2.16 JCMOS1 (Default 1-2)

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td></td></tr><tr><td>2</td><td>RTCRST#</td><td>Reset CMOS</td></tr><tr><td>3</td><td>GND</td><td></td></tr></table>

![The image displays the number '1' followed by a vertical rectangular icon containing three stacked circles, with a small downward arrow above it.](.imb-m45h-50m-00068-1010/eeb712453236863aee7fe6b45389693fabeefbb84a6d1e9f9686898ef1e67840.jpg)

# 4.2.17 JPW4 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>JDIO1. Pin40</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JDIO1. Pin40</td></tr><tr><td>5</td><td>+12V</td><td>6</td><td>JDIO1. Pin40</td></tr></table>

![The image displays the number '1' on the far left and the number '2' on the far right. Centered between them is a vertical domino tile. The top half of the tile features a single dot, while the bottom half features six dots arranged in two vertical columns of three.](.imb-m45h-50m-00068-1010/e8c6e514acf825d33a7bd7b2b529582f306168164f82bf4d0f338008e5a5ba4a.jpg)

# 4.2.18 JPW1 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>JI2C1 Pin1</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JI2C1 Pin1</td></tr><tr><td>5</td><td>+3.3V</td><td>6</td><td>JI2C1 Pin1</td></tr></table>

![The image displays a vertical rectangular panel containing eight circular outlines arranged in four rows and two columns. To the left of the panel is the number '1' and to the right is the number '2'. A small 'x' mark is positioned at the top center of the panel.](.imb-m45h-50m-00068-1010/a848375ebf1704bda2d068f123c0d9e4b42e1feb06ea94bd659b2de0a2557e13.jpg)

# 4.2.19 JPW2 (Default: 3-4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V_DUAL</td><td>2</td><td>JSMB1 Pin1</td></tr><tr><td>3</td><td>NC</td><td>4</td><td>JSMB1 Pin1</td></tr><tr><td>5</td><td>+3.3V_DUAL</td><td>6</td><td>JSMB1 Pin1</td></tr></table>

![The image displays the number '1' on the left and the number '2' on the right. Between the numbers is a tall, narrow rectangle with a black border. Inside the rectangle, at the top center, is a small black triangle pointing downwards. Below the triangle is a grid of six black circles arranged in two columns and three rows.](.imb-m45h-50m-00068-1010/041e870759ce480f4d72ab6f728d754f32447c571c4d50179c74380765dfbc5b.jpg)

# 4.2.20 JSMB1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>NC/+3.3V/+5V select</td></tr><tr><td>2</td><td>SMB_DATA</td><td>SMBUS data</td></tr><tr><td>3</td><td>SMB_CLK</td><td>SMBUS clock</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr></table>

![The image displays the number '1' centered at the top. Below it is a graphic consisting of a small right-pointing triangle (resembling a speaker icon) to the left of a horizontal rectangular bar. Inside the bar are four circles arranged in a row. The leftmost circle contains a square, while the other three circles are empty.](.imb-m45h-50m-00068-1010/ac328c3b40afd57fca2665c023dd1bd93b9c5768a1b4e5ddaf86f9e3e09db039.jpg)

# 4.2.21 JI2C1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>NC/+3.3V/+5V select</td></tr><tr><td>2</td><td>I2C_DATA</td><td>I2C data</td></tr><tr><td>3</td><td>I2C_CLK</td><td>I2C clock</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr></table>

![The image displays the number '1' in the upper left corner. Below it is a horizontal rectangular shape containing four circles arranged in a row. The leftmost circle contains a smaller square shape. To the left of the rectangle is a small triangle pointing to the right.](.imb-m45h-50m-00068-1010/8c6ee8e7ebf097f307a774fe8670af795f942a44ef93a113407ab13d5e6ed692.jpg)

# 4.3 Jumper and Switch Settings

Table 3: Jumper and Switch Definitions

<table><tr><td colspan="3">Jumper Block</td></tr><tr><td>Item</td><td>Description</td><td>Remarks</td></tr><tr><td>JCMOS1</td><td>One 1x3 2.54mm pin header1-2 (default) = Normal, 2-3 = Clear CMOS</td><td>Normal (Default)&lt;img src="images/33f946a431bf5796609ed9b39f8570e262650990b0ceb28fbdabd7b7e054de3b.jpg"/&gt;Clear CMOS&lt;img src="images/c52e2be37ab5f3035cc9ac01bfbdb9bd3c0bd47520f7e1fdc0cb25060117d89b.jpg"/&gt;</td></tr><tr><td>JPSON1</td><td>One 1x3 2.54mm pin header1-2 = AT Mode; 2-3 (default) = ATX mode</td><td>AT mode&lt;img src="images/cb2bad6748bcdec2577101b97ea2f8b89880318403cd1a7c9a18d4bb4c5ef4a6.jpg"/&gt;ATX mode(Default)&lt;img src="images/91e8eef1aa4e033e6364006f8b455d11fd7515c65dd4b97431c1313e6829696e.jpg"/&gt;</td></tr><tr><td>JSETCOM1JSETCOM2</td><td>One 2x9 2.0mm pin headerRS232: 5-6, 7-9, 8-10, 13-15, 14-16(default)RS422: 3-4, 9-11, 10-12, 15-17, 16-18RS485: 1-2, 9-11, 10-12, 15-17, 16-18</td><td>&lt;img src="images/3ac14ac57e70fab880ac7a4898f492616e87148a1f83dfc23f8d6f93c4ede098.jpg"/&gt; &lt;img src="images/835fa63780b8d2737d0edb6371a6cd01123d430de3d31335be9a63e649df1301.jpg"/&gt; &lt;img src="images/2b3fa96b98bfa2c70c85dcf59a5fccfd487e7638ee34ca68d092fe920978f79b.jpg"/&gt;</td></tr></table>

<table><tr><td colspan="7">Jumper Block</td></tr><tr><td rowspan="4">COM1_S1~S4 master/slave and terminal selection</td><td></td><td>S1</td><td>S2</td><td>S3</td><td>S4</td><td rowspan="4">(Default)&lt;img src="images/f1d01f87e96869d7c95853c4bb2f8be350436586ad062b00a9fbfc8e48523521.jpg"/&gt;</td></tr><tr><td>RS-232</td><td>2-3</td><td>2-3</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-485</td><td>1-2</td><td>1-2</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-422</td><td>1-2</td><td>1-2</td><td>1-2</td><td>1-2</td></tr><tr><td rowspan="4">COM2_S1~S4 master/slave and terminal selection</td><td></td><td>S1</td><td>S2</td><td>S3</td><td>S4</td><td rowspan="4">(Default)&lt;img src="images/23298fb05822b2c884b7b6f38d326abe901bc9b7f4cec126c5b4b5b93205afec.jpg"/&gt;</td></tr><tr><td>RS-232</td><td>2-3</td><td>2-3</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-485</td><td>1-2</td><td>1-2</td><td>2-3</td><td>2-3</td></tr><tr><td>RS-422</td><td>1-2</td><td>1-2</td><td>1-2</td><td>1-2</td></tr></table>

<table><tr><td colspan="3">Jumper Block</td></tr><tr><td>JPW4</td><td>One 2x3 2.0mm pin headerNC (default)/+5V/+12V</td><td>NC (Default)1 2&lt;img src="images/db38947037ea4d9e832986b0477bb663c2d114e7b06b27ec97bf55dfc347b8a9.jpg"/&gt;____+5V1 2&lt;img src="images/9fd58309cd57b520da587d993648753060c7940f2fad6f506d45d2bb4fdbd7b8.jpg"/&gt;____+12V1 2&lt;img src="images/5873359370720167d3f7217a0861d196f6bfa57bd908cce9e893e05b5e847b9b.jpg"/&gt;</td></tr><tr><td>JPW1</td><td>One 2X3 2.0mm pin headerNC (default)/+5V/+3.3V</td><td>NC (Default)1 2&lt;img src="images/3ddb829170fd8fbcc217522dd73a1192aa49f41f436770ed09480869075958d5.jpg"/&gt;____+5V1 2&lt;img src="images/e2c4715bda98ca93b1a4a9036a0096eadc4210ace2837610ae64b860e4be497e.jpg"/&gt;____+3.3V1 2&lt;img src="images/b24c1160a9cde915b9f2f12db480289c4f0a74a574702c60162cdf8e706b34e3.jpg"/&gt;____</td></tr><tr><td>JPW2</td><td>One 2x3 2.0mm pin headerNC (default)/+5V/+3.3V</td><td>NC (Default)1 2&lt;img src="images/a695756b7ed7b5c0995b9fe5eeb2bc270a50793aee52eadee8cd61d63d68bf41.jpg"/&gt;+5V1 2&lt;img src="images/9fd58309cd57b520da587d993648753060c7940f2fad6f506d45d2bb4fdbd7b8.jpg"/&gt;+3.3V1 2&lt;img src="images/5873359370720167d3f7217a0861d196f6bfa57bd908cce9e893e05b5e847b9b.jpg"/&gt;</td></tr></table>

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# 5 Driver Installation

Download the requisite drivers for your system from the IMB-M45H product page at:

https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/ATXMotherboards/IMB-M45H

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# 6 System Resources

# 6.1 System Memory Map

Table 4: System Memory Map

<table><tr><td>Address Range</td><td>Address Range</td><td>Size</td><td>Description</td></tr><tr><td>(4GB-2MB)</td><td>FFE00000 – FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB-18MB) – (4GB-17MB-1)</td><td>FEE00000 – FEEFFFFFF</td><td>1 MB</td><td>MSI Interrupts</td></tr><tr><td>(4GB-20MB) – (4GB-19MB-1)</td><td>FEC00000 – FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB – 16MB</td><td>F00000 – FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>1MB -15MB</td><td>100000 - EFFFFFF</td><td>14MB</td><td>Main Memory</td></tr><tr><td>0K –1MB</td><td>00000 – FFFFFFF</td><td>1MB</td><td>DOS Compatibility Memory</td></tr></table>

# 6.2 I/O Map

Table 5: IO Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>0000-0CF7</td><td>PCI Express Root Complex</td></tr><tr><td>0D00-FFFF</td><td>PCI Express Root Complex</td></tr><tr><td>0020-0021</td><td>Programmable interrupt controller</td></tr><tr><td>0024-0025</td><td>Programmable interrupt controller</td></tr><tr><td>0028-0029</td><td>Programmable interrupt controller</td></tr><tr><td>002C-002D</td><td>Programmable interrupt controller</td></tr><tr><td>0030-0031</td><td>Programmable interrupt controller</td></tr><tr><td>0034-0035</td><td>Programmable interrupt controller</td></tr><tr><td>0038-0039</td><td>Programmable interrupt controller</td></tr><tr><td>003C-003D</td><td>Programmable interrupt controller</td></tr><tr><td>00A0-00A1</td><td>Programmable interrupt controller</td></tr><tr><td>00A4-00A5</td><td>Programmable interrupt controller</td></tr><tr><td>00A8-00A9</td><td>Programmable interrupt controller</td></tr><tr><td>00AC-00AD</td><td>Programmable interrupt controller</td></tr><tr><td>00B0-00B1</td><td>Programmable interrupt controller</td></tr><tr><td>00B4-00B5</td><td>Programmable interrupt controller</td></tr><tr><td>00B8-00B9</td><td>Programmable interrupt controller</td></tr><tr><td>00BC-00BD</td><td>Programmable interrupt controller</td></tr><tr><td>04D0-04D1</td><td>Programmable interrupt controller</td></tr><tr><td>04D0-04D1</td><td>Programmable interrupt controller</td></tr><tr><td>002E-002F</td><td>Motherboard resources</td></tr><tr><td>004E-004F</td><td>Motherboard resources</td></tr><tr><td>0061-0061</td><td>Motherboard resources</td></tr><tr><td>0063-0063</td><td>Motherboard resources</td></tr><tr><td>0065-0065</td><td>Motherboard resources</td></tr><tr><td>0067-0067</td><td>Motherboard resources</td></tr><tr><td>0070-0070</td><td>Motherboard resources</td></tr><tr><td>0080-0080</td><td>Motherboard resources</td></tr><tr><td>0092-0092</td><td>Motherboard resources</td></tr><tr><td>00B2-00B3</td><td>Motherboard resources</td></tr><tr><td>0680-069F</td><td>Motherboard resources</td></tr><tr><td>FFFF-FFFF</td><td>Motherboard resources</td></tr><tr><td>1800-18FE</td><td>Motherboard resources</td></tr><tr><td>164E-164F</td><td>Motherboard resources</td></tr><tr><td>0040-0043</td><td>System timer</td></tr><tr><td>0050-0053</td><td>System timer</td></tr><tr><td>0070-0077</td><td>System CMOS/real time clock</td></tr><tr><td>00F0-00F0</td><td>Numeric data processor</td></tr><tr><td>02E0-02E7</td><td>COM5</td></tr><tr><td>02E8-02EF</td><td>COM4</td></tr><tr><td>02F8-02FF</td><td>COM2</td></tr><tr><td>0378-037F</td><td>Printer Port</td></tr><tr><td>03E0-03E7</td><td>COM6</td></tr><tr><td>03E8-03EF</td><td>COM3</td></tr><tr><td>03F8-03FF</td><td>COM1</td></tr><tr><td>E000-EFFF</td><td>Chipset PCI Express Root Port</td></tr><tr><td>E000-EFFF</td><td>PCI-to-PCI Bridge</td></tr><tr><td>F000-F03F</td><td>Intel HD Graphic 630</td></tr><tr><td>F040-F05F</td><td>SMBUS</td></tr><tr><td>F090-F097</td><td>Standard SATA AHCI Controller</td></tr><tr><td>F080-F083</td><td>Standard SATA AHCI Controller</td></tr><tr><td>F060-F07F</td><td>Standard SATA AHCI Controller</td></tr></table>

# 6.3 Interrupt Request (IRQ) Lines

# 6.3.1 IRQ Lines PIC Mode

Table 6: IRQ Lines PIC Mode

<table><tr><td>IRQ#</td><td>Device</td></tr><tr><td>0</td><td>System timer</td></tr><tr><td>3</td><td>COM2</td></tr><tr><td>4</td><td>COM1</td></tr><tr><td>5</td><td>COM3, COM4</td></tr><tr><td>8</td><td>System CMOS/real time clock</td></tr><tr><td>10</td><td>COM5, COM6</td></tr><tr><td>13</td><td>Numeric data processor</td></tr><tr><td>14</td><td>Intel Serial IO GPIO Host Controller</td></tr><tr><td>15</td><td>Intel Chipset Smbus</td></tr><tr><td>16</td><td>HD Audio Controller</td></tr></table>

Note: These IRQs can be used for PCI devices when onboard device is disabled.

# 6.3.2 IRQ Lines APIC Mode

Table 7 IRQ Lines APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>System Counter</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>2</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port3 (COM3)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port4 (COM4)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>7</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>10</td><td>Serial Port5 (COM5)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>10</td><td>Serial Port6 (COM6)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>N/A</td><td>N/A</td><td></td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Intel IO GPIO Host Controller</td><td>N/A</td><td>Note (1)</td></tr><tr><td>16</td><td>High Definition Audio Controller</td><td>N/A</td><td></td></tr><tr><td>54-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Note (1)</td></tr></table>

Note: These IRQs can be used for PCI devices when onboard device is disabled.

# 6.4 PCI Features

# 6.4.1 PCI Configuration Space Map

Table 8 PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel VGA Controller</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>Intel USB 3.0 XHCI</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>Intel Data acquisition/signal process</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel Communication device</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Internal</td><td>Intel AHCI 1.0 controller</td></tr><tr><td>00h</td><td>1Dh</td><td>00h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Dh</td><td>03h</td><td>Internal</td><td>Intel PCI-to-PCI bridge PCIe</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel ISA bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>Intel HD Audio Device</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>Intel SMBU</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>Intel Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>06h</td><td>Internal</td><td>Intel Ethernet Controller</td></tr><tr><td>01h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller PCIe</td></tr><tr><td>02h</td><td>00h</td><td>00h</td><td>Internal</td><td>ITE PCI to-PCI Bridge</td></tr></table>

Note: The bus number change if the PEG/PCIE port has a device.

# 6.4.2 PCI Interrupt Routing Map

Table 9 PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>LpcBridge</td><td>High Definition Audio</td><td>SMBus</td><td>PCIE Root Port #9 (LAN1)</td><td>PCIE Root Port #5 (PCIE x4)</td><td>PCIE Root Port #12 (ITE8892)</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTD:19</td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td></td><td>INTB:17</td><td>INTB:17</td><td>INTA:16</td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td></td><td>INTC:18</td><td>INTC:18</td><td>INTB:17</td></tr><tr><td>Int3</td><td>INTD:19</td><td></td><td></td><td>INTD:19</td><td>INTD:19</td><td>INTC:18</td></tr></table>

<table><tr><td>INT Line</td><td>PCI Slot 1</td><td>PCI Slot 2</td><td>PCI Slot 3</td><td>PCI Slot 4</td><td>PCI Slot 5</td><td>PCIE Root Port #11 (LAN2)</td></tr><tr><td>Int0</td><td>INTA:17</td><td>INTA:18</td><td>INTA:19</td><td>INTA:16</td><td>INTA:17</td><td>INTC:18</td></tr><tr><td>Int1</td><td>INTB:18</td><td>INTB:19</td><td>INTB:16</td><td>INTB:17</td><td>INTB:18</td><td>INTD:19</td></tr><tr><td>Int2</td><td>INTC:19</td><td>INTC:16</td><td>INTC:17</td><td>INTC:18</td><td>INTC:19</td><td>INTA:16</td></tr><tr><td>Int3</td><td>INTD:16</td><td>INTD:17</td><td>INTD:18</td><td>INTD:19</td><td>INTD:16</td><td>INTB:17</td></tr></table>

# 6.5 SMBus Slave Addresses

Table 10 SMBus Slave Addresses

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMM A</td><td>A0h</td></tr><tr><td>DIMM B</td><td>A4h</td></tr></table>

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# 7 BIOS Setup

# 7.1 Menu Structure

This section presents the primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections describe the submenus and options for each menu item. The default options are presented in bold, and the function of each setting is described in the right hand column of the table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td></tr><tr><td>- BIOS Information- System Date- System Time</td><td>- CPU Configuration ▶- PCH-FW Configuration ▶- ACPI Settings ▶- NCT6106D Super IO Configuration ▶- NCT6106D HW Monitor ▶- S5 RTC Wake Settings ▶- Serial Port Console Redirection ▶- Intel TXT Information ▶- USB Configuration ▶- CSM Configuration ▶- NVME Configuration ▶- Network Stack Configuration ▶</td><td>- System Agent (SA) Configuration ▶- PCH-IO Configuration ▶</td></tr><tr><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>- Administrator Password Description- User Password</td><td>- Boot Configuration ▶- Driver Option Priorities ▶- Fixed Boot Oder Priorities ▶</td><td>- Save &amp; Exit ▶- Default Options ▶- Boot Override ▶</td></tr></table>

# Notes:

► indicates a submenu Gray text indicates info only

# 7.2 Main Menu

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.

7.2.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>American Megatrends</td><td></td></tr><tr><td>Core Version</td><td>x.xx</td><td></td></tr><tr><td>Compliancy</td><td>UEFI x.x; PI x.x</td><td></td></tr><tr><td>Project Version</td><td>IMB-M45H x.xx.xx</td><td></td></tr><tr><td>Build Date and Time</td><td>mm/dd/yyyy hh:mm:ss</td><td></td></tr><tr><td>Access Level</td><td>Administrator</td><td></td></tr><tr><td>Memory Information</td><td></td><td></td></tr><tr><td>Total Memory</td><td>xxxx MB</td><td></td></tr><tr><td>Memory Frequency</td><td>xxxx MHz</td><td></td></tr><tr><td>Power Type</td><td>[ATX Mode]</td><td></td></tr><tr><td>System Date</td><td>mm/dd/yyyy</td><td>Sets the system date. Use &lt;Tab&gt; to switch between elements.</td></tr><tr><td>System Time</td><td>hh:mm:ss</td><td>Sets the system time. Use &lt;Tab&gt; to switch between elements.</td></tr></table>

# 7.3 Advanced Menu

This menu contains the settings for most of the user interfaces in the system.

7.3.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info Only</td><td>CPU type</td></tr><tr><td>ID</td><td>Info Only</td><td>CPU ID</td></tr><tr><td>Speed</td><td>Info Only</td><td>CPU Speed (xxxx MHz)</td></tr><tr><td>L1 Data Cache</td><td>Info Only</td><td>CPU L1 Data Cache</td></tr><tr><td>L1 Instruction Cache</td><td>Info Only</td><td>CPU L1 Instruction Cache</td></tr><tr><td>L2 Cache</td><td>Info Only</td><td>CPU L2 Cache</td></tr><tr><td>L3 Cache</td><td>Info Only</td><td>CPU L3 Cache</td></tr><tr><td>L4 Cache</td><td>Info Only</td><td>CPU L4 Cache</td></tr><tr><td>VMX</td><td>Info Only</td><td>CPU Virtual Machine Extension</td></tr><tr><td>SMX/TXT</td><td>Info Only</td><td>CPU Safer Mode Extension / Trusted Execution Technology</td></tr><tr><td>C6DRAM</td><td>DisabledEnabled</td><td>Enables or Disables moving of DRAM content to PRM memory when CPU is in C6 state</td></tr><tr><td>SW Guard Extensions (SGX)</td><td>Software ControlledEnabledDisabled</td><td>Sets Software Guard Extensions (SGX)</td></tr><tr><td>Select Owner EPOCH input type</td><td>No Change in Owner ECOPHsChange to NewRandom Owner ECOPHsManual User Defined Owner OPCHs</td><td>There are three Owner EPOCH modes (Each EPOCH is 64-bit):</td></tr><tr><td>Intel (VMX)Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Processor Cores</td><td>All/1/2/3/4/5</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Hyper-Threading</td><td>DisabledEnabled</td><td>Enables or Disables Hyper-Threading</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enables or Disables Turbo Mode</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enables or Disables utilization of additional hardware capabilities provided by Intel Trusted Execution Technology.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>DisabledEnabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enables or Disables CPU Power Management.Allows CPU to go to C States when it's not 100% utilized.</td></tr><tr><td>Enhanced C-state</td><td>DisabledEnabled</td><td>Enables or Disables C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>Package C state limit</td><td>AutoCPU DefaultC10C9C8C7sC7C6C3C2C0/C1</td><td>Maximum Package C State Limit Setting.CPU Default: Leaves to Factory default value.Auto: Initializes to deepest available Package C State Limit.</td></tr></table>

# 7.3.2 Advanced > PCH-FW Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ME Firmware Version</td><td>Info Only</td><td>PCH Firmware Version</td></tr><tr><td>ME Firmware Mode</td><td>Info Only</td><td>PCH Firmware Mode</td></tr><tr><td>ME Firmware SKU</td><td>Info Only</td><td>PCH Firmware SKU</td></tr><tr><td>ME Firmware Status 1</td><td>Info Only</td><td>PCH Firmware Status</td></tr><tr><td>ME Firmware Status 2</td><td>Info Only</td><td>PCH Firmware Status</td></tr><tr><td>ME State</td><td>Disabled Enabled</td><td>When Disabled ME will be put into ME Temporarily Disabled Mode.</td></tr><tr><td>ME UnLock Control</td><td>Lock Unlock</td><td>ME Unlock switch function.Note: This function will automatically recover settings from Unlock to Lock after powering on the system.</td></tr></table>

# 7.3.3 Advanced > ACPI Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>S3 Video Repost</td><td>DisabledEnabled</td><td>Enables or Disables S3 Video Repost</td></tr><tr><td>PCIE# Wake from S5</td><td>DisabledEnabled</td><td>Enables or Disables PCIE to wake the system from S5.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables or Disables Hibernation.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend DisabledS3 only(Suspend to RAM)</td><td>Enables or Disables ACPI Sleep State</td></tr><tr><td>Wake on Ring</td><td>DisabledEnabled</td><td>Enables or Disables wake on ring function under ACPI S3/S4/S5.</td></tr></table>

7.3.4 Advanced > NCT6106D SuperIO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 1 (COMA)</td></tr><tr><td>Serial Port 2 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 2 (COMB)</td></tr><tr><td>Serial Port 3 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 3 (COMC)</td></tr><tr><td>Serial Port 4 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 4 (COMD)</td></tr><tr><td>Serial Port 5 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 5 (COME)</td></tr><tr><td>Serial Port 6 Configuration▶</td><td>Submenu</td><td>Sets Parameters of Serial Port 6 (COMF)</td></tr><tr><td>Parallel Port Configuration▶</td><td>Submenu</td><td>Sets Parameters of Parallel Port (LPT/LPTE)</td></tr><tr><td>WatchDog Count Mode</td><td>SecondMinute</td><td>WatchDog Count Mode Selection</td></tr><tr><td>WatchDog TimeOut Value</td><td>0</td><td>WatchDog Timeout Value, 0 = disabled.</td></tr><tr><td>Chassis Opened Warning</td><td>DisabledEnabled</td><td>Enables or Disables chassis intrusion detection. Note: If chassis tamper occurs, you can only enter setup to clear this error.</td></tr><tr><td>ErP/EuP S5 Support</td><td>DisabledEnabled</td><td>Enables or Disables ErP/EuP S5 support</td></tr></table>

7.3.5 Advanced > NCT6106D SuperIO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=3F8hIRQ=4</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal setting for Super IO Device</td></tr><tr><td>RS485 Auto Flow</td><td>DisabledEnabled</td><td>Enables or Disables RS485 Auto Flow Control Function (Make sure to set RS485 on the COM1 jumper header if this setting is enabled.)</td></tr></table>

7.3.6 Advanced > NCT6106D SuperIO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2F8hIRQ=3</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>RS485 Auto Flow</td><td>DisabledEnabled</td><td>Enables or Disables RS485 Auto Flow Control Function (Make sure to set RS485 on the COM2 jumper header if this setting is enabled.)</td></tr></table>

7.3.7 Advanced > NCT6106D SuperIO Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=3E8hIRQ=5</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.8 Advanced > NCT6106D SuperIO Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2E8h; IRQ=5</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.9 Advanced > NCT6106D SuperIO Configuration > Serial Port 5 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2E0h; IRQ=10</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.10 Advanced > NCT6106D SuperIO Configuration > Serial Port 6 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables or Disables Serial Port(COM)</td></tr><tr><td>Device Settings</td><td>IO=3E0h; IRQ=10</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr></table>

7.3.11 Advanced > NCT6106D SuperIO Configuration > Parallel Port Configuration

<table><tr><td>Parallel Port</td><td>Options</td><td>Note</td></tr><tr><td>Parallel Port</td><td>DisabledEnabled</td><td>Enables or Disables Parallel Port (LPT/LPTE)</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Serial Port device settings</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>Device Mode</td><td>STD Printer ModeSPP ModeEPP-1.9 and SPP ModeEPP-1.7 and SPP ModeECP modeECP and EPP 1.9 modeECP and EPP 1.7 mode</td><td>Changes the Printer Port mode.</td></tr></table>

7.3.12 Advanced > NCT6106D HW Monitor

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info Only</td><td>Smart Fan Function Page</td></tr><tr><td>System temperature</td><td>Info Only</td><td>xx C</td></tr><tr><td>CPU temperature (PECI)</td><td>Info Only</td><td>xx C</td></tr><tr><td>SYS_Fan1 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>CPU_Fan1 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>SYS_Fan2 Speed</td><td>Info Only</td><td>xx RPM</td></tr><tr><td>VCORE</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>+12V</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>+5V</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>5V_Dual</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>AVCC</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>3VSB</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>3VCC</td><td>Info Only</td><td>x.xxxV</td></tr><tr><td>VBAT</td><td>Info Only</td><td>x.xxxV</td></tr></table>

7.3.13 Advanced > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan Function</td><td>DisabledEnabled</td><td>Enables or Disables Smart Fan Function</td></tr><tr><td>Smart Fan Mode Configuration▶</td><td>Submenu</td><td>Smart Fan Mode Configuration</td></tr></table>

7.3.14 Advanced > Smart Fan > Smart Fan Mode Configuration – Manual Mode

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SYS Smart Fan1 Mode</td><td>Manual ModeThermal Cruise Mode</td><td>SYS Smart Fan1 Mode</td></tr><tr><td>SYS expect PWM Output/DC Voltage</td><td>255</td><td>System FAN1 expect PWM Output/DC Voltage</td></tr><tr><td>CPU Smart Fan Mode</td><td>Manual ModeThermal Cruise Mode</td><td>CPU Smart Fan Mode</td></tr><tr><td>CPU expect PWM Output/DC Voltage</td><td>255</td><td>CPU FAN expect PWM Output/DC Voltage</td></tr><tr><td>SYS Smart Fan2 Mode</td><td>Manual ModeThermal Cruise Mode</td><td>SYS Smart Fan2 Mode</td></tr><tr><td>SYS expect PWM Output/DC Voltage</td><td>255</td><td>CHA FAN2 expect PWM Output/DC Voltage</td></tr></table>

7.3.15 Advanced > Smart Fan > Smart Fan Mode Configuration – Thermal Cruise Mode

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xxxFAN Target Temperature</td><td>50</td><td>FAN Target Temperature</td></tr><tr><td>xxxFAN Tolerance of Target Temp</td><td>5</td><td>FAN Tolerance of Target Temperature</td></tr><tr><td>xxxFAN Step Up Time</td><td>10</td><td>FAN step up time, 1 step = 0.1 second</td></tr><tr><td>xxxFAN Step Down Time</td><td>10</td><td>FAN step down time, 1 step = 0.1 second</td></tr><tr><td>xxxFAN Start-Up Value</td><td>127</td><td>FAN Start-Up Value</td></tr><tr><td>xxxFAN Stop Value</td><td>127</td><td>FAN Stop Value</td></tr></table>

7.3.16 Advanced > S5 RTC Wake Setting

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Wake System From S5</td><td>DisabledEnabled</td><td>Enables or Disables System wake on alarm event.</td></tr></table>

7.3.17 Advanced > Serial Port Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Enables or Disables Console Redirection</td></tr><tr><td>Console Redirection Settings▶</td><td>Submenu</td><td>Show when Console Redirection is enabled</td></tr></table>

7.3.18 Advanced > Serial Port Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VY100VT100+VT-UTF8ANSI</td><td>Type Select</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Select serial port transmission speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission error.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enables or Disables VT-UTF8 Combo Key</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled, only a test will be sent.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables or Disables extended terminal resolution.</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Selects FunctionKey and KeyPad on Putty.</td></tr></table>

7.3.19 Advanced > Intel TXT Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Chipset</td><td>Info Only</td><td></td></tr><tr><td>BIOS Acm</td><td>Info Only</td><td></td></tr><tr><td>CPU Txt</td><td>Info Only</td><td></td></tr><tr><td>Error Code</td><td>Info Only</td><td></td></tr><tr><td>Class Code</td><td>Info Only</td><td></td></tr><tr><td>Major Code</td><td>Info Only</td><td></td></tr><tr><td>Minor Code</td><td>Info Only</td><td></td></tr></table>

7.3.20 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Note</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enables or Disables UEFI Network Stack.</td></tr></table>

7.3.21 Advanced > CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>DisabledEnabled</td><td>Enables or Disables CSM Support</td></tr><tr><td>CSM16 Module Version</td><td></td><td></td></tr><tr><td>Option ROM execution</td><td></td><td></td></tr><tr><td>Network</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI device</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy other device OpROM.</td></tr></table>

7.3.22 Advanced > NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVMe controller and Drive information</td><td>Info Only</td><td>NVMe Device Options Settings</td></tr><tr><td>Show device</td><td>Info Only</td><td></td></tr></table>

7.3.23 Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Devices</td><td>Show current USB devices</td><td></td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables or Disables Legacy USB support.</td></tr><tr><td>XHCI Hand-Off</td><td>DisabledEnabled</td><td>This is a workaround for OSes without XHCI hand-off support.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enables or Disables USB Mass Storage Driver Support</td></tr></table>

# 7.4 Chipset Menu

This menu contains settings for other user interfaces in the system.

7.4.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info Only</td><td></td></tr><tr><td>VT-d Capability</td><td>Info Only</td><td></td></tr><tr><td>Memory Configuration▶</td><td>Submenu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration▶</td><td>Submenu</td><td>Graphics Configuration</td></tr><tr><td>PEG Port Configuration▶</td><td>Submenu</td><td>PEG Port Options</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>VT-d capability</td></tr></table>

7.4.2 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info Only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info Only</td><td></td></tr><tr><td>Memory Timings</td><td>Info Only</td><td></td></tr><tr><td>DIMM_A1</td><td>Info Only</td><td></td></tr><tr><td>DIMM_B1</td><td>Info Only</td><td></td></tr><tr><td>Max TOULUD</td><td>Dynamic</td><td>Maximum value of TOULUD</td></tr></table>

7.4.3 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIE</td><td>Selects which of IGFX/PEG/PCIE Graphics device should be Primary Display</td></tr><tr><td>Internal Graphics</td><td>AutoDisableEnable</td><td>Keeps IGFX enabled based on the setup options.</td></tr><tr><td>PSMI Support</td><td>Disable</td><td></td></tr><tr><td>DVMT Pre-Allocated</td><td>0326448121620242832_F736404448525660 M</td><td>Selects DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>256M128MMAX</td><td>Selects DVMT 5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

7.4.4 Chipset > System Agent (SA) Configuration > PEG port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG 0:1:0</td><td></td><td></td></tr><tr><td>Enable Root port</td><td>DisabledEnabledAuto</td><td>Enables or Disables the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configures PEG 0:1:0 Max Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>DisabledEnabled</td><td>Detects Non-Compliance PCI Express Device in PEG</td></tr></table>

7.4.5 Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration▶</td><td>Submenu</td><td>PCI Express Configuration settings</td></tr><tr><td>SATA And RST Configuration▶</td><td>Submenu</td><td>SATA Device Options Setting</td></tr><tr><td>USB Configuration▶</td><td>Submenu</td><td>USB Configuration settings</td></tr><tr><td>HD Audio Configuration▶</td><td>Submenu</td><td>HD Audio Subsystem Configuration Settings</td></tr><tr><td>Serial IO Configuration▶</td><td>Submenu</td><td>Serial IO Configuration Settings</td></tr><tr><td>LAN1 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard NIC.</td></tr><tr><td>LAN Option-ROM</td><td>DisabledEnabled</td><td>Shows if Network to Legacy</td></tr><tr><td>Wake on Lan Enable</td><td>DisabledEnabled</td><td>Enables or Disables integrated LAN to wake the system.</td></tr><tr><td>LAN2 Controller</td><td>DisabledEnabled</td><td>Enables or Disables onboard Lan2</td></tr><tr><td>LAN Option-ROM</td><td>DisabledEnabled</td><td>Shows if Network to Legacy</td></tr><tr><td>Restore AC Power Loss</td><td>Power On/Power off/Last State</td><td>Specifies what state to go to when power is reapplied after a power failure (G3 state)</td></tr><tr><td>GPIO Group Control</td><td>DisabledEnabled</td><td>Configures the digital GPIO pins</td></tr></table>

7.4.6 Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info only</td><td></td></tr><tr><td>PCI Express Root Port 5(PCIEx4_1)▶</td><td>Submenu</td><td>PCI Express Root Port 5 Settings.</td></tr><tr><td>PCIE Port 9 is assigned to LAN1</td><td>N/A</td><td></td></tr><tr><td>PCIE Port 11 is assigned to LAN2</td><td>N/A</td><td></td></tr><tr><td>PCIE Port 12 is assigned to ITE8892</td><td>N/A</td><td></td></tr></table>

7.4.7 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port 5

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 5</td><td>DisabledEnabled</td><td>Controls the PCI Express Root Port.</td></tr><tr><td>ASPM 5</td><td>AutoL0sL1L1L0sDisabled</td><td>Sets the ASPM Level: Force L0s – Force all link to L0s StateAUTO – BIOS auto configureDISABLE – Disables ASPM</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2</td><td>Configures PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>DisabledEnabled</td><td>Detects Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr></table>

7.4.8 Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>SATA Configuration</td><td>Options</td><td>Note</td></tr><tr><td>SATA Controller(s)</td><td>DisabledEnabled</td><td>Enables or Disables SATA Device</td></tr><tr><td>SATA Mode</td><td>AHCI</td><td>Determines how SATA controllers operate.</td></tr><tr><td>Serial ATA Port 1</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td></td><td></td></tr><tr><td>Port 1</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 2</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td></td><td></td></tr><tr><td>Port 2</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 3</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td></td><td></td></tr><tr><td>Port 3</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr><tr><td>Serial ATA Port 4</td><td>Show device</td><td></td></tr><tr><td>Software Preserve</td><td></td><td></td></tr><tr><td>Port 4</td><td>DisabledEnabled</td><td>Enables or Disables SATA Port</td></tr></table>

7.4.9 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Disable Compliance Mode</td><td>DisabledEnabled</td><td>Options to disable Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode.</td></tr><tr><td>USB12 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB34 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB56 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB78 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr><tr><td>USB910 Standby Power Support</td><td>DisabledEnabled</td><td>Enables or Disables USB standby power</td></tr></table>

7.4.10 Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>DisabledEnabledAuto</td><td>Controls Detection of the HD-Audio device.</td></tr></table>

7.4.11 Chipset > PCH-IO Configuration > Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>DisabledEnabled</td><td>Enables or Disables Serial IO Controller</td></tr></table>

# 7.5 Security Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Sets Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Sets User Password</td></tr></table>

7.6 Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info Only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1 (seconds)</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means infinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or Disables Quiet Boot option</td></tr><tr><td>Support Native Resolution</td><td>Disabled Enabled</td><td>Enables or Disables Native Resolution support</td></tr><tr><td>Driver Option Priorities</td><td>Info Only</td><td></td></tr><tr><td>Boot mode select</td><td>LEGACY UEFI</td><td>Selects Legacy or UEFI boot mode</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Info Only</td><td></td></tr><tr><td>1st Boot</td><td>Hard Disk</td><td>Sets the system boot order.</td></tr><tr><td>2nd Boot</td><td>NVME</td><td>Sets the system boot order.</td></tr><tr><td>3rd Boot</td><td>CD/DVD</td><td>Sets the system boot order.</td></tr><tr><td>4th Boot</td><td>USB Hard Disk</td><td>Sets the system boot order.</td></tr><tr><td>5th Boot</td><td>USB CD/DVD</td><td>Sets the system boot order.</td></tr><tr><td>6th Boot</td><td>USB Key</td><td>Sets the system boot order.</td></tr><tr><td>7th Boot</td><td>USB Floppy</td><td>Sets the system boot order.</td></tr><tr><td>8th Boot</td><td>Network</td><td>Sets the system boot order.</td></tr></table>

7.7 Save & Exit Menu

<table><tr><td>Save &amp; Exit</td><td>Options</td><td>Note</td></tr><tr><td>Save Changes and Exit</td><td>YesNo</td><td>Exits system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>YesNo</td><td>Exits system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>YesNo</td><td>Resets the system after saving the changes.</td></tr><tr><td>Default Options</td><td>YesNo</td><td></td></tr><tr><td>Restore Defaults</td><td>YesNo</td><td>Restores or Loads Default values for all Setup options.</td></tr><tr><td>Boot Override</td><td></td><td></td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td>Attempts to Launch EFI Shell application (Shell.efi) from one of the available filesystem devices</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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