# LEC-ALN/ASL

User’s Guide

intel

![Close-up of a blue printed circuit board with integrated circuits and gold connectors (no visible text or symbols)](.lec-aln-asl-manual-50m-72519-1020-12/fc8cfee26a53e4dee0a522d3bda8c660e51a82eef0712be77df673506734ffc6.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2024-09-02</td><td>AL</td></tr><tr><td>1.1</td><td>Specifications and pinout and signal descriptions updated</td><td>2025-04-11</td><td>AL</td></tr><tr><td>1.2</td><td>Introduction, specifications, block diagram, and pinout and signal descriptions updated</td><td>2025-05-27</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangular warning sign with a thick black border containing a black exclamation point in the center.](.lec-aln-asl-manual-50m-72519-1020-12/bb02023702586d07c3b9cf09d6fa4660110812547ac9225cea2555ea5e755691.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black-and-white line drawing of a wheeled trash bin (or waste container) that is crossed out by a large 'X'. This is the standard symbol indicating that the item should not be disposed of in general household waste. Below the symbol is a solid black rectangular block that obscures the bottom portion of the image. There is no visible text in the image.](.lec-aln-asl-manual-50m-72519-1020-12/5cfc18ff336f77721038bfcade72a0e7887d583397afa5344afd546cb28c7c82.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a red icon resembling a document or a note. It is a rectangle with a folded corner at the bottom right. Inside the red shape, there are two horizontal white lines centered vertically. The icon is outlined in white.](.lec-aln-asl-manual-50m-72519-1020-12/3335294f85e2458a37fa785aab044e62f2cf63a3dc641e37f81a7b984fbbaf66.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![A yellow triangular warning sign containing a white exclamation mark in the center.](.lec-aln-asl-manual-50m-72519-1020-12/491dfda88f66ba6e91310734c3c58e443d221b898aaf5bdea1d4c36b5bdd2d78.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard warning symbol: a red triangle with rounded corners containing a single white exclamation point in the center, set against a white background.](.lec-aln-asl-manual-50m-72519-1020-12/364c9c5f2ea0412d8f08a4437f5e37d9a198695301aefe57a05a2758c200c68e.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History .....

Preface .

1. Introduction ...... C

LEC-ALN / ASL .. ..9
The SMARC Form Factor .. ..9

2. Specifications... .10

Core System... . 10
Video.... ... 11
Audio ... .. 11
Dual Ethernet... ... 12
Expansion Busses.. .... 12
System Storage .. ... 13
SEMA® Board Management Controller .. .... 14
Debug Header ..... ... 14
BIOS.... .... 14
Power... .... 14
Mechanical and Environmental . . 15

3. Block Diagram .. .16
4. Pinout and Signal Descriptions ....... ..17

Pin Summary ... . 17
Signal Terminology Descriptions... . 17
Signal Description by Function.. .. 18

4.3.1 The First Display Interface .. . 18
4.3.2 Second Display Interface .. . 21
4.3.3 MIPI Camera Support... .. 23
4.3.4 HDA (Audio) ... ... 25
4.3.5 USB Ports ... ... 26
4.3.6 PCIe Ports .. ... 28
4.3.7 SATA Gen 3 Ports.. . 29
4.3.8 LAN Ports... ... 30
4.3.9 SPI & ESPI... . 32
4.3.10 SPI0 .. ... 32

4.3.11 ESPI... . 33

General Purpose I2C... .. 34

4.4.1 GPIO... . 35

4.4.2 UART... .. 36

4.4.3 CAN bus .. . 37

4.4.4 Miscellaneous .. . 37

4.4.5 Power and System Management .. . 38

4.4.6 Boot Select.. . 39

4.4.7 Power ... .... 40

SMARC Pin to Controller Mapping... .. 41

5. Additional Features ...... ..53

Module Feature Locations ..... . 53

Status LEDs... . 54

5.2.1 Exception Codes .. . 55

6. System Resources ....... ..56

System Memory Map... . 56

I/O Map ... . 58

Interrupt Request (IRQ) Lines ... . 59

PCI Configuration Space Map.. ... 60

PCI Interrupt Routing Map ... .. 61

SMBus Address Table ... . 61

I2C Address Table.. . 61

7. BIOS Configurations ... .62

Main ... . 63

7.1.1 Main > BIOS Information... ... 63

7.1.2 Main > System Information.. .. 63

7.1.3 Main > Board Information .. .... 64

7.1.4 Main > System Date and Time.. ... 65

. 65

7.2.1 Advanced > CPU Configuration... .... 65

7.2.2 Advanced > Power & Performance... .... 66

7.2.3 Intel® Time Coordinated Computing .. . 74

7.2.4 Advanced > Graphics Configuration .. ... 76

7.2.5 Advanced > Power Management . . 77

7.2.6 Advanced > System Management .. ... 78

7.2.7 Advanced > Thermal Management .. . 79

7.2.8 Advanced > Watchdog Timer... ... 80

7.2.9 Advanced > Super IO Configuration ... . 80

7.2.10 Advanced > Miscellaneous.. . 82

7.2.11 Advanced > USB Configuration.. . 83

7.2.12 Advanced > AMI Graphics Output Protocol Policy . . 84

7.2.13 Advanced > Serial Console Redirection .. . 84

7.2.14 Advanced > Network Stack Configuration . . 86

7.2.15 Advanced > Trusted Computing.. . 86

Chipset .. . 87

7.3.1 Chipset > System Agent (SA) Configuration .. . 87

7.3.2 Chipset > PCH-IO Configuration... ... 90

Security ..... ... 97

7.4.1 Security > Password Description... . 97

7.4.2 Security > Secure Boot Menu.. . 98

Boot .... ... 98

7.5.1 Boot > Boot Configuration .. ... 98

Save & Exit.... .....100

8. BIOS Checkpoints, Beep Codes .... . 101

Status Code Ranges . ...102

Standard Status Codes.. .....103

8.2.1 SEC Phase ... ....103

8.2.2 SEC Phase > SEC Beep Codes.. ....104

8.2.3 SEC Phase > PEI Phase.. ..104

8.2.4 SEC Phase > PEI Beep Codes . ..108

8.2.5 SEC Phase > DXE Status Codes.. ..108

8.2.6 SEC Phase > DXE Beep Codes . ..112

8.2.7 SEC Phase > ACPI/ASL Checkpoint ... ..113

OEM-reserved Checkpoint Ranges. ...114

9. Software Support .......... . 115

Yocto... .....115

Ubuntu.. .....115

Windows... .....115

10.Mechanical and Thermal... . 116

Module Dimensions .. ...116

Thermal Solutions .. ...117

# List of Figures

Figure 1 – Module function diagram.. ...16
Figure 2 – Module top/bottom side pin numbering.... .17
Figure 3 – Module feature locations (top side) ... ..53
Figure 4 – Module dimensions.... . 116
Figure 5 – Thermal solutions... . 117

# 1. Introduction

# LEC-ALN / ASL

ADLINK LEC-ALN / ASL is a SMARC module based on Intel Atom® x7000 series (e.g., x7425E, x7213RE) processors (formerly Alder Lake N or Amston Lake) with integrated Intel® UHD graphics and high-speed interfaces. It supports up to 16GB LPDDR5 memory and is available with rugged operating temperature range and low power envelope, making it ideal for mission-critical fanless edge computing applications that require safety and reliability at all times.

# The SMARC Form Factor

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer-on-module definition targeting applications that require low power and high performance at low costs. Typically, under 6W, the modules often utilize ARM and other alternative low-power option CPUs, and are used in many familiar handheld devices, such as tablet computers and smart phones.

Two module sizes are defined in SMARC: 82 mm x 50 mm and 82 mm x 80 mm.

The module PCBs have 314 edge fingers that mate with a low-profile 314 pin, 0.5 mm pitch, right angle connector (the connector is sometimes identified as a 321-pin connector, with 7 pins used by the key).

SMARC modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE, and a single-channel LVDS display transmitter, are concentrated on the module. Modules are used with application-specific carrier boards that implement other features such as audio codecs, touch controllers, wireless devices, and more.

The modular approach allows scalability, faster time to market, and upgradability while still maintaining low costs, low power, and small physical size.

![The image displays the text 'SGeT'. The letters 'S', 'G', and 'T' are uppercase, bold, and colored a bright lime green. The letter 'e' is lowercase, colored magenta, and is positioned between the 'G' and 'T', sitting lower than the baseline of the other letters.](.lec-aln-asl-manual-50m-72519-1020-12/1264352239a22d95c0b5821242deb65327d23e9d3925f9dd7ebb407354a896a1.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

SMARC module and carrier specifications are available at: https://sget.org/standards/smarc/

# 2. Specifications

# Core System

# SoC

• 7th Gen Intel® Atom® series (formerly Alder Lake N)

 I3-N305
N200
N97
N95
. N50
x7425E
x7213E
x7211E

# Standard embedded parts

• 7th Gen Intel® Atom® series (formerly Amston Lake)

. x7405C
x7213RE
x7433RE
x7835RE
x7203C
 x7211RE

Industrial grade parts

# L2 Cache

6MB

# Memory

4/8/16 GB LPDDR5 at 4800 MT/s memory down type with IBECC.

# Video

LEC-ALN / ASL standard display supports 4K-capable HDMI 2.0a, 4K DP++ and single/dual-channel 24-bit LVDS.

![The image displays a red icon resembling a document or notepad. It features a rectangular outline with a folded bottom-right corner. Inside the outline are three horizontal red lines stacked vertically, resembling lines of text.](.lec-aln-asl-manual-50m-72519-1020-12/c1f5a1f20df45e598d937536d7f0e53fecca98b62b39e7f7b5667f8a6955e091.jpg)

Note: The LVDS output is derived from an eDP to LVDS bridge. As build option, the bridge can be removed.

# GPU Core

Intel Gen11LP UHD Graphics

# HDMI

HDMI 2.0a supporting up to 4K (4096 x 2160 at 60Hz)

# LVDS

LVDS single/dual channel 24-bit at max. 1920x 1200 over eDP to LVDS bridge

# Audio

HDA audio interface (used by default).

![The image displays a simple red icon on a white background. It features the outline of a document or page with a folded corner (dog-ear) at the top right. Inside the outline, there are two horizontal red lines stacked vertically, resembling an equals sign or text lines.](.lec-aln-asl-manual-50m-72519-1020-12/7255dae3dff5a776f76fdcf72ca3b7889587e245bc3af0106c151c56ae2b4d8f.jpg)

Note: Audio codec is located on carrier.

# Dual Ethernet

# Primary LAN (GbE0)

Intel® Ethernet Controller I226 Series with optional IEEE-1588 PTP (Precision Time Protocol)

Supports 2.5Gb data transfer rates, both full-duplex and half-duplex.

# Secondary LAN (GbE1)

Intel® Ethernet Controller I226 Series with optional IEEE-1588 PTP (Precision Time Protocol)

Supports 2.5Gb data transfer rates, both full-duplex and half-duplex.

# 2.5 Expansion Busses

# PCIe

4x PCI Express Gen3 x1 interfaces (configurable to one x4, two x2 or one x2 + two x1 or four x1)

# SATA

1x SATA Gen3, BOM option (BOM option, replaces 1x PCIe D lane as needed)

# USB

2x USB 3.1, 6x USB 2.0, no OTG support

# UART

4x UART interface SER0, 2(Tx/Rx/CTS/RTS) and SER1, SER3 (Tx/Rx)

7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)

Programmable baud rates up to 4 Mbps.

![The image displays a red icon resembling a document or a note. It features a thick red outline of a square with rounded corners and a folded bottom-right corner. Inside the outline, there are two horizontal red lines positioned centrally.](.lec-aln-asl-manual-50m-72519-1020-12/ce93ed78859d126dc98e3c6cbdc1a94f55115dd14a5858e6e88f58856245ac1c.jpg)

Note: The EC UART (4-wire mode) does not support auto flow control.

# CAN bus

2x CAN 2.0B only or mixed CAN 2.0B and, data bit rate of up to 1 Mbps, via USB to CAN BOM option

# SPI

1x SPI 1x eSPI /GSPI

# HDA

1x High-Definition Audio (HDA) as default

# I2C

4x I2C interfaces

Supports 7-bit and 10-bit address modes

Software programmable clock frequency:

100 kbit/s in Standard-mode
400 kbit/s in Fast-mode
1 Mbit/s in Fast-mode Plus

# GPIO

14x GPIO with interrupt (GPIO4 used as HDA\_RST# by default)

# System Storage

# eMMC

Soldered on module 32, 64, 128 GB (build option) either standard or at -40 to 85o C temperature range

Compatible with eMMC specification 4.51 and higher

# SEMA® Board Management Controller

Voltage/current monitoring, boot configuration, logistics, forensic information, flat panel control, watchdog timer

# Debug Header

Flat cable connector for use with optional DB-30 debug module

Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration

# 2.9 BIOS

Single BIOS chip, AMI Aptio V UEFI BIOS

# Power

# Supply Voltage

5V +/- 5%

# Power Sequencing

VDD\_IN is the first power domain to be turned on by the carrier circuit during power-up. Other circuit components on the carrier, which are galvanically coupled to the module, shall not be supplied to avoid feedback. From the moment VDD\_IN is stable — recognizable by VIN\_PWR\_BAD# de-asserted — the module takes over control of the power sequencing. As soon as the module reaches the next system state standby, CARRIER\_PWR\_ON signals the carrier to switch on all its standby voltages. No feedback is provided to allow the carrier to signal Power OK to the modules power state machine. When the state Runtime is reached, the module de-asserts CARRIER\_STBY#. The carrier then switches on the remaining rails.

# Mechanical and Environmental

# Form Factor

SGET SMARC Specifications v2.1.1

# Dimensions

SMARC small size module, 82mm x 50mm

# Operating Temperature

Standard: 0°C to 60°C

Rugged: -40°C to 85°C (optional)

# Humidity

5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# 3. Block Diagram

![The flowchart depicts an 'Alder Lake SoC' (labeled 'Intel®') as the central component, connected to various peripherals and interfaces.\n\n**Central Block:**\n*   **Alder Lake SoC** (contains text 'Intel®')\n\n**Top Interface:**\n*   A top block labeled **'314-pin Golden finger'** connects downwards to various blocks and the SoC.\n*   **Direct Connections to SoC:**\n    *   **'Power Management'**\n    *   **'CSIO.C SII'**\n    *   **'2x USB3.2 host'**\n    *   **'6x USB2.0 host'**\n    *   **'2x UART'**\n    *   **'1x HDA'**\n    *   **'4x I2C'**\n    *   **'14 X GPIO'**\n    *   **'PCIe x1 Gen3 ports 0,1,2,3'**\n    *   **'DP++ / HDMI / DD1'**\n    *   **'HDMI/DDI DD12'**\n*   **Dotted Connection:**\n    *   **'1x SATA Gen3'** connects via a dotted orange arrow to the SoC.\n*   **Connections via Intermediate Orange Blocks:**\n    *   **'CAN 0,1'** connects to **'F1004'**, which connects to the SoC via **'USB'**.\n    *   **'GbE_1'** connects to **'I226'**, which connects to the SoC via **'PCIe'**.\n    *   **'GbE_0'** connects to **'I276'**, which connects to the SoC via **'PCIe'**.\n    *   **'LVD5/DSI/eDP'** connects to **'LVD5'**, which connects to the SoC via **'DD10'**. A dotted line labeled **'DSI'** originates near this block.\n\n**Left-Side Connections:**\n*   Two orange blocks connect to the SoC via double-headed arrows:\n    *   **'HCLBMC'** (receives connections from **'BOOT Select'** and **'2x UART'** from the Golden Finger).\n    *   **'SPI BIOS'** (receives connection from **'G SPI / eSPI'** from the Golden Finger).\n\n**Bottom Connections:**\n*   Arrows point from the SoC to the following blocks:\n    *   **'Debug'** (white block)\n    *   **'TPM'** (orange block) via a line labeled **'SPI'**.\n    *   **'eMMC'** (orange block) via a line labeled **'eMMC 5.0 (8Bit)'**.\n    *   **'LPDDR5 Memory down 4/8/16G B'** (white block).](.lec-aln-asl-manual-50m-72519-1020-12/a68372fb2beb03bf7b4cf307738c3cfed819df0d485b7d2286188d5e57c379e4.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# Pin Summary

The below tables are a list of all signal pins on the MXM 3 connector in the standard specification of SMARC 2.1.

![Top Side\nP1 P74 P75 P156\nKey](.lec-aln-asl-manual-50m-72519-1020-12/10430a5e2981030224ae539dbeb657857e5b0bc4f1aacf732e3a84c1f8136f8e.jpg)

![Bottom Side\nS156 S76 S75 S1\nKey](.lec-aln-asl-manual-50m-72519-1020-12/9f1760a9be0ecf980e7aba431d9625bc1d2d48a7cdf4a828563129c1b456b402.jpg)

Figure 2 – Module top/bottom side pin numbering

# 4.2 Signal Terminology Descriptions

Signals described in the specification but not supported on the LEC-ALN / ASL are marked with STRIKETHROUGH.

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>O OD</td><td>Open drain output from the module</td></tr><tr><td>I OD</td><td>Open drain input to the module, with mandatory PU (pull up) on module</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>I/O</td><td>Bi-directional Input/Output</td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr><tr><td>VDD_IN</td><td>Main power source from carrier to module</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analog signaling for Gigabit Media Dependent Interface</td></tr><tr><td>LVDS DP</td><td>Low Voltage Differential Signal for DisplayPort interface</td></tr><tr><td>MIPI D-PHY</td><td>Low Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>MIPI D-PHY</td><td>Low Voltage Differential Signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS LCD</td><td>Low Voltage Differential Signal for LCD displays</td></tr><tr><td>LVDS PCIE</td><td>Low Voltage Differential Signal for PCIe</td></tr><tr><td>LVDS SATA</td><td>Low Voltage Differential Signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition Minimized Differential Signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signaling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>3.3V</td><td>3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr></table>

# 4.3 Signal Description by Function

# 4.3.1 The First Display Interface

The first display interface is a group of 30pins that is split into a channel 0 and channel 1. The SMARC specification allows support for dual-channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each, or 2 eDP ports 4 lanes each. A mix of different display types, such as DSI and eDP is also permitted. The tables below show which display ports are supported on this particular module.

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S125</td><td>LVDS0_0+</td><td>DSIO_D0+</td><td>eDP0_TX0+</td></tr><tr><td>S126</td><td>LVDS0_0-</td><td>DSIO_D0-</td><td>eDP0_TX0-</td></tr><tr><td>S128</td><td>LVDS0_1+</td><td>DSIO_D1+</td><td>eDP0_TX1+</td></tr><tr><td>S129</td><td>LVDS0_1 -</td><td>DSIO_D1-</td><td>eDP0_TX1-</td></tr><tr><td>S131</td><td>LVDS0_2+</td><td>DSIO_D2+</td><td>eDP0_TX2+</td></tr><tr><td>S132</td><td>LVDS0_2-</td><td>DSIO_D2-</td><td>eDP0_TX2-</td></tr><tr><td>S137</td><td>LVDS0_3+</td><td>DSIO_D3+</td><td>eDP0_TX3+</td></tr><tr><td>S138</td><td>LVDS0_3-</td><td>DSIO_D3-</td><td>eDP0_TX3-</td></tr><tr><td>S134</td><td>LVDS0_CK+</td><td>DSIO_CLK+</td><td>eDP0_AUX+</td></tr><tr><td>S135</td><td>LVDS0_CK-</td><td>DSIO_CLK-</td><td>eDP0_AUX-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td></tr><tr><td>S144</td><td></td><td>DSIO_TE</td><td>eDP0_HPD</td></tr></table>

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S111</td><td>LVDS1_0+</td><td>DSI1_D0+</td><td>eDP1_TX0+</td></tr><tr><td>S112</td><td>LVDS1_0-</td><td>DSI1_D0-</td><td>eDP1_TX0-</td></tr><tr><td>S114</td><td>LVDS1_1+</td><td>DSI1_D1+</td><td>eDP1_TX1+</td></tr><tr><td>S115</td><td>LVDS1_1 -</td><td>DSI1_D1-</td><td>eDP1_TX1-</td></tr><tr><td>S117</td><td>LVDS1_2+</td><td>DSI1_D2+</td><td>eDP1_TX2+</td></tr><tr><td>S118</td><td>LVDS1_2-</td><td>DSI1_D2-</td><td>eDP1_TX2-</td></tr><tr><td>S120</td><td>LVDS1_3+</td><td>DSI1_D3+</td><td>eDP1_TX3+</td></tr><tr><td>S121</td><td>LVDS1_3-</td><td>DSI1_D3-</td><td>eDP1_TX3-</td></tr><tr><td>S108</td><td>LVDS1_CK+</td><td>DSI1_CLK+</td><td>eDP1_AUX+</td></tr><tr><td>S109</td><td>LVDS1_CK-</td><td>DSI1_CLK-</td><td>eDP1_AUX-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S113</td><td></td><td>DSI1_TE</td><td>eDP1_HPD</td></tr></table>

<table><tr><td>S139</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td></tr></table>

![The image displays a red icon on a white background. It depicts a stylized document or page with a folded top-right corner. Inside the red border, there are two horizontal red lines representing text.](.lec-aln-asl-manual-50m-72519-1020-12/1ee8324b0690f67f7fb7c87a63f357720557b9d731fa9426ddcf7ac77e2a4c59.jpg)

# Note:

1. LVDS0/LVDS1 are standard supported through eDP to LVDS bridge on the module
2. eDP can be used by build option, disabling the LVDS0 ports.

4.3.1.1 LVDS0/LVDS1 Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>LVDS0_0+</td><td>S125</td><td rowspan="8">Primary LVDS Channel Differential Pair Data Lines</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">A 100ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_0-</td><td>S126</td></tr><tr><td>LVDS0_1+</td><td>S128</td></tr><tr><td>LVDS0_1 -</td><td>S129</td></tr><tr><td>LVDS0_2+</td><td>S131</td></tr><tr><td>LVDS0_2-</td><td>S132</td></tr><tr><td>LVDS0_3+</td><td>S137</td></tr><tr><td>LVDS0_3-</td><td>S138</td></tr><tr><td>LVDS0_CK+</td><td>S134</td><td rowspan="2">Primary LVDS Channel Differential Pair Clock Lines</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">A 100-ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_CK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary LVDS Channel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary LVDS Channel Backlight Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary LVDS Channel Brightness Control</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td colspan="8"></td></tr><tr><td>LVDS1_0+</td><td>S111</td><td rowspan="8">Secondary LVDS Channel Differential Pair Data Lines</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">A 100-ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_0-</td><td>S112</td></tr><tr><td>LVDS1_1+</td><td>S114</td></tr><tr><td>LVDS1_1 -</td><td>S115</td></tr><tr><td>LVDS1_2+</td><td>S117</td></tr><tr><td>LVDS1_2-</td><td>S118</td></tr><tr><td>LVDS1_3+</td><td>S120</td></tr><tr><td>LVDS1_3-</td><td>S121</td></tr><tr><td>LVDS1_CK+</td><td>S108</td><td rowspan="2">Secondary LVDS Channel Differential Pair Clock Lines</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">A 100-ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_CK-</td><td>S109</td></tr><tr><td>LCD1_VDD_EN</td><td>S116</td><td>Secondary LVDS Channel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Active highOnly in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td>LCD1_BKLT_EN</td><td>S107</td><td>Secondary LVDS Channel Backlight Enable</td><td>Q CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Active highOnly in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td>LCD1_BKLT_PWM</td><td>S122</td><td>Secondary LVDS Channel Brightness Control</td><td>Q CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Through pulse width modulation (PWM)only in use, when two separate LVDS ports are supported, please check Module user manual</td></tr></table>

<table><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if two LVDS panels are used</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if two LVDS panels are used</td></tr></table>

# 4.3.1.2 eDP Mode (Build Option)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>eDP0_TX0+</td><td>S125</td><td rowspan="8">Primary 4-Lane eDP Differential Pair Data Lines</td><td rowspan="8">O DP</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier.</td></tr><tr><td>eDP0_TX0-</td><td>S126</td></tr><tr><td>eDP0_TX1+</td><td>S128</td></tr><tr><td>eDP0_TX1-</td><td>S129</td></tr><tr><td>eDP0_TX2+</td><td>S131</td></tr><tr><td>eDP0_TX2-</td><td>S132</td></tr><tr><td>eDP0_TX3+</td><td>S137</td></tr><tr><td>eDP0_TX3-</td><td>S138</td></tr><tr><td>eDP0_AUX+</td><td>S134</td><td rowspan="2">Primary Bidirectional Channel used for Link Management and Device Control</td><td rowspan="2">I/O DP</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>eDP0_AUX-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary Panel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary Panel Backlight Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary Panel Brightness Control</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td>eDP0_HPD</td><td>S144</td><td>Detection of Hot Plug / Unplug of Primary eDP Display and Notification of the Link Layer</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>PD 1M</td><td>Module must tolerate high level in stand-by mode</td></tr></table>

4.3.2 Second Display Interface

<table><tr><td>Pin #</td><td>HDMI signal names</td><td>DP++ signal names</td></tr><tr><td>P92</td><td>HDMI_D2+</td><td>DP1_LANE0+</td></tr><tr><td>P93</td><td>HDMI_D2-</td><td>DP1_LANE0-</td></tr><tr><td>P95</td><td>HDMI_D1+</td><td>DP1_LANE1+</td></tr><tr><td>P96</td><td>HDMI_D1-</td><td>DP1_LANE1-</td></tr><tr><td>P98</td><td>HDMI_D0+</td><td>DP1_LANE2+</td></tr><tr><td>P99</td><td>HDMI_D0-</td><td>DP1_LANE2-</td></tr><tr><td>P101</td><td>HDMI_CK+</td><td>DP1_LANE3+</td></tr><tr><td>P102</td><td>HDMI_CK-</td><td>DP1_LANE3-</td></tr><tr><td>S105</td><td>HDMI_CTRL_CK</td><td>DP1_AUX+</td></tr><tr><td>S106</td><td>HDMI_CTRL_DAT</td><td>DP1_AUX-</td></tr><tr><td>P104</td><td>HDMI_HPD</td><td>DP1_HPD</td></tr></table>

4.3.2.1 HDMI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>HDMI_D2+</td><td>P92</td><td rowspan="6">HDMI port, differential pair data lines</td><td rowspan="6">O TMDS HDMI</td><td rowspan="6"></td><td rowspan="6">Runtime</td><td rowspan="6"></td><td rowspan="6">AC coupled off module</td></tr><tr><td>HDMI_D2-</td><td>P93</td></tr><tr><td>HDMI_D1+</td><td>P95</td></tr><tr><td>HDMI_D1-</td><td>P96</td></tr><tr><td>HDMI_D0+</td><td>P98</td></tr><tr><td>HDMI_D0-</td><td>P99</td></tr><tr><td>HDMI_CK+</td><td>P101</td><td rowspan="2">HDMI port, differential pair clock lines</td><td rowspan="2">O TMDS HDMI</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>HDMI_CK-HDMI_CTRL_CK</td><td>P102P105</td></tr><tr><td></td><td></td><td>I2C_CLK line dedicated to HDMI</td><td>O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>A level shifter FET and a 5V PU resistor shall be placed between the module and the HDMI connector.A stronger pull-up is demanded on the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete carrier pull-ups are used, the value depends on the individual carrier board implementation.</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>I/O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>A level shifter FET and a 5V PU resistor shall be placed between the module and the HDMI connector.A stronger pull-up is demanded on the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete carrier pull-ups are used, the value depends on the individual carrier Board implementation.</td></tr><tr><td>HDMI_HPD</td><td>P104</td><td>HDMI Hot plug active high detection signal serves as an interrupt request</td><td>I CMOS</td><td>1.8V</td><td>runtime</td><td>PD 100K</td><td>A module must tolerate high voltage levels while in stand-by mode</td></tr></table>

# 4.3.3 MIPI Camera Support

4.3.3.1 MIPI CSI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>CSI0_RX0+</td><td>S11</td><td rowspan="4">CSI0 differential input (point to point)</td><td rowspan="4">I D-PHY / I M-PHY</td><td rowspan="4"></td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4"></td></tr><tr><td>CSI0_RX0-</td><td>S12</td></tr><tr><td>CSI0_RX1+</td><td>S14</td></tr><tr><td>CSI0_RX1-</td><td>S15</td></tr><tr><td>CSI0_CK+</td><td>S8</td><td rowspan="2">CSI0 differential clock input (point to point)</td><td rowspan="2">I D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI0_CK-</td><td>S9</td></tr><tr><td>I2C_CAM0_DAT /CSI0_TX-</td><td>S7</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM0_CK / CSI0_TX+</td><td>S5</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM0_PWR# / GPIO0</td><td>P108</td><td>Camera 0 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO0</td></tr><tr><td>CAM0_RST# / GPIO2</td><td>P110</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO2</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

4.3.3.2 CSI1 (4 Lanes)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI1_RX0+</td><td>P7</td><td rowspan="8">CSI1 differential input</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>CSI1_RX0-</td><td>P8</td></tr><tr><td>CSI1_RX1+</td><td>P10</td><td rowspan="6">/ I LVDS M-PHY</td></tr><tr><td>CSI1_RX1-</td><td>P11</td></tr><tr><td>CSI1_RX2+</td><td>P13</td></tr><tr><td>CSI1_RX2-</td><td>P14</td></tr><tr><td>CSI1_RX3+</td><td>P16</td></tr><tr><td>CSI1_RX3-</td><td>P17</td></tr><tr><td>CSI1_CK+</td><td>P3</td><td rowspan="2">CSI1 differential clock input (point to point)</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI1_CK-</td><td>P4</td></tr><tr><td>I2C_CAM1_DAT / CSI1_TX-</td><td>S2</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM1_CK / CSI1_TX+</td><td>S1</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM1_PWR# / GPIO1</td><td>P109</td><td>Camera 1 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO1</td></tr><tr><td>CAM1_RST# / GPIO3</td><td>P111</td><td>Camera 1 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO 3</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

4.3.4 HDA (Audio)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>HDA_SYNC / I2S2_LRCK</td><td>S50</td><td>High-definition audio sample synchronization clock to codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td><td rowspan="5">LEC-ALN does not support 1.5V for HDA. Please ensure that the audio codec used is compatible with 1.8V I/O voltage. This specification does not account for mismatched voltage levels, and only 1.8V-compatible audio codecs should be used.</td></tr><tr><td>HDA_SDO / I2S2_SDOUT</td><td>S51</td><td>High-definition audio data out to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_SDI / I2S2_SDIN</td><td>S52</td><td>High-definition audio data in from codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_CK / I2S2_CK</td><td>S53</td><td>High-definition audio clock to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_RST# / GPIO4</td><td>P112</td><td>High-definition audio reset output to codec, low active.</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr></table>

![The image displays a simple red icon on a white background. It depicts a document or piece of paper with a folded bottom-right corner. Inside the shape, two horizontal red lines are centered, representing text.](.lec-aln-asl-manual-50m-72519-1020-12/6a0cca213ff7bff70b0d78cc2292814c23469ae4ba2adec56e136951aa71ae59.jpg)
Note: The support for I2S1 signalling pins has been removed after the SMARC 2.0 specification update.

4.3.5 USB Ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB0+USB0-</td><td>P60P61</td><td>USB differential data pairs for port 0</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB0_EN_OC#</td><td>P62</td><td>USB over-current sense for port 0</td><td>I ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr><tr><td>USB0_VBUS_DET</td><td>P63</td><td>USB port 0 host power detection, when this port is used as a device.</td><td>↓USB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td>Can be connected to a USB client port VBUS pin</td></tr><tr><td>USB0_OTG_ID</td><td>P64</td><td>Input pin to announce OTG device insertion on USB 2.0 port</td><td>↓CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB1+USB1-</td><td>P65P66</td><td>USB differential data pairs for port 1</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB1_EN_OC#</td><td>P67</td><td>USB over-current sense for port 1</td><td>I ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB2+USB2-</td><td>P69P70</td><td>USB differential data pairs for port 2</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB2_SSRX+USB2_SSRX-</td><td>S74S75</td><td>Receive signal differential pairs for SuperSpeed on port 2</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for the RX pairs are on the USB Device</td></tr><tr><td>USB2_SSTX+USB2_SSTX-</td><td>S71S72</td><td>Transmit signal differential pairs for SuperSpeed on port 2</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for the TX pairs are on the Module</td></tr><tr><td>USB2_EN_OC#</td><td>P71</td><td>USB over-current sense for port 2</td><td>I ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB3+USB3-</td><td>S68S69</td><td>USB differential data pairs for port 3</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_SSRX+USB3_SSRX-</td><td>S65S66</td><td>Receive signal differential pairs for SuperSpeed on port 3</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for the RX pairs are on the USB Device</td></tr><tr><td>USB3_SSTX+USB3_SSTX-</td><td>S62S63</td><td>Transmit signal differential pairs for SuperSpeed on port 3</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for the TX pairs are on the Module</td></tr><tr><td>USB3_EN_OC#</td><td>P74</td><td>USB over-current sense for port 3</td><td>I ODCMOS</td><td>3.3Vsb /3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr><tr><td>USB3_VBUS_DET</td><td>S37</td><td>USB port 3 host power detection, when this port is used as a device.</td><td>↓USB VBUS 5V</td><td>USB VBUS5V</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_OTG_ID</td><td>S104</td><td>Input pin to announce OTG device insertion on USB 3.0 port</td><td>↓CMOS</td><td>3.3Vsb /3.3V</td><td>Standby</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB4+USB4-</td><td>S35S36</td><td>USB differential data pairs for port 4</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB4_EN_OC#</td><td>P76</td><td>USB over-current sense for port 4</td><td>I ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB5+USB5-</td><td>S59S60</td><td>USB differential data pairs for port 5</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB5_EN_OC#</td><td>S55</td><td>USB over-current sense for port 5</td><td>I ODCMOS</td><td>3.3Vsb /3.3V</td><td>Standby</td><td>PU 10K</td><td>Pulled low by the module OD driver to disable the USB0 power. Pulled low by the carrier OD driver to indicate an over-current situation.</td></tr></table>

![The image displays a red icon resembling a document or a piece of paper with a curled bottom-right corner. Inside the red border, there are two horizontal red lines stacked vertically. The background is white.](.lec-aln-asl-manual-50m-72519-1020-12/2fb810e4b666a5c1eba0e0677fda66f9d9a09ce03e0d411d3282eb88407fc920.jpg)

Note: All USB connections are directly from SoC, there is no support for OTG.

# 4.3.6 PCIe Ports

The module supports 4x PCIe Gen 3.0 ports. Refer to the table below for port details.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIE_A_TX+PCIE_A_TX-</td><td>P89P90</td><td>Differential PCIe link A transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on the module</td></tr><tr><td>PCIE_A_RX+PCIE_A_RX-</td><td>P86P87</td><td>Differential PCIe link A receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off the module</td></tr><tr><td>PCIE_A_REFCK+PCIE_A_REFCK-</td><td>P83P84</td><td>Differential PCIe Link A reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_RST#</td><td>P75</td><td>PCIe Port A reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_CKREQ#</td><td>P78</td><td>PCIe Port A clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on the module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_B_TX+PCIE_B_TX-</td><td>S90S91</td><td>Differential PCIe link B transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_B_RX+PCIE_B_RX-</td><td>S87S88</td><td>Differential PCIe link B receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_B_REFCK+PCIE_B_REFCK-</td><td>S84S85</td><td>Differential PCIe Link B reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_RST#</td><td>S76</td><td>PCIe Port B reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_CKREQ#</td><td>P77</td><td>PCIe Port B clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on the module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_C_TX+PCIE_C_TX-</td><td>S81S82</td><td>Differential PCIe link C transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on the module</td></tr><tr><td>PCIE_C_RX+PCIE_C_RX-</td><td>S78S79</td><td>Differential PCIe link C receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off the module</td></tr><tr><td>PCIE_C_REFCK+PCIE_C_REFCK-</td><td>P80P81</td><td>Differential PCIe Link C reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_C_RST#</td><td>S77</td><td>PCIe Port C reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_D_TX+PCIE_D_TX-</td><td>S29S30</td><td>Differential PCIe link D transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on the module</td></tr><tr><td>PCIE_D_RX+PCIE_D_RX-</td><td>S32S33</td><td>Differential PCIe link D receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off the module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_WAKE#</td><td>S146</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td><td>I ODCMOS</td><td>3.3V</td><td>Standby</td><td>PU 1K</td><td></td></tr></table>

# 4.3.7 SATA Gen 3 Ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr></table>

<table><tr><td>SATA0_TX+SATA0_TX-</td><td>P48P49</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on the module 10 nF</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>P51P52</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on the module 10 nF</td></tr><tr><td>SATA_ACT#</td><td>S54</td><td>SATA activity indicator</td><td>O ODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more carrier LED current</td></tr></table>

![The image shows a red outline icon of a document or memo pad with a folded bottom-right corner. Inside the border, there are two horizontal red lines centered on a white background.](.lec-aln-asl-manual-50m-72519-1020-12/cf2da3ecc51ca4dee89cbd111b70a0ec9894e6c3de02661ac2672bf158befca8.jpg)
Note: SATA is a BIOS option that reduces the available PCIe ports to 3 lanes if enabled.

# 4.3.8 LAN Ports

# 4.3.8.1 First LAN Port

The first LAN port is derived from the PCIe-connected I226 Ethernet controller.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GBE0_MDI0+</td><td>P30</td><td>Differential Pair Signals for External Transformer</td><td rowspan="8">I/IO GBE</td><td rowspan="8"></td><td rowspan="8">Standby</td><td rowspan="8"></td><td rowspan="8">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10 _MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_MDI0-</td><td>P29</td><td rowspan="2">Carrier Series Termination: Magnetics module appropriate for 10/100/1000 GBE transceivers</td></tr><tr><td>GBE0_MDI1+</td><td>P27</td></tr><tr><td>GBE0_MDI1-</td><td>P26</td><td>Carrier Parallel Termination:</td></tr><tr><td>GBE0_MDI2+</td><td>P24</td><td>Secondary side center tap terminations</td></tr><tr><td>GBE0_MDI2-</td><td>P23</td><td>appropriate for Gigabit Ethernet</td></tr><tr><td>GBE0_MDI3+</td><td>P20</td><td>implementations</td></tr><tr><td>GBE0_MDI3-</td><td>P19</td><td></td></tr><tr><td>GBE0_LINK100#</td><td>P21</td><td>Link Speed Indication LED for GBE0 10/100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more carrier LED current $^{1}$ </td></tr><tr><td>GBE0_LINK1000#</td><td>P22</td><td>Link Speed Indication LED for GBE0 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more carrier LED current $^{1}$ </td></tr><tr><td>GBE0_LINK_ACT#</td><td>P25</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more carrier LED current $^{1}$ </td></tr><tr><td>GBE0_CTREF</td><td>P28</td><td>Center -Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td></td><td></td></tr><tr><td>GBE0_SDP</td><td>P6</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td></td><td></td></tr></table>

# 4.3.8.2 Second LAN Port

The second LAN port is derived from the PCIe-connected I226 Ethernet controller.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GBE1_MDI0+</td><td>S17</td><td>Differential Pair Signals for External Transformer</td><td rowspan="8">I/IO GBE</td><td rowspan="8"></td><td rowspan="8">Standby</td><td rowspan="8"></td><td rowspan="8">Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10 _MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE1_MDI0-</td><td>S18</td><td rowspan="2">Carrier Series Termination: Magnetics module appropriate for 10/100/1000 GBE transceivers</td></tr><tr><td>GBE1_MDI1+</td><td>S20</td></tr><tr><td>GBE1_MDI1-</td><td>S21</td><td>Carrier Parallel Termination:</td></tr><tr><td>GBE1_MDI2+</td><td>S23</td><td>Secondary side center tap terminations</td></tr><tr><td>GBE1_MDI2-</td><td>S24</td><td>appropriate for Gigabit Ethernet</td></tr><tr><td>GBE1_MDI3+</td><td>S26</td><td>implementations</td></tr><tr><td>GBE1_MDI3-</td><td>S27</td><td></td></tr><tr><td>GBE1_LINK100#</td><td>S19</td><td>Link Speed Indication LED for GBE1 10/100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td></tr><tr><td>GBE1_LINK1000#</td><td>S22</td><td>Link Speed Indication LED for GBE1 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td></tr><tr><td>GBE1_LINK_ACT#</td><td>S31</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td></tr><tr><td>GBE1_CTREF</td><td>S28</td><td>Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td></td><td></td></tr><tr><td>GBE1_SDP</td><td>P5</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td></td><td></td></tr></table>

![The image displays a simple, red outline icon of a document or page. The icon features a folded bottom-right corner (a 'dog-ear') and contains two horizontal red lines inside the border, representing text.](.lec-aln-asl-manual-50m-72519-1020-12/d184ce0fa7dc2fe458ca75718eb5ae0f0855bb0863960fed486f8f609eb5323f.jpg)

# Note:

1. Both LAN interfaces use a PCIe connected Intel® Ethernet Controller I226 Series.
2. LAN LEDs are inactive when the LAN transfer rate is 2.5Gb.

# 4.3.9 SPI & ESPI

4.3.10 SPI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI0_CS0#</td><td>P43</td><td>SPI0 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>This signal can be used to select carrier SPI as boot device</td></tr><tr><td>SPI0_CS1#</td><td>P31</td><td>SPI0 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CK</td><td>P44</td><td>SPI0 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_DIN</td><td>P45</td><td>SPI0 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Also referred to as MISO</td></tr><tr><td>SPI0_DO</td><td>P46</td><td>SPI0 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Also referred to as MOSI</td></tr><tr><td colspan="8"></td></tr><tr><td>SPI1_CS0#</td><td>P54</td><td>SPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_CS1#</td><td>P55</td><td>SPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_CK</td><td>P56</td><td>SPI1_Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_DIN</td><td>P57</td><td>SPI1 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_DO</td><td>P58</td><td>SPI1 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr></table>

![A red outline icon of a document file with a folded top-right corner. Inside the outline are two horizontal lines.](.lec-aln-asl-manual-50m-72519-1020-12/f890073ab99e00b99a6344dfb2c86f370d9b5a17d2f9dcb6f831827f03e1b0d0.jpg)
Note: SPI0 is free to use on the carrier but only supports one device through CS0.

4.3.11 ESPI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ESPI_CS0#</td><td>P54</td><td>ESPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CK</td><td>P56</td><td>ESPI Master Clock Output</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_RESET#</td><td>S58</td><td>ESPI Reset</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves</td></tr><tr><td>ESPI_ALERT0#</td><td>S43</td><td rowspan="2">ESPI ALERT</td><td rowspan="2">I OD CMOS</td><td rowspan="2">1.8V</td><td rowspan="2">Standby</td><td rowspan="2"></td><td rowspan="2">This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave.This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.</td></tr><tr><td>ESPI_ALERT1#</td><td>S44</td></tr><tr><td>ESPI_IO_0</td><td>P58</td><td rowspan="4">ESPI Master Data Input / Output.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V</td><td rowspan="4">Standby</td><td rowspan="4"></td><td rowspan="4">ESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO).</td></tr><tr><td>ESPI_IO_1</td><td>P57</td></tr><tr><td>ESPI_IO_2</td><td>S56</td></tr><tr><td>ESPI_IO_3</td><td>S57</td></tr></table>

![The image displays a red icon representing a document or file. It features a square shape with a folded bottom-right corner. Inside the red outline, there are two horizontal parallel lines. The background is white.](.lec-aln-asl-manual-50m-72519-1020-12/6da6c2a5132c6141c5ef5d628407ca7fc3b958dd1912c12310fd4f8185d2d13e.jpg)
Note: eSPI / GSPI can be switched by zero Ohm resistors (BOM option).

# 4.4 General Purpose I2C

The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels, or I2C for PMIC. Only one I2C bus is marked as General purpose.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>I2C_GP_DAT</td><td>S49</td><td>General purpose I2C data signal</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_GP_CK</td><td>S48</td><td>General purpose I2C clock signal</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr></table>

Most of the other I2C busses are described in their designated function tables rather than in a combined list.

Below is an overview of all I2C busses and their locations.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>Location</td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>I2C_CAM0_DAT</td><td>S7</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM0_CK</td><td>S5</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_DAT</td><td>S2</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_CK</td><td>S1</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA (SMBus for x86)</td><td>Power and System Management</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK (SMBus for x86)</td><td>Power and System Management</td></tr><tr><td>I2C_GP_DAT</td><td>S49</td><td>General purpose I2C data signal</td><td>General purpose I2C</td></tr><tr><td>I2C_GP_CK</td><td>S48</td><td>General purpose I2C clock signal</td><td>General purpose I2C</td></tr></table>

4.4.1 GPIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO0 / CAM0_PWR#</td><td>P108</td><td>General purpose I/O pin 0.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS</td></tr><tr><td>GPIO1 / CAM1_PWR#</td><td>P109</td><td>General purpose I/O pin 1.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>Default use is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS</td></tr><tr><td>GPIO2 / CAM0_RST#</td><td>P110</td><td>General purpose I/O pin 2.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>Default use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS</td></tr><tr><td>GPIO3 / CAM1_RST#</td><td>P111</td><td>General purpose I/O pin 3.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>Default use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS</td></tr><tr><td>GPIO4/ HDA_RST#</td><td>P112</td><td>General purpose I/O pin 4.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>GPIO 4 support requires BOM change</td></tr><tr><td>GPIO5 / PWM_OUT</td><td>P113</td><td>General purpose I/O pin 5.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO6</td><td>P114</td><td>General purpose I/O pin 6.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO7</td><td>P115</td><td>General purpose I/O pin 7.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO8</td><td>P116</td><td>General purpose I/O pin 8.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO9</td><td>P117</td><td>General purpose I/O pin 9.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO10</td><td>P118</td><td>General purpose I/O pin 10.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO11</td><td>P119</td><td>General purpose I/O pin 11.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO12</td><td>S142</td><td>General purpose I/O pin 12</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr><tr><td>GPIO13</td><td>S123</td><td>General purpose I/O pin 13</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td></td></tr></table>

4.4.2 UART

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SER0_TX</td><td>P129</td><td>Asynchronous serial data output port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RX</td><td>P130</td><td>Asynchronous serial data input port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr><tr><td>SER0_RTS#</td><td>P131</td><td>&quot;Request to Send&quot; handshake line for port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_CTS#</td><td>P132</td><td>&quot;Clear to Send&quot; handshake line for port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr><tr><td colspan="8"></td></tr><tr><td>SER1_TX</td><td>P134</td><td>Asynchronous serial data output port 1</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER1_RX</td><td>P135</td><td>Asynchronous serial data input port 1</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr><tr><td colspan="8"></td></tr><tr><td>SER2_TX</td><td>P136</td><td>Asynchronous serial data output port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER2_RX</td><td>P137</td><td>Asynchronous serial data input port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr><tr><td>SER2_RTS#</td><td>P138</td><td>&quot;Request to Send&quot; handshake line for port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER2_CTS#</td><td>P139</td><td>&quot;Clear to Send&quot; handshake line for port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr><tr><td colspan="8"></td></tr><tr><td>SER3_TX</td><td>P140</td><td>Asynchronous serial data output port 3</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER3_RX</td><td>P141</td><td>Asynchronous serial data input port 3</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>PU 100K</td></tr></table>

4.4.3 CAN bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CAN0_TX</td><td>P143</td><td>CAN port 0 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>supported on Linux and windows</td></tr><tr><td>CAN0_RX</td><td>P144</td><td>CAN port 0 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>supported on Linux and windows</td></tr></table>

supported on Linux and windows

<table><tr><td>CAN1_TX</td><td>P145</td><td>CAN port 1 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>supported on Linux and windows</td></tr><tr><td>CAN1_RX</td><td>P146</td><td>CAN port1 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>supported on Linux and windows</td></tr></table>

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Note: CAN bus is derived from a USB to CAN controller

4.4.4 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>TEST#</td><td>S157</td><td>Held low by the carrier to invoke the module vendor&#x27;s specific test function(s).</td><td>I CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K on the module, driven by OD on the carrier.</td><td>The module must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation</td></tr><tr><td>WDT_TIME_OUT#</td><td>S145</td><td>Watch-Dog-Timer Output, low active.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Driven only during runtime</td></tr></table>

4.4.5 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>BATLOW#</td><td>S156</td><td>Battery low indication to Module. Carrier to float the line in inactive state.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CARRIER_PWR_ON</td><td>S154</td><td>Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.</td><td>OCMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td>1.8Vsb is only used for signaling, not a power source to the module</td></tr><tr><td>CARRIER_STBY#</td><td>S153</td><td>The Module shall drive this signal low when the system is in a standby power state.</td><td>OCMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td></td></tr><tr><td>CHARGER_PRSNT#</td><td>S152</td><td>Held low by Carrier if DC input for battery charger is present.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CHARGING#</td><td>S151</td><td>Held low by Carrier during battery charging. Carrier to float the line when charge is complete.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>VIN_PWR_BAD#</td><td>S150</td><td>Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.</td><td>IOD CMOS</td><td>5V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Module must implement PU but actual value is dependent on a particular module design.</td></tr><tr><td>SLEEP#</td><td>S149</td><td>Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>LID#</td><td>S148</td><td>Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.</td><td>IOD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>RESET_OUT#</td><td>P126</td><td>General purpose reset output to Carrier board.</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>RESET_IN#</td><td>P127</td><td>Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB DATA. Pulled up on module.</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB CLK. Pulled up on module.</td></tr><tr><td>SMB_ALERT_1V8#</td><td>P1</td><td>SMBus Alert# (interrupt) signal</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 10K</td><td>only used on x86 design</td></tr></table>

4.4.6 Boot Select

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>BOOT_SEL0#</td><td>P123</td><td rowspan="3">Input straps determine the Module boot</td><td rowspan="3">IOD CMOS</td><td rowspan="3">1.8Vsb</td><td rowspan="3">Standby</td><td rowspan="3">PU 10K</td><td rowspan="3">Driven by OD on Carrier.Pulled up on module.Supports MODE 7 (default) and MODE 3.</td></tr><tr><td>BOOT_SEL1#</td><td>P124</td></tr><tr><td>BOOT_SEL2#</td><td>P125</td></tr><tr><td>FORCE_RECOV#</td><td>S155</td><td></td><td>IOD CMOS</td><td>1.8Vsb</td><td>Standby</td><td>PU 10K-</td><td>Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module.For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode - such as over a Serial Port.For x86 systems this signal may be used to load BIOS defaults.Pulled up on Module. Driven by OD part on Carrier.</td></tr></table>

4.4.7 Power

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>Power Rail / Tolerance</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="7"></td></tr><tr><td>VDD_IN</td><td>P147, P148, P149, P150, P151, P152, P153, P154, P155, P156</td><td>Module power input voltage 4.75 min to 5.25V max</td><td>P</td><td>4.75 to 5.25V</td><td></td><td></td></tr><tr><td>GND</td><td>P2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158</td><td>Module signal and power return, and GND reference</td><td>P</td><td>Ground</td><td></td><td></td></tr><tr><td>VDD_RTC</td><td>S147</td><td>Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P</td><td>[2 to 3.25] / 3.25V</td><td></td><td></td></tr></table>

SMARC Pin to Controller Mapping

<table><tr><td>Pin</td><td>SMARC Signal Name</td><td>Module Direction</td><td>Module Termination</td><td>Type/Tolerance</td><td>Controller</td><td>Controller Pin Name</td><td>I/O Mux default</td><td>Power Rail</td></tr><tr><td>P1</td><td>SMB_ALERT_1V8#</td><td>-</td><td>-</td><td>-</td><td></td><td></td><td>-</td><td>-</td></tr><tr><td>P2</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P3</td><td>CSI1_CK+</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_CLK_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P4</td><td>CSI1_CK-</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_CLK_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P5</td><td>GBE1_SDP</td><td>Out</td><td>-</td><td>GPIO/3.3V</td><td></td><td>SPD0</td><td></td><td></td></tr><tr><td>P6</td><td>GBE0_SDP</td><td>Out</td><td>-</td><td>GPIO/3.3V</td><td></td><td>CLK_OUT</td><td></td><td></td></tr><tr><td>P7</td><td>CSI1_RX0+</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D0_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P8</td><td>CSI1_RX0-</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D0_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P9</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P10</td><td>CSI1_RX1+</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D1_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P11</td><td>CSI1_RX1-</td><td>In</td><td>-</td><td>LVDS D-PHY</td><td></td><td>MIPI_CSI2_D1_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P12</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P13</td><td>CSI1_RX2+</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D2_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P14</td><td>CSI1_RX2-</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D2_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P15</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P16</td><td>CSI1_RX3+</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D3_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P17</td><td>CSI1_RX3-</td><td>In</td><td>-</td><td>MIPI D-PHY</td><td></td><td>MIPI_CSI2_D3_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P18</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P19</td><td>GBE0_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_M_D</td><td>-</td><td>VDDIO</td></tr><tr><td>P20</td><td>GBE0_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_P_D</td><td>-</td><td>VDDIO</td></tr><tr><td>P21</td><td>GBE0_LINK100#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED_1</td><td>-</td><td>VDDIO</td></tr><tr><td>P22</td><td>GBE0_LINK1000#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED_2</td><td>-</td><td>VDDIO</td></tr><tr><td>P23</td><td>GBE0_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_M_C</td><td>-</td><td>VDDIO</td></tr><tr><td>P24</td><td>GBE0_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_P_C</td><td>-</td><td>VDDIO</td></tr><tr><td>P25</td><td>GBE0_LINK_ACT#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED_0</td><td>-</td><td>VDDIO</td></tr><tr><td>P26</td><td>GBE0_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_M_B</td><td>-</td><td>VDDIO</td></tr><tr><td>P27</td><td>GBE0_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_P_B</td><td>-</td><td>VDDIO</td></tr><tr><td>P28</td><td>GBE0_CTREF</td><td>PWR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P29</td><td>GBE0_MD10-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_M_A</td><td>-</td><td>VDDIO</td></tr><tr><td>P30</td><td>GBE0_MD10+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>TD_P_A</td><td>-</td><td>VDDIO</td></tr><tr><td>P31</td><td>SPI0_CS1#</td><td>Out</td><td>-</td><td>SPI/1.8V</td><td>ALN/ASL x7000</td><td>SPIO_CS1#</td><td>-</td><td>VCC_SPI</td></tr><tr><td>P32</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P33</td><td>SDIO_WP</td><td>In</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_WP</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P34</td><td>SDIO_CMD</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_CMD</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P35</td><td>SDIO_CD#</td><td>In</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_CD</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P36</td><td>SDIO_CK</td><td>Out</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_CLK</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P37</td><td>SDIO_PWR_EN</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>GPIO1_IO12</td><td>ALTO</td><td>NVCC_GPIO1</td></tr><tr><td>P38</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P39</td><td>SDIO_D0</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_DATA0</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P40</td><td>SDIO_D1</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_DATA1</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P41</td><td>SDIO_D2</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_DATA2</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P42</td><td>SDIO_D3</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>ALN/ASL x7000</td><td>SD2_DATA3</td><td>ALTO</td><td>NVCC_SD2</td></tr><tr><td>P43</td><td>SPI0_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>SPI0_CS0#</td><td>ALTO</td><td>VCC_SPI</td></tr><tr><td>P44</td><td>SPI0_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>SPI0_CLK</td><td>ALTO</td><td>VCC_SPI</td></tr><tr><td>P45</td><td>SPI0_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>SPI0_MISO</td><td>ALTO</td><td>VCC_SPI</td></tr><tr><td>P46</td><td>SPI0_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>SPI0_MOSI</td><td>ALTO</td><td>VCC_SPI</td></tr><tr><td>P47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P48</td><td>SATA_TX+</td><td>out</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE12_TXP/SATA1_TXP</td><td>-</td><td>-</td></tr><tr><td>P49</td><td>SATA_TX-</td><td>out</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE12_TXP/SATA1_TXN</td><td>-</td><td>-</td></tr><tr><td>P50</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P51</td><td>SATA_RX+</td><td>In</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE12_TXP/SATA1_RXP</td><td>-</td><td>-</td></tr><tr><td>P52</td><td>SATA_RX-</td><td>In</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE12_TXP/SATA1_RXN</td><td>-</td><td>-</td></tr><tr><td>P53</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P54</td><td>ESPI_CS0# / SPI1_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_CS1#</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>P55</td><td>ESPI_CS1# / SPI1_CS1#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P56</td><td>ESPI_CK / SPI1_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_CLK</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>P57</td><td>ESPI_IO_1 / SPI1_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_MISO</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>P58</td><td>ESPI_IO_0 / SPI1_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_MOSI</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>P59</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P60</td><td>USB0+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2P_1</td><td></td><td>VCC_DSW</td></tr><tr><td>P61</td><td>USB0-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2N_1</td><td></td><td>VCC_DSW</td></tr><tr><td>P62</td><td>USB0_EN_OC#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>USB_OC0#</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>P63</td><td>USB0_VBUS_DET</td><td>PWR</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB1_VBUS</td><td>-</td><td>USB1_VDD33</td></tr><tr><td>P64</td><td>USB0_OTG_ID</td><td>In</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB1_ID</td><td>-</td><td>USB1_VDD33</td></tr><tr><td>P65</td><td>USB1+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2P_2</td><td>-</td><td>VCC_DSW</td></tr><tr><td>P66</td><td>USB1-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2N_2</td><td>-</td><td>VCC_DSW</td></tr><tr><td>P67</td><td>USB1_EN_OC#</td><td>In</td><td>-PU-10K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>USB_OC1#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P68</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P69</td><td>USB2+</td><td>Bi-Dir</td><td>-</td><td>PHY</td><td>ALN/ASL x7000</td><td>USB2P_3</td><td>-</td><td>VCC_DSW</td></tr><tr><td>P70</td><td>USB2-</td><td>Bi-Dir</td><td>-</td><td>PHY</td><td>ALN/ASL x7000</td><td>USB2N_3</td><td>-</td><td>VCC_DSW</td></tr><tr><td>P71</td><td>USB2_EN_OC#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>USB_OC1#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P72</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>P73</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>P74</td><td>USB3_EN_OC#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>USB_OC1#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P75</td><td>PCIE_A_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>PLTRST#</td><td>ALT5</td><td>VCCPRIM</td></tr><tr><td>P76</td><td>USB4_EN_OC#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>USB_OC2#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P77</td><td>PCIE_B_CREQ#</td><td>-</td><td>PU-10K</td><td>-</td><td>ALN/ASL x7000</td><td>SRCCLKREQ1#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P78</td><td>PCIE_A_CREQ#</td><td>-</td><td>PU-10K</td><td>-</td><td>ALN/ASL x7000</td><td>SRCCLKREQ0#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P79</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+</td><td>Out</td><td>-</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_P2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P81</td><td>PCIE_C_REFCK-</td><td>Out</td><td>-</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_N2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P82</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+</td><td>Out</td><td>Serial 0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_P0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P84</td><td>PCIE_A_REFCK-</td><td>Out</td><td>Serial 0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_N0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P85</td><td>GND</td><td>-</td><td>-</td><td></td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P86</td><td>PCIE_A_RX+</td><td>In</td><td>Serial 0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE9_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P87</td><td>PCIE_A_RX-</td><td>In</td><td>Serial 0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE9_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P88</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P89</td><td>PCIE_A_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE9_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P90</td><td>PCIE_A_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE2_TXN_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P91</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P92</td><td>HDMI_D2+ / DP1_LANE0+</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_P0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P93</td><td>HDMI_D2- / DP1_LANE0-</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_N0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P94</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P95</td><td>HDMI_D1+ / DP1_LANE1+</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_P1</td><td></td><td>VCCPRIM</td></tr><tr><td>P96</td><td>HDMI_D1- / DP1_LANE1-</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_N1</td><td></td><td>VCCPRIM</td></tr><tr><td>P97</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P98</td><td>HDMI_D0+ / DP1_LANE2+</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_P2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P99</td><td>HDMI_D0- / DP1_LANE2-</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_N2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P100</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P101</td><td>HDMI_CK+ / DP1_LANE3+</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_P3</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P102</td><td>HDMI_CK- / DP1_LANE3-</td><td>Out</td><td>-</td><td>HDMI</td><td>ALN/ASL x7000</td><td>TCP1_TX_N3</td><td>`</td><td>VCCPRIM</td></tr><tr><td>P103</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P104</td><td>HDMI_HPD / DP1_HPD</td><td>In</td><td></td><td>HDMI</td><td>ALN/ASL x7000</td><td>DDSP_HPD2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK / DP1_AUX+</td><td>Out</td><td>PU-2.2K / PD-100K</td><td>HDMI</td><td>ALN/ASL x7000</td><td>DDP2_CTRLCLK TCP1_AUX_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT / DP1_AUX-</td><td>Bi-Dir</td><td>PU-2.2K / PD-100K</td><td>HDMI</td><td>ALN/ASL x7000</td><td>DDP2_CTRLDATA TCP1_AUX_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P107</td><td>DP1_AUX_SEL</td><td>Out</td><td>PD-1M</td><td>HDMI</td><td>ALN/ASL x7000</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O0</td><td>ALTO</td><td>VCC_GPIO</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O1</td><td>ALTO</td><td>VCC_GPIO</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O2</td><td>ALTO</td><td>VCC_GPIO</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>GPIO1_I/O3</td><td>ALTO</td><td>VCC_GPIO</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>HDA_RST#</td><td>-</td><td>VCCPGPPR</td></tr><tr><td>P113</td><td>GPIO5 / PWM_OUT</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O5</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P114</td><td>GPIO6 / TACHIN</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O6</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P115</td><td>GPIO7</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O7</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P116</td><td>GPIO8</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O8</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P117</td><td>GPIO9</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O9</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P118</td><td>GPIO10</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O10</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P119</td><td>GPIO11</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O11</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>P120</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P121</td><td>I2C_PM_CK</td><td>Out</td><td>PU-2k2</td><td>I2C2</td><td>ALN/ASL x7000</td><td>SMBCLK</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>P122</td><td>I2C_PM_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C2</td><td>ALN/ASL x7000</td><td>SMBDATA</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>P123</td><td>BOOT_SEL0#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>EC</td><td>KSO13</td><td>-</td><td>EC_VCC</td></tr><tr><td>P124</td><td>BOOT_SEL1#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>EC</td><td>KSO14</td><td>-</td><td>EC_VCC</td></tr><tr><td>P125</td><td>BOOT_SEL2#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>EC</td><td>KSO15</td><td>-</td><td>EC_VCC</td></tr><tr><td>P126</td><td>RESET_OUT#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>PLTRST#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P127</td><td>RESET_IN#</td><td>In</td><td>PU-4K7</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>SYS_RESET#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P128</td><td>POWER_BTN#</td><td>In</td><td>PU-4K7</td><td>GPIO / 3.3V</td><td>EC</td><td>GPE4</td><td>-</td><td>EC_VCC</td></tr><tr><td>P129</td><td>SER0_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>TXD</td><td>ALT0</td><td>EC_VCC</td></tr><tr><td>P130</td><td>SER0_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>RXD</td><td>ALT0</td><td>EC_VCC</td></tr><tr><td>P131</td><td>SER0_RTS#</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>RTS0</td><td>ALT1</td><td>EC_VCC</td></tr><tr><td>P132</td><td>SER0_CTS#</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>CTS0</td><td>ALT1</td><td>EC_VCC</td></tr><tr><td>P133</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P134</td><td>SER1_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>CTX</td><td>ALT0</td><td>EC_VCC</td></tr><tr><td>P135</td><td>SER1_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EC</td><td>CRX</td><td>ALT0</td><td>EC_VCC</td></tr><tr><td>P136</td><td>SER2_TX</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>UART2_TXD</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P137</td><td>SER2_RX</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>UART2_RXD</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P138</td><td>SER2_RTS#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>UART2_RTS#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P139</td><td>SER2_CTS#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>UART2_CTS#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>P140</td><td>SER3_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>ALN/ASL x7000</td><td>UART1_TXD</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>P141</td><td>SER3_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>ALN/ASL x7000</td><td>UART1_RXD</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>P142</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P143</td><td>CAN0_TX</td><td>Out</td><td>-</td><td>CAN</td><td>F81604</td><td>CAN1_TX</td><td>-</td><td>VCC_CAN</td></tr><tr><td>P144</td><td>CAN0_RX</td><td>In</td><td>-</td><td>CAN</td><td>F81604</td><td>CAN1_RX</td><td>-</td><td>VCC_CAN</td></tr><tr><td>P145</td><td>CAN1_TX</td><td>-</td><td>-</td><td>-</td><td>F81604</td><td>CAN2_TX</td><td></td><td>VCC_CAN</td></tr><tr><td>P146</td><td>CAN1_RX</td><td>-</td><td>-</td><td>-</td><td>F81604</td><td>CAN2_RX</td><td></td><td>VCC_CAN</td></tr><tr><td>P147</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P148</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P149</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P150</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P151</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P152</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P153</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P154</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P155</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P156</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>S1</td><td>CSI1_TX+ / I2C_CAM1_CK</td><td>In</td><td>PU-2k2</td><td>I2C3</td><td>ALN/ASL x7000</td><td>I2C5_SCL</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>S2</td><td>CSI1_TX- / I2C_CAM1_DAT</td><td>In</td><td>PU-2k2</td><td>I2C3</td><td>ALN/ASL x7000</td><td>I2C5_SDA</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>S3</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S4</td><td>RSVD</td><td>In</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S5</td><td>CSI0_TX- / I2C_CAM0_CK</td><td>Out</td><td>PU-2k2</td><td>I2C4</td><td>ALN/ASL x7000</td><td>I2C1_SCL</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>S6</td><td>CAM_MCK</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>IMGCLKOUT0</td><td>ALT5</td><td>VCCPRIM</td></tr><tr><td>S7</td><td>CSI0_TX+ / I2C_CAM0_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C4</td><td>ALN/ASL x7000</td><td>I2C1_SDA</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>S8</td><td>CSI0_CK+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_CLK_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S9</td><td>CSI0_CK-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_CLK_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S10</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S11</td><td>CSI0_RX0+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_D0_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S12</td><td>CSI0_RX0-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_D0_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S13</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S14</td><td>CSI0_RX1+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_D1_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S15</td><td>CSI0_RX1-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>ALN/ASL x7000</td><td>CSI0_B_D1_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S16</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S17</td><td>GBE1_MDI0+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_A_P</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S18</td><td>GBE1_MDI0-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_A_N</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S19</td><td>GBE1_LINK100#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED0</td><td>-</td><td>-</td></tr><tr><td>S20</td><td>GBE1_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_B_P</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S21</td><td>GBE1_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_B_N</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S22</td><td>GBE1_LINK1000#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED2</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S23</td><td>GBE1_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_C_P</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S24</td><td>GBE1_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_C_N</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S25</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S26</td><td>GBE1_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_D_P</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S27</td><td>GBE1_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>Intel® I226 Series</td><td>MDI_D_N</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S28</td><td>GBE1_CTREF</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S29</td><td>PCIE_D_TX+ / SERDES_1_TX+</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PIE12_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S30</td><td>PCIE_D_TX- / SERDES_1_TX-</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE12_TXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S31</td><td>GBE1_LINK_ACT#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>Intel® I226 Series</td><td>LED1</td><td>-</td><td>VCC_GBE1</td></tr><tr><td>S32</td><td>PCIE_D_RX+ / SERDES_1_RX+</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PIE12_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S33</td><td>PCIE_D_RX- / SERDES_1_RX-</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE12_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S34</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>S35</td><td>USB4+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2P_5</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S36</td><td>USB4-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2N_5</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S37</td><td>USB3_VBUS_DET</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S38</td><td>AUDIO_MCK</td><td>Out</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>I2S_MCLK1_OUT</td><td>ALT0</td><td>VCCPRIM</td></tr><tr><td>S39</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>N.C.</td></tr><tr><td>S40</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>N.C.</td></tr><tr><td>S41</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>N.C.</td></tr><tr><td>S42</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>N.C.</td></tr><tr><td>S43</td><td>ESPI_ALERT0#</td><td>In</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_ALERT0#</td><td>ALT5</td><td>VCCPRIM</td></tr><tr><td>S44</td><td>ESPI_ALERT1#</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S45</td><td>MDIO_CLK</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S46</td><td>MDIO_DAT</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>S48</td><td>I2C_GP_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C3</td><td>EC</td><td>SMCLK4</td><td>ALTO</td><td>VCC_EC</td></tr><tr><td>S49</td><td>I2C_GP_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C3</td><td>EC</td><td>SMDAT4</td><td>ALTO</td><td>VCC_EC</td></tr><tr><td>S50</td><td>HDA_SYNC / I2S2_LRCK</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>HDA_SYNC</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>S51</td><td>HDA_SDO / I2S2_SDOUT</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>HDA_SDO</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>S52</td><td>HDA_SDI / I2S2_SDIN</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>HDA_SDI</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>S53</td><td>HDA_CK / I2S2_CK</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>ALN/ASL x7000</td><td>HDA_SCLK</td><td>ALTO</td><td>VCCPRIM</td></tr><tr><td>S54</td><td>SATA_ACT#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>SATA_LED#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S55</td><td>USB5_EN_OC#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>USB_OC2#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S56</td><td>ESPI_IO_2</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>ESPI_IO2</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S57</td><td>ESPI_IO_3</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>ESPI_IO3</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S58</td><td>ESPI_RESET#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>ESPI_RESET#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S59</td><td>USB5+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>USB2P_6</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S60</td><td>USB5-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>USB2N_6</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S61</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S62</td><td>USB3_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_2_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S63</td><td>USB3_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_2_TXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S64</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S65</td><td>USB3_SSRX+</td><td>In</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_2_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S66</td><td>USB3_SSRX-</td><td>In</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_2_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S67</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S68</td><td>USB3+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2P_4</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S69</td><td>USB3-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB2N_4</td><td>-</td><td>VCC_DSW</td></tr><tr><td>S70</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S71</td><td>USB2_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_1_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S72</td><td>USB2_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_1_TXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S73</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S74</td><td>USB2_SSRX+</td><td>In</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_1_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S75</td><td>USB2_SSRX-</td><td>In</td><td>-</td><td>USB</td><td>ALN/ASL x7000</td><td>USB32_1_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S76</td><td>PCIE_B_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>PLTRST#</td><td>ALT5</td><td>VCCPRIM</td></tr><tr><td>S77</td><td>PCIE_C_RST#</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PLTRST#</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S78</td><td>PCIE_C_RX+ / SERDES_2_RX+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE11_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S79</td><td>PCIE_C_RX- / SERDES_2_RX-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE11_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S80</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S81</td><td>PCIE_C_TX+ / SERDES_2_TX+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE11_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S82</td><td>PCIE_C_TX- / SERDES_2_TX-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>PCIE11_TXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S83</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S84</td><td>PCIE_B_REFCK+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_P1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S85</td><td>PCIE_B_REFCK-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>CLKOUT_PCIE_N1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S86</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S87</td><td>PCIE_B_RX+</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE10_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S88</td><td>PCIE_B_RX-</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE10_RXN</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S89</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S90</td><td>PCIE_B_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE10_TXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S91</td><td>PCIE_B_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>ALN/ASL x7000</td><td>PCIE10_RXP</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S92</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S93</td><td>DPO_LANE0+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_TX_P0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S94</td><td>DPO_LANE0-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_TX_N0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S95</td><td>DPO_AUX_SEL</td><td>-</td><td>-</td><td>-</td><td>DDH4</td><td>DDH4</td><td>-</td><td>-</td></tr><tr><td>S96</td><td>DPO_LANE1+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_RX_P0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S97</td><td>DPO_LANE1-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_RX_N0</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S98</td><td>DPO_HPD</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>DDSP_HPD1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S99</td><td>DPO_LANE2+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_TX_P1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S100</td><td>DPO_LANE2-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_TX_N1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S101</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S102</td><td>DPO_LANE3+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_RX_P1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S103</td><td>DPO_LANE3-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_RX_N1</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S104</td><td>USB3_OTG_ID</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S105</td><td>DP0_AUX+</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_AUX_P</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S106</td><td>DP0_AUX-</td><td>-</td><td>-</td><td>-</td><td>ALN/ASL x7000</td><td>TCP0_AUX_N</td><td>-</td><td>VCCPRIM</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S108</td><td>LVDS1_CK+/ eDP1_AUX+/ DSI1_CLK+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSCKE_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S109</td><td>LVDS1_CK-/ eDP1_AUX-/ DSI1_CLK-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSCKE_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S110</td><td>GND</td><td>-</td><td>-</td><td>-</td><td></td><td></td><td>-</td><td>-</td></tr><tr><td>S111</td><td>LVDS1_0+/ eDP1_TX0+/ DSI1_D0+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSAE_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S112</td><td>LVDS1_0-/ eDP1_TX0-/ DSI1_D0-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSAE_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S113</td><td>eDP1_HPD-/DSI1_TE</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S114</td><td>LVDS1_1+/ eDP1_TX1+/ DSI1_D1+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSBE_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S115</td><td>LVDS1_1-/ eDP1_TX1-/ DSI1_D1-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSBE_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S117</td><td>LVDS1_2+/ eDP1_TX2+/ DSI1_D2+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSCE_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S118</td><td>LVDS1_2-/ eDP1_TX2-/ DSI1_D2-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSCE_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S119</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S120</td><td>LVDS1_3+/ eDP1_TX3+/ DSI1_D3+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSDE_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S121</td><td>LVDS1_3-/ eDP1_TX3-/ DSI1_D3-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSDE_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S123</td><td>GPIO13</td><td>-</td><td>-</td><td>-</td><td>SX1509</td><td>I/IO13</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>S124</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S125</td><td>LVDS0_0+/ eDP0_TX0+/ DSI0_D0+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>LVSAO_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S126</td><td>LVDS0_0- / eDP0_TX0- / DSI0_D0-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSAO_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>PTN3460</td><td>BKLTEN</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S128</td><td>LVDS0_1+ / eDP0_TX1+ / DSI0_D1+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSBO_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S129</td><td>LVDS0_1- / eDP0_TX1- / DSI0_D1-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSBO_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S130</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S131</td><td>LVDS0_2+ / eDP0_TX2+ / DSI0_D2+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSCO_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S132</td><td>LVDS0_2- / eDP0_TX2- / DSI0_D2-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSCO_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>Out</td><td>-</td><td>GPIO/1.8V</td><td>PTN3460</td><td>PVCCEN</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S134</td><td>LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSCKO_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S135</td><td>LVDS0_CK- / eDP0_AUX- / DSI0_CLK-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSCKO_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S136</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S137</td><td>LVDS0_3+ / eDP0_TX3+ / DSI0_D3+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSDO_P</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S138</td><td>LVDS0_3- / eDP0_TX3- / DSI0_D3-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>LVSDO_N</td><td>-</td><td>VCC_LVDS</td></tr><tr><td>S139</td><td>I2C_LCD_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C4</td><td>PTN3460</td><td>DDC_SCL</td><td>ALT0</td><td>VCC_LVDS</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C4</td><td>PTN3460</td><td>DDC_SDA</td><td>ALT0</td><td>VCC_LVDS</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>eDP_BKLTCTL</td><td>ALT1</td><td>VCCPRIM</td></tr><tr><td>S142</td><td>GPIO12</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>I/O12</td><td>-</td><td>VCC_GPIO</td></tr><tr><td>S143</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S144</td><td>eDP0_HPD / DSI0_TE</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S145</td><td>WDT_TIME_OUT#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>EC</td><td>KSO0/PD0</td><td>-</td><td>VCC_EC</td></tr><tr><td>S146</td><td>PCIE_WAKE#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>WAKE#</td><td>ALT5</td><td>VCC_DSW</td></tr><tr><td>S147</td><td>VDD_RTC</td><td>PWR</td><td>-</td><td>PWR</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S148</td><td>LID#</td><td>In</td><td>PU-4.7K</td><td>GPIO / 3.3V</td><td>EC</td><td>GPC6</td><td>ALT5</td><td>VCC_EC</td></tr><tr><td>S149</td><td>SLEEP#</td><td>In</td><td>PU-4.7K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>GPP_H9</td><td>ALT5</td><td>VCPRIM</td></tr><tr><td>S150</td><td>VIN_PWR_BAD#</td><td>In</td><td>PU-10K</td><td>GPIO / 5V</td><td>EC</td><td>GPH6/ID6</td><td>-</td><td>VCC_EC</td></tr><tr><td>S151</td><td>CHARGING#</td><td>Out</td><td>PU-68K</td><td>GPIO / 3.3V</td><td>EC</td><td>KSI6</td><td>ALT5</td><td>VCC_EC</td></tr><tr><td>S152</td><td>CHARGER_PRSNT#</td><td>Out</td><td>PU-100K</td><td>GPIO / 3.3V</td><td>EC</td><td>KSI7</td><td>ALT5</td><td>VCC_EC</td></tr><tr><td>S153</td><td>CARRIER_STBY#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>EC</td><td>KSI3</td><td>-</td><td>VCC_EC</td></tr><tr><td>S154</td><td>CARRIER_PWR_ON</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>EC</td><td>GPF4</td><td>-</td><td>VCC_EC</td></tr><tr><td>S155</td><td>FORCE_RECOV#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>ALN/ASL x7000</td><td>GPP_E8</td><td>-</td><td>VCPRIM</td></tr><tr><td>S156</td><td>BATLOW#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>ALN/ASL x7000</td><td>BATLOW#</td><td>-</td><td>VCPRIM</td></tr><tr><td>S157</td><td>TEST#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>EC</td><td>KSI0</td><td>-</td><td>VCC_EC</td></tr><tr><td>S158</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches, and additional items located on the module that may not necessarily be included in the PICMG standard specification. The locations of these items are illustrated below:

# 5.1 Module Feature Locations

![Status LEDs\n31-pin Debug Connector\n*A smaller connector now included in DB40 kits with cable.](.lec-aln-asl-manual-50m-72519-1020-12/81d589b588193f228d12b4a9e0c7f0d1fa0ed92c5604a65bfa23dba8cb85989f.jpg)

Figure 3 – Module feature locations (top side)

# Status LEDs

The integration of the status LEDs onto the module simplifies maintenance procedures, ensuring swift and efficient identification of operational status.

LED3 LED2 LED1

![The image features two red lines originating from a common point on the far left side. One line extends horizontally to the right, while the other extends diagonally upward to the right, forming an acute angle. The background is white, with a black horizontal bar visible along the very top edge. There is no text in the image.](.lec-aln-asl-manual-50m-72519-1020-12/41041283b393e97214aa935eb94c2601ca5d5dc39543903b96e6e6f640100c14.jpg)

![Close-up of a blue printed circuit board with electronic components and connectors (no readable text or symbols)](.lec-aln-asl-manual-50m-72519-1020-12/c4c7d6a42469b099ab13f26e22ac14a7b1d1d79d72f599bccb566e3d917ae483.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC/EC output</td><td>Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>Watchdog (WD)</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

5.2.1 Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>8</td><td>RESETIN_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr></table>

# 6. System Resources

6.1 System Memory Map

<table><tr><td>Memory Range</td><td>Target</td><td>Dependency / Comments</td></tr><tr><td>000A0000 – 000B FFFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>000E 0000 - 000F 3FFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>000E 4000 - 000F 7FFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>000E 8000 - 000F BFFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>000E C000 – 000E FFFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>000F 0000 - 000F FFFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>0080400000 – 00BFFFFFFF</td><td>PCIE port</td><td>PCIe root port</td></tr><tr><td>00C0000000- 00CFFFFFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FD690000 – 00FD69FFFF</td><td>Serial IO GPIO Host Controller</td><td>Serial IO GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6A0000 – 00FD6AFFF</td><td>Serial IO GPIO Host Controller</td><td>Serial IO GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6D0000 – 00FD6DFFF</td><td>Serial IO GPIO Host Controller</td><td>Serial IO GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6E0000 – 00FD6EFFF</td><td>Serial IO GPIO Host Controller</td><td>Serial IO GPIO Host Controller – INTC1057</td></tr><tr><td>00FE010000- 00FE010FFF</td><td>SPI Controller</td><td>SPI Controller – 54A4</td></tr><tr><td>00FED00000- 00FED003FF</td><td>High precision event timer</td><td></td></tr><tr><td>00FED20000-00FED7FFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FED45000-00FED8FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FED90000-00FED93FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDA0000-00FEDA0FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDA1000-00FEDA1FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDC0000-00FEDC7FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEE00000-00FEEFFFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>004000000000 – 00 400FFFFFFF</td><td>Intel UHD Graphics</td><td></td></tr><tr><td>006000000000 – 00600FFFFFFF</td><td>Intel UHD Graphics</td><td></td></tr><tr><td>006001100000-00600110FFF</td><td>XHCI Controller</td><td>Intel USB3.0 XHCI Controller</td></tr><tr><td>006001118000-0060011180FF</td><td>SMBus</td><td>SMBus-54A3</td></tr><tr><td>00600111B000-00600111BFFF</td><td>Intel SD Host Controller</td><td></td></tr><tr><td>007FFFEF3000-007FFFEF3FFF</td><td>UART#0</td><td>Intel Serial IO UART Host Controller – 54A8</td></tr><tr><td>007FFFEF4000-007FFFEF4FFF</td><td>UART#1</td><td>Intel Serial IO UART Host Controller – 54C7</td></tr><tr><td>007FFFEF5000-007FFFEF5FFF</td><td>I2C#0</td><td>Intel Serial IO I2C Host Controller – 54C6</td></tr><tr><td>007FFFEF6000-007FFFEF6FFF</td><td>I2C#1</td><td>Intel Serial IO I2C Host Controller-54C5</td></tr><tr><td>007FFFEF7000-007FFFEF7FFF</td><td>Intel ME</td><td>Intel ME Interface #1</td></tr><tr><td>007FFFEF8000-007FFFEF8FFF</td><td>I2C#2</td><td>Intel Serial IO I2C Host Controller-54E9</td></tr><tr><td>007FFFEF9000-007FFFEF9FFF</td><td>I2C#3</td><td>Intel Serial IO I2C Host Controller-54E8</td></tr><tr><td>007FFFEFA000-007FFFEFAFFF</td><td>UART#2</td><td>Intel Serial IO UART Host Controller – 54A9</td></tr><tr><td>007FFFEFB000-007FFFEFBFFF</td><td>GNA</td><td>Intel GNA Scoring Accelerator module</td></tr><tr><td>007FFFEFC000-007FFEFCFFF</td><td>HDA</td><td>High Definition Audio Controller</td></tr><tr><td>007FFFF00000-007FFFFFFF</td><td>HDA</td><td>High Definition Audio Controller</td></tr></table>

# I/O Map

Fixed I/O Decode Ranges

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>020h – 02Dh &amp; 030h – 03Dh</td><td>Programmable interrupt controller</td></tr><tr><td>02Eh – 02Fh</td><td>Motherboard resource</td></tr><tr><td>040h – 043h &amp; 050h – 053h</td><td>System Timer</td></tr><tr><td>04Eh – 04Fh</td><td>Motherboard resource</td></tr><tr><td>062h, 066h</td><td>Microsoft ACPI-CompliantEmbedded Controller</td></tr><tr><td>061h, 063h, 065h, 067h, 070h, 080h, 092h</td><td>Motherboard resource</td></tr><tr><td>0A0h – 0B1h &amp; 0B4h – 0BDh</td><td>Interrupt Controller</td></tr><tr><td>0B2h and 0B3h</td><td>Motherboard resource</td></tr><tr><td>0E0h – 0EFh</td><td>Available</td></tr><tr><td>0F0h</td><td>Co-processor error register</td></tr><tr><td>200h - 201h</td><td>SEMA Embedded Controller</td></tr><tr><td>2F8h – 2FFh</td><td>Serial Port 2</td></tr><tr><td>3F8h – 3FFh</td><td>Serial Port 1</td></tr><tr><td>378h – 37Fh</td><td>Available</td></tr><tr><td>380h – 3AFh</td><td>Available</td></tr><tr><td>4D0h-4D1h</td><td>Interrupt Controller</td></tr><tr><td>680h – 69Fh &amp; 0A00h – 0A6Fh &amp; 164Eh -164Fh &amp; 1854h-1857h &amp; 2000h-20FEh</td><td>Motherboard resource</td></tr><tr><td>3000h-303Fh</td><td>Intel UHD Graphics</td></tr><tr><td>EFA0h- EFBFh</td><td>SMBus – 54A3</td></tr><tr><td>020h – 02Dh &amp; 030h – 03Dh</td><td>Programmable interrupt controller</td></tr><tr><td>02Eh – 02Fh</td><td>Motherboard resource</td></tr></table>

# 6.3 Interrupt Request (IRQ) Lines

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>System timer</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>14</td><td>Intel Serial IO GPIO Host Controller</td><td>N/A</td><td>No</td></tr><tr><td>16</td><td>Intel SD Host Controller</td><td>PCI Usage</td><td>No</td></tr><tr><td>16</td><td>Intel Serial IO UART Host Controller-54A8</td><td>PCI Usage</td><td>No</td></tr><tr><td>17</td><td>Intel Serial IO UART Host Controller-54A9</td><td>PCI Usage</td><td>No</td></tr><tr><td>19</td><td>High Definition Audio Controller</td><td>PCI Usage</td><td>No</td></tr><tr><td>27</td><td>Intel Serial IO I2C Host Controller-54E8</td><td>PCI Usage</td><td>No</td></tr><tr><td>31</td><td>Intel Serial IO I2C Host Controller-54C5</td><td>PCI Usage</td><td>No</td></tr><tr><td>32</td><td>Intel Serial IO I2C Host Controller-54C6</td><td>PCI Usage</td><td>No</td></tr><tr><td>36</td><td>Intel Serial IO SPI Host Controller-54AA</td><td>PCI Usage</td><td>No</td></tr><tr><td>40</td><td>Intel Serial IO I2C Host Controller-54E9</td><td>PCI Usage</td><td>No</td></tr><tr><td>42</td><td>Intel Serial IO UART Host Controller-54C7</td><td>PCI Usage</td><td>No</td></tr><tr><td>43-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Yes</td></tr></table>

![The image displays a simple icon in a reddish-orange color. It depicts a document or memo symbol, characterized by a rounded rectangular outline with a folded bottom-right corner. Inside the outline, two horizontal lines are centered.](.lec-aln-asl-manual-50m-72519-1020-12/483cfda03de00f5122372da42d09e6dae5ec78ef0aa8dc5d90fcb6b0a6e7c8cc.jpg)

Note: These IRQs can be used for PCI devices when the onboard device is disabled.

PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel Corporation Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel VGA Controller</td></tr><tr><td>00h</td><td>08h</td><td>00h</td><td>Internal</td><td>Intel system device</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>USB xHCI Controller</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>RAM Controller</td></tr><tr><td>00h</td><td>15h</td><td>00h</td><td>Internal</td><td>I2C Controller #0</td></tr><tr><td>00h</td><td>15h</td><td>01h</td><td>Internal</td><td>I2C Controller #1</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel® CSME Interface #1</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Internal</td><td>I2C Controller #2</td></tr><tr><td>00h</td><td>19h</td><td>01h</td><td>Internal</td><td>I2C Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>02h</td><td>Internal</td><td>UART #0</td></tr><tr><td>00h</td><td>1Ah</td><td>00h</td><td>Internal</td><td>SD Host Controller</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port 4</td></tr><tr><td>00h</td><td>1Eh</td><td>00h</td><td>Internal</td><td>UART #1</td></tr><tr><td>00h</td><td>1Eh</td><td>01h</td><td>Internal</td><td>UART #2</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel ISA bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>HD Audio</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>SMBus Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>SPI Controller</td></tr><tr><td>01h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet controller I226-V</td></tr></table>

6.5 PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>xHCI Controller</td><td>SATA Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTD: 16</td><td>INTA: 16</td><td>INTA: 16</td></tr><tr><td>Int1</td><td></td><td>INTB: 17</td><td>INTB: 17</td></tr><tr><td>Int2</td><td></td><td>INTC: 18</td><td>INTC: 18</td></tr><tr><td>Int3</td><td></td><td>INTD: 19</td><td>INTD: 19</td></tr></table>

<table><tr><td>INT Line</td><td>PCIe Port 4</td><td>PCIe Port 7</td><td>PCIe Port 9</td><td>PCIe Port 10</td><td>PCIe Port 11</td><td>PCIe Port 12</td></tr><tr><td>Int0</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td></tr><tr><td>Int1</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td></tr><tr><td>Int2</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td></tr><tr><td>Int3</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td></tr></table>

SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>IT5121(EC)</td><td>050h</td></tr><tr><td>SX1509</td><td>03Fh</td></tr><tr><td>PTN3460</td><td>0C0h</td></tr></table>

I2C Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>THRM-Sensor (SU1)</td><td>92h</td></tr><tr><td>THRM-Sensor (SU2)</td><td>90h</td></tr><tr><td>EEPROM (U12)</td><td>A0h</td></tr></table>

# 7. BIOS Configurations

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS InformationSystem InformationBoard Information►System DateSystem Time</td><td>CPU Configuration►Power &amp; Performance►Inter(R) Time Coordinated Computing►Power Management►System Management►Thermal Management►Watchdog Timer►Super IO Configuration►Miscellaneous►USB Configuration►AMI Graphics Output Protocol Policy►Serial Port Console Redirection►Network Stack Configuration►Trusted Computing►</td><td>System Agent (SA)Configuration►PCH-IO Configuration►</td><td>SetupAdministratorPasswordUser PasswordSecure Boot</td><td>BootConfigurationFIXED BOOTORDER PrioritiesUEFI USB KeyDrive BBSPriorities</td><td>Save Change and ExitDiscard Changes and ExitSave Changes and ResetDiscard Changes and ResetSave OptionsBoot Override</td></tr></table>

![The image displays a red icon on a white background. It features a square outline with rounded corners and a folded bottom-right corner (a dog-ear). Inside the outline are two horizontal red lines, resembling a document or note.](.lec-aln-asl-manual-50m-72519-1020-12/306d8617e3e6ff11cceb76b08f88ab2c0dad205dea649b440ed3922b6b2d3b2f.jpg)

Note: ► indicates a submenu

Gray text indicates info only

# 7.1 Main

The Main Menu provides read-only information about your system and also allows you to set the system date and time. Refer to the tables below for details of the submenus and settings.

7.1.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display Core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Display compliancy information</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display compliancy information</td></tr><tr><td>GOP Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr></table>

7.1.2 Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display CPU Brand Name.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU Frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH Information.</td></tr><tr><td>Board Information</td><td>Submenu</td><td></td></tr></table>

7.1.3 Main > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC serial Number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC last repair date.</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display SMC MAC ID.</td></tr><tr><td>MAC ID 2</td><td>Read only</td><td>Display SMC MAC ID 2.</td></tr><tr><td>UUID</td><td>Read only</td><td>Display SMC UUID</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td></td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down.</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.1.4 Main > System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr><tr><td>Access Level</td><td>Read only</td><td>It shows what access level is used to enter BIOS setup menu.</td></tr></table>

# Advanced

The Advanced menu contains the settings for most of the user interfaces in the system.

7.2.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Brand String</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel Virtualization Technology support or not.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled, Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Efficient-cores</td><td>All,7,6,5,4,3,2,1,0</td><td>The number of E-cores to enable in each processor package. Note: The number of cores and E-cores are taken into account together. When both are {0,0}, Pcode will enable all cores.</td></tr></table>

# 7.2.2 Advanced > Power & Performance

7.2.2.1 Advanced > Power & Performance > CPU – Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Performance Mode</td><td>Max Battery, Max Non-Turbo Performance, Turbo Performance</td><td>Select the performance state that the BIOS will set starting from the reset vector.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled, Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Race To Halt (RTH)</td><td>Disabled, Enabled</td><td>Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled, Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.</td></tr><tr><td>Per Core P State OS control P State</td><td>Disabled, Enabled</td><td>Enable/Disable Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.</td></tr><tr><td>HwP Autonomous Per Core P State</td><td>Disabled, Enabled</td><td>Disable Autonomous PCPS (Bit 30 = 1, command 0x11). Autonomous will request the same value for all cores all the time. Enable PCPS (default Bit 30 = 0, command 0x11)</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>Disabled, Enabled</td><td>Enable EPP grouping (default Bit 29 =0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (Bit 29 =1 , command 0x11) autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>Disabled, Enabled</td><td>Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b , subcommand 0x3 to 1. This will allow OOB EPB PECI override control</td></tr><tr><td>HwP Lock</td><td>Disabled, Enabled</td><td>Enable/Disable HWP Lock support in Misc Power Management MSR.</td></tr><tr><td>HDC Control</td><td>Disabled, Enabled</td><td>This option allows HDC configuration.</td></tr><tr><td>Turbo Mode</td><td>Disabled, Enabled</td><td>Enable/Disable processor Turbo Mode (requires EMTTM enabled too). AUTO means enabled.</td></tr><tr><td>View/Configure Turbo Options</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Current Turbo Settings</td></tr><tr><td>Max Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Min Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Package TDP Limit</td><td>Info only</td><td></td></tr><tr><td>Power Limit 1</td><td>Info only</td><td></td></tr><tr><td>Power Limit 2</td><td>Info only</td><td></td></tr><tr><td>Turbo Ratio Limit Options</td><td>Submenu</td><td></td></tr><tr><td>Energy Efficient P-state</td><td>Disabled, Enabled</td><td>Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR 1B0h and CPUID Fun</td></tr><tr><td>Package Power Limit MSR Lock</td><td>Disabled, Enabled</td><td>Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.</td></tr><tr><td>Energy Efficient Turbo</td><td>Disabled, Enabled</td><td>Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave it enabled.</td></tr><tr><td>Config TDP Configurations</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Config TDP Configurations</td></tr><tr><td>Enable Configurable TDP</td><td>Applies to non-cTDP, Applies to cTDP</td><td>Applies TDP initialization settings based on non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and BIOS will bypass cTDP initialization flow</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal, Down2, Down1, Deactivate</td><td>Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>Configurable TDP Lock</td><td>Enabled, Disabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.</td></tr><tr><td>CTDP BIOS control</td><td>Enabled, Disabled</td><td>Enables Configurable Processor Base Power (cTDP) control via runtime ACPI BIOS methods. This "BIOS only" feature does not require EC or driver support.</td></tr><tr><td>ConfigTDP Levels</td><td>2</td><td>Configurable Processor Base Power (cTDP) Levels Supported from MSR</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>17 (Unlocked)</td><td>Configurable Processor Base Power (cTDP) Turbo Activation Ratio values from MSR</td></tr><tr><td>Power Limit 1</td><td>15.0W (MSR:15.0)</td><td>Power Limit 1 values from MMIO</td></tr><tr><td>Power Limit 2</td><td>15.0W (MSR:15.0)</td><td>Power Limit 2 values from MMIO</td></tr><tr><td colspan="3">Custom Settings Nominal</td></tr><tr><td>ConfigTDP Nominal</td><td>Ratio:18 TAR:17PL1:15.0W</td><td>Configurable Processor Base Power (cTDP) Nominal Ratio and Processor Base Power (TDP) from MSR</td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>15000</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0xFF, 0x00, 0x01]</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td colspan="3">Custom Settings Level1</td></tr><tr><td>ConfigTDP Level1</td><td>Ratio:10 TAR:9 PL1:9.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td> $Power\ Limit\ 2$ </td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td> $Power\ Limit\ 1\ Time\ Window*$ </td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Windowvalue in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>0</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td>CPU VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">CPU VR Settings</td></tr><tr><td>Current VccIn Aux Icc Max</td><td>108</td><td>Current VccIn Aux Icc Max</td></tr><tr><td>PSYS Slope</td><td>0</td><td>PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9."</td></tr><tr><td>PSYS Offset</td><td>0</td><td>PSYS Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. PSYS Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>PSYS Prefix</td><td>+, -</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>PSYS PMax Power</td><td>0</td><td>PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.</td></tr><tr><td>Min Voltage Override</td><td>Disabled, Enabled</td><td>Min Voltage Override. Enable to override minimum voltage for runtime and for C8.</td></tr><tr><td>VccIn Aux Icc Max</td><td>0</td><td>Sets the Max Icc VccIn Aux value defined in 1/4A increments. Range is 0-512. For an IccMax 32A, enter 128(32*4).</td></tr><tr><td>VccIn Aux IMON Slope</td><td>111</td><td>VccIN Aux IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Offset</td><td>0</td><td>VccIN Aux IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Prefix</td><td>+.-</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>Vsys/Psys Critical</td><td>Disabled, Psys Critical, Vsys Critical</td><td>Vsys/Psys Critical Enable or disable</td></tr><tr><td>Assertion Deglitch Mantissa</td><td>1</td><td>Assertion Deglitch Mantissa 0x4F[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>Assertion Deglitch Exponent</td><td>0</td><td>Assertion Deglitch Exponent 0x4F[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Mantissa</td><td>13</td><td>De Assertion Deglitch Mantissa 0x49[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Exponent</td><td>2</td><td>De Assertion Deglitch Exponent 0x49[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>VR Power Delivery Design</td><td>Auto</td><td>Specifies the ADL Desktop board design used for the VR settings override values. By default, BIOS will override the default Desktop VR settings based on the board design. A value of AUTO(0) will use the board ID to determine the board design. Any other value will override the board id logic to provide a custom VR PowerDelivery Design value. This is intended primarily for validation.</td></tr><tr><td>Acoustic Noise Settings</td><td>Submenu</td><td></td></tr><tr><td>Acoustic Noise Mitigation</td><td>Disabled, Enabled</td><td>Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state</td></tr><tr><td>Pre Wake Time</td><td>0</td><td>Set the maximum Pre Wake randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Up Time</td><td>0</td><td>Set the maximum Ramp Up randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Down Time</td><td>0</td><td>Set the maximum Ramp Down randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td colspan="3">IA VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for IA Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during the deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state.</td></tr><tr><td>Slow Slew Rate for IA Domain</td><td>Fast/2, Fast/4, Fast/8, Fast/16</td><td>Set VR IA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise</td></tr><tr><td colspan="3">GT VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for GT Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state</td></tr><tr><td>Slow Slew Rate for GT Domain</td><td>Fast/2, Fast/4, Fast/8</td><td>Set VR GT Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled</td></tr><tr><td>Core/IA VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Core/IA VR Domain</td></tr><tr><td>VR Config Enable</td><td>Disabled, Enabled</td><td>VR Config Enable</td></tr><tr><td>Current AC Loadline</td><td>500</td><td></td></tr><tr><td>Current DC Loadline</td><td>500</td><td></td></tr><tr><td>Current Psi1 Threshold</td><td>16</td><td></td></tr><tr><td>Current Psi2 Threshold</td><td>8</td><td></td></tr><tr><td>Current Psi3 Threshold</td><td>4</td><td></td></tr><tr><td>Current Imon Slope</td><td>0</td><td></td></tr><tr><td>Current Imon Offset</td><td>1</td><td></td></tr><tr><td>Current VR Current Limit</td><td>148</td><td></td></tr><tr><td>Current Tdc Current Limit</td><td>208</td><td></td></tr><tr><td>Current Voltage Limit</td><td>1600</td><td></td></tr><tr><td>AC Loadline</td><td>0</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>0</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS Current Threshold1</td><td>16</td><td>PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold2</td><td>8</td><td>PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold3</td><td>4</td><td>PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS3 Enable</td><td>Disabled, Enabled</td><td>PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS4 Enable</td><td>Disabled, Enabled</td><td>PS4 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>0</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>0</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>+, -</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Current Limit</td><td>0</td><td>Voltage Regulator Current Limit (IccMax). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>0</td><td>Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed at any given time. Range is 0 - 7999mV. Uses BIOS VR mailbox command 0x8.</td></tr><tr><td>TDC Enable</td><td>Disabled, Enabled</td><td>TDC Enable. 0- Disable, 1 - Enable</td></tr><tr><td>TDC Current Limit</td><td>0</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>1 sec</td><td>VR TDC Time Window, value in seconds. 1s is default. Range from 1s to 448s.</td></tr><tr><td>TDC Lock</td><td>Disabled, Enabled</td><td>TDC Lock</td></tr><tr><td>IRMS</td><td>Disabled, Enabled</td><td>Enables/Disables IRMS – Current root mean square</td></tr><tr><td>GT VR Settings</td><td>Submenu</td><td></td></tr><tr><td>RFI Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">RFI Domain</td></tr><tr><td>RFI Current Frequency</td><td>139.200MHz</td><td></td></tr><tr><td>RFI Frequency</td><td>0</td><td>Sets desired RFI frequency, in increments of 100KHz. (For a frequency of 100.6MHz, enter 1006.)</td></tr><tr><td>FIVR Spread Spectrum</td><td>Disabled, Enabled</td><td>Enables or Disables the Spread Spectrum</td></tr><tr><td>RFI Spread Spectrum</td><td>0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%</td><td>Set the Spread Spectrum</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled, Enabled</td><td>Enables/Disables Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>Disabled, Enabled</td><td>Enables/Disables Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2.</td></tr><tr><td>Power Limit 4 Override</td><td>Disabled, Enabled</td><td>Enables/Disables Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>Disabled, Enabled</td><td>Enables/Disables CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Thermal Monitor</td><td>Disabled, Enabled</td><td>Enables/Disables Thermal Monitor</td></tr><tr><td>Interrupt Redirection Mode Selection</td><td>Fixed Priority, Round robin, Hash Vector, NoChange</td><td>Interrupts Redirection Mode Select for Logical Interrupts</td></tr><tr><td>Timed MWAIT</td><td>Disabled, Enabled</td><td>Enables/Disable Timed MWAIT Support</td></tr><tr><td>Custom P-state Table</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Custom P-state Table</td></tr><tr><td>Number of P states</td><td>0</td><td>Sets the number of custom P-states. At lease 2 states must be present.</td></tr><tr><td>EC Turbo Control Mode</td><td>Disabled, Enabled</td><td>Enables/Disables EC Turbo Control mode</td></tr><tr><td>Energy Performance Gain</td><td>Disabled, Enabled</td><td>Enables/Disables Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>26</td><td></td></tr><tr><td>EPG DIMM ldd3P</td><td>11</td><td></td></tr><tr><td>Power Limit 3 Settings</td><td>Submenu</td><td></td></tr><tr><td>Power Limit 3 Override</td><td>Disabled, Enabled</td><td>Enables/Disables Power Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CPU Lock Configuration</td><td>Submenu</td><td>Enables/Disables Power Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CFG Lock</td><td>Disabled, Enabled</td><td>Configure MSR 0Xe2[15], CFG Lock bit</td></tr><tr><td>Overclocking Lock</td><td>Disabled, Enabled</td><td>Enables/Disables Overclocking Lock (BIT 20) in FLEX RATIO(194) MSR</td></tr></table>

7.2.2.2 Advanced > Power & Performance > GT – Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RC6(Render Standby)*</td><td>Disabled, Enabled</td><td>Check to enable render standby support.</td></tr><tr><td>Maximum GT frequency</td><td>Default Max Frequency, 100Mhz, 150Mhz, 200Mhz, 250Mhz, 300Mhz, 350Mhz, 400Mhz, 450Mhz, 500Mhz, 550Mhz, 600Mhz, 650Mhz, 700Mhz, 750Mhz, 800Mhz, 850Mhz, 900Mhz, 950Mhz, 1000Mhz, 1050Mhz, 1100Mhz, 1150Mhz, 1200Mhz</td><td>Maximum GT frequency limited by the user. Choose between 100MHz (RPN) and 1350MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU</td></tr><tr><td>Disable Turbo GT frequency</td><td>Enabled, Disabled</td><td>Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited</td></tr></table>

7.2.3 Intel® Time Coordinated Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>#AC Split Lock*</td><td>Enabled, Disabled</td><td>Enables or Disables Alignment Check Exception (#AC). When enabled, this will assert an #AC when any atomic operation has an operand that crosses two cache lines.</td></tr><tr><td>#GP Fault UC Lock</td><td>Enabled, Disabled</td><td>Enables or Disables GP Fault Exception (GP#). When enabled, this will assert an GP# when encountering a Lock to un-cacheable memory before the bus is locked.</td></tr><tr><td>Intel(R) TCC Authentication*</td><td>OEM Enrolled Key</td><td>Intel(R) TCC Authentication determines the key to be used. OEM Enrolled Key is built in by OEM. Non-OEM Enrolled Key can be added by the user.</td></tr><tr><td>Intel(R) TCC Mode*</td><td>Enabled, Disabled</td><td>Enables or Disables Intel(R) TCC Mode. When enabled, this will modify system settings to improve real-time performance. The full list of settings and their current state are displayed below when Intel(R) TCC mode is enabled.</td></tr><tr><td>Intel(R) TCC Mode Affected Settings</td><td></td><td></td></tr><tr><td>IO Fabric Low Latency*</td><td>Disabled, Enabled</td><td>Enables or Disables IO Fabric Low Latency. This will turn off some power management in the PCH IO fabrics. This option provides the most aggressive IO Fabric performance setting. S3 state is NOT supported.</td></tr><tr><td>GT CLOS*</td><td>Disabled, Enabled</td><td>Enables or Disables Graphics Technology(GT) Class of Service. Enable will reduce Gfx LLC allocation to minimize impact of Gfx workload on LLC</td></tr><tr><td>C states*</td><td>Disabled, Enabled</td><td>Enables/Disables CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Intel(R) Speed Shift Technology*</td><td>Disabled, Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Intel(R) SpeedStep(tm)*</td><td>Disabled, Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>ACPI D3Cold Support*</td><td>Disabled, Enabled</td><td>Enables/Disables ACPI D3Cold support to be executed on D3 entry and exit</td></tr><tr><td>Low Power S0 Idle Capability*</td><td>Disabled, Enabled</td><td>This variable determines if we enable ACPI Lower Power S0 Idle Capability (Mutually exclusive with Smart connect). While this is enabled, it the disables 8254 timer for SLP_S0 support.</td></tr><tr><td>SA GV*</td><td>Disabled, Fixed to 1st Point,Fixed to 2nd Point, Fixed to 3rd Point, Fixed to 4th Point, Enabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency switching.</td></tr><tr><td>Page Close Idle Timeout*</td><td>Enabled, Disabled</td><td>Page Close Idle Timeout Control</td></tr><tr><td>Power Down Mode*</td><td>Auto, No Power Down, APD,PPD-DLLoff</td><td>CKE Power Down Mode Control</td></tr><tr><td>RC6(Render Standby)*</td><td>Disabled, Enabled</td><td>Check to enable render standby support.</td></tr><tr><td>DMI Link ASPM Control*</td><td>Disabled,L0s, L1, Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>Legacy IO Low Latency*</td><td>Disabled, Enabled</td><td>Set to enable low latency of legacy IO. Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.</td></tr><tr><td>CPU PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH PCI Express Configuration</td><td>Submenu</td><td></td></tr></table>

7.2.4 Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enables/Disables eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>LVDS Backlight Mode</td><td>EC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight</td><td>Submenu</td><td></td></tr><tr><td>LVDS Backlight Brightness</td><td>Value Range (0-255)</td><td>A change takes effect immediately. The value range starts by 0 and ends of 255.</td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatibility</td><td>DDI port 1 function: choose between DisplayPort or HDMI</td></tr><tr><td>DDI port 2</td><td>No DeviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatibility</td><td>DDI port 2 function: choose between DisplayPort or HDMI</td></tr></table>

7.2.5 Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Disabled, Enabled</td><td>Enables or disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Disabled, Enabled</td><td>Enables or disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State*</td><td>Suspend Disabled, S3(Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>LID Function</td><td>Disabled, Enabled</td><td>Enables/Disables LID Function</td></tr><tr><td>Sleep Function</td><td>Disabled, Enabled</td><td>Enables/Disables Sleep Button Function</td></tr><tr><td>ECO Mode*</td><td>Disabled, Enabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power-Up Mode*</td><td>Turn On, Remain Off, Last State</td><td>Turn On:</td></tr><tr><td colspan="3">ATTENTION: The Power-Up Mode only has effect,</td></tr><tr><td colspan="3">if the module is in ATX-Mode.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td></td></tr></table>

# 7.2.5.1 Advanced > Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info only</td><td></td></tr><tr><td>Main Current</td><td>Read only</td><td>Displays input current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Displays input power.</td></tr><tr><td>RTC</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>5VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>VIN</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3V</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VMEM</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VCORE</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr></table>

# 7.2.6 Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info Only</td><td></td></tr><tr><td>Version</td><td>Info Only</td><td>Displays SEMA Module Version.</td></tr><tr><td>SEMA Firmware</td><td>Info Only</td><td>Displays SEMA Firmware Version.</td></tr><tr><td>SEMA Flags</td><td>Submenu</td><td>Displays SEMA Flags</td></tr><tr><td>SEMA Features</td><td>Info</td><td>Displays SEMA Supported Features</td></tr></table>

7.2.6.1 Advanced > System Management > SEMA Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Flags</td><td>Info Only</td><td></td></tr><tr><td>BIOS Select</td><td>Info Only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Info Only</td><td></td></tr></table>

7.2.7 Advanced > Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info Only</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C100 C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled</td></tr><tr><td>Temperature and Fan Speed</td><td>Submenu</td><td></td></tr></table>

7.2.7.1 Advanced > Thermal Management > Temperature and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Displays Current CPU Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Displays Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Displays Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Displays Max Board Temperature</td></tr><tr><td>Board Temperatures</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Displays Current Board Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Displays Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Displays Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Displays Max Board Temperature</td></tr></table>

7.2.8 Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>Disabled Enabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up. Pressing F12 druing start up disables the Power Up Watchdog</td></tr><tr><td>Timeout</td><td>65535</td><td>Here you can enter the time the Power Up Watchdog should wait until it resets the system. The value range starts by 24 and ends by 65535</td></tr><tr><td>RunTime Watchdog</td><td>Disabled Enabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>24</td><td>Here you can enter the time the Runtime Watchdog should wait until it resets the system. The value range starts by 30 and ends by 65535.</td></tr></table>

7.2.9 Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>IT5121E Super IO Configuration</td><td>Submenu</td><td>System Super IO Chip Parameters.</td></tr></table>

7.2.9.1.1 Advanced > Super IO Configuration > IT5121E Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">IT5121E Super IO Configuration</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr></table>

Submenu: Super IO Configuration > Serial Port x Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Serial Port 1 Configuration</td></tr><tr><td>Serial Port 1 Configuration</td><td>Disabled, Enabled</td><td>Set Parameters of Serial Port 1</td></tr><tr><td>Device Settings</td><td>4;</td><td></td></tr><tr><td>Change Settings</td><td>Auto, IO=3F8h; IRQ=4;, IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12;</td><td>Select an optimal setting for Super IO Device</td></tr><tr><td colspan="3">Serial Port 2 Configuration</td></tr><tr><td>Serial Port 2 Configuration</td><td>Disabled, Enabled</td><td>Serial Port 2 Configuration</td></tr><tr><td>Device Settings</td><td>3;</td><td>Device Settings</td></tr><tr><td>Change Settings</td><td>Auto, IO=2F8h; IRQ=3;, IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12;,IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12;, Normal, High Speed</td><td>Change Settings</td></tr></table>

7.2.10 Advanced > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions (S3 &amp; S4) to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. ATX: OS will turn off system power when shutdown.</td></tr><tr><td>I2C Speed Control</td><td>100 kbps400 kbps</td><td>I2C Speed Control</td></tr><tr><td>WOL From S5</td><td>OFFON</td><td>This Config to control power on/off LAN in S5 State by SEMA(EC).</td></tr><tr><td>LID Function</td><td>DisabledEnabled</td><td>Enable/Disable LID function.</td></tr><tr><td>Sleep Function</td><td>DisabledEnabled</td><td>Enable/Disable Sleep Function.</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr></table>

7.2.11 Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attachment USB devices.</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable / Disable USB Mass Storge Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.&#x27;Auto&#x27; uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.</td></tr><tr><td>Mass Storage Device</td><td>Info Only</td><td></td></tr></table>

7.2.12 Advanced > AMI Graphics Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Intel(R) Graphics Controller</td></tr><tr><td colspan="3">Intel(R) GOP Driver [21.0.10XX]</td></tr><tr><td>Output Select</td><td>HDMI</td><td>Auto detect Output Interface</td></tr><tr><td>Output Select*</td><td>HDMI/DP/eDP</td><td>Manual select Output Interface</td></tr><tr><td>Brightness Setting</td><td>[ Max-Value, Min-Value, Step-Value, Step-Value] = [ 0xFFFFFFF, 0x00000000, 0x00000001, Brightness Setting]</td><td>Item shown when eDP detectedSet Gop Brightness value</td></tr><tr><td>BIST Enable</td><td>Disabled, Enabled</td><td>Item shown when eDP detectedStarts or stops the BIST on the integrated display panel.</td></tr></table>

7.2.13 Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>Disabled, Enabled</td><td>To enable or disable console redirection of COMx.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

7.2.13.1Advanced > Serial Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Configure the type of console emulation.Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Configure the number of data bits in each transmitted or received serial character for both serial ports.</td></tr><tr><td>Parity</td><td>NoneEvenOdd</td><td>Configures if parity bit is generated (transmit data) or checked.A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Configures the number of stop bits transmitted and received in each serial character for both serial ports. Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareSoftware</td><td>Configures flow control for console redirection. Hardware flow control uses RTC/CTS. Software flow control uses XON/XOFF.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 combination key support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables or disables extended terminal resolution.</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select Function Keys and Key Pad on Putty.</td></tr></table>

7.2.14 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Disabled, Enabled</td><td>Enable/Disable UEFI Network Stack</td></tr><tr><td>IPv4 PXE Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv4 HTTP Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.</td></tr><tr><td>IPv6 PXE Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>IPv6 HTTP Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>[ Max-Value, Min-Value, Step-Value] =[ 0x05, 0x00, 0x01]</td><td>Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>[ Max-Value, Min-Value, Step-Value] =[ 0x32, 0x01, 0x01]</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

7.2.15 Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable, Enable</td><td>Enables or Disables BIOS support for security device.O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td colspan="3">NO Security Device Found</td></tr></table>

# 7.3 Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>submenu</td><td></td></tr></table>

# 7.3.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Stop Grant Configuration</td><td>Auto</td><td>Automatic/Manual stop grant configuration</td></tr><tr><td>VT-d</td><td>Enabled, Disabled</td><td>VT-d capability</td></tr><tr><td>Control Iommu Pre-boot Behavior</td><td>Disable IOMMUEnable IOMMU during boot</td><td>Enable IOMMU in Pre-boot environment (If DMAR table is installed in DXE and If VTD_INFO_PPI is installed in PEI.)</td></tr><tr><td>X2APIC Opt Out</td><td>Enabled, Disabled</td><td>Enable/Disable X2APIC_OPT_OUT bit</td></tr><tr><td>DMA Control Guarantee</td><td>Enabled, Disabled</td><td>Enable/Disable DMA_CONTROL_GUARANTEE bit</td></tr><tr><td>WRC Feature</td><td>Enabled, Disabled</td><td>Enable/Disable SA WRC(Write Cache) Feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enabled, Disabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB.</td></tr><tr><td>IPU Device (B0:D5:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU Device.</td></tr><tr><td>IPU 1181 Dash Camera</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU 1181 Dash Camera support.</td></tr></table>

7.3.1.1 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info-only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info-only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info-only</td><td></td></tr><tr><td>Controller x Channel x Slot x</td><td>Info-only</td><td></td></tr><tr><td>Size</td><td>Info-only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info-only</td><td></td></tr><tr><td>Manufacturer</td><td>Info-only</td><td></td></tr><tr><td>Memory Test on Warm Boot</td><td>Enabled, Disabled</td><td>Enable Or Disable Base Memory Test Run on Warm Boot</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067133314001600180018672000213322002400260026672800293330003200</td><td>Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller</td></tr><tr><td>SA GV</td><td>Enabled, Disabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency swithing.</td></tr><tr><td>Controller 0, Channel X DIMM Control</td><td>Enabled, Disabled</td><td>Controller 0, Channel X DIMM Control Support - Enable or Disable Dimms on Controller 0, Channel X.</td></tr><tr><td>Controller 1, Channel X DIMM Control</td><td>Enabled, Disabled</td><td>Controller 1, Channel X DIMM Control Support - Enable or Disable Dimms on Controller 1, Channel X.</td></tr><tr><td>Force Single Rank</td><td>Disabled, Enabled</td><td>When enabled, only Rank 0 will be used in each DIMM</td></tr><tr><td>In-Band ECC Support (Industrial SKU only)</td><td>Enabled, Disabled</td><td>Enable/Disable In-Band ECC. Either the IBECC or the TME can be enabled.</td></tr></table>

7.3.1.2 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>Disabled, Enabled</td><td>If enabled, it will not scan for External Gfx Card on PEG and PCH PCIE Ports</td></tr><tr><td>Primary Display</td><td>Auto, IGFX, PEG Slot, PCH PCI, HG</td><td>Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select HG for Hybrid Gfx.</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>submenu</td><td></td></tr><tr><td>Internal Graphics</td><td>Auto, Disabled, Enabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB, 4MB, 8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB, 256MB, 512MB, 1024MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M, 32M, 64M, 96M, 128M, 160M, 4M, 8M, 12M, 16M, 20M, 24M, 28M, 32M/F7, 36M, 40M, 44M, 48M, 52M, 56M, 60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>Intel Graphics Pei Display Peim</td><td>Enabled, Disabled</td><td>Enable/Disable Pei (Early) Display</td></tr></table>

7.3.1.3 Chipset > System Agent (SA) Configuration > MIPI Camera Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CVF Support</td><td>Disabled, Enabled</td><td>Disables/Enables CVF using either Native IOs or USB IOs Expansion.</td></tr><tr><td>Control Logic 1</td><td>Disabled, Enabled</td><td>Control Logic 1</td></tr><tr><td>Control logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Control logic 2</td><td>Disabled, Enabled</td><td>Control logic 2</td></tr><tr><td>Control logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Camera1</td><td>Disabled, Enabled</td><td>Camera1</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr><tr><td>Camera2</td><td>Disabled, Enabled</td><td>Camera2</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr></table>

7.3.2 Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>Security Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr><tr><td>Seriallo Configuration</td><td>Submenu</td><td></td></tr><tr><td>SCS Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN Controller</td><td>Info-Only</td><td>No GbE Region</td></tr><tr><td>Port 80h Redirection</td><td>Fixed setting- LPC Bus</td><td>Control where the Port 80h cycles are sent.</td></tr><tr><td>Enhance Port 80h LPC Decoding</td><td>Enabled, Disabled</td><td>Supports the word/dword decoding of port 80h behind LPC</td></tr><tr><td>Enable TCO Timer</td><td>Disabled, Enabled</td><td>Enable/Disable TCO timer. When disabled, it disables PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.</td></tr><tr><td>Pcie Ref PII SSC</td><td>Auto, 0.0%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2.0%, Disable</td><td>Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.</td></tr><tr><td>SPD Write Disable</td><td>TRUE, FALSE</td><td>Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr></table>

7.3.2.1 Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>DMI Link ASPM Control</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>Port8xh Decode</td><td>Disabled, Enabled</td><td>PCI Express Port8xh Decode Enable/Disable.</td></tr><tr><td>PCIE Ports 9-12 Configuration</td><td>4x1 Port, 1x2 2x1 Port, 2x2 Port, 1x4 Port</td><td>To configure PCI-E Port 9-12 of PCH.[4X1]:Port 1-4 (x1) and Port 8 (x1) / [1x2 2x1]:Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1) / [2x2]:Port 1-2 (x2) and Port 3-4 (x2) / [1x4]:Port 1 (x4), Ports 2-4 (disabled)</td></tr><tr><td>Select PCIE/SATA Combo port 1</td><td>PCIE portSATA port</td><td>Notes: Please make sure the system boots completed after changing the configuration.\r\nDo Not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.</td></tr><tr><td>PCI Express Root Port 3</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 4</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 7</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 9</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 10</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 11</td><td>Submenu</td><td>.</td></tr><tr><td>PCI Express Root Port 12</td><td>Submenu</td><td></td></tr></table>

7.3.2.1.1 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port#

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port</td><td>DisabledEnable</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-inSlot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level.Force L0s - Force all links to L0s StateAuto - BIOS auto configure;Disabled - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>L1 Low</td><td>DisabledEnable</td><td>PCI Express L1 Low Substate Enable/Disable.</td></tr><tr><td>ACS</td><td>DisabledEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>DisabledEnable</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>DisabledEnable</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>DisabledEnable</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>DisabledEnable</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>DisabledEnable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled Enable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled Enable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>CTO</td><td>Disabled Enable</td><td>PCI Express Completion Timer TO Enable/Disable</td></tr><tr><td>SEFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled Enable</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled Enable</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>Disabled Enable</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Configure PCIe Speed.</td></tr><tr><td>Transmitter Half Swing</td><td>Disabled Enabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Non-Compliance</td><td>Disabled Enable</td><td>Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB.</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info only</td><td></td></tr><tr><td>LTR</td><td>DisabledEnable</td><td>PCH PCIE Latency Reporting Enable/Disable.</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow."</td></tr><tr><td>Non Snoop Latency Override</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>LTR Lock</td><td>DisabledEnable</td><td>PCIE LTR Configuration Lock</td></tr></table>

7.3.2.2 Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Disabled, Enabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Controller Speed</td><td>Default, Gen1, Gen2, Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Test Mode</td><td>Disabled, Enabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Aggressive LPM Support</td><td>Disabled, Enabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>Serial ATA Port X</td><td>Info-Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info-Only</td><td></td></tr><tr><td>Port X</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td>Info Only</td><td></td></tr><tr><td>External</td><td>Disabled, Enabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>Disabled, Enabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive, Solid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td></td></tr><tr><td>SATA Port X DevSlp</td><td>Disabled, Enabled</td><td></td></tr><tr><td>DITO Configuration</td><td>Disabled, Enabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO Value</td><td>625</td><td>DITO Value</td></tr><tr><td>DM Value</td><td>15</td><td>DM Value</td></tr></table>

7.3.2.3 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xDCI Support</td><td>Disabled, Enabled</td><td>Enable/Disable xDCI (USB OTG Device).</td></tr><tr><td>USB2 PHY Sus Well Power Gating</td><td>Disabled, Enabled</td><td>Select 'Enabled' to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H</td></tr><tr><td>USB PDO Programming</td><td>Disabled, Enabled</td><td>Select 'Enabled' if Port Disable Override functionality is used.</td></tr><tr><td>USB Overcurrent</td><td>Disabled, Enabled</td><td>Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>Disabled, Enabled</td><td>Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Audio Offload</td><td>Disabled, Enabled</td><td>Enable/Disable USB Audio Offload functionality</td></tr><tr><td>Enable HSII on xHCI</td><td>Disabled, Enabled</td><td>Enable/Disable HSII feature. It may lead to increased power consumption.</td></tr><tr><td>USB3.1 Portx Speed Selection</td><td>0</td><td>Port Selection value in decimal for Gen1; Default - Gen2; Bit 0 corresponds to Port 0 and so on</td></tr><tr><td>USB Port Disable Override</td><td>Disabled, Select Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr></table>

7.3.2.4 Chipset > PCH-IO Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Memory Lock</td><td>Disabled, Enabled</td><td>Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>Disabled, Enabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr><tr><td>Force unlock on all GPIO pads</td><td>Disabled, Enabled</td><td>If Enabled BIOS will force all GPIO pads to be in unlocked state</td></tr></table>

7.3.2.5 Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device.</td></tr></table>

7.3.2.6 Chipset > PCH-IO Configuration > Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C1 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C5 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>SPI0 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART0 Controller</td><td>Disabled, Enabled, Communication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART1 Controller</td><td>Disabled, Enabled, Communication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART2 Controller</td><td>Disabled, Enabled, Communication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>GPIO IRQ Route</td><td>IRQ14, IRQ15</td><td>Route all GPIOs to one of the IRQ.</td></tr><tr><td>Serial IO UART0 Settings</td><td>Submenu</td><td></td></tr><tr><td>Serial IO UART2 Settings</td><td>Submenu</td><td></td></tr></table>

7.3.2.7 Chipset > PCH-IO Configuration > SCS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>eMMC 5.1 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables eMMC Controller</td></tr><tr><td>eMMC 5.1 HS400 Mode</td><td>Disabled, Enabled</td><td>Enables/Disables SCS eMMC 5.1 HS400 Mode</td></tr></table>

# Security

7.4.1 Security > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Setup Administrator Password</td><td>Enter Password</td><td>Set Setup Administrator Password</td></tr><tr><td>User Password</td><td>Enter Password</td><td>Set User Password</td></tr><tr><td>Secure Boot</td><td>Submenu</td><td></td></tr></table>

7.4.2 Security > Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Boot</td><td>DisabledEnabled</td><td>Secure Boot feature is Active if Secure Boot is enabled, platform Key(PK) is enrolled and the System is in User mode, The mode change requires platform reset</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode options: Standard or Custom.In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication</td></tr><tr><td>Restore Factory Keys</td><td></td><td>Force System to User Mode.Install factory default Secure Boot key databases</td></tr><tr><td>Reset To Setup Mode</td><td></td><td>Delete all Secure Boot Key databases from NVRAM.</td></tr><tr><td>Key Management</td><td>Submenu</td><td>Enables expert users to modify. Secure Boot Policy variables without variable authentication.</td></tr></table>

# Boot

7.5.1 Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for the BBS boot option.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll Sata Devices</td><td>If Last Boot SATA Devices Only is selected, only the last boot SATA device will be available in POST. If All SATA devices is selected, all SATA devices will be available in OS and POST.</td></tr><tr><td>VGA Support</td><td>AutoEFI Driver</td><td>If set to Auto, only the installed Legacy OpRom with Legacy OS and logo will NOT be shown during POST. The EFI driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>DisabledFull InitialPartial Initial</td><td>If disabled, all USB devices will NOT be available until after the OS boots. If set to Partial Initial, USB mass storage and specific USB ports/devices will NOT be available before the OS boots. If enabled, all USB devices will be available in both OS and POST.</td></tr><tr><td>PS2 Devices Support</td><td>DisabledEnabled</td><td>If disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>DisabledEnabled</td><td>If Disabled, Network Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>DisabledEnabled</td><td>If disable, the Redirection function will be disabled.</td></tr><tr><td>Boot Mode select</td><td>UEFILEGACY</td><td>Select boot mode LEGACY/UEFI</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Info only</td><td></td></tr><tr><td>UEFI Hard Disk Drive BBS Priorities</td><td>Submenu</td><td></td></tr><tr><td>UEFI Application Boot Priorities</td><td>Submenu</td><td></td></tr></table>

Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td></td></tr><tr><td>Restore Defaults</td><td></td><td></td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the user defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

# 8. BIOS Checkpoints, Beep Codes

This document section lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined are inherent to the AMIBIOS generic core and do not include any chipset or board-specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout the boot block and Power-On Self-Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized and generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers to the following “boot phases”, which may apply to various status codes & checkpoint descriptions:

Security (SEC) – initial low-level initialization
Pre-EFI Initialization (PEI) – memory initialization1
• Driver Execution Environment (DXE) – main hardware initialization2
• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, …)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a POST Card or POST Diagnostic Card. These are PCI addin cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited- since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

1 Analogous to “boot block” functionality of legacy BIOS
2 Analogous to “POST” functionality in legacy BIOS

Status Code Ranges

<table><tr><td>Code Range</td><td>Description</td></tr><tr><td colspan="2"></td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xFC</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# Standard Status Codes

# 8.2.1 SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr></table>

<table><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2 SEC Phase > SEC Beep Codes

None.

8.2.3 SEC Phase > PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self-test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr></table>

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB - 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4 SEC Phase > PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5 SEC Phase > DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

8.2.6 SEC Phase > DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

8.2.7 SEC Phase > ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

OEM-reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

# 9. Software Support

# Yocto

Yocto is available on ADLINK Github > https://github.com/ADLINK/meta-adlink-x86-64bit

# Ubuntu

Ubuntu is supported from kernel 5.15 and up.

# 9.3 Windows

Windows 11 is supported.

# 10. Mechanical and Thermal

# Module Dimensions

PCB dimension: 82 x 50 x 1.2 mm, 12 layer PCB

![This is a technical engineering drawing featuring multiple views and details of a module.\n\n**Top Left View:**\n*   **Text:** 'Module Primary (Top) Side'\n*   **Dimensions/Labels:**\n    *   Vertical: 0, 4, 50, 46\n    *   Left side vertical stack: 12, 7.70, 6.20, 3.30, 3.10, 0\n    *   Bottom edge: 1.25 PIN P1\n    *   Bottom width: 39\n    *   Pin sections: '74 PINS P1 - P74' and '82 PINS P75 - P156'\n    *   Top right corner dimensions: 78, 82\n    *   Hole callouts: '4X Ø6' and '4X Ø2.70 THROUGH'\n\n**Top Right View:**\n*   **Text:** 'Module Primary (Bottom) Side'\n*   **Dimensions/Labels:**\n    *   Top edge: '1.00 PIN S1'\n    *   Pin sections: '75 PINS S1 - S75' and '83 PINS S76 - S158'\n    *   Circled letters near holes: D, E, F\n\n**Middle Row (Detail Views):**\n*   **Left Detail (DETAILA):**\n    *   **Text:** 'DETAILA TOP SIDE'\n    *   **Dimensions/Labels:** '73X0.50', '81X0.50', '156X0.35', 'FULLRAD'\n    *   Vertical: '3.30', '3.10 TYP'\n    *   Horizontal: '1.00', '1.25', '1.25'\n    *   Pins: 'P74', 'P75'\n*   **Center Detail (DETAILC):**\n    *   **Text:** 'DETAILC NOTCH, 2 PLACES'\n    *   **Dimensions/Labels:** '1.70', '6.20', '(1.50)', 'S1', '2X R0.50'\n*   **Right Detail (Pin Alignment):**\n    *   **Text:** 'PIN ALIGNMENT DETAL'\n    *   **Labels:** 'P74', 'P75' (TOP SIDE), 'S75', 'S76' (BOTTOM SIDE)\n    *   **Dimension:** '0.25'\n*   **Far Right Detail (DETAILB):**\n    *   **Text:** 'DETAILB BOTTOM SIDE'\n    *   **Dimensions/Labels:** '1', '1', '74X0.50', '82X0.50', '3.10 TYP', '158X0.35'\n    *   Pins: 'S75', 'S76'\n\n**Bottom Row:**\n*   **Left Detail (Chamfer):**\n    *   **Text:** 'CHAMFEREDGE DETAL'\n    *   **Dimensions/Labels:** '0.18', '1.20±0.1', '45°'\n*   **Right Detail (Side View):**\n    *   **Text:** '3.00 MAX COMPONENT HEIGHT (TOP SIDE)'\n    *   **Text:** '1.30 MAX COMPONENT HEIGHT (BOTTOM SIDE)'](.lec-aln-asl-manual-50m-72519-1020-12/7e9e735794977951a685a015e146f57f5ee8eaa79c815b6677ab13c3396a4920.jpg)
Figure 4 – Module dimensions

# Thermal Solutions

For optimal performance, LEC-ALN / ASL has to be cooled by a passive heat sink / heat spreader, which is optionally available for purchase.

![This is a technical engineering drawing showing four orthographic views of a rectangular component with vertical fins and mounting holes.\n\n**Top Left View (Front View):**\n*   Vertical dimension labels on the far left: **78**, **82**.\n*   Vertical markers on the left edge: **42**, **38**, **34**, **8**, **4**, **0**.\n*   Vertical markers on the right edge: **34**, **8**, **0**.\n*   Vertical marker at top right: **4**.\n*   Vertical marker at bottom right: **0**.\n\n**Top Right View (Side View):**\n*   Top horizontal dimension: **12±0.3**.\n*   Middle vertical dimension: **0.75+0.05** over **-0**.\n*   Bottom horizontal dimension: **3±0.1**.\n\n**Bottom Left View (Side View):**\n*   Top oval label: **④ 3±0.1**.\n*   Middle oval label: **⑤ 1.2±0.1**.\n*   Bottom oval label: **⑥ 1.8±0.1**.\n\n**Bottom Right View (Rear/Bottom View):**\n*   Top oval label: **① 82±0.2**.\n*   Left oval label: **② 42±0.2**.\n*   Vertical text on the right edge: **NC1765**.](.lec-aln-asl-manual-50m-72519-1020-12/9b86ddfafc6f22373f6cec968737dcd26804584790ff8590c4513082319335b6.jpg)

<table><tr><td>HTS-sALN</td><td>Heat spreader for LEC-ALN / ASL</td></tr><tr><td>THS-sALN</td><td>Low profile heat sink for LEC-ALN / ASL</td></tr></table>

Figure 5 – Thermal solutions
[🔗 Link to the original document](.lec-aln-asl-manual-50m-72519-1020-12/lec-aln-asl-manual-50m-72519-1020-12.pdf)