# LEC-BT

# (Low Energy Computer on Module)

Technical Reference

P/N 50-1Z166-1020

Rev 3.00

![The image features a green, cross-shaped graphic with rounded edges, resembling a plus sign. The shape has a color gradient that transitions from a dark olive green on the left side to a bright lime green on the right side. A white square cutout is positioned in the exact center of the shape. The background is plain white.](.lec-bt-50-1z166-1020-300-en/10be18702d8b62e0839d1ed345e3b30b6a052ab5fdebde24ac3af0bf8fda129a.jpg)

# SMARC

![Close-up of an ADLINK TECHNOLOGY INC. circuit board with integrated circuits and connectors (no readable text or symbols beyond component labels)](.lec-bt-50-1z166-1020-300-en/c209079101f8f9c9aa471fb3a942c5f3ca54c3a8cbfd3c327231def43a8fc7d2.jpg)

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Reason for Change</td><td>Date</td></tr><tr><td>1.00</td><td>Initial Release</td><td>Feb/16</td></tr><tr><td>2.00</td><td>Updated AFB signals in Table 3-2; removed PCAM signals from Table 3-2; added section 4 Utilities; updated block diagram</td><td>Feb/16</td></tr><tr><td>3.00</td><td>Added Electrical Specifications table to chapter 1 to define input voltage as a fixed 5V supply</td><td>Aug/16</td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr></table>

ADLINK Technology, Incorporated

www.adlinktech.com

© Copyright 2014, 2015, 2016 ADLINK Technology, Incorporated

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Important Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this manual for future reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);
 Make sure to use recommended voltage and power source settings;
 Always install and operate equipment near an easily accessible electrical socketoutlet;
 Secure the power cord (do not place any object on/over the power cord);
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
 If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Table of Contents

# 1 Overview ...

1.1 Block Diagram...
1.2 Major Components (ICs). . 2
1.3 Connectors, Switches, and LEDs .. 4
1.4 Specifications... 6

1.4.1 Physical Specifications . ..6
1.4.2 Mechanical Specifications . ..6
1.4.3 Electrical Specifications ..
1.4.4 Power Specifications ..
1.4.5 Environmental Specifications..
1.4.6 Thermal/Cooling Requirements .. .8

# 2 Hardware .. 9

2.1 CPU .. 9
2.2 Memory ..... 9
2.3 eMMC NAND Flash .. 9

# 3 Interfaces ....... ..... 10

3.1 18/24 Bit LVDS LCD . 10
3.2 HDMI (High-Definition Multimedia Interface) .. .. 10
3.3 Camera (CSI)... 11
3.4 Audio (HDA)... 11
3.5 PCI Express (PCIe).. 11
3.6 Gigabit Ethernet 11
3.7 USB Ports .... 11

3.7.1 USB 2.0 . .11
3.7.2 USB 3.0 . .11

3.8 SATA... 11
3.9 I2C Bus ..... 12
3.10 SPI .. 12
3.11 Serial (UART)... . 12
3.12 I2S (Audio) ... 12
3.13 SD/SDIO Interface ...... 12
3.14 eMMC Interface ... . 12
3.15 GPIO .. . 13
3.16 AFB (Alternate Function Block).. . 13
3.17 LPC Debug . 14
3.18 SMARC Interface Signals . 14
3.19 Debug (DB40)... . 21

# 4 Utilities .... 23

4.1 BIOS.. 23

4.1.1 Configuring the BIOS .. . 23
4.1.2 Main screen of the BIOS .. . 23
4.1.3 Advanced Settings screen . . 24
4.1.4 Security screen .... . 32
4.1.5 Boot screen .... . 32
4.1.6 Save & Exit screen.. . 33

4.2 SEMA functions... 34

4.2.1 Board Specific SEMA functions ...... . 34

4.3 Watchdog Timer.. 36
4.4 Temperature Sensors . 36
4.5 Programming Examples.. 36

# Appendix A Technical Support ..... . 37

# 1 Overview

This manual presents a general overview of the LEC-BT. After reviewing this document you should understand the following perspectives of the LEC-BT.

 Feature Overview
 Hardware Functions
 Interface Definitions
 Utility Definitions
 Contact Information

NOTE: Refer to http://www.sget.org/standards/smarc.html for SMARC specifications. Please refer to BSP readme documents in the Quick Drive for BSP installation instructions.

# 1.1 Block Diagram

Figure 1-1 represents the component functions of the module.
![**Central Blocks:**\n*   **Intel® Bay Trail-I SoC** (Large central vertical rectangle)\n*   **314-pin Golden finger** (Large vertical rectangle on the left)\n\n**Peripheral Blocks:**\n*   **LVDS RTD2136**\n*   **GPIO PCA9535A**\n*   **LAN i210IT**\n*   **BMC HWM**\n*   **SPI-BIOS**\n*   **DDR3L Memory down 2/4/8 GB ECC**\n*   **eMMC 4-64 GB**\n*   **PMIC IDTP9145**\n*   **Debug Connector for DB40**\n\n**Connections:**\n\n**Left Side (Golden finger (-) SoC/Peripherals):**\n*   **LVDS:** `LVDS 18/24bit Single channel` connects to **LVDS RTD2136**, which connects to **DDI0**.\n*   **Display/Audio:** `DDI1 (HDMI)`, `HDA (default) or I2S`, and `1x I2C PM` connect directly between the Golden finger and SoC.\n*   **GPIO:** `12x GPIO (5x reserved for CSI)` connects to **GPIO PCA9535A**, which connects to **SMBus** and **INT**.\n*   **LAN:** `GbE` connects to **LAN i210IT**, which connects via **PCIe x1**.\n*   **PCIe:** `PCIe x1, PCIe port 1,2,3` connects directly.\n*   **Camera/Serial/USB:** `MIPI CSI Camera (4L/1L), I2C for CAM`, `2x Serial (incl. RTS/CTS) + PCU-UART`, `1x USB2.0 client, 2x USB2.0 host`, and `1x USB3.0 and 1x USB2.0 on AFB` connect directly.\n*   **Storage/IO:** `2x SATA`, `SDIO x4`, and `Power Management` connect directly.\n*   **Boot/Management Cluster:**\n    *   `BOOT Select` connects to **BMC HWM**.\n    *   `2x I2C (GP/LVDS)` connects to **BMC HWM**.\n    *   **BMC HWM** connects via **SMB**.\n    *   **BMC HWM** connects vertically to **SPI-BIOS**.\n    *   **SPI-BIOS** connects via **1x SPI**.\n    *   A separate **1x SPI** connection exists at the very bottom.\n\n**Right Side (SoC (-) Peripherals):**\n*   **Memory:** **DDR3L 1066/1333MHz** connects to **DDR3L Memory down 2/4/8 GB ECC**.\n*   **Storage:** **8bit eMMC** connects to **eMMC 4-64 GB**.\n*   **PMIC:** An unlabeled arrow connects SoC to **PMIC IDTP9145**.\n*   **Debug:** **LPC** connects to **Debug Connector for DB40**.](.lec-bt-50-1z166-1020-300-en/9ccf326dcf31d8f9646492a9c1d4ae1447d587d4a270f836dea78aa2b21bc389.jpg)

Figure 1-1: Functional Block Diagram

# 1.2 Major Components (ICs)

Table 1-1 lists the major integrated circuits on the LEC-BT, including a brief description of each IC. Figure 1-2 shows the locations of the major ICs.

Table 1-1: Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U1)</td><td>Intel</td><td>E3845 (quad core, 10W, 1.91GHz)E3826 (dual core, 7W, 1.46GHz)E3815 (single core, 5W, 1.46GHz)E3805 (dual core, 3W, headless, 1.33GHz)</td><td>Atom, 22nm SoC (System on Chip) with Intel 64 architecture</td><td>Integrates Processor Core, Graphics and Memory Controller Hub, and I/O Hub</td></tr><tr><td>Ethernet Controller (U9)</td><td>Intel</td><td>WGI210IT SLIXT</td><td>Single-port Gigabit Ethernet controller</td><td>Integrates GbE MAC, PHY, and SGMII/SerDes to enable 10T/100TX/1000T Ethernet signals using the PCIe x1 bus</td></tr><tr><td rowspan="2">DDR3L SDRAM (U24, U25, U26, U27, U28, U29, U30 [ECC], U31, U32)</td><td>Micron</td><td rowspan="2">MT41K256M8RH-125 (2GB model)MT41K512M8RH-125 (4GB model)IM8G08D3FBBG-15EI (8GB model)</td><td rowspan="2">On-board DDR3L, 1.35V2Gb, 32Mx8x84Gb, 64Mx8x88Gb, 128Mx8x8System Memory</td><td rowspan="2">Provides high-speed data transfer</td></tr><tr><td>Intelligent Memory</td></tr><tr><td>eMMC, NAND Flash (U48 - on bottom side)</td><td>Micron</td><td>MTFC8GLVEA-4M-IT</td><td>MultiMediaCard Controller and NAND Flash Memory up to 64GB</td><td>Provides communication and mass data storage capabilities</td></tr></table>

# Key:

U1 - CPU
U9 - Ethernet Controller
U25 - DDR3L SDRAM
U26 - DDR3L SDRAM
U29 - DDR3L SDRAM
U30 - DDR3L SDRAM (ECC)
U31 - DDR3L SDRAM

![U29\nU31\nU30\nU26\nU1\nU25\nU9\nLEC_BT_Top_Comp_a](.lec-bt-50-1z166-1020-300-en/1e03e6bdc75cf378570be6f67a72427800b0f9c490c721ede58f80283fbc2308.jpg)

Figure 1-2: Component Locations (Top Side)

#

U24 - DDR3L SDRAM
U27 - DDR3L SDRAM
U28 - DDR3L SDRAM
U32 - DDR3L SDRAM
U48 - NAND Flash

![U32\nU28\nU27\nU24\nU48](.lec-bt-50-1z166-1020-300-en/2305518a7f4b2fc6e23fc09ec72e34c19149556dc3aa586b1b2a5b654c437373.jpg)

Figure 1-3: Component Locations (Bottom Side)
LEC\_BT\_Bottom\_Comp\_a

# 1.3 Connectors, Switches, and LEDs

Table 1-2 describes the connectors, switches, and LEDs shown in Figure 1-4.

Table 1-2: Module Connector Description

<table><tr><td>Connector#</td><td>Board Access</td><td>Description</td></tr><tr><td>GF1 – SMARC P-S</td><td>Top/Bottom</td><td>314-pin, MXM edge connector for routing Camera, Graphics, and I/O signals from the module to the baseboard</td></tr><tr><td>CN1</td><td>Top</td><td>40-pin, DB40 connector for debug card</td></tr><tr><td>SW1, SW2, SW3 – 4-pin dip switches for enabling/disabling CSI1 camera, 4L, Data 0-3 [default=ON/ON]</td><td>Top</td><td>SW1-SW3 CSI1 Settings:► One-lane CSI1 configuration (CSI1-D0) - Set SW1, SW2, and SW3 to ON/ON► Two-lane CSI1 configuration (CSI1-D0 and CSI1-D1) - Set SW1 to OFF/OFF and leave SW2 and SW3 ON/ON [factory default]► Three-lane CSI1 configuration (CSI1-D0, CSI1-D1, and CSI1-D2) - Set SW1, SW2 to OFF/OFF and leave SW3 ON/ON► Four-lane CSI1 configuration (CSI1-D0, CSI1-D1, CSI1-D2, and CSI1-D3) - Set SW1, SW2, and SW3 to OFF/OFF&lt;img src="images/39523ae3eceecea21706749d49addcf41755d5516f1e18474b168853043507d6.jpg"/&gt;SW2. SW3 Switch Default Settings&lt;img src="images/335a2c4709f1f4d9561813192916b3bef3162fd2ef283aa1d6dc6fbafd51e0e7.jpg"/&gt;LEC-BT_SW2_SW2_a</td></tr><tr><td>SW4</td><td>Top</td><td>4-pin dip switch for:Loading BIOS setup defaults at Boot Up (2=off [default], 3=on)Selecting 18/24 bit LVDS modes (1=18bit [default], 4=24bit)SW4 Switch Default Setting&lt;img src="images/bf8e970011837f0150ce7dd620faa70acc234d270a31b082533a8cbce5267c5a.jpg"/&gt;LEC-BT_SW2_c</td></tr><tr><td>SW5</td><td>Top</td><td>4-pin dip switch for:BIOS_SELECT (1=BIOS2 [blue LED blinks fast], 4=BIOS1 [default])WDT Disable (2=off [BMC switches to BIOS2 when BIOS1 not detected-default], 3=on [disables BIOS Detection Watchdog])&lt;img src="images/fc57c32f667530c1e9d7fd4ea2011514f9fb932e251e266293041e5a3992cee1.jpg"/&gt;</td></tr><tr><td>LED1</td><td>Top</td><td>Blue LED indicating system status activities for HW Reset, SW Reset, Power Up, Power Down, Reset Button, Power Button, and Exception Blink Codes</td></tr><tr><td>LED2</td><td>Top</td><td>Green LED for Power On</td></tr><tr><td>LED3</td><td>Top</td><td>Red LED for Watchdog Activity</td></tr></table>

CN1 - DB40 Debug

GF1A - SMARC Interface 1A SW1 - CSI1\_D1
GF1B - SMARC Interface 1B SW2 - CSI1\_D2
SW3 - CSI1\_D3
LED2 - Power On (Green) SW4 - BIOS Defaults and LVDS 18/24 Bit Select
LED3 - Watchdog Activity (Red) SW5 - BIOS 1-2 Select and Watchdog Disable

![SW4\nSW5\nSW3\nSW2\nSW1\nGF1A\nLED1\nLED3\nLED2\nCN1\n1\nB3\nN5\nN4\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS\nSLS](.lec-bt-50-1z166-1020-300-en/90da7ecf4a10834b66ae9f28ad17eecf71ac0039b734f6055a42bb4497731801.jpg)

Figure 1-4: Connector Locations (Top Side)

# 1.4 Specifications

# 1.4.1 Physical Specifications

Table 1-3 lists the physical dimensions of the module.

Table 1-3: Weight and Footprint Dimensions

<table><tr><td>Item</td><td>Dimension</td><td rowspan="6">Overall height is measured from the upper board surface to the top of the highest permanent component (CN1 connector) on the upper board surface. This measurement does not include the cooling solution, which can vary. The cooling solution will probably increase this dimension.</td></tr><tr><td>Weight</td><td>0.02 kg (0.05 lb)</td></tr><tr><td>Height (overall)</td><td>2.50 mm (0.098 inches)</td></tr><tr><td>Board thickness</td><td>1.27 mm (0.05 inches)</td></tr><tr><td>Width</td><td>80.00 mm (3.15 inches)</td></tr><tr><td>Length</td><td>82.00 mm (3.23 inches)</td></tr></table>

# 1.4.2 Mechanical Specifications

![Module Primary (Top) Side\n7X Ø 2.70\nTHROUGH\n7X Ø 6.00\nBOTH SIDE\nP1 P74 P75 P156\n0 4 80 76 41 78 82\n46\n12](.lec-bt-50-1z166-1020-300-en/f3df8c1b28f410fc3e564fe2deb5e162f3812e32fa36a17da668a3f2d843de52.jpg)

Figure 1-5: Mechanical Dimensions (Top Side)
NOTE: All dimensions are given in millimeters.

# 1.4.3 Electrical Specifications

Table 1-4 specifies the electrical characteristics of the module.

Table 1-4: Electrical Specifications

<table><tr><td>Parameter</td><td>Value</td></tr><tr><td>Voltage Input</td><td></td></tr><tr><td>Standard</td><td>► Fixed 5-Volt Supply (+4.75V DC min to +5.25V DC max)</td></tr><tr><td>RTC</td><td>► 3.0V, 2.0V to 3.3V (battery)</td></tr><tr><td>Power States</td><td>► C1-C6 processor power states► S0 (active), S4 (suspend-to-disk), S5 (soft-off and wake-on-LAN), and S5 ECO (wake on USB S3/S4, WOL S3/S4/S5) system power states</td></tr></table>

# 1.4.4 Power Specifications

Table 1-5 provides the power requirements for this module.

Table 1-5: Power Supply Requirements

<table><tr><td>Parameter</td><td>E3815 (5W) Characteristics</td><td>E3826 (7W) Characteristics</td><td>E3845 (10W) Characteristics</td></tr><tr><td>Input Type</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td></tr><tr><td>In-rush Voltage &amp; Current</td><td>0.55A (2.75W) @ 5V</td><td>0.65A (3.25W) @ 5V</td><td>0.85A (4.25W) @ 5V</td></tr><tr><td>Typical Idle Voltage &amp; Current</td><td>0.66A (3.30W) @ 5V</td><td>0.65A (3.25W) @ 5V</td><td>0.77A (3.85W) @ 5V</td></tr><tr><td>Intel TAT (Intel Thermal Analysis Tool) Voltage &amp; Current</td><td>1.18A (5.90W) @ 5V</td><td>1.60A (8.00W) @ 5V</td><td>2.52A (12.60W) @ 5V</td></tr></table>

Operating configurations:

 In-rush operating configuration - Typical under Windows 8.1
 Idle operating configuration - Typical under Windows 8.1
 Intel TAT (Thermal Analysis Tool) operating configuration - Typical under Windows 8.1

# 1.4.5 Environmental Specifications

Table 1-6 provides the most efficient operating and storage condition ranges required for this module.

Table 1-6: Environmental Requirements

<table><tr><td>Parameter</td><td>Conditions</td></tr><tr><td>Temperature</td><td></td></tr><tr><td>Standard</td><td>0° to +60°C (+32° to +140°F)</td></tr><tr><td>Extended</td><td>-40° to +85°C (-40° to +185°F)</td></tr><tr><td>Storage</td><td>-55° to +85°C (-67° to +185°F)</td></tr><tr><td>Humidity</td><td></td></tr><tr><td>Operating</td><td>5% to 90% relative humidity, non-condensing</td></tr><tr><td>Non-operating</td><td>5% to 95% relative humidity, non-condensing</td></tr></table>

# 1.4.6 Thermal/Cooling Requirements

The LEC-BT is designed to operate at its maximum CPU speed and requires a thermal solution. ADLINK offers a heat spreader as one part of the cooling solution.

CAUTION: The optional heat spreader plate requires another form of cooling, such as a fan. A heat spreader plate is not a complete thermal solution for the LEC-BT.

The overall system design must keep the ICs within their operating temperature specifications.

# 2 Hardware

# 2.1 CPU

The LEC-BT product family offers multiple versions of the Intel Atom E3800 Series CPU (SoC): the E3805 (Dual Core, headless), the E3815 (Single Core), the E3826 (Dual Core), and the E3845 (Quad Core). E3800 CPUs feature the Intel 64 Architecture and are manufactured based on Intel’s 22-nanometer technology. Refer to the CPU data sheet at:

http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-e3800-family-datasheet.pdf

# 2.2 Memory

The LEC-BT employs one channel of 64-bit DDR3L on-board memory. Nine SDRAM memory chips provide up to 8GB of low voltage non-ECC (and ECC in one of the nine chips), unbuffered system memory. Refer to the SDRAM data sheet at:

http://www.micron.com/parts/dram/ddr3-sdram/mt41k512m8rh-125

# 2.3 eMMC NAND Flash

The Intel E3800 SoC supports one single, 8-bit eMMC interface, which can used to support the onboard eMMC NAND flash device. If the onboard eMMC NAND flash device is being supported, the eMMC pins on the MXM SMARC connector are not supported.

A custom configuration can be provided if the eMMC flash device will not be used. In this case the eMMC signals will be routed to the SDMMC SMARC pins, available for use by the baseboard.

The module supports NAND chips with capacities from 4GB to 64GB. The default capacity is 8GB. Refer to the NAND Flash data sheet at:

http://www.micron.com/parts/nand-flash/managed-nand/mtfc8glvea-4m-it

and the SMARC specification at:

http://www.sget.org/standards/smarc.html

# 3 Interfaces

This section provides descriptions of the interfaces and signals within the SMARC P-S (Primary-Secondary) connector. Refer to the SMARC specification at:

http://www.sget.org/standards/smarc.html for definitions of the SMARC interfaces. The SMARC

P-S (Primary-Secondary) connector provides the following interfaces:

 LVDS
 HDMI
 Camera CSIO
 Audio
 PCIe
 Gb Ethernet
 USB 2.0
 USB 3.0
 SATA
 I2C
 SPI
 Serial
 I2S
 SD/SDIO
 eMMC
 GPIO
 AFB
 Debug

NOTE: ADLINK Technology Inc. only supports the features/options tested and listed in this manual. The main chips used in the LEC-BT may provide more features or options than are listed for the LEC-BT, but some of these features or options are not supported on the module and will not function as specified in the chip documentation.

# 3.1 18/24 Bit LVDS LCD

The LVDS interface is connected to the DDI0 interface of the SoC, while the translation is made by a DisplayPort™-to-LVDS converter. (Refer to the Realtek RTD2136R-CG, Display-Port-to-LVDS converter data sheet.)

NOTE: Backlight Enable, Display Enable, and PWMOUT are controlled from the BIOS setup.

# 3.2 HDMI (High-Definition Multimedia Interface)

The default setup defines the DDI1 port as HDMI and provides the following signals:

 1 Clock pair
 3 Data pairs
 Service signals

The HDMI interface is compliant with the HDMI 1.4 specification.

# 3.3 Camera (CSI)

The LEC-BT brings out two ports from the SoC for an MIPI-CSI 2.0 (serial) camera interface. Port 1 receives input through the CSI0 pins on the SMARC connector, supporting one clock lane and one data lane. Port 2 receives input through the CSI1 pins on the SMARC connector, supporting one clock lane and four data lanes. Each lane operates at up to 1GT/s and supports approximately 800 Mbit/s of actual pixels.

# 3.4 Audio (HDA)

The SoC provides an HDA controller, which communicates with internal or external CODECs over the Intel HDA serial link. HDA signals are brought out through the I2S2 pins on the SMARC connector and are multiplexed with LPE\_I2S audio signals. When HDA is active, LPE audio is disabled.

# 3.5 PCI Express (PCIe)

The CPU features four PCIe x1 ports, and the LEC-BT module uses three of them for the PCIe interface and one of them for the Gigabit Ethernet interface. The PCIe interface supports the PCIe Base Specification 2.0 with a maximum signal rate of 5 GT/s and can be configured to support PCIe edge cards or Express Cards.

# 3.6 Gigabit Ethernet

The on-board Intel I210IT Ethernet controller uses PCIe x1 (v2.1) bus signals from the CPU to enable 10T/100TX/1000T operation through integrated MAC, PHY, and SGMII/SerDes interfaces.

# 3.7 USB Ports

The USB interface originates from two host controllers on the SoC that provide four USB 2.0 ports and one USB 3.0 port.

# 3.7.1 USB2.0

Three of the four USB 2.0 ports use the USB 0-2 pins on the SMARC connector (0 = client; 1 = host; 2 = host.) The fourth USB 2.0 port is routed through the AFB-DIFF2 pins on the SMARC connector, which map to the USB\_DP/N [0] pins on the SoC.

# 3.7.2 USB 3.0

The USB 3.0 port uses the AFB\_DIFF 0-1 pins on the SMARC connector, which map to the USB3\_TX/RX pins on the SoC. See Table 3-3.

# 3.8 SATA

The SATA interface provides two ports, one through the SATA0 pins (P48, P49, P51, and P52) and one through the SATA1, AFB pins (S71, S72, S74, and S75) on the SMARC connector. The interface supports 1.5Gb/s and 3.0Gb/s.

# 3.9 I2C Bus

The LEC-BT provides four interfaces through the I2C bus for General Purpose, Power Management, Camera, and LCD video I2C signals with operating speeds up to 400kHz. All I2C interfaces have 1.8V pull ups with 2.2k resistors.

Table 3-1: I2C Signal Map

<table><tr><td>SMARC Connector I2C Pins</td><td>Map To:</td></tr><tr><td>S5 / S7</td><td>SOC: SIO_I2C1</td></tr><tr><td>S48 / S49</td><td>BMC: I2C_GP</td></tr><tr><td>P105 / P106</td><td>SoC: DDI1_DDC (HDMI)</td></tr><tr><td>P121 / P122</td><td>SoC: SMB (DATA / CLK)</td></tr><tr><td>S139 / S140</td><td>BMC or RTD2136 LVDS_DID</td></tr></table>

# 3.10 SPI

The LEC-BT implements the SPI1 controller from the SoC (the SPI0 controller is not connected). The SPI1 controller connects to the SMARC connector at pins P54, P56, P57, and P58 (pin P55 is not connected), which support two SPI Flash devices on the module for BIOS storage. Consequently, the SPI0 pins P43, P44, P45, P46 on the SMARC connector are not connected.

# 3.11 Serial (UART)

The LEC-BT provides three serial interfaces: Two ports are high-speed, 4-wire ports (with TX/ RX and RTS#/CTS#), and one port is 2-wire (with TX/RX only.)

# 3.12 I2S (Audio)

The LEC-BT supports an I2S audio interface as an alternate configuration to the default HD Audio interface. The I2S signals are supported through the I2S0 pins on the SMARC connector, and a programmable voltage regulator is used to switch between the I2S (1V8) and HDA (1V5). The default is HDA, and the change to I2S mode is be made through the LPE Audio BIOS setting. The I2S1 pins are not connected.

# 3.13 SD/SDIO Interface

Four parallel data lines comprise the SD/SDIO interface, supporting SD Card sockets.

# 3.14 eMMC Interface

The LEC-BT provides one 8-bit eMMC interface port, brought out from the SoC through the SDMMC pins on the SMARC connector. If the eMMC NAND chip on the module is being used, the SDMMC pins will not be available for the baseboard.

# 3.15 GPIO

The LEC-BT provides 12 GPIO signals from the PCA9535A GPIO expander on the module. The GPIO signals can be utilized for General Purpose IOs as well as camera reset, camera power, and HDA reset.

Table 3-1: GPIO Default Settings

<table><tr><td>SMARC Connector Pin</td><td>Default Function</td></tr><tr><td>GPIO0</td><td>CAM0_PWR#</td></tr><tr><td>GPIO1</td><td>CAM1_PWR#</td></tr><tr><td>GPIO2</td><td>CAM0_RST#</td></tr><tr><td>GPIO3</td><td>CAM1_RST#</td></tr><tr><td>GPIO4</td><td>HDA_RST#</td></tr><tr><td>GPIO5</td><td>GPIO</td></tr><tr><td>GPIO6</td><td>GPIO</td></tr><tr><td>GPIO7</td><td>GPIO</td></tr><tr><td>GPIO8</td><td>GPIO</td></tr><tr><td>GPIO9</td><td>GPIO</td></tr><tr><td>GPIO10</td><td>GPIO</td></tr><tr><td>GPIO11</td><td>GPIO</td></tr></table>

# 3.16 AFB (Alternate Function Block)

The module supports certain AFB pins that are dedicated for specific functions. Table 3-2 provides the map from the AFB signal on the module to its designated function signal on the SoC.

Table 3-2:AFB Pin Map to SoC

<table><tr><td>Pin</td><td>AFB Signal</td><td>SoC Signal</td></tr><tr><td>S17</td><td>AFB0_OUT</td><td>Intel SoC_PMC_SLP_S3#</td></tr><tr><td>S18</td><td>AFB1_OUT</td><td>Intel SoC_PMC_SLP_S4#</td></tr><tr><td>S19</td><td>AFB2_OUT</td><td>Intel SoC_PMC_SUS_STAT#</td></tr><tr><td>S20</td><td>AFB3_IN</td><td>Not connected</td></tr><tr><td>S21</td><td>AFB4_IN</td><td>Not connected</td></tr><tr><td>S22</td><td>AFB5_IN</td><td>Not connected</td></tr><tr><td>S23</td><td>AFB6_PTIO</td><td>EN_OC# for USB SS on AFB</td></tr><tr><td>S24</td><td>AFB7_PTIO</td><td>PCU_SMB_ALERT#</td></tr><tr><td>S55</td><td>AFB8_PTIO</td><td>Not connected</td></tr><tr><td>S56</td><td>AFB9_PTIO</td><td>Not connected</td></tr><tr><td>S62</td><td>AFB_DIFF0+</td><td>USB3.0_TX+</td></tr><tr><td>S63</td><td>AFB_DIFF0-</td><td>USB3.0_TX-</td></tr><tr><td>S65</td><td>AFB_DIFF1+</td><td>USB3.0_RX+</td></tr><tr><td>S66</td><td>AFB_DIFF1-</td><td>USB3.0_RX-</td></tr><tr><td>S68</td><td>AFB_DIFF2+</td><td>USB_DP [0]</td></tr><tr><td>S69</td><td>AFB_DIFF2-</td><td>USB_DN [0]</td></tr><tr><td>S71</td><td>AFB_DIFF3+</td><td>SATA_TXP [1]</td></tr><tr><td>S72</td><td>AFB_DIFF3-</td><td>SATA_TXN [1]</td></tr><tr><td>S74</td><td>AFB_DIFF4+</td><td>SATA_RXP [1]</td></tr><tr><td>S75</td><td>AFB_DIFF4-</td><td>SATA_RXN [1]</td></tr></table>

# 3.17 LPC Debug

A 40-pin, front flip, DB40 connector allows access to debug and update the BIOS, BMC, and OS code on the module. (Refer to “Debug (DB40)” on page 21.)

# 3.18 SMARC Interface Signals

Table 3-3 provides the pin signals for the SMARC P-S connector. Refer to the SMARC specification at http://www.sget.org/standards/smarc.html for definitions of the SMARC signals.

Table 3-3: SMARC P-S Connector (GF1) Signal Descriptions

<table><tr><td>Pin #</td><td>Primary (Top Side)</td><td>Pin #</td><td>Secondary (Bottom Side)</td></tr><tr><td></td><td></td><td>S1</td><td>Not connected</td></tr><tr><td>P1</td><td>Not connected</td><td>S2</td><td>Not connected</td></tr><tr><td>P2</td><td>GND</td><td>S3</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+ (CSI1 differential clock inputs.)</td><td>S4</td><td>Not connected</td></tr><tr><td>P4</td><td>CSI1_CK- (CSI1 differential clock inputs.)</td><td>S5</td><td>I2C_CAM_CK (Serial / Parallel camera support link - I2C clock)</td></tr><tr><td>P5</td><td>Not connected</td><td>S6</td><td>Not connected</td></tr><tr><td>P6</td><td>Not connected</td><td>S7</td><td>I2C_CAM_DAT (Serial / Parallel camera support link - I2C data)</td></tr><tr><td>P7</td><td>CSI1_D0+ (CSI1 differential data inputs.)</td><td>S8</td><td>CSI0_CK+ (CSI0 differential clock inputs.)</td></tr><tr><td>P8</td><td>CSI1_D0- (CSI1 differential data inputs.)</td><td>S9</td><td>CSI0_CK- (CSI0 differential clock inputs.)</td></tr><tr><td>P9</td><td>GND</td><td>S10</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_D1+ (CSI1 differential data inputs.)</td><td>S11</td><td>CSI0_D0+ (CSI0 differential data inputs.)</td></tr><tr><td>P11</td><td>CSI1_D1- (CSI1 differential data inputs.)</td><td>S12</td><td>CSI0_D0- (CSI0 differential data inputs.)</td></tr><tr><td>P12</td><td>GND</td><td>S13</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_D2+ (CSI1 differential data inputs.)</td><td>S14</td><td>Not connected</td></tr><tr><td>P14</td><td>CSI1_D2- (CSI1 differential data inputs.)</td><td>S15</td><td>Not connected</td></tr><tr><td>P15</td><td>GND</td><td>S16</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_D3+ (CSI1 differential data inputs.)</td><td>S17</td><td>AFB0_OUT (General purpose AFB output; maps to PMC_SLP_S3# on the SOC)</td></tr><tr><td>P17</td><td>CSI1_D3- (CSI1 differential data inputs.)</td><td>S18</td><td>AFB1_OUT (General purpose AFB output; maps to PMC_SLP_S4# on the SOC)</td></tr><tr><td>P18</td><td>GND</td><td>S19</td><td>AFB2_OUT (General purpose AFB output; maps to PMC_SUS_STAT# on the SOC)</td></tr><tr><td>P19</td><td>GBE_MDI3- (Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S20</td><td>Not connected</td></tr><tr><td>P20</td><td>GBE_MDI3+(Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S21</td><td>Not connected</td></tr><tr><td>P21</td><td>GBE_LINK100# (Link Speed Indication LED for 100Mbps; able to sink 24mA or more carrier LED current)</td><td>S22</td><td>Not connected</td></tr><tr><td>P22</td><td>GBE_LINK1000# (Link Speed Indication LED for 1000Mbps; able to sink 24mA or more carrier LED current)</td><td>S23</td><td>AFB6_PTIO (EN_OC# for USB SS)</td></tr><tr><td>P23</td><td>GBE_MDI2- (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S24</td><td>AFB7_PTIO (PCU_SMB_ALERT#)</td></tr><tr><td>P24</td><td>GBE_MDI2+ (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S25</td><td>GND</td></tr><tr><td>P25</td><td>GBE_LINK_ACT# (Link / Activity Indication LED Driven low on Link [10, 100 or 1000 mbps] Blinks on Activity; able to sink 24mA or more Carrier LED current)</td><td>S26</td><td>SDMMC_D0 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P26</td><td>GBE_MDI1- (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S27</td><td>SDMMC_D1 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P27</td><td>GBE_MDI1+ (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S28</td><td>SDMMC_D2 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P28</td><td>GBE_CTREF(Center-Tap reference voltage for GBE0 Carrier board Ethernet magnetic [if required by the Module GBE PHY])</td><td>S29</td><td>SDMMC_D3 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P29</td><td>GBE0_MDI0- (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S30</td><td>SDMMC_D4 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P30</td><td>GBE0_MDI0+ (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S31</td><td>SDMMC_D5 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P31</td><td>Not connected</td><td>S32</td><td>SDMMC_D6 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P32</td><td>GND</td><td>S33</td><td>SDMMC_D7 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P33</td><td>SDIO_WP (SDIO card Write Protect; 10K pull-up to 3.3V)</td><td>S34</td><td>GND</td></tr><tr><td>P34</td><td>SDIO_CMD (SDIO card Command line)</td><td>S35</td><td>SDMMC_CK (clock)</td></tr><tr><td>P35</td><td>SDIO_CD# (SDIO Card Detect; 10K pull-up to 3.3V)</td><td>S36</td><td>SDMMC_CMD (command line)</td></tr><tr><td>P36</td><td>SDIO_CK (SDIO card Clock)</td><td>S37</td><td>SDMMC_RST# (Reset signal to eMMC device)</td></tr><tr><td>P37</td><td>SDIO_PWR_EN (SDIO card Power Enable)</td><td>S38</td><td>Not connected</td></tr><tr><td>P38</td><td>GND</td><td>S39</td><td>I2S0_LRCK (Left &amp; Right audio synchronization clock)</td></tr><tr><td>P39</td><td>SDIO_D0 (SDIO card 4-bit data path)</td><td>S40</td><td>I2S0_SDOUT (Digital audio output)</td></tr><tr><td>P40</td><td>SDIO_D1 (SDIO card 4-bit data path)</td><td>S41</td><td>I2S0_SDIN (Digital audio input)</td></tr><tr><td>P41</td><td>SDIO_D2 (SDIO card 4-bit data path)</td><td>S42</td><td>I2S0_CK (Digital audio clock)</td></tr><tr><td>P42</td><td>SDIO_D3 (SDIO card 4-bit data path)</td><td>S43</td><td>Not connected</td></tr><tr><td>P43</td><td>Not connected</td><td>S44</td><td>Not connected</td></tr><tr><td>P44</td><td>Not connected</td><td>S45</td><td>Not connected</td></tr><tr><td>P45</td><td>Not connected</td><td>S46</td><td>Not connected</td></tr><tr><td>P46</td><td>Not connected</td><td>S47</td><td>GND</td></tr><tr><td>P47</td><td>GND</td><td>S48</td><td>I2C_GP_CK (I2C General Purpose clock signal)</td></tr><tr><td>P48</td><td>SATA0_TX+ (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S49</td><td>I2C_GP_DAT I2C (General Purpose data signal)</td></tr><tr><td>P49</td><td>SATA0_TX- (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S50</td><td>I2S2_LRCK (Left &amp; Right audio synchronization clock)</td></tr><tr><td>P50</td><td>GND</td><td>S51</td><td>I2S2_SDOUT (Digital audio output)</td></tr><tr><td>P51</td><td>SATA0_RX+ (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S52</td><td>I2S2_SDIN (Digital audio input)</td></tr><tr><td>P52</td><td>SATA0_RX- (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S53</td><td>I2S2_CK (Digital audio clock)</td></tr><tr><td>P53</td><td>GND</td><td>S54</td><td>SATA_ACT# (Active low SATA activity indicator If implemented, able to sink 24mA or more Carrier LED current)</td></tr><tr><td>P54</td><td>SPI1_CS0# (SPI1 Master Chip Select 0 output)</td><td>S55</td><td>Not connected</td></tr><tr><td>P55</td><td>Not connected</td><td>S56</td><td>Not connected</td></tr><tr><td>P56</td><td>SPI1_CK (SPI1 Master Clock output)</td><td>S57</td><td>Not connected</td></tr><tr><td>P57</td><td>SPI1_DIN (SPI1 Master Data input [input to CPU, output from SPI device])</td><td>S58</td><td>Not connected</td></tr><tr><td>P58</td><td>SPI1_DO (SPI1 Master Data output [output from CPU, input to SPI device])</td><td>S59</td><td>Not connected</td></tr><tr><td>P59</td><td>GND</td><td>S60</td><td>Not connected</td></tr><tr><td>P60</td><td>USB0+ (Differential USB0 data pair)</td><td>S61</td><td>GND</td></tr><tr><td>P61</td><td>USB0- (Differential USB0 data pair)</td><td>S62</td><td>AFB_DIFF0+ (maps to USB3_TX_P on the SOC)</td></tr><tr><td>P62</td><td>USB0_EN_OC# (Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S63</td><td>AFB_DIFF0- (maps to USB3_TX_N on the SOC)</td></tr><tr><td>P63</td><td>Not connected</td><td>S64</td><td>GND</td></tr><tr><td>P64</td><td>Not connected</td><td>S65</td><td>AFB_DIFF1+ (maps to USB3_RX_P on the SOC)</td></tr><tr><td>P65</td><td>USB1+ (Differential USB1 data pair)</td><td>S66</td><td>AFB_DIFF1- (maps to USB3_RX_N on the SOC)</td></tr><tr><td>P66</td><td>USB1- (Differential USB1 data pair)</td><td>S67</td><td>GND</td></tr><tr><td>P67</td><td>USB1_EN_OC# (Pulled low by Module OD driver to disable USB1 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S68</td><td>AFB_DIFF2+ (maps to USB_D0_P on the SOC)</td></tr><tr><td>P68</td><td>GND</td><td>S69</td><td>AFB_DIFF2- (maps to USB_D0_N on the SOC)</td></tr><tr><td>P69</td><td>USB2+ (Differential USB2 data pair)</td><td>S70</td><td>GND</td></tr><tr><td>P70</td><td>USB2- (Differential USB2 data pair)</td><td>S71</td><td>AFB_DIFF3+ (maps to SATA_TX1_P on the SOC)</td></tr><tr><td>P71</td><td>USB2_EN_OC# (Pulled low by Module OD driver to disable USB2 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up shall be present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S72</td><td>AFB_DIFF3- (maps to SATA_TX1_N on the SOC)</td></tr><tr><td>P72</td><td>PCIE_C_PRSNT# (PCIe Port C present input. Pulled up or terminated on Module)</td><td>S73</td><td>GND</td></tr><tr><td>P73</td><td>PCIE_B_PRSNT# (PCIe Port B present input. Pulled up or terminated on Module)</td><td>S74</td><td>AFB_DIFF4+ (maps to SATA_RX1_P on the SOC)</td></tr><tr><td>P74</td><td>PCIE_A_PRSNT# (PCIe Port A present input. Pulled up or terminated on Module)</td><td>S75</td><td>AFB_DIFF4- (maps to SATA_RX1_N on the SOC)</td></tr><tr><td></td><td>Key</td><td></td><td>Key</td></tr><tr><td>P75</td><td>PCIE_A_RST# (PCIe Port A reset output)</td><td>S76</td><td>PCIE_B_RST# (PCIe Port B reset output, active low)</td></tr><tr><td>P76</td><td>PCIE_C_CREQ# (PCIe Port C clock request input. Pulled up or terminated on Module)</td><td>S77</td><td>PCIE_C_RST# (PCIe Port A reset output, active low)</td></tr><tr><td>P77</td><td>PCIE_B_CREQ# (PCIe Port B clock request input. Pulled up or terminated on Module)</td><td>S78</td><td>PCIE_C_RX+ (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P78</td><td>PCIE_A_CREQ# (PCIe Port A clock request input. Pulled up or terminated on Module)</td><td>S79</td><td>PCIE_C_RX- (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P79</td><td>GND</td><td>S80</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+ (Differential PCIe Link C reference clock output. DC coupled)</td><td>S81</td><td>PCIE_C_TX+ (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P81</td><td>PCIE_C_REFCK- (Differential PCIe Link C reference clock output. DC coupled)</td><td>S82</td><td>PCIE_C_TX- (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P82</td><td>GND</td><td>S83</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+ (Differential PCIe Link A reference clock output. DC coupled)</td><td>S84</td><td>PCIE_B_REFCK+ (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P84</td><td>PCIE_A_REFCK- (Differential PCIe Link A reference clock output. DC coupled)</td><td>S85</td><td>PCIE_B_REFCK- (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P85</td><td>GND</td><td>S86</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+ (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S87</td><td>PCIE_B_RX+ (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P87</td><td>PCIE_A_RX- (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S88</td><td>PCIE_B_RX- (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P88</td><td>GND</td><td>S89</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+ (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>S90</td><td>PCIE_B_TX+ (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P90</td><td>PCIE_A_TX- (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>P91</td><td>PCIE_B_TX- (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P91</td><td>GND</td><td>S92</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+ (TMDS / HDMI data 2 differential pair)</td><td>S93</td><td>Not connected</td></tr><tr><td>P93</td><td>HDMI_D2- (TMDS / HDMI data 2 differential pair)</td><td>S94</td><td>Not connected</td></tr><tr><td>P94</td><td>GND</td><td>S95</td><td>Not connected</td></tr><tr><td>P95</td><td>HDMI_D1+ (TMDS / HDMI data 1 differential pair)</td><td>S96</td><td>Not connected</td></tr><tr><td>P96</td><td>HDMI_D1- (TMDS / HDMI data 1 differential pair)</td><td>S97</td><td>Not connected</td></tr><tr><td>P97</td><td>GND</td><td>S98</td><td>Not connected</td></tr><tr><td>P98</td><td>HDMI_D0+ (TMDS / HDMI data 0 differential pair)</td><td>S99</td><td>Not connected</td></tr><tr><td>P99</td><td>HDMI_D0- (TMDS / HDMI data 0 differential pair)</td><td>S100</td><td>Not connected</td></tr><tr><td>P100</td><td>GND</td><td>S101</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+ (TMDS / HDMI clock output differential pair)</td><td>S102</td><td>Not connected</td></tr><tr><td>P102</td><td>HDMI_CK- (TMDS / HDMI clock output differential pair)</td><td>S103</td><td>Not connected</td></tr><tr><td>P103</td><td>GND</td><td>S104</td><td>Not connected</td></tr><tr><td>P104</td><td>HDMI_HPD (HDMI Hot Plug Detect input)</td><td>S105</td><td>Not connected</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK (I2C clock line dedicated to HDMI)</td><td>S106</td><td>Not connected</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT (I2C data line dedicated to HDMI)</td><td>S107</td><td>Not connected</td></tr><tr><td>P107</td><td>HDMI_CEC (HDMI Consumer Electronics Control, 1 - wire peripheral control interface)</td><td>S108</td><td>Not connected</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR# [default] (Camera 0 Power Enable, active low output)</td><td>S109</td><td>Not connected</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR# [default] (Camera 1 Power Enable, active low output)</td><td>S110</td><td>GND</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST# [default] (Camera 0 Reset, active low output)</td><td>S111</td><td>Not connected</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST# [default] (Camera 1 Reset, active low output)</td><td>S112</td><td>Not connected</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST# [default] (HD Audio Reset, active low output)</td><td>S113</td><td>Not connected</td></tr><tr><td>P113</td><td>GPIO5 (General Purpose IO)</td><td>S114</td><td>Not connected</td></tr><tr><td>P114</td><td>GPIO6 (General Purpose IO)</td><td>S115</td><td>Not connected</td></tr><tr><td>P115</td><td>GPIO7 (General Purpose IO)</td><td>S116</td><td>Not connected</td></tr><tr><td>P116</td><td>GPIO8 (General Purpose IO)</td><td>S117</td><td>Not connected</td></tr><tr><td>P117</td><td>GPIO9 (General Purpose IO)</td><td>S118</td><td>Not connected</td></tr><tr><td>P118</td><td>GPIO10 (General Purpose IO)</td><td>S119</td><td>GND</td></tr><tr><td>P119</td><td>GPIO11 (General Purpose IO)</td><td>S120</td><td>Not connected</td></tr><tr><td>P120</td><td>GND</td><td>P121</td><td>Not connected</td></tr><tr><td>P121</td><td>I2C_PM_CK (Power management I2C bus clock)</td><td>S122</td><td>Not connected</td></tr><tr><td>P122</td><td>I2C_PM_DAT(Power management I2C bus data)</td><td>S123</td><td>Not connected</td></tr><tr><td>P123</td><td>BOOT_SEL0# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S124</td><td>GND</td></tr><tr><td>P124</td><td>BOOT_SEL1# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S125</td><td>LVDS0+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P125</td><td>BOOT_SEL2# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S126</td><td>LVDS0- (LVDS LCD data channel differential pair)</td></tr><tr><td>P126</td><td>RESET_OUT# (General purpose reset output to Carrier board.)</td><td>S127</td><td>LCD_BKLT_EN (High enables panel backlight)</td></tr><tr><td>P127</td><td>RESET_IN# (Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S128</td><td>LVDS1+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P128</td><td>POWER_BTN# (Power-button input from Carrier board. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the Module Pulled up on Module. Driven by OD part on Carrier.)</td><td>S129</td><td>LVDS1- (LVDS LCD data channel differential pair)</td></tr><tr><td>P129</td><td>SER0_TX (Asynchronous serial port data out)</td><td>S130</td><td>GND</td></tr><tr><td>P130</td><td>SER0_RX (Asynchronous serial port data in)</td><td>S131</td><td>LVDS2+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P131</td><td>SER0_RTS# (Request to Send handshake line for SER0)</td><td>S132</td><td>LVDS2- (LVDS LCD data channel differential pair)</td></tr><tr><td>P132</td><td>SER0_CTS# (Clear to Send handshake line for SER0)</td><td>S133</td><td>LCD_VDD_EN (High enables panel VDD)</td></tr><tr><td>P133</td><td>GND</td><td>S134</td><td>LVDS_CK+ (LVDS LCD differential clock pair)</td></tr><tr><td>P134</td><td>SER1_TX (Asynchronous serial port data out)</td><td>S135</td><td>LVDS_CK- (LVDS LCD differential clock pair)</td></tr><tr><td>P135</td><td>SER1_RX (Asynchronous serial port data in)</td><td>S136</td><td>GND</td></tr><tr><td>P136</td><td>SER2_TX (Asynchronous serial port data out)</td><td>S137</td><td>LVDS3+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P137</td><td>SER2_RX (Asynchronous serial port data in)</td><td>S138</td><td>LVDS3- (LVDS LCD data channel differential pair)</td></tr><tr><td>P138</td><td>SER2_RTS# (Request to Send handshake line for SER2)</td><td>S139</td><td>I2C_LCD_CK (I2C clock – to read LCD display EDID EEPROMs)</td></tr><tr><td>P139</td><td>SER2_CTS# (Clear to Send handshake line for SER2)</td><td>S140</td><td>I2C_LCD_DAT (I2C data – to read LCD display EDID EEPROMs)</td></tr><tr><td>P140</td><td>Not connected</td><td>S141</td><td>LCD_BKLT_PWM (Display backlight PWM control)</td></tr><tr><td>P141</td><td>Not connected</td><td>S142</td><td>Not connected</td></tr><tr><td>P142</td><td>GND</td><td>S143</td><td>GND</td></tr><tr><td>P143</td><td>Not connected</td><td>S144</td><td>RSVD / EDP_HPD (Reserved for future eDP Hot Plug Detect pin)</td></tr><tr><td>P144</td><td>Not connected</td><td>S145</td><td>WDT_TIME_OUT# (Watchdog Timer Output)</td></tr><tr><td>P145</td><td>Not connected</td><td>S146</td><td>PCIE_WAKE (PCIe wake up interrupt to host – common to PCIe; links A, B, C – pulled up or terminated on Module)</td></tr><tr><td>P146</td><td>Not connected</td><td>S147</td><td>VDD_RTC (Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.SeeSection 7.3RTC Voltage Railof the SMARC specification for an important safety note on the implementation of lithium backup batteries.)</td></tr><tr><td>P147</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S148</td><td>LID# (Lid open/close indication to Module.Low indicates lid closure, which systemmayuse to initiate a sleep state. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the ModulePulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P148</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S149</td><td>SLEEP# (Sleep indicator from Carrier board; sourced from user Sleep button or Carrier logic. Carrier to float the line in inactive state. Active low, level sensitive; de-bounced on the Module.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P149</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S150</td><td>VIN_PWR_BAD# (Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits)is notenabled while this signal is held low by the Carrier.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P150</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S151</td><td>CHARGING# (Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P151</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S152</td><td>CHARGER_PRSNT# (Held low by Carrier if DC input for battery charger is present. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P152</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S153</td><td>CARRIER_STBY# (The Module drives this signal low when the system is in a standby power state)</td></tr><tr><td>P153</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S154</td><td>CARRIER_PWR_ON (Carrier board circuits [apart from power management and power path circuits]arepowered up until the Module asserts the CARRIER_PWR_ON signal)</td></tr><tr><td>P154</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S155</td><td>FORCE_RECOV# (Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery function, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P155</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S156</td><td>BATLOW# (Battery low indication to Module. Carrier to float the line in inactive state. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P156</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S157</td><td>TEST# (Held low by Carrier to invoke Module vendor specific test function(s). Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td></td><td></td><td>S158</td><td>GND</td></tr></table>

# 3.19 Debug (DB40)

Table 3-4 lists the pin signals of the CN1 connector, which provides 40 pins, 1 row, consecutive sequence with 0.02" (0.50mm) pitch.

Table 3-4: Debug Interface Signals (CN1)
NOTE: The gray table cells denote ground.

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>RESVD</td></tr><tr><td>2</td><td>SMC_STATUS</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>SEL_BIOS</td></tr><tr><td>5</td><td>POSTWDT_DIS#</td></tr><tr><td>6</td><td>SUS_S5#</td></tr><tr><td>7</td><td>SUS_S4#</td></tr><tr><td>8</td><td>SUS_S3#</td></tr><tr><td>9</td><td>CB_PWROK</td></tr><tr><td>10</td><td>CB_RESET#</td></tr><tr><td>11</td><td>SYS_RESET#</td></tr><tr><td>12</td><td>PWRBTN#</td></tr><tr><td>13</td><td>SMC_OCD0B</td></tr><tr><td>14</td><td>SMC_OCD0A</td></tr><tr><td>15</td><td>SMC_CLK</td></tr><tr><td>16</td><td>SMC_DATA</td></tr><tr><td>17</td><td>SMC_RESET_IN#</td></tr><tr><td>18</td><td>SMC_FLMD0</td></tr><tr><td>19</td><td>SMC_RXD6</td></tr><tr><td>20</td><td>SMC_TXD6</td></tr><tr><td>21</td><td>GND3</td></tr><tr><td>22</td><td>3V3_DUAL</td></tr><tr><td>23</td><td>3V3_SMC1</td></tr><tr><td>24</td><td>LPC_AD0</td></tr><tr><td>25</td><td>LPC_AD1</td></tr><tr><td>26</td><td>LPC_AD2</td></tr><tr><td>27</td><td>LPC_AD3</td></tr><tr><td>28</td><td>LPC_FRAME#</td></tr><tr><td>29</td><td>CLK33_LPC</td></tr><tr><td>30</td><td>RST#</td></tr><tr><td>31</td><td>BIOS_DIS0</td></tr><tr><td>32</td><td>GND2</td></tr><tr><td>33</td><td>LPC_3V3</td></tr><tr><td>34</td><td>SPI_BIOS_CLK</td></tr><tr><td>35</td><td>SPI_BIOS_MOSI</td></tr><tr><td>36</td><td>SPI_BIOS_MISO</td></tr><tr><td>37</td><td>SPI_BIOS_CS1#</td></tr><tr><td>38</td><td>SPI_BIOS_CS0#</td></tr><tr><td>39</td><td>GND1</td></tr><tr><td>40</td><td>VCC_SPI_IN</td></tr></table>

# 4 Utilities

# 4.1 BIOS

The LEC-BT features an AMI BIOS. The default settings provide a “ready to run” system, even without a BIOS setup backup battery.

The BIOS is located in flash memory and can be easily updated with software under DOS.

All setup changes of the BIOS are stored in the CMOS RAM.

The soldered battery will provide power to store that information for over two years without board activation.

# 4.1.1 Configuring the BIOS

 Pressing &lt;DEL&gt; during power up starts the BIOS setup utility.
 Pressing &lt;F11&gt; during power up starts the boot menu.
 Pressing &lt;END&gt; during power up returns settings to default.

# 4.1.2 Main screen of the BIOS

The main screen of the BIOS SETUP UTILITY provides an overview of the BIOS version, the clock speed, installed memory, memory speed, date and time, and other system information. The date and time can be configured by the user.

<table><tr><td colspan="2">BIOS Information
BIOS Vendor American Megatrends
Core Version 5.009
Compliancy UEFI 2.3; PI 1.2
Project Version LECBT 1.12 x64
Build Date and Time 2015/08/27 09:37:57</td><td rowspan="3">System Management</td></tr><tr><td colspan="2">CPU Configuration
Microcode Patch 903
BayTrail SoC D0 Stepping</td></tr><tr><td colspan="2">Memory Information
Total Memory 4096 MB (DDR3L)</td></tr><tr><td colspan="2">GOP Information
Intel(R) GOP Driver [7.2.1013]</td><td rowspan="3">←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">TXE Information
Sec RC Version 00.05.00.00
TXE FW Version 01.01.04.1148</td></tr><tr><td colspan="2">System Management
System Date [Fri 2015/03/20]
System Time [18:42:49]</td></tr><tr><td colspan="3">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr><tr><td colspan="3">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.</td></tr><tr><td colspan="3">Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>Core Version</td><td>5.009</td><td rowspan="18">Set the Time. Use Tab to switch between Time elements.</td></tr><tr><td>Compliancy</td><td>UEFI 2.3; PI 1.2</td></tr><tr><td>Project Version</td><td>LECBT 1.12 x64</td></tr><tr><td>Build Date and Time</td><td>2015/08/27 09:37:57</td></tr><tr><td>CPU Configuration</td><td></td></tr><tr><td>Microcode Patch</td><td>903</td></tr><tr><td>BayTrail SoC</td><td>DO Stepping</td></tr><tr><td>Memory Information</td><td></td></tr><tr><td>Total Memory</td><td>4096 MB (DDR3L)</td></tr><tr><td>GOP Information</td><td></td></tr><tr><td>Intel(R) GOP Driver</td><td>[7.2.1013]</td></tr><tr><td>TXE Information</td><td></td></tr><tr><td>Sec RC Version</td><td>00.05.00.00</td></tr><tr><td>TXE FW Version</td><td>01.01.04.1148</td></tr><tr><td>System Management</td><td></td></tr><tr><td>System Date</td><td>[Fri 2015/03/20]</td></tr><tr><td>System Time</td><td>[18:43:16]</td></tr><tr><td>Access Level</td><td>Administrator</td></tr></table>

# 4.1.3 Advanced Settings screen

The main screen of “Advanced Settings” provides configuration settings for CPU, Graphics, SATA, USB, SDIO, Network, Audio, PCI/PCIe, Devices, ACPI, Serial, Thermal, Security, Miscellaneous, and SIO.

![The image displays a yellow triangular warning sign with a black border. Centered inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION' is written in black, uppercase letters. The background is white.](.lec-bt-50-1z166-1020-300-en/b1eb09677f53f148cbad744f0fd6c00e861a9f9b189892198774bb9d41a33231.jpg)

Inappropriate values for any of the following advanced settings below may cause the system to malfunction.

<table><tr><td colspan="2">Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td rowspan="2">CPU ConfigurationGraphics ConfigurationSATA ConfigurationUSB ConfigurationSDIO ConfigurationNetwork ConfigurationAudio ConfigurationPCI/PCIe ConfigurationBaytrail Features ConfigurationACPI SettingsSerial Port Console RedirectionThermal ConfigurationSecurity ConfigurationMiscellaneousIntel(R) I210 Gigabit Network Connection - 00:20:9D:21...</td><td>Configure Gigabit Ethernet device parameters</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Advanced > CPU

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>CPU ConfigurationSocket 0 CPU InformationCPU Thermal ConfigurationPPM ConfigurationCPU Speed 64-bit Limit CPUID Maximum Execute Disable Bit Intel Virtualization Technology Power Technology</td><td>1918 MHz Supported [Disabled] [Enabled] [Enabled] [Energy Efficient]</td></tr><tr><td></td><td></td></tr></table>

# Advanced > Graphics

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td rowspan="2">Graphics ConfigurationIntel IGD ConfigurationGraphics Power Management ControlVBIOS - LCD ControlLVDS Backlight Mode [BMC Mode]</td><td>Config Intel IGD Settings.</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

# Advanced > SATA

<table><tr><td colspan="2">Optio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>IDE ConfigurationSerial-ATA (SATA) [Enabled]SATA Test Mode [Disabled]SATA Speed Support [Gen2]SATA ODD Port [No ODD]SATA Mode [AHCI Mode]Serial-ATA Port 0 [Enabled]SATA Port0 HotPlug [Disabled]Serial-ATA Port 1 [Enabled]SATA Port1 HotPlug [Disabled]SATA Port0Not PresentSATA Port1Not Present</td><td>Enable / Disable Serial ATA←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

<table><tr><td colspan="2">Optio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>USB ConfigurationUSB Module Version 8.11.01USB Devices:1 Drive, 1 Keyboard, 1 Mouse, 3 HubsLegacy USB Support [Enabled]XHCI Hand-off [Enabled]EHCI Hand-off [Disabled]USB Mass Storage Driver Support [Enabled]USB hardware delays and time-outs:USB transfer time-out [20 sec]Device reset time-out [20 sec]Device power-up delay [Auto]USB Host Controller ConfigurationUSB Host Controller ConfigurationMass Storage Devices:U1-JetFlashTranscend 8GB 8.07 [Auto]</td><td>Enables Legacy USB support.AUTO option disables legacysupport if no USB devices areconnected. DISABLE option willkeep USB devices availableonly for EFI applications.→: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

# Advanced > SDIO

<table><tr><td colspan="2">Optio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td rowspan="2">SDIO ConfigurationSDIO Access Mode [Auto]Mass Storage Devices:Sdio Device 1 Details:Bus 0 Dev 17 Func 0MMC - MMC08G [Auto]</td><td>Auto Option: Access SD device in DMA mode if controller supports it,otherwise in PIO mode.DMA Option: Access SD device in DMA mode.PIO Option: Access SD device in PIO mode.</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

# Advanced > Audio

<table><tr><td rowspan="2">Audio ConfigurationLPE Audio Support [Disabled]Audio Controller [Enabled]Azalia VCi Enable [Enabled]Azalia Docking Support Enable [Disabled]Azalia PME Enable [Enabled]Azalia HDMI Codec [Enabled]</td><td>Select LPE Audio ACPI mode or PCI mode</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

# Advanced > PCI-PCIe

<table><tr><td rowspan="2">PCI/PCIe Configuration▶ PCIe Chipset Settings▶ PCI Subsystem Settings</td><td>PCI Express Configuration settings</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

# Advanced > ACPI

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td rowspan="2">ACPI SettingsEnable ACPI Auto Configuration [Disabled]Enable Hibernation [Enabled]ACPI Sleep State [S3 (Suspend to RAM)]Lock Legacy Resources [Disabled]</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

# Advanced > Serial

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td rowspan="2">COM1Console Redirection [Enabled]► Console Redirection Settings</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

# Advanced > Thermal

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td rowspan="2">Thermal Configuration ParametersCritical Trip Point [Disabled]Passive Trip Point [Disabled]</td><td>This value controls the temperature of the ACPI critical Trip Point in which the OS will shut the system off.</td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

# Advanced > Security

<table><tr><td colspan="2">Main</td></tr><tr><td rowspan="2">Intel(R) TXE ConfigurationTXE [Enabled]TXE HMRFPO [Disabled]TXE Firmware Update [Enabled]TXE EOP Message [Enabled]TXE Unconfiguration PerformIntel(R) Anti-Theft Technology ConfigurationIntel(R) AT [Disabled]Intel(R) AT Platform PBA [Enabled]Intel(R) AT Suspend Mode [Disabled]</td><td></td></tr><tr><td>←: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

# Advanced > Miscellaneous

<table><tr><td colspan="2">Optio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>Miscellaneous</td><td></td></tr><tr><td>LVDS I2C Master [Dp2LVDS Controller] Onboard Ethernet [Enabled]</td><td></td></tr><tr><td>Smart Battery Support [Enabled] Select Smart Battery Controller [LTC1760]</td><td></td></tr><tr><td>High Precision Timer [Enabled]</td><td></td></tr><tr><td>Global SMI Lock [Enabled] PCI Express Dynamic Clock Gating [Disabled]</td><td></td></tr><tr><td>Max TOLUD [Dynamic]</td><td> $\rightarrow   :$  Select Screen  $\uparrow   \downarrow$  : Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F9: Optimized Defaults F10: Save &amp; Exit ESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends， Inc.

# Advanced > SDIO

<table><tr><td colspan="2">Optio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
Advanced</td></tr><tr><td>SDIO Configuration
SDIO Access Mode [Auto]
Mass Storage Devices:
Sdio Device 1 Details:
Bus 0 Dev 17 Func 0
MMC - MMC08G [Auto]</td><td>Auto Option: Access SD device in DMA mode if controller supports it, otherwise in PIO mode.DMA Option: Access SD device in DMA mode.PIO Option: Access SD device in PIO mode.</td></tr><tr><td></td><td>←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

# 4.1.4 Security screen

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td rowspan="5">Password Description
If ONLY the Administrator&#x27;s password is set, then this only limits access to Setup and is only asked for when entering Setup.
If ONLY the User&#x27;s password is set, then this is a power on password and must be entered to boot or enter Setup. In Setup the User will have Administrator rights.
The password length must be in the following range:
Minimum length 3
Maximum length 20
Administrator Password
User Password
► Secure Boot menu</td><td rowspan="5">Set Administrator Password
←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr></tr><tr></tr><tr></tr><tr></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

# 4.1.5 Boot screen

If more than one drive is attached to the LEC-BT, you can select from the first “Boot Configuration” screen the boot order in which the drives are scanned for a bootable OS image.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.</td></tr><tr><td colspan="2">Main</td></tr><tr><td>Compatibility Support Module Configuration</td><td>Enable/Disable CSM Support.</td></tr><tr><td>CSM Support [Enabled]</td><td></td></tr><tr><td>CSM16 Module Version 07.75</td><td></td></tr><tr><td>GateA20 Active [Upon Request]</td><td></td></tr><tr><td>Option ROM Messages [Force BIOS]</td><td></td></tr><tr><td>INT19 Trap Response [Immediate]</td><td></td></tr><tr><td>Boot option filter [UEFI and Legacy]</td><td></td></tr><tr><td>Option ROM execution</td><td></td></tr><tr><td>Network [UEFI only]</td><td rowspan="4">←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Storage [UEFI only]</td></tr><tr><td>Video [Legacy first]</td></tr><tr><td>Other PCI devices [UEFI only]</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

# 4.1.6 Save & Exit screen

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td rowspan="2">Save Changes and ExitDiscard Changes and ExitSave Changes and ResetDiscard Changes and ResetSave OptionsSave ChangesDiscard ChangesRestore DefaultsSave as User DefaultsRestore User DefaultsBoot OverrideUEFI: U1-JetFlashTranscend 8GB 8.07MMC - MMC08GUEFI: Built-in EFI ShellU1-JetFlashTranscend 8GB 8.07Launch EFI Shell from filesystem deviceReset System with ME disable ModeMEUD000</td><td>Exit system setup after saving the changes.</td></tr><tr><td>---: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF9: Optimized DefaultsF10: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.

# 4.2 SEMA functions

Under the management of the BMC chip (Board Management Controller), the SEMA utility (Smart Embedded Management Agent) provides system control and failure protection—counting, monitoring, and measuring hardware and software events, from which the SoC can trigger corrective commands. The optional SEMA Cloud utility not only controls local events on the module but system client events on the Internet of Things (IoT.) Refer to the following bullets for a list of SEMA functions.

 Total operating hours counter Counts the time the module has been run in minutes.
 On-time minutes counter Counts the seconds since last system start.
 Temperature monitoring of CPU and Board temperature Minimum and maximum temperature values of CPU and board are stored in flash.
 Power monitor Reads the current drawn by the board and reports the nominal operating voltage.
 Power cycles counter
 Boot counter Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
 Watchdog Timer Set / Reset / Disable Watchdog Timer.
 System Restart Cause Power loss / Watchdog / External Reset.
 Flash area 1kB Flash area for customer data
 Protected Flash area 128 Bytes for Keys, ID's, etc. can be stored in a write- and clear-protectable region.
 Board Identify Vendor / Board / Serial number

The SEMA Tools are available for Windows and Linux. SEMA functionality can also be used in applications. Refer to the SEMA software manual and technical manual on the ADLINK web site for more information.

# 4.2.1 Board Specific SEMA functions

# Voltages

The BMC of the LEC-BT implements a Voltage Monitor and samples several Onboard Voltages. The Voltages can be read by calling the SEMA function, “Get Voltages”. The function returns a 16-bit value divided in Hi-Byte (MSB) and Lo-Byte (LSB).

Table 4-1: BMC Voltage Monitor Values

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>---</td><td>---</td></tr><tr><td>1</td><td>+V1.0S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>2</td><td>+V1.2S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>3</td><td>+V1.8S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>4</td><td>+V3.3S</td><td>(MSB&lt;&lt;8 + LSB) * 1.100 * 3.3 / 1024</td></tr><tr><td>5</td><td>+V1.5S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>6</td><td>+V5.0A</td><td>(MSB&lt;&lt;8 + LSB) * 1.833 * 3.3 / 1024</td></tr><tr><td>7</td><td>(MAINCURRENT)</td><td>Use Main Current Function</td></tr></table>

# Main Current

The BMC of the LEC-BT implements a Current Monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in Hi-Byte (MSB) and Lo-Byte (LSB). These four values represent the last four currents drawn by the board. The values are sampled every 250ms. The order of the four values is NOT in relationship to time. The access to the BMC may increase the drawn current of the whole system. In this case, you still have three samples without the influence of the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) * 8. 0 6 \mathrm{mA}
$$

# TS#-Events

TS# is activated by a temperature sensor when a device reaches its critical temperature and released when the device is back in its normal temperature range. This counter gives the user information about temperature or cooling issues. This counter is cleared when the system is removed from power. The LEC-BT only monitors the board temperature and does not support TS#-Events.

# Exception Blink Codes

In the case of an error, the BMC shows a blink code on the STATUS-LED (LED1). This error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash storage and is cleared when the power is removed. Therefore, the “Clear Exception Code”-Command is not supported.

Table 4-2: Exception Blink Codes

&lt;table&gt;<tr><td>Exception Blink Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S3</td></tr><tr><td>5</td><td>RESET_FAIL</td></tr><tr><td>6</td><td></td></tr><tr><td>7</td><td>POWER_FAIL</td></tr><tr><td>8</td><td>LOW_VIN</td></tr><tr><td>9</td><td>NO_PWRGD_ATX</td></tr><tr><td>10</td><td>NO_PWRGD_1V0S</td></tr><tr><td>11</td><td>NO_PWRGD_1V2S</td></tr><tr><td>13</td><td>NO_PWRGD_1V8S</td></tr><tr><td>14</td><td>NO_PWRGD_3V3S</td></tr><tr><td>15</td><td>NO_PWRGD_1V5S</td></tr></table>

# BMC Flags

The BMC Flags register returns the last detected exception code since power up.

# 4.3 Watchdog Timer

The LEC-BT features three separate Watchdog Timers. One of them is integrated in the SoC and two are provided by the BMC (managed by the SEMA).

The SoC Watchdog can be configured in the BIOS or by programming the Watchdog registers. If this function is used by user application, the application has to provide all logging functionality if desired.

The BMC Watchdog activations are caused by under voltage protection. The Watchdog LED flashes after restart but only if the power supply reaches 4.2V.

# 4.4 Temperature Sensors

The LEC-BT supports two temperature sensor functions. One is offered from the SoC and one from a dedicated chip (Texas Instruments LM73) on the board.

The SoC temperature sensors can be configured by programming the appropriate SoC registers. Refer to the Thermal Management chapter in the Intel Atom E3800 data sheet for more information. The on-board LM73 temperature sensor is managed by the BMC and is configured through the SEMA utility.

# 4.5 Programming Examples

Programming examples can be provided based on a Linux operating system, upon request.

# Appendix A Technical Support

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in Table A-1 below. Requests for support through Ask an Expert are given the highest priorities, and usually will be addressed within one working day.

 ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the ADLINK web site at http://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK”, unique to you with access to exclusive services and account information.

 Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to the My Question area where you can check status, update your request, and access other features.
 Download Service – This service is also free and available 24 hours a day at http://www.adlinktech.com. For certain downloads such as technical documents and software, you must register online before you can log in to this service.

Table A-1: Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://www.adlinktech.com/AAE/</td></tr><tr><td>Web Site</td><td>http://www.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Zhonghe DistrictNew Taipei City 235, Taiwan新北市中和區建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech ParkPudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.comADLINK Technology BeijingAddress: 北京市海淀区上地东路1号盈创动力大厦E座801室(100085)Rm. 801, Power Creative E, No. 1 Shang Di East Rd.Beijing, 100085 ChinaTel: +86-10-5885-8666Fax: +86-10-5885-8626Email: market@adlinktech.com</td></tr><tr><td rowspan="6"></td><td>ADLINK Technology ShenzhenAddress: 深圳市南山区科技园南区高新南七道数字技术园A1栋2楼C区(518057)2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7High-Tech Industrial Park S., Shenzhen, 518054 ChinaTel: +86-755-2643-4858Fax: +86-755-2664-6353Email: market@adlinktech.com</td></tr><tr><td>LiPPERT ADLINK Technology GmbHAddress: Hans-Thoma-Strasse 11D-68163 Mannheim, GermanyTel: +49-621-43214-0Fax: +49-621 43214-30Email: emea@adlinktech.com</td></tr><tr><td>PENTA ADLINK Technology GmbHUlrichsbergerstrasse 1794469 Deggendorf, GermanyTel: +49 (0) 991 290 94 - 10Fax: +49 (0) 991 290 94 - 29Email: emea@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (French Liaison Office)Address: 6 allée de Londres, Immeuble Ceylan91940 Les Ulis, FranceTel: +33 (0) 1 60 12 35 66Fax: +33 (0) 1 60 12 35 66Email: france@adlinktech.com</td></tr><tr><td>ADLINK Technology Japan CorporationAddress: 〒101-0045 東京都千代田区神田鍛冶町3-7-4神田374 ビル4FKANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,Chiyoda-ku, Tokyo 101-0045, JapanTel: +81-3-4455-3722Fax: +81-3-5209-6013Email: japan@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Korean Liaison Office)Address: 경기도 성남시 분당구 수내로46번길4경동빌딩2층(수내동4-4번지)(우)463-8252F, Kyungdong B/D, 4 Sunae-ro 46 beon-gilBundang-gu, Seongnam-si, Gyeonggi-do, Korea, 13595Toll Free +82-80-800-0585Tel +82-31-786-0585Fax +82-31-786-0583Email: korea@adlinktech.com</td></tr><tr><td rowspan="4"></td><td>ADLINK Technology Singapore Pte. Ltd.Address: 84 Genting Lane #07-02A, Cityneon Design CentreSingapore 349584Tel: +65-6844-2261Fax: +65-6844-2263Email: singapore@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)Address: #50-56, First Floor, Spearhead TowersMargosa Main Road (between 16th/17th Cross)Malleswaram, Bangalore - 560 055, IndiaTel: +91-80-65605817, +91-80-42246107Fax: +91-80-23464606Email: india@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Israeli Liaison Office)Address: 27 Maskit St., Corex BuildingPO Box 12777Herzliya 4673300, IsraelTel: +972-54-632-5251Fax: +972-77-208-0230Email: israel@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (UK Liaison Office)Tel: +44 774 010 59 65Email: UK@adlinktech.com</td></tr></table>
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