# LEC-BTS

# Technical Reference

Low Energy Computer On Module with

Intel® Atom™ E3800 Series and N2807 Celeron® Processors

![Close-up of a green printed circuit board with various electronic components and gold contacts (no readable text or symbols)](.lec-bts-50-1z173-1020-21/5f036fdf08fc5a5fb04d8f139fec61a2c7fc45209b42d2ab0d1e13d6fcf867a0.jpg)

![Against a solid black background is a stylized, four-pointed cross shape with rounded edges. The object features a horizontal color gradient, shifting from a pale yellow-green on the left to a vibrant lime green on the right. In the center of the cross is a cutout in the shape of a white square.](.lec-bts-50-1z173-1020-21/8a178aa9343d4da0a2a0acc6d069b6b5c6323cbef1041b17554262d6520918ad.jpg)

SMARC

Manual Rev.: 2.1

Revision Date: May 3, 2018

Part Number: 50-1Z173-1020

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK's Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Date</td><td>Description of Change(s)</td></tr><tr><td>1.00</td><td>Mar/16</td><td>Initial Release</td></tr><tr><td>2.00</td><td>Jul/16</td><td>Added Chapter 4, Utilities; updated SMARC signals, in Table 3-2 on page 14; added Electrical Specifications section to Chapter 1</td></tr><tr><td>2.1</td><td>May/18</td><td>Removed heatsink as an option from section 1.4.6</td></tr></table>

# © Copyright 2016, 2017, 2018 ADLINK Technology, Incorporated

www.adlinktech.com

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines, no text or labels present](.lec-bts-50-1z173-1020-21/4bc7196121ec5da5b1115a81970446b4a11032c8a901c1221d103a5f8dc59212.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin with two crossed lines (no text or symbols)](.lec-bts-50-1z173-1020-21/31775ac4bd1fa11776112370be0d208283a3d0255f64e7f1b949cfa257c72bfc.jpg)

![The image displays a black outline of a square containing the universal recycling symbol (three chasing arrows forming a triangle) in the center. Below the square frame, the text 'Li-ion' appears in bold, black letters.](.lec-bts-50-1z173-1020-21/b7c082bbe0981224319af6e46e555219e9d308bff20decba7aa4bb706b2a1900.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.lec-bts-50-1z173-1020-21/a1d80517632b09b5cb28e0d137da8793308baeb010cb574de3cbfac9d0b28aac.jpg)

![The image displays a vertical graphic consisting of two parts. At the top is a black square logo containing a white geometric design formed by four thick, interlocking arrows pointing in different directions (up, down, left, and right). Below the logo is a line of black Chinese text that reads '廢電池請回收'.](.lec-bts-50-1z173-1020-21/b1ee55d0794b266528fab62d1791f6dbb514f8fc45ce4bfb550c2d2f1d58fa35.jpg)

# California Proposition 65 Warning

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![The image displays a vertical icon consisting of a white document sheet with a folded top-right corner. Inside the document are faint horizontal lines and a large red checkmark in the center. Below the document graphic is the text 'NOTE:' in black, capital letters.](.lec-bts-50-1z173-1020-21/2b39d605234b42eaa81cfbb8092da872cc7aca20b00aa69daf0826c80b205bf9.jpg)

This information adds clarity or specifics to text and illustrations.

![The image displays a standard safety warning sign consisting of a yellow triangle with a black border. Inside the triangle is a large black exclamation mark. Below the triangle, the word 'CAUTION:' is printed in black, uppercase letters.](.lec-bts-50-1z173-1020-21/1afcbdecffdfbc286b6539ab4ba0513b3c43744453120bf9280b695164dac59f.jpg)

This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard warning sign featuring a red triangle with rounded corners containing a white exclamation point in the center. Below the triangle, the word 'WARNING:' is printed in black, uppercase letters.](.lec-bts-50-1z173-1020-21/4dfab275d2bf4595b668d904dc45f4ffa7b55875a0e9eee8fc78265667a1eb0f.jpg)

This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Important Safety Instructions

For user safety, please read and follow all Instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
▶ Keep this manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);
▶ Make sure to use recommended voltage and power source settings;
▶ Always install and operate equipment near an easily accessible electrical socket-outlet;
▷ Secure the power cord (do not place any object on/over the power cord);
▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
▷ If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Table of Contents

# Preface ...... ii

# 1 Overview .... 1

1.1 Block Diagram ....1
1.2 Major Components (ICs) 2
1.3 Connectors, Switches, and LEDs .... 3
1.4 Specifications 6

1.4.1 Physical Specifications 6
1.4.2 Mechanical Specifications 6
1.4.3 Electrical Specifications 7
1.4.4 Power Specifications 7
1.4.5 Environmental Specifications 7
1.4.6 Thermal/Cooling Requirements 8

# 2 Hardware 9

2.1 CPU 9
2.2 Memory 9
2.3 I210 LAN Controller 9
2.4 SMBus Slave Addresses 9
2.5 Getting Started 9

# 3 Interfaces 11

3.1 18/24 Bit LVDS LCD 11
3.2 HDMI (High-Definition Multimedia Interface) 11
3.3 Camera CSI 12
3.4 Audio (HDA) 12
3.5 PCI Express (PCIe) 12
3.6 Gigabit Ethernet 12
3.7 USB Ports 12

3.7.1 USB2.0 12
3.7.2 USB 3.0 12

3.8 SATA 12
3.9 I2C Bus 12
3.10 SPI 12
3.11 Serial (UART) 13
3.12 I2S 13
3.13 SD/SDIO Interface 13
3.14 eMMC Interface 13
3.15 GPIO 13
3.16 LPC Debug 13
3.17 SMARC Interface Signals 14
3.18 Debug (DB40) 22

# 4 Utilities 23

4.1 BIOS 23

4.1.1 Starting the BIOS Setup Utility 23
4.1.2 Main Menu 24
4.1.3 Advanced Menu 29
4.1.4 Security Menu 54
4.1.5 Boot 55
4.1.6 Save & Exit 58

4.2 SEMA functions 59

4.2.1 Board Specific SEMA functions 59

4.3 Watchdog Timer 61
4.4 Temperature Sensors 61
4.5 Programming Examples 61

# Appendix A Technical Support 63

# 1 Overview

This manual presents a general overview of the LEC-BTS. After reviewing this document you should understand the following perspectives of the LEC-BTS.

▶ Feature Overview
▶ Hardware Functions
▶ Interface Signal Definitions
▶ Utility Definitions
▶ Contact Information

NOTE: Refer to http://www.sget.org/standards/smarc.html for SMARC specifications. Please refer to BSP readme documents in the Quick Drive for BSP installation instructions.

# 1.1 Block Diagram

Figure 1-1 represents the component functions of the module.
![The diagram illustrates the connectivity of the **Intel® Bay Trail-I SoC** to various peripherals and external components.\n\n**Labeled Blocks:**\n*   314-pin Golden finger\n*   LVDS RTD2136\n*   GPIO PCA9535A\n*   LAN i210IT\n*   BMC HWM\n*   SPI BIOS\n*   Intel® Bay Trail-I SoC\n*   DDR3L Memory down 2/4 GB\n*   PMIC IDTP9145\n*   Debug Connector for DB40\n\n**Connections:**\n*   **314-pin Golden finger** connects to **LVDS RTD2136** via **LVDS 18/24bit Single channel**.\n*   **LVDS RTD2136** connects to the SoC via **DDI0**.\n*   **314-pin Golden finger** connects directly to the SoC via:\n    *   **DDI1 (HDMI)**\n    *   **Audio (HDA or I2S)**\n    *   **2x I2C (LCD/GP)**\n    *   **PCIe x1, PCIe port 1,2,3**\n    *   **MMC (8bit)**\n    *   **Camera Support (CSI 4L/1L)**\n    *   **2x Serial (incl. RTS/CTS) + PCU-UART**\n    *   **USB2.0 port 0: client or host**\n    *   **3x USB2.0 host**\n    *   **1x USB3.0 host on AFB**\n    *   **2x SATA**\n    *   **SDIO x4**\n    *   **Power Management**\n*   **314-pin Golden finger** connects to **GPIO PCA9535A** via **12x GPIO (5x reserved for CSI)**.\n*   **GPIO PCA9535A** connects to the SoC via **SMBus** (SoC to GPIO) and **INT** (GPIO to SoC).\n*   **314-pin Golden finger** connects to **LAN i210IT** via **GbE**.\n*   **LAN i210IT** connects to the SoC via **PCIe x1**.\n*   **314-pin Golden finger** connects to **BMC HWM** via **BOOT Select** and **2x I2C**.\n*   **BMC HWM** connects to the SoC via **SMB**.\n*   **BMC HWM** connects to **SPI BIOS** (vertical link).\n*   **SPI BIOS** connects to the SoC via **SPI** and **1x SPI**.\n*   **SoC** connects to **DDR3L Memory down 2/4 GB** via **DDR3L 1066/1333MHz**.\n*   **SoC** connects to **PMIC IDTP9145** (bidirectional, unlabeled).\n*   **SoC** connects to **Debug Connector for DB40** via **LPC**.](.lec-bts-50-1z173-1020-21/5794dea09ab857dbb8cab98c7bca76415b6397976b07e14688f5d956029fe154.jpg)

Figure 1-1: Functional Block Diagram

# 1.2 Major Components (ICs)

Table 1-1 lists the major integrated circuits on the LEC-BTS, including a brief description of each IC. Figures 1-2 and 1-3 show the locations of the major ICs.

Table 1-1: Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U1)</td><td>Intel</td><td>E3805 (dual core, 3W, headless, 1.33GHz)E3815 (single core, 5W, 1.46GHz)E3826 (dual core, 7W, 1.46GHz)E3845 (quad core, 10W, 1.91GHz)N2807 (dual core, 4.3W, 1.58Ghz)</td><td>Atom, 22nm SoC (System on Chip) with Intel 64 ArchitectureCeleron, 22nm SoC (System on Chip) with Intel 64 Architecture</td><td>Integrates Processor Core, Graphics and Memory Controller Hub, and I/O Hub</td></tr><tr><td>Ethernet Controller (U9 [bottom])</td><td>Intel</td><td>WGI210IT SLIXT</td><td>Single-port Gigabit Ethernet controller</td><td>Integrates GbE MAC, PHY, and SGMII/SerDes to enable 10T/100TX/1000T Ethernet signals using the PCIe x1 bus</td></tr><tr><td>DDR3L SDRAM (U24 [bottom], U25, U26 [top], U27 [bottom])</td><td>Micron</td><td>MT41K256M16HA-125</td><td>On-board DDR3L, 1.35V, 4Gb, 32Mx16x8, non-ECC, un-buffered System Memory</td><td>Provides high-speed data transfer</td></tr></table>

Key:

U1 - CPU

U25 - DDR3L SDRAM

U26 - DDR3L SDRAM

![U1\nU26\nU25\nLEC_BTS_Top_Comp_a\nP74\nP156](.lec-bts-50-1z173-1020-21/9b68ee8058c21a6f0aa9a5e88a5a26b3f598b6ca5d601cdf0302c7ee562aa020.jpg)

Figure 1-2: Component Locations (Top Side)

![Key:\nU9 - GbE Controller\nU24 - DDR3L SDRAM\nU27 - DDR3L SDRAM\nS158\nS75\nLEC_BTS_Bot_Comp_a](.lec-bts-50-1z173-1020-21/f1ccc935d2b7d1eaa02b4e0cba121c862957139337ca4c47ff0508d0abd9115b.jpg)

Figure 1-3: Component Locations (Bottom Side)

# 1.3 Connectors, Switches, and LEDs

Table 1-2 describes the connectors, switches, and LEDs shown in Figure 1-4.

Table 1-2: Module Connector Description

<table><tr><td>Reference</td><td>Board Access</td><td>Description</td></tr><tr><td>GF1 – SMARC P-S</td><td>Top/Bottom</td><td>314-pin, MXM edge connector for routing camera, graphics, and I/O signals from the module to the baseboard.</td></tr><tr><td>CN1</td><td>Top</td><td>40-pin, DB40 connector for debug card</td></tr><tr><td>SW1</td><td>Top</td><td>4-pin dip switch for selecting CSI1 camera, 4L, Data1 configuration [default=off] &lt;img src="images/6f8df9ced70e8d45b37307517a36fa452fdaf1279959f17de4dd5c717604fcd0.jpg"/&gt;</td></tr><tr><td>SW2</td><td>Top</td><td>4-pin dip switch for selecting CSI1 camera, 4L, Data2 configuration [default=on] &lt;img src="images/3e358f62c64e265f850c3aa9f975019af5036efebe1fabd878d0c3956b05fd6c.jpg"/&gt;</td></tr><tr><td>SW3</td><td>Top</td><td>4-pin dip switch for selecting CSI1 camera, 4L, Data3 configuration [default=on] &lt;img src="images/e61979d9d33ddc96d082d20809d585ac7b88b9c92503b6b9732c08d350bfc3ea.jpg"/&gt;</td></tr><tr><td colspan="3">SW1, SW2, SW3 Configurations:Camera with 1 MIPI-CSI lane = SW1-SW3 switches all set to ONCamera with 2 MIPI-CSI lanes = SW1 (both OFF); SW2 (both ON); SW3 (both ON)Camera with 3 MIPI-CSI lanes = SW1 (both OFF); SW2 (both OFF); SW3 (both ON)Camera with 4 MIPI-CSI lanes = SW1-SW3 switches all set to OFF</td></tr><tr><td>SW4</td><td>Top</td><td>4-pin dip switch for selecting LVDS color depth (18bit or 24bit) and loading BIOS setup defaults at Boot Up:1 = LVDS 18bit [default]4 = LVDS 24bit2 = BIOS setup defaults off [default]3 = BIOS setup defaults on&lt;img src="images/7fdef2f4100472faa5fce1fe046d8cf99b49970b30541a567fe50711b0b58a7b.jpg"/&gt;</td></tr><tr><td>SW5</td><td>Top</td><td>4-pin dip switch for BIOS_SELECT:1 = BIOS 2 [blue LED blinks fast]4 = BIOS 1 and WDT Disable [default]2 = BMC switches to BIOS 2 when BIOS 1 not detected [default]3 = Disables BIOS Detection Watchdog&lt;img src="images/5ea6a31bea62f6c21400883ce48049b51b164230768d4c8d61da19eee072bbaa.jpg"/&gt;</td></tr><tr><td>LED1</td><td>Top</td><td>Blue LED indicating system status activities for HW Reset, SW Reset, Power Up, Power Down, Reset Button, and Power Button</td></tr><tr><td>LED2</td><td>Top</td><td>Green LED for Power On</td></tr><tr><td>LED3</td><td>Top</td><td>Red LED for Watchdog Activity</td></tr></table>

Key:
CN1 - DB40 Bebug
GF1 - SMARC
LED1 - System Status
LED2 - Power ON
SW1 - CSI 1 Camera
SW2 - CSI 2 Camera
SW3 - CSI 3 Camera
SW4 - BIOS Defaults
SW5 - BIOS1-2 Select

![CN1\nSW1 SW2 SW3 LED4 LED5 SW5 SW4\nGF1A P74 GF1B P156\nLEC_BTS_Top_Comp_a](.lec-bts-50-1z173-1020-21/7453078e5d341983b247809e8ccd79726c5ba34f6e19f49cd81f6b56d9ddfda2.jpg)

Figure 1-4: Connector Locations (Top Side)

# 1.4 Specifications

# 1.4.1 Physical Specifications

Table 1-3 lists the physical dimensions of the module.

Table 1-3: Weight and Footprint Dimensions

<table><tr><td>Item</td><td>Dimension</td><td rowspan="6">Overall height is measured from the upper board surface to the top of the highest permanent component (CN1 connector) on the upper board surface. This measurement does not include the cooling solution, which can vary. The cooling solution will probably increase this dimension.</td></tr><tr><td>Weight</td><td>0.02 kg (0.05 lb)</td></tr><tr><td>Height (overall)</td><td>2.50 mm (0.098 inches)</td></tr><tr><td>Board thickness</td><td>1.27 mm (0.05 inches)</td></tr><tr><td>Width</td><td>50.00 mm (1.97 inches)</td></tr><tr><td>Length</td><td>82.00 mm (3.23 inches)</td></tr></table>

# 1.4.2 Mechanical Specifications

![Module Primary (Top) Side\n78 82\n4X Ø6\n4X Ø2.70 THROUGH\n12\n7.70\n6.20\n3.30\n3.10\n0\n1.25 PIN P1\n74 PINS\nP1 - P74\nP74 A\n82 PINS\nP75 - P156\n39\n12\n46\n50](.lec-bts-50-1z173-1020-21/b62557921eaee245de3ddb04cd8fc490f85e73c71fb047310fbd22a6cec09ac7.jpg)

Figure 1-5: Mechanical Dimensions (Top Side)
NOTE: All dimensions are given in millimeters.

# 1.4.3 Electrical Specifications

Table 1-4 specifies the electrical characteristics of the module.

Table 1-4: Electrical Specifications

<table><tr><td>Parameter</td><td>Value</td></tr><tr><td>Voltage Input</td><td></td></tr><tr><td>Standard</td><td>► Fixed 5-Volt Supply (+4.75V DC min to +5.25V DC max)</td></tr><tr><td>RTC</td><td>► 3.0V, 2.0V to 3.3V (battery)</td></tr><tr><td>Power States</td><td>► C1-C6 processor power states► S0 (active), S1 (sleep), S3 (save to RAM), S4 (suspend-to-disk), S5 (soft-off and wake-on-LAN), and S5 ECO (wake on USB S3/S4, WOL S3/S4/S5) system power states</td></tr></table>

# 1.4.4 Power Specifications

Table 1-5 provides the power requirements for this module.

Table 1-5: Power Supply Requirements

<table><tr><td>Parameter</td><td>E3815 (5W) Characteristics</td><td>E3826 (7W) Characteristics</td><td>E3845 (10W) Characteristics</td></tr><tr><td>Input Type</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td></tr><tr><td>In-rush Voltage &amp; Current</td><td>0.55A (2.75W) @ 5V</td><td>0.65A (3.25W) @ 5V</td><td>0.85A (4.25W) @ 5V</td></tr><tr><td>Typical Idle Voltage &amp; Current</td><td>0.66A (3.30W) @ 5V</td><td>0.65A (3.25W) @ 5V</td><td>0.77A (3.85W) @ 5V</td></tr><tr><td>BIT* Voltage &amp; Current</td><td>1.18A (5.90W) @ 5V</td><td>1.60A (8.00W) @ 5V</td><td>2.52A (12.60W) @ 5V</td></tr></table>

Operating configurations:

▶ In-rush operating configuration - Typical under Windows 8.1
▶ Idle operating configuration - Typical under Windows 8.1
Intel TAT (Thermal Analysis Tool) operating configuration - Typical under Windows 8.1

# 1.4.5 Environmental Specifications

Table 1-6 provides the most efficient operating and storage condition ranges required for this module.

Table 1-6: Environmental Requirements

<table><tr><td>Parameter</td><td>Conditions</td></tr><tr><td>Temperature</td><td></td></tr><tr><td>Standard</td><td>0° to +60°C (+32° to +140°F)</td></tr><tr><td>Extended</td><td>-40° to +85°C (-40° to +185°F)</td></tr><tr><td>Storage</td><td>-55° to +85°C (-67° to +185°F)</td></tr><tr><td>Humidity</td><td></td></tr><tr><td>Operating</td><td>5% to 90% relative humidity, non-condensing</td></tr><tr><td>Non-operating</td><td>5% to 95% relative humidity, non-condensing</td></tr></table>

# 1.4.6 Thermal/Cooling Requirements

The LEC-BTS is designed to operate at its maximum CPU speeds and requires a thermal solution to cool the SoC. ADLINK offers a heat spreader (separate order number) for cooling. This facilitates future module upgrades without the need to re-design the custom heatsink.

![The image displays a yellow triangular warning sign containing a black exclamation point in the center. Directly below the triangle is a black rectangular bar with the white text 'CAUTION:'.](.lec-bts-50-1z173-1020-21/70f77a38425a10b77d145d39b377ddd6061f6da3b08a62f77abf57d2be588f6e.jpg)

The optional heat spreader plate requires another form of cooling, such as a fan. A heat spreader plate is not a complete thermal solution for the LEC-BTS.

# 2 Hardware

# 2.1 CPU

The LEC-BTS product family offers three versions of the Intel Atom E3800 Series CPU: the E3805 (dual core), the E3815 (Single Core), the E3826 (Dual Core), the E3845 (Quad Core), and the N2807 (Celeron Dual Core). E3800 CPUs feature the Intel 64 Architecture and are manufactured based on Intel's 22-nanometer technology. Refer to the CPU data sheet at the Intel web site.

# 2.2 Memory

The LEC-BTS employs one channel of 64-bit DDR3L on-board memory. Four SDRAM memory chips provide up to 16Gb of low voltage non-ECC, unbuffered system memory. Refer to the SDRAM data sheet at the Micron web site.

# 2.3 I210 LAN Controller

The Intel I210 provides a single-port controller that supports GbE functionality using the high-speed PCIe standard, v2.1 (2.5GT/s). The I210 features an integrated PHY, which enables 1000BASE-T implementations such as rack-mounted or pedestal servers in add-on NIC or LAN-on-Motherboard (LOM) designs. Other implementations include blade servers such as LOMs or mezzanine cards as well as embedded applications such as switch add-on cards and network appliances. Refer to the Intel I210 Ethernet Controller data sheet at the Intel web site.

# 2.4 SMBus Slave Addresses

Figure 2-1 lists the corresponding slave addresses of the devices on the SMBus

Table 2-1: SMBus Slave Addresses

<table><tr><td>Address (HEX)</td><td>Function</td><td>Device</td></tr><tr><td>(40)</td><td>GPIO</td><td>PCA9535A</td></tr><tr><td>(50)</td><td>BMC/SEMA</td><td>BMC</td></tr><tr><td>(6A)</td><td>DP to LVDS</td><td>RTD2136R</td></tr><tr><td>(A0)</td><td>DDR3L channel A</td><td>DDR3L memory</td></tr><tr><td>(92)</td><td>Thermal Sensor</td><td>LM73</td></tr></table>

# 2.5 Getting Started

Mount the LEC-BTS to the carrier as illustrated in Figure 2-1, which provides a profile view of the module mounted to the carrier with dimensions.

![5.7mm Min\n1.5mm Min\nTOP Side\nComponent 3mm Max\nModule PCB 1.2mm\nBOT Side\nComponent 1.3mm Max\nCarrier Connector\nCarrier PCB 1.6mm Typ](.lec-bts-50-1z173-1020-21/568d9e151744f5dd2974849c0d532fb331233d984cad6b6bb4072829923cd27d.jpg)

Figure 2-1: SMARC module mounting dimensions (profile)

![The image displays a digital icon featuring a white document or piece of paper with faint horizontal lines representing text. A large, bold red checkmark is centered on the paper. Below the graphic, the text 'NOTE:' appears in black, capital letters.](.lec-bts-50-1z173-1020-21/4445dac328fc15bf2a7f958e72e2e2ca942e1460611df3b78ff9b888517515bf.jpg)

ADLINK strongly recommends plastic spacers instead of metal spacers for mounting the board. Metal spacers create the possibilities of short circuits with the components located around the mounting holes, which can ruin the board.

![A standard warning sign featuring a yellow triangle with a black border and a black exclamation point in the center. Below the triangle, the word 'CAUTION:' is printed in bold, black capital letters.](.lec-bts-50-1z173-1020-21/0966c23e58280555ed4f72f16983b3281b2d5f880c5b44b5380f25530a9d316b.jpg)

Be sure to observe the EMC security measures. Make sure you are always at the same potential as the module.

![The image shows a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the triangle, the text 'CAUTION:' is written in black capital letters.](.lec-bts-50-1z173-1020-21/070dde76f606fb6db639c78321c85bdeaa1d71c513a1bb0c9e7045ef5473297f.jpg)

Never connect or disconnect peripherals like HDDs while the power supply is connected and switched on.

Connect a USB keyboard or mouse to the carrier. Use the SATA cable to connect a hard disk. Make sure that the pins match their counterparts correctly and are not twisted. If you plan to use additional peripherals, connect them to the appropriate headers or connectors on the carrier.

Connect a power supply to the power connector on the carrier and switch on the power.

![The image displays a white document icon with a folded top-right corner, overlaid with a large, red checkmark. Below the document graphic, the text 'NOTE:' appears in black capital letters, followed by three small black dots arranged horizontally.](.lec-bts-50-1z173-1020-21/5ba82b9251e24253be66deb998dffc074d269391e6ffb6277bb50aac22e451f5.jpg)

Observe the minimum voltage values for the standard peripherals mentioned. For additional peripherals, make sure enough power is available. The system will not work if there is not enough supply current for all your devices.

The display shows the BIOS messages. If you want to change the standard BIOS settings, press the &lt;DEL&gt; key to enter the BIOS setup menus. See Chapter 4 for setup details.

If you need to load the BIOS default values, they can be automatically loaded at boot time.

The LEC-BTS boots from CD drives, USB sticks, hard disks, or $\mu$ SD-Cards. Provided that any of these is connected and contains a valid operating system image, the display then shows the boot screen of your operating system.

The LEC-BTS needs adequate cooling measures depending on the desired operating temperature range. Using the board without cooling could permanently damage the board.

# 3 Interfaces

This section provides descriptions of the interfaces and signals within the SMARC P-S (Primary-Secondary) connector. Refer to the SMARC specification at: http://www.sget.org/standards/smarc.html for definitions of the SMARC interfaces. The SMARC P-S (Primary-Secondary) connector provides the following interfaces:

▶ LVDS
▶ HDMI
▶ Camera CSIO
▶ Audio
▶ PCIe
▶ Gb Ethernet
▶ USB 2.0
▶ USB 3.0
▶ SATA
▶ I2C
▶ SPI
▶ Serial
▶ I2S
▶ SD/SDIO
▶ eMMC
▶ GPIO
▶ SMARC
▶ Debug

![The image displays a graphic icon of a white document with a folded top-right corner and faint horizontal lines representing text. Superimposed over the document is a large, bold red checkmark. Below the document graphic, the text 'NOTE:' is written in black capital letters.](.lec-bts-50-1z173-1020-21/ee483c36fde2baa9683bc58615be9c929ad09d373e2512279d97b22ddb88f769.jpg)

ADLINK Technology Inc. only supports the features/options tested and listed in this manual. The main chips used in the LEC-BTS may provide more features or options than are listed for the LEC-BTS, but some of these features or options are not supported on the module and will not function as specified in the chip documentation.

# 3.1 18/24 Bit LVDS LCD

The LVDS interface is connected to the DDI0 interface of the SoC, while the translation is made by a DisplayPort™-to-LVDS converter. (Refer to the Realtek RTD2136R-CG, DisplayPort-to-LVDS converter datasheet.)

![An icon of a white document featuring a large red checkmark on the left side. Below the document is the text 'NOTE :'.](.lec-bts-50-1z173-1020-21/44326c929f6e2bf9cc9dbc2a83f4f28512fb428339717db516caba36bb3e4473.jpg)

The LEC-BTS supports single-channel LVDS. Backlight Enable, Display Enable, and PWMOUT are controlled from the BIOS setup.

# 3.2 HDMI (High-Definition Multimedia Interface)

The default setup defines the DDI1 port as HDMI and provides the following signals:

▶ 1 Clock pair
▶ 3 Data pairs
▶ Service signals

The HDMI interface is compliant with the HDMI 1.4 specification.

# 3.3 Camera CSI

The LEC-BTS brings out signals for two MIPI-CSI 2.0 (serial) camera interfaces, the first with clock and one data lane, the second with clock and up to four data lanes supporting up to 800 Mbit/s of actual pixels.

# 3.4 Audio (HDA)

The SoC provides an HDA controller, which communicates with internal or external CODECs over the Intel HDA serial link. HDA signals are brought out through the I2S2 pins on the SMARC connector and are multiplexed with LPE\_I2S audio signals. When HDA is active, LPE audio is disabled.

# 3.5 PCI Express (PCIe)

The CPU features four PCIe x1 ports, and the LEC-BTS module uses three of them for the PCIe interface and one of them for the Gigabit Ethernet interface. The PCIe interface supports the PCIe Base Specification 2.0 with a maximum signal rate of 5 GT/s and can be configured to support PCIe edge cards or Express Cards.

# 3.6 Gigabit Ethernet

The on-board Intel I210IT Ethernet controller uses PCIe x1 (v2.1) bus signals from the CPU to enable 10T/100TX/1000T operation through integrated MAC, PHY, and SGMII/SerDes interfaces.

# 3.7 USB Ports

The USB interface originates from two host controllers on the SoC that provide four USB 2.0 ports and one USB 3.0 port.

# 3.7.1 USB2.0

Three of the four USB 2.0 ports use the USB 0-2 pins on the SMARC connector. The fourth USB 2.0 port is routed through the AFB-DIFF2 pins on the SMARC connector, which map to the USB\_DP/N [0] pins on the SoC.

# 3.7.2 USB 3.0

The USB 3.0 port uses the AFB\_DIFF 0-1 pins on the SMARC connector, which map to the USB3\_TX/RX pins on the SoC. See Table 3-2.

# 3.8 SATA

The SATA interface provides one port through the SATA0 pins on the SMARC connector. The interface supports 1.5Gb/s and 3.0Gb/s. The LEC-BTS supports a second SATA port through the AFB Diff 3 and AFB Diff 4 signals on the SMARC connector (pins S71-S72 and S74-S75.)

# 3.9 I2C Bus

The LEC-BTS provides four interfaces through the I2C bus for General Purpose, Power Management, Camera, and LCD video I2C signals with operating speeds up to 400kHz. All I2C interfaces have 1.8V pull ups with 2.2k resistors.

# 3.10 SPI

The CPU implements an SPI controller, which supports two SPI Flash devices on the module for BIOS storage.

# 3.11 Serial (UART)

The LEC-BTS provides two serial interfaces: One port is a high-speed, 4-wire port (with TX/RX and RTS#/CTS#), and one port is 2-wire (with TX/RX only.)

# 3.12 I2S

The SMARC connector provides three pins for an LPE\_I2S audio interface. The LPE\_I2S interface is brought out through the I2S0 pins on the SMARC connector.

# 3.13 SD/SDIO Interface

Four parallel data lines comprise the SD/SDIO interface, supporting SD Card sockets.

# 3.14 eMMC Interface

The LEC-BTS provides one 8-bit eMMC interface port, brought out from the CPU through the SDMMC pins on the SMARC connector.

# 3.15 GPIO

The LEC-BTS provides 12 GPIO signals from the CMOS device on the module. The GPIO signals can be utilized for General Purpose IOs as well as camera, HDA, PWM, TACH, and CAN interfaces.

Table 3-1: GPIO Default Settings

<table><tr><td>SMARC Connector Pin</td><td>Default Function</td></tr><tr><td>GPIO0</td><td>CAM0_PWR#</td></tr><tr><td>GPIO1</td><td>CAM1_PWR#</td></tr><tr><td>GPIO2</td><td>CAM0_RST#</td></tr><tr><td>GPIO3</td><td>CAM1_RST#</td></tr><tr><td>GPIO4</td><td>HDA_RST#</td></tr><tr><td>GPIO5</td><td>GPIO</td></tr><tr><td>GPIO6</td><td>GPIO</td></tr><tr><td>GPIO7</td><td>GPIO</td></tr><tr><td>GPIO8</td><td>GPIO</td></tr><tr><td>GPIO9</td><td>GPIO</td></tr><tr><td>GPIO10</td><td>GPIO</td></tr><tr><td>GPIO11</td><td>GPIO</td></tr></table>

# 3.16 LPC Debug

A 40-pin, front flip, DB40 connector allows access to debug and update the BIOS, BMC, and OS code on the module. (Refer to “Debug (DB40)” on page 22.)

# 3.17 SMARC Interface Signals

Table 3-2 provides the pin signals for the SMARC P-S connector. Refer to the SMARC specification at http://www.sget.org/standards/smarc.html for definitions of the SMARC signals.

Note: The # symbol indicates the signal is Active Low.
Table 3-2: SMARC P-S Connector (GF1) Signal Descriptions

<table><tr><td>Pin #</td><td>Primary (Top Side)</td><td>Pin #</td><td>Secondary (Bottom Side)</td></tr><tr><td></td><td></td><td>S1</td><td>Not connected</td></tr><tr><td>P1</td><td>Not connected</td><td>S2</td><td>Not connected</td></tr><tr><td>P2</td><td>GND</td><td>S3</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+ (CSI1 differential clock inputs.)</td><td>S4</td><td>Not connected</td></tr><tr><td>P4</td><td>CSI1_CK- (CSI1 differential clock inputs.)</td><td>S5</td><td>I2C_CAM_CK (Serial / Parallel camera support link - I2C clock)</td></tr><tr><td>P5</td><td>Not connected</td><td>S6</td><td>CAM_MCK</td></tr><tr><td>P6</td><td>Not connected</td><td>S7</td><td>I2C_CAM_DAT (Serial / Parallel camera support link - I2C data)</td></tr><tr><td>P7</td><td>CSI1_D0+ (CSI1 differential data inputs.)</td><td>S8</td><td>CSI0_CK+ (CSI0 differential clock inputs.)</td></tr><tr><td>P8</td><td>CSI1_D0- (CSI1 differential data inputs.)</td><td>S9</td><td>CSI0_CK- (CSI0 differential clock inputs.)</td></tr><tr><td>P9</td><td>GND</td><td>S10</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_D1+ (CSI1 differential data inputs.)</td><td>S11</td><td>CSI0_D0+ (CSI0 differential data inputs.)</td></tr><tr><td>P11</td><td>CSI1_D1- (CSI1 differential data inputs.)</td><td>S12</td><td>CSI0_D0- (CSI0 differential data inputs.)</td></tr><tr><td>P12</td><td>GND</td><td>S13</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_D2+ (CSI1 differential data inputs.)</td><td>S14</td><td>Not connected</td></tr><tr><td>P14</td><td>CSI1_D2- (CSI1 differential data inputs.)</td><td>S15</td><td>Not connected</td></tr><tr><td>P15</td><td>GND</td><td>S16</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_D3+ (CSI1 differential data inputs.)</td><td>S17</td><td>AFB0_OUT (General purpose AFB output; maps to PMC_SLP_S3# on the SOC)</td></tr><tr><td>P17</td><td>CSI1_D3- (CSI1 differential data inputs.)</td><td>S18</td><td>AFB1_OUT (General purpose AFB output; maps to PMC_SLP_S4# on the SOC)</td></tr><tr><td>P18</td><td>GND</td><td>S19</td><td>AFB2_OUT (General purpose AFB output; maps to PMC_SUS_STAT# on the SOC)</td></tr><tr><td>P19</td><td>GBE_MDI3- (Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S20</td><td>Not connected</td></tr><tr><td>P20</td><td>GBE_MDI3+(Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S21</td><td>Not connected</td></tr><tr><td>P21</td><td>GBE_LINK100# (Link Speed Indication LED for 100Mbps; able to sink 24mA or more carrier LED current)</td><td>S22</td><td>Not connected</td></tr><tr><td>P22</td><td>GBE_LINK1000# (Link Speed Indication LED for 1000Mbps; able to sink 24mA or more carrier LED current)</td><td>S23</td><td>AFB6_PTIO (EN_OC# for USB SS)</td></tr><tr><td>P23</td><td>GBE_MDI2- (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S24</td><td>AFB7_PTIO (PCU_SMB_ALERT#)</td></tr><tr><td>P24</td><td>GBE_MDI2+ (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S25</td><td>GND</td></tr><tr><td>P25</td><td>GBE_LINK_ACT# (Link / Activity Indication LED Driven low on Link [10, 100 or 1000 mbps] Blinks on Activity; able to sink 24mA or more Carrier LED current)</td><td>S26</td><td>SDMMC_D0 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P26</td><td>GBE_MDI1- (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S27</td><td>SDMMC_D1 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P27</td><td>GBE_MDI1+ (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S28</td><td>SDMMC_D2 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P28</td><td>GBE_CTREF(Center-Tap reference voltage for GBE0 Carrier board Ethernet magnetic [if required by the Module GBE PHY])</td><td>S29</td><td>SDMMC_D3 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P29</td><td>GBE0_MDI0- (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S30</td><td>SDMMC_D4 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P30</td><td>GBE0_MDI0+ (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S31</td><td>SDMMC_D5 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P31</td><td>Not connected</td><td>S32</td><td>SDMMC_D6 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P32</td><td>GND</td><td>S33</td><td>SDMMC_D7 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P33</td><td>SDIO_WP (SDIO card Write Protect; 10K pull-up to 3.3V)</td><td>S34</td><td>GND</td></tr><tr><td>P34</td><td>SDIO_CMD (SDIO card Command line)</td><td>S35</td><td>SDMMC_CK (clock)</td></tr><tr><td>P35</td><td>SDIO_CD# (SDIO Card Detect; 10K pull-up to 3.3V)</td><td>S36</td><td>SDMMC_CMD (command line)</td></tr><tr><td>P36</td><td>SDIO_CK (SDIO card Clock)</td><td>S37</td><td>SDMMC_RST# (Reset signal to eMMC device)</td></tr><tr><td>P37</td><td>SDIO_PWR_EN (SDIO card Power Enable)</td><td>S38</td><td>Not connected</td></tr><tr><td>P38</td><td>GND</td><td>S39</td><td>I2S0_LRCK (Left &amp; Right audio synchronization clock)</td></tr><tr><td>P39</td><td>SDIO_D0 (SDIO card 4-bit data path)</td><td>S40</td><td>I2S0_SDOUT (Digital audio output)</td></tr><tr><td>P40</td><td>SDIO_D1 (SDIO card 4-bit data path)</td><td>S41</td><td>I2S0_SDIN (Digital audio input)</td></tr><tr><td>P41</td><td>SDIO_D2 (SDIO card 4-bit data path)</td><td>S42</td><td>I2S0_CK (Digital audio clock)</td></tr><tr><td>P42</td><td>SDIO_D3 (SDIO card 4-bit data path)</td><td>S43</td><td>Not connected</td></tr><tr><td>P43</td><td>Not connected</td><td>S44</td><td>Not connected</td></tr><tr><td>P44</td><td>Not connected</td><td>S45</td><td>Not connected</td></tr><tr><td>P45</td><td>Not connected</td><td>S46</td><td>Not connected</td></tr><tr><td>P46</td><td>Not connected</td><td>S47</td><td>GND</td></tr><tr><td>P47</td><td>GND</td><td>S48</td><td>I2C_GP_CK (I2C General Purpose clock signal)</td></tr><tr><td>P48</td><td>SATA0_TX+ (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S49</td><td>I2C_GP_DAT I2C (General Purpose data signal)</td></tr><tr><td>P49</td><td>SATA0_TX- (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S50</td><td>I2S2_LRCK (Left &amp; Right audio synchronization clock)</td></tr><tr><td>P50</td><td>GND</td><td>S51</td><td>I2S2_SDOUT (Digital audio output)</td></tr><tr><td>P51</td><td>SATA0_RX+ (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S52</td><td>I2S2_SDIN (Digital audio input)</td></tr><tr><td>P52</td><td>SATA0_RX- (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S53</td><td>I2S2_CK (Digital audio clock)</td></tr><tr><td>P53</td><td>GND</td><td>S54</td><td>SATA_ACT# (Active low SATA activity indicator If implemented, able to sink 24mA or more Carrier LED current)</td></tr><tr><td>P54</td><td>SPI1_CS0# (SPI1 Master Chip Select 0 output)</td><td>S55</td><td>Not connected</td></tr><tr><td>P55</td><td>Not connected</td><td>S56</td><td>Not connected</td></tr><tr><td>P56</td><td>SPI1_CK (SPI1 Master Clock output)</td><td>S57</td><td>Not connected</td></tr><tr><td>P57</td><td>SPI1_DIN (SPI1 Master Data input [input to CPU, output from SPI device])</td><td>S58</td><td>Not connected</td></tr><tr><td>P58</td><td>SPI1_DO (SPI1 Master Data output [output from CPU, input to SPI device])</td><td>S59</td><td>Not connected</td></tr><tr><td>P59</td><td>GND</td><td>S60</td><td>Not connected</td></tr><tr><td>P60</td><td>USB0+ (Differential USB0 data pair)</td><td>S61</td><td>GND</td></tr><tr><td>P61</td><td>USB0- (Differential USB0 data pair)</td><td>S62</td><td>AFB_DIFF0+ (maps to USB3_TX_P on the SOC)</td></tr><tr><td>P62</td><td>USB0_EN_OC# (Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S63</td><td>AFB_DIFF0- (maps to USB3_TX_N on the SOC)</td></tr><tr><td>P63</td><td>USB0_VBUS_DET (USB host power detection when this port is used as a device)</td><td>S64</td><td>GND</td></tr><tr><td>P64</td><td>USB0_OTG_ID (USB OTG ID input, active high)</td><td>S65</td><td>AFB_DIFF1+ (maps to USB3_RX_P on the SOC)</td></tr><tr><td>P65</td><td>USB1+ (Differential USB1 data pair)</td><td>S66</td><td>AFB_DIFF1- (maps to USB3_RX_N on the SOC)</td></tr><tr><td>P66</td><td>USB1- (Differential USB1 data pair)</td><td>S67</td><td>GND</td></tr><tr><td>P67</td><td>USB1_EN_OC# (Pulled low by Module OD driver to disable USB1 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S68</td><td>AFB_DIFF2+ (maps to USB_D0_P on the SOC)</td></tr><tr><td>P68</td><td>GND</td><td>S69</td><td>AFB_DIFF2- (maps to USB_D0_N on the SOC)</td></tr><tr><td>P69</td><td>USB2+ (Differential USB2 data pair)</td><td>S70</td><td>GND</td></tr><tr><td>P70</td><td>USB2- (Differential USB2 data pair)</td><td>S71</td><td>AFB_DIFF3+ (maps to SATA_TX1_P on the SOC)</td></tr><tr><td>P71</td><td>USB2_EN_OC# (Pulled low by Module OD driver to disable USB2 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up shall be present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S72</td><td>AFB_DIFF3- (maps to SATA_TX1_N on the SOC)</td></tr><tr><td>P72</td><td>PCIE_C_PRSNT# (PCIe Port C present input. Pulled up or terminated on Module)</td><td>S73</td><td>GND</td></tr><tr><td>P73</td><td>PCIE_B_PRSNT# (PCIe Port B present input. Pulled up or terminated on Module)</td><td>S74</td><td>AFB_DIFF4+ (maps to SATA_RX1_P on the SOC)</td></tr><tr><td>P74</td><td>PCIE_A_PRSNT# (PCIe Port A present input. Pulled up or terminated on Module)</td><td>S75</td><td>AFB_DIFF4- (maps to SATA_RX1_N on the SOC)</td></tr><tr><td></td><td>Key</td><td></td><td>Key</td></tr><tr><td>P75</td><td>PCIE_A_RST# (PCIe Port A reset output)</td><td>S76</td><td>PCIE_B_RST# (PCIe Port B reset output, active low)</td></tr><tr><td>P76</td><td>PCIE_C_CREQ# (PCIe Port C clock request input. Pulled up or terminated on Module)</td><td>S77</td><td>PCIE_C_RST# (PCIe Port A reset output, active low)</td></tr><tr><td>P77</td><td>PCIE_B_CREQ# (PCIe Port B clock request input. Pulled up or terminated on Module)</td><td>S78</td><td>PCIE_C_RX+ (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P78</td><td>PCIE_A_CREQ# (PCIe Port A clock request input. Pulled up or terminated on Module)</td><td>S79</td><td>PCIE_C_RX- (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P79</td><td>GND</td><td>S80</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+ (Differential PCIe Link C reference clock output. DC coupled)</td><td>S81</td><td>PCIE_C_TX+ (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P81</td><td>PCIE_C_REFCK- (Differential PCIe Link C reference clock output. DC coupled)</td><td>S82</td><td>PCIE_C_TX- (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P82</td><td>GND</td><td>S83</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+ (Differential PCIe Link A reference clock output. DC coupled)</td><td>S84</td><td>PCIE_B_REFCK+ (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P84</td><td>PCIE_A_REFCK- (Differential PCIe Link A reference clock output. DC coupled)</td><td>S85</td><td>PCIE_B_REFCK- (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P85</td><td>GND</td><td>S86</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+ (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S87</td><td>PCIE_B_RX+ (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P87</td><td>PCIE_A_RX- (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S88</td><td>PCIE_B_RX- (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P88</td><td>GND</td><td>S89</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+ (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>S90</td><td>PCIE_B_TX+ (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P90</td><td>PCIE_A_TX- (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>P91</td><td>PCIE_B_TX- (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P91</td><td>GND</td><td>S92</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+ (TMDS / HDMI data 2 differential pair)</td><td>S93</td><td>Not connected</td></tr><tr><td>P93</td><td>HDMI_D2- (TMDS / HDMI data 2 differential pair)</td><td>S94</td><td>Not connected</td></tr><tr><td>P94</td><td>GND</td><td>S95</td><td>Not connected</td></tr><tr><td>P95</td><td>HDMI_D1+ (TMDS / HDMI data 1 differential pair)</td><td>S96</td><td>Not connected</td></tr><tr><td>P96</td><td>HDMI_D1- (TMDS / HDMI data 1 differential pair)</td><td>S97</td><td>Not connected</td></tr><tr><td>P97</td><td>GND</td><td>S98</td><td>Not connected</td></tr><tr><td>P98</td><td>HDMI_D0+ (TMDS / HDMI data 0 differential pair)</td><td>S99</td><td>Not connected</td></tr><tr><td>P99</td><td>HDMI_D0- (TMDS / HDMI data 0 differential pair)</td><td>S100</td><td>Not connected</td></tr><tr><td>P100</td><td>GND</td><td>S101</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+ (TMDS / HDMI clock output differential pair)</td><td>S102</td><td>Not connected</td></tr><tr><td>P102</td><td>HDMI_CK- (TMDS / HDMI clock output differential pair)</td><td>S103</td><td>Not connected</td></tr><tr><td>P103</td><td>GND</td><td>S104</td><td>Not connected</td></tr><tr><td>P104</td><td>HDMI_HPD (HDMI Hot Plug Detect input)</td><td>S105</td><td>Not connected</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK (I2C clock line dedicated to HDMI)</td><td>S106</td><td>Not connected</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT (I2C data line dedicated to HDMI)</td><td>S107</td><td>Not connected</td></tr><tr><td>P107</td><td>HDMI_CEC (HDMI Consumer Electronics Control, 1 - wire peripheral control interface)</td><td>S108</td><td>Not connected</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR# [default] (Camera 0 Power Enable, active low output)</td><td>S109</td><td>Not connected</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR# [default] (Camera 1 Power Enable, active low output)</td><td>S110</td><td>GND</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST# [default] (Camera 0 Reset, active low output)</td><td>S111</td><td>Not connected</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST# [default] (Camera 1 Reset, active low output)</td><td>S112</td><td>Not connected</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST# [default] (HD Audio Reset, active low output )</td><td>S113</td><td>Not connected</td></tr><tr><td>P113</td><td>GPIO5 (General Purpose IO)</td><td>S114</td><td>Not connected</td></tr><tr><td>P114</td><td>GPIO6 (General Purpose IO)</td><td>S115</td><td>Not connected</td></tr><tr><td>P115</td><td>GPIO7 (General Purpose IO)</td><td>S116</td><td>Not connected</td></tr><tr><td>P116</td><td>GPIO8 (General Purpose IO)</td><td>S117</td><td>Not connected</td></tr><tr><td>P117</td><td>GPIO9 (General Purpose IO)</td><td>S118</td><td>Not connected</td></tr><tr><td>P118</td><td>GPIO10 (General Purpose IO)</td><td>S119</td><td>GND</td></tr><tr><td>P119</td><td>GPIO11 (General Purpose IO)</td><td>S120</td><td>Not connected</td></tr><tr><td>P120</td><td>GND</td><td>P121</td><td>Not connected</td></tr><tr><td>P121</td><td>I2C_PM_CK (Power management I2C bus clock)</td><td>S122</td><td>Not connected</td></tr><tr><td>P122</td><td>I2C_PM_DAT (Power management I2C bus data)</td><td>S123</td><td>Not connected</td></tr><tr><td>P123</td><td>BOOT_SEL0# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S124</td><td>GND</td></tr><tr><td>P124</td><td>BOOT_SEL1# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S125</td><td>LVDS0+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P125</td><td>BOOT_SEL2# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S126</td><td>LVDS0- (LVDS LCD data channel differential pair)</td></tr><tr><td>P126</td><td>RESET_OUT# (General purpose reset output to Carrier board.)</td><td>S127</td><td>LCD_BKLT_EN (High enables panel backlight)</td></tr><tr><td>P127</td><td>RESET_IN# (Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S128</td><td>LVDS1+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P128</td><td>POWER_BTN# (Power-button input from Carrier board. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the Module Pulled up on Module. Driven by OD part on Carrier.)</td><td>S129</td><td>LVDS1- (LVDS LCD data channel differential pair)</td></tr><tr><td>P129</td><td>SER0_TX (Asynchronous serial port data out)</td><td>S130</td><td>GND</td></tr><tr><td>P130</td><td>SER0_RX (Asynchronous serial port data in)</td><td>S131</td><td>LVDS2+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P131</td><td>SER0_RTS# (Request to Send handshake line for SER0)</td><td>S132</td><td>LVDS2- (LVDS LCD data channel differential pair)</td></tr><tr><td>P132</td><td>SER0_CTS# (Clear to Send handshake line for SER0)</td><td>S133</td><td>LCD_VDD_EN (High enables panel VDD)</td></tr><tr><td>P133</td><td>GND</td><td>S134</td><td>LVDS_CK+ (LVDS LCD differential clock pair)</td></tr><tr><td>P134</td><td>SER1_TX (Asynchronous serial port data out)</td><td>S135</td><td>LVDS_CK- (LVDS LCD differential clock pair)</td></tr><tr><td>P135</td><td>SER1_RX (Asynchronous serial port data in)</td><td>S136</td><td>GND</td></tr><tr><td>P136</td><td>SER2_TX (Asynchronous serial port data out)</td><td>S137</td><td>LVDS3+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P137</td><td>SER2_RX (Asynchronous serial port data in)</td><td>S138</td><td>LVDS3- (LVDS LCD data channel differential pair)</td></tr><tr><td>P138</td><td>SER2_RTS# (Request to Send handshake line for SER2)</td><td>S139</td><td>I2C_LCD_CK (I2C clock – to read LCD display EDID EEPROMs)</td></tr><tr><td>P139</td><td>SER2_CTS# (Clear to Send handshake line for SER2)</td><td>S140</td><td>I2C_LCD_DAT (I2C data – to read LCD display EDID EEPROMs)</td></tr><tr><td>P140</td><td>Not connected</td><td>S141</td><td>LCD_BKLT_PWM (Display backlight PWM control)</td></tr><tr><td>P141</td><td>Not connected</td><td>S142</td><td>Not connected</td></tr><tr><td>P142</td><td>GND</td><td>S143</td><td>GND</td></tr><tr><td>P143</td><td>Not connected</td><td>S144</td><td>RSVD / EDP_HPD (Reserved for future eDP Hot Plug Detect pin)</td></tr><tr><td>P144</td><td>Not connected</td><td>S145</td><td>WDT_TIME_OUT# (Watchdog Timer Output)</td></tr><tr><td>P145</td><td>Not connected</td><td>S146</td><td>PCIE_WAKE (PCIe wake up interrupt to host – common to PCIe; links A, B, C – pulled up or terminated on Module)</td></tr><tr><td>P146</td><td>Not connected</td><td>S147</td><td>VDD_RTC (Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.See Section 7.3 RTC Voltage Rail of the SMARC specification for an important safety note on the implementation of lithium backup batteries.)</td></tr><tr><td>P147</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S148</td><td>LID# (Lid open/close indication to Module.Low indicates lid closure, which system may use to initiate a sleep state. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the ModulePulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P148</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S149</td><td>SLEEP# (Sleep indicator from Carrier board; sourced from user Sleep button or Carrier logic. Carrier to float the line in inactive state. Active low, level sensitive; de-bounced on the Module.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P149</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S150</td><td>VIN_PWR_BAD# (Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) is not enabled while this signal is held low by the Carrier.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P150</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S151</td><td>CHARGING# (Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P151</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S152</td><td>CHARGER_PRSNT# (Held low by Carrier if DC input for battery charger is present. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P152</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S153</td><td>CARRIER_STBY# (The Module drives this signal low when the system is in a standby power state)</td></tr><tr><td>P153</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S154</td><td>CARRIER_PWR_ON (Carrier board circuits [apart from power management and power path circuits] are powered up until the Module asserts the CARRIER_PWR_ON signal)</td></tr><tr><td>P154</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S155</td><td>FORCE_RECOV# (Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery function, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P155</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S156</td><td>BATLOW# (Battery low indication to Module. Carrier to float the line in inactive state. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P156</td><td>VDD_IN (Module power input voltage - 5V)</td><td>S157</td><td>TEST# (Held low by Carrier to invoke Module vendor specific test function(s). Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td></td><td></td><td>S158</td><td>GND</td></tr></table>

# 3.18 Debug (DB40)

Table 3-3 lists the pin signals of the CN1 connector, which provides 40 pins, 1 row, consecutive sequence with 0.02" (0.50mm) pitch.

Table 3-3: Debug Interface Signals (CN1)

<table><tr><td>Pin #</td><td>Interface</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>RESVD (0R0 PD to GND)</td></tr><tr><td>2</td><td rowspan="4">SMC Debug</td><td>SMC_STATUS (Connect LED)</td></tr><tr><td>3</td><td>BIOS_MODE (Not Used)</td></tr><tr><td>4</td><td>SEL_BIOS (Connect to jumper for debug)</td></tr><tr><td>5</td><td>POSTWDT_DIS# (Connect to jumper for debug)</td></tr><tr><td>6</td><td rowspan="7">Test Point</td><td>SUS_S5# (Bridge to pin 22 (3V#_DUAL)</td></tr><tr><td>7</td><td>SUS_S4#</td></tr><tr><td>8</td><td>SUS_S3#</td></tr><tr><td>9</td><td>CB_PWROK (Connected to V3P3S)</td></tr><tr><td>10</td><td>CB_RESET# (Connected to pin 30)</td></tr><tr><td>11</td><td>SYS_RESET#</td></tr><tr><td>12</td><td>PWRBTN#</td></tr><tr><td>13</td><td rowspan="11">SMC Program Interface</td><td>SMC_OCD0B (Use jumper to connect 0CD0B via 1K0 pull-down to GND)</td></tr><tr><td>14</td><td>SMC_OCD0A (Use jumper to connect 0CD0A via 1K0 pull-up to 3.3V_SMC)</td></tr><tr><td>15</td><td>SMC_CLK</td></tr><tr><td>16</td><td>SMC_DATA</td></tr><tr><td>17</td><td>SMC_RESET_IN#</td></tr><tr><td>18</td><td>SMC_FLMD0</td></tr><tr><td>19</td><td>SMC_RXD6</td></tr><tr><td>20</td><td>SMC_TXD6</td></tr><tr><td>21</td><td>GND3</td></tr><tr><td>22</td><td>3V3_DUAL (Connected to V3P3A)</td></tr><tr><td>23</td><td>3V3_SMC1 (Connected to VBMC)</td></tr><tr><td>24</td><td rowspan="10">LPC Debug Card Interface</td><td>LPC_AD0</td></tr><tr><td>25</td><td>LPC_AD1 (3.3V provided from module)</td></tr><tr><td>26</td><td>LPC_AD2</td></tr><tr><td>27</td><td>LPC_AD3</td></tr><tr><td>28</td><td>LPC_FRAME#</td></tr><tr><td>29</td><td>CLK33_LPC</td></tr><tr><td>30</td><td>RST#</td></tr><tr><td>31</td><td>BIOS_DIS0</td></tr><tr><td>32</td><td>GND2</td></tr><tr><td>33</td><td>LPC_3V3 (Connected to V3P3S)</td></tr><tr><td>34</td><td rowspan="7">SPI Program Interface</td><td>SPI_BIOS_CLK</td></tr><tr><td>35</td><td>SPI_BIOS_MOSI</td></tr><tr><td>36</td><td>SPI_BIOS_MISO</td></tr><tr><td>37</td><td>SPI_BIOS_CS1#</td></tr><tr><td>38</td><td>SPI_BIOS_CS0#</td></tr><tr><td>39</td><td>GND1</td></tr><tr><td>40</td><td>VCC_SPI_IN (SPI power input from flash tool to module)</td></tr></table>

NOTE: The gray table cells denote ground. The # symbol indicates the signal is Active Low.

# 4 Utilities

This chapter provides information on how to read information from and configure the BIOS Setup utility, the SEMA utility, the Watchdog Timer utility, and the board temperature sensors on the LEC-BTS.

# 4.1 BIOS

The LEC-BTS features an AMI BIOS. The default settings provide a “ready to run” system, even without a BIOS setup backup battery.

The BIOS is located in flash memory and can be easily updated with software under DOS.

All setup changes of the BIOS are stored in the CMOS RAM.

The battery on the baseboard will provide power to store that information for over two years without board activation.

This section presents screen shots the five primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The submenus are presented as tables and describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Table 4-1: BIOS Setup Menu Structure

<table><tr><td>Main</td><td>Advanced</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOSInformationCPUConfigurationMemoryInformationGOP InformationTXE InformationSystemManagement►System DateSystem Time</td><td>CPU►Graphics►SATA►USB►SDIO►Network►Audio►PCI/PCIe►Baytrail FeaturesConfiguration►ACPI►Serial Port Console►Thermal►Security►Miscellaneous►</td><td>Password Description►Administrator PasswordSecure Boot Menu►</td><td>Boot Configuration►CSM Parameters►Boot Option PrioritiesAdd New Boot Option►Delete Boot Option►</td><td>Reset OptionsSave OptionsBoot OverrideLaunch EFI Shell from filesystem deviceReset System with ME disabled ModeMEUD000►</td></tr></table>

# Notes:

▶ indicates a submenu

# 4.1.1 Starting the BIOS Setup Utility

Use the following bullets to initiate start-up activity for the BIOS Setup Utility.

▶ Press &lt;DEL&gt; during power up to start the BIOS setup utility.
▶ Press &lt;F11&gt; during power up to start the Boot menu.
▶ Press &lt;END&gt; during power up to return BIOS settings to default.

# 4.1.2 Main Menu

The Main Menu provides read-only information about your system and also allows you to change System Management settings and set the System Date and Time. Refer to the tables below for details of the submenus and settings.

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nMain Advanced Security Boot Save & Exit\nBIOS Information\nBIOS Vendor American Megatrends\nCore Version 5.009\nCompliancy UEFI 2.3; PI 1.2\nProject Version LEC-BTS 1.15 x64\nBuild Date and Time 2016/03/22 09:51:51\nCPU Configuration\nMicrocode Patch 903\nBayTrail SoC DO Stepping\nMemory Information\nTotal Memory 4096 MB (DDR3L)\nGOP Information\nIntel(R) GOP Driver (N/A)\nTXE Information\nSec RC Version 00.05.00.00\nTXE FW Version 01.01.04.1148\nSystem Management\nSystem Date (Tue 2016/03/22)\nSystem Time (00:01:11)\n▲ System Management\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/3b63ea43a8ca92a93c850d30e51f49232b33941fc0aa898e8253d2cca9ea8881.jpg)

Figure 4-1: BIOS Setup Main Menu

# BIOS Information

Table 4-2: Main Menu BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>ADLINK BIOS version</td></tr><tr><td>Build Date and Time</td><td>Info only</td><td>Date the BIOS was built</td></tr></table>

# Processor Information

Table 4-3: Main Menu Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Microcode</td><td>Info only</td><td>Display CPU Microcode Patch</td></tr><tr><td>Bay Trail SOC</td><td>Info only</td><td>Display SOC stepping</td></tr></table>

# Memory Information

Table 4-4: Main Menu Memory Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display total memory information</td></tr></table>

# GOP Information

Table 4-5: Main Menu GOP Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel(R) GOP Driver</td><td>I[N/A]</td><td></td></tr></table>

# TXE Information

Table 4-6: Main Menu TXE Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Sec RC Version</td><td>Info Only</td><td>Display RC Version</td></tr><tr><td>TXE FW Version</td><td>Info Only</td><td>display version of TXE</td></tr></table>

# Main Menu > System Management

The System Management submenu provides read-only information about your system and also allows you to change some System Management settings. Refer to the tables below for details of the submenus and settings

# Main Menu > System Management > Board Information

Table 4-7: Main Menu > System Management > Board Information

<table><tr><td>Board Information</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Firmware</td><td>Read only</td><td>Display SMC firmware</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SMC firmware build date</td></tr><tr><td>SEMA Boot loader</td><td>Read only</td><td>Display SMC boot loader</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SMC boot loader build date</td></tr><tr><td>Hardware Version</td><td>Read only</td><td>Display SMC hardware version</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC serial number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC manufacturing date</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC last repair date</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display SMC MAC ID</td></tr><tr><td>SEMA Features:</td><td>Read only</td><td>Display SEMA features</td></tr></table>

# Main Menu > System Management > Temperatures

Table 4-8: Main Menu > System Management > Temperature

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures</td><td colspan="2">Info only</td></tr><tr><td>Board Temperatures</td><td colspan="2">Info only</td></tr><tr><td>▷ Current</td><td>Read only</td><td>Display current board temperature</td></tr><tr><td>▷ Startup</td><td>Read only</td><td>Display board startup temperature</td></tr><tr><td>▷ Min</td><td>Read only</td><td>Display board min. temperature</td></tr><tr><td>▷ Max</td><td>Read only</td><td>Display board max. temperature</td></tr></table>

# Main Menu > System Management > Power Consumption

Table 4-9: Main Menu > System Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power</td></tr><tr><td>GPU_Vcore</td><td>Read only</td><td>Display actual GPU-Vcore voltage</td></tr><tr><td>GFX-Vcore</td><td>Read only</td><td>Display actual GFX-Vcore voltage</td></tr><tr><td>V1.00</td><td>Read only</td><td>Display actual V1.00 voltage</td></tr><tr><td>VMEM</td><td>Read only</td><td>Display actual VMEM voltage</td></tr><tr><td>V1.80</td><td>Read only</td><td>Display actual V1.80 voltage</td></tr><tr><td>V3.30</td><td>Read only</td><td>Display actual V3.30 voltage</td></tr><tr><td>V3.30</td><td>Read only</td><td>Display actual V3.30 voltage</td></tr><tr><td>VIN</td><td>Read only</td><td>Display actual VIN voltage</td></tr></table>

# Main Menu > System Management > Runtime Statistics

Table 4-10: Main Menu > System Management > Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

# Main Menu > System Management > Flags

Table 4-11: Main Menu > System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td>Display the selection of current BIOS ROM</td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td>Display ATX/AT-Mode</td></tr><tr><td>Exception Code</td><td>Read only</td><td>System exception reason</td></tr></table>

# Main Menu > System Management > Power Up

Table 4-12: Main Menu >System Management > Power Up

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Up</td><td colspan="2">Info only</td></tr><tr><td>Power Up watchdogNote: F12 disables the Power Up Watchdog.</td><td>EnabledDisabled</td><td>The Power-Up Watchdog resets the system after a certain amount of time after power-up.</td></tr><tr><td>Power-up ModeAttention: The Power-Up Mode only has affect, if the module is in ATX-Mode.</td><td>Turn onRemain offLast State</td><td>Turn On: The machine starts automatically when the power supply is turned on.Remain Off: To start the machine the power button has to be pressed.Last State: When powered on during a power failure the system will automatically power on when power is restored.</td></tr></table>

Main Menu > System Management > LVDS Backlight

Table 4-13: Main Menu > System Management > LVDS Backlight

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS Backlight</td><td colspan="2">Info only</td></tr><tr><td>LVDS Backlight Bright</td><td>255</td><td>The value range starts at 0 and ends at 255.</td></tr></table>

Main Menu > System Date and Time

Table 4-14: Main Menu > System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Day of Week, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# 4.1.3 Advanced Menu

This menu contains the settings for most of the user interfaces in the system. The “Advanced” menu provides configuration settings for CPU, Memory, Graphics, SATA, USB, SDIO, Network, Audio, PCIe Configuration, ACPI, Serial Console, Thermal, Security, and Miscellaneous.

![The image shows a standard safety warning sign. It features a yellow triangle with a thick black border. Inside the triangle is a black exclamation point (!). Below the triangle, the word 'CAUTION:' is printed in black, uppercase letters.](.lec-bts-50-1z173-1020-21/89edb140fe09138a34012778ecf7856c08fca56411052b301d844fd8327a9c35.jpg)

Inappropriate values for any of the following advanced settings may cause system errors.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.</td></tr><tr><td colspan="2">Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>CPU Configuration Graphics Configuration SATA Configuration USB Configuration SDIO Configuration Network Configuration Audio Configuration PCI/PCIe Configuration Baytrail Features Configuration ACPI Settings Serial Port Console Redirection Thermal Configuration Security Configuration Miscellaneous</td><td>CPU Configuration Parameters</td></tr><tr><td></td><td>+:-: Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F9: Optimized Defaults F10: Save &amp; Exit ESC: Exit</td></tr></table>

Figure 4-2: BIOS Setup Advanced Menu

# Advanced Menu > CPU Configuration

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nAdvanced\nCPU Configuration\n► Socket O CPU Information\n► CPU Thermal Configuration\n► PPM Configuration\nCPU Speed	1918 MHz\n64-bit	Supported\nLimit CPUID Maximum	(Disabled)\nExecute Disable Bit	(Enabled)\nIntel Virtualization Technology	(Enabled)\nPower Technology	(Energy Efficient)\nSocket specific CPU Information\n+:-: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.                    B4](.lec-bts-50-1z173-1020-21/98f9031042c32da00d66659d9e8cf2ccaca34ca8ec9c0f2fd5fe966aef7a9703.jpg)

Figure 4-3: BIOS Setup Advanced Menu > CPU Configuration

# Advanced > CPU Configuration > Socket 0 CPU Information

Table 4-15: Advanced > CPU Configuration > Socket 0 Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Brand Name</td><td>Info only</td><td>Display CPU brand name</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU signature</td></tr><tr><td>Microcode Patch</td><td>Info only</td><td>Display microcode patch</td></tr><tr><td>Max CPU speed</td><td>Info only</td><td>Display max. CPU speed</td></tr><tr><td>Min CPU speed</td><td>Info only</td><td>Display min. CPU speed</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display number of processor cores</td></tr><tr><td>Intel HT Technology</td><td>Info only</td><td>Display Intel HT Technology support</td></tr><tr><td>Intel VT-x Technology</td><td>Info only</td><td>Display Intel VT-x Technology support</td></tr><tr><td>64-bit</td><td>Info only</td><td>Display 64-bit support</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display cache info</td></tr></table>

# Advanced > CPU Configuration > CPU Thermal Configuration

Table 4-16: Advanced > CPU Configuration > CPU Thermal Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>DTS</td><td>DisabledEnabled</td><td>Enable/Disable digital thermal sensor</td></tr></table>

# Advanced > CPU Configuration > PPM Configuration

Table 4-17: Advanced > CPU Configuration > CPU Thermal Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU C state report</td><td>DisabledEnabled</td><td>Enable/Disable CPU C state report to OS</td></tr><tr><td>Max CPU C state</td><td>C7C6C1</td><td>This option controls Max C state that the processor will support</td></tr><tr><td>CPU speed</td><td colspan="2">Info only</td></tr><tr><td>64-bit</td><td colspan="2">Info only</td></tr><tr><td>Limit CPUID Maximum</td><td>DisabledEnabled</td><td>Disabled for windows XP</td></tr><tr><td>Execute Disabled Bit</td><td>DisabledEnabled</td><td>XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, Red Hat enterprise 3 Update3.)</td></tr><tr><td>Intel Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VWM can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr><tr><td>Power Technology</td><td>DisabledEnergy EfficientCustom</td><td>Enable the power management features</td></tr></table>

# Advanced Menu > Graphics

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nAdvanced\nGraphics Configuration\n► Intel IGD Configuration\n► Graphics Power Management Control\n► VBIOS - LCD Control\nLVDS Backlight Mode    (BMC Mode)\nConfig Intel IGD Settings.\n++: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/d80afeb7e96fadb8d5d71ac2731dc77742f7acdfebfca5525023648f7ccecef8.jpg)

Figure 4-4: BIOS Setup Advanced Menu > Graphics Configuration

# Advanced > Graphics > Intel IGD Configuration

Table 4-18: Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Integrated Graphics Device</td><td>EnabledDisabled</td><td>Enabled: Enable Integrated Graphics Device (IGD) when selected as the primary display; Disabled: Always disable IGD</td></tr><tr><td>IGD Turbo Enable</td><td>EnabledDisabled</td><td>Enable: Enable IGD Turbo Enable; Disable: IGD Turbo Disable</td></tr><tr><td>Primary Display</td><td>AutoIGDPCIE</td><td>Select which graphics device (IGD/PCI) should be primary display</td></tr><tr><td>GFX Boost</td><td>EnabledDisabled</td><td>Enable/Disable GFX Boost</td></tr><tr><td>PAVC</td><td>DisabledLITE ModeSERPENT Mode</td><td>Enable/Disable Protected Audio Video Control</td></tr><tr><td>DVMT Pre-Allocated</td><td>64M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>256MB</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>Aperture Size</td><td>256MB</td><td>Select the aperture size</td></tr><tr><td>DOP CG</td><td>EnabledDisabled</td><td>Enable/Disable DOP Clock Gating</td></tr><tr><td>GTT Size</td><td>2MB</td><td>Select the GTT size</td></tr><tr><td>IGD Thermal</td><td>EnabledDisabled</td><td>Enable/Disable IGD Thermal</td></tr><tr><td>Spread Spectrum clock</td><td>EnabledDisabled</td><td>Enable/Disable Spread Spectrum clock</td></tr><tr><td>ISP Enable/Disable</td><td>EnabledDisabled</td><td>Enable/Disable ISP PCI Device Selection</td></tr><tr><td>ISP PCI Device Selection</td><td>DisabledISP PCI Device as B0D2F0ISP PCI Device as B0D3F0</td><td>Default ISP is PCI B0D2F0 for Window Boot. Linux Boot to Select B0D3F0</td></tr><tr><td>Vcc_Vnn for Power State2</td><td>EnabledDisabled</td><td>Enable or Disable Vcc Vnn Config for Power State2</td></tr></table>

# Advanced > Graphics > Graphics Power Management Control

Table 4-19: Advanced > CPU Configuration > CPU Thermal Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RC6 (Render Standby)</td><td>EnabledDisabled</td><td>Enable/Disable render standby support</td></tr></table>

Advanced > Graphics > VBIOS - LCD Control

Table 4-20: Advanced > Graphics > VBIOS > LCD control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Primary IGFX Boot Display</td><td>VBIOS DefaultHDMILVDS</td><td>Select the Video Device that will be activated during POST. This has no effect if external graphics are present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display.</td></tr><tr><td>LCD Panel Type</td><td>VBIOS Default</td><td>Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>Panel Scaling</td><td>AutoOffForce Scaling</td><td>Select the LCD panel scaling option used by the Internal Graphics Device.</td></tr></table>

Advanced > Graphics > LVDS Backlight Mode

Table 4-21: Advanced >Graphics > LVDS Backlight Mode

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS Backlight Mode</td><td>• BMC Mode• GTT Mode</td><td>Select LVDS backlight control function.</td></tr></table>

Advanced Menu > SATA

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>IDE Configuration Serial-ATA (SATA) [Enabled] SATA Test Mode [Disabled] SATA Speed Support [Gen2] SATA ODD Port [No ODD] SATA Mode [AHCI Mode] Serial-ATA Port 0 [Enabled] SATA Port0 HotPlug [Disabled] Serial-ATA Port 1 [Enabled] SATA Port1 HotPlug [Disabled] SATA Port0 Not Present SATA Port1 Not Present</td><td>Enable / Disable Serial ATA ++: Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F9: Optimized Defaults F10: Save &amp; Exit ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-5: BIOS Setup Advanced Menu > SATA

Table 4-22: Advanced > SATA

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial-ATA Controller</td><td>EnabledDisabled</td><td>Enable/Disable Serial ATA.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode enable/disable</td></tr><tr><td>SATA Speed Support</td><td>Gen1Gen2</td><td>SATA speed support Gen1 or Gen2.</td></tr><tr><td>SATA ODD Port</td><td>Port0 ODDNo ODD</td><td>SATA ODD is Port0 or Port1</td></tr><tr><td>SATA Mode</td><td>IDE ModeAHCI Mode</td><td>Select IDE/AHCI</td></tr><tr><td>Serial-ATA Port X</td><td>EnabledDisabled</td><td>Enable/Disable SATA port X.</td></tr><tr><td>SATA PortX HotPlug</td><td>EnabledDisabled</td><td>Enable/Disable SATA port X hotplug.</td></tr></table>

Advanced Menu > USB

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td colspan="2">USB Configuration
USB Module Version 8.11.01
USB Devices:
1 Drive, 1 Keyboard, 3 Hubs
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
EHCI Hand-off [Disabled]
USB Mass Storage Driver Support [Enabled]</td></tr><tr><td colspan="2">USB hardware delays and time-outs:
USB transfer time-out [20 sec]
Device reset time-out [20 sec]
Device power-up delay [Auto]</td></tr><tr><td colspan="2">USB Host Controller Configuration
►USB Host Controller Configuration
Mass Storage Devices:
U1-Generic Flash Disk 8.07 [Auto]</td></tr><tr><td></td><td>Enables Legacy USB support.
AUTO option disables legacy
support if no USB devices are
connected. DISABLE option will
keep USB devices available
only for EFI applications.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr></table>

Figure 4-6: BIOS Setup Advanced Menu > USB

Table 4-23: Advanced Menu > USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB</td><td colspan="2">Info only</td></tr><tr><td>USB Module Version</td><td colspan="2">Info only</td></tr><tr><td>USB Devices</td><td>Info only</td><td>Drives, keyboards, mouse, hubs</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications and setup.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSe without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.</td></tr><tr><td>EHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSe without EHCI hand-off support. The EHCI ownership change should be claimed by the EHCI OS driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>EnabledDisabled</td><td>Enable/Disable USB mass storage driver support.</td></tr><tr><td>USB transfer time-out</td><td>1 sec5 sec10 sec20 sec</td><td>The time-out value for control, bulk, and interrupt transfers</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Host Controller.&#x27;Auto&#x27; uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.</td></tr><tr><td>Mass Storage Devices</td><td>Info only</td><td>List current USB mass storage devices.</td></tr></table>

# Advanced > USB > USB Host Controller Configuration

Table 4-24: Advanced Chipset USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Client Support</td><td>PCI modeDisabled</td><td>Enable/Disable USB OTG Support</td></tr><tr><td>XHCI Mode</td><td>EnabledDisabledAutoSmart Auto</td><td>Mode of operation of xHCI controller.</td></tr><tr><td>USB 2.0 (EHCI) Support</td><td>EnabledDisabled</td><td>Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled.</td></tr><tr><td>USB EHCI debug</td><td>EnabledDisabled</td><td>Enable/Disable PCH EHCI debug capability</td></tr><tr><td>USB Per Port Control</td><td>EnabledDisabled</td><td>Control each of the USB ports (0~2). Enable: Enable USB per port; Disable: Use USB port x settings.</td></tr><tr><td>USB Port #0~2</td><td>EnabledDisabled</td><td>Enable/Disable USB port 0-2.</td></tr></table>

# Advanced Menu > SDIO

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nAdvanced\nSDIO Configuration\nSDIO Access Mode (Auto)\nAuto Option: Access SD device\nin DMA mode if controller\nsupports it,otherwise in PIO\nmode.DMA Option: Access SD\ndevice in DMA mode.PIO Option:\nAccess SD device in PIO mode.\n+:-: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/e223d486895709c273f60ef328b658d383da4765a3157841e79ddf0e7f58290e.jpg)

Figure 4-7: BIOS Setup Advanced Menu > SDIO

Table 4-25: Advanced Menu > SDIO

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SDIO Access Mode</td><td>• Auto• DMA• PIO</td><td>Auto Option: Access SD device in DMA mode if controller supports it, other wise in PIO mode. DMA Option: Access SD device in DMA mode. PIO Option: Access SD device in PIO mode.</td></tr></table>

# Advanced Menu > Network

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nAdvanced\nNetwork Stack (Disabled) Enable/Disable UEFI Network Stack\n+:-: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/3a11ba563b40d4b96171658349b84eb11f143dee889125eb6e19b53dd935d415.jpg)

Figure 4-8: BIOS Setup Advanced Menu > Network

Table 4-26: Advanced Network

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>EnabledDisabled</td><td>Enable/Disable UEFI network stack.</td></tr></table>

# Advanced Menu > Audio Configuration

<table><tr><td colspan="2">Audio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>Audio Configuration
LPE Audio Support [Disabled]
Audio Controller [Enabled]
Azalia VCi Enable [Enabled]
Azalia Docking Support Enable [Disabled]
Azalia PME Enable [Enabled]
Azalia HDMI Codec [Enabled]</td><td>Select LPE Audio ACPI mode or PCI mode</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr></table>

Figure 4-9: BIOS Setup Advanced Menu > Audio Configuration

Table 4-27: Advanced Menu > Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LPE Audio Support</td><td>EnabledDisabled</td><td>Select LPE Audio ACPI mode or PCI mode</td></tr><tr><td>Audio Controller</td><td>EnabledDisabled</td><td>Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally Enabled</td></tr><tr><td>Azalia VCi Enable</td><td>EnabledDisabled</td><td>Enable/Disable Virtual Channel 1 of Audio Controller</td></tr><tr><td>Azalia Docking Support Enable</td><td>EnabledDisabled</td><td>Enable/Disable Azalia Docking Support of Audio Controller</td></tr><tr><td>Azalia PME Enable</td><td>EnabledDisabled</td><td>Enable/Disable Power Management capability of Audio Controller</td></tr><tr><td>Azalia HDMI Codec</td><td>EnabledDisabled</td><td>Enable/Disable internal HDMI codec for Azalia</td></tr></table>

# Advanced Menu > PCI\_PCIe Configuration

<table><tr><td rowspan="2">PCI/PCIe Configuration
► PCIe Chipset Settings
► PCI Subsystem Settings</td><td>PCI Express Configuration settings</td></tr><tr><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-10: BIOS Setup Advanced Menu > PCI\_PCIe Configuration

Advanced Menu > PCIe Configuration > PCIe Chipset Settings

Table 4-28: Advanced Menu > PCIe Configuration > PCIe Chipset Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Port x</td><td>EnabledDisabled</td><td>Enable or disable the PCI Express Port x in the chipset.</td></tr><tr><td>Hot Plug</td><td>EnabledDisabled</td><td>Enable or disable PCI Express hotplug.</td></tr><tr><td>Speed</td><td>AutoGen 2Gen 1</td><td>Configure PCIe port speed.</td></tr></table>

# Advanced Menu > PCIe Configuration > PCI Subsystem Settings

Table 4-29: Advanced Menu > PCIe Configuration > PCI Subsystem Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Latency Timer</td><td>32 PCI Bus Clocks</td><td>Value to be programmed into PCI latency timer register</td></tr><tr><td>PCI-X Latency Timer</td><td>64 PCI Bus Clocks</td><td>Value to be programmed into PCI-X latency timer register</td></tr><tr><td>VGA Palette Snoop</td><td>EnabledDisabled</td><td>Enables or Disables VGA palette registers snooping</td></tr><tr><td>PERR# Generation</td><td>EnabledDisabled</td><td>Enables or Disables PCI Device to Generate PERR#</td></tr><tr><td>SERR# Generation</td><td>EnabledDisabled</td><td>Enables or Disables PCI Device to generate SERR#</td></tr><tr><td>Above 4G Decoding</td><td>EnabledDisabled</td><td>Enables or Disables 64bit capable Devices to be Decoded in Above 4G Address Space (Only if System Supports 64 bit PCI Decoding)</td></tr><tr><td>SR-IOV Support</td><td>EnabledDisabled</td><td>If system has SR-IOV capable PCIe Devices, this option Enables or Disables Single Root IO Virtualization Support</td></tr></table>

# Advanced Menu > PCIe Configuration > PCI Subsystem Settings > PCI Express Settings

Table 4-30: Advanced Menu > PCIe Configuration > PCI Subsystem Settings > PCIe Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Relaxed Ordering</td><td>EnabledDisabled</td><td>Enables or Disables PCI Express device relaxed ordering.</td></tr><tr><td>Extended Tag</td><td>EnabledDisabled</td><td>If Enabled, allows device to use 8-bit tag field as a requester.</td></tr><tr><td>No Snoop</td><td>EnabledDisabled</td><td>Enables or Disables PCI Express device No Snoop option.</td></tr><tr><td>Maximum Payload</td><td>Auto</td><td>Set maximum payload of PCI Express device or allow system BIOS to select the value.</td></tr><tr><td>Maximum Read Request</td><td>Auto</td><td>Set Maximum Read Request Size of PCI Express Device or allow System BIOS to select the value</td></tr><tr><td>PCI Express Link Register Settings</td><td colspan="2">Info only</td></tr><tr><td>ASPM Support</td><td>DisabledAutoForce L0s</td><td>Set the ASPM Level:DISABLE - Disables ASPMAUTO - BIOS auto configureForce L0s - Force all links to L0s State</td></tr><tr><td>Extended Synch</td><td>EnabledDisabled</td><td>If ENABLED allows generation of Extended Synchronization patterns</td></tr><tr><td>Link Training Retry</td><td>Disabled235</td><td>Defines number of Retry Attempts software will take to retrain the link if previous training attempt was unsuccessful</td></tr><tr><td>Link Training Timeout (uS)</td><td>1000</td><td>Defines number of Microseconds software will wait before polling &#x27;Link Training&#x27; bit in Link Status register. Value range from 10 to 10000 uS</td></tr><tr><td>Unpopulated Links</td><td>Keep Link ONDisabled</td><td>In order to save power, software will disable unpopulated PCI Express links, if this option set to &#x27;Disable Link&#x27;</td></tr><tr><td>Restore PCIE Registers</td><td>EnabledDisabled</td><td>On non-PCI Express aware OS&#x27;s (Pre Windows Vista) some devices may not be correctly reinitialized after S3. Enabling this restores PCI Express device configurations on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume</td></tr></table>

# Advanced Menu > PCIe Configuration > PCI Subsystem Settings > PCI Express GEN 2 Settings

Table 4-31: Advanced Menu > PCIe Configuration > PCI Subsystem Settings > PCIe GEN 2 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Completion Timeout</td><td>DefaultShorterLongerDisabled</td><td>In device Functions that support Completion Timeout programmability, allows system software to modify the Completion Timeout value. 'Default' 50us to 50ms. If 'Shorter' is selected, software will use shorter timeout ranges supported by hardware. If 'Longer' is selected, software will use longer timeout ranges</td></tr><tr><td>ARI Forwarding</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type1 Configuration Request into a Type0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port</td></tr><tr><td>AtomicOp Requester Enable</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests only if Bus Master Enable bit is in the Command Register Set</td></tr><tr><td>AtomicOp Egress Blocking</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', outbound AtomicOp Requests via Egress Ports will be blocked</td></tr><tr><td>IDO Request Enable</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated</td></tr><tr><td>IDO Completion Enable</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', this permits setting the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests to be initiated</td></tr><tr><td>LTR Mechanism Enable</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', this enables the Latency Tolerance Reporting (LTR) Mechanism</td></tr><tr><td>End-End TLP Prefix Blocking</td><td>EnabledDisabled</td><td>If supported by hardware and set to 'Enabled', this function will block forwarding of TLPs containing End-End TLP Prefixes</td></tr><tr><td>PCI Express GEN2 Link Register Settings</td><td colspan="2">Info only</td></tr><tr><td>Target Link Speed</td><td>·Auto·Force to 2.5 GT/s·Force to 5.0 GT/s</td><td>If supported by hardware and set to 'Force to 2.5 GT/s' for Downstream Ports, this sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. When 'Auto' is selected HW initialized data will be used</td></tr><tr><td>Clock Power Management</td><td>·Enabled·Disabled</td><td>If supported by hardware and set to 'Enabled', the device is permitted to use CLKREQ# signal for power management of Link clock in accordance to protocol defined in appropriate form factor specification</td></tr><tr><td>Compliance SOS</td><td>·Enabled·Disabled</td><td>If supported by hardware and set to 'Enabled', this will force LTSSM to send SKP Ordered Sets between sequences when sending Compliance Pattern or Modified Compliance Pattern</td></tr><tr><td>Hardware Autonomous Width</td><td>·Enabled·Disabled</td><td>If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link width except width size reduction for the purpose of correcting unstable link operation</td></tr><tr><td>Hardware Autonomous Speed</td><td>·Enabled·Disabled</td><td>If supported by hardware and set to 'Disabled', this will disable the hardware's ability to change link speed except speed rate reduction for the purpose of correcting unstable link operation</td></tr></table>

# Advanced Menu > Baytrail Features

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
Advanced</td></tr><tr><td>LPSS &amp; SCC Devices Mode [ACPI mode]</td><td rowspan="3">LPSS &amp; SCC Devices Mode Settings</td></tr><tr><td>SCC Configuration
SCC eMMC Support [eMMC AUTO MODE]
SCC eMMC 4.5 DDR50 Support [Enabled]
SCC eMMC 4.5 HS200 Support [Disabled]
SCC SD Card Support [Enabled]</td></tr><tr><td>LPSS Configuration
LPSS I2C #1 Support [Enabled]
LPSS I2C #2 Support [Enabled]
LPSS HSUART #1 Support [Enabled]
LPSS HSUART #2 Support [Enabled]
LPSS SPISupport [Enabled]</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-11: BIOS Setup Advanced Menu > Baytrail Features

Table 4-32: Advanced > Baytrail Features

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LPSS &amp; SCC Devices Mode</td><td>ACPI modePCI mode</td><td>LPSS &amp; SCC Devices Mode Settings</td></tr><tr><td>SCC Configuration</td><td colspan="2">Info only</td></tr><tr><td>SCC eMMC Support</td><td>Enable eMMC 4.5 SupportEnable eMMC 4.41 SupporteMMC AUTO MODEDisabled</td><td>SCC eMMC Support Enable\Disable</td></tr><tr><td>SCC eMMC 4.5 DDR50 Support</td><td>EnabledDisabled</td><td>SCC eMMC 4.5 DDR50 Support Enable\Disable</td></tr><tr><td>SCC eMMC 4.5 HS200 Support</td><td>EnabledDisabled</td><td>SCC eMMC 4.5 HS200 Support Enable\Disable</td></tr><tr><td>SCC SD Card Support</td><td>EnabledDisabled</td><td>SCC SD Card Support Enable\Disable</td></tr><tr><td>LPSS Configuration</td><td colspan="2">Info only</td></tr><tr><td>LPSS I2C #1 Support</td><td>EnabledDisabled</td><td>LPSS I2C #1 Support Enable\Disable</td></tr><tr><td>LPSS I2C #2 Support</td><td>EnabledDisabled</td><td>LPSS I2C #2 Support Enable\Disable</td></tr><tr><td>LPSS HSUART #1 Support</td><td>EnabledDisabled</td><td>LPSS HSUART #1 SupportEnable\Disable</td></tr><tr><td>LPSS HSUART #2 Support</td><td>EnabledDisabled</td><td>LPSS HSUART #2 SupportEnable\Disable</td></tr><tr><td>LPSS SPISupport</td><td>EnabledDisabled</td><td>LPSS SPISupport Enable\Disable</td></tr></table>

# Advanced Menu > ACPI

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>ACPI Settings
Enable ACPI Auto Configuration [Disabled]
Enable Hibernation [Enabled]
ACPI Sleep State [S3 (Suspend to RAM)]
Lock Legacy Resources [Disabled]</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-12: BIOS Setup Advanced Menu > ACPI

Table 4-33: Advanced > ACPI

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ACPI</td><td colspan="2">Info only</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>EnabledDisabled</td><td>Enables or disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>EnabledDisabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend DisabledS3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the Suspend button is pressed.</td></tr></table>

Table 4-33: Advanced > ACPI

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Lock Legacy Resources</td><td>EnabledDisabled</td><td>Enables or Disables Lock of Legacy Resources</td></tr></table>

# Advanced Menu > Serial Port Console Redirection

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nAdvanced\nCOM1\nConsole Redirection (Disabled)\n► Console Redirection Settings\nConsole Redirection Enable or\nDisable.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/e0cf7e2af6d2850d8d0d00435ff609c60268b3f120bf0776f113d55d5600f1b9.jpg)

Figure 4-13: BIOS Setup Advanced Menu > Serial Port Console Redirection

Table 4-34: Advanced Menu > Serial Port Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings ▶</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

# Advanced Menu > Serial Port Console Redirection > Console Redirection Settings

Table 4-35: Advanced Menu > Serial Port Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0/COM1Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.ANSI: Extended ASCII char set.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Select data bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>Select parity.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Select number of stop bits.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Select flow control.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 combination key support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Legacy OS Redirection</td><td>80x2480x25</td><td>On legacy OSes, the number of rows and columns supported by redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS Post</td><td>Always EnabledBootLoader</td><td>The Settings specify if BootLoader is selected, then legacy console redirection is disabled before booting to legacy OS. Default value is Always Enable which means legacy console redirection is enabled for legacy OS.</td></tr></table>

# Advanced Menu > Thermal

<table><tr><td>Thermal Configuration Parameters
Critical Trip Point [Disabled]
Passive Trip Point [Disabled]</td><td>This value controls the temperature of the ACPI critical Trip Point in which the OS will shut the system off.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-14: BIOS Setup Advanced Menu > Thermal

Table 4-36: Advanced Menu > Thermal

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Critical Trip Point</td><td>Disabled85 C95 C</td><td>This value controls the temperature of the ACPI critical Trip Point - the point at which the OS will shut the system down.</td></tr><tr><td>Passive Trip Point</td><td>Disabled90 C80 C</td><td>This value controls the temperature of the ACPI passive Trip Point - the point at which the OS will begin throttling the processor.</td></tr></table>

# Advanced Menu > Security

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nMain\nIntel(R) TXE Configuration\nTXE (Enabled)\nTXE HMRFPO (Disabled)\nTXE Firmware Update (Enabled)\nTXE EOP Message (Enabled)\nTXE Unconfiguration Perform\nIntel(R) Anti-Theft Technology Configuration\nIntel(R) AT (Disabled)\nIntel(R) AT Platform PBA (Enabled)\nIntel(R) AT Suspend Mode (Disabled)\n++: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/d23565bc516cb50b12006177b389590cb98dfdaaf4ed713d323a3926398e8e1b.jpg)

Figure 4-15: BIOS Setup Advanced Menu > Security

Table 4-37: Advanced Menu > Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>TXE</td><td>EnabledDisabled</td><td></td></tr><tr><td>TXE HMRFPO</td><td>EnabledDisabled</td><td></td></tr><tr><td>TXE Firmware Update</td><td>EnabledDisabled</td><td></td></tr><tr><td>TXE EOP Message</td><td>EnabledDisabled</td><td>Send EOP Message Before Enter OS</td></tr><tr><td>TXE Unconfiguration Perform</td><td></td><td>Revert TXE settings to factory defaults</td></tr><tr><td>Intel(R) Anti-Theft Technology Configuration</td><td colspan="2">Info only</td></tr><tr><td>Intel(R) AT</td><td>EnabledDisabled</td><td>Enable/Disable BIOS AT Code from Runing</td></tr><tr><td>Intel(R) AT Platform PBA</td><td>EnabledDisabled</td><td>Enable/Disable BIOS AT Code from Runing</td></tr><tr><td>Intel(R) AT Suspend Mode</td><td>DisabledEnabled</td><td>Request that platform enter ATSuspend Mode - Only Available when AT Enrolled</td></tr></table>

# Advanced Menu > Miscellaneous

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc. Advanced</td></tr><tr><td>Miscellaneous
LVDS I2C Master [Dp2LVDS Controller]
Onboard Ethernet [Enabled]</td><td></td></tr><tr><td>25MHz clock on CAM_MCLK [Disabled]</td><td></td></tr><tr><td>Smart Battery Support [Enabled]
Select Smart Battery Controller [LTC1760]</td><td></td></tr><tr><td>High Precision Timer [Enabled]</td><td></td></tr><tr><td>Global SMI Lock [Enabled]
PCI Express Dynamic Clock Gating [Disabled]</td><td></td></tr><tr><td>Max TOLUD [Dynamic]</td><td>+:- Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-16: BIOS Setup Advanced Menu > Miscellaneous

Table 4-38: Advanced > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS I2C Master</td><td>• BMC Controller• Dp2LVDS Controller</td><td>Selects the master on the LVDS I2C Bus</td></tr><tr><td>Onboard Ethernet</td><td>• Enabled• Disabled</td><td>If Disabled: The onboard Ethernet controller is not available</td></tr><tr><td>25MHz clock on CAM_MCLK</td><td>• Enabled• Disabled</td><td>Enables a 25MHz clock output on SMARC CAM_MCLK</td></tr><tr><td>Smart Battery Support</td><td>• Enabled• Disabled</td><td>Enabled Smart Battery Support</td></tr><tr><td>Select Smart Battery Controller</td><td>• LTC1760• LTC4100</td><td>Select Smart Battery Controller</td></tr><tr><td>High Precision Timer</td><td>• Enabled• Disabled</td><td>Enable or disable the High Precision Event Timer</td></tr><tr><td>Global SMI Lock</td><td>• Enabled• Disabled</td><td>Enable or Disable SMI lock</td></tr><tr><td>PCI Express Dynamic Clock Gating</td><td>• Enabled• Disabled</td><td>Enable/Disable PCI Express Dynamic Clock Gating</td></tr><tr><td>Max TOLUD</td><td>Dynamic2 GB2.25 GB2.5 GB2.75 GB3 GB</td><td>Maximum Value of TOLUD</td></tr></table>

# 4.1.4 Security Menu

The Security menu allows you to set User and Administrator system passwords and to retrieve secure boot information.

![Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.\nMain Advanced Security Boot Save & Exit\nPassword Description\nIf ONLY the Administrator's password is set,\nthen this only limits access to Setup and is\nonly asked for when entering Setup.\nIf ONLY the User's password is set, then this\nis a power on password and must be entered to\nboot or enter Setup. In Setup the User will\nhave Administrator rights.\nThe password length must be\nin the following range:\nMinimum length 3\nMaximum length 20\nAdministrator Password\nUser Password\n► Secure Boot menu\nSet Administrator Password\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.](.lec-bts-50-1z173-1020-21/3f9615fff4467e3e390afe226fe035daee2f3f86a76a36a0cdca3f7bc90f285c.jpg)

Figure 4-17: BIOS Setup Security Menu

# Password Description

Table 4-39: Security Password

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>See description in Figure 4-17</td></tr><tr><td>User Password</td><td>Enter password</td><td>See description in Figure 4-17</td></tr><tr><td>Secure Boot menu ▶</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr></table>

# Security Menu > Secure Boot

Table 4-40: Security Menu > Secure Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Mode</td><td colspan="2">Setup</td></tr><tr><td>Secure Boot</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot</td><td>EnabledDisabled</td><td>Secure Boot can be enabled if:1. System running in User mode with enrolled Platform Key (PK)2. CSM function is disabled.</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode selector. &#x27;Custom&#x27; Mode enables users to change Image Execution policy and manage Secure Boot keys.</td></tr></table>

# 4.1.5 Boot

The Boot menu allows you to configure how your system will boot and select the storage location from which the system boot up will occur.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>Boot Configuration
Setup Prompt Timeout 0
Bootup NumLock State [On]</td><td></td></tr><tr><td>Quiet Boot [Enabled]
Fast Boot [Disabled]</td><td></td></tr><tr><td>CSM Configuration</td><td></td></tr><tr><td>Boot Option Priorities
Boot Option #1 [UEFI: U1-Generic F1...]
Boot Option #2 [UEFI: Built-in EFI ...]
Boot Option #3 [U1-Generic Flash Di...]</td><td></td></tr><tr><td>Add New Boot Option</td><td></td></tr><tr><td>Delete Boot Option</td><td></td></tr><tr><td>Number of seconds to wait for setup activation key.
65535(0xFFFF) means indefinite waiting.</td><td></td></tr><tr><td>+:- Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td><td></td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-18: BIOS Setup Boot Menu

# Boot Configuration

If more than one drive is attached to the LEC-BTS, you can select from the "Boot Configuration" screen the boot order in which the drives are scanned for a bootable OS image.

Table 4-41: Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Setup PromptTimeout</td><td>0</td><td>Number of seconds to wait for setup activation key.65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLockState</td><td>OnOff</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>EnabledDisabled</td><td>Enable or disables logo Quiet Boot option for OEM Logo function.</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect on BBS boot options.</td></tr><tr><td>CSM Configuration ▶</td><td>Submenu</td><td>CSM configuration: Enable/Disable, Option ROM execution settings, etc.</td></tr><tr><td>Boot Option Priorities</td><td colspan="2">Info only</td></tr><tr><td>Hard Drive BBSPriorities</td><td colspan="2">Info only</td></tr></table>

# Boot Configuration > CSM Parameters

Table 4-42: Boot Configuration > CSM Parameters

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Compatibility Support Module Configuration</td><td colspan="2">Info</td></tr><tr><td>CSM Support</td><td>EnabledDisable</td><td>CSM Support</td></tr><tr><td>CSM16 Module Version</td><td colspan="2">Info only</td></tr><tr><td>GataA20 Active</td><td>Upon RequestAlways</td><td>Upon Request – GA20 can be disabled using BIOS services.Always – do not allow disabling of GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>Option ROM Messages</td><td>Force BIOSKeep Current</td><td>Set display mode for Option ROM.</td></tr><tr><td>INT19 Trap Response</td><td>ImmediatePostponed</td><td>BIOS reaction on INT19 trapping by Option ROM:Immediate - execute the trap right away; Postponed – execute the trap during legacy boot.</td></tr><tr><td>Boot option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls legacy/UEFI ROM priority.</td></tr><tr><td>Option ROM execution</td><td colspan="2">Info only</td></tr><tr><td>Network</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and legacy storage OpROM.</td></tr><tr><td>Video</td><td>UEFI onlyLegacy only</td><td>Controls the execution of UEFI and legacy video OpROM.</td></tr><tr><td>Other PCI devices</td><td>UEFI onlyLegacy only</td><td>Determines OpROM execution policy for devices other than network, storage or video.</td></tr></table>

# 4.1.6 Save & Exit

Use the Save and Exit menu to save or discard BIOS setting changes, restore or save setting defaults, and retrieve certain override information.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2013 American Megatrends, Inc.
Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>Save Changes and Exit
Discard Changes and Exit
Save Changes and Reset
Discard Changes and Reset</td><td rowspan="3">Exit system setup after saving the changes.</td></tr><tr><td>Save Options
Save Changes
Discard Changes</td></tr><tr><td>Restore Defaults
Save as User Defaults
Restore User Defaults</td></tr><tr><td>Boot Override
UEFI: U1-Generic Flash Disk 8.07
UEFI: Built-in EFI Shell
U1-Generic Flash Disk 8.07</td><td rowspan="2">+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Launch EFI Shell from filesystem device
Reset System with ME disable ModeMEUD000</td></tr><tr><td colspan="2">Version 2.16.1242. Copyright (C) 2013 American Megatrends, Inc.</td></tr></table>

Figure 4-19: BIOS Setup Save and Exit Menu

Table 4-43: Save and Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>Yes No</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Yes No</td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Yes No</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Yes No</td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td colspan="2">Info only</td></tr><tr><td>Save Changes</td><td>Yes No</td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Yes No</td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td>Yes No</td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Yes No</td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Yes No</td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td colspan="2">Info only</td></tr></table>

# 4.2 SEMA functions

Under the management of the BMC chip (Board Management Controller), the SEMA utility (Smart Embedded Management Agent) provides system control and failure protection—counting, monitoring, and measuring hardware and software events, from which the SoC can trigger corrective commands. The optional SEMA Cloud utility not only controls local events on the module but system client events on the Internet of Things (IoT.) Refer to the following bullets for a list of SEMA functions.

▶ Total operating hours counter
Counts the time the module has been run in minutes.
▶ On-time minutes counter
Counts the seconds since last system start.
▶ Temperature monitoring of CPU and Board temperature
Minimum and maximum temperature values of CPU and board are stored in flash.
▶ Power monitor
Reads the current drawn by the board and reports the nominal operating voltage.
▶ Power cycles counter
▶ Boot counter
Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
▶ Watchdog Timer
Set / Reset / Disable Watchdog Timer.
▶ System Restart Cause
Power loss / Watchdog / External Reset.
▶ Flash area
1kB Flash area for customer data
▶ Protected Flash area
128 Bytes for Keys, ID's, etc. can be stored in a write- and clear-protectable region.
▶ Board Identify
Vendor / Board / Serial number

The SEMA Tools are available for Windows and Linux. SEMA functionality can also be used in applications. Refer to the SEMA software manual and technical manual on the ADLINK web site for more information.

# 4.2.1 Board Specific SEMA functions

# Voltages

The BMC of the LEC-BTS implements a Voltage Monitor and samples several Onboard Voltages. The Voltages can be read by calling the SEMA function, "Get Voltages". The function returns a 16-bit value divided in Hi-Byte (MSB) and Lo-Byte (LSB).

Table 4-44: BMC Voltage Monitor Values

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>---</td><td>---</td></tr><tr><td>1</td><td>+V1.0S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>2</td><td>+V1.2S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>3</td><td>+V1.8S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>4</td><td>+V3.3S</td><td>(MSB&lt;&lt;8 + LSB) * 1.100 * 3.3 / 1024</td></tr><tr><td>5</td><td>+V1.5S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>6</td><td>+V5.0A</td><td>(MSB&lt;&lt;8 + LSB) * 1.833 * 3.3 / 1024</td></tr><tr><td>7</td><td>(MAINCURRENT)</td><td>Use Main Current Function</td></tr></table>

# Main Current

The BMC of the LEC-BTS implements a Current Monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in Hi-Byte (MSB) and Lo-Byte (LSB). These four values represent the last four currents drawn by the board. The values are sampled every 250ms. The order of the four values is NOT in relationship to time. The access to the BMC may increase the drawn current of the whole system. In this case, you still have three samples without the influence of the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) * 8. 0 6 \mathrm{mA}
$$

# TS#-Events

TS# is activated by a temperature sensor when a device reaches its critical temperature and released when the device is back in its normal temperature range. This counter gives the user information about temperature or cooling issues. This counter is cleared when the system is removed from power. The LEC-BTS only monitors the board temperature and does not support TS#-Events.

# Exception Blink Codes

In the case of an error, the BMC shows a blink code on the STATUS-LED (LED1). This error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash storage and is cleared when the power is removed. Therefore, the “Clear Exception Code”-Command is not supported.

Table 4-45: Blink Codes

&lt;table&gt;<tr><td>Exception Blink Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S3</td></tr><tr><td>5</td><td>RESET_FAIL</td></tr><tr><td>6</td><td></td></tr><tr><td>7</td><td>POWER_FAIL</td></tr><tr><td>8</td><td>LOW_VIN</td></tr><tr><td>9</td><td>NO_PWRGD_ATX</td></tr><tr><td>10</td><td>NO_PWRGD_1V0S</td></tr><tr><td>11</td><td>NO_PWRGD_1V2S</td></tr><tr><td>13</td><td>NO_PWRGD_1V8S</td></tr><tr><td>14</td><td>NO_PWRGD_3V3S</td></tr><tr><td>15</td><td>NO_PWRGD_1V5S</td></tr></table>

# BMC Flags

The BMC Flags register returns the last detected exception code since power up.

# 4.3 Watchdog Timer

The LEC-BTS features three separate Watchdog Timers. One of them is integrated in the SoC and two are provided by the BMC (managed by the SEMA).

The SoC Watchdog can be configured in the BIOS or by programming the Watchdog registers. If this function is used by user application, the application has to provide all logging functionality if desired.

The BMC Watchdog activations are caused by under voltage protection. The Watchdog LED flashes after restart but only if the power supply reaches 4.2V.

# 4.4 Temperature Sensors

The LEC-BTS supports two temperature sensor functions. One is offered from the SoC and one from a dedicated chip (Texas Instruments LM73) on the board.

The SoC temperature sensors can be configured by programming the appropriate SoC registers. Refer to the Thermal Management chapter in the Atom E3800 Intel processor data sheet for more information. The on-board LM73 temperature sensor is managed by the BMC and is configured through the SEMA utility.

# 4.5 Programming Examples

Programming examples can be provided based on a Linux operating system, upon request.

# Appendix A Technical Support

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in Table A-1 below. Requests for support through Ask an Expert are given the highest priorities, and usually will be addressed within one working day.

ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the ADLINK web site at http://askanexpert.adlinktech.com. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called "My ADLINK", unique to you with access to exclusive services and account information.

▶ Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to the My Question area where you can check status, update your request, and access other features.
▶ Download Service – This service is also free and available 24 hours a day using the web site link shown in Table A-1. For certain downloads such as technical documents and software, you must register online before you can log in to this service.

Table A-1: Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://askanexpert.adlinktech.com</td></tr><tr><td>Web Site</td><td>https://emb.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Zhonghe DistrictNew Taipei City 235, Taiwan新北市中和區建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech ParkPudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.comADLINK Technology GmbHAddress: Hans-Thoma-Strasse 11D-68163 Mannheim, GermanyTel: +49-621-43214-0Fax: +49-621 43214-30Email: emea@adlinktech.comPlease visit the contact page using the web site link shown above or information on how to contact the ADLINK regional office nearest you.</td></tr></table>
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