# LEC-BW

# (Low Energy Computer On Module)

Technical Reference

P/N 50-1Z206-1010

Rev 2.00

![The image displays a logo consisting of a stylized, four-lobed shape resembling a four-leaf clover or cross. The shape features a horizontal color gradient that transitions from a yellowish-green on the left side to a brighter lime green on the right. In the center of the green shape is a white square. There is no text present in the image.](.lec-bw-50-1z206-1010-200-en/b1865bc94e97da67ddd351ebc7c02772681eb24792c41502fccc742656b1cc08.jpg)

SMARC

![Close-up of a green printed circuit board with various electronic components and gold contacts (no readable text or symbols)](.lec-bw-50-1z206-1010-200-en/546a445de683682338cd4a10612ec682c0cb0720192f42cce54c6dbe16600a2b.jpg)

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Date</td><td>Description of Change(s)</td></tr><tr><td>1.00</td><td>06/08/2016</td><td>Initial Release</td></tr><tr><td>2.00</td><td>12/02/2016</td><td>Removed Standby voltage from Table 1-3 on page 4; added mounting information to cooling section in Chapter 1; added Ordering Information to Chapter 1</td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr></table>

# © Copyright 2016 ADLINK Technology, Incorporated

www.adlinktech.com

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Important Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this manual for future reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);
 Make sure to use recommended voltage and power source settings;
 Always install and operate equipment near an easily accessible electrical socketoutlet;
 Secure the power cord (do not place any object on/over the power cord);
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
 If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![The image displays a white document icon with a folded top-right corner and faint horizontal lines representing text. A large, bold red checkmark is superimposed over the left side of the document.](.lec-bw-50-1z206-1010-200-en/cb27a54755ac5d949fd1a51fe88619963b1e78008a46e516cefeb21ccc5c0419.jpg)
NOTE:

This information adds clarity or specifics to text and illustrations.

![This image features a standard warning sign. It consists of a yellow triangle with a black border. Inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION' is printed in black capital letters.](.lec-bw-50-1z206-1010-200-en/94df53eb803e9414999d570728eb538aea3eef90ca3b7532472dd5fc8fb4cec4.jpg)

This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image features a triangular warning sign with a red gradient background that is darker at the top and lighter at the bottom, enclosed by a thin black border. Centered inside the triangle is a large white exclamation mark. Below the triangle, on a white background, the word 'WARNING' is printed in bold, black, uppercase letters.](.lec-bw-50-1z206-1010-200-en/da0626593dd8ad60c7250fa29784666a75eff361548dc6dc30f908a42230e8d3.jpg)

This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Table of Contents

# 1 Product Overview.....

1.1 Description.
1.2 Features.. 2
1.3 Block Diagram.. 3
1.4 Ordering Information . 4
1.5 Specifications. 4

1.5.1 Physical 4
1.5.2 Electrical . 4
1.5.3 Environmental. ..5
1.5.4 Mechanical . . 5
1.5.5 Power.. .6
1.5.6 Cooling .. 6

1.6 Getting Started.. 8

# 2 Hardware ... . 11

2.1 Major Components (ICs).. 11
2.2 Connectors, Switches, and LEDs . . 12
2.3 Component Features . . 14

2.3.1 CPU . ..14
2.3.2 SDRAM . . 14
2.3.3 I211 LAN Controller .. . 14
2.3.4 PTN3460i eDP-to-LVDS Converter . .. 14
2.3.5 PCA9535A GPIO Expander.. ..14
2.3.6 SMBus Slave Addresses . .. 15

# 3 Interfaces . . 17

3.1 Display Interfaces .. 17

3.1.1 18/24-Bit LVDS LCD (Primary Display) . ..17
3.1.2 HDMI (Secondary Display) . ..18
3.1.3 HDMI/Display Port (DP) [Third Display].. ..18

3.2 Camera MIPI-CSI... 19
3.3 Audio (HDA)... . 20
3.4 PCI Express (PCIe)... . 20
3.5 Gigabit Ethernet . . 20
3.6 USB Ports ... .. 21

3.6.1 USB 2.0 . ..21
3.6.2 USB 3.0 . ..21

3.7 SATA... . 21
3.8 I2C Bus . .. 21
3.9 SPI . .. 21
3.10 Serial (UART)... .. 21
3.11 SD/SDIO Interface . .. 21
3.12 eMMC Interface ... .. 21
3.13 GPIO .. . 22
3.14 LPC Debug Interface . . 22
3.15 SMARC Interface Signals . . 23

3.16 Debug (DB40) Connector Signals. 31

# 4 Utilities .... 33

4.1 BIOS . 33

4.1.1 Starting the BIOS Setup Utility .. . 33
4.1.2 Main Menu . . 34
4.1.3 Advanced Menu ... . 39
4.1.4 Security Menu .. . 56
4.1.5 Boot Menu.. . 58
4.1.6 Save & Exit Menu... . 60

4.2 SEMA functions... 61

4.2.1 Board Specific SEMA functions . 62

4.3 Watchdog Timer.. 63
4.4 Temperature Sensors ...... 63
4.5 Programming Examples. 63

# Appendix A Technical Support .. .65

# 1 Product Overview

# 1.1 Description

The LEC-BW Computer-On-Module (COM) combines the SMARC® 1.1 standard with the Intel® Pentium® and Celeron® N-series System-on-Chip (SoC), providing an ideal solution for low power consumption and high performance requirements. The module provides the high integration, high performance, low power, and ruggedness favored by Internet-of-Things (IoT) applications such as retail transactional clients, digital signage, and in-vehicle infotainment systems.

The LEC-BW module utilizes the Intel N3000 series SoC, which is based on the new Intel Architecture and is manufactured on Intel's industry-leading, tri-gate 14nm process. The module primarily targets entry-level 2-in-1 devices, lap tops, desktops, and all-in-one PCs and supports contemporary, high-bandwidth interfaces such as Ultra HD HDMI, PCI Express Gen2, Gigabit Ethernet, USB 3.0, SATA Gen3, and a state-of-the-art HD Audio interface. The module generates its own LVDS (18/24bit), TMDS, and Display Port video signals using DDI output from the SoC.

Two SPI Flash chips implement a fail-safe BIOS, allowing the user to boot the module even if current BIOS settings have corrupted the system.

Under the management of the BMC chip (Board Management Controller), the SEMA utility (Smart Embedded Management Agent) provides system control, security, and failure protection—counting, monitoring, and measuring hardware and software events, and using the SMBus to send corrective commands to the SoC. The optional SEMA Cloud utility not only controls local events on the module but system client events on the IoT.

# 1.2 Features

# CPU

Intel Pentium and Celeron N-Series, x86 dual-core or quad-core SoC (System On Chip) with integrated memory, graphics, and I/O. See Intel website.

 N3710 6W TDP, Pentium Quad-Core/2.56GHz burst freq./1600 MT/s /Gfx 700MHz
 N3160 6W TDP, Celeron Quad-Core/2.24GHz burst freq./1600 MT/s/Gfx 640MHz
 N3060 6W TDP, Celeron Dual-Core/2.48GHz burst freq./1600 MT/s/Gfx 600MHz
 N3010 4W TDP, Celeron Dual-Core/2.24GHz burst freq./1600 MT/s/Gfx 600MHz
 x5-E8000 5W TDP, Atom Quad-Core/2.00GHz burst freq./1600 MT/s/Gfx 320MHz

NOTE: Other CPU SKUs can be made available on request.

 Memory
 Up to 8GB non-ECC, unbuffered soldered, DDR3L
 1600MHz
 Single channel

 Interface Standard

 SMARC, board-to-board, Rev 1.1

 SATA

 Two 6Gb/s, Gen 3 ports

 Advanced Host Controller Interface (AHCI)

 USB

 Four USB 2.0 host ports

 One USB 3.0 host port on AFB

 Ethernet

 Single-port, gigabit Ethernet controller

 Integrated GbE MAC, PHY, and MDI ports

 10T/100TX/1000T signals using the PCIe x1 bus

 Serial UART

 One high-speed, 2-wire port

 One high-speed, 4-wire port

 Base frequency 50MHz

 I2C

 One I2C bus

 Four I2C ports

 One SMBus

 SPI

 Two internal SPI controllers

 Two SPI flash devices for BIOS storage

 Video

 Display Port/HDMI

 LVDS

 Audio

 One HDA (High Definition Audio) interface (through I2S port 2)

 Camera

 Two MIPI-CSI camera interfaces

 Camera, CSI0 (2 lanes)

 Camera, CSI1 (4 lanes)

# 1.3 Block Diagram

![This diagram depicts the architecture of an **Intel Braswell M/D SoC**, detailing its connections to various peripherals and interfaces.\n\n**Central Component:**\n*   Intel Braswell M/D SoC\n\n**Left Side (314-pin Golden finger):**\nThis vertical block interfaces with the SoC via the following connections and intermediate blocks (listed top-to-bottom):\n*   **Custom option:** DDI0 (HDMI/DP)\n*   **LVDS 18/24bit SC/DC** connects to block **LVDS NXP**, which connects via **DDI1**\n*   **DDI2 (HDMI)**\n*   **HDA**\n*   **4x I2C (some reserved)**\n*   **12x GPIO (4x CSI, 1x HDA)** connects to block **GPIO PCA9535A**, which connects via **SMBus**\n*   **GbE** connects to block **LAN i211**, which connects via **PCIe x1**\n*   **PCIe x1, PCIe port 1,2,3**\n*   **1x eMMC (8bit)**\n*   **2x Camera (MIPI CSI 4L/2L)**\n*   **2x UART (1x RTS/CTS)**\n*   **4x USB2.0 host**\n*   **USB3.0 host on AFB**\n*   **SATA0**\n*   **SATA1 on AFB**\n*   **1x SDIO (4bit)**\n*   **Power Management**\n*   **BOOT Select** connects to block **BMC**, which connects via **SMBus**\n*   Block **SPI-BIOS** (connected to BMC) connects via **SPI**\n*   **1x SPI**\n*   **1x SPI**\n\n**Right Side Connections:**\n*   **DDR3L 1600MHz** connects to block **DDR3L Memory down 1/2/4/8GB**\n*   Block **PMIC IDT P9180A**\n*   **LPC, SPI** connects to block **Debug Connector for DB40**\n\n**Footer Text:**\n*   LEC-BW_blk_diag_c](.lec-bw-50-1z206-1010-200-en/9a4c24dc57835ff562358408414479860904a0fb26b98c85d65b3ac1ac53f2a0.jpg)

Figure 1-1: Module functional block diagram

# 1.4 Ordering Information

Table 1-1: LEC-BW Models

<table><tr><td>Model Number</td><td>Description</td></tr><tr><td>LEC-BW42-4G-CT</td><td>SMARC short size module with Intel Pentium N3710, quad core, 4GB DDR3L, 0°C to 60°C</td></tr><tr><td>LEC-BW41-4G-CT</td><td>SMARC short size module with Intel Celeron N3160, quad core, 4GB DDR3L, 0°C to 60°C</td></tr><tr><td>LEC-BW22-2G-CT</td><td>SMARC short size module with Intel Celeron N3060, dual core, 2GB DDR3L, 0°C to 60°C</td></tr><tr><td>LEC-BW21-2G-CT</td><td>SMARC short size module with Intel Celeron N3010, dual core, 2GB DDR3L, 0°C to 60°C</td></tr><tr><td>LEC-BW-HS</td><td>Heat spreader for LEC-BW</td></tr><tr><td>LEC-BW-HS2</td><td>Passive heatsink for LEC-BW (requires LEC-BW heat spreader)</td></tr></table>

# 1.5 Specifications

# 1.5.1 Physical

Table 1-2 lists the physical dimensions of the module.

Table 1-2: Weight and Footprint Dimensions

<table><tr><td>Dimension</td><td>Measurement</td><td rowspan="6">Overall height is measured from the upper board surface to the top of the highest permanent component on the upper board surface. This measurement does not include the cooling solution.</td></tr><tr><td>Weight</td><td>0.020 kg[0.089 kg with heat spreader]</td></tr><tr><td>Height (overall)</td><td>2.29mm</td></tr><tr><td>Board thickness</td><td>1.20mm</td></tr><tr><td>Width</td><td>50.00mm</td></tr><tr><td>Length</td><td>82.00mm</td></tr></table>

# 1.5.2 Electrical

Table 1-3 specifies the electrical characteristics of the module.

Table 1-3: Electrical Specifications

<table><tr><td>Parameter</td><td>Value</td></tr><tr><td>Voltage Input</td><td></td></tr><tr><td>Standard</td><td>+3V DC min to +5.25V DC max, +/-5%, =/- 50mV ripple</td></tr><tr><td>RTC</td><td>3.0V, 2.0V to 3.3V (battery), +/- 20mV ripple</td></tr><tr><td>Power States</td><td>C0, C1, C2 processor power statesS0 (active), S1 (sleep), S2 (extended sleep), S3 (standby [suspend to RAM]), S4 (suspend-to-disk), and S5 (soft-off and wake-on-LAN) system power states</td></tr></table>

# 1.5.3 Environmental

Table 1-4 defines the environmental conditions under which the module is qualified to operate and to be stored.

Table 1-4: Temperature and Humidity

<table><tr><td>Parameter</td><td>Temperature</td></tr><tr><td>Temperature</td><td></td></tr><tr><td>Standard</td><td>▶ 0°C to +60°C</td></tr><tr><td>Storage</td><td>▶ -55°C to 85°C</td></tr><tr><td>Humidity</td><td></td></tr><tr><td>Operating</td><td>▶ 5% to 90% relative humidity, non-condensing</td></tr><tr><td>Non-operating</td><td>▶ 5% to 95% relative humidity, non-condensing</td></tr></table>

Table 1-5 provides shock and vibration tests performed on the board.

Table 1-5: Shock and Vibration

<table><tr><td>Parameter</td><td>Result</td></tr><tr><td>Shock Test</td><td>MIL-STD-202F, Method 213B, Table 213-I, Condition A</td></tr><tr><td>Random Vibration Test</td><td>MIL-STD-202F, Method 214A, Table 214-I, Condition D</td></tr></table>

Table 1-6 presents the average times between system failures.

Table 1-6: Mean Time Between Failures

<table><tr><td>Parameter</td><td>Value</td></tr><tr><td>MTBF at 40°C</td><td>490,000 hrs (according to MIL calculation)</td></tr></table>

# 1.5.4 Mechanical

Figure 1-2 provides the mechanical dimensions of the LEC-BW.
![82.00\n21.37\n4.00\n74.00\nØ 6.00\nØ 2.70\n50.00\n25.16\n20.45\n34.00\n12.00\n31.11\n39.00\n52.00\n82.00\nLEC-BW_mech_dmn_a\n1.30\n4.66](.lec-bw-50-1z206-1010-200-en/2b8ad0615a893a5dd97e1eb5aff95c6c4bbb1a682204fa2ae581f3295fa86f12.jpg)

Figure 1-2: Mechanical dimensions (top side)

# 1.5.5 Power

Table 1-7 provides the power requirements for this module under certain load configurations.

Table 1-7: Power Supply Requirements

<table><tr><td>Parameter</td><td>6W, N3710 SoC with 4GB SDRAM, 2M cache up to 2.56 GHz</td><td>6W, N3160 SoC with 4GB SDRAM, 2M cache up to 2.24 GHz</td><td>6W, N3060 SoC with 2GB SDRAM, 2M cache up to 2.48 GHz</td><td>4W, N3010 SoC with 2GB SDRAM, 2M cache up to 2.24 GHz</td><td>5W, x5-E8000 Atom SoC with 4GB SDRAM, 2M cache up to 2.00 GHz</td></tr><tr><td>Input Type</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td><td>Regulated DC voltage</td></tr><tr><td>Typical Idle Current and Power (EIST enabled; 500GB SSD; under Windows 7)</td><td>0.45A (2.25W) @ 5V</td><td>0.42A (2.10W) @ 5V</td><td>0.45A (2.25W) @ 5V</td><td>0.45A (2.25W) @ 5V</td><td>0.45A (2.25W) @ 5V</td></tr><tr><td>Typical Operating Mode Current and Power (EIST enabled; 500GB SSD; under Windows 7)</td><td>1.25A (6.25W) @ 5V</td><td>1.08A (5.04W) @ 5V</td><td>0.98A (4.90W) @ 5V</td><td>0.93A (4.65W) @ 5V</td><td>1.05A (5.25W) @ 5V</td></tr><tr><td>Maximum Operating Mode Current and Power (EIST enabled; 500GB SSD; under Windows 7; Intel TAT tool v5.0.1022)</td><td>4.06A (20.30W) @ 5V</td><td>3.15A (15.75W) @ 5V</td><td>2.70A (13.50W) @ 5V</td><td>2.66A (13.30W) @ 5V</td><td>2.26A (11.30W) @ 5V</td></tr><tr><td>System S3 mode (EIST enabled; 500GB SSD; under Windows 7)</td><td>0.13A (0.65W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.13A (0.65W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td></tr><tr><td>System S4 mode (EIST enabled; 500GB SSD; under Windows 7)</td><td>0.12A (0.60W) @ 5VSB</td><td>0.11A (0.55W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.11A (0.55W) @ 5VSB</td></tr><tr><td>System S5 mode with ECO enabled (EIST enabled; 500GB SSD; under Windows 7)</td><td>0.12A (0.60W) @ 5VSB</td><td>0.11A (0.55W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.12A (0.60W) @ 5VSB</td><td>0.11A (0.50W) @ 5VSB</td></tr></table>

# 1.5.6 Cooling

The LEC-BW is designed to operate at its maximum CPU speeds and requires a thermal solution to cool the CPU. ADLINK offers a heat spreader and a passive heatsink (separate order numbers) for cooling. The heatsink can be used for module evaluation. If a custom heatsink is used, it is recommended to connect it to the ADLINK heat spreader. This facilitates future module upgrades without the need to re-design the custom heatsink.

There is a separate order number for a heat spreader, which can be mounted on the module. The heat spreader provides a neutral plane to connect a custom heatsink solution. A passive heat sink is available for customer lab evaluation. This heatsink must be mounted on top of the heat spreader. If you want to use the heatsink, it is mandatory to also use the heat spreader.

![Heatsink\nHEAT\nSpreader\nLEC-BW](.lec-bw-50-1z206-1010-200-en/466bbd15eec9b09188fe3b88df7fa6d9f5d7ea86e6e4393e8f490eb70449603d.jpg)

Figure 1-3: Heatsink, Heat Spreader, Module Assembly.

# Cooling Solution Assembly

Use the following four steps to install the heat spreader and heatsink to the LEC-BW.

![XR-HL_38x14x2.5mm\nPK95_15x15x0.8mm\nXR-HL_14x12x2.5mm](.lec-bw-50-1z206-1010-200-en/f26784423c7fa4012b087c76d4db94d3bfca9145db7fd0855b31ce53d103e5b7.jpg)

Remove protective membranes from thermal pads on the heat spreader

![33-01107-0110*4pcs\nTop Side of\nHeat Spreader](.lec-bw-50-1z206-1010-200-en/3bd2af077a0ef1ca0f869f3838cf13efd46e714d073cb8ef5c28bb29ee67730d.jpg)

Mount heat spreader onto module using four M2.5x11 mounting screws

![33-01008-0080*1pcs\nBottom Side\nof LEC-BW](.lec-bw-50-1z206-1010-200-en/fcf1b22b59c6e50d14fab2f85890860daa3f2e682e92e63109438c32405973de.jpg)

Instal one M2.5x8 mounting screw to the bottom side of the module

![3D technical illustration of a heat sink component with cooling fins and mounting holes (no text or symbols)](.lec-bw-50-1z206-1010-200-en/2e555ad08b1c8a0beaf64445a6722e74c67b32b902a4211356775ed181a5fa5b.jpg)

Remove protective membranes from thermal pads on the heatsink and mount to the heat spreader using four M3x6 mounting screws

# 1.6 Getting Started

Mount the LEC-BW to the carrier as illustrated in Figure 1-4, which provides a profile view of the module mounted to the carrier with dimensions.

![5.7mm Min\n1.5mm Min\nTOP Side\nComponent 3mm Max\nModule PCB 1.2mm\nBOT Side\nComponent 1.3mm Max\nCarrier Connector\nCarrier PCB 1.6mm Typ](.lec-bw-50-1z206-1010-200-en/35eb4ff3aad5c40683a0ac7dd259e7bc98e8a1e416875f87c960a79cf4ec78fd.jpg)

Figure 1-4: SMARC module mounting dimensions (profile)

![This image features a white document icon with a folded upper-right corner. A large red checkmark is superimposed on the top right side of the document.](.lec-bw-50-1z206-1010-200-en/c0ed645292d315c96c08b584369fb60885bfc00bb710d218489642b2e1fbdd3f.jpg)
NOTE:

ADLINK strongly recommends plastic spacers instead of metal spacers for mounting the board. Metal spacers create the possibilities of short circuits with the components located around the mounting holes, which can ruin the board.

![The image displays a vertical yellow triangular warning sign with a black border. Centered within the triangle is a black exclamation mark.](.lec-bw-50-1z206-1010-200-en/989e539c6262e6da4ae8be691faf65c55d14e504a6ccd06dfba27a76b7700eb8.jpg)
CAUTION:

Be sure to observe the EMC security measures. Make sure you are always at the same potential as the module.

![The image displays the upper portion of a yellow triangular warning sign with a black border. Centered inside the triangle is a black exclamation point (!). The background surrounding the sign is white.](.lec-bw-50-1z206-1010-200-en/8c9a0e6f2f2ebaac7b23811b32495c14ef918bec4aa4d64c90013ed86d582dea.jpg)
CAUTION

Never connect or disconnect peripherals like HDDs while the power supply is connected and switched on.

Use the cable set provided in the ADLINK Technology starter kit to connect the LEC-BW to a display. Connect a USB keyboard or mouse to the carrier. Use the SATA cable to connect the hard disk. Make sure that the pins match their counterparts correctly and are not twisted. If you plan to use additional peripherals, connect them to the appropriate headers or connectors on the carrier.

Connect a power supply to the power connector on the carrier and switch on the power.

![The image displays a white document icon with a folded upper-right corner. Inside the document area, several faint horizontal gray lines represent text. Superimposed over the left side of the document is a large red checkmark that features a gradient, transitioning from a darker red at the top to a lighter red at the bottom.](.lec-bw-50-1z206-1010-200-en/a52757072470256b8b9993b9e4dc7746a355f588bfbe928c9762a53a84bfe149.jpg)
NOTE:

Observe the minimum voltage values for the standard peripherals mentioned. For additional peripherals, make sure enough power is available. The system will not work if there is not enough supply current for all your devices.

The display shows the BIOS messages. If you want to change the standard BIOS settings, press the &lt;DEL&gt; key to enter the BIOS setup menus. See Chapter 4 for setup details.

If you need to load the BIOS default values, they can be automatically loaded at boot time.

The LEC-BW boots from CD drives, USB sticks, hard disks, or µSD-Cards. Provided that any of these is connected and contains a valid operating system image, the display then shows the boot screen of your operating system.

The LEC-BW needs adequate cooling measures depending on the desired operating temperature range. Using the board without cooling could damage the board permanently.

# 2 Hardware

This chapter describes the major integrated circuits (ICs) and interface connectors and headers on the module. The third section of this chapter further describes the major ICs including the manufacturers’ model numbers.

# 2.1 Major Components (ICs)

Table 2-1 lists the major integrated circuits on the LEC-BW, including a brief description of each IC. Figure 2-1 and Figure 2-2 show the locations of the major ICs.

Table 2-1: Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U1)</td><td>Intel part numbers</td><td>N3710 Pentium (quad-core, 6W, 2.56GHz burst frequency)N3160 Celeron (quad-core, 6W, 2.24GHz burst frequency)N3060 Celeron (dual-core, 6W, 2.48GHz burst frequency)x5-E8000 Atom, (quad-core, 5W, 2.00GHz burst frequency)</td><td>N-series, 14nm SoC (System on Chip) with Intel Architecture</td><td>Integrates Processor Core, Graphics / Memory Hub, and I/O Hub</td></tr><tr><td>Ethernet Controller (LU1 on bottom side; see Figure 2-2)</td><td>Intel</td><td>WGI211AT SLJXZ</td><td>Single-port Gigabit Ethernet controller</td><td>Integrates GbE MAC, PHY, and MDI for standard 10T/100TX/1000T Ethernet signals using the PCIe x1 bus</td></tr><tr><td>BMC [Board Management Controller] (BU1)</td><td>Texas Instruments</td><td>TM4C123BH6ZRB</td><td>Micro controller for board functions including Watchdog Timer, LVDS control, system control, and failure protection</td><td>Controls dual BIOS and SEMA API through the SMBus</td></tr><tr><td>SPI Flash (U13 and U14)</td><td>Winbond</td><td>W25Q64FVSSIG TR</td><td>Serial Peripheral Interface Flash Memory chip (for firmware)</td><td>Stores BIOS 0 and BIOS 1 in Flash Memory</td></tr><tr><td>DDR3L SDRAM (MD1, MD2, MD3, MD4, MD5, MD6, MD7, MD8 [MD2, MD3, MD6, and MD7 on bottom side; see Figure 2-2])</td><td>Micron</td><td>MT41K126M8DA-125 (1GB model)MT41K256M8DA-125 (2GB model)MT41K512M8DA-125 (4GB model)MT41K1G4I (8GB model)</td><td>On-board DDR3L, 1.35V, non-ECC system memory4Gb, 8x 126Mx84Gb, 8x 256Mx84Gb, 8x 512Mx84Gb, 8x 1Mx8</td><td>Provides high-speed data transfer</td></tr></table>

Key:
U13 - BIOS 0
U14 - BIOS 1
BU1 - BMC
MD1 - DDR3L SDRAM
MD4 - DDR3L SDRAM
MD5 - DDR3L SDRAM
MD8 - DDR3L SDRAM
![MD4\nMD5\nMD8\nBU1\nU14\nU13\nMD1\nU1\nLEC-BW_top_comp_a](.lec-bw-50-1z206-1010-200-en/1d24fddf26556a024e15d536025f66adfb8a2df7543c0b096654f9a6c229083e.jpg)

Figure 2-1: Component Locations (Top Side)

MD2 - DDR3L SDRAM
MD3 - DDR3L SDRAM
MD6 - DDR3L SDRAM
MD7 - DDR3L SDRAM
![MD7 MD6 MD2\nMD3\nLU1\nLEC-BW_bod_comp_a](.lec-bw-50-1z206-1010-200-en/28d982cf0632f05e544dd66fad798733a5f7e2ec4c2e964f005560c2313047cb.jpg)

Figure 2-2: Component Locations (Bottom Side)

# 2.2 Connectors, Switches, and LEDs

Table 2-2 describes the connectors, switches, and LEDs shown in Figure 2-3 and Figure 2-4.

Table 2-2: Module Connector Description

<table><tr><td>Connector#</td><td>Board Access</td><td>Description</td></tr><tr><td>CN1</td><td>Top</td><td>40-pin, DB40 Front-Flip connector for debug card (Molex, 502790-4091)</td></tr><tr><td>GF1 - SMARC Primary and Secondary (P and S)</td><td>Top/Bottom</td><td>314-pin, MXM edge connector for Memory, Video, and I/O functions</td></tr><tr><td>LED1</td><td>Top</td><td>Blue LED indicating system status activities for HW Reset, SW Reset, Power Up, Power Down, Reset Button, and Power Button</td></tr><tr><td>LED2</td><td>Top</td><td>Green LED for Power On in S0 state, controlled by SLP_S3#</td></tr><tr><td>LED3</td><td>Top</td><td>Red LED for Watchdog time out, driven by SEMA and cleared by software or reset button</td></tr><tr><td>SW1</td><td>Top</td><td>4-pin dip switch forSetting BIOS Boot (1=Boot from SPI1, 4=Boot from SPI0 [default])Selecting BIOS Mode (2=Failsafe BIOS, 3=Normal BIOS [default])Switch Default Settings&lt;img src="images/f4e637361fc1f8067e680a1cd5eb90a755e1d27eda53a414d4e646f3323fae68.jpg"/&gt;</td></tr></table>

![Key:\nCN1 - DB40 Debug\nSW1 - BIOS Select\nGF1 Primary - SMARC MXM Primary\nLED1 - System Status (Blue)\nLED2 - Power (Green)\nLED3 - WDT (Red)\n▲ - Pin 1\nCN1\nSW1\nLED1\nLED2\nLED3\nP1 P74 P75 P156\nGF1 Primary\nLEC-BW_top conn_b](.lec-bw-50-1z206-1010-200-en/8ccbafd524bca4deb5271299ebcf7caa6c63e1b847f8151617328fbab7f363ac.jpg)

Figure 2-3: Connector Locations (Top Side)

![Key:\nGF1 Secondary - SMARC MXM Secondary\n- Pin 1\nS158 S76 S75 S1\nGF1 Secondary\nLEC_BW_bot_comp_a](.lec-bw-50-1z206-1010-200-en/18f23124e0287f9aa2ee2bea236ddfa31b9b622506d855b3fc38eedc157718e1.jpg)

Figure 2-4: Connector Locations (Bottom Side)

# 2.3 Component Features

This section further describes the supported features of the LEC-BW major, on-board hardware components.

# 2.3.1 CPU

The LEC-BW product family offers the following versions of the Intel Pentium and Celeron N-Series CPU, System-on-Chip (SoC): the N3710 Pentium (Quad Core with Gfx 700MHz), the N3160 Celeron (Quad Core with Gfx 640MHz), the N3060 Celeron (Dual Core with Gfx 600MHz), and the N3010 Celeron (Dual Core with Gfx 600MHz). The LEC-BW product family also includes a lower-cost alternative: the x5-E8000 Atom with Gfx 320MHz. N-Series CPUs feature the Intel Architecture and are manufactured based on Intel’s 14-nanometer technology. Refer to the N-series SoC data sheet on the Intel web site. Other CPU SKUs are available on request.

# 2.3.2 SDRAM

The LEC-BW employs one channel of 64-bit DDR3L on-board memory. Eight SDRAM memory chips provide up to 32Gb of low-voltage non-ECC, unbuffered system memory. Refer to the MT41K SDRAM data sheet on the Micron web site.

Depending on the DRAM chips featured on the module, the following total DRAM capacities are supported:

$\nu \quad 8 \times 1 2 6 \mathsf { M } 8 = 1 \mathsf { G B }$
$\nu \quad 8 \times 2 5 6 \mathsf { M } 8 = 2 \mathsf { G B }$
$\nu \quad 8 \times 5 1 2 \mathsf { M } 8 = 4 \mathsf { G B }$
 8x 1M8 = 8 GB

# 2.3.3 I211 LAN Controller

The Intel I211 provides a single-port controller that supports GbE functionality using the high-speed PCIe standard, v2.1 (2.5GT/s). The I211 features an integrated PHY, which enables 1000BASE-T implementations such as rack-mounted or pedestal servers in add-on NIC or LAN-on-Motherboard (LOM) designs. Other implementations include blade servers such as LOMs or mezzanine cards as well as embedded applications such as switch add-on cards and network appliances. Refer to the Intel I211 Ethernet Controller data sheet on the Intel web site.

# 2.3.4 PTN3460i eDP-to-LVDS Converter

The PTN 3460i supports single-bus or dual-bus LVDS signalling with color depths of 18 bits per pixel or 24 bits per pixel and pixel clock frequency up to 112MHz. The LVDS data packing can be done either in VESA or JEIDA formats. Also, the DP AUX interface transports I2C-over-AUX commands and support EDID-DDC communication with LVDS panel. To support panels without EDID ROM, the PTN3460 can emulate EDID ROM behavior, avoiding specific changes in system video BIOS. Find more details on the NXP website.

# 2.3.5 PCA9535A GPIO Expander

The PCA9535A is a 24-pin device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBUS applications. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. The operating power supply voltage range of the PCA535A is 1.65V to 5.5V. Find more details on the NXP website.

# 2.3.6 SMBus Slave Addresses

Table 2-3 lists the corresponding slave addresses of the devices on the SMBus.

Table 2-3: SMBus Slave Addresses

<table><tr><td>Address (HEX)</td><td>Function</td><td>Device</td></tr><tr><td>(40)</td><td>GPIO</td><td>PCA9535A</td></tr><tr><td>(50)</td><td>BMC/SEMA</td><td>BMC</td></tr><tr><td>(C0)</td><td>eDP to LVDS</td><td>PTN3460i</td></tr><tr><td>(A0)</td><td>DDR3L channel A</td><td>DDR3L memory</td></tr><tr><td>(92)</td><td>Thermal Sensor</td><td>LM73</td></tr></table>

# 3 Interfaces

This section provides descriptions of the interfaces and signals within the SMARC P-S (Primary-Secondary) connector. Refer to the SMARC specification at:

http://www.sget.org/standards/qseven.html for definitions of the SMARC interfaces. The SMARC P-S (Primary-Secondary) connector provides the following interfaces:

 Video
 Camera
 HD Audio
 PCI Express (PCIe)
 Gb Ethernet
 USB 2.0
 USB 3.0
 SATA
 I2C
 SPI
 Serial UART
 I2S (Audio)
 SD/SDIO
 eMMC
 GPIO
 Debug

![The image displays a graphic of a white document with a folded top-right corner and a large red checkmark in the center. Below the document graphic, the text 'NOTE:' is written in black capital letters.](.lec-bw-50-1z206-1010-200-en/1177f421b443de3ded7638f3894a1957ce59954558cb418c4de51cd79c0c70d6.jpg)

ADLINK Technology, Inc. only supports the features/ options tested and listed in this manual. The main chips used in the LEC-BW may provide more features or options than are listed for the LEC-BW, but some of these features or options are not supported on the module and will not function as specified in the chip documentation.

# 3.1 Display Interfaces

The LEC-BW supports three independent display interfaces. This section describes all three interfaces including the standard and optional configurations for each.

# 3.1.1 18/24-Bit LVDS LCD (Primary Display)

The LVDS interface is connected to the DDI1 port of the CPU, and the translation is made by the eDP-to-LVDS converter. The standard LEC-BW configuration supports a single channel LVDS interface with a max. resolution of 1280x720 pixels at 60Hz, as defined by the SMARC specification. As a custom option, a second LVDS channel can be supported (separate order number for both, module and carrier.) The dual channel LVDS interface supports resolutions up to 1920x1200 at 60Hz. Refer to the NXP PTN3460I, eDP-to-LVDS converter datasheet. See the LEC-BW display interface diagrams in Section 3.1.3.

# 3.1.2 HDMI (Secondary Display)

The second digital display is an HDMI interface, which originates from the DDI2 port of the CPU. The standard LEC-BW display configuration supports HDMI (TMDS) output to the display. The standard HDMI interface provides the following features:

 1 clock pair
 3 Data pairs
 Service signals
 HDMI resolutions up to 3840x2160 @ 30Hz or 2560x1600 @ 60Hz

# 3.1.3 HDMI/Display Port (DP) [Third Display]

An optional configuration (separate order number for both, module and carrier) supports a third digital display, which can be either HDMI (TMDS) or Display Port output. It originates from DDI0. This implementation re-uses the SMARC parallel LCD pins, which would otherwise go unused on the LEC-BW. The optional custom display configuration provides the following features:

 1 clock pair
 3 Data pairs
 Service signals
 HDMI or DP resolutions up to 3840x2160 @ 30Hz or 2560x1600 @ 60Hz
 Compliant with the HDMI 1.4b specification.
 Compliant with the DP 1.1a specification.

The following diagram represents the standard and optional display interface configurations supported by the LEC-BW when mounted on the LEC-BASE MINI carrier.

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n*   **Top-Left Group:** A container box holding two smaller blocks labeled 'HDMI /DP' and 'SC LVDS'.\n*   **Middle-Left Block:** A box labeled 'SC LVDS'.\n*   **Bottom-Left Block:** A box labeled 'HDMI'.\n*   **Center Block:** A box labeled 'NXP LVDS Transceiver'.\n*   **Right-Side Vertical Block:** A tall box divided into three sections labeled 'DDI0', 'DDI1', and 'DDI2'.\n\n**Connections:**\n*   **HDMI/DP Connection:** A bidirectional arrow labeled 'HDMI/DP' connects the 'HDMI /DP' block to the 'DDI0' section.\n*   **SC LVDS to Transceiver (Top):** A single-headed arrow points downward from the 'SC LVDS' block (inside the top-left group) to the 'NXP LVDS Transceiver'.\n*   **SC LVDS to Transceiver (Middle):** A bidirectional arrow connects the middle-left 'SC LVDS' block to the 'NXP LVDS Transceiver'.\n*   **Transceiver to DDI1:** A bidirectional arrow connects the 'NXP LVDS Transceiver' to the 'DDI1' section.\n*   **HDMI Connection:** A bidirectional arrow labeled 'HDMI' connects the bottom-left 'HDMI' block to the 'DDI2' section.](.lec-bw-50-1z206-1010-200-en/0f1be1870db8e58b4064b658fbd8500c7207fbc9bd0e4352ab406c1170f8b7ad.jpg)

The following diagram represents an overview of the standard and optional display interface configurations supported by the LEC-BW when mounted on both versions of the LEC-BASE MINI carrier. The LEC-BASE MINI (Standard) supports the standard dual display configuration, while LEC-BASE MINI (Custom) supports the custom configuration with a third display and a second LVDS channel.

![This diagram is titled **'LEC-BW (Standard)'**. It consists of three main blocks on the left and a larger block structure on the right.\n\n**Labeled Blocks:**\n*   **Left Side:**\n    *   A box labeled **'SC LVDS Display'**.\n    *   A box below it labeled **'HDMI/DP Display'**.\n*   **Right Side:**\n    *   A large box labeled **'LEC-BASE MINI'**.\n    *   Nested inside the bottom of this box is a smaller box labeled **'LEC-BW'**.\n\n**Connections:**\n*   A double-headed arrow connects the **'SC LVDS Display'** block and the **'LEC-BASE MINI'** block. The text above this arrow reads **'Single Channel LVDS 18/24bit'**.\n*   A double-headed arrow connects the **'HDMI/DP Display'** block and the **'LEC-BASE MINI'** block. The text above this arrow reads **'HDMI'**.](.lec-bw-50-1z206-1010-200-en/3cccf577fe4b5ed12d485417109a4645e3499d76215d4b3e677d6f600b6da90b.jpg)

![The diagram is titled **LEC-BW (Custom Option)**. It features a large block on the right labeled **LEC-BASE MINI**, which contains a nested inner block labeled **LEC-BW**.\n\nTo the left of this main block are three smaller blocks connected via bidirectional arrows:\n\n1.  The top block is labeled **HDMI/ DP Display**. It connects to the main block with an arrow labeled **HDMI/DP**.\n2.  The middle block is labeled **DC LVDS Display**. It connects to the main block with an arrow labeled **Dual Channel LVDS 18/24bit**.\n3.  The bottom block is labeled **HDMI/DP Display**. It connects to the main block with an arrow labeled **HDMI**.](.lec-bw-50-1z206-1010-200-en/241607205c052aa5533b703406199f59d37e220b43fffccb93dd9153baa3d95a.jpg)

# 3.2 Camera MIPI-CSI

The LEC-BW brings out signals for two MIPI-CSI 2.0 (serial) camera interfaces, one with two data lanes and one with four data lanes, supporting up to 800 Mbit/s of actual pixels. The following bullets highlight the imaging capabilities of the Camera interface.

 Sensor interface for 2 sensors: x4, x2
 Up to 2 simultaneous sensors
 5MP 2-D image capture
 Up to 1080p30 2-D video capture
 RAW 8, 10, 12, 14, RGB444, 565, 888, YUV420, 422, JPEG input formats
 YUV422, YUV420, RAW output formats
 Special features

 Image and video stabilization
 Low light noise reduction
 Burst mode capture
 Memory to memory processing
 3A (Auto Exposure [AE], Auto White Balance [AWB], and Auto Focus [AF])
 High Dynamic Range (HDR)
 Multi focus
 Zero shutter lag

# 3.3 Audio (HDA)

The CPU provides an HDA controller, which communicates over the Intel HDA serial link with internal CODECs on the CPU or external CODECs on the baseboard. HDA signals are brought out through the I2S2 pins on the SMARC connector and are multiplexed with LPE\_I2S audio signals. When HDA is active, LPE audio is disabled. The following list highlights the features of the audio interface.

 Decode: MP3, AAC-LC, HE-ACC v1/2, WMA9, 10, PRO, Lossless, Voice, MPEG layer 2, Real Audio, OggVorbis, FLAC, DD/DD+
 Encode: MP3, ACC-LC, WMA, DD-2channel
 Supports MSI and legacy interrupt delivery
 Support for ACPI D3 and D0 Device States
 Supports up to:
 6 streams (three input, three output)
 16 channels per stream
 32 bits/sample
 192KHz sample rate
 24 MHz HDA\_CLK supports:
 SDO double pumped at 48Mb/s
 SDI single pumped at 24Mb/s
 Supports 1.5V and 1.8V modes
 Supports optional Immediate Command/Response mechanism

![The image displays a digital icon of a white document with a folded top-right corner. A large, bold red checkmark is superimposed over the center of the page. Faint gray lines resembling text or form fields are visible on the document.](.lec-bw-50-1z206-1010-200-en/bf047a936beac7844134a1095858ca978185857e41141cb23911850d22176b28.jpg)
NOTE:

A camera driver is required for each OS.

# 3.4 PCI Express (PCIe)

The CPU features four PCIe x1 ports, and the LEC-BW module uses three of them for the PCIe interface and one of them for the Gigabit Ethernet interface. The PCIe interface supports the PCIe Base Specification 2.0 with a maximum signal rate of 5 GT/s and can be configured to support PCIe edge cards or Express Cards.

# 3.5 Gigabit Ethernet

The on-board Intel I211IT Ethernet controller uses PCIe x1 (v2.1) bus signals from the CPU to enable 10T/100TX/1000T operation through integrated MAC, PHY, and MDI interfaces.

# 3.6 USB Ports

The USB interface originates from two host controllers on the CPU that provide four USB 2.0 host ports and one USB 3.0 host port.

# 3.6.1 USB 2.0

Three of the four USB 2.0 ports use the USB 0-2 pins on the SMARC connector (0 = host; 1 = host; 2 = host.) The fourth USB 2.0 port uses the AFB\_DIFF2 pins (S68-S69) on the SMARC connector.

# 3.6.2 USB 3.0

The USB 3.0 port uses the AFB\_DIFF pins on the SMARC connector and map to the AFB header on the LEC-BASE baseboard. See pins S62/S63 and S65/S66 in Table 3-2.

# 3.7 SATA

The SATA interface provides two GEN3 ports. The SATA0 pins on the SMARC connector provide one port. The AFB-DIFF 3 and 4 pins provide the second port. The interface supports up to 6Gb/s for each port.

# 3.8 I2C Bus

The LEC-BW provides five interfaces through the I2C bus for general purpose signals with operating speeds up to 400kHz. The following table maps the I2C interfaces to their corresponding pins on the SMARC interface connector.

<table><tr><td>SMARC Pins</td><td>I2C Interfaces</td></tr><tr><td>P105/P106</td><td>HDMI Control</td></tr><tr><td>P121/P122</td><td>PM</td></tr><tr><td>S5/S7</td><td>Camera</td></tr><tr><td>S48/S49</td><td>GP</td></tr><tr><td>S139/S140</td><td>LCD/EDID</td></tr></table>

# 3.9 SPI

The CPU implements two SPI controllers. One SPI controller connects to two SPI flash devices on the module and to the DB40 connecter. The second SPI controller supports devices on the carrier through the SMARC (MXM3) connector pins (SPI0 and SPI1).

# 3.10 Serial (UART)

The LEC-BW provides two serial interfaces: one high-speed, 4-wire port with TX/RX and RTS#/ CTS# signals and one 2-wire port (with TX/RX only.)

# 3.11 SD/SDIO Interface

Four parallel data lines comprise the SD/SDIO interface, supporting SD Card sockets.

# 3.12 eMMC Interface

The LEC-BW provides one 8-bit eMMC interface port, brought out from the CPU through the SDMMC pins on the SMARC connector.

# 3.13 GPIO

The LEC-BW provides 12 GPIO signals from the CMOS device on the module. The GPIO signals can be utilized for General Purpose IO interfaces as well as HDA reset. Table 3-1 provides the default functions of the GPIO signals.

Table 3-1: GPIO Default Settings

<table><tr><td>SMARC Connector Pin</td><td>Default Function</td></tr><tr><td>GPIO0</td><td>GPIO</td></tr><tr><td>GPIO1</td><td>GPIO</td></tr><tr><td>GPIO2</td><td>GPIO</td></tr><tr><td>GPIO3</td><td>GPIO</td></tr><tr><td>GPIO4</td><td>HDA_RST#</td></tr><tr><td>GPIO5</td><td>GPIO</td></tr><tr><td>GPIO6</td><td>GPIO</td></tr><tr><td>GPIO7</td><td>GPIO</td></tr><tr><td>GPIO8</td><td>GPIO</td></tr><tr><td>GPIO9</td><td>GPIO</td></tr><tr><td>GPIO10</td><td>GPIO</td></tr><tr><td>GPIO11</td><td>GPIO</td></tr></table>

![The image displays a white document icon with a folded top-right corner and faint horizontal lines. A large, red checkmark is superimposed over the front of the document.](.lec-bw-50-1z206-1010-200-en/173f99d4b973ddc3328f440bb5dae27a2a7d1e4895e2af9d19e95a97d45c43e4.jpg)
NOTE:

The signals GPIO0-GPIO3 alternatively can be used for MIPI CSI camera signals, CAM0\_PWR#, CAM1\_PWR#, CAM0\_RST#, CAM1\_RST#. This requires a separate module order number (BOM option). Its usage depends on the availability of camera drivers of the installed operating system. A camera add-on card is needed for the LEC\_BASE MINI carrier.

# 3.14 LPC Debug Interface

A 40-pin, front flip, DB40 connector allows access to the system to debug and update the BIOS, BMC, and OS code. (Refer to “Debug (DB40) Connector Signals” on page 31.)

# 3.15 SMARC Interface Signals

Table 3-2 provides the supported pin signal definitions for the SMARC connector. Refer to the SMARC specification at http://www.sget.org/standards/smarc.html for further details of the SMARC signals.

Table 3-2: SMARC P-S Connector (GF1) Signal Descriptions

<table><tr><td>Pin #</td><td>Primary (Top Side)</td><td>Pin #</td><td>Secondary (Bottom Side)</td></tr><tr><td></td><td></td><td>S1</td><td>Not connected</td></tr><tr><td>P1</td><td>Not connected</td><td>S2</td><td>Not connected</td></tr><tr><td>P2</td><td>GND</td><td>S3</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+ (CSI1 differential clock inputs.)</td><td>S4</td><td>Not connected</td></tr><tr><td>P4</td><td>CSI1_CK- (CSI1 differential clock inputs.)</td><td>S5</td><td>I2C_CAM_CK (Serial / Parallel camera support link - I2C clock)</td></tr><tr><td>P5</td><td>Not connected</td><td>S6</td><td>CAM_MCK (Master clock output for CSI camera support (may be used for CSIO and / or CSI1)</td></tr><tr><td>P6</td><td>Not connected</td><td>S7</td><td>I2C_CAM_DAT (Serial / Parallel camera support link - I2C data)</td></tr><tr><td>P7</td><td>CSI1_D0+ (CSI1 differential data inputs.)</td><td>S8</td><td>CSI0_CK+ (CSI0 differential clock inputs.)</td></tr><tr><td>P8</td><td>CSI1_D0- (CSI1 differential data inputs.)</td><td>S9</td><td>CSI0_CK- (CSI0 differential clock inputs.)</td></tr><tr><td>P9</td><td>GND</td><td>S10</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_D1+ (CSI1 differential data inputs.)</td><td>S11</td><td>CSI0_D0+ (CSI0 differential data inputs.)</td></tr><tr><td>P11</td><td>CSI1_D1- (CSI1 differential data inputs.)</td><td>S12</td><td>CSI0_D0- (CSI0 differential data inputs.)</td></tr><tr><td>P12</td><td>GND</td><td>S13</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_D2+ (CSI1 differential data inputs.)</td><td>S14</td><td>CSI0_D1+ (CSI0 differential data inputs)</td></tr><tr><td>P14</td><td>CSI1_D2- (CSI1 differential data inputs.)</td><td>S15</td><td>CSI0_D1- (CSI0 differential data inputs)</td></tr><tr><td>P15</td><td>GND</td><td>S16</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_D3+ (CSI1 differential data inputs.)</td><td>S17</td><td>AFB0_OUT (General purpose AFB output; maps to PMU_SLP_S3# on the SOC)</td></tr><tr><td>P17</td><td>CSI1_D3- (CSI1 differential data inputs.)</td><td>S18</td><td>AFB1_OUT (General purpose AFB output; maps to PMU_SLP_S4# on the SOC)</td></tr><tr><td>P18</td><td>GND</td><td>S19</td><td>AFB2_OUT (General purpose AFB output; maps to PMU_SUS_STAT# on the SOC)</td></tr><tr><td>P19</td><td>GBE_MDI3- (Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S20</td><td>Not connected</td></tr><tr><td>P20</td><td>GBE_MDI3+(Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S21</td><td>Not connected</td></tr><tr><td>P21</td><td>GBE_LINK100# (Link Speed Indication LED for 100Mbps; able to sink 24mA or more carrier LED current)</td><td>S22</td><td>Not connected</td></tr><tr><td>P22</td><td>GBE_LINK1000# (Link Speed Indication LED for 1000Mbps; able to sink 24mA or more carrier LED current)</td><td>S23</td><td>AFB6_PTIO (EN_OC# for USB SS)</td></tr><tr><td>P23</td><td>GBE_MDI2- (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S24</td><td>AFB7_PTIO (PCU_SMB_ALERT#)</td></tr><tr><td>P24</td><td>GBE_MDI2+ (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S25</td><td>GND</td></tr><tr><td>P25</td><td>GBE_LINK_ACT# (Link / Activity Indication LED Driven low on Link [10, 100 or 1000 mbps] Blinks on Activity; able to sink 24mA or more Carrier LED current)</td><td>S26</td><td>SDMMC_D0 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P26</td><td>GBE_MDI1- (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S27</td><td>SDMMC_D1 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P27</td><td>GBE_MDI1+ (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S28</td><td>SDMMC_D2 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P28</td><td>GBE_CTREF (Center-Tap reference voltage for GBE0 Carrier board Ethernet magnetic [if required by the Module GBE PHY])</td><td>S29</td><td>SDMMC_D3 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P29</td><td>GBE0_MDI0- (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S30</td><td>SDMMC_D4 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P30</td><td>GBE0_MDI0+ (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S31</td><td>SDMMC_D5 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P31</td><td>SPI0_CS1# (SPI0 Master Chip Select 1 output)</td><td>S32</td><td>SDMMC_D6 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P32</td><td>GND</td><td>S33</td><td>SDMMC_D7 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P33</td><td>SDIO_WP (SDIO card Write Protect; 1K pull-up to 3.3V)</td><td>S34</td><td>GND</td></tr><tr><td>P34</td><td>SDIO_CMD (SDIO card Command line)</td><td>S35</td><td>SDMMC_CK (clock)</td></tr><tr><td>P35</td><td>SDIO_CD# (SDIO Card Detect; 1K pull-up to 3.3V)</td><td>S36</td><td>SDMMC_CMD (command line)</td></tr><tr><td>P36</td><td>SDIO_CK (SDIO card Clock)</td><td>S37</td><td>SDMMC_RST# (Reset signal to eMMC device)</td></tr><tr><td>P37</td><td>SDIO_PWR_EN (SDIO card Power Enable)</td><td>S38</td><td>Not connected</td></tr><tr><td>P38</td><td>GND</td><td>S39</td><td>Not connected</td></tr><tr><td>P39</td><td>SDIO_D0 (SDIO card 4-bit data path)</td><td>S40</td><td>Not connected</td></tr><tr><td>P40</td><td>SDIO_D1 (SDIO card 4-bit data path)</td><td>S41</td><td>Not connected</td></tr><tr><td>P41</td><td>SDIO_D2 (SDIO card 4-bit data path)</td><td>S42</td><td>Not connected</td></tr><tr><td>P42</td><td>SDIO_D3 (SDIO card 4-bit data path)</td><td>S43</td><td>Not connected</td></tr><tr><td>P43</td><td>SPI0_CS0# (SPI0 Master Chip Select 0 output; use to select carrier SPI boot device)</td><td>S44</td><td>Not connected</td></tr><tr><td>P44</td><td>SPI0_CK (SPI0 Master Clock output)</td><td>S45</td><td>Not connected</td></tr><tr><td>P45</td><td>SPI0_DIN (SPI0 Master Data input [input to CPU, output from SPI device])</td><td>S46</td><td>Not connected</td></tr><tr><td>P46</td><td>SPI0_DO (SPI0 Master Data output [output from CPU, input to SPI device])</td><td>S47</td><td>GND</td></tr><tr><td>P47</td><td>GND</td><td>S48</td><td>I2C_GP_CK (I2C General Purpose clock signal)</td></tr><tr><td>P48</td><td>SATA0_TX+ (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S49</td><td>I2C_GP_DAT I2C (General Purpose data signal)</td></tr><tr><td>P49</td><td>SATA0_TX- (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S50</td><td>HDA_SYNC (Intel HD Audio Sync: 48KHz fixed rate)</td></tr><tr><td>P50</td><td>GND</td><td>S51</td><td>HDA_SDO (Intel HD Audio Data Out: Serial TMD data output to the codec(s). The serial output is double-pumped for a bit rate of 48Mb/s.)</td></tr><tr><td>P51</td><td>SATA0_RX+ (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S52</td><td>HDA_SDI0 (Intel HD Audio Data In: Serial TMD data input from the codec(s). The serial input is single-pumped for a bit rate of 24Mb/s)</td></tr><tr><td>P52</td><td>SATA0_RX- (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S53</td><td>HDA_CLK (Intel Audio Bit Clock [output]: 24MHz serial data clock generated by the Intel HD Audio controller.</td></tr><tr><td>P53</td><td>GND</td><td>S54</td><td>SATA_ACT# (Active low SATA activity indicator If implemented, able to sink 24mA or more Carrier LED current)</td></tr><tr><td>P54</td><td>SPI1_CS0# (SPI1 Master Chip Select 0 output)</td><td>S55</td><td>Not connected</td></tr><tr><td>P55</td><td>SPI1_CS1# (SPI1 Master Chip Select 1 output)</td><td>S56</td><td>Not connected</td></tr><tr><td>P56</td><td>SPI1_CK (SPI1 Master Clock output)</td><td>S57</td><td>Not connected</td></tr><tr><td>P57</td><td>SPI1_DIN (SPI1 Master Data input [input to CPU, output from SPI device])</td><td>S58</td><td>Not connected</td></tr><tr><td>P58</td><td>SPI1_DO (SPI1 Master Data output [output from CPU, input to SPI device])</td><td>S59</td><td>Not connected</td></tr><tr><td>P59</td><td>GND</td><td>S60</td><td>Not connected</td></tr><tr><td>P60</td><td>USB0+ (Differential USB0 data pair)</td><td>S61</td><td>GND</td></tr><tr><td>P61</td><td>USB0- (Differential USB0 data pair)</td><td>S62</td><td>AFB_DIFF0+ (maps to USB3_TX_P [USB 3.0] on the SOC)</td></tr><tr><td>P62</td><td>USB0_EN_OC# (Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S63</td><td>AFB_DIFF0- (maps to USB3_TX_N [USB 3.0] on the SOC)</td></tr><tr><td>P63</td><td>Not connected</td><td>S64</td><td>GND</td></tr><tr><td>P64</td><td>USB0_OTG_ID (USB OTG ID input, active high)</td><td>S65</td><td>AFB_DIFF1+ (maps to USB3_RX_P [USB 3.0] on the SOC)</td></tr><tr><td>P65</td><td>USB1+ (Differential USB1 data pair)</td><td>S66</td><td>AFB_DIFF1- (maps to USB3_RX_N [USB 3.0] on the SOC)</td></tr><tr><td>P66</td><td>USB1- (Differential USB1 data pair)</td><td>S67</td><td>GND</td></tr><tr><td>P67</td><td>USB1_EN_OC# (Pulled low by Module OD driver to disable USB1 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S68</td><td>AFB_DIFF2+ (maps to USB_D3_P [USB 2.0] on the SOC)</td></tr><tr><td>P68</td><td>GND</td><td>S69</td><td>AFB_DIFF2- (maps to USB_D3_N [USB 2.0] on the SOC</td></tr><tr><td>P69</td><td>USB2+ (Differential USB2 data pair)</td><td>S70</td><td>GND</td></tr><tr><td>P70</td><td>USB2- (Differential USB2 data pair)</td><td>S71</td><td>AFB_DIFF3+ (maps to SATA_TX1_P on the SOC)</td></tr><tr><td>P71</td><td>USB2_EN_OC# (Pulled low by Module OD driver to disable USB2 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up shall be present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S72</td><td>AFB_DIFF3- (maps to SATA_TX1_N on the SOC)</td></tr><tr><td>P72</td><td>PCIE_C_PRSNT# (PCIe Port C present input. Pulled up or terminated on Module)</td><td>S73</td><td>GND</td></tr><tr><td>P73</td><td>PCIE_B_PRSNT# (PCIe Port B present input. Pulled up or terminated on Module)</td><td>S74</td><td>AFB_DIFF4+ (maps to SATA_RX1_P on the SOC)</td></tr><tr><td>P74</td><td>PCIE_A_PRSNT# (PCIe Port A present input. Pulled up or terminated on Module)</td><td>S75</td><td>AFB_DIFF4- (maps to SATA_RX1_N on the SOC)</td></tr><tr><td>P75</td><td>PCIE_A_RST# (PCIe Port A reset output)</td><td>S76</td><td>PCIE_B_RST# (PCIe Port B reset output, active low)</td></tr><tr><td>P76</td><td>PCIE_C_CREQ# (PCIe Port C clock request input. Pulled up or terminated on Module)</td><td>S77</td><td>PCIE_C_RST# (PCIe Port A reset output, active low)</td></tr><tr><td>P77</td><td>PCIE_B_CREQ# (PCIe Port B clock request input. Pulled up or terminated on Module)</td><td>S78</td><td>PCIE_C_RX+ (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P78</td><td>PCIE_A_CREQ# (PCIe Port A clock request input. Pulled up or terminated on Module)</td><td>S79</td><td>PCIE_C_RX- (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P79</td><td>GND</td><td>S80</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+ (Differential PCIe Link C reference clock output. DC coupled)</td><td>S81</td><td>PCIE_C_TX+ (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0201 package 0.1uF)</td></tr><tr><td>P81</td><td>PCIE_C_REFCK- (Differential PCIe Link C reference clock output. DC coupled)</td><td>S82</td><td>PCIE_C_TX- (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0201 package 0.1uF)</td></tr><tr><td>P82</td><td>GND</td><td>S83</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+ (Differential PCIe Link A reference clock output. DC coupled)</td><td>S84</td><td>PCIE_B_REFCK+ (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P84</td><td>PCIE_A_REFCK- (Differential PCIe Link A reference clock output. DC coupled)</td><td>S85</td><td>PCIE_B_REFCK- (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P85</td><td>GND</td><td>S86</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+ (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S87</td><td>PCIE_B_RX+ (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P87</td><td>PCIE_A_RX- (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S88</td><td>PCIE_B_RX- (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P88</td><td>GND</td><td>S89</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+ (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0201 capacitor are on module)</td><td>S90</td><td>PCIE_B_TX+ (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0201 package 0.1uF)</td></tr><tr><td>P90</td><td>PCIE_A_TX- (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0201 capacitor are on module)</td><td>S91</td><td>PCIE_B_TX- (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0201 package 0.1uF)</td></tr><tr><td>P91</td><td>GND</td><td>S92</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+ (TMDS / HDMI data 2 differential pair)</td><td>S93</td><td>DP_D0+ / HDMI_B_D2+ (Display Port or HDMI data pair 0; output)</td></tr><tr><td>P93</td><td>HDMI_D2- (TMDS / HDMI data 2 differential pair)</td><td>S94</td><td>DP_D0- / HDMI_B_D2- (Display Port or HDMI data pair 0; output)</td></tr><tr><td>P94</td><td>GND</td><td>S95</td><td>GND</td></tr><tr><td>P95</td><td>HDMI_D1+ (TMDS / HDMI data 1 differential pair)</td><td>S96</td><td>DP_D1+ / HDMI_B_D1+ (Display Port or HDMI data pair 1; output)</td></tr><tr><td>P96</td><td>HDMI_D1- (TMDS / HDMI data 1 differential pair)</td><td>S97</td><td>DP_D1- / HDMI_B_D1- (Display Port or HDMI data pair 1; output)</td></tr><tr><td>P97</td><td>GND</td><td>S98</td><td>GND)</td></tr><tr><td>P98</td><td>HDMI_D0+ (TMDS / HDMI data 0 differential pair)</td><td>S99</td><td>DP_D2+ / HDMI_B_D0+ (Display Port or HDMI data pair 2; output)</td></tr><tr><td>P99</td><td>HDMI_D0- (TMDS / HDMI data 0 differential pair)</td><td>S100</td><td>DP_D2- / HDMI_B_D0- (Display Port or HDMI data pair 2; output)</td></tr><tr><td>P100</td><td>GND</td><td>S101</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+ (TMDS / HDMI clock output differential pair)</td><td>S102</td><td>DP_D3+ / HDMI_B_CK+ (Display Port data pair or HDMI clock pair; output)</td></tr><tr><td>P102</td><td>HDMI_CK- (TMDS / HDMI clock output differential pair)</td><td>S103</td><td>DP_D3- / HDMI_B_CK- (Display Port data pair or HDMI clock pair; output)</td></tr><tr><td>P103</td><td>GND</td><td>S104</td><td>GND</td></tr><tr><td>P104</td><td>HDMI_HPD (HDMI Hot Plug Detect input)</td><td>S105</td><td>DP_HDP / HDMI_B_HDP (Display Port or HDMI Hot Plug Detect; input)</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK (I2C clock line dedicated to HDMI)</td><td>S106</td><td>DP_AUX+ / HDMI_B_CTRL_CK (Display Port Auxiliary Channel pair or HDMI control clock; input/output)</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT (I2C data line dedicated to HDMI)</td><td>S107</td><td>DP_AUX- / HDMI_B_CTRL_DAT (Display Port Auxiliary Channel pair or HDMI control data; input/output)</td></tr><tr><td>P107</td><td>Not Connected</td><td>S108</td><td>AUX_SEL / HDMI_B_CEC (DP or HDMI Select or HDMI Consumer Electronic Control, 1-wire peripheral control interface)</td></tr><tr><td>P108</td><td>GPIO0 (General Purpose IO [Output recommended])</td><td>S109</td><td>Not connected</td></tr><tr><td>P109</td><td>GPIO1 (General Purpose IO [Output recommended])</td><td>S110</td><td>GND</td></tr><tr><td>P110</td><td>GPIO2 (General Purpose IO [Output recommended])</td><td>S111</td><td>LVDS_B_0+ (LVDS control channel data pair; output)</td></tr><tr><td>P111</td><td>GPIO3 (General Purpose IO [Output recommended])</td><td>S112</td><td>LVDS_B_0- (LVDS control channel data pair; output)</td></tr><tr><td>P112</td><td>HDA_RST# (HDA reset output)</td><td>S113</td><td>Not connected</td></tr><tr><td>P113</td><td>GPIO5 (General Purpose IO [Output recommended])</td><td>S114</td><td>LVDS_B_1+ (LVDS control channel data pair; output)</td></tr><tr><td>P114</td><td>GPIO6 (General Purpose IO [Input recommended])</td><td>S115</td><td>LVDS_B_1- (LVDS control channel data pair; output)</td></tr><tr><td>P115</td><td>GPIO7 (General Purpose IO [Input recommended])</td><td>S116</td><td>Not connected</td></tr><tr><td>P116</td><td>GPIO8 (General Purpose IO [Input recommended])</td><td>S117</td><td>LVDS_B_2+ (LVDS control channel data pair; output)</td></tr><tr><td>P117</td><td>GPIO9 (General Purpose IO [Input recommended])</td><td>S118</td><td>LVDS_B_2- (LVDS control channel data pair; output)</td></tr><tr><td>P118</td><td>GPIO10 (General Purpose IO [Input recommended])</td><td>S119</td><td>GND</td></tr><tr><td>P119</td><td>GPIO11 (General Purpose IO [Input recommended])</td><td>S120</td><td>LVDS_B_CK+ (LVDS control channel clock pair; output)</td></tr><tr><td>P120</td><td>GND</td><td>S121</td><td>LVDS_B_CK- (LVDS control channel clock pair; output)</td></tr><tr><td>P121</td><td>I2C_PM_CK (Power management I2C bus clock)</td><td>S122</td><td>LVDS_B_3+ (LVDS control channel data pair; output)</td></tr><tr><td>P122</td><td>I2C_PM_DAT(Power management I2C bus data)</td><td>S123</td><td>LVDS_B_3+ (LVDS control channel data pair; output)</td></tr><tr><td>P123</td><td>BOOT_SEL0# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S124</td><td>GND</td></tr><tr><td>P124</td><td>BOOT_SEL1# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S125</td><td>LVDS_A_0+ (LVDS control channel data pair; output)</td></tr><tr><td>P125</td><td>BOOT_SEL2# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S126</td><td>LVDS_A_0- (LVDS control channel data pair; output)</td></tr><tr><td>P126</td><td>RESET_OUT# (General purpose reset output to Carrier board.)</td><td>S127</td><td>LVDS_BKLT_EN (High enables panel backlight)</td></tr><tr><td>P127</td><td>RESET_IN# (Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S128</td><td>LVDS_A_1+ (LVDS control channel data pair; output)</td></tr><tr><td>P128</td><td>POWER_BTN# (Power-button input from Carrier board. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the Module Pulled up on Module. Driven by OD part on Carrier.)</td><td>S129</td><td>LVDS_A_1- (LVDS control channel data pair; output)</td></tr><tr><td>P129</td><td>SER0_TX (Asynchronous serial port data out)</td><td>S130</td><td>GND</td></tr><tr><td>P130</td><td>SER0_RX (Asynchronous serial port data in)</td><td>S131</td><td>LVDS_A_2+ (LVDS control channel data pair; output)</td></tr><tr><td>P131</td><td>SER0_RTS# (Request to Send handshake line for SER0)</td><td>S132</td><td>LVDS_A_2- (LVDS control channel data pair; output)</td></tr><tr><td>P132</td><td>SER0_CTS# (Clear to Send handshake line for SER0)</td><td>S133</td><td>LCD_VDD_EN (High enables panel VDD)</td></tr><tr><td>P133</td><td>GND</td><td>S134</td><td>LVDS_A_CK+ (LVDS control channel clock pair; output)</td></tr><tr><td>P134</td><td>SER1_TX (Asynchronous serial port data out)</td><td>S135</td><td>LVDS_A_CK- (LVDS control channel clock pair; output)</td></tr><tr><td>P135</td><td>SER1_RX (Asynchronous serial port data in)</td><td>S136</td><td>GND</td></tr><tr><td>P136</td><td>Not connected</td><td>S137</td><td>LVDS_A_3+ (LVDS control channel clock pair; output)</td></tr><tr><td>P137</td><td>Not connected</td><td>S138</td><td>LVDS_A_3- (LVDS control channel clock pair; output)</td></tr><tr><td>P138</td><td>Not connected</td><td>S139</td><td>LVDS_DDC_CLK (I2C clock – to read LCD display EDID EEPROMs)</td></tr><tr><td>P139</td><td>Not connected</td><td>S140</td><td>LVDS_DDC_DAT (I2C data – to read LCD display EDID EEPROMs)</td></tr><tr><td>P140</td><td>Not connected</td><td>S141</td><td>LCD_BKLT_PWM (Display backlight PWM control)</td></tr><tr><td>P141</td><td>Not connected</td><td>S142</td><td>Not connected</td></tr><tr><td>P142</td><td>GND</td><td>S143</td><td>GND</td></tr><tr><td>P143</td><td>Not connected</td><td>S144</td><td>EDP_HPD (eDP Hot Plug Detect pin)</td></tr><tr><td>P144</td><td>Not connected</td><td>S145</td><td>WDT_TIME_OUT# (Watchdog Timer Output)</td></tr><tr><td>P145</td><td>Not connected</td><td>S146</td><td>PCIE_WAKE (PCIe wake up interrupt to host – common to PCIe; links A, B, C – pulled up or terminated on Module)</td></tr><tr><td>P146</td><td>Not connected</td><td>S147</td><td>VDD_RTC (Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.See Section 7.3 RTC Voltage Rail of the SMARC specification for an important safety note on the implementation of lithium backup batteries.)</td></tr><tr><td>P147</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S148</td><td>LID# (Lid open/close indication to Module.Low indicates lid closure, which system may use to initiate a sleep state. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the ModulePulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P148</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S149</td><td>SLEEP# (Sleep indicator from Carrier board; sourced from user Sleep button or Carrier logic. Carrier to float the line in inactive state. Active low, level sensitive; de-bounced on the Module.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P149</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S150</td><td>VIN_PWR_BAD# (Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits)is not enabled while this signal is held low by the Carrier.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P150</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S151</td><td>CHARGING# (Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P151</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S152</td><td>CHARGER_PRSNT# (Held low by Carrier if DC input for battery charger is present. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P152</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S153</td><td>CARRIER_STBY# (The Module drives this signal low when the system is in a standby power state)</td></tr><tr><td>P153</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S154</td><td>CARRIER_PWR_ON (Carrier board circuits [apart from power management and power path circuits]are powered up until the Module asserts the CARRIER_PWR_ON signal)</td></tr><tr><td>P154</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S155</td><td>FORCE_RECOV# (Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery function, then a low on the Module FORCE_RECOV# pinmay invoke the SOC native Force Recovery mode – such as over a Serial Port. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P155</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S156</td><td>BATLOW# (Battery low indication to Module. Carrier to float the line in inactive state. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P156</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S157</td><td>TEST# (Held low by Carrier to invoke Module vendor specific test function(s). Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td></td><td></td><td>S158</td><td>GND</td></tr></table>

NOTE: The # symbol indicates the signal is Active Low.

# 3.16 Debug (DB40) Connector Signals

Table 3-3 lists the pin signals of the CN1 connector, which provides 40 pins, 1 row, consecutive sequence with 0.02" (0.50mm) pitch.

Table 3-3: Debug Interface Signals (CN1)

<table><tr><td>Pin #</td><td>Interface</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>RESVD</td></tr><tr><td>2</td><td rowspan="4">SMC Debug</td><td>SMC_STATUS</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>SEL_BIOS</td></tr><tr><td>5</td><td>POSTWDT_DIS#</td></tr><tr><td>6</td><td rowspan="7">Test Point</td><td>SUS_S5#</td></tr><tr><td>7</td><td>SUS_S4#</td></tr><tr><td>8</td><td>SUS_S3#</td></tr><tr><td>9</td><td>CB_PWROK</td></tr><tr><td>10</td><td>CB_RESET#</td></tr><tr><td>11</td><td>SYS_RESET#</td></tr><tr><td>12</td><td>PWRBTN#</td></tr><tr><td>13</td><td rowspan="11">SMC Program Interface</td><td>SMC_OCD0B</td></tr><tr><td>14</td><td>SMC_OCD0A</td></tr><tr><td>15</td><td>SMC_CLK</td></tr><tr><td>16</td><td>SMC_DATA</td></tr><tr><td>17</td><td>SMC_RESET_IN#</td></tr><tr><td>18</td><td>SMC_FLMD0</td></tr><tr><td>19</td><td>SMC_RXD6</td></tr><tr><td>20</td><td>SMC_TXD6</td></tr><tr><td>21</td><td>GND3</td></tr><tr><td>22</td><td>3V3_DUAL</td></tr><tr><td>23</td><td>3V3_SMC1</td></tr><tr><td>24</td><td rowspan="10">LPC Debug Card Interface</td><td>LPC_AD0</td></tr><tr><td>25</td><td>LPC_AD1</td></tr><tr><td>26</td><td>LPC_AD2</td></tr><tr><td>27</td><td>LPC_AD3</td></tr><tr><td>28</td><td>LPC_FRAME#</td></tr><tr><td>29</td><td>CLK33_LPC</td></tr><tr><td>30</td><td>RST#</td></tr><tr><td>31</td><td>BIOS_DIS0</td></tr><tr><td>32</td><td>GND2</td></tr><tr><td>33</td><td>LPC_3V3</td></tr><tr><td>34</td><td rowspan="7">SPI Program Interface</td><td>SPI_BIOS_CLK</td></tr><tr><td>35</td><td>SPI_BIOS_MOSI</td></tr><tr><td>36</td><td>SPI_BIOS_MISO</td></tr><tr><td>37</td><td>SPI_BIOS_CS1#</td></tr><tr><td>38</td><td>SPI_BIOS_CS0#</td></tr><tr><td>39</td><td>GND1</td></tr><tr><td>40</td><td>VCC_SPI_IN</td></tr></table>

NOTE: The gray table cells denote ground. The # symbol indicates the signal is Active Low.

# 4 Utilities

This chapter provides information on how to read information from and configure the BIOS Setup utility, the SEMA utility, the Watchdog Timer utility, and the board temperature sensors on the LEC-BW.

# 4.1 BIOS

The LEC-BW features an AMI BIOS. The default settings provide a “ready to run” system, even without a BIOS setup backup battery.

The BIOS is located in flash memory and can be easily updated with software under DOS.

All setup changes of the BIOS are stored in the CMOS RAM.

The battery on the baseboard will provide power to store that information for over two years without board activation.

This section presents the five primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Table 4-1: BIOS Setup Menu Structure

<table><tr><td>Main</td><td>Advanced</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>System InformationProcessor InformationVGA Firmware VersionMemory InformationSOC InformationSystem Management ▶System DateSystem Time</td><td>CPU▶Graphics▶Memory▶SATA▶USB▶Network ▶PCIe ▶ConfigurationACPI and Power Management▶Sound▶Serial Port Console▶Thermal▶Miscellaneous▶</td><td>Password Description▶Secure Boot Menu▶</td><td>Boot ConfigurationCSM Configuration ▶</td><td>Reset Options ▶Save Options ▶</td></tr></table>

# Notes:

► indicates a submenu

Gray text indicates info only

# 4.1.1 Starting the BIOS Setup Utility

Use the following bullets to initiate start-up activity for the BIOS Setup Utility.

 Press &lt;DEL&gt; during power up to start the BIOS setup utility.
 Press &lt;F11&gt; during power up to start the Boot menu.
 Press &lt;END&gt; during power up to return BIOS settings to default.

# 4.1.2 Main Menu

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings.

<table><tr><td colspan="2">BIOS Information
BIOS Vendor American Megatrends
Core Version 5.11
Compliancy UEFI 2.4; PI 1.3
Project Version LEC-BW 0.97 x64
Build Date and Time 02/25/2016 19:03:43
Access Level Administrator</td><td>System Management</td></tr><tr><td colspan="2">Processor Information
Intel(R) Pentium(R) CPU N3700 @ 1.60GHz</td><td></td></tr><tr><td colspan="2">Max CPU Speed 1600 MHz
CPU Signature 406c3</td><td></td></tr><tr><td colspan="2">Processor Cores 4</td><td></td></tr><tr><td colspan="2">Intel(R) GOP Driver [8.0.1038]</td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Total Memory 4096 MB (DDR3L)</td><td></td></tr><tr><td colspan="2">SOC Information</td><td></td></tr><tr><td colspan="2">Braswell SoC CO Stepping</td><td></td></tr><tr><td colspan="2">TXE FW Version 02.00.02.2092</td><td></td></tr><tr><td colspan="2">System Management</td><td></td></tr><tr><td colspan="2">System Date [Sun 01/01/2012]
System Time [00:00:33]</td><td></td></tr><tr><td colspan="3">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-1: BIOS Setup Main Menu

Main Menu > System Information

Table 4-2: Main Menu > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Project Version</td><td>• Info only</td><td>• ADLINK BIOS version</td></tr><tr><td>• Build Date and Time</td><td>• Info only</td><td>• Date the BIOS was built</td></tr></table>

Main Menu > Processor Information

Table 4-3: Main Menu > Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display CPU brand name</td></tr><tr><td>Max CPU Speed</td><td>Info only</td><td>Display CPU frequency</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU ID</td></tr><tr><td>Processors Cores</td><td>Info only</td><td>Display number of processor</td></tr></table>

Main Menu > VGA Firmware Version

Table 4-4: Main Menu > VGA Firmware Version

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• IGFX VBIOS Version• IGFX GOP Version</td><td>• Info only</td><td>• Display legacy VBIOS or GOP driver version</td></tr></table>

Main Menu > Memory Information

Table 4-5: Main Menu > Memory Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Total Memory</td><td>• Info only</td><td>• Display total memory information</td></tr></table>

Main Menu > SOC Information

Table 4-6: Main Menu Main Menu > SOC Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Braswell Soc</td><td>• Info only</td><td>• Display SOC stepping</td></tr><tr><td>• TXE FW Version</td><td>• Info only</td><td>• Display version of TXE</td></tr></table>

Main Menu > System Management

<table><tr><td>System Management
Version: 1.00
Overview
► Board Information
System Health
► Temperatures and Fan Speed
► Power Consumption
► Runtime Statistics
► Flags
Hardware Controls
► Power Up
► LVDS Backlight
► Smart Fan</td><td>Board Information</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-2: BIOS Setup Main Menu > System Management

Main Menu > System Management > Board Information

Table 4-7: Main Menu> System Management > Board Information

<table><tr><td>Board Information</td><td>Options</td><td>Description</td></tr><tr><td>• SEMA Firmware</td><td>• Read only</td><td>• Display SMC firmware</td></tr><tr><td>Build Date</td><td>• Read only</td><td>• Display SMC firmware build date</td></tr><tr><td>• SEMA Boot loader</td><td>• Read only</td><td>• Display SMC boot loader</td></tr><tr><td>Build Date</td><td>• Read only</td><td>• Display SMC boot loader build date</td></tr><tr><td>• Hardware Version</td><td>• Read only</td><td>• Display SMC hardware version</td></tr><tr><td>• Serial Number</td><td>• Read only</td><td>• Display SMC serial number</td></tr><tr><td>• Manufacturing Date</td><td>• Read only</td><td>• Display SMC manufacturing date</td></tr><tr><td>• Last Repair Date</td><td>• Read only</td><td>• Display SMC last repair date</td></tr><tr><td>• MAC ID</td><td>• Read only</td><td>• Display SMC MAC ID</td></tr><tr><td>• SEMA Features:</td><td>• Read only</td><td>• Display SEMA features</td></tr></table>

Main Menu > System Management > Temperatures and Fan Speed

Table 4-8: Main Menu > System Management > Temperature and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Temperatures and Fan</td><td colspan="2">• Info only</td></tr><tr><td>Board Temperatures</td><td colspan="2">• Info only</td></tr><tr><td>▷ Current</td><td>• Read only</td><td>• Display current board temperature</td></tr><tr><td>▷ Startup</td><td>• Read only</td><td>• Display board startup temperature</td></tr><tr><td>▷ Min</td><td>• Read only</td><td>• Display board min. temperature</td></tr><tr><td>▷ Max</td><td>• Read only</td><td>• Display board max. temperature</td></tr><tr><td>CPU Fan Speed</td><td>• Read only</td><td>• Display CPU fan speed</td></tr></table>

Main Menu > System Management > Power Consumption

Table 4-9: Main Menu > System Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power</td></tr><tr><td>VCC_CORE</td><td>Read only</td><td>Display actual Core voltage</td></tr><tr><td>VNN_A</td><td>Read only</td><td>Display actual SOC voltage</td></tr><tr><td>VGG_S3</td><td>Read only</td><td>Display actual GFX Core voltage</td></tr><tr><td>VDDQ</td><td>Read only</td><td>Display actual Memory voltage</td></tr><tr><td>VRTC</td><td>Read only</td><td>Display actual RTC voltage</td></tr><tr><td>V3P3_S</td><td>Read only</td><td>Display actual System voltage</td></tr><tr><td>V5Vin</td><td>Read only</td><td>Display actual VIN voltage</td></tr><tr><td>VSMARC</td><td>Read only</td><td>Display actual SMARC voltage</td></tr><tr><td>V1P5_S0</td><td>Read only</td><td>Display actual V1.50 voltage</td></tr><tr><td>V1P24_A</td><td>Read only</td><td>Display actual V1.24 voltage</td></tr><tr><td>V1P05_A</td><td>Read only</td><td>Display actual V1.05 voltage</td></tr><tr><td>V1P15_S</td><td>Read only</td><td>Display actual V1.15 voltage</td></tr><tr><td>V1P8_A</td><td>Read only</td><td>Display actual V1.80 voltage</td></tr><tr><td>V3P3_A</td><td>Read only</td><td>Display actual V3.30 voltage</td></tr></table>

Main Menu > System Management > Runtime Statistics

Table 4-10: Main Menu > System Management > Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Runtime Statistics</td><td colspan="2">• Info only</td></tr><tr><td>Total Runtime</td><td>• Read only</td><td>• The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>• Read only</td><td>• The returned value specifies the time in seconds the system is running in S0 state.• This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>• Read only</td><td>• The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>• Read only</td><td>• The Bootcounter is increased after a HW-or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>• Read only</td><td>• The boot reason is the event which causes the reboot of the system.</td></tr></table>

Main Menu > System Management > Flags

Table 4-11: Main Menu > System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td>Display the selection of current BIOS ROM</td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td>Display ATX/AT-Mode</td></tr><tr><td>Exception Code</td><td>Read only</td><td>System exception reason</td></tr></table>

Main Menu > System Management > Power Up

Table 4-12: Main Menu > System Management > Power Up

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Up</td><td colspan="2">Info only</td></tr><tr><td>Power Up watchdogNote: F12 disables the Power Up Watchdog.</td><td>EnabledDisabled</td><td>The Power-Up Watchdog resets the system after a certain amount of time after power-up.</td></tr><tr><td>Power-up ModeAttention: The Power-Up Mode only has affect, if the module is in ATX-Mode.</td><td>Turn onRemain offLast State</td><td>Turn On: The machine starts automatically when the power supply is turned on.Remain Off: To start the machine the power button has to be pressed.Last State: When powered on during a power failure the system will automatically power on when power is restored.</td></tr></table>

Main Menu > System Management > LVDS Backlight

Table 4-13: Main Menu > System Management > LVDS Backlight

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• LVDS Backlight</td><td colspan="2">• Info only</td></tr><tr><td>LVDS Backlight Bright</td><td>• 255</td><td>• The value range starts at 0 and ends at 255.</td></tr></table>

Main Menu > System Management > Smart Fan

Table 4-14: Main Menu > System Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>Select CPU fan mode</td></tr><tr><td>CPU Trigger Point 1</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>40</td><td>Specifies the temperature threshold at which the BMC turns on the CPU fan with the specified PWM level</td></tr><tr><td>PWM Level</td><td>30</td><td>Select PWM level</td></tr><tr><td>CPU Trigger Point 2</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>50</td><td>Specifies the temperature threshold at which the BMC turns on CPU fan the specified PWM level</td></tr><tr><td>PWM Level</td><td>40</td><td>Select PWM level</td></tr><tr><td>CPU Trigger Point 3</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>60</td><td>Specifies the temperature threshold at which the BMC turns on CPU fan the specified PWM level</td></tr><tr><td>PWM Level</td><td>63</td><td>Select PWM level</td></tr><tr><td>CPU Trigger Point 4</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>70</td><td>Specifies the temperature threshold at which the BMC turns on CPU fan the specified PWM level</td></tr><tr><td>PWM Level</td><td>100</td><td>Select PWM level</td></tr></table>

Main Menu > System Date and Time

Table 4-15: Main Menu > System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• System Date</td><td>• Day of Week, MM/DD/YYYY</td><td>• Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>• System Time</td><td>• HH/MM/SS</td><td>• Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# 4.1.3 Advanced Menu

This menu contains the settings for most of the user interfaces in the system. The “Advanced” menu provides configuration settings for CPU, Memory, Graphics, SATA, USB, Network, Audio, PCIe Configuration, ACPI Power Management, Serial Console, Thermal, and Miscellaneous.

![This image displays a standard safety warning sign. It features a yellow triangle with a thick black border containing a black exclamation point in the center. Below the triangle, the word 'CAUTION' is written in bold, black, uppercase letters.](.lec-bw-50-1z206-1010-200-en/3c0ad92e399d465c4c626b53f65ab0135e348b316bf1a88ab4fa991d111bfa76.jpg)

Inappropriate values for any of the following advanced settings below may cause system errors.

![Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.\nMain Advanced Security Boot Save & Exit\nCPU\nMemory\nGraphics\nSATA\nUSB\nNetwork\nPCIe Configuration\nACPI and Power Management\nSound\nSerial Port Console\nThermal\nMiscellaneous\nCPU\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.](.lec-bw-50-1z206-1010-200-en/93fab4fb6c52f8ab6dcece7b8996de0182ad9e68d3451daa050868de7241c687.jpg)

Figure 4-3: BIOS Setup Advanced Menu

# Advanced Menu > CPU

<table><tr><td colspan="2">CPU
Intel(R) Pentium(R) CPU N3700 @ 1.60GHz
CPU Signature 406c3
Microcode Patch 362
Max CPU Speed 1600 MHz
Min CPU Speed 480 MHz
Processor Cores 4
Intel HT Technology Not Supported
Intel VT-x Technology Supported
64-bit Supported</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr><tr><td colspan="2">L1 Data Cache 24 kB x 4
L1 Code Cache 32 kB x 4
L2 Cache 1024 kB x 2
L3 Cache Not Present</td><td rowspan="3">+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Intel Virtualization Technology [Enabled]</td></tr><tr><td colspan="2">CPU Processor Power Management (PPM)
EIST [Enabled]
CPU C state Report [Enabled]
DTS [Enabled]</td></tr><tr><td colspan="3">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-4: BIOS Setup Advanced Menu > CPU

Table 4-16: Advanced Menu > CPU

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU</td><td colspan="2">Info only</td></tr><tr><td>CPU Brand Name</td><td>Info only</td><td>Display CPU brand name</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU signature</td></tr><tr><td>Microcode Patch</td><td>Info only</td><td>Display microcode patch</td></tr><tr><td>Max CPU speed</td><td>Info only</td><td>Display max. CPU speed</td></tr><tr><td>Min CPU speed</td><td>Info only</td><td>Display min. CPU speed</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display number of processor cores</td></tr><tr><td>Intel HT Technology</td><td>Info only</td><td>Display Intel HT Technology support</td></tr><tr><td>Intel VT-x Technology</td><td>Info only</td><td>Display Intel VT-x Technology support</td></tr><tr><td>64-bit</td><td>Info only</td><td>Display 64-bit support</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display cache info</td></tr><tr><td>Intel Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>CPU Processor Power Management (PPM)</td><td colspan="2">Info only</td></tr><tr><td>EIST</td><td>DisabledEnabled</td><td>Enable/Disable Intel SpeedStep</td></tr><tr><td>CPU C state Report</td><td>DisabledEnabled</td><td>Enable/Disable CPU C state report to OS</td></tr><tr><td>DTS</td><td>DisabledEnabled</td><td>Enabled/Disable digital thermal sensor</td></tr></table>

# Advanced Menu > Memory

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc. Advanced</td></tr><tr><td colspan="2">Memory
Total Memory 4096 MB (DDR3L)
Memory Frequency 1600 HZ
Memory Vlotype 1.35V
Memory Slot0 4096 MB (DDR3L)</td></tr><tr><td colspan="2">SPD Write Protect [Enabled]
Max TOLUD [2 GB]</td></tr><tr><td></td><td>Enable:Writes to SMBus slave addresses AOh - AEh are disabled.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-5: BIOS Setup Advanced Menu > Memory

Table 4-17: Advanced Menu > Memory

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Memory</td><td colspan="2">• Info only</td></tr><tr><td>• Total Memory</td><td>• Info only</td><td>• Display total memory</td></tr><tr><td>• Memory Frequency</td><td>• Info only</td><td>• Display memory frequency</td></tr><tr><td>• Memory Voltage</td><td>• Info only</td><td>• Display memory vlotage</td></tr><tr><td>• Memory Slot0</td><td>• Info only</td><td>• Display DIMM#0</td></tr><tr><td>• SPD Write Protect</td><td>• Enabled• Disabled</td><td>• Enabled: Writes to SMBus slave addresses A0h – Aeh are disabled</td></tr><tr><td>• Max TOLUD</td><td>• 2 GB• 2.25 GB• 2.5 GB• 2.75 GB• 3 GB</td><td>• Maximum value of TOLUD</td></tr></table>

# Advanced Menu > Graphics

![Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.\nAdvanced\nGraphics\nIntel(R) GOP Driver (8.0.1038)\nPrimary Display (Auto)\nIntegrated Graphics Device (Enabled)\nAperture Size (256MB)\nDVMT Pre-Allocated (32M)\nDVMT Total Gfx Mem (256MB)\nLVDS Backlight Mode (BMC Mode)\n▶ AMI Graphic Output Protocol Policy\nGT - Power Management Control\nRC6(Render Standby) (Enabled)\nSwitch DDIO (HDMI)\nPrimary IGFX Boot Display (Auto)\nLCD Panel Type (Auto)\nNXP PTN3460 Configuration\nData format and Color Depth (VESA 24 bpp)\nLVDS Output Mode (Single LVDS bus)\nDE Polarity (Active High)\nVsync Polarity (Active High)\nSelect which of IGD/PCI\nGraphics device should be\nPrimary Display.\n++: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.](.lec-bw-50-1z206-1010-200-en/3c7b03496548872cd54d1853815c6ad800899022cb3a58c1e3bc464104e98014.jpg)

Figure 4-6: BIOS Setup Advanced Menu > Graphics

Table 4-18: Advanced Menu > Graphics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Graphics</td><td colspan="2">• Info only</td></tr><tr><td>• IGFX VBIOS Version</td><td colspan="2">• Info only</td></tr><tr><td>• Primary Display</td><td>• Auto• IGD• PCIE</td><td>• Select which graphics device (IGD/PCI) should be primary display</td></tr><tr><td>• Integrated Graphics Device</td><td>• Enabled• Disabled</td><td>• Enabled: Enable Integrated Graphics Device (IGD) when selected as the primary display; Disabled: Always disable IGD</td></tr><tr><td>• Aperture Size</td><td>• 256MB</td><td>• Select the aperture size</td></tr><tr><td>• DVMT Pre-Allocated</td><td>• 32M</td><td>• Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>256MB</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>LVDS Backlight Mode</td><td>BMC ModeGTT Mode</td><td>Select LVDS backlight control function.</td></tr><tr><td>AMI Graphics Output Protocol Policy[UEFI GOP only]</td><td>Submenu</td><td>User select monitor output by graphics output protocol</td></tr><tr><td>GT – Power Management Control</td><td colspan="2">Info only</td></tr><tr><td>RC6 (Render Standby)</td><td>EnabledDisabled</td><td>Enable/Disable render standby support</td></tr><tr><td>Switch DDI0</td><td>HDMIDisplay Port</td><td>DDI0 function choose to Display Port or HDMI</td></tr><tr><td>Primary IGFX Boot Display</td><td>AutoEFPLFPEFP2</td><td>Select the Video Device which will be activated during POST. This has no effect if external graphics present.Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display</td></tr><tr><td>LCD Panel Type</td><td>Auto</td><td>Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>NXP PTN3460 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr></table>

Advanced Menu > AMI Graphics Output Protocol Policy

Table 4-19: Advanced Menu > AMI Graphics Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel(R) Valley View Graphics Controller</td><td colspan="2">Info only</td></tr><tr><td>Intel(R) GOP Driver</td><td colspan="2">Info only</td></tr><tr><td>Output Select[List connect device]</td><td>HDMI1</td><td>Output Interface.</td></tr><tr><td>Brightness Setting[LFP device connect only]</td><td>255</td><td>Set GOP Brightness value.</td></tr><tr><td>BIST Enable</td><td>EnabledDisabled</td><td>Starts or stops the built-in self-test (BIST) on the integrated display panel.</td></tr></table>

# Advanced Menu > SATA

![Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.\nAdvanced\nSATA\nSATA Controller (Enabled)\nSATA Interface Speed (Gen2)\n► SATA Port Configuration\nEnable/Disable SATA Device\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.](.lec-bw-50-1z206-1010-200-en/5ebe6a88e21b00542902470bc673d46505c1d4aa996dd4a14f706f21e06e6e29.jpg)

Figure 4-7: BIOS Setup Advanced Menu > SATA

Table 4-20: Advanced Menu > SATA

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• SATA</td><td colspan="2">• Info only</td></tr><tr><td>• SATA Controller(s)</td><td>• Enabled• Disabled</td><td>• Enable/Disable SATA Device.</td></tr><tr><td>• SATA Interface Speed</td><td>• Gen1• Gen2• Gen3</td><td>• Select SATA Interface speed, CHV A1 always with Gen1 Speed.</td></tr><tr><td>• SATA Port Configuration</td><td colspan="2">• Submenu</td></tr></table>

Advanced Menu > SATA > SATA Port Configuration

Table 4-21: Advanced Menu > SATA > SATA Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• SATA Port Configuration</td><td colspan="2">• Info only</td></tr><tr><td>• Port X</td><td>• Disabled• Enabled</td><td>• Enable/Disable SATA port X.</td></tr><tr><td>• Spin Up Device</td><td>• Enabled• Disabled</td><td>• If enabled for any of ports, Staggered Spin Up will be performed, and only the drives that have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.</td></tr><tr><td>• Device Sleep Support</td><td>• Enabled• Disabled</td><td>• Enable/Disable Device Sleep Support on that port.</td></tr><tr><td>• HotPlug</td><td>• Enabled• Disabled</td><td>• Enable/Disable SATA port X hotplug.</td></tr></table>

# Advanced Menu > USB

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc. Advanced</td></tr><tr><td>USB
USB Module Version 13
USB Devices:
1 Drive, 1 Keyboard, 1 Mouse, 2 Hubs
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
USB Mass Storage Driver Support [Enabled]
Port 60/64 Emulation [Enabled]
►USB Configuration
USB hardware delays and time-outs:
USB transfer time-out [20 sec]
Device reset time-out [20 sec]
Device power-up delay [Auto]
Mass Storage Devices:
JetFlashTranscend 8GB 8.07 [Auto]</td><td>Enables Legacy USB support.
AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications.
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-8: BIOS Setup Advanced Menu > USB

Table 4-22: Advanced Menu > USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• USB</td><td colspan="2">• Info only</td></tr><tr><td>• USB Module Version</td><td colspan="2">• Info only</td></tr><tr><td>• USB Devices</td><td>• Info only</td><td>• Drives, keyboards, mouse, hubs</td></tr><tr><td>• Legacy USB Support</td><td>• Enabled• Disabled• Auto</td><td>• Enables legacy USB support.• Auto option disables legacy support if no USB devices are connected.• Disable option will keep USB devices available only for EFI applications and setup.</td></tr><tr><td>• XHCI Hand-off</td><td>• Enabled• Disabled</td><td>• This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.</td></tr><tr><td>• USB Mass Storage Driver Support</td><td>• Enabled• Disabled</td><td>• Enable/Disable USB mass storage driver support.</td></tr><tr><td>• Port 60/64 Emulation</td><td>• Disabled• Enabled</td><td>• Enables I/O port 60h/64h emulation support. This should be enabled for the complete USB keyboard legacy support for non-USB aware OSes.</td></tr><tr><td>• USB Configuration</td><td colspan="2">• Submenu</td></tr><tr><td>• USB hardware delays and time-outs:</td><td colspan="2">• Info only</td></tr><tr><td>• USB transfer time-out</td><td>• 1 sec• 5 sec• 10 sec• 20 sec</td><td>• The time-out value for control, bulk, and interrupt transfers</td></tr><tr><td>• Device reset time-out</td><td>• 10 sec• 20 sec• 30 sec• 40 sec</td><td>• USB mass storage device Start Unit command time-out.</td></tr><tr><td>• Device power-up delay</td><td>• Auto• Manual</td><td>• Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.</td></tr><tr><td>• Mass Storage Devices</td><td>• Info only</td><td>• List current USB mass storage devices.</td></tr></table>

Advanced Menu > USB > USB Configuration

Table 4-23: Advanced Menu > USB > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• USB Configuration</td><td colspan="2">• Info only</td></tr><tr><td>• XHCI Mode</td><td>• Enabled• Disabled</td><td>• Mode of operation of xHCI controller.</td></tr></table>

# Advanced Menu > Network

![Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.\nAdvanced\nNetwork\nNetwork Stack (Disabled)\nLAN Controller (Enabled)\nWake on LAN (Enabled)\nEnable/Disable UEFI Network Stack\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.](.lec-bw-50-1z206-1010-200-en/b9b8cf35faa53ebaae88761f69ff4546a9ff95ee54dee1369498da4f20ad6559.jpg)

Figure 4-9: BIOS Setup Advanced Menu > Network

Table 4-24: Advanced Menu > Network

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Network</td><td colspan="2">• Info only</td></tr><tr><td>• Network Stack</td><td>• Enabled Disabled</td><td>• Enable/Disable UEFI network stack.</td></tr><tr><td>• LAN Controller</td><td>• Enabled Disabled</td><td>• Enable/Disable LAN controller.</td></tr><tr><td>• Wake on LAN</td><td>• Disable • Enabled</td><td>• If Enabled: LAN_PWR is always on; If Disabled: LAN_PWR is off after entering Suspend mode.</td></tr></table>

# Advanced Menu > PCIe Configuration

<table><tr><td>PCIe Configuration
► PCI Express Root Port0
► PCI Express Root Port1
► PCI Express Root Port2</td><td>PCI Express Root Port0</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-10: BIOS Setup Advanced Menu > PCIe Configuration

Table 4-25: Advanced Menu > PCIe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• PCIe Configuration</td><td colspan="2">• Info only</td></tr><tr><td>• PCI Express Root Port x</td><td colspan="2">• Submenu</td></tr></table>

Advanced Menu > PCIe Configuration > PCI Express Port x

Table 4-26: Advanced Menu > PCIe Configuration > PCI Express Port x

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Port x</td><td>EnabledDisabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>ASPM</td><td>AutoDisabledL0sL1L0sL1</td><td>PCI Express Active State Power Management settings.</td></tr><tr><td>URR</td><td>DisabledEnabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>DisabledEnabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>DisabledEnabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>• CER</td><td>• Disabled• Enabled</td><td>• PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>• SEFE</td><td>• Disabled• Enabled</td><td>• Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>• SENFE</td><td>• Disabled• Enabled</td><td>• Enable or disable Root PCI Express System Error on Non-Fatal Error.</td></tr><tr><td>• SECE</td><td>• Disabled• Enabled</td><td>• Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>• PME SCI</td><td>• Disabled• Enabled</td><td>• PCI Express PME SCI Enable/Disable.</td></tr><tr><td>• Hot Plug</td><td>• Disabled• Enabled</td><td>• Enable or disable PCI Express hotplug.</td></tr><tr><td>• PCIe Speed</td><td>• Auto• Gen 2• Gen 1</td><td>• Configure PCIe port speed.</td></tr></table>

# Advanced Menu > ACPI and Power Management

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
Advanced</td></tr><tr><td>ACPI and Power Management
Enable ACPI Auto Configuration [Disabled]
Enable Hibernation [Enabled]
ACPI Sleep State [S3 (Suspend to RAM)]</td><td>Enables or Disables BIOS ACPI
Auto Configuration.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-11: BIOS Setup Advanced Menu > ACPI and Power Management

Table 4-27: Advanced Menu > ACPI and Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ACPI and Power Management</td><td colspan="2">Info only</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>EnabledDisabled</td><td>Enables or disables BIOS ACPI Auto Configuration.</td></tr><tr><td>· Enable Hibernation</td><td>· EnabledDisabled</td><td>· Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may be not effective with some OS.</td></tr><tr><td>· ACPI Sleep State</td><td>· Suspend Disabled· S3 (Suspend to RAM)</td><td>· Select the highest ACPI sleep state the system will enter when the Suspend button is pressed.</td></tr></table>

Advanced Menu > Sound

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc. Advanced</td></tr><tr><td>Sound
Audio Controller [Enabled]</td><td>Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally Enabled.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-12: BIOS Setup Advanced Menu > Sound

Table 4-28: Advanced Menu > Sound

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Sound</td><td colspan="2">• Info only</td></tr><tr><td>• Audio Controller</td><td>• Disabled• Enabled</td><td>• Control Detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally Enabled.</td></tr></table>

# Advanced Menu > Serial Port Console

<table><tr><td>Serial Port Console
PCU UART COMO
Console Redirection [Disabled]
► Console Redirection Settings
COM1(Pci Bus0,Dev30,Func3)
Console Redirection [Disabled]
► Console Redirection Settings
Legacy Console Redirection
► Legacy Console Redirection Settings
Serial Port for Out-of-Band Management/
Windows Emergency Management Services (EMS)
Console Redirection [Disabled]
► Console Redirection Settings</td><td>Console Redirection Enable or Disable.
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-13: BIOS Setup Advanced Menu > Serial Port Console

Table 4-29: Advanced Menu > Serial Port Console

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port Console</td><td colspan="2">Info only</td></tr><tr><td>PCU UART COM0</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM1 (Pci Bus0,Dev30,Func3)</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>Legacy Console Redirection</td><td colspan="2">Info only</td></tr><tr><td>► Legacy Console Redirection Settings</td><td colspan="2">• Submenu</td></tr><tr><td>• Serial Port for Out-of-Band• Management/Windows Emergency• Management Services (EMS)</td><td colspan="2">• Info only</td></tr><tr><td>► Console Redirection</td><td>• Disabled• Enabled</td><td>• Console Redirection enable or disable.</td></tr><tr><td>► Console Redirection Settings</td><td>• Submenu</td><td>• The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

Advanced Menu > Serial Port Console > Console Redirection Settings (COM0 / COM1)

Table 4-30: Advanced Menu > Serial Port Console > Console Redirection Settings (COM0 / COM1)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• COM0/COM1• Console Redirection Settings</td><td colspan="2">• Info only</td></tr><tr><td>• Terminal Type</td><td>• VT100• VT100+• VT-UTF8• ANSI</td><td>• VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. ANSI: Extended ASCII char set.</td></tr><tr><td>• Bits per second</td><td>• 9600• 19200• 38400• 57600• 115200</td><td>• Selects serial port transmission speed. The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.</td></tr><tr><td>• Data Bits</td><td>• 7• 8</td><td>• Select data bits.</td></tr><tr><td>• Parity</td><td>• None• Even• Odd• Mark• Space</td><td>• Select parity.</td></tr><tr><td>• Stop Bits</td><td>• 1• 2</td><td>• Select number of stop bits.</td></tr><tr><td>• Flow Control</td><td>• None• Hardware RTS/CTS</td><td>• Select flow control.</td></tr><tr><td>• VT-UTF8 Combo Key Support</td><td>• Disabled• Enable</td><td>• Enable VT-UTF8 combination key support for ANSI/VT100 terminals.</td></tr><tr><td>• Recorder Mode</td><td>• Disabled• Enable</td><td>• With this mode enabled only text will be sent. This is to capture terminal data.</td></tr><tr><td>• Resolution 100x31</td><td>• Disabled• Enable</td><td>• Enables or disables extended terminal resolution</td></tr><tr><td>• Legacy OS Redirection</td><td>• 80x24• 80x25</td><td>• On legacy OSes, the number of rows and columns supported by redirection</td></tr><tr><td>• Putty KeyPad</td><td>• VT100• LINUX• XTERMR6• SCO• ESCN• VT400</td><td>• Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>• Redirection After BIOS Post</td><td>• Always Enabled• BootLoader</td><td>• The Settings specify if BootLoader is selected, then legacy console redirection is disabled before booting to legacy OS. Default value is Always Enable which means legacy console redirection is enabled for legacy OS.</td></tr></table>

Advanced Menu > Serial Port Console > Legacy Console Redirection Settings (COM1)

Table 4-31: Advanced Menu > Serial Port Console > Legacy Console Redirection Settings (COM1)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Legacy Serial Redirection Port</td><td>• PCU UART COM0• COM1(Pci Bus0,Dev30,Func3)</td><td>• Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages</td></tr></table>

Advanced Menu > Serial Port Console > Console Redirection Settings (EMS)

Table 4-32: Advanced Menu > Serial Port Console > Serial Port Console Redirection Settings (EMS)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Out-of-Band Mgmt Port</td><td>PCU UART COM0COM1(Pci Bus0,Dev30,Func3)</td><td>Microsoft Windows Emergency Management Services (EMS) allows for remote management of a Windows Server OS through a serial port.</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>VT-UTF8 is the preferred terminal type for out-of-band management. The next best choice is VT100+ and then VT100. See above, in Console Redirection Settings page, for more Help with Terminal Type/Emulation.</td></tr><tr><td>Bits per second</td><td>96001920057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTSSoftware Xon/Xoff</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a &#x27;stop&#x27; signal can be sent to stop the data flow. Once the buffers are empty, a &#x27;start&#x27; signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>Data Bits</td><td colspan="2">Info only</td></tr><tr><td>Parity</td><td colspan="2">Info only</td></tr></table>

Table 4-32: Advanced Menu > Serial Port Console > Serial Port Console Redirection Settings (EMS)

<table><tr><td>• Stop Bits</td><td>• Info only</td></tr></table>

# Advanced Menu > Thermal

<table><tr><td>Thermal
CPU Temperature : +51 °
Critical Trip Point 95
Active Cooling Trip Point [BMC Default]
Passive Trip Point 85</td><td>This value controls the temperature of the ACPI critical Trip Point - the point in which the OS will shut the system off. Note: 100C is the Plan of Record(PDR) for all Intel Mobile processors.</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-14: BIOS Setup Advanced Menu > Thermal

Table 4-33: Advanced Menu > Thermal

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Thermal</td><td colspan="2">• Info only</td></tr><tr><td>• CPU Temperature</td><td colspan="2">• Info only</td></tr><tr><td>• Critical Trip Point</td><td>• Disabled• 85 C• 95 C</td><td>• This value controls the temperature of the ACPI critical Trip Point - the point in which the OS will shut the system off. Note: 100C is the Plan of Record (PDR) for all Intel Mobile processors.</td></tr><tr><td>• Active Cooling Trip Point</td><td>• Disabled• 40 C• 50 C• 60 C• 70 C• BMC Default</td><td>• Active Cooling Trip Point.</td></tr><tr><td>• Passive Trip Point</td><td>• Disabled• 90 C• 80 C</td><td>• This value controls the temperature of the ACPI critical Trip Point - the point in which the OS will begin throttling the processor.</td></tr></table>

# Advanced Menu > Miscellaneous

<table><tr><td colspan="2">Miscellaneous USB3 Clock Spread Spectrum [Enabled] Display Clock Spread Spectrum [Disabled] SATA Clock Spread Spectrum [Disabled] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCC eMMC Support (D16:F0) [Disabled] SCC SD Card Support (D18:F0) [Disabled] Internal UART [Enabled] LPSS HSUART #1 (D30:F3) [ACPI Mode]</td><td>Enable USB3 Clock Spread Spectrum feature.</td></tr><tr><td></td><td></td><td>+:- Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F9: Optimized Defaults F10: Save &amp; Exit ESC: Exit</td></tr><tr><td colspan="3">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-15: BIOS Setup Advanced Menu > Miscellaneous

Table 4-34: Advanced Menu > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Miscellaneous</td><td colspan="2">• Info only</td></tr><tr><td>• USB3 Clock Spread Spectrum</td><td>• Enabled• Disabled</td><td>• Enable USB3 Clock Spread Spectrum feature.</td></tr><tr><td>• Display Clock Spread Spectrum</td><td>• EnabledDisabled</td><td>• Enable DISPLAY Clock Spread Spectrum feature.</td></tr><tr><td>• SATA Clock Spread Spectrum</td><td>• EnabledDisabled</td><td>• Enable SATA Clock Spread Spectrum feature.</td></tr><tr><td>• SCC eMMC Support (D16:F0)</td><td>• ACPI mode• PCI mode• Disable</td><td>• SCC eMMC support enable/disable.</td></tr><tr><td>• SCC SD Card Support (D18:F0)</td><td>• ACPI mode• PCI mode• Disable</td><td>• SCC SD card support enable/disable.</td></tr><tr><td>• Internal Uart</td><td>• Disabled• Enable</td><td>• Enable/Disable Internal UART</td></tr><tr><td>• LPSS HSUART #1 (D30:F3)</td><td>• ACPI mode• PCI mode• Disable</td><td>• Enable/Disable LPSS HSUART #1 Support</td></tr></table>

# 4.1.4 Security Menu

The Security menu allows you to set User and Administrator system passwords and to retrieve secure boot information.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>Password Description
If ONLY the Administrator&#x27;s password is set, then this only limits access to Setup and is only asked for when entering Setup.
If ONLY the User&#x27;s password is set, then this is a power on password and must be entered to boot or enter Setup. In Setup the User will have Administrator rights.
The password length must be in the following range:
Minimum length 3
Maximum length 20
Administrator Password
User Password
► Secure Boot menu</td><td>Set Administrator Password
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-16: BIOS Setup Security Menu

Security Menu > Password Description

Table 4-35: Security Menu > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Administrator Password</td><td>• Enter password</td><td></td></tr><tr><td>• User Password</td><td>• Enter password</td><td></td></tr><tr><td>• Secure Boot menu</td><td>• Submenu</td><td>• Customizable Secure Boot settings.</td></tr></table>

# Security Menu > Secure Boot

<table><tr><td>System Mode</td><td>Setup</td><td rowspan="6">Secure Boot can be enabled if 1. System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled</td></tr><tr><td>Secure Boot</td><td>Not Active</td></tr><tr><td>Vendor Keys</td><td>Not Active</td></tr><tr><td>Secure Boot</td><td>[Enabled]</td></tr><tr><td>Secure Boot Mode</td><td>[Standard]</td></tr><tr><td>Key Management</td><td></td></tr><tr><td></td><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="3">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-17: BIOS Setup Security Menu > Secure Boot

Table 4-36: Security Menu > Secure Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Mode</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot</td><td colspan="2">Info only</td></tr><tr><td>Vendor Keys</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot</td><td>DisabledEnabled</td><td>Secure Boot can be enabled if:1. System running in User mode with enrolled Platform Key (PK)2. CSM function is disabled.</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode selector. &#x27;Custom&#x27; Mode enables users to change Image Execution policy and manage Secure Boot keys.</td></tr></table>

# 4.1.5 Boot Menu

The Boot menu allows you to configure how your system will boot and select the storage location from which the system boot up will occur.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
Main Advanced Security Boot Save &amp; Exit</td></tr><tr><td>Boot Configuration
Setup Prompt Timeout 6
Bootup NumLock State [On]
Quiet Boot [Enabled]</td><td>Number of seconds to wait for setup activation key.
65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Boot Option Priorities
Boot Option #1 [UEFI: JetFlashTrans...]
Boot Option #2 [UEFI: Built-in EFI ...]
Fast Boot [Disabled]</td><td></td></tr><tr><td>BOM Config [Default]</td><td></td></tr><tr><td>► CSM Configuration</td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-18: BIOS Setup Boot Menu

Table 4-37: BIOS Setup Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Boot Configuration</td><td colspan="2">• Info only</td></tr><tr><td>• Setup Prompt Timeout</td><td>• 6</td><td>• Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>• Bootup NumLock State</td><td>• On• Off</td><td>• Select the keyboard NumLock state.</td></tr><tr><td>• Quiet Boot</td><td>• Disabled• Enabled</td><td>• Enable or disables logo Quiet Boot option for OEM Logo function.</td></tr><tr><td>• Boot Option Priorities</td><td colspan="2">• Info only</td></tr><tr><td>• Fast Boot</td><td>• Disabled• Enabled</td><td>• Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect on BBS boot options.</td></tr><tr><td>• BOM Config</td><td>• Default• Legacy System• Yocto Linux</td><td>• BOM Config</td></tr><tr><td>• CSM Configuration</td><td>• Submenu</td><td>• CSM configuration: Enable/Disable, Option ROM execution settings, etc.</td></tr></table>

# Boot Menu > CSM Configuration

If more than one drive is attached to the LEC-BW, you can select from the “Boot Configuration” screen the boot order in which the drives are scanned for a bootable OS image.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
Boot</td></tr><tr><td>Compatibility Support Module Configuration</td><td>Enable/Disable CSM Support.</td></tr><tr><td>CSM Support [Enabled]</td><td></td></tr><tr><td>CSM16 Module Version 07.79</td><td></td></tr><tr><td>GateA20 Active [Upon Request]</td><td></td></tr><tr><td>INT19 Trap Response [Immediate]</td><td></td></tr><tr><td>Boot option filter [UEFI only]</td><td></td></tr><tr><td>Option ROM execution</td><td></td></tr><tr><td>Network [Do not launch]</td><td rowspan="4">+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Storage [Legacy]</td></tr><tr><td>Video [UEFI]</td></tr><tr><td>Other PCI devices [UEFI]</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-19: Boot Menu > CSM Configuration

Table 4-38: Boot Menu > CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Compatibility Support Module Configuration</td><td colspan="2">• Info</td></tr><tr><td>• CSM Support</td><td>• Enabled• Disable</td><td>• CSM Support</td></tr><tr><td>• CSM16 Module Version</td><td colspan="2">• Info only</td></tr><tr><td>• GataA20 Active</td><td>• Upon Request• Always</td><td>• GataA20 Active</td></tr><tr><td>• INT19 Trap Response</td><td>• Immediate• Postponed</td><td>• INT19 Trap Response</td></tr><tr><td>• Boot option filter</td><td>• UEFI and Legacy• Legacy only• UEFI only</td><td>• Boot option filter</td></tr><tr><td>• Option ROM execution order</td><td colspan="2">• Info only</td></tr><tr><td>• Network</td><td>• Do not launch• UEFI only• Legacy only</td><td>• Controls the execution of UEFI and legacy PXE OpROM.</td></tr><tr><td>• Storage</td><td>• Do not launch• UEFI only• Legacy only</td><td>• Controls the execution of UEFI and legacy storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and legacy video OpROM.</td></tr><tr><td>Other PCI devices</td><td>UEFI onlyLegacy only</td><td>Determines OpROM execution policy for devices other than network, storage or video.</td></tr></table>

# 4.1.6 Save & Exit Menu

Use the Save and Exit menu to save or discard BIOS setting changes, restore or save setting defaults, and retrieve certain override information.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.</td></tr><tr><td>Main Advanced Security Boot Save &amp; Exit</td><td></td></tr><tr><td>Save Options
Save Changes and Exit
Discard Changes and Exit
Save Changes and Reset
Discard Changes and Reset
Save Changes
Discard Changes
Default Options
Restore Defaults
Save as User Defaults
Restore User Defaults
Boot Override
UEFI: JetFlashTranscend 8GB 8.07, Partition 1
UEFI: Built-in EFI Shell
Launch EFI Shell from filesystem device</td><td>Exit system setup after saving the changes.
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F9: Optimized Defaults
F10: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.17.1249. Copyright (C) 2016 American Megatrends, Inc.</td></tr></table>

Figure 4-20: BIOS Setup Save and Exit Menu

Table 4-39: Save and Exit Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>• Save Options</td><td colspan="2">• Info only</td></tr><tr><td>• Save Changes and Exit</td><td>Yes No</td><td>• Exit system setup after saving the changes.</td></tr><tr><td>• Discard Changes and Exit</td><td>Yes No</td><td>• Exit system setup without saving any changes.</td></tr><tr><td>• Save Changes and Reset</td><td>Yes No</td><td>• Reset the system after saving the changes.</td></tr><tr><td>• Discard Changes and Reset</td><td>Yes No</td><td>• Reset system setup without saving any changes.</td></tr><tr><td>• Save Changes</td><td>Yes No</td><td>• Save Changes done so far to any of the setup options.</td></tr><tr><td>• Discard Changes</td><td>Yes No</td><td>• Discard Changes done so far to any of the setup options.</td></tr><tr><td>• Default Options</td><td colspan="2">• Info only</td></tr><tr><td>Restore Defaults</td><td>Yes No</td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Yes No</td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Yes No</td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td colspan="2">Info only</td></tr></table>

# 4.2 SEMA functions

Under the management of the BMC chip (Board Management Controller), the SEMA utility (Smart Embedded Management Agent) provides system control and failure protection—counting, monitoring, and measuring hardware and software events, from which the SoC can trigger corrective commands. The optional SEMA Cloud utility not only controls local events on the module but system client events on the Internet of Things (IoT.) Refer to the following bullets for a list of SEMA functions.

 Total operating hours counter Counts the time the module has been run in minutes.
 On-time minutes counter Counts the seconds since last system start.
 Temperature monitoring of CPU and Board temperature Minimum and maximum temperature values of CPU and board are stored in flash.
 Power monitor Reads the current drawn by the board and reports the nominal operating voltage.
 Power cycles counter
 Boot counter Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
Watchdog Timer Set / Reset / Disable Watchdog Timer.
 System Restart Cause Power loss / Watchdog / External Reset.
 Flash area 1kB Flash area for customer data
 Protected Flash area 128 Bytes for Keys, ID's, etc. can be stored in a write- and clear-protectable region.
? Board Identify Vendor / Board / Serial number

The SEMA Tools are available for Windows and Linux. SEMA functionality can also be used in applications. Refer to the SEMA software manual and technical manual on the ADLINK web site for more information.

# 4.2.1 Board Specific SEMA functions

# Voltages

The BMC of the LEC-BW implements a Voltage Monitor and samples several Onboard Voltages. The Voltages can be read by calling the SEMA function, “Get Voltages”. The function returns a 16-bit value divided in Hi-Byte (MSB) and Lo-Byte (LSB).

Table 4-40: BMC Voltage Monitor Values

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>---</td><td>---</td></tr><tr><td>1</td><td>+V1.0S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>2</td><td>+V1.2S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>3</td><td>+V1.8S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>4</td><td>+V3.3S</td><td>(MSB&lt;&lt;8 + LSB) * 1.100 * 3.3 / 1024</td></tr><tr><td>5</td><td>+V1.5S</td><td>(MSB&lt;&lt;8 + LSB) * 3.3 / 1024</td></tr><tr><td>6</td><td>+V5.0A</td><td>(MSB&lt;&lt;8 + LSB) * 1.833 * 3.3 / 1024</td></tr><tr><td>7</td><td>(MAINCURRENT)</td><td>Use Main Current Function</td></tr></table>

# Main Current

The BMC of the LEC-BW implements a Current Monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in Hi-Byte (MSB) and Lo-Byte (LSB). These four values represent the last four currents drawn by the board. The values are sampled every 250ms. The order of the four values is NOT in relationship to time. The access to the BMC may increase the drawn current of the whole system. In this case, you still have three samples without the influence of the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) * 8. 0 6 \mathrm{mA}
$$

# TS#-Events

TS# is activated by a temperature sensor when a device reaches its critical temperature and released when the device is back in its normal temperature range. This counter gives the user information about temperature or cooling issues. This counter is cleared when the system is removed from power. The LEC-BW only monitors the board temperature and does not support TS#-Events.

# Exception Blink Codes

In the case of an error, the BMC shows a blink code on the STATUS-LED (LED1). This error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash storage and is cleared when the power is removed. Therefore, the “Clear Exception Code”- Command is not supported.

Table 4-41: Blink Codes

&lt;table&gt;<tr><td>Exception Blink Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S3</td></tr><tr><td>5</td><td>RESET_FAIL</td></tr><tr><td>6</td><td></td></tr><tr><td>7</td><td>POWER_FAIL</td></tr><tr><td>8</td><td>LOW_VIN</td></tr><tr><td>9</td><td>NO_PWRGD_ATX</td></tr><tr><td>10</td><td>NO_PWRGD_1V0S</td></tr><tr><td>11</td><td>NO_PWRGD_1V2S</td></tr><tr><td>13</td><td>NO_PWRGD_1V8S</td></tr><tr><td>14</td><td>NO_PWRGD_3V3S</td></tr><tr><td>15</td><td>NO_PWRGD_1V5S</td></tr></table>

# BMC Flags

The BMC Flags register returns the last detected exception code since power up.

# 4.3 Watchdog Timer

The LEC-BW features three separate Watchdog Timers. One of them is integrated in the SoC and two are provided by the BMC (managed by the SEMA).

The SoC Watchdog can be configured in the BIOS or by programming the Watchdog registers. If this function is used by user application, the application has to provide all logging functionality if desired.

The BMC Watchdog activations are caused by under voltage protection. The Watchdog LED flashes after restart but only if the power supply reaches 4.2V.

# 4.4 Temperature Sensors

The LEC-BW supports two temperature sensor functions. One is offered from the SoC and one from a dedicated chip (Texas Instruments LM73) on the board.

The SoC temperature sensors can be configured by programming the appropriate SoC registers. Refer to the Thermal Management chapter in the N-series Intel processor data sheet for more information. The on-board LM73 temperature sensor is managed by the BMC and is configured through the SEMA utility.

# 4.5 Programming Examples

Programming examples can be provided based on a Linux operating system, upon request.

# Appendix A Technical Support

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in Table A-1 below. Requests for support through Ask an Expert are given the highest priorities, and usually will be addressed within one working day.

 ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the ADLINK web site at http://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK”, unique to you with access to exclusive services and account information.

 Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to the My Question area where you can check status, update your request, and access other features.
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Table A-1: Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://www.adlinktech.com/AAE/</td></tr><tr><td>Web Site</td><td>http://www.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Zhonghe DistrictNew Taipei City 235, Taiwan新北市中和區建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech ParkPudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.comADLINK Technology BeijingAddress:北京市海淀区上地东路1号盈创动力大厦E座801室(100085)Rm. 801, Power Creative E, No. 1 Shang Di East Rd.Beijing, 100085 ChinaTel:+86-10-5885-8666Fax:+86-10-5885-8626Email:market@adlinktech.com</td></tr><tr><td rowspan="6"></td><td>ADLINK Technology ShenzhenAddress:深圳市南山区科技园南区高新南七道数字技术园A1栋2楼C区(518057)2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7High-Tech Industrial Park S., Shenzhen, 518054 ChinaTel:+86-755-2643-4858Fax:+86-755-2664-6353Email:market@adlinktech.com</td></tr><tr><td>LiPPERT ADLINK Technology GmbHAddress:Hans-Thoma-Strasse 11D-68163 Mannheim, GermanyTel:+49-621-43214-0Fax:+49-621 43214-30Email:emea@adlinktech.com</td></tr><tr><td>PENTA ADLINK Technology GmbHUlrichsbergerstrasse 1794469 Deggendorf, GermanyTel:+49 (0) 991 290 94 - 10Fax:+49 (0) 991 290 94 - 29Email:emea@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (French Liaison Office)Address:6 allée de Londres, Immeuble Ceylan91940 Les Ulis, FranceTel:+33 (0) 1 60 12 35 66Fax:+33 (0) 1 60 12 35 66Email:france@adlinktech.com</td></tr><tr><td>ADLINK Technology Japan CorporationAddress:〒101-0045 東京都千代田区神田鍛冶町3-7-4神田374 ビル4FKANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,Chiyoda-ku, Tokyo 101-0045, JapanTel:+81-3-4455-3722Fax:+81-3-5209-6013Email:japan@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Korean Liaison Office)Address:경기도 성남시 분당구 수내로46번길4경동빌딩2층(수내동4-4번지)(우)463-8252F, Kyungdong B/D, 4 Sunae-ro 46 beon-gilBundang-gu, Seongnam-si, Gyeonggi-do, Korea, 13595Toll Free+82-80-800-0585Tel+82-31-786-0585Fax+82-31-786-0583Email:korea@adlinktech.com</td></tr><tr><td rowspan="4"></td><td>ADLINK Technology Singapore Pte. Ltd.Address: 84 Genting Lane #07-02A, Cityneon Design CentreSingapore 349584Tel: +65-6844-2261Fax: +65-6844-2263Email: singapore@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)Address: #50-56, First Floor, Spearhead TowersMargosa Main Road (between 16th/17th Cross)Malleswaram, Bangalore - 560 055, IndiaTel: +91-80-65605817, +91-80-42246107Fax: +91-80-23464606Email: india@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Israeli Liaison Office)Address: 27 Maskit St., Corex BuildingPO Box 12777Herzliya 4673300, IsraelTel: +972-54-632-5251Fax: +972-77-208-0230Email: israel@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (UK Liaison Office)Tel: +44 774 010 59 65Email: UK@adlinktech.com</td></tr></table>
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