# LEC-iMX6

# (Low Energy Computer on Module)

Technical Reference

P/N 50-1Z167-1010

Rev 2.00

![The image features a logo set against a black background. The logo is a cross shape with four rounded arms extending from a central point. The left arm is a solid dark green, while the top, right, and bottom arms are a lighter lime green, creating a gradient effect that transitions from the darker green on the left to the lighter green on the other sides. In the exact center of the cross is a white square cutout.](.lec-imx6-50-1z167-1010-200-en/57b611f7e3aa758ab9bbefce018621fc44cab0a223fe975344d9ad8cfb52e322.jpg)

SMARC

![Close-up of a green printed circuit board with various electronic components and gold contacts (no readable text or symbols)](.lec-imx6-50-1z167-1010-200-en/047ad3491e5c806a05f90d028d480d4b22e2cd4ce5d281c6ca6b2ba1e43afa8a.jpg)

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Reason for Change</td><td>Date</td></tr><tr><td>1.0</td><td>Initial Release</td><td>Jan/16</td></tr><tr><td>2.00</td><td>Revised camera signals in Table 4-1 on page 17; revised block diagram; other minor revisions</td><td>Jan/16</td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr></table>

ADLINK Technology, Incorporated

www.adlinktech.com

© Copyright 2014, 2015, 2016 ADLINK Technology, Incorporated

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Important Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this manual for future reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);
 Make sure to use recommended voltage and power source settings;
 Always install and operate equipment near an easily accessible electrical socketoutlet;
 Secure the power cord (do not place any object on/over the power cord);
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Table of Contents

# 1 Overview ..

1.1 Block Diagram..
1.2 Major Components (ICs).. . 2
1.3 Connectors, LEDs, and Switches . . 3
1.4 Specifications... 4
1.5 Getting Started.. . 8

# 2 Hardware .. 11

2.1 CPU . 11
2.2 Memory ......... 11
2.3 eMMC NAND Flash . 11

# 3 Interfaces . . 12

3.1 Parallel LCD Video.. . 12
3.2 18/24 Bit LVDS LCD . 12
3.3 HDMI (High-Definition Multimedia Interface) . . 13
3.4 Camera PCAM.. . 13
3.5 Camera MIPI-CSI.. . 13
3.6 PCIe .... . 13
3.7 Gigabit Ethernet . . 13
3.8 USB 2.0 Ports .. . 14
3.9 SATA... 14
3.10 I2C 14
3.11 SPI .. 14
3.12 Serial (UART)... . 15
3.13 SPDIF . 15
3.14 I2S.. . 15
3.15 CAN ...... . 15
3.16 SD/SDIO Interface ........ . 15
3.17 eMMC Interface ... 16
3.18 GPIO .. . 16
3.19 AFB Alternate Function Block. . 16
3.20 LPC Debug . . 16

# 4 Interface Signals... .. 17

4.1 SMARC Interface.. . 17
4.2 Debug (DB40)... . 25

# 5 Power and System Management .... . 26

5.1 SEMA Utility .. 26
5.2 On-Board Power Supply . 26
5.3 System States ... 26
5.4 External Power Button . 26
5.5 Reset-In Signal. 26
5.6 External Battery... 26

# Appendix A Technical Support .. .27

# 1 Overview

This initial manual version presents a general overview of the LEC-iMX6. After reviewing this document you should understand the following features of the LEC-iMX6.

 Functional Block Diagram
 Major Components (ICs) and Connectors (Locations and Descriptions)
 Specifications
 Boot Up Configuration
 Interface Signal and Power Management Definitions

NOTE: Please refer to BSP readme documents in the Quick Drive for BSP installation instructions.

# 1.1 Block Diagram

Figure 1-1 represents the component functions of the module.
![**Blocks:**\n*   314-pin SMARC Connector\n*   Freescale iMX6\n*   Memory DDR3L (4 blocks)\n*   Flash (2 blocks)\n*   eMMC (optional)\n*   40-pin Debug Connector\n*   RTC\n*   BMC\n*   LM73 Thermal Sensor\n*   USB Hub\n*   LAN PHY\n*   PCIe switch (option)\n*   SPI Flash (option)\n*   MUX\n*   PCA 9535A GPIO\n\n**Connections:**\n*   **Direct connections between 314-pin SMARC Connector and Freescale iMX6:**\n    *   Bidirectional: LCD 24-bit RGB, LVDS 24-bit (incl. DDC), HDMI (Including DDC), USB0 Host/OTG, SATA, eMMC/SDMMC (8-bit), SDIO (4-bit), PCIe, 4x UARTS (2x 4, 2x 2), 2x CAN, SPDIF, 3x I2C, 1x SPI, Boot Select (0,1,2), Force Recovery.\n    *   From 314-pin SMARC Connector to Freescale iMX6: MIPI CSI Camera, 2 lanes, PCAM (10-bit).\n\n*   **Connections via intermediary blocks:**\n    *   314-pin SMARC Connector -) USB2 Host, USB1 Host -) USB Hub -) USB -) Freescale iMX6.\n    *   314-pin SMARC Connector -) GbE -) LAN PHY -) RGMII -) Freescale iMX6.\n    *   314-pin SMARC Connector -) PCIe (dashed) -) PCIe switch (option) -) PCIe (dashed) -) Freescale iMX6.\n    *   PCIe switch (option) connects to SPI Flash (option), which connects to Freescale iMX6 (dashed).\n    *   314-pin SMARC Connector -) I2S, SPI -) MUX -) SPI/I2S -) Freescale iMX6.\n    *   314-pin SMARC Connector (-) 12x GPIO -) PCA 9535A GPIO -) 1x I2C -) Freescale iMX6.\n\n*   **Connections from Freescale iMX6 to right-side blocks:**\n    *   Bidirectional: Memory DDR3L (4 blocks), eMMC (optional), 40-pin Debug Connector, RTC, BMC.\n    *   Freescale iMX6 -) Flash -) 1x SPI -) Flash.\n\n*   **Additional connections:**\n    *   BMC (-) LM73 Thermal Sensor.\n    *   From 314-pin SMARC Connector to BMC: 1x I2C (option), Power Management, Watchdog.](.lec-imx6-50-1z167-1010-200-en/de73616e343582e1477a4a9a466cdc7e3ff3121a2a907c04bace9704af7fd627.jpg)

Figure 1-1: Functional Block Diagram

# 1.2 Major Components (ICs)

Table 1-1 lists the major integrated circuits on the LEC-iMX6, including a brief description of each IC. Figure 1-2 and Figure 1-3 show the locations of the major ICs.

Table 1-1: Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U1)</td><td>Freescale Semiconductor</td><td>i.MX 6Solo (one core, no SATA)i.MX 6Dual (two cores, SATA)i.MX 6DualLite (two cores, no SATA)i.MX 6Quad (four cores, SATA)</td><td>800 MHz, ARMCortex-A9, 40nm SoC (System on Chip)</td><td>Integrates Processor Core, Graphics and Memory Controller Hub, and I/O Hub</td></tr><tr><td>DDR3L SDRAM (U7, U8, U9, U10 [U8 and U10 on bottom side])</td><td>Micron</td><td>MT41K256M16HA</td><td>On-board DDR3L, 1.35V, 4Gb, 32Mx16x8 System Memory</td><td>Provides high-speed data transfer</td></tr><tr><td>Ethernet PHY Transceiver (U11)</td><td>Atheros</td><td>AR8035-AL1B-R</td><td>Integrated 10/100/1000 Mbps single-port, tri-speed Ethernet PHY Transceiver</td><td>Provides a standard IEEE 802.3 Ethernet interface for Ethernet transfer rates up to 400Mbps</td></tr><tr><td>eMMC, NAND Flash (U16 - on bottom side)</td><td>Micron</td><td>MTFC8GLDEA-4M-IT</td><td>MultiMediaCard Controller and NAND Flash Memory up to 64GB</td><td>Provides communication and mass data storage capabilities</td></tr></table>

![Key:\nU1 - CPU\nU7 - DDR3L SDRAM\nU9 - DDR3L SDRAM\nU11 - Ethernet Controller\nPin 1\nU7\nU4\nU9\nU11\nP1 P74 P75 P156\nLEC_iMX6_Top_Comp_b](.lec-imx6-50-1z167-1010-200-en/1bfbd69923921042b050735adce91f6e654a8a753be86076f0d092f968c9f1d8.jpg)

Figure 1-2: Component Locations (Top Side)

# Key:

U8 - DDR3L SDRAM

U10 - DDR3L SDRAM

U16 - eMMC, NAND Flash

A - Pin 1

![LEC_IMX6_Bottom_Comp_b\nU16\nU8\nU10\nS158\nS76 S75\nS1](.lec-imx6-50-1z167-1010-200-en/cc682b743e7273dbed46397c8c515dbc5e01f7353e10ac876034fa93febd9c0c.jpg)

Figure 1-3: Component Locations (Bottom Side)

# 1.3 Connectors, LEDs, and Switches

Table 1-2 describes the connectors, LEDs, and switches shown in Figure 1-4.

Table 1-2: Module Connector, LED, and Switch Descriptions

<table><tr><td>Connector, LED, Switch #</td><td>Board Access</td><td>Description</td></tr><tr><td>J1 – SMARC P-S</td><td>Top/Bottom</td><td>314-pin, MXM edge connector for Camera, Display, and I/O functions.</td></tr><tr><td>CN2</td><td>Top</td><td>40-pin connector for debug card</td></tr><tr><td>LED1</td><td>Top</td><td>Blue LED indicating system status activities for HW Reset, SW Reset, Power Up, Power Down, Reset Button, Power Button, and U-Boot_Select</td></tr><tr><td>LED2</td><td>Top</td><td>Green LED for Power On</td></tr><tr><td>LED3</td><td>Top</td><td>Red LED for Watchdog Activity</td></tr><tr><td>SW1</td><td>Top</td><td>4-pin dip switch for:U-BOOT_SELECT: 1=off, 4=on [default]1 = 4MB SPI Flash with U-BOOT+Debian installer4 = 8MB SPI Flash with U-BOOT [default]WDT Disable: 2=off, 3=on [default]&lt;img src="images/c89653f7bb567613ad2f45fb94b41dfd206b74420590cfc9111934f03aaf41cd.jpg"/&gt;</td></tr></table>

![Key:\nJ1 - SMARC Connector\nCN2 - DB40 Debug Connector\nLED1 - System Status, Blue\nLED2 - Power On, Green\nLED3 - Watchdog Activity, Red\nSW1 - U-BOOT_Select\nPin 1\nCN2\nJ1\nP74\nP75\nJ1\nSW1\nP156\nLEC_iMX6_Top_Conn_b\nLED 1 LED 2 LED 3](.lec-imx6-50-1z167-1010-200-en/66f37cefe8a4e59ba1265ce6e465c9e0ccdf832c28025b0b749e3754cc9edbd0.jpg)

Figure 1-4: Connector, LED, and Switch Locations (Top Side)

# 1.4 Specifications

# 1.4.1 Physical Specifications

Table 1-3 lists the physical dimensions of the module.

Table 1-3: Weight and Footprint Dimensions

<table><tr><td>Item</td><td>Dimension</td><td rowspan="6">Overall height is measured from the upper board surface to the top of the highest permanent component (CN2 connector) on the upper board surface. This measurement does not include the cooling solution, which can vary. The cooling solution will probably increase this dimension.</td></tr><tr><td>Weight</td><td>0.02 kg (0.05 lb)</td></tr><tr><td>Height (overall)</td><td>3.05 mm (0.12 inches)</td></tr><tr><td>Board thickness</td><td>1.27 mm (0.05 inches)</td></tr><tr><td>Width</td><td>50.00 mm (1.97 inches)</td></tr><tr><td>Length</td><td>82.00 mm (3.23 inches)</td></tr></table>

# 1.4.2 Mechanical Specifications

![Module Primary (Top) Side\n78 82\n4X Ø6\n4X Ø2.70\nTHROUGH\n12\n7.70\n6.20\n3.30\n3.10\nP1\nP74\nP75\nP156\n74 PINS\nP1 - P74\n82 PINS\nP75 - P156\n1.25 PIN P1\n39\nLEC-IMX6_mech_dmn_top_a](.lec-imx6-50-1z167-1010-200-en/ff309a71b177aed6f72aae4de29dfb11406d947fd8a3dac82e4832bab6e48862.jpg)

Figure 1-5: Mechanical Dimensions (Top Side)

NOTE: All dimensions are given in millimeters.

# 1.4.3 Power Specifications

Table 1-4 provides the power requirements for this module.

Table 1-4: Power Supply Requirements

<table><tr><td>Parameter</td><td>800MHzCharacteristics</td></tr><tr><td>Input Type</td><td>+3V to +5.25V Regulated DC voltage</td></tr><tr><td>In-rush Current</td><td>@5V:Solo: 443mADual Lite: 456mADual: 794mQuad: 813mA</td></tr><tr><td>Typical Idle Current</td><td>@ 5V:Dual: 337mQuad: 362mA</td></tr><tr><td>BIT (Burn-In Test) Current</td><td>@5VSolo: 509mADual Lite: 524mADual: 902mQuad: 907mA</td></tr></table>

Operating configurations:

 In-rush operating configuration - Typical
 Idle operating configuration - Typical
 BIT operating configuration - Typical

# 1.4.4 Environmental Specifications

Table 1-5 provides the most efficient operating and storage condition ranges required for this module.

Table 1-5: Environmental Requirements

<table><tr><td>Parameter</td><td>Conditions</td></tr><tr><td>Temperature</td><td></td></tr><tr><td>Extended</td><td>-40° to +85°C (-40° to +185°F)</td></tr><tr><td>Storage</td><td>-55° to +85°C (-67° to +185°F)</td></tr><tr><td>Humidity</td><td></td></tr><tr><td>Operating</td><td>5% to 90% relative humidity, non-condensing</td></tr><tr><td>Non-operating</td><td>5% to 95% relative humidity, non-condensing</td></tr></table>

# 1.4.5 Thermal/Cooling Requirements

The LEC-iMX6 is designed to operate at its maximum CPU speed and requires a thermal solution. ADLINK offers one cooling option described in Table 1-6.

CAUTION: The optional heat spreader plate requires another form of cooling, such as a fan. A heat spreader plate is not a complete thermal solution for the LEC-iMX6.

CAUTION: The overall system design must keep the ICs within their operating temperature specifications.

Table 1-6: ADLINK Optional Cooling Option

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Heat Spreader</td><td>Provides a simple thermal platform on which to build a cooling solution. The heat spreader is available as an optional order item.</td></tr></table>

# 1.5 Getting Started

This section describes how to configure the boot select jumpers on the LEC-BASE baseboard and how to configure U-Boot to run a Linux image.

# 1.5.1 Configure boot select jumpers

Before starting up the LEC-iMX6, the boot select jumpers on the LEC-BASE baseboard must be configured to correspond with the storage location of the U-Boot boot loader. This section also discusses boot requirements for the Operating System.

Before you boot your system, consider the storage locations of the following software:

 U-Boot boot loader (the factory default location is the onboard SPI flash)
 Linux Operating System

The storage locations (devices) of these two software packages can be the same or distinct.

1. To boot the system from a specific boot device (location of the U-Boot boot loader), the LEC-BASE boot select jumpers must be set as shown in the following photos.

![Boot Select 0\nBoot Select 1\nForce Recovery\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3719230\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3748725\n3760000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000](.lec-imx6-50-1z167-1010-200-en/4fc1f9011a8cbcf873472ea04af71beb2d1aa902a3f3063942868965d6e7588c.jpg)

![Close-up of a green printed circuit board with multiple electronic components and a highlighted section showing four gold contacts (no readable text or symbols)](.lec-imx6-50-1z167-1010-200-en/e1fc7183028c6ad16da36f7e5081dee347d74e90a848bd03e2d0d3e71f895850.jpg)

Boot from module SPI flash [factory default location]
(JP16=1-2; JP17=1-2; JP18 1-2; JP19=1-2)

![Close-up of a green printed circuit board with multiple electronic components and connectors (no readable text or symbols)](.lec-imx6-50-1z167-1010-200-en/ac8ba8c02996241b117dc9f19a1baa91ae4e28c91ddfe5efaddd37c92f18f244.jpg)

Boot from carrier SATA disk
(JP16=2-3; JP17=2-3; JP18 2-3; JP19=1-2)

![Close-up of a green printed circuit board with multiple electronic components and connectors (no readable text or symbols)](.lec-imx6-50-1z167-1010-200-en/d985b5de23e3dfc787ee18f23b7617a5a679ca753c6508ab1dbd5b2ac171ef53.jpg)

Boot from carrier SD card
(JP16=1-2; JP17=2-3; JP18 2-3; JP19=1-2)

2. The storage location of the Operating System can be set during boot up through a U-Boot command entry. Otherwise, the default setting will be used.

# 1.5.2 Verify U-Boot Configuration

To ensure U-Boot will run a Linux image from the corresponding boot device, perform the following steps.

1. Make a serial connection between the COM1 port of the LEC-iMX6 target and a host computer.
2. Open a terminal program with settings 115200 Baud, 8N1. The following screen appears.

```txt
U-Boot 2013.04-g8e0ca0f (Jul 09 2014 - 22:48:01)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
CPU: Temperature 24 C, calibration data: 0x5784ee69
Reset cause: POR
Board: ADLINK LEC-iMX6
I2C: ready
DRAM: 2 GiB
Flash: MX25L6405D, total 8 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Env: 8 KiB in 8 MiB MX25L6405D SPI
In: serial
Out: serial
Err: serial
PMIC: PFUZE100, device ID 10, revision 11
Net: FEC [PRIME], FEC using MAC address from net device

Normal Boot
Hit any key to stop autoboot: 0
U-Boot>
```

3. Press any key to interrupt and open the U-Boot command shell.
4. Enter pri at the U-Boot> command line to list all environmental variables set inside U-Boot.
5. Find the appropriate variable and run the corresponding start command. For example: run boot\_usb.

```ini
boot_uSD=set load ext2load mmc 2:1; mmc dev 1; if mmc rescan; then set bootargs mmcblk2p1 ro; else set bootargs mmcblk1p1 ro; fi; run boot
boot_usb=usb start; set load ext2load usb 3:1; set bootargs sdc1 ro; run boot
bootargs=mmcblk2p1 ro
bootcmd=run boot_uSD
bootdelay=1
bootfile=/boot/uImage
console=console=ttymxc0,115200
ethact=FEC
ethaddr=00:20:9d:23:c6:13
ethprime=FEC
fdt_high=0xffffff
fdtaddr=0x18000000
fdtfile=/boot/lec-imx6q.dtb
initrd_high=0xffffff
load=ext2load mmc 2:1
loadaddr=0x12000000
mtdparts=mtdparts=spi32764.0:384K(u-boot)ro,-(root)
stderr=serial
stdin=serial
stdout=serial

Environment size: 1289/8188 bytes
U-Boot>
```

6. To run Linux from USB by default, edit bootcmd using:

 edit bootcmd
 run boot\_usb
 save

Note: You need to enter “save” after making a change, or the new setting will be lost after the next boot.

# 2 Hardware

# 2.1 CPU

The LEC-iMX6 product family offers four standard models of the Freescale™ i.MX6 CPU: the i.MX 6Solo (1 core, 2 displays, no SATA), the i.MX 6Dual (2 cores, 3 displays, SATA), the i.MX 6DualLite (2 cores, 2 displays, no SATA), and the i.MX 6Quad (4 cores, 3 displays, SATA). LEC-iMX6 CPUs feature 32-bit ARM Cortex-A9 processor cores built on 40-nanometer process technology. The CPUs are designed for one-chip platforms, all using the same package, and are pin compatible. Refer to the CPU data sheet and reference manual at: http://www.freescale.com/webapp/sps/site/taxonomy.jsp?code=IMX6X\_SERIES.

# 2.2 Memory

The LEC-iMX6 employs one channel of 64-bit DDR3L on-board memory. Four SDRAM memory chips provide up to 32Gb of non-ECC, unbuffered, low voltage system memory. Refer to the SDRAM datasheet at: http://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125-it

# 2.3 eMMC NAND Flash

The module supports an optional on-board eMMC (Multi-Media Card) NAND chip with capacity up to 64GB and can be used as the Boot device.The data signals are routed from the NAND chip through the SDMMC pins on the SMARC connector. If the optional eMMC NAND chip is present on the module, the eMMC interface will not be available for the baseboard on the SMARC connector. Refer to the NAND Flash datasheet at: http://www.micron.com/parts/nand-flash/managed-nand/mtfc8gldea-4m-it

# 3 Interfaces

This section provides descriptions of the interfaces and signals within the SMARC P-S (Primary-Secondary) connector. The SMARC P-S connector provides the following features:

 Parallel LCD
 LVDS
 HDMI
 Camera PCAM
 Camera MIPI-CSI
 PCIe
 Gb Ethernet
 USB 2.0 (Host and OTG)
 SATA

 SPI
 Serial
 SPDIF
 I2S
 CAN
 SD/SDIO
 eMMC
 GPIO
 AFB (Alternate Function Block)
 Debug

NOTE: ADLINK Technology Inc. only supports the features/options tested and listed in this manual. The main chips used in the LEC-iMX6 may provide more features or options than are listed for the LEC-iMX6, but some of these features or options are not supported on the module and will not function as specified in the chip documentation.

# 3.1 Parallel LCD Video

The Parallel LCD interface on the LEC-iMX6 can be used in 18-Bit or 24-Bit modes at up to 225 Mpixels/sec.

The voltage level of the LCD interface is 1.8V.

The Parallel LCD interface uses the I2C interface from the i.MX 6. At the SMARC connector the signal names are I2C\_LCD\_CK and I2C\_LCD\_DAT. The I2C interface is also shared onboard with I2C\_GP\_CK and I2C\_GP\_DAT at the SMARC connector and with the PMIC I2C interface.

# 3.2 18/24 Bit LVDS LCD

The module routes single-channel LVDS output from the CPU through the following SMARC interface pins:

 1 Clock pair (S134/S135)
 4 Data pairs (S125/S126; S128/S129; S131/S132; S137/S138)

The LVDS port can support up to 165 Mpixels/sec and voltage levels of the LVDS specification.

# 3.3 HDMI (High-Definition Multimedia Interface)

The HDMI port utilizes the following HDMI pins on the SMARC interface:

 1 Clock pair (P101/P102)
 3 Data pairs (P92/P93; P95/P96; P98/P99)
 Service signals (P104-P107)

The HDMI interface is compliant with HDMI 1.4, HDMI CTS 1.4a, DVI 1.0 (with DVI-to-HDMI adapter), and HDCP 1.4. The module supports Monitor Detection for plug and unplug detection.

The voltage level of the HDMI interface is 1.8V.

# 3.4 Camera PCAM

The Parallel Camera interface supports 10-Bit video with up to 240 MHz clock speed.

The voltage level of the PCAM interface is 1.8V.

# 3.5 Camera MIPI-CSI

The LEC-iMX6 brings out signals for an MIPI CSI-2 serial camera interface. This serial camera port supports up to 1000 Mbps/lane in 1/2-lane mode.

The voltage level of the MIPI CSI-2 interface complies with the MIPI CSI specification.

# 3.6 PCIe

The module supports a PCIe port x1 lane, Gen 2.0 from the CPU, providing up to 5 Gb/s bandwidth in each direction. An optional PCIe switch IC allows for three lanes of PCIe expansion and an optional SPI Flash. The i.MX 6 PCIe includes 3 Cores: Dual Mode core, Root Complex core, and Endpoint core.

The LEC-iMX6 PCIe configurations include the following options:

 1x PCIe 1x Gen 2.0
 3x PCIe 1x Gen 2.0 using the optional PCIe switch
 Service signals per lane:

<table><tr><td>PCIE_X_CKREQ#</td><td>PCIE_X_RST#</td><td>PCIE_X_PRSNT#</td></tr></table>

 One PCIe wake-up input signal:

<table><tr><td>PCIE_WAKE#</td><td>Input</td></tr></table>

# 3.7 Gigabit Ethernet

The LEC-iMX6 uses an Ethernet PHY, which is connected to the CPU Ethernet controller with an RGMII interface. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-Te applications. The following bullets highlight the Ethernet interface:

 Operates on TCP/IP, UDP/IP, and ICMP/IP protocol data or on IP header only
 Supports IPv4 and IPv6

NOTE: The Ethernet throughput is limited to 400 Mbit/s by the Freescale SoC.

# 3.8 USB 2.0 Ports

The LEC-iMX6 provides two host USB ports and one OTG port. The two host ports are provided from a 4-port USB HUB. All Ports are fully compliant with the USB 2.0 Specification.

# 3.9 SATA

Only the Dual and Quad variants of the LEC-iMX6 module provide a SATA interface. The SATA interfaces on the Dual and Quad models comply with the following specifications.

 Serial ATA 3.0
 AHCI Revision 1.3
 AMBA 2.0 from ARM

The interface supports 1.5Gb/s and 3.0Gb/s.

# 3.10 I2C

The CPU provides three I2C master ports, and the SMARC connector provides five I2C slave ports for Camera, General Purpose, LCD, Power Management, and HDMI Control (private) interfaces. Refer to the following block diagram. The I2C interfaces operate at data rates up to 400 kbps. All I2C interfaces have 1.8V pull ups with 1k resistors.

![The diagram illustrates the interconnections between an **SMARC Connector** (left vertical block) and an **iMX6 Processor** (right vertical block) via several I2C buses and an HDMI DDC line.\n\n**Labeled Blocks:**\n*   **SMARC Connector** (Left Frame)\n*   **iMX6 Processor** (Right Frame)\n*   **PCle Switch**\n*   **RTC**\n*   **I2C PMIC**\n*   **Temp sens**\n*   **BMC** (Contains internal labels: 'I2C2', 'I2C1', 'I2C0')\n*   **DEBUG/Progr CONNECTOR**\n*   **GPIO Expander**\n\n**Connections:**\n\n1.  **I2C1 Bus:**\n    *   Connects **I2C_CAM** (Slave) on the connector to **I2C1** (Master) on the processor.\n    *   **PCle Switch** (Slave) connects via resistor **R1**.\n    *   **RTC** (Slave) connects via resistor **R2**.\n\n2.  **I2C2 Bus:**\n    *   Connects **I2C_GP** (Slave) and **I2C_LCD** (Slave) on the connector to **I2C2** (Master) on the processor.\n    *   **I2C PMIC** (Slave) connects via resistor **R3**.\n    *   **I2C_GP** connects via resistor **R4**.\n    *   **I2C_LCD** connects via resistor **R5**.\n    *   **Temp sens** (Slave) connects via a resistor labeled **RNI** (Red) with text '**Optional PMIC Master**'.\n    *   **BMC** connects via a resistor labeled **RNI** (Red) with text '**DDC Master Optional**'.\n\n3.  **I2C3 Bus:**\n    *   Connects **I2C_PM** (Slave) on the connector to **I2C3** (Master) on the processor.\n    *   **GPIO Expander** connects via resistor **R8** (Red).\n    *   **BMC** connects via resistor **R7** (Red).\n\n4.  **HDMI DDC Bus:**\n    *   Connects **HDMI_CTRL** (Slave) on the connector to **HDMI DDC** (Master) on the processor.\n\n5.  **BMC Additional Connections:**\n    *   The **BMC** block has a 'Slave' output connecting to the **DEBUG/Progr CONNECTOR**.](.lec-imx6-50-1z167-1010-200-en/1d11b64bffd26e6d42cc662acefe9fbef84e798e7c2fe750ddc79d17c55e0c30.jpg)

# 3.11 SPI

The LEC-iMX6 provides three SPI interfaces. SPI0 is multiplexed with I2S and connected to the SMARC connector. SPI1 connects directly to the SMARC connector. The internal SPI interface connects to the U-Boot flash memory devices.

The voltage levels of the SPI interfaces are 1.8V.

# 3.12 Serial (UART)

The LEC-iMX6 provides four serial interfaces: Two ports are high-speed, 4-wire ports (with TX/ RX and RTS#/CTS#), and two ports are 2-wire (with TX/RX only.) Refer to the following table.

The voltage levels of the UART interfaces are 1.8V.

<table><tr><td>i.MX6</td><td>SMARC connector</td><td>Bus width</td></tr><tr><td>UART1</td><td>SER0</td><td>4 wire bus</td></tr><tr><td>UART2</td><td>SER1</td><td>2 wire bus</td></tr><tr><td>UART5</td><td>SER2</td><td>4 wire bus</td></tr><tr><td>UART4</td><td>SER3</td><td>2 wire bus</td></tr></table>

# 3.13 SPDIF

The Sony/Philips Digital Interconnect Format (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio. Since the SPDIF internal data width is 24-bit, the eight most-significant bits of all registers return zeros. The SPDIF uses 2 wires, one data output, and one input.

The voltage level of the SPDIF interface is 1.8V

# 3.14 I2S

The LEC-iMX6 provides one I2S audio interface, and the signals are brought out through the I2S0 pins on the SMARC connector. The signals are shared with the SPI0 interface on the SMARC connector. The signal that allows switching between SPI and I2S is GPIO1\_IO3. The default state is SPI (GPIO1\_IO3 = low). When GPIO1\_IO3 = high, I2S is switched through the SMARC connector.

The voltage level of the I2S interface is 1.8V

# 3.15 CAN

The LEC-iMX6 provides two CAN (FLEXCAN) interfaces that comply with the CAN 2.0B protocol specification. Two CAN bus transceivers reside on the CPU and are not required on the module. Refer to the following table for signal designators.

<table><tr><td>i.MX6</td><td>SMARC connector</td></tr><tr><td>FLEXCAN1</td><td>CAN0</td></tr><tr><td>FLEXCAN2</td><td>CAN1</td></tr></table>

The voltage level of the CAN interface is 1.8V

# 3.16 SD/SDIO Interface

Four parallel data lines comprise the SD/SDIO interface, supporting SD Card sockets. The LEC-iMX6 provides a 4-bit transfer mode at the SMARC connector using the SDIO pins and the SD2 interface of the i.MX 6 CPU. The following modes can be selected for data transfer:

 SD/SDIO full speed mode (up to 25 MHz)
 SD/SDIO high speed mode (up to 50 MHz)
 SD/SDIO UHS-I mode (up to 208 MHz in SDR mode, up to 50 Mhz in DDR mode)

The SDIO interface can be selected as the Boot Device. The voltage level of the SD/SDIO interface is 3.3V

# 3.17 eMMC Interface

The LEC-iMX6 provides one onboard eMMC NAND Flash memory chip with a standard 8GB storage capacity (other optional storage capacities are available.) The eMMC interface has an 8-bit width and complies with the MMC system specification. The LEC-iMX6 supports a second 8-bit wide eMMC interface at the SMARC connector (pins S26-S33.)

# 3.18 GPIO

The LEC-iMX6 provides 12 GPIO signals. Seven signals (GPIO 4, 5, 6, 8, 9, 10, 11) are generated by the 9535A GPIO expander, and the remaining five signals (0, 1, 2, 3, and 7) originate from the iMX6 CPU and are designated for CAM0 and CAM1 (PWR and RST). The GPIO signals can be utilized for General Purpose IOs as well as camera enable pins and camera field input, as defined in the SMARC specification.

# 3.19 AFB Alternate Function Block

The AFB is used for an MLB (Media Local Bus) interface. The MLB is only supported in automotive and consumer parts.

# 3.20 LPC Debug

A 40-pin, front flip, DB40 connector allows access to debug and update the U-Boot boot loader, BMC, and OS code on the module. (Refer to “Debug (DB40)” on page 25.)

# 4 Interface Signals

# 4.1 SMARC Interface

Table 4-1 provides the pin signals for the SMARC P-S connector. Refer to the SMARC specification at http://www.sget.org/standards/smarc.html for definitions of the SMARC signals.

Table 4-1: SMARC P-S Connector (J1) Signal Descriptions

<table><tr><td>Pin #</td><td>Primary (Top Side)</td><td>Pin #</td><td>Secondary (Bottom Side)</td></tr><tr><td></td><td></td><td>S1</td><td>CSI0_VSYNC (Serial camera Vertical Sync input)</td></tr><tr><td>P1</td><td>Not Connected</td><td>S2</td><td>CSI0_HSYNC (Parallel camera Horizontal Sync input)</td></tr><tr><td>P2</td><td>GND</td><td>S3</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+ (CSI1 differential clock input.)</td><td>S4</td><td>CSI0_PXL_CK0 (Serial camera primary pixel clock input)</td></tr><tr><td>P4</td><td>CSI1_CK- (CSI1 differential clock input.)</td><td>S5</td><td>I2C_CAM_CK (Serial / Parallel camera support link - I2C clock)</td></tr><tr><td>P5</td><td>PCAM_DE (Parallel camera Data Enable input)</td><td>S6</td><td>CAM_MCK (Master clock output for CSI camera support (may be used for CSI0 and / or CSI1)</td></tr><tr><td>P6</td><td>PCAM_MCK (Parallel camera Master Clock output)</td><td>S7</td><td>I2C_CAM_DAT (Serial / Parallel camera support link - I2C data)</td></tr><tr><td>P7</td><td>CSI1_D0+ (CSI1 differential data input.)</td><td>S8</td><td>CSI0_CK+(CSI0 differential clock input)</td></tr><tr><td>P8</td><td>CSI1_D0- (CSI1 differential data input.)</td><td>S9</td><td>CSI0_CK-(CSI0 differential clock input)</td></tr><tr><td>P9</td><td>GND</td><td>S10</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_D1+ (CSI1 differential data input.)</td><td>S11</td><td>CSI0_D0+(CSI0 differential data input)</td></tr><tr><td>P11</td><td>CSI1_D1- (CSI1 differential data input.)</td><td>S12</td><td>CSI0_D0-(CSI0 differential data input)</td></tr><tr><td>P12</td><td>GND</td><td>S13</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_D2+ (CSI1 differential data input.)</td><td>S14</td><td>CSI0_D1+(CSI0 differential data input)</td></tr><tr><td>P14</td><td>CSI1_D2- (CSI1 differential data input.)</td><td>S15</td><td>CSI0_D1-(CSI0 differential data input)</td></tr><tr><td>P15</td><td>GND</td><td>S16</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_D3+ (CSI1 differential data input.)</td><td>S17</td><td>Not connected</td></tr><tr><td>P17</td><td>CSI1_D3- (CSI1 differential data input.)</td><td>S18</td><td>Not connected</td></tr><tr><td>P18</td><td>GND</td><td>S19</td><td>Not connected</td></tr><tr><td>P19</td><td>GBE_MDI3- (Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S20</td><td>Not connected</td></tr><tr><td>P20</td><td>GBE_MDI3+ (Bi-directional transmit/receive pair 3 to magnetics [Media Dependent Interface])</td><td>S21</td><td>Not connected</td></tr><tr><td>P21</td><td>GBE_LINK100# (Link Speed Indication LED for 100Mbps; able to sink 24mA or more carrier LED current)</td><td>S22</td><td>Not connected</td></tr><tr><td>P22</td><td>GBE_LINK1000# (Link Speed Indication LED for 1000Mbps; able to sink 24mA or more carrier LED current)</td><td>S23</td><td>Not connected</td></tr><tr><td>P23</td><td>GBE_MDI2- (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S24</td><td>Not connected</td></tr><tr><td>P24</td><td>GBE_MDI2+ (Bi-directional transmit/receive pair 2 to magnetics [Media Dependent Interface])</td><td>S25</td><td>GND</td></tr><tr><td>P25</td><td>GBE_LINK_ACT# (Link / Activity Indication LED Driven low on Link [10, 100 or 1000 mbps] Blinks on Activity; able to sink 24mA or more Carrier LED current)</td><td>S26</td><td>SDMMC_D0 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P26</td><td>GBE_MDI1- (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S27</td><td>SDMMC_D1 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P27</td><td>GBE_MDI1+ (Bi-directional transmit/receive pair 1 to magnetics [Media Dependent Interface])</td><td>S28</td><td>SDMMC_D2 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P28</td><td>GBE_CTREF (Center-Tap reference voltage for GBE0 Carrier board Ethernet magnetic [if required by the Module GBE PHY])</td><td>S29</td><td>SDMMC_D3 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P29</td><td>GBE0_MDI0- (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S30</td><td>SDMMC_D4 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P30</td><td>GBE0_MDI0+ (Bi-directional transmit/receive pair 0 to magnetics [Media Dependent Interface])</td><td>S31</td><td>SDMMC_D5 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P31</td><td>SPI0_CS1# (SPI0 Master Chip Select 1 output)</td><td>S32</td><td>SDMMC_D6 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P32</td><td>GND</td><td>S33</td><td>SDMMC_D7 (bidirectional, 8-bit data path; may be used for 4- and 1-bit wide eMMC devices as well)</td></tr><tr><td>P33</td><td>SDIO_WP (SDIO card Write Protect; 10K pull-up to 3.3V)</td><td>S34</td><td>GND</td></tr><tr><td>P34</td><td>SDIO_CMD (SDIO card Command line)</td><td>S35</td><td>SDMMC_CK (clock)</td></tr><tr><td>P35</td><td>SDIO_CD# (SDIO Card Detect; 10K pull-up to 3.3V)</td><td>S36</td><td>SDMMC_CMD (command line)</td></tr><tr><td>P36</td><td>SDIO_CK (SDIO card Clock)</td><td>S37</td><td>SDMMC_RST# (Reset signal to eMMC device)</td></tr><tr><td>P37</td><td>SDIO_PWR_EN (SDIO card Power Enable)</td><td>S38</td><td>AUDIO_MCK (Master clock output to Audio codecs)</td></tr><tr><td>P38</td><td>GND</td><td>S39</td><td>I2S0_LRCK (Left&amp; Right audio synchronization clock)</td></tr><tr><td>P39</td><td>SDIO_D0 (SDIO card 4-bit data path)</td><td>S40</td><td>I2S0_SDOUT (Digital audio Output)</td></tr><tr><td>P40</td><td>SDIO_D1 (SDIO card 4-bit data path)</td><td>S41</td><td>I2S0_SDIN (Digital audio Input)</td></tr><tr><td>P41</td><td>SDIO_D2 (SDIO card 4-bit data path)</td><td>S42</td><td>I2S0_CK (Digital audio clock)</td></tr><tr><td>P42</td><td>SDIO_D3 (SDIO card 4-bit data path)</td><td>S43</td><td>Not connected</td></tr><tr><td>P43</td><td>SPI0_CS0# (SPI0 Master Chip Select 0 output; use to select carrier SPI boot device)</td><td>S44</td><td>Not connected</td></tr><tr><td>P44</td><td>SPI0_CK (SPI0 Master Clock output)</td><td>S45</td><td>Not connected</td></tr><tr><td>P45</td><td>SPI0_DIN (SPI0 Master Data input [input to CPU, output from SPI device])</td><td>S46</td><td>Not connected</td></tr><tr><td>P46</td><td>SPI0_DO (SPI0 Master Data output [output from CPU, input to SPI device])</td><td>S47</td><td>GND</td></tr><tr><td>P47</td><td>GND</td><td>S48</td><td>I2C_GP_CK (I2C General Purpose clock signal)</td></tr><tr><td>P48</td><td>SATA0_TX+ (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S49</td><td>I2C_GP_DAT (I2C General Purpose data signal)</td></tr><tr><td>P49</td><td>SATA0_TX- (Differential SATA 0 transmit data Pair; 0.1 uF 0402 capacitor on module)</td><td>S50</td><td>Not connected</td></tr><tr><td>P50</td><td>GND</td><td>S51</td><td>Not connected</td></tr><tr><td>P51</td><td>SATA_RX+ (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S52</td><td>Not connected</td></tr><tr><td>P52</td><td>SATA_RX- (Differential SATA 0 receive data Pair; 0.1 uF 0402 capacitor on module)</td><td>S53</td><td>Not connected</td></tr><tr><td>P53</td><td>GND</td><td>S54</td><td>Not connected</td></tr><tr><td>P54</td><td>SPI1_CS0# (SPI1 Master Chip Select 0 output)</td><td>S55</td><td>Not connected</td></tr><tr><td>P55</td><td>SPI1_CS1# (SPI1 Master Chip Select 1 output)</td><td>S56</td><td>Not connected</td></tr><tr><td>P56</td><td>SPI1_CK (SPI1 Master Clock output)</td><td>S57</td><td>Not connected</td></tr><tr><td>P57</td><td>SPI1_DIN (SPI1 Master Data input [input to CPU, output from SPI device])</td><td>S58</td><td>GND</td></tr><tr><td>P58</td><td>SPI1_DO (SPI1 Master Data output [output from CPU, input to SPI device])</td><td>S59</td><td>SPDIF_OUT (Digital Audio Output)</td></tr><tr><td>P59</td><td>GND</td><td>S60</td><td>SPDIF_IN (Digital Audio Input)</td></tr><tr><td>P60</td><td>USB0+ (Differential USB0 data pair)</td><td>S61</td><td>GND</td></tr><tr><td>P61</td><td>USB0- (Differential USB0 data pair)</td><td>S62</td><td>Not connected</td></tr><tr><td>P62</td><td>USB0_EN_OC# (Pulled low by Module OD driver to disable USB0power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S63</td><td>Not connected</td></tr><tr><td>P63</td><td>USB0_VBUS_DET (USB host power detection, when this port is used as a device.)</td><td>S64</td><td>GND</td></tr><tr><td>P64</td><td>USB0_OTG_ID (USB OTG ID input, active high)</td><td>S65</td><td>AFB_DIFF1+ (maps to MLB_CP [Media Local Bus_Clock Positive] on the SOC)</td></tr><tr><td>P65</td><td>USB1+ (Differential USB1 data pair)</td><td>S66</td><td>AFB_DIFF1- (maps to MLB_CN [Media Local Bus_Clock Negative] on the SOC)</td></tr><tr><td>P66</td><td>USB1- (Differential USB1 data pair)</td><td>S67</td><td>GND</td></tr><tr><td>P67</td><td>USB1_EN_OC# (Pulled low by Module OD driver to disable USB1 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up is present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S68</td><td>AFB_DIFF2+ (maps to MLB_SP [Media Local Bus_Signal Positive] on the SOC)</td></tr><tr><td>P68</td><td>GND</td><td>S69</td><td>AFB_DIFF2- (maps to MLB_SN [Media Local Bus_Signal Negative] on the SOC)</td></tr><tr><td>P69</td><td>USB2+ (Differential USB2 data pair)</td><td>S70</td><td>GND</td></tr><tr><td>P70</td><td>USB2- (Differential USB2 data pair)</td><td>S71</td><td>AFB_DIFF3+ (maps to MLB_DP [Media Local Bus_Data Positive] on the SOC)</td></tr><tr><td>P71</td><td>USB2_EN_OC# (Pulled low by Module OD driver to disable USB2 power. Pulled low by Carrier OD driver to indicate over-current situation. A pull-up shall be present on the Module to a 3.3V rail. The pull-up rail may be switched off to conserve power if the USB port is not in use. Further details may be found in Section 4.12.4 of SMARC Specification.)</td><td>S72</td><td>AFB_DIFF3- (maps to MLB_DN [Media Local Bus_Data Negative] on the SOC)</td></tr><tr><td>P72</td><td>PCIE_C_PRSNT# (PCIe Port C present input. Pulled up or terminated on Module)</td><td>S73</td><td>GND</td></tr><tr><td>P73</td><td>PCIE_B_PRSNT# (PCIe Port B present input. Pulled up or terminated on Module)</td><td>S74</td><td>Not Connected</td></tr><tr><td>P74</td><td>PCIE_A_PRSNT# (PCIe Port A present input. Pulled up or terminated on Module)</td><td>S75</td><td>Not Connected</td></tr><tr><td></td><td>Key</td><td></td><td>Key</td></tr><tr><td>P75</td><td>PCIE_A_RST# (PCIe Port A reset output)</td><td>S76</td><td>PCIE_B_RST# (PCIe Port B reset output, active low)</td></tr><tr><td>P76</td><td>PCIE_C_CREQ# (PCIe Port C clock request input. Pulled up or terminated on Module)</td><td>S77</td><td>PCIE_C_RST# (PCIe Port A reset output, active low)</td></tr><tr><td>P77</td><td>PCIE_B_CREQ# (PCIe Port B clock request input. Pulled up or terminated on Module)</td><td>S78</td><td>PCIE_C_RX+ (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P78</td><td>PCIE_A_CREQ# (PCIe Port A clock request input. Pulled up or terminated on Module)</td><td>S79</td><td>PCIE_C_RX- (Differential PCIe Link C receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P79</td><td>GND</td><td>S80</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+ (Differential PCIe Link C reference clock output. DC coupled)</td><td>S81</td><td>PCIE_C_TX+ (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P81</td><td>PCIE_C_REFCK- (Differential PCIe Link C reference clock output. DC coupled)</td><td>S82</td><td>PCIE_C_TX- (Differential PCIe Link C transmit data pair 0. Series coupling caps are on the Module. Caps are 0402 package 0.1uF)</td></tr><tr><td>P82</td><td>GND</td><td>S83</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+ (Differential PCIe Link A reference clock output. DC coupled)</td><td>S84</td><td>PCIE_B_REFCK+ (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P84</td><td>PCIE_A_REFCK- (Differential PCIe Link A reference clock output. DC coupled)</td><td>S85</td><td>PCIE_B_REFCK- (Differential PCIe Link B reference clock output; DC coupled)</td></tr><tr><td>P85</td><td>GND</td><td>S86</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+ (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S87</td><td>PCIE_B_RX+ (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P87</td><td>PCIE_A_RX- (Differential PCIe Link A receive data pair 0. No coupling caps on Module)</td><td>S88</td><td>PCIE_B_RX- (Differential PCIe Link B receive data pair 0. No coupling caps on Module)</td></tr><tr><td>P88</td><td>GND</td><td>S89</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+ (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>S90</td><td>PCIE_B_TX+ (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P90</td><td>PCIE_A_TX- (Differential PCIe Link A transmit data pair 0. Series coupling capacitors are on the Module. 0.1 uF 0402 capacitor are on module)</td><td>P91</td><td>PCIE_B_TX- (Differential PCIe Link B transmit data pair 0. Series coupling caps are on the Module Caps are 0402 package 0.1uF)</td></tr><tr><td>P91</td><td>GND</td><td>S92</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+ (TMDS / HDMI data 2 differential pair)</td><td>S93</td><td>LCD_D0 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P93</td><td>HDMI_D2- HDMI_D2- (TMDS / HDMI data 2 differential pair)</td><td>S94</td><td>LCD_D1 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P94</td><td>GND</td><td>S95</td><td>LCD_D2 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P95</td><td>HDMI_D1+ (TMDS / HDMI data 1 differential pair)</td><td>S96</td><td>LCD_D3 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P96</td><td>HDMI_D1- (TMDS / HDMI data 1 differential pair)</td><td>S97</td><td>LCD_D4 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P97</td><td>GND</td><td>S98</td><td>LCD_D5 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P98</td><td>HDMI_D0+ (TMDS / HDMI data 0 differential pair)</td><td>S99</td><td>LCD_D6 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P99</td><td>HDMI_D0- (TMDS / HDMI data 0 differential pair)</td><td>S100</td><td>LCD_D7 (8-bit BLU color data - 18-bit display implementations leave the two LS bits (D0, D1) bit not connected)</td></tr><tr><td>P100</td><td>GND</td><td>S101</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+ (TMDS / HDMI clock output differential pair)</td><td>S102</td><td>LCD_D8 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P102</td><td>HDMI_CK- (TMDS / HDMI clock output differential pair)</td><td>S103</td><td>LCD_D9 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P103</td><td>GND</td><td>S104</td><td>LCD_D10 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P104</td><td>HDMI_HPD (HDMI Hot Plug Detect input)</td><td>S105</td><td>LCD_D11 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK (I2C clock line dedicated to HDMI)</td><td>S106</td><td>LCD_D12 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT (I2C data line dedicated to HDMI)</td><td>S107</td><td>LCD_D13 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P107</td><td>HDMI_CEC (Not Supported)</td><td>S108</td><td>LCD_D14 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P108</td><td>CAM0_PWR# (Camera 0 Power Enable, active low output)</td><td>S109</td><td>LCD_D15 (8-bit GRN color data - 18-bit display implementations leave the two LS bits (D8, D9) not connected)</td></tr><tr><td>P109</td><td>CAM1_PWR# (Camera 1 Power Enable, active low output)</td><td>S110</td><td>GND</td></tr><tr><td>P110</td><td>CAM0_RST# (Camera 0 Reset, active low output)</td><td>S111</td><td>LCD_D16 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P111</td><td>CAM1_RST# (Camera 1 Reset, active low output)</td><td>S112</td><td>LCD_D17 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P112</td><td>GPIO4 (General Purpose IO)</td><td>S113</td><td>LCD_D18 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P113</td><td>GPIO5 (General Purpose IO)</td><td>S114</td><td>LCD_D19 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P114</td><td>GPIO6 (General Purpose IO)</td><td>S115</td><td>LCD_D20 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P115</td><td>PCAM_FLD (PCAM_FLD (Field) signal input)</td><td>S116</td><td>LCD_D21 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P116</td><td>GPIO8 (General Purpose IO)</td><td>S117</td><td>LCD_D22 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P117</td><td>GPIO9 (General Purpose IO)</td><td>S118</td><td>LCD_D23 (8-bit RED color data - 18-bit display implementations leave the two LS bits (D16, D17) not connected)</td></tr><tr><td>P118</td><td>GPIO10 (General Purpose IO)</td><td>S119</td><td>GND</td></tr><tr><td>P119</td><td>GPIO11 (General Purpose IO)</td><td>S120</td><td>LCD_DE (Display Enable - signal is high during the active display line; low otherwise)</td></tr><tr><td>P120</td><td>GND</td><td>P121</td><td>LCD_VS (Vertical Sync - high pulse indicates the start of a new display frame)</td></tr><tr><td>P121</td><td>I2C_PM_CK (Power management I2C bus clock)</td><td>S122</td><td>LCD_HS (Horizontal Sync - high pulse indicates the start of a new horizontal display line)</td></tr><tr><td>P122</td><td>I2C_PM_DAT (Power management I2C bus data)</td><td>S123</td><td>LCD_PCK (Pixel Clock - display data transitions on the positive clock edge)</td></tr><tr><td>P123</td><td>BOOT_SEL0# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S124</td><td>GND</td></tr><tr><td>P124</td><td>BOOT_SEL1# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S125</td><td>LVDS0+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P125</td><td>BOOT_SEL2# (Input straps determine the Module boot device. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S126</td><td>LVDS0- (High enables panel backlight)</td></tr><tr><td>P126</td><td>RESET_OUT# (General purpose reset output to Carrier board.)</td><td>S127</td><td>LCD_BKLT_EN (High enables panel backlight)</td></tr><tr><td>P127</td><td>RESET_IN# (Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise. Pulled up on Module. Driven by OD part on Carrier.)</td><td>S128</td><td>LVDS1+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P128</td><td>POWER_BTN# (Power-button input from Carrier board. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the Module Pulled up on Module. Driven by OD part on Carrier.)</td><td>S129</td><td>LVDS1- (LVDS LCD data channel differential pair)</td></tr><tr><td>P129</td><td>SER0_TX (Asynchronous serial port data out)</td><td>S130</td><td>GND</td></tr><tr><td>P130</td><td>SER0_RX (Asynchronous serial port data in)</td><td>S131</td><td>LVDS2+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P131</td><td>SER0_RTS# (Request to Send handshake line for SER0)</td><td>S132</td><td>LVDS2- (LVDS LCD data channel differential pair)</td></tr><tr><td>P132</td><td>SER0_CTS# (Clear to Send handshake line for SER0)</td><td>S133</td><td>LCD_VDD_EN (High enables panel VDD)</td></tr><tr><td>P133</td><td>GND</td><td>S134</td><td>LVDS_CK+ (LVDS LCD differential clock pair)</td></tr><tr><td>P134</td><td>SER1_TX (Asynchronous serial port data out)</td><td>S135</td><td>LVDS_CK- (LVDS LCD differential clock pair)</td></tr><tr><td>P135</td><td>SER1_RX (Asynchronous serial port data in)</td><td>S136</td><td>GND</td></tr><tr><td>P136</td><td>SER2_TX (Asynchronous serial port data out)</td><td>S137</td><td>LVDS3+ (LVDS LCD data channel differential pair)</td></tr><tr><td>P137</td><td>SER2_RX (Asynchronous serial port data in)</td><td>S138</td><td>LVDS3- (LVDS LCD data channel differential pair)</td></tr><tr><td>P138</td><td>SER2_RTS# (Request to Send handshake line for SER2)</td><td>S139</td><td>I2C_LCD_CK (I2C clock – to read LCD display EDID EEPROMs)</td></tr><tr><td>P139</td><td>SER2_CTS# (Clear to Send handshake line for SER2)</td><td>S140</td><td>I2C_LCD_DAT (I2C data – to read LCD display EDID EEPROMs)</td></tr><tr><td>P140</td><td>SER3_TX (Asynchronous serial port data out)</td><td>S141</td><td>LCD_BKLT_PWM (Display backlight PWM control)</td></tr><tr><td>P141</td><td>SER3_RX (Asynchronous serial port data in)</td><td>S142</td><td>Not connected</td></tr><tr><td>P142</td><td>GND</td><td>S143</td><td>GND</td></tr><tr><td>P143</td><td>CAN0_TX (CAN0 Transmit output)</td><td>S144</td><td>Not connected</td></tr><tr><td>P144</td><td>CAN0_RX (CAN0 Receive input)</td><td>S145</td><td>WDT_TIME_OUT# (Watchdog Timer Output)</td></tr><tr><td>P145</td><td>CAN1_TX (CAN1 Transmit output)</td><td>S146</td><td>PCIE_WAKE (PCIe wake up interrupt to host – common to PCIe; links A, B, C – pulled up or terminated on Module)</td></tr><tr><td>P146</td><td>CAN1_RX (CAN1 Receive input)</td><td>S147</td><td>VDD_RTC (Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.See Section 7.3 RTC Voltage Rail of the SMARC specification for an important safety note on the implementation of lithium backup batteries.)</td></tr><tr><td>P147</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S148</td><td>LID# (Lid open/close indication to Module.Low indicates lid closure, which systemmayuse to initiate a sleep state. Carrier to float the line in inactive state. Active low, level sensitive. De-bounced on the ModulePulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P148</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S149</td><td>SLEEP# (Sleep indicator from Carrier board; sourced from user Sleep button or Carrier logic. Carrier to float the line in inactive state. Active low, level sensitive; de-bounced on the Module.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P149</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S150</td><td>VIN_PWR_BAD# (Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits)is notenabled while this signal is held low by the Carrier.Pulled up on Module.Driven by OD part on Carrier.)</td></tr><tr><td>P150</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S151</td><td>CHARGING# (Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P151</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S152</td><td>CHARGER_PRSNT# (Held low by Carrier if DC input for battery charger is present. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P152</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S153</td><td>CHARGER_STBY# (The Module drives this signal low when the system is in a standby power state)</td></tr><tr><td>P153</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S154</td><td>CARRIER_PWR_ON (Carrier board circuits [apart from power management and power path circuits]arepowered up until the Module asserts the CARRIER_PWR_ON signal)</td></tr><tr><td>P154</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S155</td><td>FORCE_RECOV# (Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery function, then a low on the Module FORCE_RECOV# pinmayinvoke the SOC native Force Recovery mode – such as over a Serial Port. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P155</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S156</td><td>BATLOW# (Battery low indication to Module. Carrier to float the line in inactive state. Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td>P156</td><td>VDD_IN (Module power input voltage - 3.0V min to 5.25V max)</td><td>S157</td><td>TEST# (Held low by Carrier to invoke Module vendor specific test function(s). Pulled up on Module. Driven by OD part on Carrier.)</td></tr><tr><td></td><td></td><td>S158</td><td>GND</td></tr></table>

# 4.2 Debug (DB40)

Table 4-2 lists the pin signals of the CN2 connector, which provides 40 pins, 1 row, consecutive sequence with 0.02" (0.50mm) pitch.

Table 4-2: Debug Interface Signals (CN2)
NOTE: The gray table cells denote ground.

<table><tr><td>Pin #</td><td>Signal</td><td>Interface</td></tr><tr><td>1</td><td>RESVD</td><td></td></tr><tr><td>2</td><td>SMC_STATUS</td><td>SMC Debug</td></tr><tr><td>3</td><td>Not Connected</td><td>SMC Debug</td></tr><tr><td>4</td><td>SEL_U-BOOT</td><td>SMC Debug</td></tr><tr><td>5</td><td>POSTWDT_DIS#</td><td>SMC Debug</td></tr><tr><td>6</td><td>SUS_S5#</td><td>Test Point</td></tr><tr><td>7</td><td>SUS_S4#</td><td>Test Point</td></tr><tr><td>8</td><td>SUS_S3#</td><td>Test Point</td></tr><tr><td>9</td><td>CB_PWROK</td><td>Test Point</td></tr><tr><td>10</td><td>CB_RESET#</td><td>Test Point</td></tr><tr><td>11</td><td>SYS_RESET#</td><td>Test Point</td></tr><tr><td>12</td><td>PWRBTN#</td><td>Test Point</td></tr><tr><td>13</td><td>SMC_OCD0B</td><td>SMC Program</td></tr><tr><td>14</td><td>SMC_OCD0A</td><td>SMC Program</td></tr><tr><td>15</td><td>SMC_CLK</td><td>SMC Program</td></tr><tr><td>16</td><td>SMC_DATA</td><td>SMC Program</td></tr><tr><td>17</td><td>SMC_RESET_IN#</td><td>SMC Program</td></tr><tr><td>18</td><td>SMC_FLMD0</td><td>SMC Program</td></tr><tr><td>19</td><td>SMC_RXD6</td><td>SMC Program</td></tr><tr><td>20</td><td>SMC_TXD6</td><td>SMC Program</td></tr><tr><td>21</td><td>GND</td><td></td></tr><tr><td>22</td><td>3V3_DUAL</td><td>SMC Program</td></tr><tr><td>23</td><td>3V3_SMC1</td><td>SMC Program</td></tr><tr><td>24</td><td>Not Connected</td><td></td></tr><tr><td>25</td><td>Not Connected</td><td></td></tr><tr><td>26</td><td>LPC_AD2</td><td>LPC Debug Card</td></tr><tr><td>27</td><td>LPC_AD3</td><td>LPC Debug Card</td></tr><tr><td>28</td><td>LPC_FRAME#</td><td>LPC Debug Card</td></tr><tr><td>29</td><td>CLK33_LPC</td><td>LPC Debug Card</td></tr><tr><td>30</td><td>RST#</td><td>LPC Debug Card</td></tr><tr><td>31</td><td>Not Connected</td><td></td></tr><tr><td>32</td><td>Not Connected</td><td></td></tr><tr><td>33</td><td>LPC_3V3</td><td>LPC Debug Card</td></tr><tr><td>34</td><td>SPI_U-BOOT_CLK</td><td>SPI Program</td></tr><tr><td>35</td><td>SPI_U-BOOT_MOSI</td><td>SPI Program</td></tr><tr><td>36</td><td>SPI_U-BOOT_MISO</td><td>SPI Program</td></tr><tr><td>37</td><td>SPI_U-BOOT_CS1#</td><td>SPI Program</td></tr><tr><td>38</td><td>SPI_U-BOOT_CS0#</td><td>SPI Program</td></tr><tr><td>39</td><td>GND</td><td></td></tr><tr><td>40</td><td>VCC_SPI_IN</td><td>SPI Program</td></tr></table>

# 5 Power and System Management

# 5.1 SEMA Utility

Under the management of the BMC chip (Board Management Controller), the SEMA utility (Smart Embedded Management Agent) provides system control and failure protection—counting, monitoring, and measuring hardware and software events, from which the SOC can trigger corrective commands. The optional SEMA Cloud utility not only controls local events on the module but system client events on the IoT.

# 5.2 On-Board Power Supply

The on-board power supply generates all necessary voltages from the single supply voltage range of 3V to 5.25V DC.

Externally, +5V Standby can be used instead of the on-board generated +5V Standby voltage.

# 5.3 System States

The following system states are supported: Suspend to RAM, Freeze, and Standby.

# 5.4 External Power Button

The board provides support for a power button to initiate transition from Off to On and On to Off (hold for 4 seconds to power off.)

# 5.5 Reset-In Signal

The board provides support for a reset button to restart the system.

# 5.6 External Battery

The module supports an external RTC that is powered by a battery on the baseboard.

# Appendix A Technical Support

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in Table A-1 below. Requests for support through Ask an Expert are given the highest priorities, and usually will be addressed within one working day.

 ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the ADLINK web site at http://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK”, unique to you with access to exclusive services and account information.

 Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to the My Question area where you can check status, update your request, and access other features.
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Table A-1: Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://www.adlinktech.com/AAE/</td></tr><tr><td>Web Site</td><td>http://www.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Zhonghe DistrictNew Taipei City 235, Taiwan新北市中和區建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech ParkPudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.comADLINK Technology BeijingAddress:北京市海淀区上地东路1号盈创动力大厦E座801室(100085)Rm. 801, Power Creative E, No. 1 Shang Di East Rd.Beijing, 100085 ChinaTel:+86-10-5885-8666Fax:+86-10-5885-8626Email:market@adlinktech.com</td></tr><tr><td rowspan="7"></td><td>ADLINK Technology ShenzhenAddress:深圳市南山区科技园南区高新南七道数字技术园A1栋2楼C区(518057)2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7High-Tech Industrial Park S., Shenzhen, 518054 ChinaTel:+86-755-2643-4858Fax:+86-755-2664-6353Email:market@adlinktech.com</td></tr><tr><td>LiPPERT ADLINK Technology GmbHAddress:Hans-Thoma-Strasse 11D-68163 Mannheim, GermanyTel:+49-621-43214-0Fax:+49-621 43214-30Email:emea@adlinktech.com</td></tr><tr><td>PENTA ADLINK Technology GmbHUlrichsbergerstrasse 1794469 Deggendorf, GermanyTel:+49 (0) 991 290 94 - 10Fax:+49 (0) 991 290 94 - 29Email:emea@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (French Liaison Office)Address:6 allée de Londres, Immeuble Ceylan91940 Les Ulis, FranceTel:+33 (0) 1 60 12 35 66Fax:+33 (0) 1 60 12 35 66Email:france@adlinktech.com</td></tr><tr><td>ADLINK Technology Japan CorporationAddress:〒101-0045 東京都千代田区神田鍛冶町3-7-4神田374ビル4FKANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,Chiyoda-ku, Tokyo 101-0045, JapanTel:+81-3-4455-3722Fax:+81-3-5209-6013Email:japan@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Korean Liaison Office)Address:137-881 서울시 서초구 서초대로 326, 802 (서초동, 모인터빌딩)802, Mointer B/D, 326 Seocho-daero, Seocho-Gu,Seoul 137-881, KoreaTel:+82-2-2057-0565Fax:+82-2-2057-0563Email:korea@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd.Address:84 Genting Lane #07-02A, Cityneon Design CentreSingapore 349584Tel:+65-6844-2261Fax:+65-6844-2263Email:singapore@adlinktech.com</td></tr><tr><td></td><td>ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)Address: #50-56, First Floor, Spearhead TowersMargosa Main Road (between 16th/17th Cross)Malleswaram, Bangalore - 560 055, IndiaTel: +91-80-65605817, +91-80-42246107Fax: +91-80-23464606Email: india@adlinktech.comADLINK Technology, Inc. (Israeli Liaison Office)Address: 27 Maskit St., Corex BuildingPO Box 12777Herzliya 4673300, IsraelTel: +972-54-632-5251Fax: +972-77-208-0230Email: israel@adlinktech.comADLINK Technology, Inc. (UK Liaison Office)Tel: +44 774 010 59 65Email: UK@adlinktech.com</td></tr></table>
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