# LEC-IMX95

User’s Guide

![The image displays the logo for 'NXP' set against a white background. The letters N, X, and P are stylized, interlocking, and colored in yellow-orange, brownish-grey, blue, and green. The letter 'N' is on the left, primarily yellow-orange with a brownish-grey vertical section. The central 'X' features a blue vertical section and a green vertical section. The letter 'P' is on the right, colored green with a loop.](.lec-imx95-user-manual-50m-72520-1020-12/5ea7b0f67fb876ffd89ec966ad687591b28cc8a668afb9b372ad8701b52f15fb.jpg)

![Close-up of a blue printed circuit board with integrated circuits and various electronic components (no readable text or symbols)](.lec-imx95-user-manual-50m-72520-1020-12/6fdaca741ea539fa5c9a75c31a7dc706c3d67b0b9baf96bf623b404048c49bdf.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-08-18</td><td>AL</td></tr><tr><td>1.1</td><td>Specifications updated</td><td>2025-11-05</td><td>AL</td></tr><tr><td>1.2</td><td>Specifications updated</td><td>2025-11-24</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border. Centered inside the triangle is a black exclamation point.](.lec-imx95-user-manual-50m-72520-1020-12/7e27b77fb2666c6163eb0275f7ce4449e341d542eddc3bb56b116df0e98b2117.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

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# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a digital icon featuring a red outline of a document or piece of paper against a white background. The document shape has a 'dog-ear' fold at the top-right corner. Inside the red border, there are three horizontal red bars of roughly equal length stacked vertically, representing lines of text.](.lec-imx95-user-manual-50m-72520-1020-12/2541f2cfa41dceb8e4461afd6b6503c4fc0e6b1b51debee812b101d3745bfef6.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow triangular warning sign with a white border. Centered inside the triangle is a white exclamation mark. The background is white with faint, light gray diagonal stripes visible on the left and right sides.](.lec-imx95-user-manual-50m-72520-1020-12/fa10db90ac791885cfb765607fd919544f4ff223baf303eb18e56defd83ac07e.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard warning symbol consisting of a red equilateral triangle with rounded corners and a thin black outline. Centered inside the triangle is a large, white exclamation point. The background is plain white.](.lec-imx95-user-manual-50m-72520-1020-12/65395d2c4a371bd88b9bad78461f8037d55b308b037d77758bd5d479c249ef5e.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History .....

Preface .

1. Introduction ...... . 8

LEC-IMX95.. .. 8

The SMARC Form Factor .. .

Module Feature List.. .. 9

2. Specifications ... . 10

Core System... . 10

GPU ... . 10

Display Interfaces .. 11

Camera.. . 11

Audio ... . 11

Dual Wired Ethernet... ... 12

Wi-Fi / Bluetooth .... . 12

Extension busses.. ... 12

System Storage .. ... 13

Board Controller... .. 14

Debug Header ..... . 14

FAN Control .... . 14

Power.... ... 15

3. Block Diagram .............. ... 16

4. Pinout and Signal Descriptions .... 1

Pin Summary ... . 17

Signal Terminology Descriptions... .. 18

Signal Description by Function...... . 19

The Primary Display Interface ..... .. 19

Second Display Interface ... . 23

MIPI Camera Support ....... .. 22

Audio Interfaces.... ... 24

USB Ports ..... ... 25

PCIe and SerDes .. . 27

Dual LAN Ports... ... 28

SDIO Card (4-Bit).. .. 30
SPI Interfaces.. . 31
GPIO.... . 32
CAN Bus .. ... 33
Miscellaneous .. . 34
Power and System Management .. . 34
Boot Select...
Power .. . 37
Pin to Controller Mapping Table... . 38

5. Software Support ... . 53

Early Access... . 53

Yocto.... ... 53

Android... ... 53

6. Mechanical and Thermal .. . 54

Module Dimensions . .. 54

Thermal Solutions .. ... 55

Heatspreader: HTS... . 55

Heatsink: THS... . 56

# List of Figures

Figure 1 – Module function diagram .. ... 16
Figure 2 – Module top/bottom side pin numbering .... . 17
Figure 3 – Module dimensions............ .. 54
Figure 4 – Heatspreader: HTS .. . 55
Figure 5 – Heatsink: THS .... .. 56

# 1. Introduction

# LEC-IMX95

The ADLINK LEC-IMX95 is a SMARC module based on the NXP i.MX 95 series, featuring integrated Mali graphics and an NPU.

It supports up to 16 GB of LPDDR5 memory and up to 256 GB of eMMC storage, and is available with a rugged operating temperature range and a lowpower envelope, making it ideal for mission-critical, fanless edge computing applications that require safety and reliability at all times.

# The SMARC Form Factor

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer-on-Module (CoM) specification designed for applications that require low power consumption, low cost, and high performance. The modules typically use ARM SoCs that are similar or identical to those found in many common devices, such as tablet computers and smartphones. Alternative low-power SoCs and CPUs, such as x86 processors designed for tablets and other RISC-based CPUs, may also be used. The typical power envelope of a module is under 6W.

Two module sizes are defined: 82 mm x 50 mm and 82 mm x 80 mm. Each module PCB includes 314 edge fingers that mate with a low-profile 314-pin, 0.5 mm pitch, right-angle connector. (This connector is sometimes identified as a 321-pin connector, but 7 pins are reserved for the key and therefore not used.)

The modules serve as building blocks for both portable and stationary embedded systems. The core CPU and supporting circuits — including DRAM, boot flash, power sequencing, CPU power supplies, Gigabit Ethernet (GbE), and a single-channel LVDS display transmitter — are integrated on the module. These modules are used in conjunction with application-specific carrier boards that implement additional features such as audio CODECs, touch controllers, wireless devices, and more. This modular approach enables scalability, faster time to market, and easy upgradability, while maintaining low cost, low power consumption, and compact physical size.

![The image displays a logo featuring the text 'SGeT' in a bold, sans-serif font. The letters 'S,' 'G,' and 'T' are large and colored a bright lime green. The letter 'e' is lowercase, significantly smaller, and colored a deep magenta pink. It is positioned between the 'G' and 'T,' resting slightly lower than the baseline of the uppercase letters.](.lec-imx95-user-manual-50m-72520-1020-12/be45a7d8983a29f63eac3abed53b2d8f428e8594744eec734b7b33029cc48fba.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

SMARC module and carrier specifications are available at: https://sget.org/standards/smarc/

# Module Feature List

Memory: LPDDR5 4 to 16GB solder down memory

eMMC: BGA 32 \~256 GB supporting eMMC 5.1 standard

QSPI: QSPI boot flash as BOM option

WIFI / BT: standard M.2 1216 footprint available, AW-CM276NF as BOM option to provide WIFI / BT

GPIO’s: 14 GPIO’s via MCU and CPU

LAN: Gbe built in Mac’s connected to RTL8211 PHY

POWER: standard NXP PMIC solution

Graphics: Brings LVDS0,1 / DSI / HDMI (via DSI2HDMI) to the carrier with BOM options

USB: OTG straight from SoC, Other USB’s over USB3/2 HUB, 2nd USB port to Bluetooth

AUDIO: I2S on carrier

PCIe: 2x single lane GEN3

CAN: 2x CAN FD

BOOT SELECT: Various boot supported (Sd, eMMC, Serial boot, SPI boot), managed by MCU

SECURITY: Built in HAB

All other signals follow 2.2 standards.

# 2. Specifications

# Core System

# CPU

Up to 6x ARM Cortex-A55 @2.0 GHz

1x ARM Cortex-M7 on flex domain

1x ARM M33 on low power real time domain

# Memory

Several BOM options up to 16 GB LPDDR5

# L2 Cache

Per core >32KB I-Cache, 32KB D-Cache, 64KB L2 cache

Unified > 512KB L3 cache

# security

Crypto, Tamper detection, secure clock, Secure boot, eFuse key storage, random number generator

# GPU

# GPU Core

Mali G310

# GPU Feature Support

3D GPU supporting 50 GFLOPs

OpenGL®ES 3.2

Vulkan ®1.2

OpenCL 3.0

# VPU Feature Support

• 4Kp30 H.265 and H.264 encode and decode
• 1 x JPEG Encoder
• 1 x JPEG Dec

# Display Interfaces

# MIPI DSI

1x MIPI DSI 4 lane Compliant to MIPI-DSI standard v1.2 Maximum resolution 4Kp30 (HDMI removed when using DSI)

# LVDS

Dual Channel LVDS port 18/24 bit resolutions up to 1080p60

# HDMI

The HDMI interface is derived from the on chip DSI port and goes over a DSI to HDMI bridge (build option)

# Camera

Supports one 4-lane MIPI CSI-2 input; a second 2-lane input shares the DSI interface

# Audio

Supports I2S codec for high performance

# Dual Wired Ethernet

# Primary LAN

MAC 10/100/1000 TSN Ethernet Controller on SoC with RTL8211 PHY

Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex

# Secondary LAN

MAC 10/100/1000 TSN Ethernet Controller on SoC with RTL8211 PHY

Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex

# Wi-Fi / Bluetooth

M.2 12-16 industry standard footprint with Azurewave AW-CM276NF (build option)

# Extension busses

# PCIe

2x single lane REV 3.0

# USB

2x USB3.0, 3x USB2.0 (via HUB)

# UART

Four UART interfaces SER0/2 (4W) ,1,3 (2W). Ser 2 is shared with SPI1

# CANbus

CAN0,1 supports CAN2.0B only, or a mix of CAN2.0B and CAN FD modes, with data bit rates up to 8 Mbps

# SPI

2x SPI (SPI 1 is shared with UART and is unavailable when the UART function is selected)

#

1x I2S interface with audio resolution from 16-bits to 32-bits and a sample rate of up to 192KHz (see Audio Codec support)

# I2C

Three I2C interfaces

Support for 7-bit mode
• Software programmable clock frequency of 100 kbit/s in Standard-mode,

400 kbit/s in the Fast-mode or 1 Mbit/s in Fast-mode Plus

# GPIO

14x GPIO with interrupt

# System Storage

# SDIO

1x SDIO (4-bit) compatible with SD3.0, MMC ver. 4.51 to edge connector

# eMMC

32 \~ 256 GB (build option)

Compatible with eMMC specification 5.0 and 5.1

# Board Controller

BMC lite for power sequence

SEMA BMC Error Code

<table><tr><td>Exception Code</td><td>Error Code</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_VIN</td></tr><tr><td>3</td><td>NO_SDM_RESIN_N</td></tr><tr><td>4</td><td>NO_SDM_RESIN_N</td></tr></table>

# Debug Header

JTAG

# FAN Control

Available from CPU

# Power

Power Modes: ON / OFF / SUSPEND

Power on / off behaviour same as x86 ATX (hold off boot until PWRBTN) / AT (always boot)

Voltage Input: 5.0V +/- 5%

Operating Temperatures (vs power input)

Standard Operating Temperature: 0 to 60°C commercial grade BOM (memory, eMMC, USB hub, SOC)

Extreme Rugged Operating Temperature: -40 + 85°C industrial grade BOM (memory, eMMC, USB hub, SOC)

# Environmental

Humidity: 5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating).

EMI: EN55022 Class B inside an enclosure

Shock and Vibration: HALT Testing, with test report that confirms Extended Operating Temp range during and after vibration.

Separate Shock test report to MIL-STD-202F, Method 213B, Table 213-I, Condition A.

IN ADDITION: When installed on baseboard shall operate under 18 sawtooth mechanical shocks

(3 shocks in each direction) with a peak acceleration of 40g for a duration of 18 msec each and 75g for a duration of 6 msec each.

Capable of supporting Random Vibration: MIL-STD-202F, Method 214A, Table 214-I, Condition D.

If HALT testing shows equal or better performance, a separate vibration test report is not necessary.

MTBF: 300,000 hrs (at 40 C), 100,000 hrs (at 85 C),

# 3. Block Diagram

![**Central Processor Block**\n*   **Main Block:** 'i.MX95' (Large reddish-brown background)\n*   **Internal Component 1:** '6X A55', '1X M7', '1X M33' (Yellow box, dashed border)\n*   **Internal Component 2:** 'elQ Neutron NPU' (Yellow box, dashed border)\n\n**Left-Side Interface Labels & Controllers**\n*   **Interfaces:** 'LVDS 1', 'LVDS 0 / DSI', 'HDMI', 'CSI0', 'CSI1', 'LAN0', 'LAN1', 'PCleA Gen3 x1', 'PCleB Gen3 x1', 'USB0 2.0(OTG)', 'USB1 2.0', 'USB4 2.0', 'USB5 2.0', 'USB2 3.0 gen1', 'USB3 3.0 gen1', 'CAN0', 'CAN1', 'SDIO', 'I2S', '14x GPIO', '3x I2C', 'SPI0', 'SPI1', 'SER 0,1,2,3', 'PCle_D'\n*   **Controllers/Modules:** 'DSI to HDMI' (Orange box), 'RTL8211' (Blue boxes), '5 port HUB' (Orange box), 'MUX' (Blue box), 'MCU STM32L431' (Blue box)\n\n**Right-Side Component Labels**\n*   **Memory/Storage:** 'LPDDR5 x32', 'eMMC 32~256 GB', 'QSPI'\n*   **Peripherals/Security:** 'TPM 2.0', 'AW-CM276NF WIFI / BT'\n*   **Power/Debug:** 'PMIC PF0900', 'PMIC PF5301', 'PMIC PF5302', 'DB30 -JTAG', 'EEPROM'\n\n**Connections (Text on Lines)**\n*   **Top/Left Inputs:** 'LVDS1', 'LVDS0', 'DSI/CSI0', 'RGMii', 'PCle Gen 3', 'USB 2.0', 'USB 3.0 Gen1', 'CAN', 'SDIO', 'I2S', 'GPIO', 'I2C', 'SPI', 'SPI/UART', 'UART', '10GBe SERDES'\n*   **Right Outputs:** 'SPI' (connecting to QSPI), 'I2C' (connecting to TPM 2.0), 'SDIO(wifi)', 'UART(bt)', 'I2C' (connecting to EEPROM)\n*   **Annotations/Notes:** 'BOM OPTION to CSI0 2L or DSI', 'Standard CSI1 4L', 'PCle(shared port 8)', 'USB (shared port 1)', 'SER0/2: 4-wire, SER1/3: 2-wire', 'SER2 shared with SPI1'](.lec-imx95-user-manual-50m-72520-1020-12/7e8058d81de2cb5fb40bb6254b61c6deb0601991a113afcc9796510cb9e1d056.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# Pin Summary

The below tables are a list of all signal pins on the MXM 3 connector in the standard specification of SMARC 2.1.

![Module Primary (Top) Side\n75\n82\n4XØ6\n4X Ø2.70\nTHROUGH\n12\n7.70\n6.20\n3.30\n3.10\n0\n1.25 PIN P1\n74 PINS\nP1 - P74\n82 PINS\nP75 - P156\n39](.lec-imx95-user-manual-50m-72520-1020-12/14ed2f73973f3146559248c188b9e4b61ff711057f556c329734c113b5f7b42e.jpg)

![1.00 PIN S1\n75 PINS\nS1 - S75\n83 PINS\nS76 - S158\nD\nS1\nB\nS75\nS76\nS126\nModule Primary (Bottom) Side](.lec-imx95-user-manual-50m-72520-1020-12/f172d79240a35be1d7ae7d7b9a090165f4c1d065fa47161a817212d92f453198.jpg)

Figure 2 – Module top/bottom side pin numbering

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td></td><td></td></tr><tr><td>P1</td><td>SMB_ALERT#</td></tr><tr><td>P2</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+</td></tr><tr><td>P4</td><td>CSI1_CK-</td></tr><tr><td>P5</td><td>GBE1_SDP</td></tr><tr><td>P6</td><td>GBE0_SDP</td></tr><tr><td>P7</td><td>CSI1_RX0+</td></tr><tr><td>P8</td><td>CSI1_RX0-</td></tr><tr><td>P9</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_RX1+</td></tr><tr><td>P11</td><td>CSI1_RX1-</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_RX2+</td></tr><tr><td>P14</td><td>CSI1_RX2-</td></tr><tr><td>P15</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_RX3+</td></tr><tr><td>P17</td><td>CSI1_RX3-</td></tr><tr><td>P18</td><td>GND</td></tr><tr><td>P19</td><td>GBE0_MDI3-</td></tr><tr><td>P20</td><td>GBE0_MDI3+</td></tr><tr><td>P21</td><td>GBE0_LINK_MID#</td></tr><tr><td>P22</td><td>GBE0_LINK_MAX#</td></tr><tr><td>P23</td><td>GBE0_MDI2-</td></tr><tr><td>P24</td><td>GBE0_MDI2+</td></tr><tr><td>P25</td><td>GBE0_LINK_ACT#</td></tr><tr><td>P26</td><td>GBE0_MDI1-</td></tr><tr><td>P27</td><td>GBE0_MDI1+</td></tr><tr><td>P28</td><td>GBE0_CTREF</td></tr><tr><td>P29</td><td>GBE0_MDI0-</td></tr><tr><td>P30</td><td>GBE0_MDI0+</td></tr><tr><td>P31</td><td>SPI0_CS1#</td></tr><tr><td>P32</td><td>GND</td></tr><tr><td>P33</td><td>GND</td></tr><tr><td>P34</td><td>ESPI_CS0# / SPI1_CS0#</td></tr><tr><td>P35</td><td>ESPI_CS1# / SPI1_CS1#</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S1</td><td>CSI1_TX+ / I2C_CAM1_CK</td></tr><tr><td>S2</td><td>CSI1_TX- / I2C_CAM1_DAT</td></tr><tr><td>S3</td><td>GND</td></tr><tr><td>S4</td><td>RSVD</td></tr><tr><td>S5</td><td>CSI0_TX+ / I2C_CAM0_CK</td></tr><tr><td>S6</td><td>CAM_MCK</td></tr><tr><td>S7</td><td>CSI0_TX- / I2C_CAM0_DAT</td></tr><tr><td>S8</td><td>CSI0_CK+</td></tr><tr><td>S9</td><td>CSI0_CK-</td></tr><tr><td>S10</td><td>GND</td></tr><tr><td>S11</td><td>CSI0_RX0+</td></tr><tr><td>S12</td><td>CSI0_RX0-</td></tr><tr><td>S13</td><td>GND</td></tr><tr><td>S14</td><td>CSI0_RX1+</td></tr><tr><td>S15</td><td>CSI0_RX1-</td></tr><tr><td>S16</td><td>GND</td></tr><tr><td>S17</td><td>GBE1_MDI0+</td></tr><tr><td>S18</td><td>GBE1_MDI0-</td></tr><tr><td>S19</td><td>GBE1_LINK_MID#</td></tr><tr><td>S20</td><td>GBE1_MDI1+</td></tr><tr><td>S21</td><td>GBE1_MDI1-</td></tr><tr><td>S22</td><td>GBE1_LINK1_MAX#</td></tr><tr><td>S23</td><td>GBE1_MDI2+</td></tr><tr><td>S24</td><td>GBE1_MDI2-</td></tr><tr><td>S25</td><td>GND</td></tr><tr><td>S26</td><td>GBE1_MDI3+</td></tr><tr><td>S27</td><td>GBE1_MDI3-</td></tr><tr><td>S28</td><td>GBE1_CTREF</td></tr><tr><td>S29</td><td>PCIE_D_TX+ /</td></tr><tr><td>S30</td><td>PCIE_D_TX- /</td></tr><tr><td>S31</td><td>GBE1_LINK_ACT#</td></tr><tr><td>S32</td><td>PCIE_D_RX+ /</td></tr><tr><td>S33</td><td>PCIE_D_RX- /</td></tr><tr><td>S34</td><td>GND</td></tr><tr><td>S35</td><td>USB4+</td></tr><tr><td>S36</td><td>USB4-</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P36</td><td>ESPI_CK / SPI1_CK /</td></tr><tr><td>P37</td><td>ESPI_IO_1 / SPI1_DIN /</td></tr><tr><td>P38</td><td>ESPI_IO_0 / SPI1_DO /</td></tr><tr><td>P39</td><td>GND</td></tr><tr><td>P40</td><td>USB0+</td></tr><tr><td>P41</td><td>USB0-</td></tr><tr><td>P42</td><td>USB0_EN_OC#</td></tr><tr><td>P43</td><td>USB0_VBUS_DET</td></tr><tr><td>P44</td><td>USB0_OTG_ID</td></tr><tr><td>P45</td><td>USB1+</td></tr><tr><td>P46</td><td>GND</td></tr><tr><td>P47</td><td>ESPI_CS0# / SPI1_CS0#</td></tr><tr><td>P48</td><td>ESPI_CS1# / SPI1_CS1#</td></tr><tr><td>P49</td><td>ESPI_CK / SPI1_CK /</td></tr><tr><td>P50</td><td>ESPI_IO_1 / SPI1_DIN /</td></tr><tr><td>P51</td><td>ESPI_IO_0 / SPI1_DO /</td></tr><tr><td>P52</td><td>GND</td></tr><tr><td>P53</td><td>USB0+</td></tr><tr><td>P54</td><td>USB0-</td></tr><tr><td>P55</td><td>USB0_EN_OC#</td></tr><tr><td>P56</td><td>USB0_VBUS_DET</td></tr><tr><td>P57</td><td>USB0_OTG_ID</td></tr><tr><td>P58</td><td>USB1+</td></tr><tr><td>P59</td><td>GND</td></tr><tr><td>P60</td><td>ESPI_CS0# / SPI1_CS0#</td></tr><tr><td>P61</td><td>ESPI_CS1# / SPI1_CS1#</td></tr><tr><td>P62</td><td>ESPI_CK / SPI1_CK /</td></tr><tr><td>P63</td><td>ESPI_IO_1 / SPI1_DIN /</td></tr><tr><td>P64</td><td>ESPI_IO_0 / SPI1_DO /</td></tr><tr><td>P65</td><td>GND</td></tr><tr><td>P66</td><td>USB1-</td></tr><tr><td>P67</td><td>USB1_EN_OC#</td></tr><tr><td>P68</td><td>GND</td></tr><tr><td>P69</td><td>USB2+</td></tr><tr><td>P70</td><td>USB2-</td></tr><tr><td>P71</td><td>USB2_EN_OC#</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S37</td><td>USB3_VBUS_DET</td></tr><tr><td>S38</td><td>AUDIO_MCK</td></tr><tr><td>S39</td><td>I2S0_LRCK</td></tr><tr><td>S40</td><td>I2S0_SDOUT</td></tr><tr><td>S41</td><td>I2S0_SDIN</td></tr><tr><td>S42</td><td>I2S0_CK</td></tr><tr><td>S43</td><td>ESPI_ALERT0#</td></tr><tr><td>S44</td><td>ESPI_ALERT1#</td></tr><tr><td>S45</td><td>MDIO_CLK</td></tr><tr><td>S46</td><td>MDIO_DAT</td></tr><tr><td>S47</td><td>GND</td></tr><tr><td>S48</td><td>I2C_GP_CK</td></tr><tr><td>S49</td><td>I2C_GP_DAT</td></tr><tr><td>S50</td><td>HDA_SYNC / I2S2_LRCK /</td></tr><tr><td>S51</td><td>HDA_SDO / I2S2_SDOUT /</td></tr><tr><td>S52</td><td>HDA_SDI / I2S2_SDIN /</td></tr><tr><td>S53</td><td>HDA_CK / I2S2_CK /</td></tr><tr><td>S54</td><td>SATA_ACT#</td></tr><tr><td>S55</td><td>USB5_EN_OC#</td></tr><tr><td>S56</td><td>ESPI_IO_2 / QSPI_IO_2</td></tr><tr><td>S57</td><td>ESPI_IO_3 / QSPI_IO_3</td></tr><tr><td>S58</td><td>ESPI_RESET#</td></tr><tr><td>S59</td><td>USB5+</td></tr><tr><td>S60</td><td>USB5-</td></tr><tr><td>S61</td><td>GND</td></tr><tr><td>S62</td><td>USB3_SSTX+</td></tr><tr><td>S63</td><td>USB3_SSTX-</td></tr><tr><td>S64</td><td>GND</td></tr><tr><td>S65</td><td>USB3_SSRX+</td></tr><tr><td>S66</td><td>USB3_SSRX-</td></tr><tr><td>S67</td><td>GND</td></tr><tr><td>S68</td><td>USB3+</td></tr><tr><td>S69</td><td>USB3-</td></tr><tr><td>S70</td><td>GND</td></tr><tr><td>S71</td><td>USB2_SSTX+</td></tr><tr><td>S72</td><td>USB2_SSTX-</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P72</td><td>RSVD</td></tr><tr><td>P73</td><td>RSVD</td></tr><tr><td>P74</td><td>USB3_EN_OC#</td></tr><tr><td></td><td></td></tr><tr><td></td><td>Key</td></tr><tr><td></td><td></td></tr><tr><td>P75</td><td>PCIE_A_RST#</td></tr><tr><td>P76</td><td>USB4_EN_OC#</td></tr><tr><td>P77</td><td>PCIE_B_CKREQ#</td></tr><tr><td>P78</td><td>PCIE_A_CKREQ#</td></tr><tr><td>P79</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+</td></tr><tr><td>P81</td><td>PCIE_C_REFCK-</td></tr><tr><td>P82</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+</td></tr><tr><td>P84</td><td>PCIE_A_REFCK-</td></tr><tr><td>P85</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+</td></tr><tr><td>P87</td><td>PCIE_A_RX-</td></tr><tr><td>P88</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+</td></tr><tr><td>P90</td><td>PCIE_A_TX-</td></tr><tr><td>P91</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+/</td></tr><tr><td>P93</td><td>HDMI_D2-/</td></tr><tr><td>P94</td><td>GND</td></tr><tr><td>P95</td><td>HDMI_D1+/</td></tr><tr><td>P96</td><td>HDMI_D1-/</td></tr><tr><td>P97</td><td>GND</td></tr><tr><td>P98</td><td>HDMI_D0+/</td></tr><tr><td>P99</td><td>HDMI_D0-/</td></tr><tr><td>P100</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+/</td></tr><tr><td>P102</td><td>HDMI_CK-/</td></tr><tr><td>P103</td><td>GND</td></tr><tr><td>P104</td><td>HDMI_HPD / DP1_HPD</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S73</td><td>GND</td></tr><tr><td>S74</td><td>USB2_SSRX+</td></tr><tr><td>S75</td><td>USB2_SSRX-</td></tr><tr><td></td><td></td></tr><tr><td></td><td>Key</td></tr><tr><td></td><td></td></tr><tr><td>S76</td><td>PCIE_B_RST#</td></tr><tr><td>S77</td><td>PCIE_C_RST#</td></tr><tr><td>S78</td><td>PCIE_C_RX+ /</td></tr><tr><td>S79</td><td>PCIE_C_RX- /</td></tr><tr><td>S80</td><td>GND</td></tr><tr><td>S81</td><td>PCIE_C_TX+ /</td></tr><tr><td>S82</td><td>PCIE_C_TX- /</td></tr><tr><td>S83</td><td>GND</td></tr><tr><td>S84</td><td>PCIE_B_REFCK+</td></tr><tr><td>S85</td><td>PCIE_B_REFCK-</td></tr><tr><td>S86</td><td>GND</td></tr><tr><td>S87</td><td>PCIE_B_RX+</td></tr><tr><td>S88</td><td>PCIE_B_RX-</td></tr><tr><td>S89</td><td>GND</td></tr><tr><td>S90</td><td>PCIE_B_TX+</td></tr><tr><td>S91</td><td>PCIE_B_TX-</td></tr><tr><td>S92</td><td>GND</td></tr><tr><td>S93</td><td>DP0_LANE0+</td></tr><tr><td>S94</td><td>DP0_LANE0-</td></tr><tr><td>S95</td><td>DP0_AUX_SEL</td></tr><tr><td>S96</td><td>DP0_LANE1+</td></tr><tr><td>S97</td><td>DP0_LANE1-</td></tr><tr><td>S98</td><td>DP0_HPD</td></tr><tr><td>S99</td><td>DP0_LANE2+</td></tr><tr><td>S100</td><td>DP0_LANE2-</td></tr><tr><td>S101</td><td>GND</td></tr><tr><td>S102</td><td>DP0_LANE3+</td></tr><tr><td>S103</td><td>DP0_LANE3-</td></tr><tr><td>S104</td><td>USB3_OTG_ID</td></tr><tr><td>S105</td><td>DP0_AUX+</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK /</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT /</td></tr><tr><td>P107</td><td>DP1_AUX_SEL</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR#</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR#</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST#</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST#</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST#</td></tr><tr><td>P113</td><td>GPIO5 / PWM_OUT</td></tr><tr><td>P114</td><td>GPIO6 / TACHIN</td></tr><tr><td>P115</td><td>GPIO7</td></tr><tr><td>P116</td><td>GPIO8</td></tr><tr><td>P117</td><td>GPIO9</td></tr><tr><td>P118</td><td>GPIO10</td></tr><tr><td>P119</td><td>GPIO11</td></tr><tr><td>P120</td><td>GND</td></tr><tr><td>P121</td><td>I2C_PM_CK</td></tr><tr><td>P122</td><td>I2C_PM_DAT</td></tr><tr><td>P123</td><td>BOOT_SEL0#</td></tr><tr><td>P124</td><td>BOOT_SEL1#</td></tr><tr><td>P125</td><td>BOOT_SEL2#</td></tr><tr><td>P126</td><td>RESET_OUT#</td></tr><tr><td>P127</td><td>RESET_IN#</td></tr><tr><td>P128</td><td>POWER_BTN#</td></tr><tr><td>P129</td><td>SER0_TX</td></tr><tr><td>P130</td><td>SER0_RX</td></tr><tr><td>P131</td><td>SER0_RTS#</td></tr><tr><td>P132</td><td>SER0_CTS#</td></tr><tr><td>P133</td><td>GND</td></tr><tr><td>P134</td><td>SER1_TX</td></tr><tr><td>P135</td><td>SER1_RX</td></tr><tr><td>P136</td><td>SER2_TX</td></tr><tr><td>P137</td><td>SER2_RX</td></tr><tr><td>P138</td><td>SER2_RTS#</td></tr><tr><td>P139</td><td>SER2_CTS#</td></tr><tr><td>P140</td><td>SER3_TX</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S106</td><td>DP0_AUX-</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td></tr><tr><td>S108</td><td>LVDS1_CK+ / eDP1_AUX+ /</td></tr><tr><td>S109</td><td>LVDS1_CK- / eDP1_AUX- /</td></tr><tr><td>S110</td><td>GND</td></tr><tr><td>S111</td><td>LVDS1_0+ / eDP1_TX0+ /</td></tr><tr><td>S112</td><td>LVDS1_0- / eDP1_TX0- /</td></tr><tr><td>S113</td><td>eDP1_HPD / DSI1_TE</td></tr><tr><td>S114</td><td>LVDS1_1+ / eDP1_TX1+ /</td></tr><tr><td>S115</td><td>LVDS1_1- / eDP1_TX1- /</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td></tr><tr><td>S117</td><td>LVDS1_2+ / eDP1_TX2+ /</td></tr><tr><td>S118</td><td>LVDS1_2- / eDP1_TX2- /</td></tr><tr><td>S119</td><td>GND</td></tr><tr><td>S120</td><td>LVDS1_3+ / eDP1_TX3+ /</td></tr><tr><td>S121</td><td>LVDS1_3- / eDP1_TX3- /</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S123</td><td>GPIO13</td></tr><tr><td>S124</td><td>GND</td></tr><tr><td>S125</td><td>LVDS0_0+ / eDP0_TX0+ /</td></tr><tr><td>S126</td><td>LVDS0_0- / eDP0_TX0- /</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td></tr><tr><td>S128</td><td>LVDS0_1+ / eDP0_TX1+ /</td></tr><tr><td>S129</td><td>LVDS0_1- / eDP0_TX1- /</td></tr><tr><td>S130</td><td>GND</td></tr><tr><td>S131</td><td>LVDS0_2+ / eDP0_TX2+ /</td></tr><tr><td>S132</td><td>LVDS0_2- / eDP0_TX2- /</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td></tr><tr><td>S134</td><td>LVDS0_CK+ / eDP0_AUX+ /</td></tr><tr><td>S135</td><td>LVDS0_CK- / eDP0_AUX- /</td></tr><tr><td>S136</td><td>GND</td></tr><tr><td>S137</td><td>LVDS0_3+ / eDP0_TX3+ /</td></tr><tr><td>S138</td><td>LVDS0_3- / eDP0_TX3- /</td></tr><tr><td>S139</td><td>I2C_LCD_CK</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P141</td><td>SER3_RX</td></tr><tr><td>P142</td><td>GND</td></tr><tr><td>P143</td><td>CAN0_TX</td></tr><tr><td>P144</td><td>CAN0_RX</td></tr><tr><td>P145</td><td>CAN1_TX</td></tr><tr><td>P146</td><td>CAN1_RX</td></tr><tr><td>P147</td><td>VDD_IN</td></tr><tr><td>P148</td><td>VDD_IN</td></tr><tr><td>P149</td><td>VDD_IN</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S142</td><td>GPIO12</td></tr><tr><td>S143</td><td>GND</td></tr><tr><td>S144</td><td>eDP0_HPD / DSI0_TE</td></tr><tr><td>S145</td><td>WDT_TIME_OUT#</td></tr><tr><td>S146</td><td>PCIE_WAKE#</td></tr><tr><td>S147</td><td>VDD_RTC</td></tr><tr><td>S148</td><td>LID#</td></tr><tr><td>S149</td><td>SLEEP#</td></tr><tr><td>S150</td><td>VIN_PWR_BAD#</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P150</td><td>VDD_IN</td></tr><tr><td>P151</td><td>VDD_IN</td></tr><tr><td>P152</td><td>VDD_IN</td></tr><tr><td>P153</td><td>VDD_IN</td></tr><tr><td>P154</td><td>VDD_IN</td></tr><tr><td>P155</td><td>VDD_IN</td></tr><tr><td>P156</td><td>VDD_IN</td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S151</td><td>CHARGING#</td></tr><tr><td>S152</td><td>CHARGER_PRSNT#</td></tr><tr><td>S153</td><td>CARRIER_STBY#</td></tr><tr><td>S154</td><td>CARRIER_PWR_ON</td></tr><tr><td>S155</td><td>FORCE_RECOV#</td></tr><tr><td>S156</td><td>BATLOW#</td></tr><tr><td>S157</td><td>TEST#</td></tr><tr><td>S158</td><td>GND</td></tr><tr><td></td><td></td></tr></table>

![The image displays a red icon shaped like a document or piece of paper with a folded bottom-right corner. Inside the shape are two horizontal parallel lines.](.lec-imx95-user-manual-50m-72520-1020-12/ed747ad9b53438494eb8c42097ebd05e8195527e565e5addc768746feb74d4aa.jpg)

Note: Above is the complete SMARC function set, not all signals are available.

# 4.2 Signal Terminology Descriptions

Signals described in the specification but not supported on the LEC-IMX95 are marked with STRIKETHROUGH.

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional input/output</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>PU</td><td>PU (pull-up) resistor</td></tr><tr><td>PD</td><td>PD (pull-down) resistor</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analogue signalling for gigabit media dependent interface</td></tr><tr><td>DP</td><td>Low voltage differential signal for DisplayPort interface</td></tr><tr><td>D-PHY</td><td>Low voltage differential signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>M-PHY</td><td>Low voltage differential signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS</td><td>Low voltage differential signal for LCD displays</td></tr><tr><td>PCIE</td><td>Low voltage differential signal for PCIe</td></tr><tr><td>SATA</td><td>Low voltage differential signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition minimized differential signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signalling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>VDD_IN</td><td>Main power source from Carrier to Module</td></tr><tr><td>3.3V</td><td>3.3V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>Sleep</td><td>Module is in its lowest power state</td></tr><tr><td>Runtime</td><td>Module is full on. CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>Standby</td><td>Module is in standby state or higher</td></tr></table>

# 4.3 Signal Description by Function

# The Primary Display Interface

LVDS and DSI are both supported on this module; eDP is not supported. LVDS includes both Channel 0 and Channel 1. DSI0 supports 4 lanes and is muxed with LVDS0. The tables below show which display ports are supported on this particular module.

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S125</td><td>LVDS0_0+</td><td>DSIO_D0+</td><td>eDP0_TX0+</td></tr><tr><td>S126</td><td>LVDS0_0-</td><td>DSIO_D0-</td><td>eDP0_TX0-</td></tr><tr><td>S128</td><td>LVDS0_1+</td><td>DSIO_D1+</td><td>eDP0_TX1+</td></tr><tr><td>S129</td><td>LVDS0_1 -</td><td>DSIO_D1-</td><td>eDP0_TX1-</td></tr><tr><td>S131</td><td>LVDS0_2+</td><td>DSIO_D2+</td><td>eDP0_TX2+</td></tr><tr><td>S132</td><td>LVDS0_2-</td><td>DSIO_D2-</td><td>eDP0_TX2-</td></tr><tr><td>S137</td><td>LVDS0_3+</td><td>DSIO_D3+</td><td>eDP0_TX3+</td></tr><tr><td>S138</td><td>LVDS0_3-</td><td>DSIO_D3-</td><td>eDP0_TX3-</td></tr><tr><td>S134</td><td>LVDS0_CK+</td><td>DSIO_CLK+</td><td>eDP0_AUX+</td></tr><tr><td>S135</td><td>LVDS0_CK-</td><td>DSIO_CLK-</td><td>eDP0_AUX-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td></tr><tr><td>S144</td><td></td><td>DSIO_TE</td><td>eDP0_HPD</td></tr></table>

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S111</td><td>LVDS1_0+</td><td>DSI1_D0+</td><td>eDP1_TX0+</td></tr><tr><td>S112</td><td>LVDS1_0-</td><td>DSI1_D0-</td><td>eDP1_TX0-</td></tr><tr><td>S114</td><td>LVDS1_1+</td><td>DSI1_D1+</td><td>eDP1_TX1+</td></tr><tr><td>S115</td><td>LVDS1_1 -</td><td>DSI1_D1-</td><td>eDP1_TX1-</td></tr><tr><td>S117</td><td>LVDS1_2+</td><td>DSI1_D2+</td><td>eDP1_TX2+</td></tr><tr><td>S118</td><td>LVDS1_2-</td><td>DSI1_D2-</td><td>eDP1_TX2-</td></tr><tr><td>S120</td><td>LVDS1_3+</td><td>DSI1_D3+</td><td>eDP1_TX3+</td></tr><tr><td>S121</td><td>LVDS1_3-</td><td>DSI1_D3-</td><td>eDP1_TX3-</td></tr><tr><td>S108</td><td>LVDS1_CK+</td><td>DSI1_CLK+</td><td>eDP1_AUX+</td></tr><tr><td>S109</td><td>LVDS1_CK-</td><td>DSI1_CLK-</td><td>eDP1_AUX-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S113</td><td></td><td>DSI1_TE</td><td>eDP1_HPD</td></tr></table>

<table><tr><td>S139</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td></tr></table>

4.3.1.1 LVDS0/LVDS1 Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>LVDS0_0+</td><td>S125</td><td rowspan="8">Primary LVDS Channel Differential Pair Data Lines</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">100 Ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_0-</td><td>S126</td></tr><tr><td>LVDS0_1+</td><td>S128</td></tr><tr><td>LVDS0_1 -</td><td>S129</td></tr><tr><td>LVDS0_2+</td><td>S131</td></tr><tr><td>LVDS0_2-</td><td>S132</td></tr><tr><td>LVDS0_3+</td><td>S137</td></tr><tr><td>LVDS0_3-</td><td>S138</td></tr><tr><td>LVDS0_CK+</td><td>S134</td><td rowspan="2">Primary LVDS channel differential pair clock lines</td><td rowspan="2">O LVDS LCD</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">100 Ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_CK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary LVDS channel power enable;, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary LVDS channel backlight enable;, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary LVDS channel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through Pulse Width Modulation (PWM)</td></tr></table>

<table><tr><td>LVDS1_0+</td><td>S111</td><td rowspan="8">Secondary LVDS channel differential pair data lines</td><td rowspan="8">O LVDS LCD</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">100 Ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_0-</td><td>S112</td></tr><tr><td>LVDS1_1+</td><td>S114</td></tr><tr><td>LVDS1_1 -</td><td>S115</td></tr><tr><td>LVDS1_2+</td><td>S117</td></tr><tr><td>LVDS1_2-</td><td>S118</td></tr><tr><td>LVDS1_3+</td><td>S120</td></tr><tr><td>LVDS1_3-</td><td>S121</td></tr><tr><td>LVDS1_CK+</td><td>S108</td><td rowspan="2">Secondary LVDS channel differential pair clock lines.</td><td rowspan="2">O LVDS LCD</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">100 Ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_CK-</td><td>S109</td></tr><tr><td>LCD1_VDD_EN</td><td>S116</td><td>Secondary panel power enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD1_BKLT_EN</td><td>S107</td><td>Secondary panel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Only in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td>LCD1_BKLT_PWM</td><td>S122</td><td>Secondary panel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr></table>

<table><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if 2 panels are used</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if 2 panels are used</td></tr></table>

4.3.1.2 DSI0 Mode (Muxed on LVDS0)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>DSI0_D0+</td><td>S125</td><td rowspan="8">Primary DSI panel differential pair data lines</td><td rowspan="8">O D-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">No blocking capacitors or termination required. Layout for 90 Ohms differential impedance.</td></tr><tr><td>DSI0_D0-</td><td>S126</td></tr><tr><td>DSI0_D1+</td><td>S128</td></tr><tr><td>DSI0_D1-</td><td>S129</td></tr><tr><td>DSI0_D2+</td><td>S131</td></tr><tr><td>DSI0_D2-</td><td>S132</td></tr><tr><td>DSI0_D3+</td><td>S137</td></tr><tr><td>DSI0_D3-</td><td>S138</td></tr><tr><td>DSI0_CLK+</td><td>S134</td><td rowspan="2">Primary DSI panel differential pair clock lines.</td><td rowspan="2">O D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>DSI0_CLK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary panel power enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary panel backlight enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary panel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td>DSI0_TE</td><td>S144</td><td>Primary DSI panel tearing effect signal</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>1M PD</td><td></td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr></table>

# Second Display Interface

# HDMI Mode (HDMI Option Disables DSI0)

HDMI displays use 5V I²C signaling. The module's HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK signals need to be level-translated on the carrier from the module's 1.8V level. A similar consideration applies to the HDMI\_HPD signal.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>HDMI_D2+</td><td>P92</td><td rowspan="6">HDMI port, differential pair data lines</td><td rowspan="6">O TMDS HDMI</td><td rowspan="6"></td><td rowspan="6">Runtime</td><td rowspan="6"></td><td rowspan="6">AC coupled off module</td></tr><tr><td>HDMI_D2-</td><td>P93</td></tr><tr><td>HDMI_D1+</td><td>P95</td></tr><tr><td>HDMI_D1-</td><td>P96</td></tr><tr><td>HDMI_D0+</td><td>P98</td></tr><tr><td>HDMI_D0-</td><td>P99</td></tr><tr><td>HDMI_CK+</td><td>P101</td><td rowspan="2">HDMI port, differential pair clock lines</td><td rowspan="2">O TMDS HDMI</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>HDMI_CK-</td><td>P102</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>A level shifter FET and a 5V PU resistor shall be placed between the module and the HDMI connector.A stronger pull-up is demanded on the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete carrier pull-ups are used, the value depends on the individual carrier board implementation.</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>I/O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>A level shifter FET and a 5V PU resistor shall be placed between the module and the HDMI connector.A stronger pull-up is demanded on the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete carrier pull-ups are used, the value depends on the individual carrier Board implementation.</td></tr><tr><td>HDMI_HPD</td><td>P104</td><td>HDMI Hot plug active high detection signal serves as an interrupt request</td><td>I CMOS</td><td>1.8V</td><td>runtime</td><td>PD 1M</td><td>Important: A module must tolerate high voltage levels while in stand-by mode</td></tr></table>

# MIPI Camera Support

4.3.3.1 MIPI CSI0 (2 Lanes), BOM Option, Pin-Shared with DSI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>CSI0_RX0+</td><td>S11</td><td rowspan="4">CSI0 differential input (point to point)</td><td rowspan="4">I D-PHY / I M-PHY</td><td rowspan="4"></td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4"></td></tr><tr><td>CSI0_RX0-</td><td>S12</td></tr><tr><td>CSI0_RX1+</td><td>S14</td></tr><tr><td>CSI0_RX1-</td><td>S15</td></tr><tr><td>CSI0_CK+</td><td>S8</td><td rowspan="2">CSI0 differential clock input (point to point)</td><td rowspan="2">I D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI0_CK-</td><td>S9</td></tr><tr><td>I2C_CAM0_DAT /CSI0_TX-</td><td>S7</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM0_CK / CSI0_TX+</td><td>S5</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM0_PWR# / GPIO0</td><td>P108</td><td>Camera 0 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO0</td></tr><tr><td>CAM0_RST# / GPIO2</td><td>P110</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO2</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

4.3.3.2 CSI1 (4 Lanes)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI1_RX0+</td><td>P7</td><td rowspan="8">CSI1 differential input</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>CSI1_RX0-</td><td>P8</td></tr><tr><td>CSI1_RX1+</td><td>P10</td><td rowspan="6">/ I LVDS M-PHY</td></tr><tr><td>CSI1_RX1-</td><td>P11</td></tr><tr><td>CSI1_RX2+</td><td>P13</td></tr><tr><td>CSI1_RX2-</td><td>P14</td></tr><tr><td>CSI1_RX3+</td><td>P16</td></tr><tr><td>CSI1_RX3-</td><td>P17</td></tr><tr><td>CSI1_CK+</td><td>P3</td><td rowspan="2">CSI1 differential clock input (point to point)</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI1_CK-</td><td>P4</td></tr><tr><td>I2C_CAM1_DAT / CSI1_TX-</td><td>S2</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM1_CK / CSI1_TX+</td><td>S1</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM1_PWR# / GPIO1</td><td>P109</td><td>Camera 1 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO1</td></tr><tr><td>CAM1_RST# / GPIO3</td><td>P111</td><td>Camera 1 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with GPIO 3</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

# Audio Interfaces

I2S0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>I2S0_LRCK</td><td>S39</td><td>I2S0 Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td>I2S0_SDOUT</td><td>S40</td><td>I2S0 Digital audio Output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_SDIN</td><td>S41</td><td>I2S0 Digital audio Input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_CK</td><td>S42</td><td>I2S0 Digital audio clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td colspan="8"></td></tr><tr><td>AUDIO_MCK</td><td>S38</td><td>Master clock output to I2S codec(s)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with I2S2</td></tr></table>

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Note: The support for I2S1 signalling pins has been removed after the SMARC 2.0 specification update.

# USB Ports

The i.MX95 SoC provides a single USB 3.2 Gen 1 port and a single USB 2.0 port. All ports routed to the carrier are derived via an on-module USB hub. USB0 is used as the serial download port.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB0+USB0-</td><td>P60P61</td><td>USB differential data pairs for port 0</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From HUB</td></tr><tr><td>USB0_EN_OC#</td><td>P62</td><td>USB over-current sense for port 0</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB0_VBUS_DET</td><td>P63</td><td>USB port 0 host power detection, when this port is used as a device.</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td>When this Port is used as a device it can be connected to a USB client port VBUS pin</td></tr><tr><td>USB0_OTG_ID</td><td>P64</td><td>Input pin to announce OTG device insertion on USB 2.0 port</td><td></td><td></td><td>Standby</td><td></td><td>Resistor value to ground according to USB specification</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB1+USB1-</td><td>P65P66</td><td>USB differential data pairs for port 1</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From HUB</td></tr><tr><td>USB1_EN_OC#</td><td>P67</td><td>USB over-current sense for port 1</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB1 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB2+USB2-</td><td>P69P70</td><td>USB differential data pairs for port 2</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From SOC</td></tr><tr><td>USB2_SSRX+USB2_SSRX-</td><td>S74S75</td><td>Receive signal differential pairs for SuperSpeed on port 2</td><td>I USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB2_SSTX+USB2_SSTX-</td><td>S71S72</td><td>Transmit signal differential pairs for SuperSpeed on port 2</td><td>O USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB2_EN_OC#</td><td>P71</td><td>USB over-current sense for port 2</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB2 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB3+USB3-</td><td>S68S69</td><td>USB differential data pairs for port 3</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_SSRX+USB3_SSRX-</td><td>S65S66</td><td>Receive signal differential pairs for SuperSpeed on port 3</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB3_SSTX+USB3_SSTX-</td><td>S62S63</td><td>Transmit signal differential pairs for SuperSpeed on port 3</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB3_EN_OC#</td><td>P74</td><td>USB over-current sense for port 3</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB3 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB3_VBUS_DET</td><td>S37</td><td>USB port 3 host power detection, when this port is used as a device.</td><td>↓USB VBUS 5V</td><td>USB VBUS5V</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>USB3_OTG_ID</td><td>S104</td><td>Input pin to announce OTG device insertion on USB 3.0 port</td><td>↓CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB4+USB4-</td><td>S35S36</td><td>USB differential data pairs for port 4</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td>From HUB</td></tr><tr><td>USB4_EN_OC#</td><td>P76</td><td>USB over-current sense for port 4</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB4 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB5+USB5-</td><td>S59S60</td><td>USB differential data pairs for port 5</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB5_EN_OC#</td><td>S55</td><td>USB over-current sense for port 5</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB5 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr></table>

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Note: 3.3V or switched 3.3V: If a USB channel is not used, the USB[0:5]\_EN\_OC# pull-up rails may be held at GND to prevent leakage currents.

![The image shows a red outline icon of a document or page. It is rectangular with a folded corner at the bottom right. Inside the shape, there are two horizontal lines centered vertically.](.lec-imx95-user-manual-50m-72520-1020-12/fe5a2034438c696e70f5a752aa71fac1295b4bf59b29d35b997042961ce43fb2.jpg)

Note: USB downstream ports are derived from a USB 3.1 Gen 2 hub.

# PCIe and SerDes

PCIe Port D is used to bring out the 10GbE signal over SerDes.

# PCIe Ports

The i.MX95 supports two single-lane PCIe Gen 3.0 interfaces.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIE_A_TX+PCIE_A_TX-</td><td>P89P90</td><td>Differential PCIe link A transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_A_RX+PCIE_A_RX-</td><td>P86P87</td><td>Differential PCIe link A receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_A_REFCK+PCIE_A_REFCK-</td><td>P83P84</td><td>Differential PCIe Link A reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_RST#</td><td>P75</td><td>PCIe Port A reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_CKREQ#</td><td>P78</td><td>PCIe Port A clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on Module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_B_TX+PCIE_B_TX-</td><td>S90S91</td><td>Differential PCIe link B transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_B_RX+PCIE_B_RX-</td><td>S87S88</td><td>Differential PCIe link B receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_B_REFCK+PCIE_B_REFCK-</td><td>S84S85</td><td>Differential PCIe Link B reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_RST#</td><td>S76</td><td>PCIe Port B reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_CKREQ#</td><td>P77</td><td>PCIe Port B clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on the module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

# Dual LAN Ports

GBE0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GBE0_MDI0+</td><td>P30</td><td>Differential Pair Signals for External Transformer</td><td>I/IO GBE</td><td></td><td>Standby</td><td></td><td rowspan="8">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10_</td></tr><tr><td>GBE0_MDI0-</td><td>P29</td><td rowspan="2">Carrier Series Termination: Magnetics Module appropriate for 10/100/1000 GBE transceivers</td><td rowspan="2">MDI</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>GBE0_MDI1+</td><td>P27</td></tr><tr><td>GBE0_MDI1-</td><td>P26</td><td>Carrier Parallel Termination:</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE0_MDI2+</td><td>P24</td><td>Secondary side center tap terminations</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE0_MDI2-</td><td>P23</td><td>appropriate for Gigabit Ethernet</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE0_MDI3+</td><td>P20</td><td rowspan="2">implementations</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>GBE0_MDI3-</td><td>P19</td></tr><tr><td>GBE0_LINK100#</td><td>P21</td><td>Link Speed Indication LED for GBE 0 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more of carrier LED current</td></tr><tr><td>GBE0_LINK1000#</td><td>P22</td><td>Link Speed Indication LED for GBE 0 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more of carrier LED current</td></tr><tr><td>GBE0_LINK_ACT#</td><td>P25</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more of carrier LED current</td></tr><tr><td>GBE0_CTREF</td><td>P28</td><td>Center Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>GBE0_SDP</td><td>P6</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr></table>

4.3.7.2 GBE1

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GBE1_MDI0+</td><td>S17</td><td>Differential Pair Signals for External Transformer</td><td rowspan="8">I/IO GBE</td><td rowspan="8"></td><td rowspan="8">Standby</td><td rowspan="8"></td><td rowspan="8">Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE1_MDI0-</td><td>S18</td><td>Carrier Series Termination:</td></tr><tr><td>GBE1_MDI1+</td><td>S20</td><td>Magnetics Module appropriate for 10/100/1000</td></tr><tr><td>GBE1_MDI1-</td><td>S21</td><td>GBE transceivers</td></tr><tr><td>GBE1_MDI2+</td><td>S23</td><td>Carrier Parallel Termination:</td></tr><tr><td>GBE1_MDI2-</td><td>S24</td><td>Secondary side center tap terminations</td></tr><tr><td>GBE1_MDI3+</td><td>S26</td><td>appropriate for Gigabit Ethernet</td></tr><tr><td>GBE1_MDI3-</td><td>S27</td><td>implementations</td></tr><tr><td>GBE1_LINK100#</td><td>S19</td><td>Link Speed Indication LED for GBE 1 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK1000#</td><td>S22</td><td>Link Speed Indication LED for GBE 1 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK_ACT#</td><td>S31</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24 mA or more Carrier LED current</td></tr><tr><td>GBE1_CTREF</td><td>S28</td><td>Center Tap reference voltage for Carrier board Ethernet magnetic(if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>GBE1_SDP</td><td>P5</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr></table>

# SDIO Card (4-Bit)

The carrier SDIO card may be selected as the boot device.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SDIO_D0</td><td>P39</td><td rowspan="4">SDIO Data lines. These signals operate in push-pull mode.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V or 3.3V</td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4">SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_D1</td><td>P40</td></tr><tr><td>SDIO_D2</td><td>P41</td></tr><tr><td>SDIO_D3</td><td>P42</td></tr><tr><td>SDIO_WP</td><td>P33</td><td>SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CMD</td><td>P34</td><td>SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td>SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_CD#</td><td>P35</td><td>SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CK</td><td>P36</td><td>SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SDIO_PWR_EN</td><td>P37</td><td>SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>should be driven low in STB Mode by the module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

# SPI Interfaces

# SPI0

A carrier SPI device may be selected as the boot device.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI0_CS0#</td><td>P43</td><td>SPI0 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>This signal can be used to select carrier SPI as boot device</td></tr><tr><td>SPI0_CS1#</td><td>P31</td><td>SPI0 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CK</td><td>P44</td><td>SPI0 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_DIN</td><td>P45</td><td>SPI0 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MISO</td></tr><tr><td>SPI0_DO</td><td>P46</td><td>SPI0 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MOSI</td></tr></table>

# SPI or ESPI

ESPI Mode (eCSPI on ARM)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ESPI_CS0#</td><td>P54</td><td>ESPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CS1#</td><td>P55</td><td>ESPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CK</td><td>P56</td><td>ESPI Master Clock Output</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Pin provides reference timing for all serial input / output operations.</td></tr><tr><td>ESPI_RESET#</td><td>S58</td><td>ESPI Reset</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves</td></tr><tr><td>ESPI_ALERT0#ESPI_ALERT1#</td><td>S43S44</td><td>ESPI ALERT</td><td>I ODCMOS</td><td>1.8V</td><td>Standby</td><td>4.7k PU</td><td>This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave. This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.</td></tr><tr><td>ESPI_IO_0</td><td>P58</td><td rowspan="2">ESPI Master Data Input / Output</td><td>I/O</td><td rowspan="2">1.8V</td><td rowspan="2">Standby</td><td rowspan="2"></td><td rowspan="2">In Single I/O mode, ESPI_IO_0 is eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is SPI master input / eSPI slave output (MISO).</td></tr><tr><td>ESPI_IO_1</td><td>P57</td><td>CMOS</td></tr><tr><td rowspan="2">ESPI_IO_1 / SPI1_DIN</td><td rowspan="2">S56</td><td rowspan="2">In</td><td>I/O</td><td rowspan="2">1.8V</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CMOS</td></tr><tr><td rowspan="2">ESPI_IO_0 / SPI1_DO</td><td rowspan="2">S57</td><td rowspan="2">Out</td><td>I/O</td><td rowspan="2">1.8V</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CMOS</td></tr></table>

GPIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>GPIO0 / CAM0_PWR#</td><td>P108</td><td>General purpose I/O pin 0.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternate use is Camera 0 Power Enable, active low output</td></tr><tr><td>GPIO1 / CAM1_PWR#</td><td>P109</td><td>General purpose I/O pin 1.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternate use is Camera 1 Power Enable, active low output</td></tr><tr><td>GPIO2 / CAM0_RST#</td><td>P110</td><td>General purpose I/O pin 2.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternate use is Camera 0 Reset, active low output</td></tr><tr><td>GPIO3 / CAM1_RST#</td><td>P111</td><td>General purpose I/O pin 3.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternate use is Camera 1 Reset, active low output</td></tr><tr><td>GPIO4 / HDA_RST#</td><td>P112</td><td>General purpose I/O pin 4.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternative use is HD Audio Reset, active low output</td></tr><tr><td>GPIO5 / PWM_OUT</td><td>P113</td><td>General purpose I/O pin 5.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>alternate use is PWM output</td></tr><tr><td>GPIO6 / TACHIN</td><td>P114</td><td>General purpose I/O pin 6.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>FAN Tachometer input (used with GPIO5 PWM_OUT)</td></tr><tr><td>GPIO7</td><td>P115</td><td>General purpose I/O pin 7.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr><tr><td>GPIO8</td><td>P116</td><td>General purpose I/O pin 8.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr><tr><td>GPIO9</td><td>P117</td><td>General purpose I/O pin 9.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr><tr><td>GPIO10</td><td>P118</td><td>General purpose I/O pin 10.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr><tr><td>GPIO11</td><td>P119</td><td>General purpose I/O pin 11.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr><tr><td>GPIO12</td><td>S142</td><td>General purpose I/O pin 12</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td>advised as INT signal to any expander on carrier.</td></tr><tr><td>GPIO13</td><td>S123</td><td>General purpose I/O pin 13</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K $^{1}$ </td><td></td></tr></table>

![The image displays a red outline icon of a document or note with a folded bottom-right corner. Inside the white area, there are two horizontal red lines centered within the shape.](.lec-imx95-user-manual-50m-72520-1020-12/96ae7345e56d4e8fc34668a51722af56358dcd8f824464fba1e8e09afcc49dcc.jpg)

Note1 : also allows for SoC-integrated pull-ups.

These can be ≤ 10kΩ. A maximum 2.2kΩ pull-down should be implemented on the carrier if a low level needs to be ensured.

# CAN Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CAN0_TX</td><td>P143</td><td>CAN port 0 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAN0_RX</td><td>P144</td><td>CAN port 0 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

<table><tr><td>CAN1_TX</td><td>P145</td><td>CAN port 1 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAN1_RX</td><td>P146</td><td>CAN port1 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>TEST#</td><td>S157</td><td>Held Low by Carrier to Invoke Module Vendor Specific Test Functions</td><td>I ODCMOS</td><td>1.8 to 5 V</td><td>Runtime</td><td>PU</td><td>Module must implement PU but actual value is depended on particular Module design. Carrier Board should leave this pin floating for normal operation. Driven by OD on Carrier</td></tr><tr><td>WDT_TIME_OUT#</td><td>S145</td><td>Watch-Dog-Timer Output, low active.</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PWM_OUT / GPIO5</td><td>P113</td><td>Pulse Width Modulation (PWM) output</td><td>I/OCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K</td><td>GPIO5 is the default pin configuration</td></tr></table>

Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>BATLOW#</td><td>S156</td><td>Battery low indication to Module. Carrier to float the line in inactive state.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CARRIER_PWR_ON</td><td>S154</td><td>Carrier Board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td>On x86 designs this pin should utilize a standby related power signal i.e. RSM_RST# or SLP_A# signal.</td></tr><tr><td>CARRIER_STBY#</td><td>S153</td><td>The Module shall drive this signal low when the system is in a standby power state.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td>On x86 designs this pin should utilize the SUS_S3# signal.</td></tr><tr><td>CHARGER_PRSNT#</td><td>S152</td><td>Held low by Carrier if DC input for battery charger is present.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CHARGING#</td><td>S151</td><td>Held low by Carrier during battery charging. Carrier to float the line when charge is complete.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>VIN_PWR_BAD#</td><td>S150</td><td>Power bad indication from Carrier Board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.</td><td>IOD CMOS</td><td>VDD_IN</td><td></td><td>PU 10K</td><td>Driven by OD on Carrier Module must implement PU but actual value is depended on particular module design.</td></tr><tr><td>SLEEP#</td><td>S149</td><td>Sleep indicator from Carrier Board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Activelow, level sensitive.Shouldbe de-bounced on the Module.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>LID#</td><td>S148</td><td>Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive.Shouldbe de-bounced on the Module.</td><td>IODCMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10K</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive.Shouldbe debounced on the Module.</td><td>IODCMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10K</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>RESET_OUT#</td><td>P126</td><td>General purpose reset output to Carrier board.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>RESET_IN#</td><td>P127</td><td>Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise.This signalShallbe level triggered during bootup to allow to stop booting of the module.After bootup itMayact as an edge triggered signal.</td><td>IODCMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10K</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA</td><td>I/O ODCMOS</td><td>1.8V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>On x86 systems these serve as SMB DATA.Pulled up on module.</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK</td><td>ODCMOS</td><td>1.8V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>On x86 systems these serve as SMB CLK.Pulled up on module.</td></tr><tr><td>SMB_ALERT_1V8#</td><td>P1</td><td>SMBus Alert# (interrupt) signal</td><td>LODMOS</td><td>1.8V to 5V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>only used on x86 design</td></tr></table>

Boot Select

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>BOOT_SEL0#</td><td>P123</td><td rowspan="3">Input straps determine the module boot</td><td rowspan="3">I OD CMOS</td><td rowspan="3">1.8V</td><td rowspan="3">Standby</td><td rowspan="3">PU 10K</td><td rowspan="3">Driven by OD on the carrier.Pulled up on the module.Booting from eMMC and SD card is supported.</td></tr><tr><td>BOOT_SEL1#</td><td>P124</td></tr><tr><td>BOOT_SEL2#</td><td>P125</td></tr><tr><td>FORCE_RECOV#</td><td>S155</td><td></td><td>I OD CMOS</td><td>1.8V</td><td>Standby</td><td>PU 10K</td><td>Driven by OD on the carrier.Pulled up on the module.Low on this pin allows non-protected segments of the module boot device to be rewritten/restored from an external USB host on Module USB0. The Module USB0 operates in client mode when the Force Recovery function is invoked. Pulled high on the module.For SoCs that do not implement a USB-based Force Recovery function, a low on the Module FORCE_RECOV# pin may invoke the SoC&#x27;s native Force Recovery mode – such as over a serial port.For x86 systems, this signal may be used to load BIOS defaults.Pulled up on the module. Driven by OD part on carrier.</td></tr></table>

Power

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>Power Rail / Tolerance</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VDD_IN</td><td>P147, P148, P149, P150, P151, P152, P153, P154, P155, P156</td><td>Module power input voltage 4.75 min to 5.25V max</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>4.75V to 5.25V / 5V</td><td></td><td></td></tr><tr><td>GND</td><td>P2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158</td><td>Module signal and power return, and GND reference</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>Ground</td><td></td><td></td></tr><tr><td>VDD_RTC</td><td>S147</td><td>Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>[2 to 3.25] / 3.25V</td><td></td><td></td></tr></table>

Pin to Controller Mapping Table

<table><tr><td>Pin</td><td>SMARC Signal Name</td><td>Module Direction</td><td>Module Termination</td><td>Type/Tolerance</td><td>Controller</td><td>Controller Pin Name</td><td>I/O Mux default</td></tr><tr><td>P1</td><td>SMB_ALERT_1V8#</td><td>In</td><td>PU-2.2K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO18</td><td>Alt0</td></tr><tr><td>P2</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P3</td><td>CSI1_CK+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_CLK_P</td><td>-</td></tr><tr><td>P4</td><td>CSI1_CK-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_CLK_N</td><td>-</td></tr><tr><td>P5</td><td>GBE1_SDP</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td></tr><tr><td>P6</td><td>GBE0_SDP</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P7</td><td>CSI1_RX0+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D0_P</td><td>-</td></tr><tr><td>P8</td><td>CSI1_RX0-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D0_N</td><td>-</td></tr><tr><td>P9</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P10</td><td>CSI1_RX1+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D1_P</td><td>-</td></tr><tr><td>P11</td><td>CSI1_RX1-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D1_N</td><td>-</td></tr><tr><td>P12</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P13</td><td>CSI1_RX2+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D2_P</td><td>-</td></tr><tr><td>P14</td><td>CSI1_RX2-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D2_N</td><td>-</td></tr><tr><td>P15</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P16</td><td>CSI1_RX3+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D3_P</td><td>-</td></tr><tr><td>P17</td><td>CSI1_RX3-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_CSI1_D3_N</td><td>-</td></tr><tr><td>P18</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P19</td><td>GBE0_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN3</td><td>-</td></tr><tr><td>P20</td><td>GBE0_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP3</td><td>-</td></tr><tr><td>P21</td><td>ENET1_LINK100#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED1/CFG_LDO0</td><td>-</td></tr><tr><td>P22</td><td>GBE0_LINK1000#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED2/CFG_LDO1</td><td>-</td></tr><tr><td>P23</td><td>GBE0_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN2</td><td>-</td></tr><tr><td>P24</td><td>GBE0_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP2</td><td>-</td></tr><tr><td>P25</td><td>GBE0_LINK_ACT#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED0/CFG_EXT</td><td>-</td></tr><tr><td>P26</td><td>GBE0_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN1</td><td>-</td></tr><tr><td>P27</td><td>GBE0_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP1</td><td>-</td></tr><tr><td>P28</td><td>GBE0_CTREF</td><td>PWR</td><td>-</td><td>Analog / 3.3V</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P29</td><td>GBE0_MDIO-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN0</td><td>-</td></tr><tr><td>P30</td><td>GBE0_MDIO+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP0</td><td>-</td></tr><tr><td>P31</td><td>SPI0_CS1#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO24</td><td>Alt6</td></tr><tr><td>P32</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P33</td><td>SDIO_WP</td><td>In</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>XSPI1_DQS</td><td>Alt0</td></tr><tr><td>P34</td><td>SDIO_CMD</td><td>Bi-Dir</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_CMD</td><td>Alt0</td></tr><tr><td>P35</td><td>SDIO_CD#</td><td>In</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_CD_B</td><td>Alt0</td></tr><tr><td>P36</td><td>SDIO_CK</td><td>Out</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_CLK</td><td>Alt0</td></tr><tr><td>P37</td><td>SDIO_PWR_EN</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>i.MX95</td><td>SD2_RESET_B</td><td>Alt0</td></tr><tr><td>P38</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P39</td><td>SDIO_D0</td><td>Bi-Dir</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_DATA0</td><td>Alt0</td></tr><tr><td>P40</td><td>SDIO_D1</td><td>Bi-Dir</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_DATA1</td><td>Alt0</td></tr><tr><td>P41</td><td>SDIO_D2</td><td>Bi-Dir</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_DATA2</td><td>Alt0</td></tr><tr><td>P42</td><td>SDIO_D3</td><td>Bi-Dir</td><td>-</td><td>SD / 1.8/3.3V</td><td>i.MX95</td><td>SD2_DATA3</td><td>Alt0</td></tr><tr><td>P43</td><td>SPI0_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO00</td><td>Alt4</td></tr><tr><td>P44</td><td>SPI0_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO03</td><td>Alt4</td></tr><tr><td>P45</td><td>SPI0_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO01</td><td>Alt4</td></tr><tr><td>P46</td><td>SPI0_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO02</td><td>Alt4</td></tr><tr><td>P47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P48</td><td>SATA_TX+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P49</td><td>SATA_TX-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P50</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P51</td><td>SATA_RX+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P52</td><td>SATA_RX-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P53</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P54</td><td>ESPI_CS0# / SPI1_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO04</td><td>Alt4</td></tr><tr><td>P55</td><td>ESPI_CS1# / SPI1_CS1#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO25</td><td>Alt6</td></tr><tr><td>P56</td><td>ESPI_CK / SPI1_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO07</td><td>Alt4</td></tr><tr><td>P57</td><td>ESPI_IO_1 / SPI1_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO05</td><td>Alt4</td></tr><tr><td>P58</td><td>ESPI_IO_0 / SPI1_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>i.MX95</td><td>GPIO_IO06</td><td>Alt4</td></tr><tr><td>P59</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P60</td><td>USB0+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>i.MX95</td><td>USB1_D_P</td><td>-</td></tr><tr><td>P61</td><td>USB0-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>i.MX95</td><td>USB1_D_N</td><td>-</td></tr><tr><td>P62</td><td>USB0_EN_OC#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P63</td><td>USB0_VBUS_DET</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P64</td><td>USB0_OTG_ID</td><td>In</td><td>-</td><td>USB / 3.3V</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P65</td><td>USB1+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DP_W</td><td>-</td></tr><tr><td>P66</td><td>USB1-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DM_W</td><td>-</td></tr><tr><td>P67</td><td>USB1_EN_OC#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>USB Hub (GL3590)</td><td>OVCUR_W</td><td>-</td></tr><tr><td>P68</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P69</td><td>USB2+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>TXP1_X</td><td>-</td></tr><tr><td>P70</td><td>USB2-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>TXN1_X</td><td>-</td></tr><tr><td>P71</td><td>USB2_EN_OC#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>USB Hub (GL3590)</td><td>OVCUR_X</td><td>-</td></tr><tr><td>P72</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P73</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P74</td><td>USB3_EN_OC#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>USB Hub (GL3590)</td><td>OVCUR_Y</td><td>-</td></tr><tr><td>P75</td><td>PCIE_A_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPIO expander(SX1509)</td><td>I/O6</td><td>-</td></tr><tr><td>P76</td><td>USB4_EN_OC#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>USB Hub (GL3590)</td><td>OVCUR_A</td><td>-</td></tr><tr><td>P77</td><td>PCIE_B_CREQ#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>Clock Generator(RC21008)</td><td>CLKIN1_GPI3</td><td>-</td></tr><tr><td>P78</td><td>PCIE_A_CREQ#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>9FGV0241AKILF</td><td>CKPWRGD_PD</td><td>-</td></tr><tr><td>P79</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+</td><td>Out</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P81</td><td>PCIE_C_REFCK-</td><td>Out</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P82</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+</td><td>Out</td><td>-</td><td>PCIe</td><td>Clock Generator(RC21008)</td><td>OUT3</td><td>-</td></tr><tr><td>P84</td><td>PCIE_A_REFCK-</td><td>Out</td><td>-</td><td>PCIe</td><td>Clock Generator(RC21008)</td><td>OUT3_B</td><td>-</td></tr><tr><td>P85</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P86</td><td>PCIE_A_RX+</td><td>In</td><td>-</td><td>PCIe</td><td>i.MX95</td><td>PCIE1_RX0_P</td><td>-</td></tr><tr><td>P87</td><td>PCIE_A_RX-</td><td>In</td><td>-</td><td>PCIe</td><td>i.MX95</td><td>PCIE1_RX0_N</td><td>-</td></tr><tr><td>P88</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P89</td><td>PCIE_A_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>i.MX95</td><td>PCIE1_TX0_P</td><td>-</td></tr><tr><td>P90</td><td>PCIE_A_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>i.MX95</td><td>PCIE1_TX0_N</td><td>-</td></tr><tr><td>P91</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P92</td><td>HDMI_D2+ / DP1_LANE0+</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D0+</td><td>-</td></tr><tr><td>P93</td><td>HDMI_D2- / DP1_LANE0-</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D0-</td><td>-</td></tr><tr><td>P94</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P95</td><td>HDMI_D1+ / DP1_LANE1+</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D1+</td><td>-</td></tr><tr><td>P96</td><td>HDMI_D1- / DP1_LANE1-</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D1-</td><td>-</td></tr><tr><td>P97</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P98</td><td>HDMI_D0+ / DP1_LANE2+</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D2+</td><td>-</td></tr><tr><td>P99</td><td>HDMI_D0- / DP1_LANE2-</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_D2-</td><td>-</td></tr><tr><td>P100</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P101</td><td>HDMI_CK+ / DP1_LANE3+</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_C+</td><td>-</td></tr><tr><td>P102</td><td>HDMI_CK- / DP1_LANE3-</td><td>Out</td><td>-</td><td>HDMI</td><td>LT9611</td><td>TX_C-</td><td>-</td></tr><tr><td>P103</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P104</td><td>HDMI_HPD / DP1_HPD</td><td>In</td><td>PD-1M</td><td>HDMI</td><td>LT9611</td><td>HPD_GPIO2</td><td>-</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK / DP1_AUX+</td><td>Out</td><td>PU-100K</td><td>HDMI</td><td>LT9611</td><td>DSCL</td><td>-</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT / DP1_AUX-</td><td>Bi-Dir</td><td>PU-100K</td><td>HDMI</td><td>LT9611</td><td>DSDA</td><td>-</td></tr><tr><td>P107</td><td>DP1_AUX_SEL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR#</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PB0</td><td>-</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR#</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PB1</td><td>-</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST#</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PB2</td><td>-</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST#</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PB5</td><td>-</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST#</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO34</td><td>Alt0</td></tr><tr><td>P113</td><td>GPIO5 / PWM_OUT</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO22</td><td>Alt4</td></tr><tr><td>P114</td><td>GPIO6 / TACHIN</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>XSPI1_DATA7</td><td>Alt5</td></tr><tr><td>P115</td><td>GPIO7</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO14</td><td>Alt0</td></tr><tr><td>P116</td><td>GPIO8</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO15</td><td>Alt0</td></tr><tr><td>P117</td><td>GPIO9</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>CCM_CLKO2</td><td>Alt5</td></tr><tr><td>P118</td><td>GPIO10</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>CCM_CLKO4</td><td>Alt5</td></tr><tr><td>P119</td><td>GPIO11</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PB10</td><td>-</td></tr><tr><td>P120</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P121</td><td>I2C_PM_CK</td><td>Out</td><td>PU-2k2</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO29</td><td>Alt1</td></tr><tr><td>P122</td><td>I2C_PM_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO28</td><td>Alt1</td></tr><tr><td>P123</td><td>BOOT_SEL0#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PC6</td><td>-</td></tr><tr><td>P124</td><td>BOOT_SEL1#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PC7</td><td>-</td></tr><tr><td>P125</td><td>BOOT_SEL2#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PC8</td><td>-</td></tr><tr><td>P126</td><td>RESET_OUT#</td><td>Out</td><td>PU-100K</td><td>GPIO / 1.8V</td><td>Logic IC</td><td>Logic IC</td><td>-</td></tr><tr><td>P127</td><td>RESET_IN#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>Logic IC</td><td>Logic IC</td><td>-</td></tr><tr><td>P128</td><td>POWER_BTN#</td><td>In</td><td>PU-100K</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>ONOFF</td><td>-</td></tr><tr><td>P129</td><td>SER0_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO08</td><td>Alt5</td></tr><tr><td>P130</td><td>SER0_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO09</td><td>Alt5</td></tr><tr><td>P131</td><td>SER0_RTS#</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO11</td><td>Alt5</td></tr><tr><td>P132</td><td>SER0_CTS#</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO10</td><td>Alt5</td></tr><tr><td>P133</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P134</td><td>SER1_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>UART1_TXD</td><td>Alt0</td></tr><tr><td>P135</td><td>SER1_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>UART1_RXD</td><td>Alt0</td></tr><tr><td>P136</td><td>SER2_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO04</td><td>Alt5</td></tr><tr><td>P137</td><td>SER2_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO05</td><td>Alt5</td></tr><tr><td>P138</td><td>SER2_RTS#</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO07</td><td>Alt5</td></tr><tr><td>P139</td><td>SER2_CTS#</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>GPIO_IO06</td><td>Alt5</td></tr><tr><td>P140</td><td>SER3_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>UART2_TXD</td><td>Alt0</td></tr><tr><td>P141</td><td>SER3_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>i.MX95</td><td>UART2_RXD</td><td>Alt0</td></tr><tr><td>P142</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P143</td><td>CAN0_TX</td><td>Out</td><td>-</td><td>CAN / 1.8V</td><td>i.MX95</td><td>PDM_CLK</td><td>Alt6</td></tr><tr><td>P144</td><td>CAN0_RX</td><td>In</td><td>-</td><td>CAN / 1.8V</td><td>i.MX95</td><td>PDM_BIT_STREAM0</td><td>Alt6</td></tr><tr><td>P145</td><td>CAN1_TX</td><td>Out</td><td>-</td><td>CAN / 1.8V</td><td>i.MX95</td><td>GPIO_IO30</td><td>Alt2</td></tr><tr><td>P146</td><td>CAN1_RX</td><td>In</td><td>-</td><td>CAN / 1.8V</td><td>i.MX95</td><td>GPIO_IO31</td><td>Alt2</td></tr><tr><td>P147</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P148</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P149</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P150</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P151</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P152</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P153</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P154</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P155</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>P156</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td></tr><tr><td>S1</td><td>CSI1_TX+ / I2C_CAM1_CK</td><td>Out</td><td>PU-2k2</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO29</td><td>Alt1</td></tr><tr><td>S2</td><td>CSI1_TX- / I2C_CAM1_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO28</td><td>Alt1</td></tr><tr><td>S3</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S4</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S5</td><td>CSI0_TX- / I2C_CAM0_CK</td><td>Out</td><td>PU-2k2</td><td>-</td><td>i.MX95</td><td>I2C2_SCL</td><td>Alt0</td></tr><tr><td>S6</td><td>CAM_MCK</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>CCM_CLKO1</td><td>Alt0</td></tr><tr><td>S7</td><td>CSI0_TX+ / I2C_CAM0_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>-</td><td>i.MX95</td><td>I2C2_SDA</td><td>Alt0</td></tr><tr><td>S8</td><td>CSI0_CK+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_CLK_P</td><td>-</td></tr><tr><td>S9</td><td>CSI0_CK-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_CLK_N</td><td>-</td></tr><tr><td>S10</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S11</td><td>CSI0_RX0+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_D0_P</td><td>-</td></tr><tr><td>S12</td><td>CSI0_RX0-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_D0_N</td><td>-</td></tr><tr><td>S13</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S14</td><td>CSI0_RX1+</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_D1_P</td><td>-</td></tr><tr><td>S15</td><td>CSI0_RX1-</td><td>In</td><td>-</td><td>MIPI_CSI</td><td>i.MX95</td><td>MIPI_DSICSI1_D1_N</td><td>-</td></tr><tr><td>S16</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S17</td><td>GBE1_MDI0+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP0</td><td>-</td></tr><tr><td>S18</td><td>GBE1_MDI0-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN0</td><td>-</td></tr><tr><td>S19</td><td>GBE1_LINK100#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED0</td><td>-</td></tr><tr><td>S20</td><td>GBE1_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP1</td><td>-</td></tr><tr><td>S21</td><td>GBE1_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN1</td><td>-</td></tr><tr><td>S22</td><td>GBE1_LINK1000#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED1</td><td>-</td></tr><tr><td>S23</td><td>GBE1_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP2</td><td>-</td></tr><tr><td>S24</td><td>GBE1_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN2</td><td>-</td></tr><tr><td>S25</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S26</td><td>GBE1_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIP3</td><td>-</td></tr><tr><td>S27</td><td>GBE1_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>RTL8211</td><td>MDIN3</td><td>-</td></tr><tr><td>S28</td><td>GBE1_CTREF</td><td>PWR</td><td>-</td><td>Analog / 3.3V</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S29</td><td>PCIE_D_TX+/SERDES_1_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>SERDES</td><td>i.MX95</td><td>ETH_TX0_P</td><td>-</td></tr><tr><td>S30</td><td>PCIE_D_TX-/SERDES_1_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>SERDES</td><td>i.MX95</td><td>ETH_TX0_N</td><td>-</td></tr><tr><td>S31</td><td>GBE1_LINK_ACT#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>RTL8211</td><td>LED3</td><td>-</td></tr><tr><td>S32</td><td>PCIE_D_RX+ / SERDES_1_RX+</td><td>In</td><td>-</td><td>SERDES</td><td>i.MX95</td><td>ETH_RX0_P</td><td>-</td></tr><tr><td>S33</td><td>PCIE_D_RX- / SERDES_1_RX-</td><td>In</td><td>-</td><td>SERDES</td><td>i.MX95</td><td>ETH_RX0_N</td><td>-</td></tr><tr><td>S34</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S35</td><td>USB4+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DP_A</td><td>-</td></tr><tr><td>S36</td><td>USB4-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DM_A</td><td>-</td></tr><tr><td>S37</td><td>USB3_VBUS_DET</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S38</td><td>AUDIO_MCK</td><td>Out</td><td>-</td><td>SAI / 1.8V</td><td>i.MX95</td><td>GPIO_IO17</td><td>Alt1</td></tr><tr><td>S39</td><td>I2S0_LRCK</td><td>Bi-Dir</td><td>-</td><td>SAI / 1.8V</td><td>i.MX95</td><td>GPIO_IO26</td><td>Alt7</td></tr><tr><td>S40</td><td>I2S0_SDOUT</td><td>Out</td><td>-</td><td>SAI / 1.8V</td><td>i.MX95</td><td>GPIO_IO21</td><td>Alt1</td></tr><tr><td>S41</td><td>I2S0_SDIN</td><td>In</td><td>-</td><td>SAI / 1.8V</td><td>i.MX95</td><td>GPIO_IO20</td><td>Alt1</td></tr><tr><td>S42</td><td>I2S0_CK</td><td>Bi-Dir</td><td>-</td><td>SAI / 1.8V</td><td>i.MX95</td><td>GPIO_IO16</td><td>Alt1</td></tr><tr><td>S43</td><td>ESPI_ALERT0#</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S44</td><td>ESPI_ALERT1#</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S45</td><td>MDIO_CLK</td><td>Out</td><td>-</td><td>SERDES / 1.8V</td><td>i.MX95</td><td>ENET1_MDC</td><td>Alt0</td></tr><tr><td>S46</td><td>MDIO_DAT</td><td>Bi-Dir</td><td>PU-1.5K</td><td>SERDES / 1.8V</td><td>i.MX95</td><td>ENET1_MDIO</td><td>Alt0</td></tr><tr><td>S47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S48</td><td>I2C_GP_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO12</td><td>Alt6</td></tr><tr><td>S49</td><td>I2C_GP_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C / 1.8V</td><td>i.MX95</td><td>GPIO_IO13</td><td>Alt6</td></tr><tr><td>S50</td><td>HDA_SYNC / I2S2_LRCK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S51</td><td>HDA_SDO / I2S2_SDOUT</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S52</td><td>HDA_SDI / I2S2_SDIN</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S53</td><td>HDA_CK / I2S2_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S54</td><td>SATA_ACT#</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S55</td><td>USB5_EN_OC#</td><td>Bi-Dir</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>GPIO expander(SX1509)</td><td>OVCUR_B</td><td>-</td></tr><tr><td>S56</td><td>ESPI_IO_2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S57</td><td>ESPI_IO_3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S58</td><td>ESPI_RESET#</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S59</td><td>USB5+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DP_B</td><td>-</td></tr><tr><td>S60</td><td>USB5-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DM_B</td><td>-</td></tr><tr><td>S61</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S62</td><td>USB3_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB3</td><td>USB Hub (GL3590)</td><td>TXP1_Y</td><td>-</td></tr><tr><td>S63</td><td>USB3_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB3</td><td>USB Hub (GL3590)</td><td>TXN1_Y</td><td>-</td></tr><tr><td>S64</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S65</td><td>USB3_SSRX+</td><td>In</td><td>-</td><td>USB3</td><td>USB Hub (GL3590)</td><td>RXP1_Y</td><td>-</td></tr><tr><td>S66</td><td>USB3_SSRX-</td><td>In</td><td>-</td><td>USB3</td><td>USB Hub (GL3590)</td><td>RXN1_Y</td><td>-</td></tr><tr><td>S67</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S68</td><td>USB3+</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DP_Y</td><td>-</td></tr><tr><td>S69</td><td>USB3-</td><td>Bi-Dir</td><td>-</td><td>USB / 3.3V</td><td>USB Hub (GL3590)</td><td>DM_Y</td><td>-</td></tr><tr><td>S70</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S71</td><td>USB2_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB3</td><td>USB Hub (GL3590)</td><td>TXP1_X</td><td>-</td></tr><tr><td>S72</td><td>USB2_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB3</td><td>USB Hub (GL3590)</td><td>TXN1_X</td><td>-</td></tr><tr><td>S73</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S74</td><td>USB2_SSRX+</td><td>In</td><td>-</td><td>USB3</td><td>USB Hub (GL3590)</td><td>RXP1_X</td><td>-</td></tr><tr><td>S75</td><td>USB2_SSRX-</td><td>In</td><td>-</td><td>USB3</td><td>USB Hub (GL3590)</td><td>RXN1_X</td><td>-</td></tr><tr><td>S76</td><td>PCIE_B_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPIO expander(SX1509)</td><td>I/O7</td><td>-</td></tr><tr><td>S77</td><td>PCIE_C_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPIO expander(SX1509)</td><td>I/O2</td><td>-</td></tr><tr><td>S78</td><td>PCIE_C_RX+ / SERDES_2_RX+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S79</td><td>PCIE_C_RX- / SERDES_2_RX-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S80</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S81</td><td>PCIE_C_TX+ / SERDES_2_TX+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S82</td><td>PCIE_C_TX- / SERDES_2_TX-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S83</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S84</td><td>PCIE_B_REFCK+</td><td>Out</td><td>-</td><td>PCIe</td><td>Clock Generator(RC21008)</td><td>OUT6</td><td>-</td></tr><tr><td>S85</td><td>PCIE_B_REFCK-</td><td>Out</td><td>-</td><td>PCIe</td><td>Clock Generator(RC21008)</td><td>OUT6_B</td><td>-</td></tr><tr><td>S86</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S87</td><td>PCIE_B_RX+</td><td>In</td><td>-</td><td>PCIe</td><td>i.MX95</td><td>PCIE2_RX0_P</td><td>-</td></tr><tr><td>S88</td><td>PCIE_B_RX-</td><td>In</td><td>-</td><td>PCIe</td><td>i.MX95</td><td>PCIE2_RX0_N</td><td>-</td></tr><tr><td>S89</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S90</td><td>PCIE_B_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>i.MX95</td><td>PCIE2_TX0_P</td><td>-</td></tr><tr><td>S91</td><td>PCIE_B_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>i.MX95</td><td>PCIE2_TX0_N</td><td>-</td></tr><tr><td>S92</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S93</td><td>DP0_LANE0+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S94</td><td>DP0_LANE0-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S95</td><td>DP0_AUX_SEL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S96</td><td>DP0_LANE1+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S97</td><td>DP0_LANE1-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S98</td><td>DP0_HPD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S99</td><td>DP0_LANE2+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S100</td><td>DP0_LANE2-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S101</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S102</td><td>DP0_LANE3+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S103</td><td>DP0_LANE3-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S104</td><td>USB3_OTG_ID</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S105</td><td>DP0_AUX+</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S106</td><td>DP0_AUX-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>Out</td><td>PD-100K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PA1</td><td>-</td></tr><tr><td>S108</td><td>LVDS1_CK+/eDP1_AUX+/DSI1_CLK+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>LVDS1_CLK_P</td><td>-</td></tr><tr><td>S109</td><td>LVDS1_CK-/eDP1_AUX-/DSI1_CLK-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>LVDS1_CLK_N</td><td>-</td></tr><tr><td>S110</td><td>GND</td><td>-</td><td>-</td><td>-</td><td></td><td></td><td>-</td></tr><tr><td>S111</td><td>LVDS1_0+/eDP1_TX0+/DSI1_D0+</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D0_P</td><td>-</td></tr><tr><td>S112</td><td>LVDS1_0-/eDP1_TX0-/DSI1_D0-</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D0_N</td><td>-</td></tr><tr><td>S113</td><td>eDP1_HPD / DSI1_TE</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S114</td><td>LVDS1_1+/eDP1_TX1+/DSI1_D1+</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D1_P</td><td>-</td></tr><tr><td>S115</td><td>LVDS1_1-/eDP1_TX1-/DSI1_D1-</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D1_N</td><td>-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>Out</td><td>PD-100K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PA0</td><td>-</td></tr><tr><td>S117</td><td>LVDS1_2+ / eDP1_TX2+ / DSI1_D2+</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D2_P</td><td>-</td></tr><tr><td>S118</td><td>LVDS1_2- / eDP1_TX2- / DSI1_D2-</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D2_N</td><td>-</td></tr><tr><td>S119</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S120</td><td>LVDS1_3+ / eDP1_TX3+ / DSI1_D3+</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D3_P</td><td>-</td></tr><tr><td>S121</td><td>LVDS1_3- / eDP1_TX3- / DSI1_D3-</td><td>Out</td><td>-</td><td>LVDS</td><td>i.MX95</td><td>LVDS1_D3_N</td><td>-</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO23</td><td>Alt4</td></tr><tr><td>S123</td><td>GPIO13</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PA3</td><td>-</td></tr><tr><td>S124</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S125</td><td>LVDS0_0+ / eDP0_TX0+ / DSI0_D0+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_D0_P/LVDS0_D0_P</td><td>-</td></tr><tr><td>S126</td><td>LVDS0_0- / eDP0_TX0- / DSI0_D0-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_D0_N/LVDS0_D0_N</td><td>-</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>Out</td><td>PD-100K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PA12</td><td>-</td></tr><tr><td>S128</td><td>LVDS0_1+ / eDP0_TX1+ / DSI0_D1+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_D1_P/LVDS0_D1_P</td><td>-</td></tr><tr><td>S129</td><td>LVDS0_1- / eDP0_TX1- / DSI0_D1-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_D1_N/LVDS0_D1_N</td><td>-</td></tr><tr><td>S130</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S131</td><td>LVDS0_2+ / eDP0_TX2+ / DSI0_D2+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSI_D2_P/LVDS0_D2_P</td><td>-</td></tr><tr><td>S132</td><td>LVDS0_2- / eDP0_TX2- / DSI0_D2-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSI_D2_N/LVDS0_D2_N</td><td>-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>Out</td><td>PD-100K</td><td>GPIO/1.8V</td><td>MCU(STM32L431)</td><td>PA11</td><td>-</td></tr><tr><td>S134</td><td>LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_CLK_P/LVDS0_CLK_P</td><td>-</td></tr><tr><td>S135</td><td>LVDS0_CK- / eDP0_AUX- / DSI0_CLK-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSICSI_CLK_N/LVDS0_CLK_N</td><td>-</td></tr><tr><td>S136</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S137</td><td>LVDS0_3+ / eDP0_TX3+ / DSI0_D3+</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSI_D3_P/LVDS0_D3_P</td><td>-</td></tr><tr><td>S138</td><td>LVDS0_3- / eDP0_TX3- / DSI0_D3-</td><td>Out</td><td>-</td><td>DSI/LVDS</td><td>i.MX95</td><td>DSI_D3_N/LVDS0_D3_N</td><td>-</td></tr><tr><td>S139</td><td>I2C_LCD_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C / 1.8V</td><td>i.MX95</td><td>I2C2_SCL</td><td>Alt0</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C / 1.8V</td><td>i.MX95</td><td>I2C2_SDA</td><td>Alt0</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>GPIO_IO19</td><td>Alt1</td></tr><tr><td>S142</td><td>GPIO12</td><td>In/Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PA4</td><td>-</td></tr><tr><td>S143</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S144</td><td>eDP0_HPD / DSI0_TE</td><td>In</td><td>PD-1M</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O15</td><td>-</td></tr><tr><td>S145</td><td>WDT_TIME_OUT#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>i.MX95</td><td>WDOG_ANY</td><td>Alt0</td></tr><tr><td>S146</td><td>PCIE_WAKE#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>GPIO expander(PCAL6408)</td><td>P6</td><td>-</td></tr><tr><td>S147</td><td>VDD_RTC</td><td>PWR</td><td>-</td><td>Analog / 2V~3.25V</td><td>PCF8563BS</td><td>VDD</td><td>-</td></tr><tr><td>S148</td><td>LID#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O9</td><td>-</td></tr><tr><td>S149</td><td>SLEEP#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O10</td><td>-</td></tr><tr><td>S150</td><td>VIN_PWR_BAD#</td><td>In</td><td>PU-10K</td><td>GPIO / 5V</td><td>Logic IC</td><td>Logic IC</td><td>-</td></tr><tr><td>S151</td><td>CHARGING#</td><td>Out</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O11</td><td>-</td></tr><tr><td>S152</td><td>CHARGER_PRSNT#</td><td>Out</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O12</td><td>-</td></tr><tr><td>S153</td><td>CARRIER_STBY#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>Logic IC</td><td>Logic IC</td><td>-</td></tr><tr><td>S154</td><td>CARRIER_PWR_ON</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>Logic IC</td><td>Logic IC</td><td>-</td></tr><tr><td>S155</td><td>FORCE_RECOV#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>MCU(STM32L431)</td><td>PC9</td><td>-</td></tr><tr><td>S156</td><td>BATLOW#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O13</td><td>-</td></tr><tr><td>S157</td><td>TEST#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>GPIO expander(SX1509)</td><td>I/O14</td><td>-</td></tr><tr><td>S158</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr></table>

# 5. Software Support

# Early Access

All software should use the standard NXP BSP release, with source code available in our Git repository.

Deliverables: Prebuilt runtime images will be available at launch for quick evaluation.

# Yocto

based on the NXP Yocto upstream repository: https://github.com/Freescale/meta-freescale

Available on the ADLINK GitHub site: https://github.com/ADLINK/meta-adlink-nxp

• Yocto meta layer with u-boot, kernel, and root filesystem
• Yocto binary image for quick evaluation
• User guide for building the BSP and deploying the binary image

# Android

By project basis.

# 6. Mechanical and Thermal

# Module Dimensions

The module must be SMARC Short Size (82 x 50 mm)

![Preferred Area for\nRF Connectors\n(Top Side)\nKeep Out Area\n(Top and Bottom Side)\n5.10 mm](.lec-imx95-user-manual-50m-72520-1020-12/cb7734b298f81707086ed03c226efee1f5b817bb3df2ac04b9b502128f6e2d5e.jpg)

Figure 3 – Module dimensions

# Thermal Solutions

# Heatspreader: HTS

Sustained temperature range with high-performance LAB copper heatsink and high airflow: $\scriptscriptstyle - 4 0 ^ { \circ } \mathsf { C }$ to $8 5 ^ { \circ } \mathsf { C }$ ambient.

![The image displays a technical line drawing of a rectangular mechanical plate in three views.\n\n*   **Top Left:** An angled view of the underside, showing a flat plate with four threaded mounts at the corners and four smaller circular holes near the center.\n*   **Top Right:** An angled view of the top surface. Red arrows label specific components: arrow **1** points to the main plate surface, arrow **2** points to a square rim, and arrow **3** points to the central square inset. The text **NC1817** is printed on the plate near the bottom right corner.\n*   **Bottom:** A side profile view showing the plate's thickness, with a central recessed area and small mounting feet at either end.](.lec-imx95-user-manual-50m-72520-1020-12/140dc17622dc45eaea8c88a776267a26df11165b47a2d696b2f56f3c9b5439bc.jpg)

![need to check the character size & position.'\nNC1817\n② 42±0.2\n① 82±0.2](.lec-imx95-user-manual-50m-72520-1020-12/83dbc7b08f01bd901265129b5e521aae81a8aee12df0ea6678a78d597b652554.jpg)

![⑤ 2.2±0.1\n④ 0.8±0.1\n③ 6±0.2](.lec-imx95-user-manual-50m-72520-1020-12/d9bf509d7a36455ae9198ecb59c9e5cfa3513edae77a58cf41f6c325d250c820.jpg)

Figure 4 – Heatspreader: HTS

# Heatsink: THS

Sustained temperature range with moderate airflow: $0 \%$ to $6 0 ^ { \circ } \mathsf { C }$ ambient.

![This image is a technical drawing of a heat sink, likely for an electronic component, presented in four views with dimensions and callouts.\n\n**Top Left View:**\n*   An isometric view showing the heat sink's base plate, mounting holes, and fins.\n*   The text '**NC1818**' is printed near the bottom left corner.\n*   Red callouts point to specific features: **(1)** the flat base area, **(2)** the fins, and **(3)** the central square recess.\n\n**Top Right View:**\n*   An isometric view focusing on the array of fins.\n\n**Bottom Left View:**\n*   A top-down orthographic view showing the fin layout and corner mounting holes.\n*   Dimension **(1)** indicates a length of **82±0.3**.\n*   Dimension **(2)** indicates a width of **42±0.3**.\n\n**Bottom Right View:**\n*   A side profile view showing the cross-section of the base and fins.\n*   Dimension **(5)** at the top indicates a measurement of **2.2±0.1**.\n*   Dimension **(4)** in the middle indicates a measurement of **0.8±0.1**.\n*   Dimension **(3)** at the bottom indicates a measurement of **12±0.3**.](.lec-imx95-user-manual-50m-72520-1020-12/6f79af2c36826cf1231f52ab8d7e3a8aa3a988b4f69bdcaf731dfd828f09a1fb.jpg)
Figure 5 – Heatsink: THS
[🔗 Link to the original document](.lec-imx95-user-manual-50m-72520-1020-12/lec-imx95-user-manual-50m-72520-1020-12.pdf)