# LEC-PX30 # User’s Guide 22/01/2020 Rev. 0.7 Corrected engineering version ![Green printed circuit board with various electronic components and gold contacts (no visible text or symbols)](.lec-px30-0203-07/4953c892ea32848da537fc494c1f883864ce67a1d05d9e66132ae85f84e3a79c.jpg) # Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # © Copyright 2020 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![A red outline icon of a document with a folded top-right corner. Inside the white space, there are two horizontal red lines representing text.](.lec-px30-0203-07/6e34323c88626fa30baa4bb30667bc835ce99768d373c72b2a06911862addc7b.jpg) Note: This information adds clarity or specifics to text and illustrations. ![The image displays a yellow triangular warning sign with a black outline. Inside the triangle is a black exclamation point.](.lec-px30-0203-07/e2c42eefc2e49255dce60677a9e8ca63dcfd0c01eacc600ff76e7faeca0a1f30.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![A red triangular warning sign featuring a white exclamation mark in the center.](.lec-px30-0203-07/190cf58b419eb7cf015bd8ae542614761ba14398fbb11be4a1ca2c16af754ac9.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Revision History
RevisionDescriptionDateAuthor
0.6Engineering version22/8/2019JB
0.7Corrected engineering version, mechanical and SMARC to controller table6/9/2019JB
# Table of Contents 1. Introduction .. 1.1 The SMARC Formfactor . 2. Specifications.. . 8 2.1 Core System... ...8 2.2 Video.... ...9 2.3 Audio ... ... 10 2.4 Dual Ethernet... ... 10 2.5 Extension busses... ... 10 2.6 System Storage .. ... 12 2.7 SEMA® Board Management Controller .. ... 12 2.8 Debug Header ... ... 12 2.9 Power... ... 12 2.10 Mechanical and Environmental . ... 13 3. Block Diagram .. .14 4. Pinout and Signal Descriptions ........ ... 15 4.1 Pin Summary .. ... 15 4.2 Signal Terminology Descriptions.. ... 19 4.3 Signal Description by function... ... 20 4.3.1 The First Display Interface . .. 20 4.3.2 Second & Third Display Interface . .. 23 4.3.3 MIPI Cameras.. .. 24 4.3.4 Audio.. .. 25 4.3.5 USB... ... 26 4.3.6 PCIe and SerDes pin sharing... . 28 4.3.7 SATA .. ... 28 4.3.8 LAN ... .. 29 4.3.9 SDIO... .. 31 4.3.10.... . 31 4.3.11 SPI ..... .. 32 4.3.12 GPIO... ... 33 4.3.13 UART... .. 34 4.3.14 CAN bus.. .. 35 4.3.15 Miscellaneous ... . 35 4.3.16 Power and System Management . .. 36 4.3.17 Boot Select... ... 38 4.3.18 Power .. .. 39 4.4 SMARC pin to controller mapping... .. 40 5. Software Support ... .51 5.1.1 Early Access . . 51 5.1.2 Yocto .. .. 51 5.1.3 Ubuntu... .. 51 6. Mechanical and Thermal... .52 6.1 Module dimensions.. . 52 6.2 Thermal Solutions .. . 53 6.2.1 Heatspreader : HTS .. .. 53 6.2.2 Heatsink : THS .. . 54 # List of Figures Figure 1 – Module function diagram... .14 Figure 2 – Module top/botom side pin numbering .............. ... 15 Figure 3 – Heatspreader HTS-sPX30.... ... 53 # 1. Introduction ![A red triangular warning sign with rounded corners containing a centered white exclamation point.](.lec-px30-0203-07/fbd9dc9e17fb9f1884b872ce0fb931f6a64cd11dd55dc57268af8707b6762908.jpg) Warning: this is an EA (early available) engineering manual, meaning contents might properly reflect the actual or final version of this product # 1.1 The SMARC Formfactor The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer on Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented X86 devices and other RISC CPUs may be used as well. The Module power envelope is typically under 6W. Two Module sizes are defined: 82 mm x 50 mm and 82 mm x 80 mm. The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, but 7 pins are lost to the key). The Modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the Module. The Modules are used with application specific Carrier Boards that implement other features such as audio CODECs, touch controllers, wireless devices, etc. The modular approach allows scalability, fast time to market and upgradability while still maintaining low costs, low power and small physical size. ![The image displays the text 'SGTe'. The letters 'S', 'G', and 'T' are large and yellow. The letter 'e' is smaller, colored magenta, and positioned in the lower right area beneath the 'G' and 'T'.](.lec-px30-0203-07/76a88c136ee3e941b5a1d616c41a7de63d4ac7618b4b8a40f27ff3c5de329452.jpg) STANDARDIZATION GROUP FOR EMBEDDED TECHNOLOGIES SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html # 2. Specifications # 2.1 Core System # SoC Rockchip PX30 with Quad-core ARM Cortex-A35 CPU TrustZone technology support ARMv8 Cryptography Extensions” # Memory 1GB or 2GB DDR3L at 1066/1333 MHz, memory down (non ECC) # L2 Cache 256KB unified system L2 cache # IoT security CryptoAuthentication™ Device, Microchip ATECC608A Cryptographic co-processor with secure hardware-based key storage for sign-verify authentication provides Internet of Things (IoT) Protected Storage for up to 16 keys, certificates or data ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman NIST standard P256 elliptic curve support SHA-256 & HMAC hash including off-chip context save/restore AES-128: encrypt/decrypt, galois field multiply for GCM” # 2.2 Video LEC-PX30 standard display support is limited to either 4-lane MIPI DSI or single channel 24-bit LVDS. DSI and LVDS are multiplexed and either of them can simply be enabled at boot time. HDMI panel support up to 1920x1080 resolution can be achieved by using a simple bridge on the carrier. A reference design based on ADV7335 “MIPI/DSI Receiver with HDMI Transmitter” is available # GPU Core: Mali-G31 # GPU Feature Support Supports DirectX 11 FL9\_3, OpenGLES 1.1/ 2.0 / 3.2, Vulkan 1.0, OpenCL 2.0 Full Profile Video decoding: H.264 up to 1080p@60fps, H.265/HEVC up to 1080p@60fps MPEG-4, ISO/IEC 14496-2, SP@L0-3, ASP@L0-5, up to 1080p@60fps VP8, up to 1080p@60fps Video Encoding: H.264 video encoder at BP/MP/HP@level 4.2 1920x1080@30fps, 1x 1080p@30fps or 2x 720p@30fps encoding # MIPI DSI MIPI DSI 4 lanes at max. 1080p@60fps display output (default, multiplexed with LVDS signal) # LVDS LVDS single channel 24-bit at max. 1280x800@60fps (multiplexed with MIPI DSI signal) # Camera MIPI CSI RX Interface \- Compatible with the MIPI Alliance Interface specification v1.0 \- Up to 4 data lanes, 1.0Gbps maximum data rate per lane, supporting MIPI-HS, MIPI-LP mode # 2.3 Audio Supports ES8316 codec for high performance and low power multi-bit deltasigma audio ADC and DAC (located on carrier) # 2.4 Dual Ethernet # Primary LAN MAC 10/100 Ethernet Controller on SoC Supports 10/100-Mbps data transfer rates, both full-duplex and half-duplex # Secondary LAN MAC/PHY 10/100 Ethernet Controller on LAN9514 via USB 2.0 Supports 10/100-Mbps data transfer rates, both full-duplex and half-duplex # 2.5 Extension busses # USB 4x USB 2.0, 1x USB OTG # UART Two UART interfaces SER0 and SER2 (TX/X/CTS/RTS), 64-byte FIFO and support for 5-bit, 6-bit, 7-bit, 8-bit data transmit or receive # CAN bus Supports CAN2.0B only or mixed CAN2.0B and CAN FD mode, data bit rate up to 8 Mbps # SPI 2x SPI (one occupied by SPI-to-CAN controller) # I2S 2x I2S interfaces with audio resolution from 16-bits to 32-bits and sample rate up to 192KHz (see Audio Codec support) # I2C Four I2C interfaces - Support for 7-bit and 10-bit address mode - Software programmable clock frequency of 100 kbit/s in Standard-mode, 400 kbit/s in the Fast-mode or 1 Mbit/s in Fast-mode Plus # GPIO 12x GPIO with interrupt, one GPIO with PWM # 2.6 System Storage # SDIO 1x SDIO (4-bit) compatible with SD3.0, MMC ver. 4.51 # eMMC 8, 16, 32 or 64 GB (build option) Compatible with eMMC specification 4.41, 4.51, 5.0 and 5.1 # 2.7 SEMA® Board Management Controller Voltage/current monitoring, boot configuration, logistics and forensic information, flat panel control, watchdog timer # 2.8 Debug Header 30-pin multipurpose flat cable connector for use with optional DB-30 debug module Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration # 2.9 Power # Supply Voltage 4.75 V – 5.25 V # Rise Time TBD # 2.10 Mechanical and Environmental # Form Factor SGET SMARC Specifications v2.1 (2.1 is currently under approval by SGET) # Dimension SMARC short size module, 82mm x 50mm # Operating Temperature Standard: 0°C to +60°C Rugged: -20°C to +85°C (optional) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # 3. Block Diagram ![The diagram illustrates the block diagram of a system based on the central processor.\n\n**Central Block:**\n* **Rockchip PX30**\n\n**Left Side Connections (External Interface Block):**\n* **DSI0 / LVDS0** connects to **MPI DSI 4 lanes / 24-bit LVDS**.\n* **CSI1** connects to **MIPI CSI 4 lanes**.\n* **SDIO** connects to **SDMMC0 4-bit**.\n* **USB0** connects to **USB 2.0 OTG**.\n* **USB1**, **USB2**, **USB3**, and **USB4** connect to **LAN9514**, which connects to **USB 2.0 Host**.\n* **GbE0** (labeled **10/100Mbps**) connects to **LAN9514**.\n* **GbE1** (labeled **10/100Mbps**) connects to **PHY**, which connects to the central block.\n* **UART0** and **UART1** connect directly to the central block.\n* **CAN0** connects to **CAN + FD**, which connects to the central block.\n* **SPI1** and **SPI0** connect directly to the central block.\n* **I2S0** and **I2S1** connect directly to the central block.\n* **I2C_PM** connects to **PMIC**, which connects to the central block.\n* **I2C_GP** connects to **Crypto Auth. ATECC608A**, which connects to the central block.\n* **Watchdog / Boot Select, Power Control** connects to **Board Management Controller**, which connects to the central block.\n\n**Right and Bottom Connections:**\n* Four blocks labeled **DDR3L x16** connect to the central block.\n* **eMCC 8/16/32/64GB** connects to the central block.\n* **30-pin debug** connects to the central block.\n* **RTC** connects to the central block.\n* **Board Management Controller** connects to the central block.](.lec-px30-0203-07/36db1cfd355bf1ddf5d0152e903341dce7424f6519a43d5f27f39918b0add559.jpg) Figure 1 – Module function diagram # 4. Pinout and Signal Descriptions # 4.1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. Those signals not supported on LEC-PX30 are strikethrough STRIKETHROUGH ![TOP Side\nP1 P74 P75 P156\nKey](.lec-px30-0203-07/023d6a1e65c94765c9b7baa2770deb7f3b4bb6eb9556687258cae711adf721da.jpg) ![BOTTOM Side\nS156 S76 S75 S1\nKey](.lec-px30-0203-07/5ba338296d327c52bfbeee903f3e083d9e20daa0bf5bcf800c21f1ab320c4a59.jpg) Figure 2 – Module top/botom side pin numbering
P-PinPrimary (Top) Side
P1SMB_ALERT_1V8#
P2GND
P3CSI1_CK+
P4CSI1_CK-
P5GBE1_SDP
P6GBE0_SDP
P7CSI1_RX0+
P8CSI1_RX0-
P9GND
P10CSI1_RX1+
P11CSI1_RX1-
P12GND
P13CSI1_RX2+
P14CSI1_RX2-
P15GND
P16CSI1_RX3+
P17CSI1_RX3-
P18GND
P19GBE0_MDI3-
P20GBE0_MDI3+
P21GBE0_LINK100#
P22GBE0_LINK1000#
P23GBE0_MDI2-
P24GBE0_MDI2+
P25GBE0_LINK_ACT#
P26GBE0_MDI1-
P27GBE0_MDI1+
P28GBE0_CTREF
P29GBE0_MDIO-
P30GBE0_MDIO+
P31SPI0_CS1#
P32GND
P33SDIO_WP
P34SDIO_CMD
S-PinSecondary (Bottom) Side
S1CSI1_TX+ / I2C_CAM1_CK
S2CSI1_TX- / I2C_CAM1_DAT
S3GND
S4RSVD
S5CSI0_TX- / I2C_CAM0_CK
S6CAM_MCK
S7CSI0_TX+ / I2C_CAM0_DAT
S8CSI0_CK+
S9CSI0_CK-
S10GND
S11CSI0_RX0+
S12CSI0_RX0-
S13GND
S14CSI0_RX1+
S15CSI0_RX1-
S16GND
S17GBE1_MDIO+
S18GBE1_MDIO-
S19GBE1_LINK100#
S20GBE1_MDI1+
S21GBE1_MDI1-
S22GBE1_LINK1000#
S23GBE1_MDI2+
S24GBE1_MDI2-
S25GND
S26GBE1_MDI3+
S27GBE1_MDI3-
S28GBE1_CTREF
S29PCIE_D_TX+ / SERDES_1_TX+
S30PCIE_D_TX- / SERDES_1_TX-
S31GBE1_LINK_ACT#
S32PCIE_D_RX+ / SERDES_1_RX+
S33PCIE_D_RX- / SERDES_1_RX-
S34GND
S35USB4+
P-PinPrimary (Top) Side
P35SDIO_CD#
P36SDIO_CK
P37SDIO_PWR_EN
P38GND
P39SDIO_D0
P40SDIO_D1
P41SDIO_D2
P42SDIO_D3
P43SPI0_CS0#
P44SPI0_CK
P45SPI0_DIN
P46SPI0_DO
P47GND
P48SATA_TX+
P49SATA_TX-
P50GND
P51SATA_RX+
P52SATA_RX-
P53GND
P54ESPI_CS0# / SPI1_CS0#
P55ESPI_CS1# / SPI1_CS1#
P56ESPI_CK / SPI1_CK
P57ESPI_IO_1 / SPI1_DIN
P58ESPI_IO_0 / SPI1_DO
P59GND
P60USB0+
P61USB0-
P62USB0_EN_OC#
P63USB0_VBUS_DET
P64USB0_OTG_ID
P65USB1+
P66USB1-
P67USB1_EN_OC#
P68GND
P69USB2+
S-PinSecondary (Bottom) Side
S36USB4-
S37USB3_VBUS_DET
S38AUDIO_MCK
S39I2S0_LRCK
S40I2S0_SDOUT
S41I2S0_SDIN
S42I2S0_CK
S43ESPI_ALERT0#
S44ESPI_ALERT1#
S45MDIO_CLK
S46MDIO_DAT
S47GND
S48I2C_GP_CK
S49I2C_GP_DAT
S50HDA_SYNC / I2S2_LRCK
S51HDA_SDO / I2S2_SDOUT
S52HDA_SD1 / I2S2_SDIN
S53HDA_CK / I2S2_CK
S54SATA_ACT#
S55USB5_EN_OC#
S56ESPI_IO_2
S57ESPI_IO_3
S58ESPI_RESET#
S59USB5+
S60USB5-
S61GND
S62USB3_SSTX+
S63USB3_SSTX-
S64GND
S65USB3_SSRX+
S66USB3_SSRX-
S67GND
S68USB3+
S69USB3-
S70GND
P-PinPrimary (Top) Side
P70USB2-
P71USB2_EN_OC#
P72RSVD
P73RSVD
P74USB3_EN_OC#
Key
P75PCIE_A_RST#
P76USB4_EN_OC#
P77PCIE_B_CKREQ#
P78PCIE_A_CKREQ#
P79GND
P80PCIE_C_REFCK+
P81PCIE_C_REFCK-
P82GND
P83PCIE_A_REFCK+
P84PCIE_A_REFCK-
P85GND
P86PCIE_A_RX+
P87PCIE_A_RX-
P88GND
P89PCIE_A_TX+
P90PCIE_A_TX-
P91GND
P92HDMI_D2+/DP1_LANE0+
P93HDMI_D2-/DP1_LANE0-
P94GND
P95HDMI_D1+/DP1_LANE1+
P96HDMI_D1-/DP1_LANE1-
P97GND
P98HDMI_D0+/DP1_LANE2+
P99HDMI_D0-/DP1_LANE2-
P100GND
P101HDMI_CK+/DP1_LANE3+
P102HDMI_CK-/DP1_LANE3-
S-PinSecondary (Bottom) Side
S71USB2_SSTX+
S72USB2_SSTX-
S73GND
S74USB2_SSRX+
S75USB2_SSRX-
Key
S76PCIE_B_RST#
S77PCIE_C_RST#
S78PCIE_C_RX+ / SERDES_2_RX+
S79PCIE_C_RX- / SERDES_2_RX-
S80GND
S81PCIE_C_TX+ / SERDES_2_TX+
S82PCIE_C_TX- / SERDES_2_TX-
S83GND
S84PCIE_B_REFCK+
S85PCIE_B_REFCK-
S86GND
S87PCIE_B_RX+
S88PCIE_B_RX-
S89GND
S90PCIE_B_TX+
S91PCIE_B_TX-
S92GND
S93DPO_LANEO+
S94DPO_LANEO-
S95DPO_AUX_SEL
S96DPO_LANE1+
S97DPO_LANE1-
S98DPO_HPD
S99DPO_LANE2+
S100DPO_LANE2-
S101GND
S102DPO_LANE3+
S103DPO_LANE3-
P-PinPrimary (Top) Side
P103GND
P104HDMI_HPD / DP1_HPD
P105HDMI_CTRL_CK / DP1_AUX+
P106HDMI_CTRL_DAT /
P107DP1_AUX_SEL
P108GPIO0 / CAM0_PWR#
P109GPIO1 / CAM1_PWR#
P110GPIO2 / CAM0_RST#
P111GPIO3 / CAM1_RST#
P112GPIO4 / HDA_RST#
P113GPIO5 / PWM_OUT
P114GPIO6 / TACHIN
P115GPIO7
P116GPIO8
P117GPIO9
P118GPIO10
P119GPIO11
P120GND
P121I2C_PM_CK
P122I2C_PM_DAT
P123BOOT_SEL0#
P124BOOT_SEL1#
P125BOOT_SEL2#
P126RESET_OUT#
P127RESET_IN#
P128POWER_BTN#
P129SER0_TX
P130SER0_RX
P131SER0_RTS#
P132SER0_CTS#
P133GND
P134SER1_TX
P135SER1_RX
P136SER2_TX
P137SER2_RX
P138SER2_RTS#
S-PinSecondary (Bottom) Side
S104USB3_OTG_ID
S105DP0_AUX+
S106DP0_AUX-
S107LCD1_BKLT_EN
S108LVDS1_CK+/ eDP1_AUX+/-
S109LVDS1_CK-/ eDP1_AUX-/-
S110GND
S111LVDS1_0+/ eDP1_TX0+/ DSI1_D0+
S112LVDS1_0-/ eDP1_TX0-/ DSI1_D0-
S113eDP1_HPD/ DSI1_TE
S114LVDS1_1+/ eDP1_TX1+/ DSI1_D1+
S115LVDS1_1-/ eDP1_TX1-/ DSI1_D1-
S116LCD1_VDD_EN
S117LVDS1_2+/ eDP1_TX2+/ DSI1_D2+
S118LVDS1_2-/ eDP1_TX2-/ DSI1_D2-
S119GND
S120LVDS1_3+/ eDP1_TX3+/ DSI1_D3+
S121LVDS1_3-/ eDP1_TX3-/ DSI1_D3-
S122LCD1_BKLT_PWM
S123GPIO13
S124GND
S125LVDS0_0+/ eDP0_TX0+/ DSI0_D0+
S126LVDS0_0-/ eDP0_TX0-/ DSI0_D0-
S127LCD0_BKLT_EN
S128LVDS0_1+/ eDP0_TX1+/ DSI0_D1+
S129LVDS0_1-/ eDP0_TX1-/ DSI0_D1-
S130GND
S131LVDS0_2+/ eDP0_TX2+/ DSI0_D2+
S132LVDS0_2-/ eDP0_TX2-/ DSI0_D2-
S133LCD0_VDD_EN
S134LVDS0_CK+/eDP0_AUX/ DSI0_CLK+
S135LVDS0_CK-/eDP0_AUX-/ DSI0_CLK-
S136GND
S137LVDS0_3+/ eDP0_TX3+/ DSI0_D3+
S138LVDS0_3-/ eDP0_TX3-/ DSI0_D3-
S139I2C_LCD_CK
P-PinPrimary (Top) Side
P139SER2_CTS#
P140SER3_TX
P141SER3_RX
P142GND
P147VDD_IN
P148VDD_IN
P149VDD_IN
P150VDD_IN
P151VDD_IN
P152VDD_IN
S-PinSecondary (Bottom) Side
S140I2C_LCD_DAT
S141LCD0_BKLT_PWM
S142GPIO12
S143GND
S148LID#
S149SLEEP#
S150VIN_PWR_BAD#
S151CHARGING#
S152CHARGER_PRSNT#
S153CARRIER_STBY#
P-PinPrimary (Top) Side
P143CAN0_TX
P144CAN0_RX
P145CAN1_TX
P146CAN1_RX
P153VDD_IN
P154VDD_IN
P155VDD_IN
P156VDD_IN
S-PinSecondary (Bottom) Side
S144eDP0_HPD / DSIO_TE
S145WDT_TIME_OUT#
S146PCIE_WAKE#
S147VDD_RTC
S154CARRIER_PWR_ON
S155FORCE_RECOV#
S156BATLOW#
S157TEST#
S158GND
![The image displays a red icon depicting a document or memo. It consists of a red outline shaped like a page with the bottom-right corner folded up. Inside the border, two horizontal red lines are centered, symbolizing text.](.lec-px30-0203-07/44e9417c184b8f9dd8040175420687fcff45181a78f65df5b3f17c12a2ffb19d.jpg) Note: STRIKETHROUGH strike-through entries are not supported functions on this product ![The image displays a red-outlined icon resembling a document or piece of paper with rounded corners and a folded bottom-right corner. Inside the white shape, there are two horizontal red lines stacked vertically, resembling an equals sign.](.lec-px30-0203-07/4bbab33f9d8ed9ec866d4c4ee1bc67f7be9fdc398edcc426ca6671c5625fff4f.jpg) Note: Both LVDS0 and DSI0 (default) are supported, either function can be enabled at boot time in the DTS (Device Tree) # 4.2 Signal Terminology Descriptions Meaning of the terms used for signal description tables
TermDescription
IInput to the module
OOutput from the module
O ODOpen drain output from the module
I ODOpen drain input to the module, with mandatory PU (pull up) on module
ODOpen drain
I/OBi-directional Input/Output
PUPU (pull-up) resistor on module
PDPD (pull-down) resistor on module
VDD_INMain power source from carrier to module
CMOSLogic input or output
GBE MDIDifferential analog signaling for Gigabit Media Dependent Interface
LVDS DPLow Voltage Differential Signal for DisplayPort interface
LVDS D-PHYLow Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays
LVDS M-PHYLow Voltage Differential Signal for MIPI CSI-3 cameras
LVDS LCDLow Voltage Differential Signal for LCD displays
LVDS PCIELow Voltage Differential Signal for PCIe
LVDS SATALow Voltage Differential Signal for SATA
TMDS HDMITransition Minimized Differential Signal for HDMI displays
USBDC coupled differential signaling for traditional (non-Superspeed) USB signals
USB SSDifferential signal for SuperSpeed USB signals
USB VBUS 5V5V tolerant input for USB VBUS detection
3.3V3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
1.8V1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
3.3Vsb3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
1.8Vsb1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
# 4.3 Signal Description by function # 4.3.1 The First Display Interface This is a group of 30-pins that is split into a channel 0 and channel 1 and can support either dual channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI and eDP is also permitted.
Pin #LVDS NameMIPI DSI NameeDP Name
S125LVDS0_0+DSI0_D0+eDP0_TX0+
S126LVDS0_0-DSI0_D0-eDP0_TX0-
S128LVDS0_1+DSI0_D1+eDP0_TX1+
S129LVDS0_1 -DSI0_D1-eDP0_TX1-
S131LVDS0_2+DSI0_D2+eDP0_TX2+
S132LVDS0_2-DSI0_D2-eDP0_TX2-
S137LVDS0_3+DSI0_D3+eDP0_TX3+
S138LVDS0_3-DSI0_D3-eDP0_TX3-
S134LVDS0_CK+DSI0_CLK+eDP0_AUX+
S135LVDS0_CK-DSI0_CLK-eDP0_AUX-
S133LCD0_VDD_ENLCD0_VDD_ENLCD0_VDD_EN
S127LCD0_BKLT_ENLCD0_BKLT_ENLCD0_BKLT_EN
S141LCD0_BKLT_PWMLCD0_BKLT_PWMLCD0_BKLT_PWM
S144DSI0_TEeDP0_HPD
S139I2C_LCD_CKI2C_LCD_CKI2C_LCD_CK
S140I2C_LCD_DATI2C_LCD_DATI2C_LCD_DAT
Pin #LVDS NameMIPI DSI NameeDP Name
S111LVDS1_0+DSI1_D0+eDP1_TX0+
S112LVDS1_0-DSI1_D0-eDP1_TX0-
S114LVDS1_1+DSI1_D1+eDP1_TX1+
S115LVDS1_1-DSI1_D1-eDP1_TX1-
S117LVDS1_2+DSI1_D2+eDP1_TX2+
S118LVDS1_2-DSI1_D2-eDP1_TX2-
S120LVDS1_3+DSI1_D3+eDP1_TX3+
S121LVDS1_3-DSI1_D3-eDP1_TX3-
S108LVDS1_CK+DSI1_CLK+eDP1_AUX+
S109LVDS1_CK-DSI1_CLK-eDP1_AUX-
S116LCD1_VDD_ENLCD1_VDD_ENLCD1_VDD_EN
S107LCD1_BKLT_ENLCD1_BKLT_ENLCD1_BKLT_EN
S122LCD1_BKLT_PWMLCD1_BKLT_PWMLCD1_BKLT_PWM
S113DSI1_TEeDP1_HPD
Above tables for LVDS, DSI and eDP describe signals that are supported on this product. Unsupported signals are crossed out (STRIKETHROUGH) or in case multiplexed (either or) this will be described in the NOTES of the signal description tables by type. ![The image features a red outline icon of a document or page with a folded top-right corner. Inside the white interior, there are two horizontal red bars centered vertically.](.lec-px30-0203-07/c6c2eacdc7835830464d4eeeaaf7644535b4e551ea6bbcfc3f93e75fb32a14a0.jpg) Note: DSI0 mode or LVDS0 can be selected at boot time through DVT (device tree), DSI0 is default 4.3.1.1 LVDS0 mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
LVDS0_0+S125Primary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS0_0-S126
LVDS0_1+S128
LVDS0_1 -S129
LVDS0_2+S131
LVDS0_2-S132
LVDS0_3+S137
LVDS0_3-S138
LVDS0_CK+S134Primary LVDS channel differential pair clock linesO LVDS LCDRuntime
LVDS0_CK-S135
LCD0_VDD_ENS133Primary LVDS channel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary LVDS channel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary LVDS channel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
4.3.1.2 DSI0 mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
DSI0_D0+S125Primary DSI panel differential pair data linesO LVDS D-PHYRuntime
DSI0_D0-S126
DSI0_D1+S128
DSI0_D1-S129
DSI0_D2+S131
DSI0_D2-S132
DSI0_D3+S137
DSI0_D3-S138
DSI0_CLK+S134Primary DSI panel differential pair clock lines.O LVDS D-PHYRuntime
DSI0_CLK-S135
LCD0_VDD_ENS133Primary panel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary panel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary panel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
DSI0_TES144Primary DSI panel tearing effect signalI CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
# 4.3.2 Second & Third Display Interface All the below signals on Second Interface are not supported
Pin #HDMI signal namesDP++ signal names
P92HDMI_D2+DP1_LANE0+
P93HDMI_D2-DP1_LANE0-
P95HDMI_D1+DP1_LANE1+
P96HDMI_D1-DP1_LANE1-
P98HDMI_D0+DP1_LANE2+
P99HDMI_D0-DP1_LANE2-
P101HDMI_CK+DP1_LANE3+
P102HDMI_CK-DP1_LANE3-
S105HDMI_CTRL_CKDP1_AUX+
S106HDMI_CTRL_DATDP1_AUX-
P104HDMI_HPDDP1_HPD
P107-DP1_AUX_SEL
All the below signals on Third Interface are not supported
Pin #DP++ signal names
P92DPO_LANE0+
P93DPO_LANE0-
P95DPO_LANE1+
P96DPO_LANE1-
P98DPO_LANE2+
P99DPO_LANE2-
P101DPO_LANE3+
P102DPO_LANE3-
S105DPO_AUX+
S106DPO_AUX-
P104DPO_HPD
P107DPO_AUX_SEL
![This is a red icon depicting a document or page with a folded bottom-right corner. Inside the red border, there are two horizontal parallel lines, representing lines of text.](.lec-px30-0203-07/1d4e476ac7e59925ea24440cc2d82b393d78b79ff28bde3694ebeea0bf1b4957.jpg) Note: HDMI support with a resolution of up to 1920x1080 can be implemented through a DSI to HDMI on the IPi-SMARC carrier, a reference design based on Analog Devices’ ADV7533 MIPI/DSI Receiver with HDMI Transmitter is available on request # 4.3.3 MIPI Cameras # 4.3.3.1 MIPI CSI0 Not supported 4.3.3.2 MIPI CSI1
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI1_RX0+P7CSI1 differential input (point to point)I LVDS D-PHY / I LVDS M-PHYRuntime
CSI1_RX0-P8
CSI1_RX1+P10
CSI1_RX1-P11
CSI1_RX2+P13
CSI1_RX2-P14
CSI1_RX3+P16
CSI1_RX3-P17
CSI1_CK+P3CSI1 differential clock input (point to point)I LVDS D-PHYRuntime
CSI1_CK-P4
I2C_CAM1_DAT / CSI1_TX-S2I2C data for serial camera data support link or differential data laneI/O OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_DAT MIPI-CSI 3.0 mode uses CSI1_TX-
I2C_CAM1_CK / CSI1_TX+S1I2C clock for serial camera data support link or differential data laneO OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_CK MIPI-CSI 3.0 mode uses CSI1_TX+
CAM1_PWR# / GPIO1P109Camera 0 Power Enable, active low output.O CMOS1.8VRuntimeCAM1_PWR# is default, GPIO1 can be enabled through DVT
CAM1_RST# / GPIO3P111Camera 0 reset, active low outputO CMOS1.8VRuntimeCAM1_PWR# is default, GPIO3 can be enabled through DVT
CAM_MCKS6Master clock outputO CMOS1.8VRuntime
# 4.3.4 Audio 4.3.4.1 I2S0 / I2S2
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2S0_LRCKS39I2S0 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S0_SDOUTS40I2S0 Digital audio OutputO CMOS1.8VRuntime
I2S0_SDINS41I2S0 Digital audio InputI CMOS1.8VRuntime
I2S0_CKS42I2S0 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_LRCK / HDA_SYNCS50I2S2 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_SDOUT/ HDA_SDOS51I2S2 Digital audio OutputO CMOS1.8VRuntime
I2S2_SDIN/ HDA_SDIS52I2S2 Digital audio InputI CMOS1.8VRuntime
I2S2_CK/ HDA_CKS53I2S2 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
AUDIO_MCKS38Master clock output to I2S codec(s)O CMOS1.8VRuntime
![The image displays a stylized icon of a document or page. It features a white background with a thick red outline and a folded bottom-right corner (a 'dog-ear'). Inside the white area are three horizontal red lines centered vertically. There is no actual text present.](.lec-px30-0203-07/ad0f72cf6792313c5aa593be1ee752de1c0ec9169ace9aeb7d91548727d5a838.jpg) Note: I2S1 signalling has been removed during update to SMARC 2.0 specification # 4.3.5 USB
<img src="images/d3824ea16c61fb8edee187ac975ddc2d190e66820ec2ac052c46702ea43b8e45.jpg"/>
USB0+USB0-P60P61USB differential data pairs for port 0I/OUSBUSBRuntimeFrom SOC
USB0_EN_OC#P62USB over-current sense for port 0I/O ODCMOS3.3Vsb /3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB0_VBUS_DETP63USB port 0 host power detection,when this port is used as a device.IUSB VBUS5VUSB VBUS5VRuntimeCan be connected to a USB client port VBUS pin
USB0_OTG_IDP64Input pin to announce OTG deviceinsertion on USB 2.0 portICMOS3.3Vsb /3.3VRuntime
USB1+USB1-P65P66USB differential data pairs for port 1I/OUSBUSBRuntimeFrom USB HUB, alternatively USB HUB can be removed, and USB 2.0 Host directly routed to SOC
USB1_EN_OC#P67USB over-current sense for port 1I/O ODCMOS3.3Vsb /3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB2+USB2-P69P70USB differential data pairs for port 2I/OUSBUSBRuntimeFrom USB HUB
USB2_SSRX+USB2_SSRX-S74S75Receive signal differential pairs forSuperSpeed on port 2↓USB SSUSB SSRuntime-USB 3.0 mode not supported
USB2_SSTX+USB2_SSTX-S71S72Transmit signal differential pairs forSuperSpeed on port 2QUSB SSUSB SSRuntime-USB 3.0 mode not supported
USB2_EN_OC#P71USB over-current sense for port 2I/O ODCMOS3.3Vsb /3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB0+USB0-P60P61USB differential data pairs for port 0I/OUSBUSBRuntimeFrom SOC
USB0_EN_OC#P62USB over-current sense for port 0I/O ODCMOS3.3Vsb /3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB0_VBUS_DETP63USB port 0 host power detection,when this port is used as a device.IUSB VBUS5VUSB VBUS5VRuntimeCan be connected to a USB client port VBUS pin
USB0_OTG_IDP64Input pin to announce OTG deviceinsertion on USB 2.0 portICMOS3.3Vsb /3.3VRuntime
USB1+USB1-P65P66USB differential data pairs for port 1I/OUSBUSBRuntimeFrom USB HUB, alternatively USB HUB can be removed, and USB 2.0 Host directly routed to SOC
USB1_EN_OC#P67USB over-current sense for port 1I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB2+USB2-P69P70USB differential data pairs for port 2I/OUSBUSBRuntimeFrom USB HUB
USB2_SSRX+USB2_SSRX-S74S75Receive signal differential pairs for SuperSpeed on port 2↓USB_SSUSB_SSRuntime-USB 3.0 mode not supported
USB2_SSTX+USB2_SSTX-S71S72Transmit signal differential pairs for SuperSpeed on port 2QUSB_SSUSB_SSRuntime-USB 3.0 mode not supported
USB2_EN_OC#P71USB over-current sense for port 2I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB3+USB3-S68S69USB differential data pairs for port 3I/OUSBUSBRuntimeFrom USB HUB
USB3_SSRX+USB3_SSRX-S65S66Receive signal differential pairs for SuperSpeed on port 3↓USB_SSUSB_SSRuntimeUSB 3.0 mode not supported
USB3_SSTX+USB3_SSTX-S62S63Transmit signal differential pairs for SuperSpeed on port 3OUSB_SSUSB_SSRuntimeUSB 3.0 mode not supported
USB3_EN_OC#P74USB over-current sense for port 3I/O OD CMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3_VBUS_DETS37USB port 3 host power detection, when this port is used as a device.↓USB_VBUS 5VUSB_VBUS 5VRuntime
USB3_OTG_IDS104Input pin to announce OTG device insertion on USB 3.0 port↓CMOS3.3Vsb / 3.3VRuntime
USB4+USB4-S35S36USB differential data pairs for port 4I/OUSBUSBRuntimeFrom USB HUB
USB4_EN_OC#P76USB over-current sense for port 4I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
![The image displays a red icon resembling a document or notepad. It features a rectangular shape with the top-right corner folded downward. Inside the shape, two horizontal parallel lines are centered, suggesting text or list items.](.lec-px30-0203-07/b50095fd4714adeec54dbba110f3e40455f64a5640ca76df62b7f01a61144b82.jpg) Note: USB 3 & 4 ports will only be active in final design # 4.3.6 PCIe and SerDes pin sharing # 4.3.6.1 PCIe Ports This design does not support PCIe ports # 4.3.7 SATA This design does not support SATA ports # 4.3.8 LAN
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE0_MD10+P3010/100 Mbps Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1. The MDI can operate in 100, and 10Mbit/sec modes.GBE MDIRuntimeTwisted pair signals for external transformer.
GBE0_MD10-P29
GBE0_MD11+P27
GBE0_MD11-P26
GBE0_MD12+P2410010
GBE0_MD12-P23MDI[0]+/-TX+/-TX+/-
GBE0_MD13+P20MDI[1]+/-RX+/-RX+/-
GBE0_MD13-P19
GBE0_LINK100#P21Link Speed Indication LED for GBE 0 100MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK1000#P22Link Speed Indication LED for GBE 0 1000MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK_ACT#P25Link / Activity Indication LED Driven low on Link (10, 100 mbps) Blinks on ActivityO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_CTREFP28Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)Analog0 to 3.3V maxRuntime
GBE0_SDPP6IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VRuntime--
GBE1_MD10+S1710/100 Mbps Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1. The MDI can operate in 100, and 10Mbit/sec modes.GBE MDIStandbyTwisted pair signals for external transformer.
GBE1_MD10-S18
GBE1_MD11+S20
GBE1_MD11-S21
GBE1_MD12+S2310010
GBE1_MD12-S24MDI[0]+/-TX+/-TX+/-
GBE1_MD13+S26MDI[1]+/-RX+/-RX+/-
GBE1_MD13-S27
GBE1_LINK100#S19Link Speed Indication LED for GBE 1 100MbpsO ODCMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_LINK1000#S22Link Speed Indication LED for GBE 1 1000MbpsO ODCMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_LINK_ACT#S31Link / Activity Indication LED Driven low on Link (10, 100 mbps) Blinks on ActivityO ODCMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_CTREFS28Center-Tap reference voltage for Carrier board Ethernet magnetic ‘(if required by the Module GBE PHY)’Analog0 to 3.3VmaxRuntime
GBE1_SDPP5IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IOCMOS3.3VRuntime
4.3.9 SDIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SDIO_D0P39SDIO Data lines. These signals operate in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_D1P40
SDIO_D2P41
SDIO_D3P42
SDIO_WPP33SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CMDP34SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_CD#P35SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CKP36SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.O CMOS1.8V or 3.3VRuntime
SDIO_PWR_ENP37SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.O CMOS3.3VRuntimeshould be driven low in STB Mode by the module
# 4.3.10 # 4.3.11 SPI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SPI0_CS0#P43SPI0 Master Chip Select 0O CMOS1.8VRuntimeThis signal can be used to select carrier SPI as boot device
SPI0_CS1#P31SPI0 Master Chip Select 1O CMOS1.8VRuntime
SPI0_CKP44SPI0 ClockO CMOS1.8VRuntime
SPI0_DINP45SPI0 Master input / Slave outputI CMOS1.8VRuntimealso referred to as MISO
SPI0_DOP46SPI0 Master output / Slave inputO CMOS1.8VRuntimealso referred to as MOSI
SPI1_CS0#P54SPI1 Master Chip Select 0O CMOS1.8VRuntime
SPI1_CS1#P55SPI1 Master Chip Select 1O CMOS1.8VRuntime
SPI1_CKP56SPI1 ClockO CMOS1.8VRuntime
SPI1_DINP57SPI1 Master input / Slave outputI CMOS1.8VRuntimealso referred to as MISO
SPI1_DOP58SPI1 Master output / Slave inputO CMOS1.8VRuntimealso referred to as MOSI
![The image displays a red-orange icon representing a document or file. It features a rectangular shape with a folded bottom-right corner. Inside the white space of the document, there are two horizontal lines centered vertically, resembling a simplified text block or an equals sign.](.lec-px30-0203-07/36f9202b484c0c8dd8cac1895485dec4d0b5110ea81e32e5c4d79eb54295030e.jpg) Note: SPI0 is free to use on the carrier but support only one device through CS0 SPI1 supports a CAN bus controller on the module through CS0, that leaves CS1 free for a device on the carrier 4.3.12 GPIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GPIO0 / CAM0_PWR#P108General purpose I/O pin 0.I/O CMOS1.8VRuntimePU 470K on the Module.Camera 0 is not supported
GPIO1 / CAM1_PWR#P109General purpose I/O pin 1.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS
GPIO2 / CAM0_RST#P110General purpose I/O pin 2.I/O CMOS1.8VRuntimePU 470K on the ModuleCamera 0 is not supported
GPIO3 / CAM1_RST#P111General purpose I/O pin 3.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS
GPIO4 / HDA_RST#P112General purpose I/O pin 4.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO5 / PWM_OUTP113General purpose I/O pin 5.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault is GPIO mode, alternate use is PWM output
GPIO6P114General purpose I/O pin 6.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO7P115General purpose I/O pin 7.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO8P116General purpose I/O pin 8.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO9P117General purpose I/O pin 9.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO10P118General purpose I/O pin 10.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO11P119General purpose I/O pin 11.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO12S142General purpose I/O pin 12I/O CMOS1.8VRuntimePU 470K on the Moduleadvised as INT signal to I2C GPIO expander on carrier.
GPIO13S123General purpose I/O pin 13I/O CMOS1.8VRuntimePU 470K on the Module
# 4.3.13 UART
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SER0_TXP129Asynchronous serial data output port 0O CMOS1.8VRuntime
SER0_RXP130Asynchronous serial data input port 0I CMOS1.8VRuntime
SER0_RTS#P131"Request to Send" handshake line for port 0O CMOS1.8VRuntime
SER0_CTS#P132"Clear to Send" handshake line for port 0I CMOS1.8VRuntime
SER1_TXP134Asynchronous serial data output port 1O CMOS1.8VRuntime
SER1_RXP135Asynchronous serial data input port 1I CMOS1.8VRuntime
SER2_TXP136Asynchronous serial data output port 2O CMOS1.8VRuntime
SER2_RXP137Asynchronous serial data input port 2I CMOS1.8VRuntime
SER2_RTS#P138"Request to Send" handshake line for port 2O CMOS1.8VRuntime
SER2_CTS#P139"Clear to Send" handshake line for port 2I CMOS1.8VRuntime
SER3_TXP140Asynchronous serial data output port 3O CMOS1.8VRuntime
SER3_RXP141Asynchronous serial data input port 3I CMOS1.8VRuntime
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SER0_TXP129Asynchronous serial data output port 0O CMOS1.8VRuntime
SER0_RXP130Asynchronous serial data input port 0I CMOS1.8VRuntime
SER0_RTS#P131"Request to Send" handshake line for port 0O CMOS1.8VRuntime
SER0_CTS#P132"Clear to Send" handshake line for port 0I CMOS1.8VRuntime
SER1_TXP134Asynchronous serial data output port 1O CMOS1.8VRuntime
SER1_RXP135Asynchronous serial data input port 1I CMOS1.8VRuntime
SER2_TXP136Asynchronous serial data output port 2O CMOS1.8VRuntime
SER2_RXP137Asynchronous serial data input port 2I CMOS1.8VRuntime
SER2_RTS#P138"Request to Send" handshake line for port 2O CMOS1.8VRuntime
SER2_CTS#P139"Clear to Send" handshake line for port 2I CMOS1.8VRuntime
SER3_TXP140Asynchronous serial data output port 3O CMOS1.8VRuntime
SER3_RXP141Asynchronous serial data input port 3I CMOS1.8VRuntime
4.3.14 CAN bus
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CAN0_TXP143CAN port 0 Transmit outputO CMOS1.8VRuntime
CAN0_RXP144CAN port 0 Receive inputI CMOS1.8VRuntime
CAN1_TXP145CAN port 1 Transmit outputO CMOS1.8VRuntime
CAN1_RXP146CAN port1 Receive inputI CMOS1.8VRuntime
4.3.15 Miscellaneous
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
TEST#S157Held low by Carrier to invoke Module vendor specific test function(s).ICMOS[1.8 to 5]Vsb / 5.25VRuntimePU on Module. Driven by OD on CarrierModule must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation
WDT_TIME_OUT#S145Watch-Dog-Timer Output, low active.OCMOS1.8VRuntimeDriven only during runtime
PWM_OUT / GPIO5P113Pulse Width Modulation (PWM) outputI/O CMOS1.8VRuntimePU 470K on the ModuleGPIO5 is the default pin configuration
4.3.16 Power and System Management
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BATLOW#S156Battery low indication to Module. Carrier to float the line in inactive state.I OD CMOSTBDRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
CARRIER_PWR_ONS154Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.O CMOSTBD-On x86 designs this pin should utilize the RSM_RST# signal.
CARRIER_STBY#S153The Module shall drive this signal low when the system is in a standby power state.O CMOSTBD-On x86 designs this pin should utilize the SUS_S3# signal.
CHARGER_PRSNT#S152Held low by Carrier if DC input for battery charger is present.I OD CMOSTBDStandbyPU 100KDriven by OD on Carrier. Pulled up on module.
CHARGING#S151Held low by Carrier during battery charging. Carrier to float the line when charge is complete.I OD CMOSTBDStandbyPU 68KDriven by OD on Carrier. Pulled up on module.
VIN_PWR_BAD#S150Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.I OD CMOSTBDStandbyPU 10KDriven by OD on Carrier Module must implement PU but actual value is depended on particular module design.
SLEEP#S149Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state.Active low, level sensitive. Should be de-bounced on the Module.I OD CMOSTBDStandbyPU 4.7KDriven by OD on Carrier. Pulled up on module.
LID#S148Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.I OD CMOSTBDStandbyPU 4.7KDriven by OD on Carrier. Pulled up on module.
POWER_BTN#P128Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.I OD CMOSTBDStandbyPU 10KDriven by OD on Carrier. Pulled up on module.
RESET_OUT#P126General purpose reset output to Carrier board.O CMOSTBDStandbyPU 10K
RESET_IN#P127Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.I OD CMOSTBDStandbyPU 10KDriven by OD on Carrier.Pulled up on module.
I2C_PM_DATP122Power management I2C bus DATAI/O OD CMOSTBDStandbyPU 2.2KOn x86 systems these serve as SMB DATA.Pulled up on module.
I2C_PM_CKP121Power management I2C bus CLKO OD CMOSTBDStandbyPU 2.2KOn x86 systems these serve as SMB CLK.Pulled up on module.
SMB_ALERT_1V8#P1SMBus Alert# (interrupt) signalI OD CMOSTBDStandbyPU 2.2Konly used on x86 design
4.3.17 Boot Select
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BOOT_SEL0#P123Input straps determine the Module bootI OD CMOS1.8VStandbyPU 4.7KDriven by OD on Carrier.Pulled up on module.Only booting from EMMC and SDcard is supported
BOOT_SEL1#P124
BOOT_SEL2#P125
FORCE_RECOV#S155I OD CMOS1.8VRuntimePU 10K-Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.
4.3.18 Power
NamePin #DescriptionI/O TypePower Rail / TolerancePU / PDComments
VDD_INP147, P148, P149, P150, P151, P152, P153, P154, P155, P156Module power input voltage 4.75 min to 5.25V maxP Not defined within Signal Terminology Descriptions. Should we define a specific rail?4.75V to 5.25V / 5V
GNDP2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158Module signal and power return, and GND referenceP Not defined within Signal Terminology Descriptions. Should we define a specific rail?Ground
VDD_RTCS147Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.P Not defined within Signal Terminology Descriptions. Should we define a specific rail?[2 to 3.25] / 3.25V
4.4 SMARC pin to controller mapping
PinSMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P1SMB_ALERT_1V8#-------
P2GND-------
P3CSI1_CK+In-CSIPX30MIPI_CSI_CLKP-VCC_1V0
P4CSI1_CK-In-CSIPX30MIPI_CSI_CLKN-VCC_1V0
P5GBE1_SDP------
P6GBE0_SDP------
P7CSI1_RX0+In-CSIPX30MIPI_CSI_DP0-VCC_1V0
P8CSI1_RX0-In-CSIPX30MIPI_CSI_DNO-VCC_1V0
P9GND------
P10CSI1_RX1+In-CSIPX30MIPI_CSI_DP1-VCC_1V0
P11CSI1_RX1-In-CSIPX30MIPI_CSI_DN1-VCC_1V0
P12GND------
P13CSI1_RX2+In-CSIPX30MIPI_CSI_DP2-VCC_1V0
P14CSI1_RX2-In-CSIPX30MIPI_CSI_DN2-VCC_1V0
P15GND-------
P16CSI1_RX3+In-CSIPX30MIPI_CSI_DP3-VCC_1V0
P17CSI1_RX3-In-CSIPX30MIPI_CSI_DN3-VCC_1V0
P18GND-------
P19GBE0_MDI3--------
P20GBE0_MDI3+-------
P21GBE0_LINK100#Out/OD--DP83822LED_1-VCC3V3_SYS
P22GBE0_LINK1000#-------
P23GBE0_MDI2--------
P24GBE0_MDI2+-------
P25GBE0_LINK_ACT#Out/OD--DP83822LED_0-VCC3V3_SYS
P26GBE0_MDI1-Bi-Dir--DP83822RD_M-3.3VA1
P27GBE0_MDI1+Bi-Dir--DP83822RD_P-3.3VA1
P28GBE0_CTREF-------
P29GBE0_MD10-Bi-Dir--DP83822TD_M-3.3VA1
P30GBE0_MD10+Bi-Dir--DP83822TD_P-3.3VA1
P31SPI0_CS1#-------
P32GND-------
P33SDIO_WPIn-CMOS/VDD_IOPX30GPIO0_A5_dALT6/ALT6VCC3V0_PMU
P34SDIO_CMDBi-Dir-CMOS/VDD_IOPX30SDMMC0_CMDALT0/ALT0VCCIO_SD_1V8
P35SDIO_CD#In-CMOS/VDD_IOPX30SDMMC0_DETNALT6/ALT6VCC3V0_PMU
P36SDIO_CKOut-CMOS/VDD_IOPX30SDMMC0_CLKOALT0/ALT0VCCIO_SD_1V8
P37SDIO_PWR_ENOut-CMOS/VDD_IOPX30GPIO0_A2_dALT6/ALT6VCC3V0_PMU
P38GND-------
P39SDIO_D0Bi-Dir-CMOS/VDD_IOPX30SDMMC0_D0ALT0/ALT0VCCIO_SD_1V8
P40SDIO_D1Bi-Dir-CMOS/VDD_IOPX30SDMMC0_D1ALT0/ALT0VCCIO_SD_1V8
P41SDIO_D2Bi-Dir-CMOS/VDD_IOPX30SDMMC0_D2ALT0/ALT0VCCIO_SD_1V8
P42SDIO_D3Bi-Dir-CMOS/VDD_IOPX30SDMMC0_D3ALT0/ALT0VCCIO_SD_1V8
P43SPI0_CS0#Out-CMOS/VDD_IOPX30SPI0_CSNALT2/ALT2VCCIO_FLASH
P44SPI0_CKOut-CMOS/VDD_IOPX30SPI0_CLKALT2/ALT2VCCIO_FLASH
P45SPI0_DINIn-CMOS/VDD_IOPX30SPI0_RXDALT2/ALT2VCCIO_FLASH
P46SPI0_DOOut-CMOS/VDD_IOPX30SPI0_TXDALT2/ALT2VCCIO_FLASH
P47GND-------
P48SATA_TX+-------
P49SATA_TX--------
P50GND-------
P51SATA_RX+-------
P52SATA_RX--------
P53GND-------
P54ESPI_CS0# / SPI1_CS0#Out-CMOS/VDD_IOPX30SPI1_CSN0ALT2/ALT2VCC1V8_DVP
P55ESPI_CS1# / SPI1_CS1#Out-CMOS/VDD_IOPX30SPI1_CSN1ALT2/ALT2VCC1V8_DVP
P56ESPI_CK / SPI1_CKOut-CMOS/VDD_IOPX30SPI1_CLKALT2/ALT2VCC1V8_DVP
P57ESPI_IO_1 / SPI1_DINIn-CMOS/VDD_IOPX30SPI1_MISOALT2/ALT2VCC1V8_DVP
P58ESPI_IO_0 / SPI1_DOOut-CMOS/VDD_IOPX30SIP1_MOSIALT2/ALT2VCC1V8_DVP
P59GND-------
P60USB0+Bi-Dir-USBPX30OTG_DP-USB_AVDD
P61USB0-Bi-Dir-USBPX30OTG_DM-USB_AVDD
P62USB0_EN_OC#InPU-10KCMOS/ VDD_IOPX30GPIO0_A1_d-VCC3V0_PMU
P63USB0_VBUS_DETPWR-CMOS/ VDD_IOPX30USB_DET-VCC3V0_PMU
P64USB0_OTG_IDIn-CMOS/ VDD_IOPX30USB_ID-VCC3V0_PMU
P65USB1+Bi-Dir-USBLAN9514USBDP2--
P66USB1-Bi-Dir-USBLAN9514USBDM2--
P67USB1_EN_OC#InPU-10KCMOS/ VDD_IOLAN9514PRTCTL2-+3.3V
P68GND-------
P69USB2+Bi-Dir-USBLAN9514USBDP3--
P70USB2-Bi-Dir-USBLAN9514USBDM3--
P71USB2_EN_OC#Bi-DirPU-10KCMOS/ VDD_IOLAN9514PRTCTL3-+3.3V
P72RSVD-------
P73RSVD-------
P74USB3_EN_OC#InPU-10KCMOS/ VDD_IOLAN9514PRTCTL4-+3.3V
P75PCIE_A_RST#-------
P76USB4_EN_OC#InPU-10KCMOS/ VDD_IOLAN9514PRTCTL5-+3.3V
P77PCIE_B_CREQ#-------
P78PCIE_A_CREQ#-------
P79GND-------
P80PCIE_C_REFCK+-------
P81PCIE_C_REFCK--------
P82GND-------
P83PCIE_A_REFCK+-------
P84PCIE_A_REFCK--------
P85GND-------
P86PCIE_A_RX+-------
P87PCIE_A_RX--------
P88GND-------
P89PCIE_A_TX+-------
P90PCIE_A_TX--------
P91GND-------
P92HDMI_D2+ / DP1_LANE0+-------
P93HDMI_D2- / DP1_LANE0--------
P94GND-------
P95HDMI_D1+ / DP1_LANE1+-------
P96HDMI_D1- / DP1_LANE1--------
P97GND-------
P98HDMI_D0+ / DP1_LANE2+-------
P99HDMI_D0- / DP1_LANE2--------
P100GND-------
P101HDMI_CK+ / DP1_LANE3+-------
P102HDMI_CK- / DP1_LANE3--------
P103GND-------
P104HDMI_HPD / DP1_HPD-------
P105HDMI_CTRL_CK / DP1_AUX+-------
P106HDMI_CTRL_DAT / DP1_AUX--------
P107DP1_AUX_SEL-------
P108GPIO0 / CAM0_PWR#Bi-DirSerial-0RCMOS/ VDD_IOPX30GPIO3_C0_dALT5/ALT5VCC1V8_DVP
P109GPIO1 / CAM1_PWR#Bi-DirSerial-0RCMOS/ VDD_IOPX30GPIO3_C1_dALT5/ALT5VCC1V8_DVP
P110GPIO2 / CAM0_RST#Bi-DirSerial-0RCMOS/ VDD_IOPX30GPIO3_C2_dALT5/ALT5VCC1V8_DVP
P111GPIO3 / CAM1_RST#Bi-DirSerial-0RCMOS/ VDD_IOPX30GPIO3_C3_dALT5/ALT5VCC1V8_DVP
P112GPIO4 / HDA_RST#Bi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_C4_d-VCC1V8_DVP
P113GPIO5 / PWM_OUTBi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_C5_d-VCC1V8_DVP
P114GPIO6 / TACHINBi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_C6_d-VCC1V8_DVP
P115GPIO7Bi-Dir-CMOS/ VDD_IOPX30GPIO3_B2_dALT5/ALT5VCC1V8_DVP
P116GPIO8Bi-DirPU-470KCMOS/ VDD_IOPX30GPIO_B0_d-VCC1V8_DVP
P117GPIO9Bi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_B5_d-VCC1V8_DVP
P118GPIO10Bi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_D1_d-VCC1V8_DVP
P119GPIO11Bi-DirPU-470KCMOS/ VDD_IOPX30GPIO3_D12_d-VCC1V8_DVP
P120GND-------
P121I2C_PM_CKOutPU-2k2CMOS/ VDD_IOPX30I2C0_SCLALT6/ALT6VCC_1V8
P122I2C_PM_DATBi-DirPU-2k2CMOS/ VDD_IOPX30I2C0_SDAALT6/ALT6VCC_1V8
P123BOOT_SEL0#InPU-4k7CMOS/ VDD_IOBMCPB3-+1V8SMC
P124BOOT_SEL1#InPU-4k7CMOS/ VDD_IOBMCPB5-+1V8SMC
P125BOOT_SEL2#InPU-4k7CMOS/ VDD_IOBMCPA2-+1V8SMC
P126RESET_OUT#InPU-10KCMOS/ VDD_IOBMCP140-+1V8SMC
P127RESET_IN#InPU-10KCMOS/ VDD_IOBMCP140-+1V8SMC
P128POWER_BTN#InPU-10KCMOS/ VDD_IOBMCP31-+1V8SMC
P129SER0_TXOut-CMOS/ VDD_IOPX30UART2_TX_M1ALT1/ALT1VCC_RMII
P130SER0_RXIn-CMOS/ VDD_IOPX30UART2_RX_M1ALT1/ALT1VCC_RMII
P131SER0_RTS#-------
P132SER0_CTS#-------
P133GND-------
P134SER1_TX-------
P135SER1_RX-------
P136SER2_TXOut-CMOS/ VDD_IOPX30UART1_TXALT4/ALT4VCC_1V8
P137SER2_RXIn-CMOS/ VDD_IOPX30UART1_RXALT4/ALT4VCC_1V8
P138SER2_RTS#Out-CMOS/ VDD_IOPX30UART1_RTSALT4/ALT4VCC_1V8
P139SER2_CTS#In-CMOS/ VDD_IOPX30UART1_CTSALT4/ALT4VCC_1V8
P140SER3_TX-------
P141SER3_RX-------
P142GND-------
P143CAN0_TXOut-CMOS/ VDD_IOMCP2517FDTXCAN_3V3ALT2/ALT2VCC1V8_DVP
P144CAN0_RXIn-CMOS/ VDD_IOMCP2517FDRXCAN_3V3ALT2/ALT2VCC1V8_DVP
P145CAN1_TX-------
P146CAN1_RX-------
P147VDD_IN-------
P148VDD_IN-------
P149VDD_IN-------
P150VDD_IN-------
P151VDD_IN-------
P152VDD_IN-------
P153VDD_IN-------
P154VDD_IN-------
P155VDD_IN-------
P156VDD_IN-------
S1CSI1_TX+ / I2C_CAM1_CKOut-CMOS/ VDD_IOPX30I2C2_SCL-VCC_RMII
S2CSI1_TX- / I2C_CAM1_DATBi-Dir-CMOS/ VDD_IOPX30I2C2_SDA-VCC_RMII
S3GND-------
S4RSVD-------
S5CSI0_TX- / I2C_CAM0_CK-------
S6CAM_MCKOut-CMOS/ VDD_IOPX30GPIO2_B3_dALT0/ALT0VCC_RMII
S7CSI0_TX+ / I2C_CAM0_DAT-------
S8CSI0_CK+-------
S9CSI0_CK--------
S10GND-------
S11CSI0_RX0+-------
S12CSI0_RX0--------
S13GND-------
S14CSI0_RX1+-------
S15CSI0_RX1--------
S16GND-------
S17GBE1_MDI0+Bi-Dir--LAN9514TXP--
S18GBE1_MDI0-Bi-Dir--LAN9514TXN--
S19GBE1_LINK100#Out/OD--LAN9514nSPD_LED-VCC3V3_SYS
S20GBE1_MDI1+Bi-Dir--LAN9514RXP--
S21GBE1_MDI1-Bi-Dir--LAN9514RXN--
S22GBE1_LINK1000#-------
S23GBE1_MDI2+-------
S24GBE1_MDI2--------
S25GND-------
S26GBE1_MDI3+-------
S27GBE1_MDI3--------
S28GBE1_CTREF-------
S29PCIE_D_TX+ / SERDES_1_TX+-------
S30PCIE_D_TX- / SERDES_1_TX--------
S31GBE1_LINK_ACT#Out/OD--LAN9514nLNKA_LEDALT1/ALT1VCC3V3_SYS
S32PCIE_D_RX+ / SERDES_1_RX+-------
S33PCIE_D_RX- / SERDES_1_RX--------
S34GND-------
S35USB4+Out-USBLAN9514USBDP5--
S36USB4-Bi-Dir-USBLAN9514USBDM5--
S37USB3_VBUS_DET-------
S38AUDIO_MCKOut-CMOS/ VDD_IOPX30I2S1_2CH_MCLKALT0/ALT0VCC_1V8
S39I2S0_LRCKBi-Dir-CMOS/ VDD_IOPX30I2S1_2CH_LRCK_TXRX-VCC_1V8
S40I2S0_SDOUTOut-CMOS/ VDD_IOPX30I2S1_2CH_SDO-VCC_1V8
S41I2S0_SDINIn-CMOS/ VDD_IOPX30I2S1_2CH_SDI-VCC_1V8
S42I2S0_CKBi-Dir-CMOS/ VDD_IOPX30I2S1_2CH_SCKL-VCC_1V8
S43ESPI_ALERT0#-------
S44ESPI_ALERT1#-------
S45MDIO_CLK-------
S46MDIO_DAT-------
S47GND-------
S48I2C_GP_CKOutPU-2.2K-PX30I2C1_SCLALT6/ALT6VCC_1V8
S49I2C_GP_DATBi-DirPU-2.2K-PX30I2C1_SDAALT6/ALT6VCC_1V8
S50HDA_SYNC / I2S2_LRCKBi-Dir--PX30I2S0_2CH_LRCK_TXRX-VCC1V8_DVP
S51HDA_SDO / I2S2_SDOUTOut--PX30I2S0_2CH_SDO-VCC1V8_DVP
S52HDA_SDI / I2S2_SDINIn--PX30I2S0_2CH_SDI-VCC1V8_DVP
S53HDA_CK / I2S2_CKBi-Dir--PX30I2S0_2CH_SCKL-VCC1V8_DVP
S54SATA_ACT#-------
S55USB5_EN_OC#-------
S56ESPI_IO_2-------
S57ESPI_IO_3-------
S58ESPI_RESET#-------
S59USB5+-------
S60USB5--------
S61GND-------
S62USB3_SSTX+-------
S63USB3_SSTX--------
S64GND-------
S65USB3_SSRX+-------
S66USB3_SSRX--------
S67GND-------
S68USB3+Bi-Dir-USBLAN9514USBDP4--
S69USB3-Bi-Dir-USBLAN9514USBDM4--
S70GND-------
S71USB2_SSTX+-------
S72USB2_SSTX--------
S73GND-------
S74USB2_SSRX+-------
S75USB2_SSRX--------
S76PCIE_B_RST#-------
S77PCIE_C_RST#-------
S78PCIE_C_RX+ / SERDES_2_RX+-------
S79PCIE_C_RX- / SERDES_2_RX--------
S80GND-------
S81PCIE_C_TX+ / SERDES_2_TX+-------
S82PCIE_C_TX- / SERDES_2_TX--------
S83GND-------
S84PCIE_B_REFCK+-------
S85PCIE_B_REFCK--------
S86GND-------
S87PCIE_B_RX+-------
S88PCIE_B_RX--------
S89GND-------
S90PCIE_B_TX+-------
S91PCIE_B_TX--------
S92GND-------
S93DP0_LANE0+-------
S94DP0_LANE0--------
S95DP0_AUX_SEL-------
S96DP0_LANE1+-------
S97DP0_LANE1--------
S98DP0_HPD-------
S99DP0_LANE2+-------
S100DP0_LANE2--------
S101GND-------
S102DP0_LANE3+-------
S103DP0_LANE3--------
S104USB3_OTG_ID-------
S105DP0_AUX+-------
S106DP0_AUX--------
S107LCD1_BKLT_EN-------
S108LVDS1_CK+/ eDP1_AUX+/DSI1_CLK+-------
S109LVDS1_CK-/ eDP1_AUX-/DSI1_CLK--------
S110GND-------
S111LVDS1_0+/ eDP1_TX0+/DSI1_D0+-------
S112LVDS1_0-/ eDP1_TX0-/DSI1_D0--------
S113eDP1_HPD / DSI1_TE-------
S114LVDS1_1+/ eDP1_TX1+/DSI1_D1+-------
S115LVDS1_1-/ eDP1_TX1-/DSI1_D1--------
S116LCD1_VDD_EN-------
S117LVDS1_2+/ eDP1_TX2+/DSI1_D2+-------
S118LVDS1_2-/ eDP1_TX2-/DSI1_D2--------
S119GND-------
S120LVDS1_3+/ eDP1_TX3+/DSI1_D3+-------
S121LVDS1_3-/ eDP1_TX3-/DSI1_D3--------
S122LCD1_BKLT_PWM-------
S123GPIO13Bi-DirSerial-33RCMOS/ VDD_IOPX30GPIO3_A0_dALT1/ALT1VCC1V8_DVP
S124GND-------
S125LVDS0_0+ / eDP0_TX0+ / DSIO_D0+Out-LVDSPX30LVDS_TX0P-MIPI_DSI
S126LVDS0_0- / eDP0_TX0- / DSIO_D0-Out-LVDSPX30LVDS_TX1N-MIPI_DSI
S127LCD0_BKLT_ENOutSerial-0RCMOS/ VDD_IOPX30GPIO0_B7_dALT5/ALT5VCC_1V8
S128LVDS0_1+ / eDP0_TX1+ / DSIO_D1+Out-LVDSPX30LVDS_TX1P-MIPI_DSI
S129LVDS0_1- / eDP0_TX1- / DSIO_D1-Out-LVDSPX30LVDS_TX1N-MIPI_DSI
S130GND-------
S131LVDS0_2+ / eDP0_TX2+ / DSIO_D2+Out-LVDSPX30LVDS_TX2P-MIPI_DSI
S132LVDS0_2- / eDP0_TX2- / DSIO_D2-Out-LVDSPX30LVDS_TX2N-MIPI_DSI
S133LCD0_VDD_ENOut-CMOS/ VDD_IOPX30GPIO3_A4_dALT5/ALT5VCC1V8_DVP
S134LVDS0_CK+ / eDP0_AUX+ / DSIO_CLK+Out-LVDSPX30LVDS_CLKP-MIPI_DSI
S135LVDS0_CK- / eDP0_AUX- / DSIO_CLK-Out-LVDSPX30LVDS_CLKN-MIPI_DSI
S136GND-------
S137LVDS0_3+ / eDP0_TX3+ / DSIO_D3+Out-LVDSPX30LVDS_TX3P-MIPI_DSI
S138LVDS0_3- / eDP0_TX3- / DSIO_D3-Out-LVDSPX30LVDS_TX3N-MIPI_DSI
S139I2C_LCD_CKOutPU-2.2KCMOS/ VDD_IOPX30I2C2_SCLALT6/ALT6VCC_RMII
S140I2C_LCD_DATBi-DirPU-2.2KCMOS/ VDD_IOPX30I2C2_SDAALT6/ALT6VCC_RMII
S141LCD0_BKLT_PWMOutSerial-33RCMOS/ VDD_IOPX30GPIO0_C0_dALT4/ALT4VCC_1V8
S142GPIO12Bi-Dir--PX30GPIO3_C7_d-VCC1V8_DVP
S143GND-------
S144eDP0_HPD / DSIO_TE-------
S145WDT_TIME_OUT#Out-CMOS/ VDD_IOBMCP10-+1V8SMC
S146PCIE_WAKE#-------
S147VDD_RTC---RTC---
S148LID#InPU-4.7KCMOS/ VDD_IOBMCPB0ALT5/ALT5+1V8SMC
S149SLEEP#InPU-4.7KCMOS/ VDD_IOPX30GPIO1_C4_uALT5/ALT5VCC_1V8
S150VIN_PWR_BAD#InPU-10KCMOS/ VDD_IOBMCP33-+1V8SMC
S151CHARGING#OutPU-68KCMOS/ VDD_IOPX30GPIO1_C5_dALT5/ALT5VCC_1V8
S152CHARGER_PRSNT#OutPU-100KCMOS/ VDD_IOPX30GPIO1_C6_uALT5/ALT5VCC_1V8
S153CARRIER_STBY#Out-CMOS/ VDD_IOBMCP53-+1V8SMC
# 5. Software Support # 5.1.1 Early Access 5.1.2 Yocto 5.1.3 Ubuntu # 6. Mechanical and Thermal # 6.1 Module dimensions # 6.2 Thermal Solutions # 6.2.1 Heatspreader : HTS ![6\n3\n90°](.lec-px30-0203-07/cfb7667b8fbe2a8d3721a567ad2c51a1e51c074d4cfe1593bda6ff866eb2b326.jpg) ![74\n4\n34\n24\n9\n14\n68](.lec-px30-0203-07/d31d97cf59291bbbb8b399763c0c040b945c90c6c4ab60de80ed6fd4eda1fe92.jpg) ![M3 x 4pcs](.lec-px30-0203-07/df195cd389d4a7638b11748ff66501a17fb4fdce917be39fae071bb29ea7d623.jpg) ![Ø2.7mm x 4pcs\n82\n42](.lec-px30-0203-07/1ac00744e955c382f74d4d9fa342927980bde32657cc7eddda897d72b361a156.jpg) Figure 3 – Heatspreader HTS-sPX30 # 6.2.2 Heatsink : THS ![12\n3](.lec-px30-0203-07/6a3f32546090f6c83b803a3d4d1988b73c0431da7669308af716a160f90e0fa1.jpg) ![34\n4\n4\n74](.lec-px30-0203-07/05fdf8c111d2cce517609514f8d953aba20b1f04e54fb3c87e87f3ef53797c45.jpg) ![Technical line drawing of an integrated circuit chip with pins and a central square component (no text or symbols)](.lec-px30-0203-07/9f1f7d85043ff6706a01ebff1fe76037e0f93434f11912e403ba5d80479a3462.jpg) ![Ø2.7mm x 4pcs\n82\n42](.lec-px30-0203-07/7f506c5655f50b5d57cc50f9f64c88d11f30eba3cd6382de0f1e4c4b5bd1344b.jpg) Figure 4 – Heatsink THS-sPX30 [🔗 Link to the original document](.lec-px30-0203-07/lec-px30-0203-07.pdf)