| Jack # | Name | Description |
| BT1 | Battery Socket | Battery socket for 3.2 volt Lithium battery |
| DIMM1 | Memory | 184-pin, 1.27mm, slot for a single DDR RAM DIMM |
| J1A,B,C,D | PC/104 bus | 104-pins for PC/104 connector |
| J2A,B,C,D | PC/104-Plus | 120-pin, 2mm, connector for PCI bus |
| J3 | Video (CRT) | 10-pin connector for output to a CRT type monitor |
| J6 | Primary IDE | 40-pin connector for the primary IDE interface |
| J7 | Secondary IDE | 40-pin connector for the secondary IDE interface |
| J8 | CompactFlash | 50-pin, 1.27mm, socket accepts Type 1 or Type II CompactFlash cards |
| J9 | Audio In/Out | 26-pin, 2mm, connector for all of the Audio signals (input/output) |
| J10 | Ethernet 2 | 8-pin RJ45 connector for 10/100/1000BaseT Ethernet port |
| J11 | Serial A | 20-pin connector for serial ports 1 and 2 (COM 1 & COM 2) |
| J12 | Serial B | 20-pin connector for serial ports 3 and 4 (COM 3 & COM 4) |
| J13 | Utility 2 | 24-pin connector for mouse, IrDA, SMBus, USB 0 & 1, power button |
| J14 | Utility 3 | 10-pin connector for USB2 and USB3 ports (bi-direction) |
| J15 | Utility 1 | 16-pin connector for keyboard, external battery, reset switch, speaker |
| J16 | Parallel | 26-pin connector for parallel port |
| J17 | Floppy | 34-pin connector for floppy disk drive interface |
| J19 | Power In | 7-pin, 0.156" (3.96mm), connector for input power |
| J21 | Optional Fan | 3-pin header provides +5V, tach, and ground to optional CPU fan |
| J23 | Ethernet 1 | 8-pin RJ45 connector for 10/100BaseT Ethernet port |
| J26 | Video (LVDS) | 30-pin, 2mm, connector for LVDS type video displays |
# NOTE
Ampro uses a connector/header identification method in Chapter 3 to avoid difficult to see visible numbering next to the connectors. For example, a 20-pin header with two rows of pins, using odd/even numbering, where pin-2 is directly across and adjacent to pin-1, is noted in this way; 20-pin, two rows, odd/even (1, 2). Alternately, a 20-pin connector using consecutive numbering, where pin-11 is directly across and adjacent to pin-1, is noted in this way; 20-pin, two rows, consecutive (1, 11). The second number in the parenthesis is always directly across from and adjacent to pin-1, with a few exceptions (DIMM1 slot, PC/104-Plus, PC/104). See Figure 2-5.
Figure 2-5. Connector Pin-Out Identification
Figure 2-6. Connector Locations (Top view)
# CAUTION
The two Ethernet ports share a common ground (transformer center tap), that is floating until you determine how the common ground is connected. The grounding holes (8) of the LittleBoard 800 are connected to ground potential (return) of the DC power supply connected to the board through J19.
# NOTE
Pin-1 is shown as a black pin (square or round) in all connectors and jumpers in all illustrations.
# LED Definitions
Tables 2-3 and 2-4 provide the LED colors and definitions for the Ethernet ports, Port 1 (J23) and Port 2 (J10) located on the LittleBoard 800. Refer to Figure 2-6.
Table 2-3. Ethernet Port 1 (J23) LED Indicators
| Pin # | Signal | Input/Output | Description |
| 1 (A1) | Key/GND | | Key – Ground |
| 2 (A2) | VI/O | | +5 volts ±5% (Reference voltage only) |
| 3 (A3) | AD05 | T/S | PCI Address/Data Bus Line 5 – These signals (AD31 - AD0) are multiplexed on these pins. A bus transaction consists of an address followed by one or more data cycles. |
| 4 (A4) | C/BE0* | T/S | PCI Bus Command/Byte Enable 0 – These signals (C/BE 0 -3) are line multiplexed, so that during the address cycle, the command is defined and during the data cycle, the byte enable is defined. |
| 5 (A5) | GND | | Ground |
| 6 (A6) | AD11 | T/S | Address/Data Bus Line 11 – Refer to pin-A3 for more information. |
| 7 (A7) | AD14 | T/S | Address/Data Bus Line 14 – Refer to pin-A3 for more information. |
| 8 (A8) | +3.3V | | +3.3 volts ±5% power supply input |
| 9 (A9) | SERR* | O/D | System Error – This signal is for reporting address parity errors. |
| 10 (A10) | GND | | Ground |
| 11 (A11) | STOP* | S/T/S | Stop – This signal indicates the current selected device is requesting the master to stop the current transaction |
| 12 (A12) | +3.3V | | +3.3 volts ±5% power supply input |
| 13 (A13) | FRAME* | S/T/S | Frame access – This signal is driven by the current master, indicating a transaction start and will remain active until the final data cycle. |
| 14 (A14) | GND | | Ground |
| 15 (A15) | AD18 | T/S | Address/Data Bus Line 18 – Refer to pin-A3 for more information. |
| 16 (A16) | AD21 | T/S | Address/Data Bus Line 21 – Refer to pin-A3 for more information. |
| 17 (A17) | +3.3V | | +3.3 volts ±5% power supply input |
| 18 (A18) | IDSEL0 | In | Initialization Device Select 0 – These signals (IDSEL 0-3) are used as the chip-selects during configuration read and write transactions. |
| 19 (A19) | AD24 | T/S | Address/Data Bus Line 24 – Refer to pin A3 for more information. |
| 20 (A20) | GND | | Ground |
| 21 (A21) | AD29 | T/S | Address/Data Bus Line 29 – Refer to pin A3 for more information. |
| 22 (A22) | +5V | | +5 volts ±5% power supply input |
| 23 (A23) | REQ0* | T/S | Bus Request 0 – These signals (REQ 0-2) indicate to the arbitrator the device desires use of the bus. |
| 24 (A24) | GND | | Ground |
| 25 (A25) | GNT1* | T/S | Grant 1 – These signal (GNT 0-2) lines indicate access has been granted to the requesting device (PCI Masters). |
| 26 (A26) | +5V | | +5 volts ±5% power supply input |
| 27 (A27) | CLK2 | In | Clock 2 – These clocks (CLK 0-3) provide timing outputs for four external PCI devices and all timing transactions on the PCI bus. |
| 28 (A28) | GND | | Ground |
| 29 (A29) | +12V | | +12 volts ±5% power supply input |
| 30 (A30) | -12V | | -12 volts (Supplied externally or through PC/104-Plus bus) |
| 31 (B1) | NC | | Not connected (Reset) |
| 32 (B2) | AD02 | T/S | Address/Data Bus Line 2 – Refer to pin A3 for more information. |
| 33 (B3) | GND | | Ground |
| 34 (B4) | AD07 | T/S | Address/Data Bus Line 7 – Refer to pin A3 for more information. |
| 35 (B5) | AD09 | T/S | Address/Data Bus Line 9 – Refer to pin A3 for more information. |
| 36 (B6) | VI/O | | +5 volts ±5% (Reference voltage only) |
| 37 (B7) | AD13 | T/S | Address/Data Bus Line 13 – Refer to pin-A3 for more information. |
| 38 (B8) | C/BE1* | T/S | Command/Byte Enable 1 – Refer to pin-A4 for more information. |
| 39 (B9) | GND | | Ground |
| 40 (B10) | PERR* | | Parity Error – This signal is for reporting data parity errors. |
| 41 (B11) | +3.3V | | +3.3 volts ±5% power supply input |
| 42 (B12) | TRDY* | S/T/S | Target Ready – This signal indicates the selected device's ability to complete the current cycle of transaction. Both IRDY* and TRDY* must be asserted to terminate a data cycle. |
| 43 (B13) | GND | | Ground |
| 44 (B14) | AD16 | T/S | Address/Data Bus Line 16 – Refer to pin-A3 for more information. |
| 45 (B15) | +3.3V | | +3.3 volts ±5% power supply input |
| 46 (B16) | AD20 | T/S | Address/Data Bus Line 20 – Refer to pin-A3 for more information. |
| 47 (B17) | AD23 | T/S | Address/Data Bus Line 23 – Refer to pin-A3 for more information. |
| 48 (B18) | GND | | Ground |
| 49 (B19) | C/BE3* | T/S | Command/Byte Enable 3 – Refer to pin-A4 for more information. |
| 50 (B20) | AD26 | T/S | Address/Data Bus Line 26 – Refer to pin-A3 for more information. |
| 51 (B21) | +5V | | +5 volts ±5% power supply input |
| 52 (B22) | AD30 | T/S | Address/Data Bus Line 30 – Refer to pin-A3 for more information. |
| 53 (B23) | GND | | Ground |
| 54 (B24) | REQ2* | T/S | Bus Request 2 – Refer to pin-A23 for more information. |
| 55 (B25) | VI/O | | +5 volts ±5% (Reference voltage only) |
| 56 (B26) | CLK0 | In | Clock 0 – Refer to pin-A27 for more information |
| 57 (B27) | +5V | | +5 volts ±5% power supply input |
| 58 (B28) | INTD* | O/D | Interrupt D – This signal is used to request interrupts only for multi-function devices. |
| 59 (B29) | INTA* | O/D | Interrupt A – This signal is used to request an interrupt. |
| 60 (B30) | REQ3* | T/S | Bus Request 3 – Refer to pin-A23 for more information. |
| 61 (C1) | +5V | | +5 volts ±5% power supply input |
| 62 (C2) | AD01 | T/S | Address/Data Bus Line 1 – Refer to pin-A3 for more information. |
| 63 (C3) | AD04 | T/S | Address/Data Bus Lines 4 – Refer to pin-A3 for more information. |
| 64 (C4) | GND | | Ground |
| 65 (C5) | AD08 | T/S | Address/Data Bus Line 8 – Refer to pin-A3 for more information. |
| 66 (C6) | AD10 | T/S | Address/Data Bus Line 10 – Refer to pin-A3 for more information. |
| 67 (C7) | GND | | Ground |
| 68 (C8) | AD15 | T/S | Address/Data Bus Line 15 – Refer to pin-A3 for more information. |
| 69 (C9) | NC | | Not connected (Snoop Backoff) |
| 70 (C10) | +3.3V | | +3.3 volts ±5% power supply input |
| 71 (C11) | LOCK* | S/T/S | Lock – This signal indicates an operation that may require multiple transactions to complete |
| 72 (C12) | GND | | Ground |
| 73 (C13) | IRDY* | S/T/S | Initiator Ready – This signal indicates the master’s ability to complete the current data cycle of the transaction |
| 74 (C14) | +3.3V | | +3.3 volts ±5% power supply input |
| 75 (C15) | AD17 | T/S | Address/Data Bus Line 17 – Refer to pin-A3 for more information. |
| 76 (C16) | GND | | Ground |
| 77 (C17) | AD22 | T/S | Address/Data Bus Line 22 – Refer to pin-A3 for more information. |
| 78 (C18) | IDSEL1 | | Initialization Device Select 1 – Refer to pin-A18 for more information |
| 79 (C19) | VI/O | | +5 volts ±5% (Reference voltage only) |
| 80 (C20) | AD25 | T/S | Address/Data Bus Line 25 – Refer to pin-A3 for more information. |
| 81 (C21) | AD28 | T/S | Address/Data Bus Line 28 – Refer to pin-A3 for more information. |
| 82 (C22) | GND | | Ground |
| 83 (C23) | REQ1* | T/S | Bus Request 1 – Refer to pin-A23 for more information. |
| 84 (C24) | +5V | | +5 volts ±5% power supply input |
| 85 (C25) | GNT2* | T/S | Grant 2 – Refer to pin-A25 for more information |
| 86 (C26) | GND | | Ground |
| 87 (C27) | CLK3 | In | Clock 3 – Refer to pin-A27 for more information |
| 88 (C28) | +5V | | +5 volts ±5% power supply input |
| 89 (C29) | INTB* | O/D | Interrupt B – This signal is used to request interrupts only for multi-function devices. |
| 90 (C30) | GNT3* | T/S | Grant 3 – Refer to pin-A25 for more information |
| 91 (D1) | AD00 | T/S | Address/Data Bus Line 0 – Refer to pin-A3 for more information. |
| 92 (D2) | +5V | | +5 volts ±5% power supply input |
| 93 (D3) | AD03 | T/S | Address/Data Bus Line 3 – Refer to pin-A3 for more information. |
| 94 (D4) | AD06 | T/S | Address/Data Bus Line 6 – Refer to pin-A3 for more information. |
| 95 (D5) | GND | | Ground |
| 96 (D6) | M66EN | | Not supported – Reserved for 66MHz on PCI bus. |
| 97 (D7) | AD12 | T/S | Address/Data Bus Line 12 – Refer to pin-A3 for more information. |
| 98 (D8) | +3.3V | | +3.3 volts ±5% power supply input |
| 99 (D9) | PAR | T/S | Bus Parity bit – This signal is the even parity bit on AD[31:0] and C/BE[3:0]* |
| 100 (D10) | NC | | Not connected (Snoop Done) |
| 101 (D11) | GND | | Ground |
| 102 (D12) | DEVSEL* | S/T/S | Device Select – This signal is driven by the target device when its address is decoded. |
| 103 (D13) | +3.3V | | +3.3 volts ±5% power supply input |
| 104 (D14) | C/BE2* | | Command/Byte Enable 2 – Refer to pin-A4 for more information. |
| 105 (D15) | GND | | Ground |
| 106 (D16) | AD19 | T/S | Address/Data Bus Line 19 – Refer to pin-A3 for more information. |
| 107 (D17) | +3.3V | | +3.3 volts ±5% power supply input |
| 108 (D18) | IDSEL2 | | Initialization Device Select 2 – Refer to pin-A18 for more info. |
| 109 (D19) | IDSEL3 | | Initialization Device Select 3 – Refer to pin-A18 for more info. |
| 110 (D20) | GND | | Ground |
| 111 (D21) | AD27 | T/S | Address/Data Bus Line 27 – Refer to pin-A3 for more information. |
| 112 (D22) | AD31 | T/S | Address/Data Bus Line 31 – Refer to pin-A3 for more information. |
| 113 (D23) | VI/O | | +5 volts ±5% (Reference voltage only) |
| 114 (D24) | GNT0* | T/S | Grant 0 – Refer to pin-A25 for more information. |
| 115 (D25) | GND | | Ground |
| 116 (D26) | CLK1 | In | Clock 1 – Refer to pin-A27 for more information. |
| 117 (D27) | GND | | Ground |
| 118 (D28) | RST* | In | PCI bus reset – This signal is an output signal to reset the entire PCI Bus. This signal will be asserted during system reset. |
| 119 (D29) | INTC* | O/D | Interrupt C – This signal is used to request interrupts only for multi-function devices. |
| 120 (D30) | GND | | Ground |
The Input/Output signals in this table refer to the input/output signals listed in the PCI Local Bus Manual, Revision 2.2, Chapter 2, paragraph 2.1, Signal definitions. The following terms or acronyms are used in this table:
• In – Input is standard input only signal
• Out – Totem Pole output is a standard active driver
• T/S – Tri-State is a bi-directional input output pin
• S/T/S – Sustained Tri-State is an active low tri-state signal driven by one and only one agent at a time
• O/D – Open Drain allows multiple devices to share as a wire-OR.
# PC/104 Interface (J1A,B,C,D)
The PC/104 Bus uses a 104-pin 100 mil header interface. This interface header will carry all of the appropriate PC/104 signals operating at clock speeds up to 8MHz. This interface header accepts stackable modules and is located on the top of the board. The PC/104 connector uses 104-pin, 4 rows, consecutive numbering, (A1, B1, C0, D0), and 0.100" pin spacing.
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-5. PC/104 Interface Pin/Signal Descriptions (J1A)
| Pin # | Signal | Description (J1 Row A) |
| 1 (A1) | IOCHCHK* | I/O Channel Check – This signal may be activated by ISA boards to request that a non-maskable interrupt (NMI) be generated to the system processor. It is driven active to indicate an uncorrectable error has been detected. |
| 2 (A2) | SD7 | System Data 7 – This signal (0 to 19) provides a system data bit. |
| 3 (A3) | SD6 | System Data 6 – Refer to pin-A2 for more information. |
| 4 (A4) | SD5 | System Data 5 – Refer to pin-A2 for more information. |
| 5 (A5) | SD4 | System Data 4 – Refer to pin-A2 for more information. |
| 6 (A6) | SD3 | System Data 3 – Refer to pin-A2 for more information. |
| 7 (A7) | SD2 | System Data 2 – Refer to pin-A2 for more information. |
| 8 (A8) | SD1 | System Data 1 – Refer to pin-A2 for more information. |
| 9 (A9) | SD0 | System Data 0 – Refer to pin-A2 for more information. |
| 10 (A10) | IOCHRDY | I/O Channel Ready – This signal allows slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signal’s normal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read, or write command. The signal is released high when the device is ready to complete the cycle. |
| 11 (A11) | AEN | Address Enable – This signal is used to degate the system processor and other devices from the bus during DMA transfers. When this signal is active, the system DMA controller has control of the address, data, and read/write signals. This signal should be included as part of ISA board select decodes to prevent incorrect board selects during DMA cycles. |
| 12 (A12) | SA19 | System Address 19 – This signal (0 to 19) provides a system address bit. |
| 13 (A13) | SA18 | System Address 18 – Refer to pin-A12 , for more information. |
| 14 (A14) | SA17 | System Address 17 – Refer to pin-A12 , for more information. |
| 15 (A15) | SA16 | System Address 16 – Refer to pin-A12 , for more information. |
| 16 (A16) | SA15 | System Address 15 – Refer to pin-A12 , for more information. |
| 17 (A17) | SA14 | System Address 14 – Refer to pin-A12 , for more information. |
| 18 (A18) | SA13 | System Address 13 – Refer to pin-A12 , for more information. |
| 19 (A19) | SA12 | System Address 12 – Refer to pin-A12 , for more information. |
| 20 (A20) | SA11 | System Address 11 – Refer to pin-A12 , for more information. |
| 21 (A21) | SA10 | System Address 10 – Refer to pin-A12 , for more information. |
| 22 (A22) | SA9 | System Address 9 – Refer to pin-A12 , for more information. |
| 23 (A23) | SA8 | System Address 8 – Refer to pin-A12 , for more information. |
| 24 (A24) | SA7 | System Address 7 – Refer to pin-A12 , for more information. |
| 25 (A25) | SA6 | System Address 6 – Refer to pin-A12 , for more information. |
| 26 (A26) | SA5 | System Address 5 – Refer to pin-A12 , for more information. |
| 27 (A27) | SA4 | System Address 4 – Refer to pin-A12 , for more information. |
| 28 (A28) | SA3 | System Address 3 – Refer to pin-A12 , for more information. |
| 29 (A29) | SA2 | System Address 2 – Refer to pin-A12 , for more information. |
| 30 (A30) | SA1 | System Address 1 – Refer to pin-A12 , for more information. |
| 31 (A31) | SA0 | System Address 0 – Refer to pin-A12 , for more information. |
| 32 (A32) | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-6. PC/104 Interface Pin/Signal Descriptions (J1B)
| Pin # | Signal | Descriptions (J1 Row B) |
| 33 (B1) | GND | Ground |
| 34 (B2) | RSTDRV | Reset Drive – This signal is used to reset or initialize system logic on power up or subsequent system reset. |
| 35 (B3) | +5V | +5 volts ±5% power supply input |
| 36 (B4) | IRQ9 | Interrupt Request 9 – Asserted by a device when it has a pending interrupt request. Only one device may use this request line at a time. |
| 37 (B5) | -5V | -5V volt power (Supplied externally or through PC/104 bus) |
| 38 (B6) | DRQ2 | DMA Request 2 – Used by I/O resources to request DMA service, or to request ownership of the bus as a bus master device. Must be held high until associated DACK2 line is active. |
| 39 (B7) | -12V | -12 volt power (Supplied externally or through PC/104 bus) |
| 40 (B8) | ZWS | Zero Wait State – This signal is driven low by a bus slave device to indicate it is capable of performing a bus cycle without inserting any additional wait states. To perform a 16-bit memory cycle without wait states, this signal is derived from an address decode. |
| 41 (B9) | +12V | +12 volt power supply input (Supplied externally or through PC/104 bus) |
| 42 (B10) | NC | Not connected |
| 43 (B11) | SMEMW* | System Memory Write – This signal is used by bus owner to request a memory device to store data currently on the data bus and only active for the lower 1MB. Used for legacy compatibility with 8-bit cards. |
| 44 (B12) | SMEMR* | System Memory Read – This signal is used by bus owner to request a memory device to drive data onto the data bus and only active for lower 1MB. Used for legacy compatibility with 8-bit cards. |
| 45 (B13) | IOW* | I/O Write – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to capture the write data on the data bus. |
| 46 (B14) | IOR* | I/O Read – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to drive read data onto the data bus. |
| 47 (B15) | DACK3* | DMA Acknowledge 3 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 48 (B16) | DRQ3 | DMA Request 3 – Used by I/O resources to request DMA service. Must be held high until associated DACK3 line is active. |
| 49 (B17) | DACK1* | DMA Acknowledge 1 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 50 (B18) | DRQ1 | DMA Request 1 – Used by I/O resources to request DMA service. Must be held high until associated DACK1 line is active. |
| 51 (B19) | REFRESH* | Memory Refresh – This signal is driven low to indicate a memory refresh cycle is in progress. Memory is refreshed every 15.6 usec. |
| 52 (B20) | SYSCLK | System Clock – This is a free running clock typically in the 8MHz to 10MHz range, although its exact frequency is not guaranteed. |
| 53 (B21) | IRQ7 | Interrupt Request 7 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 54 (B22) | IRQ6 | Interrupt Request 6 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 55 (B23) | IRQ5 | Interrupt Request 5 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 56 (B24) | IRQ4 | Interrupt Request 4 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 57 (B25) | IRQ3 | Interrupt Request 3 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 58 (B26) | DACK2* | DMA Acknowledge 2 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 59 (B27) | TC | Terminal Count – This signal is a pulse to indicate a terminal count has been reached on a DMA channel operation. |
| 60 (B28) | BALE | Buffered Address Latch Enable – This signal is used to latch the LA23 to LA17 signals or decodes of these signals. Addresses are latched on the falling edge of BALE. It is forced high during DMA cycles. When used with AENx, it indicates a valid processor or DMA address. |
| 61 (B29) | +5V | +5 volts ±5% power supply input |
| 62 (B30) | OSC | Oscillator – This clock signal operates at 14.3MHz. This signal is not synchronous with the system clock (SYSCLK). |
| 63 (B31) | GND | Ground |
| 64 (B32) | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-7. PC/104 Interface Pin/Signal Descriptions (J1C)
| Pin # | Signal | Descriptions (J1 Row C) |
| 1 (C0) | GND | Ground |
| 2 (C1) | SBHE* | System Byte High Enable – This signal is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8). |
| 3 (C2) | LA23 | Latchable Address 23 – This signal must be latched by the resource if the line is required for the entire data cycle. |
| 4 (C3) | LA22 | Latchable Address 22 – Refer to pin-C2, for more information. |
| 5 (C4) | LA21 | Latchable Address 21 – Refer to pin-C2, for more information. |
| 6 (C5) | LA20 | Latchable Address 20 – Refer to pin-C2, for more information. |
| 7 (C6) | LA19 | Latchable Address 19 – Refer to pin-C2, for more information. |
| 8 (C7) | LA18 | Latchable Address 18 – Refer to pin-C2, for more information. |
| 9 (C8) | LA17 | Latchable Address 17 – Refer to pin-C2, for more information. |
| 10 (C9) | MEMR* | Memory Read – This signal instructs a selected memory device to drive data onto the data bus. It is active on all memory read cycles. |
| 11 (C10) | MEMW* | Memory Write – This signal instructs a selected memory device to store data currently on the data bus. It is active on all memory write cycles. |
| 12 (C11) | SD8 | System Data 8 – Refer to pin-A2 for more information. |
| 13 (C12) | SD9 | System Data 9 – Refer to pin-A2 for more information. |
| 14 (C13) | SD10 | System Data 10 – Refer to pin-A2 for more information. |
| 15 (C14) | SD11 | System Data 11 – Refer to pin-A2 for more information. |
| 16 (C15) | SD12 | System Data 12 – Refer to pin-A2 for more information. |
| 17 (C16) | SD13 | System Data 13 – Refer to pin-A2 for more information. |
| 18 (C17) | SD14 | System Data 14 – Refer to pin-A2 for more information. |
| 19 (C18) | SD15 | System Data 15 – Refer to pin-A2 for more information. |
| 20 (C19) | NC | Not connected |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-8. PC/104 Interface Pin/Signal Descriptions (J1D)
| Pin # | Signal | Descriptions (J1 Row D) |
| 21 (D0) | GND | Ground |
| 22 (D1) | MEMCS16* | Memory Chip Select 16 – This is signal is driven low by a memory slave device to indicates it is cable of performing a 16-bit memory data transfer. This signal is driven from a decode of the LA23 to LA17 address lines. |
| 23 (D2) | IOCS16* | I/O Chip Select 16 – This signal is driven low by an I/O slave device to indicate it is capable of performing a 16-bit I/O data transfer. This signal is driven from a decode of the SA15 to SA0 address lines. |
| 24 (D3) | IRQ10 | Interrupt Request 10 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 25 (D4) | IRQ11 | Interrupt Request 11 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 26 (D5) | IRQ12 | Interrupt Request 12 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 27 (D6) | IRQ15 | Interrupt Request 15 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 28 (D7) | IRQ14 | Interrupt Request 14 – Asserted by a device when it has pending interrupt request. Only one device may use this request line at a time. |
| 29 (D8) | DACK0* | DMA Acknowledge 0 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 30 (D9) | DRQ0 | DMA Request 0 – Used by I/O resources to request DMA service. Must be held high until associated DACK0 line is active. |
| 31 (D10) | DACK5* | DMA Acknowledge 5 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 32 (D11) | DRQ5 | DMA Request 5 – Used by I/O resources to request DMA service. Must be held high until associated DACK5 line is active. |
| 33 (D12) | DACK6* | DMA Acknowledge 6 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 34 (D13) | DRQ6 | DMA Request 6 – Used by I/O resources to request DMA service. Must be held high until associated DACK6 line is active. |
| 35 (D14) | DACK7* | DMA Acknowledge 7 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 36 (D15) | DRQ7 | DMA Request 7 – Used by I/O resources to request DMA service. Must be held high until associated DACK7 line is active. |
| 37 (D16) | +5V | +5 volts ±5% power supply |
| 38 (D17) | MASTER* | Bus Master Assert – This signal is used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a device can pull -MASTER low which will allow it to control the system address, data, and control lines. After -MASTER is low, the device should wait one CLK period before driving the address and data lines, and two clock periods before issuing a read or write command. |
| 39 (D18) | GND | Ground |
| 40 (D19) | GND | Ground |
# IDE Interface (J6, J7)
The LittleBoard 800 provides two IDE connectors for primary and secondary IDE signals.
The EIDE interface logic supports the following features:
• Bus master IDE transfer rate up to 100Mbps when 80-pin grounded shielded cable is used
• Increase reliability using Ultra DMA 33/66/100 transfer protocols
• Full scatter-gather capability
• Supports ATAPI and DVD compliant devices
• PIO IDE transfers as fast as 14Mbps.
• Single Bus Master EIDE
• Supports two IDE drives per interface (primary or secondary)
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Tables 3-9 and 3-10 lists the signals for the two IDE 40 pin connectors, with 2 rows, odd/even, (1, 2), 0.100” pin spacing.
Table 3-9. Primary IDE Interface Pin/Signal Descriptions (J6)
| Pin # | Signal | Description |
| 1 | RESET* | Low active hardware reset (RSTDRV inverted) |
| 2 | GND | Ground |
| 3 | PD7 | Primary Disk Data 7 – These signals (0 to 15) provide the disk data signals. |
| 4 | PD8 | Primary Disk Data 8 – These signals (0 to 15) provide the disk data signals. |
| 5 | PD6 | Primary Disk Data 6 – These signals (0 to 15) provide the disk data signals. |
| 6 | PD9 | Primary Disk Data 9 – These signals (0 to 15) provide the disk data signals. |
| 7 | PD5 | Primary Disk Data 5 – These signals (0 to 15) provide the disk data signals. |
| 8 | PD10 | Primary Disk Data 10 – These signals (0 to 15) provide the disk data signals. |
| 9 | PD4 | Primary Disk Data 4 – These signals (0 to 15) provide the disk data signals. |
| 10 | PD11 | Primary Disk Data 11 – These signals (0 to 15) provide the disk data signals. |
| 11 | PD3 | Primary Disk Data 3 – These signals (0 to 15) provide the disk data signals. |
| 12 | PD12 | Primary Disk Data 12 – These signals (0 to 15) provide the disk data signals. |
| 13 | PD2 | Primary Disk Data 2 – These signals (0 to 15) provide the disk data signals. |
| 14 | PD13 | Primary Disk Data 13 – These signals (0 to 15) provide the disk data signals. |
| 15 | PD1 | Primary Disk Data 1 – These signals (0 to 15) provide the disk data signals. |
| 16 | PD14 | Primary Disk Data 14 – These signals (0 to 15) provide the disk data signals. |
| 17 | PD0 | Primary Disk Data 0 – These signals (0 to 15) provide the disk data signals. |
| 18 | PD15 | Primary Disk Data 15 – These signals (0 to 15) provide the disk data signals. |
| 19 | GND | Ground |
| 20 | NC/Key | Not Connected - Key pin plug |
| 21 | PDDREQ | Primary Device DMA Channel Request – Used for DMA transfers between host and drive (direction of transfer controlled by DIOR* and DIOW*). Also used in an asynchronous mode with DMACK*. Drive asserts IDRQ0 when ready to transfer or receive data. |
| 22 | GND | Ground |
| 23 | PDIOW* | Primary I/O Read/Write Strobe – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 24 | GND | Ground |
| 25 | PDIOR* | Primary I/O Read/Write Strobe – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 26 | GND | Ground |
| 27 | PDIORDY | Primary I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 28 | NC | Not connected |
| 29 | PDACK* | Primary Cable Select – Used to configure IDE drives as device 0 or device 1 using a special cable |
| 30 | GND | Ground |
| 31 | IRQ14 | Interrupt Request 14 – Asserted by drive when it has pending interrupt (PIO transfer of data to or from the drive to the host). |
| 32 | NC | Not connected |
| 33 | PDA1 | Primary ATA Disk Address – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 34 | PDIAG | UDMA 33/66 Sense – Senses which DMA mode to use for IDE devices. |
| 35 | PDA0 | Primary ATA Disk Address – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 36 | PDA2 | Primary ATA Disk Address – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 37 | PDCS1 | Primary Slave/Master Chip Select 1 – Used to select the host-accessible Command Block Register. |
| 38 | PDCS3 | Primary Slave/Master Chip Select 3 – Used to select the host-accessible Command Block Register. |
| 39 | NC | Not connected |
| 40 | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-10. Secondary IDE Interface Pin/Signal Descriptions (J7)
| Pin # | Signal | Description |
| 1 | RESET* | Low active hardware reset (RSTDRV inverted) |
| 2 | GND | Ground |
| 3 | SDD7 | Secondary Disk Data 7 – These signals (0 to 15) provide the disk data signals. |
| 4 | SDD8 | Secondary Disk Data 8 – These signals (0 to 15) provide the disk data signals. |
| 5 | SDD6 | Secondary Disk Data 6 – These signals (0 to 15) provide the disk data signals. |
| 6 | SDD9 | Secondary Disk Data 9 – These signals (0 to 15) provide the disk data signals. |
| 7 | SDD5 | Secondary Disk Data 5 – These signals (0 to 15) provide the disk data signals. |
| 8 | SDD10 | Secondary Disk Data 10 – These signals (0 to 15) provide the disk data signals. |
| 9 | SDD4 | Secondary Disk Data 4 – These signals (0 to 15) provide the disk data signals. |
| 10 | SDD11 | Secondary Disk Data 11 – These signals (0 to 15) provide the disk data signals. |
| 11 | SDD3 | Secondary Disk Data 3 – These signals (0 to 15) provide the disk data signals. |
| 12 | SD12 | Secondary Disk Data 12 – These signals (0 to 15) provide the disk data signals. |
| 13 | SDD2 | Secondary Disk Data 2 – These signals (0 to 15) provide the disk data signals. |
| 14 | SDD13 | Secondary Disk Data 13 – These signals (0 to 15) provide the disk data signals. |
| 15 | SDD1 | Secondary Disk Data 1 – These signals (0 to 15) provide the disk data signals. |
| 16 | SDD14 | Secondary Disk Data 14 – These signals (0 to 15) provide the disk data signals. |
| 17 | SDD0 | Secondary Disk Data 0 – These signals (0 to 15) provide the disk data signals. |
| 18 | SDD15 | Secondary Disk Data 15 – These signals (0 to 15) provide the disk data signals. |
| 19 | GND | Ground |
| 20 | NC/Key | Not Connected - Key pin plug |
| 21 | SDDREQ | Secondary DMA Channel Request – Used for DMA transfers between host and drive (direction of transfer controlled by DIOR* and DIOW*). Also used in an asynchronous mode with DMACK*. Drive asserts IDRQ0 when ready to transfer or receive data. |
| 22 | GND | Ground |
| 23 | SDIOW* | Secondary I/O Read/Write Strobe – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 24 | GND | Ground |
| 25 | SDIOR* | Secondary I/O Read/Write Strobe – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 26 | GND | Ground |
| 27 | SIORDY | Secondary I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 28 | CSEL | Not connected |
| 29 | SDACK* | Secondary Cable Select – Used to configure IDE drives as device 0 or device 1 using a special cable |
| 30 | GND | Ground |
| 31 | IRQ15 | Interrupt Request 15 – Asserted by drive when it has pending interrupt (PIO transfer of data to or from the drive to the host). |
| 32 | NC | Not connected |
| 33 | SDA1 | Secondary IDE ATA Disk Address 1 – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 34 | SPDIAG | UDMA 33/66 Sense – Senses which DMA mode to use for IDE devices. |
| 35 | SDA0 | Secondary IDE ATA Disk Address 0 – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 36 | SDA2 | Secondary IDE ATA Disk Address 2 – Used (0 to 2) to indicate which byte in the ATA command block or control block is being accessed |
| 37 | SDCS1 | Secondary Slave/Master Chip Select 1 – Used to select the host-accessible Command Block Register. |
| 38 | SDCS3 | Secondary Slave/Master Chip Select 3 – Used to select the host-accessible Command Block Register. |
| 39 | NC | Not connected |
| 40 | GND | Ground |
# CompactFlash Socket (J8)
The board contains a Type II PC card socket, which allows for the insertion of a CompactFlash (CF) Card. The CompactFlash Card acts as a standard IDE Drive and is connected to the secondary IDE bus. If a CompactFlash card is installed, only one additional IDE drive may be added to the secondary bus. Jumpers are used to select the Master/Slave mode and the voltage selection (+5V or +3.3V). Refer to Table 2-5, Jumper Settings for more information. The CompactFlash socket has 50 pins, 2 rows, consecutive (1, 26), with 1.27mm pin spacing.
# CAUTION
To prevent system hangs when using older CompactFlash cards, ensure your CompactFlash is compatible with UDMA 100 IDE hard disk drives. Consult your CompactFlash card vendor for UDMA 100 compatibility.
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-11. CompactFlash Interface Pin/Signal Descriptions (J8)
| Pin # | Signal | Description |
| 1 | GND | Ground |
| 2 | SD3 | Secondary Disk Data 3 – These signals (D0-D15) carry the Data, Commands, and Status between the host and the controller. D0 is the LSB of the even Byte of the Word. D8 is the LSB of the Odd Byte of the Word. All Task File operations occur in byte mode on the low order bus D0-D7, while all data transfers are 16 bit using D0-D15 to provide the disk data signals. |
| 3 | SD4 | Secondary Disk Data 4 – Refer to SD3 on pin-2 for more information. |
| 4 | SD5 | Secondary Disk Data 5 – Refer to SD3 on pin-2 for more information. |
| 5 | SD6 | Secondary Disk Data 6 – Refer to SD3 on pin-2 for more information. |
| 6 | SD7 | Secondary Disk Data 7 – Refer to SD3 on pin-2 for more information. |
| 7 | SDCS1* | Secondary Chip Select 1 – This signal, along with CE2*, selects the CF and indicates to the CF when a byte or word operation is being performed. This signal accesses the even byte or odd byte of the word depending on A0 and CE2*. |
| 8, 9, 10, 11, 12 | GND | Ground |
| 13 | VCC | Voltage Jumper (JP3) – Selects voltage; pins 1-2 = +5V or pins 2-3 = +3.3V. |
| 14, 15, 16, 17 | GND | Ground |
| 18 | SA2 | Secondary Address Select 2 – One of three signals (0 – 2) used to select one of eight registers in the Task File. The host grounds all remaining address lines. |
| 19 | SA1 | Secondary Address Select 1 – Refer to SA2 on pin-18 for more information. |
| 20 | SA0 | Secondary Address Select 0 – Refer to SA2 on pin-18 for more information. |
| 21 | SD0 | Secondary Disk Data 0 – Refer to SD3 on pin-2 for more information. |
| 22 | SD1 | Secondary Disk Data 1 – Refer to SD3 on pin-2 for more information. |
| 23 | SD2 | Secondary Disk Data 2 – Refer to SD3 on pin-2 for more information. |
| 24 | NU | Not used (IOIS16*, connected through 10k ohm resistor to VCC) |
| 25 | NU | Not used (CD2*, connected through 10k ohm resistor to VCC) |
| 26 | NU | Not used (CD1*, connected through 10k ohm resistor to VCC) |
| 27 | SD11 | Secondary Disk Data 11 – Refer to SD3 on pin-2 for more information. |
| 28 | SD12 | Secondary Disk Data 12 – Refer to SD3 on pin-2 for more information. |
| 29 | SD13 | Secondary Disk Data 13 – Refer to SD3 on pin-2 for more information. |
| 30 | SD14 | Secondary Disk Data 14 – Refer to SD3 on pin-2 for more information. |
| 31 | SD15 | Secondary Disk Data 15 – Refer to SD3 on pin-2 for more information. |
| 32 | SDCS3* | Secondary Slave/Master Chip Select – This signal, along with CE1*, selects the CompactFlash card and indicates to the card when a byte or word operation is being performed. This signal always accesses the odd byte of the word. |
| 33 | NU | Not used (VS1*, connected through 10k ohm resistor to VCC) |
| 34 | SIOR* | Secondary I/O Read/Write Strobe – This signal is generated by the host and gates the I/O data onto the bus from the CompactFlash card when the card is configured to use the I/O interface. |
| 35 | SIOW* | Secondary I/O Read/Write Strobe – This signal is generated by the host and clocks the I/O data on the Card Data bus into the CompactFlash card controller registers when the card is configured to use the I/O interface. The clock occurs on the negative to positive edge of the signal (trailing edge). |
| 36 | NU | Not used (WE*, connected through 10k ohm resistor to VCC) |
| 37 | IRQ15 | Interrupt Request 15 – IRQ 15 is asserted by drive (CF) when it has a pending interrupt (PIO transfer of data to or from the drive to the host). |
| 38 | VCC | Voltage Jumper (JP3) – Selects voltage; pins 1-2 = +5V or pins 2-3 = +3.3V. |
| 39 | Mas/Slv* | Master/Slave – This pin determines the Master or Slave configuration of the CompactFlash by jumper (JP2) setting. When this pin is grounded (jumper inserted pins 2-3), CF is configured as Master. When this pin is open (jumper inserted pins 1-2), CF is configured as Slave (Default). |
| 40 | NU | Not used (VS2*, connected through 10k ohm resistor to VCC) |
| 41 | CFRST* | CF Reset – This input signal is the active low hardware reset from the host. If this pin goes high, it is used as the reset signal. This pin is driven high at power-up, causing a reset, and if left high will cause another reset. |
| 42 | SIORDY | Secondary I/O DMA Channel Ready – When negated, extends the host transfer cycle of any host register access when the CF is not ready to respond to a data transfer request. High impedance if asserted. |
| 43 | NC | Not Connected (InpAck) |
| 44 | NU | Not used (REG*, connected through 10k ohm resistor to VCC) |
| 45 | NU | Not used (ACT/SLV, connected through 10k ohm resistor to VCC) |
| 46 | SPDIAG | Secondary Pass Diagnostic – This input / output signal is used in the Master/Slave handshake protocol. |
| 47 | SD8 | Secondary Disk Data 8 – Refer to SD3 on pin-2 for more information. |
| 48 | SD9 | Secondary Disk Data 9 – Refer to SD3 on pin-2 for more information. |
| 49 | SD10 | Secondary Disk Data 10 – Refer to SD3 on pin-2 for more information. |
| 50 | GND | Ground |
# Floppy Drive Interface (J17)
The LPC47B272 chip provides the floppy controller and supports one floppy drive as configured. The floppy signals are provided through the standard 34-pin connector (J17). This connector is separate (not shared with) from the parallel port connector (J16). The floppy controller will support a 360k, 720k, 1.2M, 1.44M, or 2.88M drive.
The floppy drive connector has 34 pins, 2 rows, odd/even, (1, 2) with 0.100” pin spacing.
Table 3-12. Floppy Drive Interface Pin/Signal Descriptions (J17)
| Pin # | Signal | Description |
| 2 | DRVEN0 | Drive (Floppy) Density Select 0 |
| 4 | NC | Not connected |
| 6 | DRVEN0 | Drive (Floppy) Density Select 0 |
| 8 | INDEX | Index – Sense to detect that the head is positioned over the beginning of a track |
| 10 | MTR0 | Motor Control 0 – Select motor on drive 0. |
| 12 | NC | Not Connected (DS1) |
| 14 | DS0 | Drive Select 0 – Select drive 0. |
| 16 | NC | Not Connected (MTR1) |
| 18 | DIR | Direction – Direction of head movement (0 = inward motion, 1 = outward motion). |
| 20 | STEP | Step – Low pulse for each track-to-track movement of the head. |
| 22 | WDATA | Write Data – Encoded data to the drive for write operations. |
| 24 | WGATE | Write Gate – Signal to the drive to enable current flow in the write head. |
| 26 | TRK0 | Track 0 – Sense detects the head is positioned over track 0. |
| 28 | WRTPRT | Write Protect – Senses the diskette is write protected. |
| 29 | NC | Not Connected (NC1) |
| 30 | RDATA | Read Data – Raw serial bit stream from the drive for read operations. |
| 32 | HDSEL | Head Select – Selects the side for Read/Write operations (0 = side 1, 1 = side 0) |
| 33 | NC | Not Connected (NC2) |
| 34 | DSKCHG | Disk Change – Senses the drive door is open or the diskette has been changed since the last drive selection. |
| 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 31 | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
# Parallel Port Interface (J16)
Parallel port supports standard parallel, Bi-directional, ECP and EPP protocols. The LPC47B272 provides separate parallel port interface signals not shared with the floppy drive signals.
The parallel connector has 26 pins, 2 rows, odd/even, (1, 2), with $0 . 1 0 0 ^ { \circ }$ pin spacing.
Table 3-13. Parallel Interface Pin/Signal Descriptions (J16)
| Pin # | Pin # DB9 | Signal | Description |
| 1 | 1 (COM1) | DCD1* | Data Carrier Detect 1 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR1 as part of the DTR/DSR handshake. |
| 2 | 6 | DSR1* | Data Set Ready 1 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR1 for overall readiness to communicate. |
| 3 | 2 | RXD1 RX1- | Receive Data 1 – Serial port 1 receive data in.RX1- – If in RS485 or RS422 mode, this pin is Receive Data 1 -. |
| 4 | 7 | RTS1* TX1+ | Request To Send 1 – Indicates Serial port 1 is ready to transmit data. Used as hardware handshake with CTS1 for low level flow control.TX1+ – If in RS485 or RS422 mode, this pin is Transmit Data 1 +. |
| 5 | 3 | TXD1 TX1- | Transmit Data 1 – Serial port 1 transmit data out.TX1- – If in RS485 or RS422 mode, this pin is Transmit Data 1 -. |
| 6 | 8 | CTS1* RX1+ | Clear to Send 1 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS1 for low level flow control.RX1+ – If in RS485 or RS422 mode, this pin is Receive Data 1 -. |
| 7 | 4 | DTR1* | Data Terminal Ready 1 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR1 for overall readiness to communicate. |
| 8 | 9 | RI1* | Ring Indicator 1 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. |
| 9 | 5 | GND | Ground |
| 10 | NC | KEY/ NC | KeyNot connected |
| 11 | 1 (COM2) | DCD2* | Data Carrier Detect 2 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR2 as part of the DTR/DSR handshake. |
| 12 | 6 | DSR2* | Data Set Ready 2 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR2 for overall readiness to communicate. |
| 13 | 2 | RXD2 RX2- | Receive Data 2 – Serial port 2 receive data inRX1- – If in RS485 or RS422 mode, this pin is Receive Data 1 -. |
| 14 | 7 | RTS2* TX2+ | Request To Send 2 – Indicates Serial port 2 is ready to transmit data. Used as hardware handshake with CTS2 for low level flow control.TX2+ – If in RS485 or RS422 mode, this pin is Transmit Data 2 +. |
| 15 | 3 | TXD2 TX2- | Transmit Data 2 – Serial port 2 transmit data outTX2- – If in RS485 or RS422 mode, this pin is Transmit Data 2 -. |
| 16 | 8 | CTS2* | Clear To Send 2 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS2 for low level flow control. |
| RX2+ | RX2+ – If in RS485 or RS422 mode, this pin is Receive Data 2 -. |
| 17 | 4 | DTR2* | Data Terminal Ready 2 – Indicates Serial port 1 is powered, initialized, and ready. Used as hardware handshake with DSR2 for overall readiness to communicate. |
| 18 | 9 | NC | Not Connected (Ring Indicator 2) |
| 19 | 5 | GND | Ground |
| 20 | NC | NC | Not connected |
Notes: The shaded area denotes power or ground. Signals are listed in the table with RS232 first, followed by RS485/RS422.
Notes: The shaded area denotes power or ground. Signals are listed in the table with RS232 first, followed by RS485/RS422.
Table 3-15. Serial B Interface Pin/Signal Descriptions (J12)
| Pin # | Pin # DB9 | Signal | Description |
| 1 | 1 (COM3) | DCD3* | Data Carrier Detect 3 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR3 as part of the DTR/DSR handshake. |
| 2 | 6 | DSR3* | Data Set Ready 3 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR3 for overall readiness to communicate. |
| 3 | 2 | RXD3 RX3- | Receive Data 3 – Serial port 3 receive data in RX3- – If in RS485 or RS422 mode, this pin is Receive Data 3 -. |
| 4 | 7 | RTS3* TX3+ | Request To Send 3 – Indicates Serial port 3 is ready to transmit data. Used as hardware handshake with CTS3 for low level flow control. TX3+ – If in RS485 or RS422 mode, this pin is Transmit Data 3 +. |
| 5 | 3 | TXD3 TX3- | Transmit Data 3 – Serial port 3 transmit data out TX3- – If in RS485 or RS422 mode, this pin is Transmit Data 3 -. |
| 6 | 8 | CTS3* RX3+ | Clear To Send 3 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS3 for low level flow control. RX3+ – If in RS485 or RS422 mode, this pin is Receive Data 3 -. |
| 7 | 4 | DTR3* | Data Terminal Ready 3 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR3 for overall readiness to communicate. |
| 8 | 9 | RI3* | Ring Indicator 3 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. |
| 9 | 5 | GND | Ground |
| 10 | NC | KEY | Not Connected |
| 11 | 1 (COM4) | DCD4* | Data Carrier Detect 4 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR4 as part of the DTR/DSR handshake. |
| 12 | 6 | DSR4* | Data Set Ready 4 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR4 for overall readiness to communicate. |
| 13 | 2 | RXD4 RX4- | Receive Data 4 – Serial port 4 receive data in RX4- – If in RS485 or RS422 mode, this pin is Receive Data 4 -. |
| 14 | 7 | RTS4* TX4+ | Request To Send 4 – Indicator to serial output port 4 is ready to transmit data. Used as hardware handshake with CTS4 for low level flow control. TX4+ – If in RS485 or RS422 mode, this pin is Transmit Data 4 +. |
| 15 | 3 | TXD4 TX4- | Transmit Data 4 – Serial port 4 transmit data out TX4- – If in RS485 or RS422 mode, this pin is Transmit Data 4 -. |
| 16 | 8 | CTS4* RX4+ | Clear To Send 4 – Indicator to serial port 4 that external serial communications device is ready to receive data. Used as hardware handshake with RTS4 for low level flow control. RX4+ – If in RS485 or RS422 mode, this pin is Receive Data 4 +. |
| 17 | 4 | DTR4* | Data Terminal Ready 4 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR4 for overall readiness to communicate. |
| 18 | 9 | NC | Not connected (Ring Indicator 4) |
| 19 | 5 | GND | Ground |
| 20 | NC | NC | Not connected |
# Utility Interfaces
The Utility interfaces consists of three connectors that provide the standard interface signals for the following devices:
• Utility 1 (J15)
♦ Keyboard
♦ External battery connection
♦ Reset Switch
♦ Speaker
• Utility 2 (J13)
♦ PS/2 Mouse
♦ Infrared (IrDA) signals
♦ SMBus signals
♦ USB signals for USB ports 1 and 2
♦ Power button signal
• Utility 3 (J14)
USB signals for USB ports 3 (USB0) and 4 (and USB1)
# Utility 1 Interface (J15)
The Utility 1 (J15) interface uses an 18-pin connector and provides the various interface signals to an external I/O board with external connections for the respective connectors, such as, keyboard, speaker, etc. Table 3-17 gives the pin-outs and interface signals for Utility 1 interface and has 16 pins, 2 rows, odd/even, (1, 2) with 0.100” pin spacing.
• Keyboard
Battery
• Reset Switch
• Speaker
• External voltages (-5V In, -12V In, +3.3V Out to Power On LED)
# Keyboard Interface
The signal lines for a PS/2 keyboard are provided through the Utility 1 interface (J15), which is also fully PC/AT compatible.
# External Battery
An external battery input connection is provided through a Utility 1 interface (J15) for the Real Time Clock’s operation in the event the on-board battery is not used.
# Reset Switch
The signal lines for a reset switch (hard or soft) are provided through the Utility 1 interface (J15).
NOTE
To perform the equivalent of a power-on reset, the reset button must be pressed and held for a minimum of three seconds.
# Speaker
The signal lines for a speaker port with 0.1-watt drive are provided through a Utility 1 interface (J15).
Table 3-16. Utility 1 Interface Pin/Signal Descriptions (J15)
| Pin # | Signal | Description |
| 1 | MDI0+ | Media Dependent Interface [0] |
| 2 | MDI0- | 1000BaseT – In MDI configuration, MDI0± corresponds to BI_DA±, and in MDI-X configuration, MDI0± corresponds to BI_DB±.10/100BaseT – In MDI configuration, MDI0± is used for the transmit pair, and in MDI-X configuration, MDI0± is used for the receive pair. |
| 3 | MDI1+ | Media Dependent Interface [1] |
| 6 | MDI1- | 1000BaseT – In MDI configuration, MDI1± corresponds to BI_DB±, and in MDI-X configuration, MDI1± corresponds to BI_DA±.10/100BaseT – In MDI configuration, MDI1± is used for the transmit pair, and in MDI-X configuration, MDI1± is used for the receive pair. |
| 4 | MDI2+ | Media Dependent Interface [2] |
| 5 | MDI2- | 1000BaseT – In MDI configuration, MDI2± corresponds to BI_DC±, and in MDI-X configuration, MDI2± corresponds to BI_DD±.10/100BaseT – Unused |
| 7 | MDI3+ | Media Dependent Interface [3] |
| 8 | MDI3- | 1000BaseT – In MDI configuration, MDI3± corresponds to BI_DC±, and in MDI-X configuration, MDI3± corresponds to BI_DD±.10/100BaseT – Unused |
| 9 | SPEED_1000 | Speed (1000) LED – Indicates transfer rate at 1000Mbps. |
| 10 | SPEED_100 | Speed (100) LED – Indicates transfer rate at 10Mbps or 100Mbps. |
| 11 | LINKLED | Link LED – Indicates Link established between this port and another device |
| 12 | ACTLED | Activity LED – Indicates Activity is occurring on the Ethernet link. |
| 13, 14 | SHLD | Shields – Connected to center taps of transformer and floating ground while isolated from board common ground by 1000pf capacitor. |
Note: The shaded area denotes power or ground.
# Audio Interface (J9)
The audio solution on the LittleBoard 800 is provided by the Realtek ALC202A audio CODEC. The chip is defined by AC97 and is revision 2.2 compliant. The audio interface signals are supplied to the 26-pin 2mm connector (J9). Refer to the following list for the Audio CODEC (ALC202A) features.
• Analog Mixer Dynamic Range 97dB (typ)
• D/A Dynamic Range 89dB (typ) and A/D Dynamic Range 90dB (typ)
• AC’97 Rev 2.1 compliant
• High quality Sample Rate Conversion (SRC) from 4kHz to 48kHz
• 3D Sound circuitry and PC-Beep passthrough to Line Out while reset is held active low
• True Line Level Output with volume control independent of Line Out
Table 3-22 describes the pin-outs and signals of the audio interface and it has 26 pins, 2 rows, odd/even, (1, 2) with 2mm pin spacing.
Table 3-22. Audio Interface Pin/Signal Descriptions (J9)