# MXM-P1000

NVIDIA® Pascal™ GP107 Quadro® P1000 Embedded Graphics Module

User's Manual

![Close-up of a green printed circuit board with multiple integrated circuits and visible traces (no readable text or symbols)](.mxm-p1000-50-1z297-1000-10/797c4a201ac5e838cc80e9ee318ad516966e9767742c66ddb1d6c354c7c5bde7.jpg)

Manual Rev.: 1.0

Revision Date: June 19, 2019

Part No: 50-1Z297-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>June 19, 2019</td><td>Initial Release</td></tr></table>

# Preface

# Copyright 2019 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.mxm-p1000-50-1z297-1000-10/6e6348a3ca5b61fe83514ae922601b8923a3b14bd910752b7c1322dcc9e2a5c0.jpg)

![The image displays a black line drawing on a white background. It features a thick horizontal line at the top. From the left end of this horizontal line, a vertical line extends downwards. From the right end of the horizontal line, a vertical line extends downwards, forming the top part of a rectangular shape or square bracket.](.mxm-p1000-50-1z297-1000-10/ed7147c06ce59b1c0edd5cad33a5d61c4909fde9e37b82791df723e178a123a3.jpg)

# Battery Labels (for products with battery)

![Symbol of a trash bin crossed with no text or numbers, representing waste sorting or disposal (no text present)](.mxm-p1000-50-1z297-1000-10/6b12ad85153da4dd6574933563ad887e7d2a403d83d61bf96b7ab645bab79ea6.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.mxm-p1000-50-1z297-1000-10/bd16d30c21b779b65325e909b231cb32a04516b153a5774612d8fa66dae8ce9b.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n1.800.822.8837](.mxm-p1000-50-1z297-1000-10/9684fcf7624c9e89af84424242f557e828c691dea44d0ec98a930b92538700ea.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.mxm-p1000-50-1z297-1000-10/496f318b224d665a4617706a75b87c844c4f8f51b41d36fa0e4eb093875637c0.jpg)

廢電池請回收

# California Proposition 65 Warning

![A yellow triangle with a black outline featuring a black exclamation mark in the center, set against a white background.](.mxm-p1000-50-1z297-1000-10/92938e56078dffbdf5f67ebb687b681b916e0e67ad1517e30a1138bff051100c.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.mxm-p1000-50-1z297-1000-10/d1cf43a2e817e5c915440f60f8bbe5bb5f12fdeffe56f07944448246075378f0.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border containing a black exclamation point. Below the triangle is the text 'CAUTION:' in black capital letters.](.mxm-p1000-50-1z297-1000-10/d891595cce74bb3207c2c1e981e0a25b784fcb06681859cfac0027964b2f08f4.jpg)

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image features a red triangle containing a white exclamation point in the center. Below the triangle, the text 'WARNING:' is printed in black, uppercase letters.](.mxm-p1000-50-1z297-1000-10/580bcd3e9712a970848b616088ba0da9fc502cbd22ee1799d7cea845e189e027.jpg)

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

This page intentionally left blank.

# Table of Contents

# Preface .... iii

# List of Tables ix

# List of Figures ...... xi

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 1
1.3 Specifications.... 2

1.3.1 Board 2
1.3.2 Memory Configuration 2
1.3.3 Display Support and Options....3
1.3.4 OS 3
1.3.5 Software Support....3
1.3.6 Graphics Options....3

1.4 Functional Block Diagram.... 4
1.5 Layout and I/O 5

1.5.1 MXM Connector....6

1.6 Thermal Policy 11
1.7 Unpacking Checklist 12

# 2 System Requirements.... 13

2.1 Power Sequencing.... 13
2.2 Module Power Up and Down 13
2.3 Reset Requirements 14
2.4 Dual Mode DisplayPort Implementation 14
2.5 DVI/HDMI on DisplayPort Interface 15
2.6 Driver Installation 16
2.7 Certifications & Agencies 16

Important Safety Instructions.... 17

Getting Service 21

# List of Tables

Table 1-1: Graphics Module Display Options .... 3
Table 1-2: NVIDIA Link Display Types 4
Table 1-3: MXM Connector Pin Assignments....6
Table 1-4: Thermal Policy....12

This page intentionally left blank.

# List of Figures

Figure 1-1: MXM-P1000 Dimensions....5
Figure 1-2: MXM-P1000 Component Layout 6
Figure 1-3: MXM Connector Pins....6
Figure 2-1: Power Sequencing 13
Figure 2-2: Module Power Down 14
Figure 2-3: Reset Sequencing 14
Figure 2-4: Dual Mode DisplayPort Implementation 15
Figure 2-5: DVI/HDMI on DisplayPort Interface 16

This page intentionally left blank.

# 1 Introduction

# 1.1 Overview

The MXM-P1000 module features advanced NVIDIA® Quadro® Pascal™ architecture in the MXM 3.1 Type A form factor. The P1000 brings a new level of performance to visual graphics and computing applications, fully integrating hardware acceleration for both graphics and computing code, enabling hardware acceleration for a wider class of software applications than ever before.

The compact, module supports operability in an extended temperature range of $-40^{\circ}C$ to $85^{\circ}C$ , suitable for mission-critical harsh environments. With its 512 CUDA core Pascal GPU, the MXM-P1000 supports 4 FHD displays, offering a flexible and easy solution for medical and gaming applications.

# 1.2 Features

▶ MXM 3.1 Type A FF (82 x 70 mm)
▶ 512 CUDA cores
▶ 1.8 TFLOPS SP peak performance
▶ 4 GB GDDR5 memory
▶ 96 GB/s maximal memory bandwidth
▶ Support for up to 4 FHD displays, 50W TDP
▶ 5 year performance warranty
▶ Nvidia Quadro P1000 GPU

▷ Package 29 x 29 mm
▷ Base Clock @1354 MHz
▶ Boost Clock @1392 MHz

# 1.3 Specifications

# 1.3.1 Board

<table><tr><td colspan="2">Graphics Core</td></tr><tr><td>Architecture</td><td>NVIDIA® PascalTM GP107</td></tr><tr><td>GPU</td><td>Quadro® P1000</td></tr><tr><td>Display Outputs</td><td>4x DisplayPort 1.4 digital video outputsSupport for High Dynamic Range (HDR) video4K at 120Hz or 5K at 60Hz with 10-bit color depth</td></tr><tr><td>Signal Interface</td><td>MXM 3.1, PCI Express Gen3 x16 support</td></tr><tr><td colspan="2">GPGPU Computing</td></tr><tr><td>CUDA Support</td><td>640 CUDA cores, 1.8TFLOPS SP PeakCUDA Toolkit 8.0, CUDA Compute version 6.1OpenCLTM 1.2, DirectX® 12, OpenGL 4.5, Vulcan 1.0</td></tr><tr><td colspan="2">Memory</td></tr><tr><td>GDDR5 Memory</td><td>4GB</td></tr><tr><td>Memory Width</td><td>128-bit</td></tr><tr><td>Bandwidth</td><td>96 GB/s</td></tr><tr><td colspan="2">Physical</td></tr><tr><td>Dimensions</td><td>87 (W) x 70 (D) x 4.8 (H) mm</td></tr><tr><td>Locking Mechanism</td><td>Standard MXM 3.1 Type A</td></tr><tr><td colspan="2">Environmental</td></tr><tr><td>Operating Temp.</td><td>Standard: 0 to 55°C, ETT: -20°C to 70°C</td></tr><tr><td>Storage Temp.</td><td>-40°C to 85°C</td></tr><tr><td colspan="2">OS</td></tr><tr><td>Supported OS</td><td>Windows 7/10 &amp; Linux Drivers, 64-bit</td></tr></table>

# 1.3.2 Memory Configuration

<table><tr><td>Memory</td><td>GDDR5@6Gbps</td></tr><tr><td>Configuration</td><td>256Mx32</td></tr><tr><td rowspan="3">Memory Bandwidth</td><td>128-bit</td></tr><tr><td>82 GB/s data rate</td></tr><tr><td>x32 GDDR5 DRAM device data width</td></tr><tr><td>Capacity</td><td>Total 4 GByte</td></tr></table>

# 1.3.3 Display Support and Options

<table><tr><td>DisplayPort</td><td>▶ 1.2/1.3/1.4▶ Max. pixel clock: 1050 MP/s▶ Max. bandwidth: 25.9 GB/s/connector</td></tr><tr><td>HDMI 2.0</td><td>Max. resolution: 4096 x 2160 at 60 Hz</td></tr><tr><td>HDCP Support</td><td>1.3 (DP), 2.2 (DP, HDMI)</td></tr></table>

# 1.3.4 OS

Supported:

▶ Windows 7/10 (64bit)
▶ Linux (64bit)

# 1.3.5 Software Support

Supported:

▶ CUDA Toolkit 8.0
▶ CUDA Compute version 6.1
▶ OpenCL™ 1.2
▶ DirectX® 12
▶ OpenGL 4.5
▶ Vulcan 1.0

# 1.3.6 Graphics Options

The MXM-P1000 supports 4xDisplayPort by default. EGX-MXM-P1000 graphics module display options are as shown.

<table><tr><td>MXM port</td><td>DP_A</td><td>DP_B</td><td>DP_C</td><td>DP_D</td></tr><tr><td>NVIDIA Link</td><td>Link E</td><td>Link F</td><td>Link A</td><td>Link B</td></tr></table>

Table 1-1: Graphics Module Display Options

<table><tr><td>Link</td><td>Display Type</td></tr><tr><td>Link A</td><td>DisplayPort, DVI (Single Link or Dual Link with Link B)</td></tr><tr><td>Link B</td><td>DisplayPort, DVI (Dual Link with A)</td></tr><tr><td>Link C</td><td>DisplayPort, HDMI</td></tr><tr><td>Link D</td><td>Internal/ eDP only</td></tr><tr><td>Link E</td><td>DisplayPort, HDMI</td></tr><tr><td>Link F</td><td>DisplayPort</td></tr></table>

Table 1-2: NVIDIA Link Display Types

# 1.4 Functional Block Diagram

![Based on the provided block diagram, here is the accurate description of the labeled blocks and connections:\n\n**Labeled Blocks:**\n*   **MxM 3.1 Connector** (Left vertical block)\n*   **N18P-0140W** (Central vertical block)\n*   **SPI - VBIOS** (Bottom center box)\n*   **GDDR5 x32 memory down** (Four separate boxes on the top right)\n*   **Power Supply** (Box containing NVVDD-PH1, NVVDD-PH2, NVVDD-PH3, NVVDD-PH4)\n*   **Power Supply FBVDDQ**\n*   **Power Supply PEX_VDD**\n*   **Power Supply VDD_AON/MAIN**\n\n**Connections:**\n\n**Between MxM 3.1 Connector and N18P-0140W:**\n*   **PCIE x16 Gen3** connects to **PCIE**.\n*   Four instances of **DP1.4** connect to **IFPA**, **IFPB**, **IFPE**, and **IFPF** respectively.\n*   **I2CS** connects to **I2CS**.\n*   **(PWR EN, PWR_GOOD, WAKE#)** connects to **PM**.\n*   **JTAG** connects to **JTAG**.\n*   **P_+SRC**, **P_+5V**, and **P_+3V3** point into the MxM 3.1 Connector.\n\n**From N18P-0140W to Peripheral Blocks:**\n*   **PCIE** connects via **GDDR5 Channel A** to two blocks labeled **GDDR5 x32 memory down**.\n*   **GDDR5 Channel B** connects to two blocks labeled **GDDR5 x32 memory down**.\n*   **PM** connects to the **Power Supply** block (containing **NVVDD-PH1**, **NVVDD-PH2**, **NVVDD-PH3**, **NVVDD-PH4**).\n*   **JTAG** connects to **Power Supply FBVDDQ**.\n*   **SPI** connects to **SPI - VBIOS**.\n*   **Power Supply PEX_VDD** points into the N18P-0140W block.\n*   **Power Supply VDD_AON/MAIN** points into the N18P-0140W block.](.mxm-p1000-50-1z297-1000-10/6a94b7df3e4781c68ce01a718cab76592ac79f9fee9dadf0b72b0e066f289507.jpg)

# 1.5 Layout and I/O

![The image displays a graphic icon representing a document or page with a folded top-right corner. It features faint horizontal gray lines running across the white background, resembling a piece of lined paper. A large, bold red checkmark is superimposed diagonally across the center of the document.](.mxm-p1000-50-1z297-1000-10/3069a3fe2bd6cd6fa89e8b9df117143ec25f2b85e5b6101f34f8d08f7bc349a1.jpg)
NOTE:

All dimensions shown are in mm

![Ø3.20 x6\nØ6 x6\n70\n82](.mxm-p1000-50-1z297-1000-10/42535b64bc63df4c189dd72ec9247b239c450acc29b933cf305e2f3257293b38.jpg)

Figure 1-1: MXM-P1000 Dimensions

![4 (157.5)\n0 (0)\n6.242 (245.7)\n8.25 (324.8)\n21.127 (831.8)\n31.13 (1225.6)\n40.873 (1609.2)\n54.25 (2135.8)\n58.35 (2297.2)\n59.8 (2354.3)\n66 (2598.4)\n3.1±0.1 (122±3.94)\n0.5±0.1 (19.7±3.94)\n3.5 (137.8)\n0 (0)\n5.5 (216.5)\n18.377 (723.5)\n28.5 (1122)\n28.5 (1900.9)\n38.123 (1900.9)\n51.5 (2027.6)\n75 (2992.8)\n75.5 (3090.6)\nA\nB\nB\nB\nB\nB\n134±0.35±0.03 (13.8±1.18)\n0.85±0.03 (33.5±1.18)\n4.82±0.03 (189.8±1.18)\n2 PLACES\n剖面图 B-B\n45°±10°\n0.3±0.12 (11.8±4.72)](.mxm-p1000-50-1z297-1000-10/01f6e5fcae5ea59f94ce848810cbd7bd0315decb2727b3c2d806e1279d7779dd.jpg)

Figure 1-2: MXM-P1000 Component Layout

# 1.5.1 MXM Connector

![4(157.5)\n0(0)\n6.243(245.7)\n8.25(324.6)\n21.127(931.6)\n31.13(1225.6)\n40.873(1609.2)\n54.25(5135.8)\n58.35(297.2)\n59.8(2354.3)\n60(2599.4)\n3.140.1(122±3.94)\n134±0.35±0.03(13.8±1.18)\n0.85±0.03(33.5±1.18)\n4.82±0.03(19.9±1.18)\n2 PAGES\nA\nB\nB\nB\nA\nA\n1/20mm\n45°×10'\n0.3±0.12(11.8±4.72)\n剖面图 B-B](.mxm-p1000-50-1z297-1000-10/62b5b8716a66b9771d75518412f687c651e585dc70b89625058fc5cb3c8cd4ed.jpg)

Figure 1-3: MXM Connector Pins

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>E1</td><td>PWR_SRC</td><td></td><td>E2</td><td>PWR_SRC</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Assignments

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>E3</td><td>GND</td><td></td><td>E4</td><td>GND</td><td></td></tr><tr><td>1</td><td>5V</td><td></td><td>2</td><td>PRSNT_R#</td><td>0Ω PD</td></tr><tr><td>3</td><td>5V</td><td></td><td>4</td><td>WAKE#</td><td>NI</td></tr><tr><td>5</td><td>5V</td><td></td><td>6</td><td>PWR_GOOD</td><td>1K PU 3.3V</td></tr><tr><td>7</td><td>5V</td><td></td><td>8</td><td>PWR_EN</td><td></td></tr><tr><td>9</td><td>5V</td><td></td><td>10</td><td>27MHZ_REF</td><td>NI</td></tr><tr><td>11</td><td>GND</td><td></td><td>12</td><td>GND</td><td></td></tr><tr><td>13</td><td>GND</td><td></td><td>14</td><td>LVDS_U_HPD</td><td>NI</td></tr><tr><td>15</td><td>GND</td><td></td><td>16</td><td>JTAG_TESTEN</td><td></td></tr><tr><td>17</td><td>GND</td><td></td><td>18</td><td>PWR_LEVEL</td><td>100K PU 3.3V</td></tr><tr><td>19</td><td>PEX_STD_SW#</td><td>NI</td><td>20</td><td>TH_OVERT#</td><td>100K PU 3.3V</td></tr><tr><td>21</td><td>VGA_DISABLE#</td><td>NI</td><td>22</td><td>TH_ALERT#</td><td>100K PU 3.3V</td></tr><tr><td>23</td><td>PNL_PWR_EN</td><td></td><td>24</td><td>TH_PWM</td><td>NI</td></tr><tr><td>25</td><td>PNL_BL_EN</td><td></td><td>26</td><td>GPIO0</td><td>NI</td></tr><tr><td>27</td><td>PNL_BL_PWM</td><td></td><td>28</td><td>GPIO1</td><td>NI</td></tr><tr><td>29</td><td>HDMI_CEC</td><td>NI</td><td>30</td><td>GPIO2</td><td>NI</td></tr><tr><td>31</td><td>LVDS_L_HPD</td><td>NI</td><td>32</td><td>SMB_DAT</td><td>10K PU 3.3V</td></tr><tr><td>33</td><td>LVDS_DDC_DAT</td><td>NI</td><td>34</td><td>SMB_CLK</td><td>10K PU 3.3V</td></tr><tr><td>35</td><td>LVDS_DDC_CLK</td><td>NI</td><td>36</td><td>GND</td><td></td></tr><tr><td>37</td><td>GND</td><td></td><td>38</td><td>OEM0</td><td>NI</td></tr><tr><td>39</td><td>OEM1</td><td>NI</td><td>40</td><td>OEM2</td><td>NI</td></tr><tr><td>41</td><td>OEM3</td><td>NI</td><td>42</td><td>OEM4</td><td>NI</td></tr><tr><td>43</td><td>OEM5</td><td>NI</td><td>44</td><td>OEM6</td><td>NI</td></tr><tr><td>45</td><td>OEM7</td><td>NI</td><td>46</td><td>GND</td><td></td></tr><tr><td>47</td><td>GND</td><td></td><td>48</td><td>PEX_TX15#</td><td></td></tr><tr><td>49</td><td>PEX_RX15#</td><td></td><td>50</td><td>PEX_TX15</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Assignments

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>51</td><td>PEX_RX15</td><td></td><td>52</td><td>GND</td><td></td></tr><tr><td>53</td><td>GND</td><td></td><td>54</td><td>PEX_TX14#</td><td></td></tr><tr><td>55</td><td>PEX_RX14#</td><td></td><td>56</td><td>PEX_TX14</td><td></td></tr><tr><td>57</td><td>PEX_RX14</td><td></td><td>58</td><td>GND</td><td></td></tr><tr><td>59</td><td>GND</td><td></td><td>60</td><td>PEX_TX13#</td><td></td></tr><tr><td>61</td><td>PEX_RX13#</td><td></td><td>62</td><td>PEX_TX13</td><td></td></tr><tr><td>63</td><td>PEX_RX13</td><td></td><td>64</td><td>GND</td><td></td></tr><tr><td>65</td><td>GND</td><td></td><td>66</td><td>PEX_TX12#</td><td></td></tr><tr><td>67</td><td>PEX_RX12#</td><td></td><td>68</td><td>PEX_TX12</td><td></td></tr><tr><td>69</td><td>PEX_RX12</td><td></td><td>70</td><td>GND</td><td></td></tr><tr><td>71</td><td>GND</td><td></td><td>72</td><td>PEX_TX11#</td><td></td></tr><tr><td>73</td><td>PEX_RX11#</td><td></td><td>74</td><td>PEX_TX11</td><td></td></tr><tr><td>75</td><td>PEX_RX11</td><td></td><td>76</td><td>GND</td><td></td></tr><tr><td>77</td><td>GND</td><td></td><td>78</td><td>PEX_TX10#</td><td></td></tr><tr><td>79</td><td>PEX_RX10#</td><td></td><td>80</td><td>PEX_TX10</td><td></td></tr><tr><td>81</td><td>PEX_RX10</td><td></td><td>82</td><td>GND</td><td></td></tr><tr><td>83</td><td>GND</td><td></td><td>84</td><td>PEX_TX9#</td><td></td></tr><tr><td>85</td><td>PEX_RX9#</td><td></td><td>86</td><td>PEX_TX9</td><td></td></tr><tr><td>87</td><td>PEX_RX9</td><td></td><td>88</td><td>GND</td><td></td></tr><tr><td>89</td><td>GND</td><td></td><td>90</td><td>PEX_TX8#</td><td></td></tr><tr><td>91</td><td>PEX_RX8#</td><td></td><td>92</td><td>PEX_TX8</td><td></td></tr><tr><td>93</td><td>PEX_RX8</td><td></td><td>94</td><td>GND</td><td></td></tr><tr><td>95</td><td>GND</td><td></td><td>96</td><td>PEX_TX7#</td><td></td></tr><tr><td>97</td><td>PEX_RX7#</td><td></td><td>98</td><td>PEX_TX7</td><td></td></tr><tr><td>99</td><td>PEX_RX7</td><td></td><td>100</td><td>GND</td><td></td></tr><tr><td>101</td><td>GND</td><td></td><td>102</td><td>PEX_TX6#</td><td></td></tr><tr><td>103</td><td>PEX_RX6#</td><td></td><td>104</td><td>PEX_TX6</td><td></td></tr><tr><td>105</td><td>PEX_RX6</td><td></td><td>106</td><td>GND</td><td></td></tr><tr><td>107</td><td>GND</td><td></td><td>108</td><td>PEX_TX5#</td><td></td></tr><tr><td>109</td><td>PEX_RX5#</td><td></td><td>110</td><td>PEX_TX5</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Assignments

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>111</td><td>PEX_RX5</td><td></td><td>112</td><td>GND</td><td></td></tr><tr><td>113</td><td>GND</td><td></td><td>114</td><td>PEX_TX4#</td><td></td></tr><tr><td>115</td><td>PEX_RX4#</td><td></td><td>116</td><td>PEX_TX4</td><td></td></tr><tr><td>117</td><td>PEX_RX4</td><td></td><td>118</td><td>GND</td><td></td></tr><tr><td>119</td><td>GND</td><td></td><td>120</td><td>PEX_TX3#</td><td></td></tr><tr><td>121</td><td>PEX_RX3#</td><td></td><td>122</td><td>PEX_TX3</td><td></td></tr><tr><td>123</td><td>PEX_RX3</td><td></td><td>124</td><td>GND</td><td></td></tr><tr><td>125</td><td>GND</td><td></td><td>126</td><td>KEY</td><td></td></tr><tr><td>127</td><td>KEY</td><td></td><td>128</td><td>KEY</td><td></td></tr><tr><td>129</td><td>KEY</td><td></td><td>130</td><td>KEY</td><td></td></tr><tr><td>131</td><td>KEY</td><td></td><td>132</td><td>KEY</td><td></td></tr><tr><td>133</td><td>GND</td><td></td><td>134</td><td>GND</td><td></td></tr><tr><td>135</td><td>PEX_RX2#</td><td></td><td>136</td><td>PEX_TX2#</td><td></td></tr><tr><td>137</td><td>PEX_RX2</td><td></td><td>138</td><td>PEX_TX2</td><td></td></tr><tr><td>139</td><td>GND</td><td></td><td>140</td><td>GND</td><td></td></tr><tr><td>141</td><td>PEX_RX1#</td><td></td><td>142</td><td>PEX_TX1#</td><td></td></tr><tr><td>143</td><td>PEX_RX1</td><td></td><td>144</td><td>PEX_TX1</td><td></td></tr><tr><td>145</td><td>GND</td><td></td><td>146</td><td>GND</td><td></td></tr><tr><td>147</td><td>PEX_RX0#</td><td></td><td>148</td><td>PEX_TX0#</td><td></td></tr><tr><td>149</td><td>PEX_RX0</td><td></td><td>150</td><td>PEX_TX0</td><td></td></tr><tr><td>151</td><td>GND</td><td></td><td>152</td><td>GND</td><td></td></tr><tr><td>153</td><td>PEX_REFCLK#</td><td></td><td>154</td><td>PEX_CLK_REQ#</td><td></td></tr><tr><td>155</td><td>PEX_REFCLK</td><td></td><td>156</td><td>PEX_RST#</td><td></td></tr><tr><td>157</td><td>GND</td><td></td><td>158</td><td>VGA_DDC_DAT</td><td>NI</td></tr><tr><td>159</td><td>JTAG_TDO</td><td></td><td>160</td><td>VGA_DDC_CLK</td><td>NI</td></tr><tr><td>161</td><td>JTAG_TDI</td><td></td><td>162</td><td>VGA_VSYNC</td><td>NI</td></tr><tr><td>163</td><td>JTAG_TCLK</td><td></td><td>164</td><td>VGA_HSYNC</td><td>NI</td></tr><tr><td>165</td><td>JTAG_TMS</td><td></td><td>166</td><td>GND</td><td></td></tr><tr><td>167</td><td>JTAG_TRST#</td><td></td><td>168</td><td>VGA_RED</td><td>NI</td></tr><tr><td>169</td><td>LVDS_UCLK#</td><td>NI</td><td>170</td><td>VGA_GREEN</td><td>NI</td></tr></table>

Table 1-3: MXM Connector Pin Assignments

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>171</td><td>LVDS_UCLK</td><td>NI</td><td>172</td><td>VGA_BLUE</td><td>NI</td></tr><tr><td>173</td><td>GND</td><td></td><td>174</td><td>GND</td><td></td></tr><tr><td>175</td><td>LVDS_UTX3#</td><td>NI</td><td>176</td><td>LVDS_LCLK#</td><td>NI</td></tr><tr><td>177</td><td>LVDS_UTX3</td><td>NI</td><td>178</td><td>LVDS_LCLK</td><td>NI</td></tr><tr><td>179</td><td>GND</td><td></td><td>180</td><td>GND</td><td></td></tr><tr><td>181</td><td>LVDS_UTX2#</td><td>NI</td><td>182</td><td>LVDS_LTX3#</td><td>NI</td></tr><tr><td>183</td><td>LVDS_UTX2</td><td>NI</td><td>184</td><td>LVDS_LTX3</td><td>NI</td></tr><tr><td>185</td><td>GND</td><td></td><td>186</td><td>GND</td><td></td></tr><tr><td>187</td><td>LVDS_UTX1#</td><td>NI</td><td>188</td><td>LVDS_LTX2#</td><td>NI</td></tr><tr><td>189</td><td>LVDS_UTX1</td><td>NI</td><td>190</td><td>LVDS_LTX2</td><td>NI</td></tr><tr><td>191</td><td>GND</td><td></td><td>192</td><td>GND</td><td></td></tr><tr><td>193</td><td>LVDS_UTX0#</td><td>NI</td><td>194</td><td>LVDS_LTX1#</td><td>NI</td></tr><tr><td>195</td><td>LVDS_UTX0</td><td>NI</td><td>196</td><td>LVDS_LTX1</td><td>NI</td></tr><tr><td>197</td><td>GND</td><td></td><td>198</td><td>GND</td><td></td></tr><tr><td>199</td><td>DP_C_L0#</td><td></td><td>200</td><td>LVDS_LTX0#</td><td>NI</td></tr><tr><td>201</td><td>DP_C_L0</td><td></td><td>202</td><td>LVDS_LTX0</td><td>NI</td></tr><tr><td>203</td><td>GND</td><td></td><td>204</td><td>GND</td><td></td></tr><tr><td>205</td><td>DP_C_L1#</td><td></td><td>206</td><td>DP_D_L0#</td><td></td></tr><tr><td>207</td><td>DP_C_L1</td><td></td><td>208</td><td>DP_D_L0</td><td></td></tr><tr><td>209</td><td>GND</td><td></td><td>210</td><td>GND</td><td></td></tr><tr><td>211</td><td>DP_C_L2#</td><td></td><td>212</td><td>DP_D_L1#</td><td></td></tr><tr><td>213</td><td>DP_C_L2</td><td></td><td>214</td><td>DP_D_L1</td><td></td></tr><tr><td>215</td><td>GND</td><td></td><td>216</td><td>GND</td><td></td></tr><tr><td>217</td><td>DP_C_L3#</td><td></td><td>218</td><td>DP_D_L2#</td><td></td></tr><tr><td>219</td><td>DP_C_L3</td><td></td><td>220</td><td>DP_D_L2</td><td></td></tr><tr><td>221</td><td>GND</td><td></td><td>222</td><td>GND</td><td></td></tr><tr><td>223</td><td>DP_C_AUX#</td><td></td><td>224</td><td>DP_D_L3#</td><td></td></tr><tr><td>225</td><td>DP_C_AUX</td><td></td><td>226</td><td>DP_D_L3</td><td></td></tr><tr><td>227</td><td>RSVD</td><td></td><td>228</td><td>GND</td><td></td></tr><tr><td>229</td><td>RSVD</td><td></td><td>230</td><td>DP_D_AUX#</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Assignments

<table><tr><td colspan="3">Primary Side (underside)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD/NI</td><td>Pin</td><td>Signal</td><td>PU/PD/NI</td></tr><tr><td>231</td><td>RSVD</td><td></td><td>232</td><td>DP_D_AUX</td><td></td></tr><tr><td>233</td><td>RSVD</td><td></td><td>234</td><td>DP_C_HPD</td><td></td></tr><tr><td>235</td><td>RSVD</td><td></td><td>236</td><td>DP_D_HPD</td><td></td></tr><tr><td>237</td><td>RSVD</td><td></td><td>238</td><td>RSVD</td><td></td></tr><tr><td>239</td><td>RSVD</td><td></td><td>240</td><td>3V3</td><td></td></tr><tr><td>241</td><td>RSVD</td><td></td><td>242</td><td>3V3</td><td></td></tr><tr><td>243</td><td>RSVD</td><td></td><td>244</td><td>GND</td><td></td></tr><tr><td>245</td><td>RSVD</td><td></td><td>246</td><td>DP_B_L0#</td><td></td></tr><tr><td>247</td><td>RSVD</td><td></td><td>248</td><td>DP_B_L0</td><td></td></tr><tr><td>249</td><td>RSVD</td><td></td><td>250</td><td>GND</td><td></td></tr><tr><td>251</td><td>GND</td><td></td><td>252</td><td>DP_B_L1#</td><td></td></tr><tr><td>253</td><td>DP_A_L0#</td><td></td><td>254</td><td>DP_B_L1</td><td></td></tr><tr><td>255</td><td>DP_A_L0</td><td></td><td>256</td><td>GND</td><td></td></tr><tr><td>257</td><td>GND</td><td></td><td>258</td><td>DP_B_L2#</td><td></td></tr><tr><td>259</td><td>DP_A_L1#</td><td></td><td>260</td><td>DP_B_L2</td><td></td></tr><tr><td>261</td><td>DP_A_L1</td><td></td><td>262</td><td>GND</td><td></td></tr><tr><td>263</td><td>GND</td><td></td><td>264</td><td>DP_B_L3#</td><td></td></tr><tr><td>265</td><td>DP_A_L2#</td><td></td><td>266</td><td>DP_B_L3</td><td></td></tr><tr><td>267</td><td>DP_A_L2</td><td></td><td>268</td><td>GND</td><td></td></tr><tr><td>269</td><td>GND</td><td></td><td>270</td><td>DP_B_AUX#</td><td></td></tr><tr><td>271</td><td>DP_A_L3#</td><td></td><td>272</td><td>DP_B_AUX</td><td></td></tr><tr><td>273</td><td>DP_A_L3</td><td></td><td>274</td><td>DP_B_HPD</td><td></td></tr><tr><td>275</td><td>GND</td><td></td><td>276</td><td>DP_A_HPD</td><td></td></tr><tr><td>277</td><td>DP_A_AUX#</td><td></td><td>278</td><td>3V3</td><td></td></tr><tr><td>279</td><td>DP_A_AUX</td><td></td><td>280</td><td>3V3</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Assignments

# 1.6 Thermal Policy

The GPU core clock throttles at temperatures (TJ) past the thresholds shown with the behaviors as listed. Thermal throttling ensures that the highest temperature on the die does not exceed the sense temperature for prolonged periods of time.

<table><tr><td>Parameter</td><td>Value</td><td>Unit</td></tr><tr><td>Thermal Resistance (Junction to Case, RJC)</td><td>0.03</td><td>°C/W</td></tr><tr><td>Thermal Resistance (Junction to PCB Board, RJB)</td><td>3.0</td><td>°C/W</td></tr><tr><td>GPU Maximum Operating Temperature1</td><td>94</td><td>°C</td></tr><tr><td>GPU Slowdown Temperature (THERM_ALERT)2</td><td>97</td><td>°C</td></tr><tr><td>GPU Shutdown Temperature (OVERT)3</td><td>102</td><td>°C</td></tr></table>

Table 1-4: Thermal Policy

![The image displays an icon of a white sheet of paper with faint horizontal lines running across it, resembling a document. A large, bold red checkmark is superimposed over the paper, extending diagonally from the bottom left to the upper right. The top left corner of the document is depicted with a slight fold.](.mxm-p1000-50-1z297-1000-10/a1f38c4714eb1916036f40b8a3c5b78696b40994d8da5aebd249b43bcfdedf9d.jpg)
NOTE:

▶ Max.GPU operating temperature is the maximum at which the GPU is guaranteed to operate at target performance (base clock) under total board power level
▶ THERM\_ALERT generates a 50% (÷2) hardware clock slowdown.
▶ OVERT generates a 87.5% (÷8) hardware clock slowdown

# 1.7 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

MXM-P1000 unit

# 2 System Requirements

# 2.1 Power Sequencing

For initial power on, or to Resume from S3 and S4, this sequence must be followed.

![| Component           | Time Interval |\n|---------------------|---------------|\n| PWR_SRC             | T_PV-PE       |\n| 5V                  | T_PV-PE       |\n| 3V3                 | T_PV-PE       |\n| PWR_EN              | T_PV-PE       |\n| Module Internal Power | T_PE-PG       |\n| PWR_GOOD            | T_PE-PG       |](.mxm-p1000-50-1z297-1000-10/697cc714b0bfe8bd399ea0f190bd27299154163ddddda6a274b7ea31535be855.jpg)

Figure 2-1: Power Sequencing

# 2.2 Module Power Up and Down

Issuing the PWR\_EN signal powers the MXM module down, and the system designer can decide whether to keep the module input power when the MXM module is powered down.

![MODULE\nINPUT POWER\nPWR_EN\nMODULE\nINTERNAL POWER\nPWR_GOOD](.mxm-p1000-50-1z297-1000-10/d717cf5a4c80e16bd5170980fe7758dde4d0b74085f1576310639da8d5d21123.jpg)

Figure 2-2: Module Power Down

# 2.3 Reset Requirements

![| Signal          | Value     |\n|-----------------|-----------|\n| PWR_EN          | ≥100 ms   |\n| PWR_GOOD        | ≥100 μs   |\n| PEX_REFCLK      | ≥200 μs   |\n| PEX_RST#        | ≤500 ns   |](.mxm-p1000-50-1z297-1000-10/30f8f34636e4ce24ebe4aaca5bd305b6b045e582f66478fa02d90298089d7c63.jpg)

Figure 2-3: Reset Sequencing

# 2.4 Dual Mode DisplayPort Implementation

The MXM-P1000 supports four dual mode DisplayPorts by default. HDMI is supported via dongle (see “Display Support and Options” on page 3.). The system requires a switch circuit to determine whether the AUX or DDC signal is output from the MXM module, and AC coupling capacitors should be placed on the system board.

![The diagram illustrates a circuit connecting an **MXM Connector** (left vertical block) to a **DisplayPort Connector** (right vertical block).\n\n**Top Section (AUX Lines):**\n*   Two signal lines, labeled **AUX_P/DDC_CLK** and **AUX_N/DDC_DAT**, run horizontally from the MXM Connector to the DisplayPort Connector.\n*   These lines pass through capacitors (represented by parallel vertical lines) located centrally.\n*   To the left of the capacitors, there is a section enclosed in a bracket labeled **CONFIG1 (CABLE ADAPTOR DETECT)**. This section contains two switches connected to the signal lines.\n*   A **3.3V** rail connects via a resistor to the **AUX_P/DDC_CLK** line.\n*   A ground symbol connects via a resistor to the **AUX_N/DDC_DAT** line.\n\n**Middle Section:**\n*   A single line runs from the MXM Connector to the DisplayPort Connector, passing through a block labeled **Hot Plug Detect**.\n\n**Bottom Section (Data Lines):**\n*   Two signal lines, labeled **DP_x_Lx_P** and **DP_x_Lx_N**, run horizontally from the MXM Connector to the DisplayPort Connector.\n*   These lines pass through capacitors (represented by parallel vertical lines) located centrally.](.mxm-p1000-50-1z297-1000-10/fd7fb740bf8cc76aabf49e997bccbfeac238b56a1d1f6bb07cc13c930249d88c.jpg)

Figure 2-4: Dual Mode DisplayPort Implementation

# 2.5 DVI/HDMI on DisplayPort Interface

DVI and HDMI connectors can both be implemented through the DisplayPort interface. Circuits required on the system board are as shown. 499Ω with 1% pulldown resistors to the ground on the DP lanes must placed on the DVI/HDMI connector side of the AC coupling, gated by a MOSFET to limit leakage.

![3.3V 3.3V\nHot Plug Detect\nMXM Connector\nAUX P/DDC_CLK\nAUX N/DDC_DAT\nLevel Shifter\nDVI/HDMI Connector\nDP_x_Lx_P\nDP_x_Lx_N\n499Ω 1%\n499Ω 1%\nPWR_EN](.mxm-p1000-50-1z297-1000-10/4e5cde0feb632eb7ac0da21496f4c95a9cabb69174403bff6fe420fe408d7e97.jpg)

Figure 2-5: DVI/HDMI on DisplayPort Interface

# 2.6 Driver Installation

Drivers can be downloaded from https://www.nvidia.com.tw/Download/index.aspx?lang=tw

# 2.7 Certifications & Agencies

▶ Windows Hardware Quality Lab (WHQL) certified Windows 7, and Windows 10
▶ EU Reduction of Hazardous Substances (EU-RoHS)
▶ Conformité Européenne (CE)
▶ Federal Communications Commission (FCC)

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing (See “Getting Started” on page 33.):

▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power

▶ To avoid electrical shock and/or damage to device:

▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▶ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
▶ A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image shows a yellow triangular warning sign with a black border containing a large black exclamation point. Below the triangle, the text 'CAUTION:' appears in black capital letters.](.mxm-p1000-50-1z297-1000-10/410f20efeed63d8eca2c84a2305aa8c491bef966fc1e704edaadd111876eae56.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d'explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up

It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required

▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.mxm-p1000-50-1z297-1000-10/8b9b7f415d85ac2ae91f8458e75531041f4d3ba08acae67ed59d089b0e13691d.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

This page intentionally left blank.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you:
[🔗 Link to the original document](.mxm-p1000-50-1z297-1000-10/mxm-p1000-50-1z297-1000-10.pdf)