# nanoX-AL User’s Manual

COM Express Mini Size Type 10 Module with Intel Atom®, Pentium®, Celeron® SoC

![Close-up of a green printed circuit board with integrated circuits and connectors (no visible text or symbols)](.nanox-al-50-1j088-1030-13/7ea4a161413216483ad2630d422e98b957f9005f9f3abe894e34016effd6d3c2.jpg)

![COM\nExpress®](.nanox-al-50-1j088-1030-13/0ecba788397b1f417b63965571808e8db2d96265ac235a2838410ff70ab30cc4.jpg)

Manual Rev.: 1.3

Revision Date: July 16, 2020

Part Number: 50-1J088-1030

# Preface

# Copyright

Copyright © 2018-2020 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.nanox-al-50-1j088-1030-13/4efe474a90d52a38597cc33a4cf15ad049e0035ecb3fe07b2db651a2dfd7ffae.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin with crossed lines indicating no waste or prohibition (no text or symbols)](.nanox-al-50-1j088-1030-13/ed915a15a5d6c2c86cbd47e8c040412206c218c61c6319ce3d08b38b09de339f.jpg)

![Li-ion](.nanox-al-50-1j088-1030-13/e2dcd07ad03ff4611201700978247bc10e12090a1347f839491414d76b8d6a21.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.nanox-al-50-1j088-1030-13/814fb331c3efc0da6ef6d018c8c6bfc8f25cd3eb770852551a309bbb94d77914.jpg)

![廢電池請回收](.nanox-al-50-1j088-1030-13/33a0be7a7639581e815ae293400c104fe83bc4ba9f98c0e500b5140f631341f0.jpg)

# California Proposition 65 Warning

![A yellow triangular warning sign with a black border containing a black exclamation point in the center.](.nanox-al-50-1j088-1030-13/2e4ec830d14acd7dd7f020e692c26aa672d8cd6d7c5d46632cfb6af3cafa4e0c.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2018-04-02</td><td>JC</td></tr><tr><td>1.1</td><td>Correct LVDS specification</td><td>2019-11-18</td><td>JC</td></tr><tr><td>1.2</td><td>Update dual BIOS to “build option”; update Ethernet controller temperature support</td><td>2019-12-06</td><td>JC</td></tr><tr><td>1.3</td><td>Correct GBE0_MDIO- pin number</td><td>2020-07-16</td><td>JC</td></tr></table>

# Table of Contents

Preface ...

List of Figures ....... .....vii

List of Tables ...... ....viii

1. Introduction...........

2. Specifications ....

2.1. Core System.. 3

2.2. Expansion Busses . . 3

2.3. Video... . 4

2.4. Audio... 4

2.5. LAN.. . 4

2.6. Multi I/O and Storage. .4

2.7. Serial I/O on Module .. 5

2.8. Trusted Platform Module (TPM) . 5

2.9. SEMA Board Controller .. .5

2.10. Debug... . 6

2.11. Power Specifications . .6

2.12. Power Consumption . .6

2.13. Operating Temperatures . .6

2.14. Environmental . .6

2.15. Specification Compliance ..... .6

2.16. Operating Systems. 7

2.17. Functional Diagram . .8

2.18. Mechanical Drawing .. .9

3. Pinouts and Signal Descriptions.... .11

3.1. AB/CD Pin Definitions.. .11

3.2. Signal Description Terminology.. .. 14

3.3. AB Signal Descriptions . . 15

3.3.1. Audio Signals .. . 15

3.3.2. LVDS/eDP.. . 15

3.3.3. DDI0 Channel . . 16

3.3.4. Gigabit Ethernet .. . 16

3.3.5. SATA.. 17

3.3.6. PCI Express . 17

3.3.7. Express Card (Not supported) . . 18

3.3.8. LPC Bus.. . 18

3.3.9. USB 1.1/2.0... . 18
3.3.10. USB 3.0 Extension.. . 19
3.3.11. USB Root Segmentation.. . 20
3.3.12. SPI (BIOS only) .. . 21
3.3.13. Miscellaneous ... . 21
3.3.14. SMBus.... 22
3.3.15. I2C Bus . . 22
3.3.16. General Purpose I/O (GPIO).. 22
3.3.17. Serial Interface Signals. . 23
3.3.18. Power And System Management . . 23
3.3.19. Power and Ground.. . 24

# 4. Module Interfaces ... .25

4.1. Connector, Switch and LED Locations .. .25
4.2. 40-pin Debug Connector.. .. 26
4.3. Status LEDs.. . 28
4.4. MIPI60 Debug Header (build option) .. . 29
4.5. Switch Settings . . 30

# 5. Smart Embedded Management Agent (SEMA) ....... ..31

5.1. Board Specific SEMA Functions.. .. 32

5.1.1. Voltages . . 32
5.1.2. Main Current .. . 32
5.1.3. BMC Status... . 32
5.1.4. Exception Codes. . 33
5.1.5. BMC Flags . 33

# 6. System Resources .... .35

6.1. System Memory Map. . 35
6.2. I/O Map .. . 35
6.3. Interrupt Request (IRQ) Lines.. .37
6.4. PCI Configuration Space Map . ..40
6.5. PCI Interrupt Routing Map. ..41
6.6. SMBus Address Table.. .. 42

# 7. BIOS Setup.................. .43

7.1. Menu Structure . .. 43
7.2. Main. . 44

7.2.1. Main > BIOS Information .. . 44
7.2.2. Main > System Information ... . 44
7.2.3. Main > Board Information . . 45
7.2.4. Main >System Date/Time . . 45

7.2.5. Main >Access Level. . 45

# 7.3. Advanced.. .. 46

7.3.1. Advanced > CPU Configuration.. .. 46

7.3.2. Advanced > Graphics Configuration.. . 48

7.3.3. Advanced > Power Management. . 49

7.3.4. Advanced > System Management.. . 50

7.3.5. Advanced > Thermal Management.. . 50

7.3.6. Advanced > Watchdog Timer .. . 51

7.3.7. Advanced > CSM Configuration . . 51

7.3.8. Advanced > Super IO Configuration.. . 51

7.3.9. Advanced > Serial Console Redirection .... . 53

7.3.10. Advanced > USB.. . 55

7.3.11. Advanced > Network. . 56

7.3.12. Advanced > Miscellaneous .. . 56

7.3.13. Advanced > Driver Health. . 56

7.3.14. Advanced > Trusted Computing .. . 56

7.3.15. Advanced > Trusted Computing .. . 57

# 7.4. Chipset... .. 58

7.4.1. Chipset > North Bridge .. . 58

7.4.2. Chipset > South Bridge.. . 58

7.4.3. Chipset > Uncore Configuration.. . 58

7.4.4. Chipset > South Cluster Configuration . .. 60

# 7.5. Security.. .. 69

7.5.1. Security > Password Description . . 69

# 7.6. Boot .. .. 70

7.6.1. Boot > Boot Configuration. . 70

7.6.2. Boot > FIXED BOOT ORDER Priorities. .. 70

# 7.7. Save & Exit . .. 71

# 8. BIOS Checkpoints, Beep Codes..... .73

8.1. Status Code Ranges. .. 74

8.2. Standard Status Codes.. .. 74

8.2.1. SEC Phase.. . 74

8.2.2. SEC Beep Codes... . 75

8.2.3. PEI Phase .. . 75

8.2.4. PEI Beep Codes . . 77

8.2.5. DXE Status Codes . . 78

8.2.6. DXE Beep Codes.. . 80

8.2.7. ACPI/ASL Checkpoint. . 80

# 8.3. OEM-Reserved Checkpoint Ranges.. ..81

# 9. Mechanical Information............... .83

9.1. Board-to-Board Connectors.. . 83
9.2. Thermal Solution.. . 84
9.2.1. Heat Spreaders.. . 84
9.2.2. Heat Sinks.. . 84
9.2.3. Installation .. . 84
9.3. Mounting Methods . . 86
9.4. Standoff Types.. . 87

# Safety Instructions................ ...88

# Getting Service..... .89

# List of Figures

Figure 1: nanoX-AL Functional Block Diagram . .8
Figure 2: nanoX-AL Mechanical Drawing.. 9
Figure 3: nanoX-AL Connector, Switch and LED Locations . . 25
Figure 4: nanoX-AL and the DB40 Debug Module.. . 25
Figure 5: cExpress Switch Locations . .. 30
Figure 6: COM Express Mounting Methods . .. 86
Figure 7: COM Express Standoff Types.. .. 87

# List of Tables

Table 1: nanoX-AL Type 10 COM.0 Rev. 3.0 Pin Definitions .. . 11
Table 2: 40-pin Debug Connector Pin Definition.. .. 27
Table 3: nanoX-AL LED Descriptions... . 28
Table 4: MIPI60 Debug Header Pin Definition . .. 29
Table 5: BIOS Select and Mode Configuration Switch Settings.. .. 30
Table 6: SEMA Onboard Voltage Monitor.. .. 32
Table 7: SEMA BMC Status .. .. 32
Table 8: SEMA Exception Codes .. .. 33
Table 9: SEMA BMC Flags... .. 33

# 1. Introduction

The nanoX-AL is a COM Express® COM.0 R3.0 Type 10 module supporting Intel Atom® processor E3900 series system-on-chip (SoC). The nanoX-AL is specifically designed for customers who need optmized processing and graphics performance with low power consumption in a long product life solution.

The nanoX-AL features the dual/quad core Intel Atom® processor E3900 series supporting non-ECC type DDR3L single-channel or dual-channel memory at 1600/1867 MHz to provide excellent overall performance. Integrated Intel® Gen9 LP Graphics includes features such as OpenGL 4.3, DirectX 12, OpenCL 2.0 and support for H.265/HEVC, H.264, MPEG2, VC1, VP9, MVC, JPEG/MJPEG hardware decode. Graphics outputs include DDI ports supporting HDMI/DVI/DisplayPort and single-channel 18/24-bit LVDS (eDP by build option). The nanoX-AL is specifically designed for customers with balanced performance and power consumption requirements who want to outsource the custom core logic of their systems for reduced development time.

The nanoX-AL has 2GB of soldered type non-ECC DDR3L memory (4GB and 8GB optional). In addition, onboard eMMC memory (8GB/16GB/32GB) and SD signals are available as build options.

The nanoX-AL features a single onboard Gigabit Ethernet port, multiple PCIe lanes, USB 3.0 ports and USB 2.0 ports, and SATA 6 Gb/s ports. Support is provided for SMBus and I2 C. The module is equipped with SPI AMI EFI BIOS (dual BIOS by build option), supporting embedded features such as remote console, CMOS backup, hardware monitor, and watchdog timer.

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# 2. Specifications

# 2.1. Core System

<table><tr><td>CPU</td><td>Dual or quad-core Intel Atom® processor E3900 SoCIntel Atom® E3950 1.6/2.0GHz (Burst), 400-650MHz (Graphics) 12W (4C/1866)Intel Atom® E3940 1.6/1.8GHz (Burst), 400-600MHz (Graphics) 9W (4C/1866)Intel Atom® E3930 1.3/1.8GHz (Burst), 400-550MHz (Graphics) 6W (2C/1866)Pentium® N4200 1.1/2.5GHz (Turbo), 200-750MHz (graphics), 6W (4C/1866)Celeron® N3350 1.1/2.4GHz (Turbo), 200-650MHz (graphics), 6W (2C/1866)Supports dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x, Intel® VT-d, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture, Intel® Turbo Boost Technology 2.0, Intel AES-NI, Intel® TXT, PCLMULQDQ instruction DRNGNotes:Availability of features may vary between processor SKUs and operating systems; N4200/M3350 by project basis.</td></tr><tr><td>L3 Cache</td><td>2MB for all SKUs</td></tr><tr><td>Memory</td><td>Single channel or dual channel non-ECC 1600/1866 MHz soldered DDR3L memory up to 8GB (4GB and 8GB supported by build option)Notes:2GB and 4GB are 1866MHz and 8GB is 1600MHz (or 1866MHz, by project basis).Availability of features may vary between processor SKUs.2GB is single channel and 4GB/8GB are dual channel.</td></tr><tr><td>BIOS</td><td>AMI EFI with CMOS backup in 16MB SPI BIOS</td></tr></table>

# 2.2. Expansion Busses

<table><tr><td>PCI Express</td><td>Multiple PCI Express x1 Gen2 (AB):Lanes 0/1/2/4, configurable to 3 x1 (default); 2 x1+1 x2 or 1 x4 (by request)Recommend up to three devices only.</td></tr><tr><td>Other</td><td>LPC busSMBus (system) $I^{2}C$  (user)</td></tr></table>

# 2.3. Video

<table><tr><td>Integrated on SoC</td><td>Intel® Generation 9 Low Power Graphics core architecture with up to 18 execution units supporting two independent displays</td></tr><tr><td>GPU Feature Support</td><td>3D graphics hardware accelerationSupport for DirectX12/11.3/10/9.3, OCL 2.0, OGL ES 3.0, OGL 4.3Video decode hardware acceleration including support for H.265 (HEVC), H.264, MVC, MPEG-2, VC-1, WMV9, VP8/VP9, JPEG/MJPEG formatsVideo encode hardware acceleration including support for H.265 (HEVC), H.264, VP8/VP9, JPEG/MJPEG formatsSupports content protection using PAVP 2.0 and HDCP 1.4/2.0Note:Availability of features may vary between operating systems.</td></tr><tr><td>Display Types</td><td>Single channel 18/24-bit LVDS:supports DE mode and H/V-Sync mode display, resolution up to 1920x1200 with single channel LVDS.eDP x4 lanes (eDP 1.3, by build option in place of LVDS)DDIO:Supports DisplayPort, HDMI, DVI</td></tr></table>

# 2.4. Audio

<table><tr><td>Integrated</td><td>Intel® HD Audio integrated on SoC</td></tr><tr><td>Codec</td><td>Located on carrier miniBASE-10R (ALC262 standard support)</td></tr></table>

# 2.5. LAN

<table><tr><td>Intel MAC/PHY</td><td>Intel® Ethernet Controller I210 (Extreme Rugged operating temperature range)Intel® Ethernet Controller I211 (standard operating temperature range)Supports GbE0_SDP, IEEE 1588 for real-time applications</td></tr><tr><td>Interface</td><td>10/100/1000 Mbit/s connection</td></tr></table>

# 2.6. Multi I/O and Storage

<table><tr><td>I/O Hub</td><td>Integrated on SoC</td></tr><tr><td>USB</td><td>2x USB. 3.0/2.0/1.1 (USB 0/1)6x USB. 2.0/1.1 (USB 2/3/4/5/6/7)Note: USB port 7 supports USB 2.0 OTG on Yocto Linux OS, detection pin is B96. Does not comply with PICMG R3.0 USB OTG support order (port 0, then port 7) due to design prior to finalization of specification.</td></tr><tr><td>SATA</td><td>2x ports SATA 6Gb/s (SATA0, SATA1)</td></tr><tr><td>eMMC 5.0 (build option)</td><td>8/16/32 GB (boot device support may vary between operating systems)*</td></tr><tr><td>SD (build option)</td><td>SD 3.0 signal is muxed with GPIO, switching through BOM option (boot device support may vary between operating systems)Note: Supports 3.30V SD cards only.</td></tr><tr><td>GPIO</td><td>4 GPO and 4 GPINote: GPI with interrupt supported on Linux.</td></tr></table>

\*Note: See table below for detailed boot device support information.

Boot Device Support

<table><tr><td colspan="2"></td><td>Windows 10 Enterprise</td><td>Linux (Yocto)</td></tr><tr><td rowspan="2">Storage only</td><td>eMMC 5.0</td><td>Yes</td><td>Yes</td></tr><tr><td>SD</td><td>Yes</td><td>Yes</td></tr><tr><td rowspan="2">OS Installation</td><td>eMMC 5.0</td><td>Yes</td><td>Yes</td></tr><tr><td>SD</td><td>No</td><td>No</td></tr></table>

Note: eMMC and SD functionality as an OS installation device may change dependent on Intel updates. Please contact your local sales representative for more information.

# 2.7. Serial I/O on Module

z Ports: 2x UART ports COM 1/2, baud rate up to 115.2k bps
Console Redirection: selectable in BIOS, supported during BIOS POST

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via NCT5104D</td><td>10</td><td>0x240</td><td>Yes</td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via NCT5104D</td><td>11</td><td>0x248</td><td>Yes</td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>4</td><td>0x3F8</td><td>Yes</td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>3</td><td>0x2F8</td><td>Yes</td></tr></table>

# 2.8. Trusted Platform Module (TPM)

Chipset: Infineon
Type: TPM 2.0

Note: TPM supported by build option.

# 2.9. SEMA Board Controller

Type: ADLINK Smart Embedded Management Agent (SEMA)
Functions:

• Voltage/Current monitoring
• Power sequence debug support
AT/ATX mode control
Logistics and forensic information
Flat panel control
• General purpose I2C
• Failsafe BIOS (dual BIOS by build option)
Watchdog timer and fan control

# 2.10. Debug

40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
MIPI60 60-pin header for debug of SoC (build option)

2.11. Power Specifications

<table><tr><td>Power Modes</td><td>AT and ATX mode (AT mode startup controlled by SEMA Board Controller)</td></tr><tr><td>Standard Voltage Input</td><td>ATX: 12V ±5% / 5Vsb ±5% or AT = 12V ±5%</td></tr><tr><td>Wide Voltage Input</td><td>ATX: 4.75-20V, 5Vsb ±5%; AT: 4.75-20V</td></tr><tr><td>Power Management</td><td>ACPI 5.0 compliant, Smart Battery support</td></tr><tr><td>Power States</td><td>Supports C0, C1, C1E, C6L, C6, S0, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)</td></tr><tr><td>ECO Mode</td><td>Supports deep S5 for 5Vsb power saving</td></tr></table>

# 2.12. Power Consumption

Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.

2.13. Operating Temperatures

<table><tr><td>Standard Operating Temperature</td><td>0°C to +60°C (wide voltage input)Storage: -20°C to +70°C</td></tr><tr><td>Extreme Rugged Operating Temperature (optional)</td><td>-40°C to +85°C (standard voltage input only, build option, Intel Atom® SKUs only)Storage: -40°C to +85°C</td></tr></table>

2.14. Environmental

<table><tr><td>Humidity</td><td>Operating: 5-90% RH, non-condensingStorage: 5-95% RH (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr></table>

# 2.15. Specification Compliance

PICMG COM.0: Rev 3.0 Type 10, Mini size 84 x 55 mm

# 2.16. Operating Systems

<table><tr><td>Standard Support</td><td>Windows 10 (64-bit)Linux (64-bit)VxWorks (64-bit)</td></tr><tr><td>Extended Support (BSP)</td><td>Linux (64-bit)VxWorks (64-bit)</td></tr></table>

2.17. Functional Diagram
![The diagram illustrates the connectivity of the **Intel Atom® Processor E3900** (central block) with various peripherals and interface blocks.\n\n**Central Processor and Memory:**\n*   **Intel Atom® Processor E3900** is the central block.\n*   **Soldered 2/4/8 GB DDR3L non-ECC** connects to the processor via a double-headed arrow.\n\n**Left Side (Interface 'AB'):**\nThis column represents an interface or connector labeled **AB**. Connections include:\n*   **LVDS eDP to LVDS**: Connected via **eDP** from the processor. A dashed line labeled **eDP x4 lanes (build option)** also connects to it. Output is labeled **Single channel 18/24-bit**.\n*   **DDIO 4 lanes**: Connected to the processor.\n*   **8x USB 2.0/1.1 (port 0-7) (port 7 supports host and client mode)**: Connected via double-headed arrow.\n*   **2x USB 3.0 (port 0-1)**: Connected via double-headed arrow.\n*   **4x PCIe x1 Gen2 (port 0-3) Supports x1, x2, x4 (3 devices only)**: Connected via double-headed arrow.\n*   **GbE i210**: Connected via **PCIe x1 Gen2** from the processor. Output is labeled **GBE0_SDP**.\n*   **2x SATA 6Gb/s (port 0/1)**: Connected via double-headed arrow.\n*   **HD Audio**: Connected via double-headed arrow.\n*   **2 UART (Tx/Rx)**: Connected via dashed line labeled **HSUART** from the processor.\n*   **TPM 2.0 (build option)** and **Super I/O LPC to UART**: Connected to each other and linked to the AB column via **LPC Bus**.\n*   **SMBus**: Connected to the processor.\n*   **GPIO PCA9535**: Connected to **4x GP0, 4x GPI (SDIO)**.\n*   **GP I2C** and **DDC I2C**: Dashed lines connecting GPIO/AB area.\n*   **SPI_CS#** and **SPI**: Lines connecting to the bottom right block.\n\n**Right Side:**\n*   **MIPI60 60-pin**: Dashed box labeled **On break-out board by build option**. Connected via dashed arrow.\n*   **eMMC 5.0 8/16/32GB (build option)**: Dashed box. Connected via dashed arrow.\n\n**Bottom Right (Management and Boot):**\n*   **SEMA BMC**: Connected to **SD** and **I2C** (dashed) pins from the processor. Connected to **SPI_CS#** and **SPI** lines.\n*   **SPI0 BIOS**: Connected to SEMA BMC via double-headed arrow.\n*   **SPI1 BIOS**: Dashed box connected to SEMA BMC via dashed arrow.\n*   **LM73**: Connected to SEMA BMC.](.nanox-al-50-1j088-1030-13/5e6a8d2697b4796a5938c59fa66fa45c9734a52054797250ad2a7c1881909fb8.jpg)

Figure 1: nanoX-AL Functional Block Diagram

# 2.18. Mechanical Drawing

![This image is a technical drawing containing a 'Top View' and a 'Side View' of a mechanical component.\n\n**Top View:**\n*   **Labels:** The text 'Top View' appears on the left.\n*   **Left Annotations:** Stacked numbers read '55', '51', and '49'. Below these, vertical dimension markers read '4' and '0'.\n*   **Bottom Dimensions:** A series of numbers along the bottom edge reads '0', '4', '9.8', '67.5', '80', and '84'.\n*   **Right Annotations:** Diameter symbols followed by numbers read 'Ø6' and 'Ø2.7'.\n*   **Visuals:** The drawing shows a large rectangle with four circular mounting holes (two at the top, two at the bottom) and a long, detailed rectangular connector assembly running along the top edge.\n\n**Side View:**\n*   **Labels:** The text 'Side View' appears on the left.\n*   **Dimension:** The number '2' is shown with arrows indicating a measurement.\n*   **Visuals:** A thin horizontal profile is shown with the connector teeth visible underneath.](.nanox-al-50-1j088-1030-13/912c305f7d184edd4a1732a64b20360411b4d4a7c17849f8e0a183555cc9a4eb.jpg)
All are dimensions shown in millimeters.
Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances of the module connector locating peg holes (dimensions [9.8, 49]) should be ±0.10mm.

Figure 2: nanoX-AL Mechanical Drawing

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# 3. Pinouts and Signal Descriptions

# 3.1. AB/CD Pin Definitions

The nanoX-AL is a Type 10 module supporting USB 3.0 and DDI channel on the AB connector. All standard pins of the COM Express specification are described in the table below, including those not supported on the nanoX-AL.

Note: Signals not supported on the nanoX-AL module are crossed out.

Table 1: nanoX-AL Type 10 COM.0 Rev. 3.0 Pin Definitions

<table><tr><td colspan="2">Row A</td><td colspan="2">Row B</td></tr><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td></tr><tr><td>1</td><td>GND(FIXED)</td><td>1</td><td>GND(FIXED)</td></tr><tr><td>2</td><td>GBEO_MDI3-</td><td>2</td><td>GBEO_ACT#</td></tr><tr><td>3</td><td>GBEO_MDI3+</td><td>3</td><td>LPC_FRAME# /ESPI_CS0#</td></tr><tr><td>4</td><td>GBEO_LINK100#</td><td>4</td><td>LPC_ADO /ESPI_IO_0</td></tr><tr><td>5</td><td>GBEO_LINK1000#</td><td>5</td><td>LPC_AD1 /ESPI_IO_1</td></tr><tr><td>6</td><td>GBEO_MDI2-</td><td>6</td><td>LPC_AD2 /ESPI_IO_2</td></tr><tr><td>7</td><td>GBEO_MDI2+</td><td>7</td><td>LPC_AD3 /ESPI_IO_3</td></tr><tr><td>8</td><td>GBEO_LINK#</td><td>8</td><td>LPC_DRQ0# /ESPI_ALERT0#</td></tr><tr><td>9</td><td>GBEO_MDI1-</td><td>9</td><td>LPC_DRQ1# /ESPI_ALERT_1#</td></tr><tr><td>10</td><td>GBEO_MDI1+</td><td>10</td><td>LPC_CLK /ESPI_CK</td></tr><tr><td>11</td><td>GND(FIXED)</td><td>11</td><td>GND(FIXED)</td></tr><tr><td>12</td><td>GBEO_MDIO-</td><td>12</td><td>PWRBTN#</td></tr><tr><td>13</td><td>GBEO_MDIO+</td><td>13</td><td>SMB_CK</td></tr><tr><td>14</td><td>GBEO_CTREF</td><td>14</td><td>SMB_DAT</td></tr><tr><td>15</td><td>SUS_S3#</td><td>15</td><td>SMB_ALERT#</td></tr><tr><td>16</td><td>SATAO_TX+</td><td>16</td><td>SATA1_TX+</td></tr><tr><td>17</td><td>SATAO_TX-</td><td>17</td><td>SATA1_TX-</td></tr><tr><td>18</td><td>SUS_S4#</td><td>18</td><td>SUS_STAT# /ESPI_RESET#</td></tr><tr><td>19</td><td>SATAO_RX+</td><td>19</td><td>SATA1_RX+</td></tr><tr><td>20</td><td>SATAO_RX-</td><td>20</td><td>SATA1_RX-</td></tr><tr><td>21</td><td>GND(FIXED)</td><td>21</td><td>GND(FIXED)</td></tr><tr><td>22</td><td>USB_SSRX0-</td><td>22</td><td>USB_SSTX0-</td></tr><tr><td>23</td><td>USB_SSRX0+</td><td>23</td><td>USB_SSTX0+</td></tr><tr><td>24</td><td>SUS_S5#</td><td>24</td><td>PWR_OK</td></tr><tr><td>25</td><td>USB_SSRX1-</td><td>25</td><td>USB_SSTX1-</td></tr><tr><td>26</td><td>USB_SSRX1+</td><td>26</td><td>USB_SSTX1+</td></tr><tr><td>27</td><td>BATLOW#</td><td>27</td><td>WDT</td></tr><tr><td>28</td><td>(S)ATA_ACT#</td><td>28</td><td>HDA_SDIN2</td></tr><tr><td>29</td><td>HDA_SYNC</td><td>29</td><td>HDA_SDIN1</td></tr><tr><td>30</td><td>HDA_RST#</td><td>30</td><td>HDA_SDINO</td></tr><tr><td>31</td><td>GND(FIXED)</td><td>31</td><td>GND(FIXED)</td></tr><tr><td>32</td><td>HDA_BITCLK</td><td>32</td><td>SPKR</td></tr><tr><td>33</td><td>HDA_SDOUT</td><td>33</td><td>I2C_CK</td></tr><tr><td>34</td><td>BIOS_DISO# /ESPI_SAFS</td><td>34</td><td>I2C_DAT</td></tr><tr><td>35</td><td>THRMTRIP#</td><td>35</td><td>THRM#</td></tr></table>

Row A
Row B

<table><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td></tr><tr><td>36</td><td>USB6-</td><td>36</td><td>USB7-</td></tr><tr><td>37</td><td>USB6+</td><td>37</td><td>USB7+</td></tr><tr><td>38</td><td>USB_6_7_OC#</td><td>38</td><td>USB_4_5_OC#</td></tr><tr><td>39</td><td>USB4-</td><td>39</td><td>USB5-</td></tr><tr><td>40</td><td>USB4+</td><td>40</td><td>USB5+</td></tr><tr><td>41</td><td>GND(FIXED)</td><td>41</td><td>GND(FIXED)</td></tr><tr><td>42</td><td>USB2-</td><td>42</td><td>USB3-</td></tr><tr><td>43</td><td>USB2+</td><td>43</td><td>USB3+</td></tr><tr><td>44</td><td>USB_2_3_OC#</td><td>44</td><td>USB_0_1_OC#</td></tr><tr><td>45</td><td>USB0-</td><td>45</td><td>USB1-</td></tr><tr><td>46</td><td>USB0+</td><td>46</td><td>USB1+</td></tr><tr><td>47</td><td>VCC_RTC</td><td>47</td><td>ESPI_EN</td></tr><tr><td>48</td><td>RSVD</td><td>48</td><td>USBO_HOST_PRSNT</td></tr><tr><td>49</td><td>GBEO_SDP</td><td>49</td><td>SYS_RESET#</td></tr><tr><td>50</td><td>LPC_SERIRQ/ESPI_CS1#</td><td>50</td><td>CB_RESET#</td></tr><tr><td>51</td><td>GND(FIXED)</td><td>51</td><td>GND(FIXED)</td></tr><tr><td>52</td><td>RSVD</td><td>52</td><td>RSVD</td></tr><tr><td>53</td><td>RSVD</td><td>53</td><td>RSVD</td></tr><tr><td>54</td><td>GPIO</td><td>54</td><td>GPO1</td></tr><tr><td>55</td><td>RSVD</td><td>55</td><td>RSVD</td></tr><tr><td>56</td><td>RSVD</td><td>56</td><td>RSVD</td></tr><tr><td>57</td><td>GND</td><td>57</td><td>GPO2</td></tr><tr><td>58</td><td>PCIE_TX3+</td><td>58</td><td>PCIE_RX3+</td></tr><tr><td>59</td><td>PCIE_TX3-</td><td>59</td><td>PCIE_RX3-</td></tr><tr><td>60</td><td>GND(FIXED)</td><td>60</td><td>GND(FIXED)</td></tr><tr><td>61</td><td>PCIE_TX2+</td><td>61</td><td>PCIE_RX2+</td></tr><tr><td>62</td><td>PCIE_TX2-</td><td>62</td><td>PCIE_RX2-</td></tr><tr><td>63</td><td>GPI1</td><td>63</td><td>GPO3</td></tr><tr><td>64</td><td>PCIE_TX1+</td><td>64</td><td>PCIE_RX1+</td></tr><tr><td>65</td><td>PCIE_TX1-</td><td>65</td><td>PCIE_RX1-</td></tr><tr><td>66</td><td>GND</td><td>66</td><td>WAKE0#</td></tr><tr><td>67</td><td>GPI2</td><td>67</td><td>WAKE1#</td></tr><tr><td>68</td><td>PCIE_TX0+</td><td>68</td><td>PCIE_RX0+</td></tr><tr><td>69</td><td>PCIE_TX0-</td><td>69</td><td>PCIE_RX0-</td></tr><tr><td>70</td><td>GND(FIXED)</td><td>70</td><td>GND(FIXED)</td></tr><tr><td>71</td><td>LVDS_A0+/eDP_TX2+</td><td>71</td><td>DDIO_PAIR0+</td></tr><tr><td>72</td><td>LVDS_A0-/eDP_TX2-</td><td>72</td><td>DDIO_PAIR0-</td></tr><tr><td>73</td><td>LVDS_A1+/eDP_TX1+</td><td>73</td><td>DDIO_PAIR1+</td></tr><tr><td>74</td><td>LVDS_A1-/eDP_TX1-</td><td>74</td><td>DDIO_PAIR1-</td></tr><tr><td>75</td><td>LVDS_A2+/eDP_TX0+</td><td>75</td><td>DDIO_PAIR2+</td></tr><tr><td>76</td><td>LVDS_A2-/eDP_TX0-</td><td>76</td><td>DDIO_PAIR2-</td></tr><tr><td>77</td><td>LVDS_/eDP_VDD_EN</td><td>77</td><td>DDIO_PAIR4+</td></tr><tr><td>78</td><td>LVDS_A3+</td><td>78</td><td>DDIO_PAIR4-</td></tr><tr><td>79</td><td>LVDS_A3-</td><td>79</td><td>LVDS_/eDP_BKLT_EN</td></tr><tr><td>80</td><td>GND(FIXED)</td><td>80</td><td>GND(FIXED)</td></tr></table>

Row A
Row B

<table><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td></tr><tr><td>81</td><td>LVDS_A_CK+/ eDP_TX3+</td><td>81</td><td>DDIO_PAIR3+</td></tr><tr><td>82</td><td>LVDS_A_CK-/ eDP_TX3-</td><td>82</td><td>DDIO_PAIR3-</td></tr><tr><td>83</td><td>LVDS_I2C_CK/ eDP_AUX+</td><td>83</td><td>LVDS_BKLT_CTRL/eDP_BKLT_CTRL</td></tr><tr><td>84</td><td>LVDS_I2C_DAT/ eDP_AUX-</td><td>84</td><td>VCC_5V_SBY</td></tr><tr><td>85</td><td>GPI3</td><td>85</td><td>VCC_5V_SBY</td></tr><tr><td>86</td><td>RSVD</td><td>86</td><td>VCC_5V_SBY</td></tr><tr><td>87</td><td>eDP_HPD</td><td>87</td><td>VCC_5V_SBY</td></tr><tr><td>88</td><td>PCIE_CLK_REF+</td><td>88</td><td>BIOS_DIS1#</td></tr><tr><td>89</td><td>PCIE_CLK_REF-</td><td>89</td><td>DDIO_HPD</td></tr><tr><td>90</td><td>GND(FIXED)</td><td>90</td><td>GND(FIXED)</td></tr><tr><td>91</td><td>SPI_POWER</td><td>91</td><td>DDIO_PAIR5+</td></tr><tr><td>92</td><td>SPI_MISO</td><td>92</td><td>DDIO_PAIR5-</td></tr><tr><td>93</td><td>GPOO</td><td>93</td><td>DDIO_PAIR6+</td></tr><tr><td>94</td><td>SPI_CLK</td><td>94</td><td>DDIO_PAIR6-</td></tr><tr><td>95</td><td>SPI_MOSI</td><td>95</td><td>DDIO_DDC_AUX_SEL</td></tr><tr><td>96</td><td>TPM_PP</td><td>96</td><td>USB7_HOST_PRSNT</td></tr><tr><td>97</td><td>TYPE10#</td><td>97</td><td>SPI_CS#</td></tr><tr><td>98</td><td>SERO_TX</td><td>98</td><td>DDIO_CTRLCLK_AUX+</td></tr><tr><td>99</td><td>SERO_RX</td><td>99</td><td>DDIO_CTRLDATA_AUX-</td></tr><tr><td>100</td><td>GND(FIXED)</td><td>100</td><td>GND(FIXED)</td></tr><tr><td>101</td><td>SER1_TX</td><td>101</td><td>FAN_PWMOUT</td></tr><tr><td>102</td><td>SER1_RX</td><td>102</td><td>FAN_TACHIN</td></tr><tr><td>103</td><td>LID#</td><td>103</td><td>SLEEP#</td></tr><tr><td>104</td><td>VCC_12V</td><td>104</td><td>VCC_12V</td></tr><tr><td>105</td><td>VCC_12V</td><td>105</td><td>VCC_12V</td></tr><tr><td>106</td><td>VCC_12V</td><td>106</td><td>VCC_12V</td></tr><tr><td>107</td><td>VCC_12V</td><td>107</td><td>VCC_12V</td></tr><tr><td>108</td><td>VCC_12V</td><td>108</td><td>VCC_12V</td></tr><tr><td>109</td><td>VCC_12V</td><td>109</td><td>VCC_12V</td></tr><tr><td>110</td><td>GND(FIXED)</td><td>110</td><td>GND(FIXED)</td></tr></table>

# Notes:

LID# and SLEEP# signals are not natively supported on the SOC, they instead connect to GPIO pins simulating their behaviour.
eDP x4 lanes supported by build option.
SD signals are muxed with GPIO (supported by build option).
• No EXCD0\_PERST#, EXCD0\_CPPE#, EXCD1\_PERST#, EXCD1\_CPPE# support.

# 3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

<table><tr><td>I</td><td>Input to the Module</td></tr><tr><td>O</td><td>Output from the Module</td></tr><tr><td>I/O</td><td>Bi-directional input/output signal</td></tr><tr><td>OD</td><td>Open drain output</td></tr><tr><td>I 3.3V</td><td>Input 3.3V tolerant</td></tr><tr><td>I 5V</td><td>Input 5V tolerant</td></tr><tr><td>O 3.3V</td><td>Output 3.3V signal level</td></tr><tr><td>O 5V</td><td>Output 5V signal level</td></tr><tr><td>I/O 3.3V</td><td>Bi-directional signal 3.3V tolerant</td></tr><tr><td>I/O 5V</td><td>Bi-directional signal 5V tolerant</td></tr><tr><td>I/O 3.3Vsb</td><td>Input 3.3V tolerant active in standby state</td></tr><tr><td>P</td><td>Power Input/Output</td></tr><tr><td>REF</td><td>Reference voltage output that may be sourced from a module power plane.</td></tr><tr><td>PDS</td><td>Pull-down strap. This is an output pin on the module that is either tied to GND or not connected. The signal is used to indicate the PICMG module type to the Carrier Board.</td></tr><tr><td>PU</td><td>ADLINK implemented pull-up resistor on module</td></tr><tr><td>PD</td><td>ADLINK implemented pull-down resistor on module</td></tr></table>

# 3.3. AB Signal Descriptions

# 3.3.1. Audio Signals

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>HDA_RST#</td><td>A30</td><td>Reset output to CODEC, active low.</td><td>O 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the CODEC(s).</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external CODEC(s).</td><td>I/O 3.3V</td><td></td><td></td></tr><tr><td>HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the CODEC.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>HDA_SDIN[2:0]</td><td>B28- B30</td><td>Serial TDM data inputs from up to 3 CODECs.</td><td>I/O 3.3V</td><td></td><td>AC_SDIN0: supported AC_SDIN1: not supported AC_SDIN2: not supported</td></tr></table>

# 3.3.2. LVDS/eDP

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LVDS_A0+ / eDP_TX2+</td><td>A71</td><td rowspan="8">LVDS Channel A differential pairs</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="12">eDP by build option</td></tr><tr><td>LVDS_A0- / eDP_TX2-</td><td>A72</td></tr><tr><td>LVDS_A1+ / eDP_TX1+</td><td>A73</td></tr><tr><td>LVDS_A1- / eDP_TX1-</td><td>A74</td></tr><tr><td>LVDS_A2+ / eDP_TX0+</td><td>A75</td></tr><tr><td>LVDS_A2- / eDP_TX0+</td><td>A76</td></tr><tr><td>LVDS_A3+</td><td>A78</td></tr><tr><td>LVDS_A3-</td><td>A79</td></tr><tr><td>LVDS_A_CK+ / eDP_TX3+</td><td>A81</td><td rowspan="2">LVDS Channel A differential clock</td><td rowspan="2">O LVDS</td><td rowspan="2"></td></tr><tr><td>LVDS_A_CK- / eDP_TX3-</td><td>A82</td></tr><tr><td>LVDS_VDD_EN / eDP_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 10k</td></tr><tr><td>LVDS_BKLT_EN / eDP_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 10k</td></tr><tr><td>LVDS_BKLT_CTRL / eDP_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100k</td><td>eDP to LVDS requirement</td></tr><tr><td>LVDS_I2C_CK / eDP_AUX+</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>O 3.3V</td><td>PU 2k2 3.3V</td><td rowspan="3"></td></tr><tr><td>LVDS_I2C_DAT / eDP_AUX-</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O 3.3V</td><td>PU 2k2 3.3V</td></tr><tr><td>RSVD / eDP_HPD</td><td>A87</td><td>Digital Display Interface Hot-Plug Detect</td><td>I 3.3V</td><td>PD 100k</td></tr></table>

# 3.3.3. DDI0 Channel

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>DDI0_PAIR0+</td><td>B71</td><td rowspan="14">Digital Display Interface differential pairs</td><td rowspan="14">O PCIE</td><td rowspan="14"></td><td rowspan="14">Pair 4 to Pair 6 are not supported</td></tr><tr><td>DDI0_PAIR0-</td><td>B72</td></tr><tr><td>DDI0_PAIR1+</td><td>B73</td></tr><tr><td>DDI0_PAIR1-</td><td>B74</td></tr><tr><td>DDI0_PAIR2+</td><td>B75</td></tr><tr><td>DDI0_PAIR2-</td><td>B76</td></tr><tr><td>DDI0_PAIR3+</td><td>B81</td></tr><tr><td>DDI0_PAIR3-</td><td>B82</td></tr><tr><td>DDI0_PAIR4+</td><td>B77</td></tr><tr><td>DDI0_PAIR4-</td><td>B78</td></tr><tr><td>DDI0_PAIR5+</td><td>B91</td></tr><tr><td>DDI0_PAIR5-</td><td>B92</td></tr><tr><td>DDI0_PAIR6+</td><td>B93</td></tr><tr><td>DDI0_PAIR6-</td><td>B94</td></tr><tr><td>DDI0_HPD</td><td>B89</td><td>Digital Display Interface Hot-Plug Detect</td><td>I 3.3V</td><td>PD 100k</td><td></td></tr><tr><td rowspan="2">DDI0_CTRLCLK_AUX+</td><td rowspan="2">B98</td><td>IF DDI0_DDC_AUX_SEL is floating</td><td>I/O PCIe</td><td>PD 100k</td><td>DP1_AUX+AC coupled on Module</td></tr><tr><td>IF DDI0_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI1_CTRLCLK PU 10k 3.3V</td></tr><tr><td rowspan="2">DDI0_CTRLDATA_AUX-</td><td rowspan="2">B99</td><td>IF DDI0_DDC_AUX_SEL is floating</td><td>I/O PCIe</td><td>PU 100K 3.3V</td><td>DP1_AUX-AC coupled on Module</td></tr><tr><td>IF DDI0_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI1_CTRLDAT A PU 10k 3.3V</td></tr><tr><td>DDI0_DDC_AUX_SEL</td><td>B95</td><td>Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.</td><td>I/O OD 3.3V</td><td>PD 1M</td><td></td></tr></table>

# 3.3.4. Gigabit Ethernet

<table><tr><td>Gigabit Ethernet</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>GBE0_MDI0+GBE0_MDI0-GBE0_MDI1+GBE0_MDI1-GBE0_MDI2+GBE0_MDI2-GBE0_MDI3+GBE0_MDI3-</td><td>A13A12A10A9A7A6A3A2</td><td>Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following: $\underline{1000}$   $\underline{10010}$ MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td><td>I/OAnalog</td><td></td><td>Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td>Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td>Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK100#</td><td>A4</td><td>Gigabit Ethernet Controller 0 100Mbit/sec link indicator, activelow.</td><td>OD3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK1000#</td><td>A5</td><td>Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.</td><td>OD3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td>Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>GNDmin3.3Vmax</td><td></td><td>Not supported (NC pin)</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td>Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE 1588 support such as 1pps signal.</td><td>I/O3.3VSB</td><td></td><td></td></tr></table>

# 3.3.5. SATA

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10k 3.3V</td><td></td></tr></table>

# 3.3.6. PCI Express

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PCIE_TX0+ PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX0+ PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>PCIE_TX1+ PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX1+ PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>PCIE_TX2+ PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX2+ PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>PCIE_TX3+ PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX3+ PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O PCIE</td><td></td><td></td></tr></table>

3.3.7. Express Card (Not supported)

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>EXCD0_CPPE#</td><td>A49</td><td rowspan="2">PCI ExpressCard: PCI Express capable card request</td><td rowspan="2">I 3.3V</td><td rowspan="2">PU 10k 3.3V</td><td rowspan="2">Not supported</td></tr><tr><td>EXCD1_CPPE#</td><td>B48</td></tr><tr><td>EXCD0_PERST#</td><td>A48</td><td rowspan="2">PCI ExpressCard: reset</td><td rowspan="2">O 3.3V</td><td rowspan="2"></td><td rowspan="2">Not supported</td></tr><tr><td>EXCD1_PERST#</td><td>B47</td></tr></table>

3.3.8. LPC Bus

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LPC_AD[0:3]</td><td>B4-B7</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3V</td><td></td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>LPC_DRQ0#LPC_DRQ1#</td><td>B8B9</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>NC.No support on Apollo Lake platform</td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O OD 3.3V</td><td>PU 8k2 3.3V</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output - 33MHz nominal</td><td>O 3.3V</td><td></td><td>The LPC_CLK frequency is 25M</td></tr></table>

Note: USB port 7 can support USB Client (may vary between operating systems).
3.3.9. USB 1.1/2.0

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 2</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 3</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 4</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 5</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 6</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 7</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_HOST_PRSNT</td><td>B96</td><td>Module USB client may detect the presence of a USB host. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on themodule. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low..</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>USB7_HOST_PRSNT</td><td>B96</td><td>Module USB client may detect the presence of a USB host on USB7. A high value indicates that a host is present</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr></table>

3.3.10. USB 3.0 Extension

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>A22A23</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIE</td><td></td><td></td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>B22B23</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>A25A26</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIE</td><td></td><td></td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>B25B26</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr></table>

# 3.3.11. USB Root Segmentation

![**Overview**\nThe diagram is a block diagram divided into three main sections: a 'SoC' (System on Chip) section on the left, a central section listing port configurations, and a 'Row AB' section on the right.\n\n**Labeled Blocks**\n\n*   **SoC Section:**\n    *   **Headers:** 'SoC', 'xHCI Engine', 'PHY'\n    *   **xHCI Engine Column (14 blocks):** Alternating blocks labeled 'USB 2.0' (white background) and 'USB 3.0' (yellow background).\n    *   **PHY Column (14 blocks):** Adjacent to the engine column.\n        *   Blocks labeled 'USB 2.0 PHY' (white background).\n        *   Blocks labeled 'USB 3.0 PHY' (yellow background). Several of these have a cross symbol next to them (rows 4, 6, 10, and 14).\n\n*   **Central Section (Port Blocks):**\n    *   'USB 2.0 Port 7'\n    *   'USB 2.0 Port 6'\n    *   'USB 2.0 Port 5'\n    *   'USB 2.0 Port 4'\n    *   'USB 3.0/2.0 Port 3'\n    *   'USB 2.0 Port 2'\n    *   'USB 3.0/2.0 Port 1'\n    *   'USB 2.0 Port 0 (Host/Device Mode)'\n\n*   **Right Section (Row AB):**\n    *   **Header:** 'Row AB' (vertical text)\n    *   **Top Blocks:** 'USB 3.0 Upgrade Port 1', 'USB 3.0 Upgrade Port 0'\n    *   **Port Blocks (10 blocks):**\n        *   'USB 2.0 Port 7 (Host/Device)'\n        *   'USB 2.0 Port 6'\n        *   'USB 2.0 Port 5'\n        *   'USB 2.0 Port 4'\n        *   'USB 2.0 Port 3'\n        *   'USB 2.0 Port 2'\n        *   'USB 2.0 Port 1'\n        *   'USB 2.0 Port 0'\n\n**Connections**\n\n*   **Internal SoC Connections:** Each block in the 'xHCI Engine' column is connected horizontally to its adjacent block in the 'PHY' column.\n*   **SoC to Central Section Connections:**\n    *   Top 'USB 2.0 PHY' connects to 'USB 2.0 Port 7'.\n    *   2nd 'USB 2.0 PHY' connects to 'USB 2.0 Port 6'.\n    *   3rd 'USB 2.0 PHY' connects to 'USB 2.0 Port 5'.\n    *   5th 'USB 2.0 PHY' connects to 'USB 2.0 Port 4'.\n    *   8th 'USB 3.0 PHY' connects to 'USB 3.0/2.0 Port 3'.\n    *   9th 'USB 2.0 PHY' connects to 'USB 2.0 Port 2'.\n    *   12th 'USB 3.0 PHY' connects to 'USB 3.0/2.0 Port 1'.\n    *   14th 'USB 3.0 PHY' connects to 'USB 2.0 Port 0 (Host/Device Mode)'.\n*   **SoC to Row AB Connections:**\n    *   Top 'USB 2.0 PHY' connects to 'USB 3.0 Upgrade Port 1'.\n    *   2nd 'USB 2.0 PHY' connects to 'USB 3.0 Upgrade Port 0'.\n    *   3rd 'USB 2.0 PHY' connects to 'USB 2.0 Port 7 (Host/Device)'.\n    *   5th 'USB 2.0 PHY' connects to 'USB 2.0 Port 6'.\n    *   7th 'USB 2.0 PHY' connects to 'USB 2.0 Port 4'.\n    *   8th 'USB 3.0 PHY' connects to 'USB 2.0 Port 5' and 'USB 2.0 Port 3' (via a junction dot).\n    *   11th 'USB 2.0 PHY' connects to 'USB 2.0 Port 2'.\n    *   12th 'USB 3.0 PHY' connects to 'USB 2.0 Port 1' (via a junction dot).\n    *   14th 'USB 3.0 PHY' connects to 'USB 2.0 Port 0'.\n*   **Note:** Several 'USB 3.0 PHY' blocks are marked with a cross and do not have external connections shown.](.nanox-al-50-1j088-1030-13/650d047908e73575b457e0b56b869e9d5a19554604bd664cf5c686d364c730da.jpg)

# 3.3.12. SPI (BIOS only)

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER.SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>O P 3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10k 3.3VSB</td><td>Carrier shall pull to GND or leave not connected</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10k 3.3VSB</td><td>Carrier shall pull to GND or leave not connected</td></tr></table>

# 3.3.13. Miscellaneous

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the “speaker” in PC-AT systems</td><td>O 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3V</td><td></td><td></td></tr><tr><td>THERMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.</td><td>O OD 3.3V</td><td>PU 2.2k 3.3V</td><td>There shall be PD on carrier board</td></tr><tr><td>FAN_TACHIN11</td><td>B102</td><td>Fan tachometer input for a fan with a two pulse output.</td><td>I OD 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>TPM_PP11</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100k</td><td>PD only when TPM on module (TBD)</td></tr></table>

# 3.3.14. SMBus

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.</td><td>I/O OD 3.3VSB</td><td>PU 8k2 3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.</td><td>I/O OD 3.3VSB</td><td>PU 8k2 3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr></table>

# 3.3.15. I2C Bus

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2k2 3.3VSB</td><td>Source SEMA BMC or Apollo Lake SoC as alternative. (BMC by default)</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2k2 3.3VSB</td><td>Source SEMA BMC or Apollo Lake SoC as alternative. (BMC by default)</td></tr></table>

# 3.3.16. General Purpose I/O (GPIO)

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr></table>

Notes: GPO[0:3], PU 10k 3.3V is by build option for programming these pins to be GPI.
GPI[0:3], PD 10k is by build option for programming these pins to be GPO.

# 3.3.17. Serial Interface Signals

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SER0_TX</td><td>A98</td><td>General purpose serial port transmitter (TTL level output)</td><td>O CMOS</td><td>PU 4k7 5V</td><td>Power rail tolerance 5V/12V There shall be PD on carrier board</td></tr><tr><td>SER0_RX</td><td>A99</td><td>General purpose serial port receiver (TTL level input)</td><td>I CMOS</td><td>PU 4k7 5V</td><td>Power rail tolerance 5V/12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter (TTL level output)</td><td>O CMOS</td><td>PU 4k7 5V</td><td>Power rail tolerance 5V/12V There shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver (TTL level input)</td><td>I CMOS</td><td>PU 4k7 5V</td><td>Power rail tolerance 5V/12V</td></tr></table>

# 3.3.18. Power And System Management

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3V</td><td>PU 100k3.3VSB</td><td></td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates imminent suspend operation; used to notify LPC devices.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates system is in Suspend to Disk state. Active low output.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates system is in Soft Off state.</td><td>O3.3VSB</td><td></td><td>Not supported, connect to SUS_S4#</td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake up signal.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td>Not supported, connected to WAKE0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal used by the ACPI operating system for a LID switch.</td><td>IOD3.3VSB</td><td>PU 10k3.3VSB</td><td>Emulate GPIO (BIOS)</td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>IOD3.3VSB</td><td>PU 10K3.3VSB</td><td>Emulated GPIO (BIOS)</td></tr></table>

3.3.19. Power and Ground

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104-A109B104-B109</td><td>Primary power input: +12V nominalSee section 7 “Electrical Specifications” for allowable input range. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>4.75-20 V</td></tr><tr><td>VCC_5V_SBY</td><td>B84-B87</td><td>Standby power input: +5.0V nominal. See section 7 “Electrical Specifications” for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A66, A80, A90, A96, A100, A110, B1, B11, B21 ,B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 4. Module Interfaces

This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification

# 4.1. Connector, Switch and LED Locations

![XDP\n60-pin to CPU\n40-pin\nMulti\nPurpose\nAB\nLED1\nLED2\nLED3](.nanox-al-50-1j088-1030-13/461947de63b6894000bc916320d3e9cd0c422409192204ea8eac3f49400abe56.jpg)

Figure 3: nanoX-AL Connector, Switch and LED Locations
Note: The optional MIPI60 Debug Header is located on the breakout PCB.

# nanoX-AL and the DB40 Debug Module

(the diagram below is for illustration purpose only)

![Two green printed circuit boards with various electronic components and connectors, shown from different angles (no readable text or symbols)](.nanox-al-50-1j088-1030-13/56f90bf6773bae7bae2fc25c35c41664d7de8756ce7188d7b7501b7c852ed0fb.jpg)

Figure 4: nanoX-AL and the DB40 Debug Module

# 4.2. 40-pin Debug Connector

FPC Connector Type: FCI 59GF Flex 10042867

Pin Orientation

![This image shows a close-up of a green printed circuit board. On the far left is a large, gold-ringed circular pad. The center is dominated by a long, white multi-pin connector housing with numerous metal contacts visible beneath it. Small black surface-mount components are arranged along the top edge. White silkscreen text labels are visible on the board: 'P1' and 'P2' above the connector, 'P3' to the right of the connector, and 'Y1' on the far right edge.](.nanox-al-50-1j088-1030-13/2d748f8027c44df6efcf7a295d6f6f67bc3c412cbf8809ee2ab1b8dfcd16ed06.jpg)
1 40

40-pin Debug Connector Pin Definition on the COM Express Module

<table><tr><td>Pin #</td><td>Interface</td><td>Siganls</td><td>Remark</td></tr><tr><td>1</td><td>NC</td><td>RSVD</td><td></td></tr><tr><td>2</td><td rowspan="4">For SMC Debug</td><td>SMC_STATUS</td><td>Connect to LED</td></tr><tr><td>3</td><td>BIOS_MODE</td><td>Connect to Jumper for Debug</td></tr><tr><td>4</td><td>SEL_BIOS</td><td>Connect to Jumper for Debug</td></tr><tr><td>5</td><td>POSTWDT_DIS#</td><td>Connect to Jumper for Debug</td></tr><tr><td>6</td><td rowspan="7">Test Point</td><td>SUS_S5#</td><td></td></tr><tr><td>7</td><td>SUS_S4#</td><td></td></tr><tr><td>8</td><td>SUS_S3#</td><td></td></tr><tr><td>9</td><td>CB_PWROK</td><td></td></tr><tr><td>10</td><td>CB_RESET#</td><td></td></tr><tr><td>11</td><td>SYS_RESET#</td><td></td></tr><tr><td>12</td><td>PWRBTN#</td><td></td></tr><tr><td>13</td><td rowspan="11">SMC Program interface</td><td>SMC_OCD0B</td><td>Include a jumper to connect OCD0B via 1Kohm pull-down to GND</td></tr><tr><td>14</td><td>SMC_OCD0A</td><td>Include a jumper to connect OCD0A via 1Kohm pull-up to 3.3V_SMC</td></tr><tr><td>15</td><td>SMC_CLK</td><td></td></tr><tr><td>16</td><td>SMC_DATA</td><td></td></tr><tr><td>17</td><td>SMC_RESET_IN#</td><td></td></tr><tr><td>18</td><td>SMC_FLMD0</td><td></td></tr><tr><td>19</td><td>SMC_RXD6</td><td></td></tr><tr><td>20</td><td>SMC_TXD6</td><td></td></tr><tr><td>21</td><td>GND3</td><td></td></tr><tr><td>22</td><td>3V3_A</td><td>3.3VSB provided from COM module</td></tr><tr><td>23</td><td>3V3_SMC1</td><td>3.3VSB provided from COM module</td></tr></table>

<table><tr><td>Pin #</td><td>Interface</td><td>Siganls</td><td>Remark</td></tr><tr><td>24</td><td rowspan="10">LPC Debug card Interface</td><td>LPC_AD0</td><td></td></tr><tr><td>25</td><td>LPC_AD1</td><td></td></tr><tr><td>26</td><td>LPC_AD2</td><td></td></tr><tr><td>27</td><td>LPC_AD3</td><td></td></tr><tr><td>28</td><td>LPC_FRAME#</td><td></td></tr><tr><td>29</td><td>CLK33_LPC</td><td></td></tr><tr><td>30</td><td>RST#</td><td></td></tr><tr><td>31</td><td>BIOS_DIS0</td><td></td></tr><tr><td>32</td><td>GND2</td><td></td></tr><tr><td>33</td><td>3V3_LPC</td><td>System power 3.3V provided from COM module</td></tr><tr><td>34</td><td rowspan="7">SPI Program Interface</td><td>SPI_BIOS_CLK</td><td></td></tr><tr><td>35</td><td>SPI_BIOS_MOSI</td><td></td></tr><tr><td>36</td><td>SPI_BIOS_MISO</td><td></td></tr><tr><td>37</td><td>SPI_BIOS_CS1#</td><td></td></tr><tr><td>38</td><td>SPI_BIOS_CS0#</td><td></td></tr><tr><td>39</td><td>GND1</td><td></td></tr><tr><td>40</td><td>VCC_SPI_IN</td><td>SPI Power Input from flash tool to module.HW needs to add MOS FET to switch SPI power for SPI ROM</td></tr></table>

Table 2: 40-pin Debug Connector Pin Definition
Note: The pin definition on the debug module is the inverse of that on the COM Express module.

# 4.3. Status LEDs

To facilitate easier maintenance, status LED’s are mounted on the board.

![Close-up of a green printed circuit board (PCB) with no visible text or symbols](.nanox-al-50-1j088-1030-13/fec2d0cabda08b257cd727bf5086f498fa4669d93ac6b38a880865510f50afae.jpg)

LED1 LED2 LED3

LED Descriptions

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC output</td><td>Power Sequence Status Code (BMC)Power Changes, RESET(see 5.1.4 Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>BMC outputand same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

Table 3: nanoX-AL LED Descriptions

# 4.4. MIPI60 Debug Header (build option)

Not all pins of the Intel® MIPI60 connector are connected to the CombiProbe Intel x86/x64 MIPI60-C.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>XDP Signal</td></tr><tr><td>1</td><td>VREF_DEBUG</td><td>2</td><td>TMS</td></tr><tr><td>3</td><td>TCK0</td><td>4</td><td>TDO</td></tr><tr><td>5</td><td>TDI</td><td>6</td><td>Open Drain Reset Out</td></tr><tr><td>7</td><td>Reset In</td><td>8</td><td>No Connect</td></tr><tr><td>9</td><td>TRST_N</td><td>10</td><td>PREQ_N</td></tr><tr><td>11</td><td>PRDY_N</td><td>12</td><td>VREF_TRACE</td></tr><tr><td>13</td><td>PTI_0_CLK</td><td>14</td><td>PTI_1_CLK</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>No Connect</td><td>18</td><td>PTI_1_DATA[0]</td></tr><tr><td>19</td><td>PTI_0_DATA[0]</td><td>20</td><td>PTI_1_DATA[1]</td></tr><tr><td>21</td><td>PTI_0_DATA[1]</td><td>22</td><td>PTI_1_DATA[2]</td></tr><tr><td>23</td><td>PTI_0_DATA[2]</td><td>24</td><td>PTI_1_DATA[3]</td></tr><tr><td>25</td><td>PTI_0_DATA[3]</td><td>26</td><td>No Connect</td></tr><tr><td>27</td><td>PTI_0_DATA[4]</td><td>28</td><td>No Connect</td></tr><tr><td>29</td><td>PTI_0_DATA[5]</td><td>30</td><td>No Connect</td></tr><tr><td>31</td><td>PTI_0_DATA[6]</td><td>32</td><td>No Connect</td></tr><tr><td>33</td><td>PTI_0_DATA[7]</td><td>34</td><td>Reset Out</td></tr><tr><td>35</td><td>No Connect</td><td>36</td><td>Boot Stall</td></tr><tr><td>37</td><td>No Connect</td><td>38</td><td>CPU Boot Stall</td></tr><tr><td>39</td><td>No Connect</td><td>40</td><td>Power Button</td></tr><tr><td>41</td><td>No Connect</td><td>42</td><td>PWRGOOD</td></tr><tr><td>43</td><td>No Connect</td><td>44</td><td>No Connect</td></tr><tr><td>45</td><td>No Connect</td><td>46</td><td>No Connect</td></tr><tr><td>47</td><td>No Connect</td><td>48</td><td>I2C_SCL</td></tr><tr><td>49</td><td>No Connect</td><td>50</td><td>I2C_SDA</td></tr><tr><td>51</td><td>No Connect</td><td>52</td><td>No Connect</td></tr><tr><td>53</td><td>No Connect</td><td>54</td><td>DBG_UART_TX</td></tr><tr><td>55</td><td>No Connect</td><td>56</td><td>DBG_UART_RX</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>GND</td></tr><tr><td>59</td><td>No Connect</td><td>60</td><td>No Connect</td></tr></table>

![The image displays a label with three distinct text sections.\n\nThe top-left section is titled 'Calibration' and lists:\n'Current Date:'\n'Date: 05/16/05'\n'Time: 14:07'\n'Batch:'\n'ID:'\n'Operator:'\n'Please enter the calibration code.'\n\nThe top-right section is titled 'Calibration Code' and lists:\n'Please enter the calibration code.'\n'Cal. Date: 05/16/05'\n'Cal. Time: 14:07'\n'Cal. ID: 052004'\n'Please enter the calibration code.'\n\nThe bottom section repeats the 'Calibration' header and lists:\n'Current Date:'\n'Date: 05/16/05'\n'Time: 14:07'\n'Batch:'\n'ID:'\n'Operator:'\n'Please enter the calibration code.'](.nanox-al-50-1j088-1030-13/b4b6832562152dacac575e1ce66842dc1d8646628e30dc8bc9c2f4460b656321.jpg)
Table 4: MIPI60 Debug Header Pin Definition

# 4.5. Switch Settings

Switch Locations
![BIOS Select and Mode\nConfiguration Switch](.nanox-al-50-1j088-1030-13/63fabeffafabb34af231f091f65d67a570fa7dfd7a2b77a087000a7ef85aa2f7.jpg)

Figure 5: cExpress Switch Locations

# BIOS Select and Mode Configuration Switch

Module has two BIOS chips and BIOS operation can be configured to "PICMG" and "Failsafe" modes using BSW1, Pin 2. (name of this swtich on circuit is BSW1)

Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip CANNOT be placed in SPI0 on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of BIOS failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, it is allowed to also have an SPI0 BIOS on the carrier.

In both modes, strapping can select whether to boot from SPI0 or SPI1 (BSW1 Pin 1).

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (Default)</td><td>On</td><td>—</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>—</td></tr><tr><td>Set BIOS to PICMG mode</td><td>—</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode (Default)</td><td>—</td><td>Off</td></tr></table>

Table 5: BIOS Select and Mode Configuration Switch Settings

Note: The switch can be removed and 0 ohm used to support all configurations above by project basis.

# 5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented:

‧ Total operating hours counter. Counts the number of hours the module has been run in minutes.
‧ On-time minutes counter. Counts the seconds since last system start.
Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash.
‧ Power cycles counter
‧ Boot counter. Counts the number of boot attempts.
‧ Watchdog Timer. Set/Reset/Disable Watchdog Timer. Features auto-reload at power-up.
‧ System Restart Cause. Power loss/BIOS Fail/Watchdog/Internal Reset/External Reset
‧ Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from failsafe BIOS.
‧ Flash area. 1kB Flash area for customer data
‧ 2K Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
‧ Board Identify. Vendor/Board/Serial number/Production Date
‧ Main-current & voltage. Monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/sema/.

# 5.1. Board Specific SEMA Functions

# 5.1.1. Voltages

The BMC of the nanoX-AL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>VCORE</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>1</td><td>VGFX</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>2</td><td>VMEM</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>3</td><td>5VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>4</td><td>VIN</td><td>(MSB&lt;&lt;8 + LSB) x 6.000 x 3.3 / 1024</td></tr><tr><td>5</td><td>5V</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>6</td><td>3.3V</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>7</td><td>3.3VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>8</td><td>(MAIN CURRENT)</td><td>Use Main Current Function</td></tr></table>

Table 6: SEMA Onboard Voltage Monitor

# 5.1.2. Main Current

The BMC of the nanoX-AL implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) \times 8. 0 6 \mathrm{mA}
$$

# 5.1.3. BMC Status

This register shows the status of BMC controlled signals on the nanoX-AL.

&lt;table&gt;<tr><td>Status Bit</td><td>Signal</td></tr><tr><td>0</td><td>WDT_OUT</td></tr><tr><td>1</td><td>LVDS_VDDEN</td></tr><tr><td>2</td><td>LVDS_BKLTEN</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>POSTWDT_DISn</td></tr><tr><td>5</td><td>SEL_BIOS</td></tr><tr><td>6</td><td>BIOS_DIS0n</td></tr><tr><td>7</td><td>BIOS_DIS1n</td></tr></table>

Table 7: SEMA BMC Status

# 5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>NO_CB_PWRGD</td></tr><tr><td>7</td><td>BIOS_FAIL</td></tr><tr><td>8</td><td>RESET_FAIL</td></tr><tr><td>9</td><td>RESETIN_FAIL</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>NO_SYS_GD</td></tr><tr><td>14</td><td>NO_3V3_A_PGD</td></tr><tr><td>15</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_P_5V_3V3_S0_PG</td></tr><tr><td>17</td><td>NO_1V0_A_PG</td></tr><tr><td>18</td><td>NO_VCORE_PG</td></tr></table>

Table 8: SEMA Exception Codes

# 5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

<table><tr><td>Bit</td><td>Description</td></tr><tr><td>[0 ~ 4]</td><td>Exception Code</td></tr><tr><td>[6]</td><td>0 = AT mode1 = ATX mode</td></tr><tr><td>[7]</td><td>0 = Standard BIOS1 = Fail-safe BIOS.</td></tr></table>

Table 9: SEMA BMC Flags

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# 6. System Resources

# 6.1. System Memory Map

<table><tr><td>Address Range (hex)</td><td>Description</td></tr><tr><td>FF00_0000 - FFFF_FFFF</td><td>IFAW (BIOS)</td></tr><tr><td>FED0_0000 - FEDF_33FF</td><td>HPET</td></tr><tr><td>FEC0_0000 - FECF_FFFF</td><td>IOAPIC</td></tr><tr><td>0K -1MB</td><td>DOS DRAM</td></tr></table>

# 6.2. I/O Map

<table><tr><td>I/O Address</td><td>IOSF Primary Target</td><td>IOSF SB Target</td></tr><tr><td>000h-01Fh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>020h-021h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>024h-025h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>028h-029h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>02Ch-02Dh</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>02Eh-02Fh</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>030h-031h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>034h-035h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>038h-039h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>03Ch-03Dh</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>040h</td><td>P2SB</td><td>ITSS (Timer 0 Register)</td></tr><tr><td>041h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>042h</td><td>P2SB</td><td>ITSS (Timer 2 Register)</td></tr><tr><td>043h</td><td>P2SB</td><td>ITSS (Timer Control Word Register)</td></tr><tr><td>04Eh-04Fh</td><td>LPC/eSPI</td><td>LPC/eSPI</td></tr><tr><td>050h</td><td>P2SB</td><td>ITSS (alias of 040h)</td></tr><tr><td>051h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>052h</td><td>P2SB</td><td>ITSS (alias of 042h)</td></tr><tr><td>053h</td><td>P2SB</td><td>ITSS (alias of 043h)</td></tr><tr><td>060h</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>061h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr><tr><td>062h</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>063h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr><tr><td>064h</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>065h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr><tr><td>066h</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>067h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr><tr><td>070h</td><td>P2SB</td><td>ITSS (CPU I/F), RTC, PMC</td></tr><tr><td>071h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>072h-073h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>073h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>074h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>075h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>076h-077h</td><td>P2SB</td><td>RTC, PMC</td></tr><tr><td>080h</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>081h-083h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>084h-086h</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>087h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>088h</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>089h-08Bh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>08Ch-08Eh</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>08Fh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>090h</td><td>P2SB</td><td>LPC/eSPI</td></tr><tr><td>091h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>092h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr><tr><td>093h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>094h-096h</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>097h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>098h</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>099h-09Bh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>09Ch-09Eh</td><td>P2SB</td><td>LPC/eSPI or PMC</td></tr><tr><td>09Fh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>0A0h-0A1h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0A4h-0A5h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0A8h-0A9h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0ACh-0ADh</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0B0h-0B1h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0B2h-0B3h</td><td>P2SB</td><td>PMC</td></tr><tr><td>0B4h-0B5h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0B8h-0B9h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0BCh-0BDh</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>0C0h-0DFh</td><td>P2SB</td><td>Terminate</td></tr><tr><td>0F0h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>170h–177h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>2F8h–2FFh</td><td>P2SB</td><td>Serial Port</td></tr><tr><td>240h–24Fh</td><td>P2SB</td><td>Serial Port</td></tr><tr><td>2F8h–2FFh</td><td>P2SB</td><td>Serial Port</td></tr><tr><td>376h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>3F6h</td><td>P2SB</td><td>Terminate</td></tr><tr><td>3F8h–3FFh</td><td>P2SB</td><td>Serial Port</td></tr><tr><td>4D0h–4D1h</td><td>P2SB</td><td>ITSS (interrupt)</td></tr><tr><td>CF9h</td><td>P2SB</td><td>ITSS (CPU I/F)</td></tr></table>

# 6.3. Interrupt Request (IRQ) Lines

# APIC Interrupt Map

The following table describes the APIC interrupt mapping. The Apollo Lake platform supports 120 IRQs in total.

Note: These IRQs can be used for PCI devices when onboard device is disabled.

<table><tr><td>IO APIC Pin</td><td>Routing</td></tr><tr><td>0</td><td>8259</td></tr><tr><td>1</td><td>PS2 Keyboard</td></tr><tr><td>2</td><td>8254 Counter 0, HPET #0 (legacy mode)</td></tr><tr><td>3</td><td>Serial Port 3</td></tr><tr><td>4</td><td>Serial Port 4</td></tr><tr><td>5</td><td>NA</td></tr><tr><td>6</td><td>NA</td></tr><tr><td>7</td><td>NA</td></tr><tr><td>8</td><td>RTC, HPET #1 (legacy mode)</td></tr><tr><td>9</td><td>Option for configurable sources including internal ACPI/PCI devices, SCI and TCO</td></tr><tr><td>10</td><td>Serial Port 1</td></tr><tr><td>11</td><td>Serial Port 2</td></tr><tr><td>12</td><td>PS2 Mouse</td></tr><tr><td>13</td><td>xDCI</td></tr><tr><td>14</td><td>Option for configurable sources including GPIO, internal ACPI/PCI devices</td></tr><tr><td>15</td><td>Option for configurable sources including internal ACPI/PCI devices</td></tr><tr><td>16</td><td>Option for configurable sources including internal PIRQA, internal ACPI/PCI devices</td></tr><tr><td>17</td><td>PIRQB (xHCI)</td></tr><tr><td>18</td><td>Option for configurable sources including internal PIRQC, internal ACPI/PCI devices</td></tr><tr><td>19</td><td>Option for configurable sources including internal PIRQD, internal ACPI/PCI devices</td></tr><tr><td>20</td><td>Option for configurable sources including internal PIRQE, SCI, TCO, internal ACPI/PCI devices and HPET</td></tr><tr><td>21</td><td>Option for configurable sources including internal PIRQF, SCI, TCO, internal ACPI/PCI devices and HPET</td></tr><tr><td>22</td><td>Option for configurable sources including internal PIRQG, SCI, TCO, internal ACPI/PCI devices and HPET</td></tr><tr><td>23</td><td>Option for configurable sources including internal PIRQH, SCI, TCO, internal ACPI/PCI devices and HPET</td></tr><tr><td>24</td><td>Punit (DPTF)</td></tr><tr><td>25</td><td>Audio</td></tr><tr><td>26</td><td>ISH</td></tr><tr><td>27</td><td>I2C 0</td></tr><tr><td>28</td><td>I2C 1</td></tr><tr><td>29</td><td>I2C 2</td></tr><tr><td>30</td><td>I2C 3</td></tr><tr><td>31</td><td>I2C 4</td></tr><tr><td>32</td><td>I2C 5</td></tr><tr><td>33</td><td>I2C 6</td></tr><tr><td>34</td><td>I2C 7</td></tr><tr><td>35</td><td>SPI 0</td></tr><tr><td>36</td><td>SPI 1</td></tr><tr><td>37</td><td>SPI 2</td></tr><tr><td>38</td><td>UFS</td></tr><tr><td>39</td><td>EMMC</td></tr><tr><td>40</td><td>PMC IPC</td></tr><tr><td>41</td><td>PMC PMIC</td></tr><tr><td>42</td><td>SDIO</td></tr><tr><td>43</td><td>reserved</td></tr><tr><td>44</td><td>reserved</td></tr><tr><td>45</td><td>reserved</td></tr><tr><td>46</td><td>reserved</td></tr><tr><td>47</td><td>reserved</td></tr><tr><td>48</td><td>reserved</td></tr><tr><td>49</td><td>reserved</td></tr><tr><td>50 - 119</td><td>GPIO (Not for end user)</td></tr></table>

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 4 (COM3)</td><td>IRQ3 via SERIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 3 (COM4)</td><td>IRQ4 via SERIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>6</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>7</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>N/A</td><td>IRQ9 via SERIRQ</td><td>Note (1)</td></tr><tr><td>10</td><td>Serial Port 1 (COM1)</td><td>IRQ10 via SERIRQ</td><td>Note (1)</td></tr><tr><td>11</td><td>Serial Port 2 (COM2)</td><td>IRQ11 via SERIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>FERR# logic</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>SATA Primary</td><td>IRQ14 via SERIRQ</td><td>Note (1)</td></tr><tr><td>15</td><td>SATA Secondary</td><td>IRQ15 via SERIRQ</td><td>Note (1)</td></tr><tr><td>16</td><td>N/A</td><td>P.E.G Root Port, Intel HDA, PCIE Port 0/1/2/3/4/5/6, EHCI Conterller #2, I.G.D, XHCI Controller</td><td>Note (1)</td></tr><tr><td>17</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,</td><td>Note (1)</td></tr><tr><td>18</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus Controller, EHCI Controller #2</td><td>Note (1)</td></tr><tr><td>19</td><td>N/A</td><td>PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,</td><td>Note (1)</td></tr><tr><td>20</td><td>N/A</td><td>GbEController</td><td>Note (1)</td></tr><tr><td>21</td><td>N/A</td><td></td><td>Note (1)</td></tr><tr><td>22</td><td>N/A</td><td>Intel HDA</td><td>Note (1)</td></tr><tr><td>23</td><td>N/A</td><td>EHCI Controller #1</td><td>Note (1)</td></tr></table>

Note: These IRQs can be used for PCI devices when onboard device is disabled.

6.4. PCI Configuration Space Map

<table><tr><td>Logical Function</td><td>Bus</td><td>Device</td><td>Function</td></tr><tr><td>Host Bridge</td><td>0</td><td>0</td><td>0</td></tr><tr><td>DPTF (Camarillo)</td><td>0</td><td>0</td><td>1</td></tr><tr><td>NPK</td><td>0</td><td>0</td><td>2</td></tr><tr><td>NPK (PSF ghost)</td><td>0</td><td>0</td><td>5</td></tr><tr><td>GMM</td><td>0</td><td>0</td><td>3</td></tr><tr><td>Gen</td><td>0</td><td>2</td><td>0</td></tr><tr><td>lunit</td><td>0</td><td>3</td><td>0</td></tr><tr><td>Reserved (CSE)</td><td></td><td>7</td><td>0</td></tr><tr><td>P2SB</td><td>0</td><td>13</td><td>0</td></tr><tr><td>PMC</td><td>0</td><td>13</td><td>1</td></tr><tr><td>SPI</td><td>0</td><td>13</td><td>2</td></tr><tr><td>Shared SRAM</td><td>0</td><td>13</td><td>3</td></tr><tr><td>Audio</td><td>0</td><td>14</td><td>0</td></tr><tr><td>CSE-HECI1</td><td>0</td><td>15</td><td>0</td></tr><tr><td>CSE-HECI2</td><td>0</td><td>15</td><td>1</td></tr><tr><td>CSE-HECI3</td><td>0</td><td>15</td><td>2</td></tr><tr><td>CSE-fTPM (PSF ghost)</td><td>0</td><td>15</td><td>7</td></tr><tr><td>CSE-HOFFL</td><td>0</td><td>16</td><td>0</td></tr><tr><td>ISH</td><td>0</td><td>17</td><td>0</td></tr><tr><td>SATA</td><td>0</td><td>18</td><td>0</td></tr><tr><td>PCIe-A 1</td><td>0</td><td>19</td><td>0</td></tr><tr><td>PCIe-A 2</td><td>0</td><td>19</td><td>1</td></tr><tr><td>PCIe-A 3</td><td>0</td><td>19</td><td>2</td></tr><tr><td>PCIe-B 1(multipixted with USB3.0 port)</td><td>0</td><td>19</td><td>3</td></tr><tr><td>PCIe-B 2(connect to onboard LAN)</td><td>0</td><td>20</td><td>0</td></tr><tr><td>PCIe-A 1</td><td>0</td><td>20</td><td>1</td></tr><tr><td>USB-Host (xHCI)</td><td>0</td><td>21</td><td>0</td></tr><tr><td>USB-Device (xDCI)</td><td>0</td><td>21</td><td>1</td></tr><tr><td>I2C 0</td><td>0</td><td>22</td><td>0</td></tr><tr><td>I2C 1</td><td>0</td><td>22</td><td>1</td></tr><tr><td>I2C 2</td><td>0</td><td>22</td><td>2</td></tr><tr><td>I2C 3</td><td>0</td><td>22</td><td>3</td></tr><tr><td>CSE I2C 6/7 access</td><td>0</td><td>22</td><td>6</td></tr><tr><td>CSE SSRAM access</td><td>0</td><td>22</td><td>7</td></tr><tr><td>I2C 4</td><td>0</td><td>23</td><td>0</td></tr><tr><td>I2C 5</td><td>0</td><td>23</td><td>1</td></tr><tr><td>I2C 6</td><td>0</td><td>23</td><td>2</td></tr><tr><td>I2C 7</td><td>0</td><td>23</td><td>3</td></tr><tr><td>UART 0</td><td>0</td><td>24</td><td>0</td></tr><tr><td>UART 1</td><td>0</td><td>24</td><td>1</td></tr><tr><td>UART 2</td><td>0</td><td>24</td><td>2</td></tr><tr><td>UART 3</td><td>0</td><td>24</td><td>3</td></tr><tr><td>SPI 0</td><td>0</td><td>25</td><td>0</td></tr><tr><td>SPI 1</td><td>0</td><td>25</td><td>1</td></tr><tr><td>SPI 2</td><td>0</td><td>25</td><td>2</td></tr><tr><td>PWM</td><td>0</td><td>26</td><td>0</td></tr><tr><td>SD Card</td><td>0</td><td>27</td><td>0</td></tr><tr><td>eMMC</td><td>0</td><td>28</td><td>0</td></tr><tr><td>UFS</td><td>0</td><td>29</td><td>0</td></tr><tr><td>SDIO</td><td>0</td><td>30</td><td>0</td></tr><tr><td>LPC</td><td>0</td><td>31</td><td>0</td></tr><tr><td>SMBUS</td><td>0</td><td>31</td><td>1</td></tr></table>

# 6.5. PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>PCIE port1</td><td>PCIE port 2</td><td>PCIE port 3</td><td>PCIE Onboard LAN i210</td><td>Mobile IGFX</td><td>PUNIT Device</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTA:22</td><td>INTB:23</td><td>INTC:22</td><td>INTB:21</td><td>NTD:19</td><td></td><td></td></tr><tr><td>Int1</td><td>INTB:23</td><td>INTC:20</td><td>INTD:23</td><td>INTC:22</td><td></td><td>INTF:24</td><td>INTE:20</td></tr><tr><td>Int2</td><td>INTC:20</td><td>INTD:21</td><td>INTA:20</td><td>INTD:23</td><td></td><td></td><td></td></tr><tr><td>Int3</td><td>INTD:21</td><td>INTA:22</td><td>INTB:21</td><td>INTA:20</td><td></td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>NPK Device</td><td>IUNT</td><td>PMC</td><td>HD Audio</td><td>CES</td><td>ISH</td><td>SATA Controller</td><td>XHCI</td><td>XDCI</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTF:21</td><td>INTA:40</td><td>INTA:25</td><td>INTE:20</td><td>INTE:26</td><td>INTA:19</td><td>INTB:17</td><td></td></tr><tr><td>Int1</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>INTC:13</td></tr><tr><td>Int2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Int3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>I2C0</td><td>I2C1</td><td>I2C2</td><td>I2C3</td><td>I2C4</td><td>I2C5</td><td>I2C6</td><td>I2C7</td></tr><tr><td>Int0</td><td>INTA:27</td><td></td><td></td><td></td><td>INTF:31</td><td></td><td></td><td></td></tr><tr><td>Int1</td><td></td><td>INTB:28</td><td></td><td></td><td></td><td>INTB:32</td><td></td><td></td></tr><tr><td>Int2</td><td></td><td></td><td>INTC:29</td><td></td><td></td><td></td><td>INTC:33</td><td></td></tr><tr><td>Int3</td><td></td><td></td><td></td><td>INTD:30</td><td></td><td></td><td></td><td>INTD:34</td></tr></table>

<table><tr><td>INT Line</td><td>SPI1</td><td>SPI3</td><td>SPI3</td><td>SD Host #0</td><td>SD Host #1</td><td>SD Host #2</td><td>SD Host #3</td></tr><tr><td>Int0</td><td>INTA:35</td><td></td><td></td><td>INTC:15</td><td>INTD:39</td><td>INTH:38</td><td>INTB:37</td></tr><tr><td>Int1</td><td></td><td>INTB:36</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Int2</td><td></td><td></td><td>INTC:37</td><td></td><td></td><td></td><td></td></tr><tr><td>Int3</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

# 6.6. SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMMA</td><td>A0h</td></tr><tr><td>DIMMB</td><td>A4h</td></tr><tr><td>BMC</td><td>50h</td></tr><tr><td>Extend GPIO</td><td>40h</td></tr><tr><td>I210</td><td>49h</td></tr><tr><td>USB2514BI</td><td>58h</td></tr><tr><td>LM73</td><td>92h</td></tr><tr><td>PEX8605</td><td>B7h,C1h</td></tr><tr><td>NXP(eDP to LVDS transmitter)</td><td>C0h</td></tr></table>

# 7. BIOS Setup

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information System Information Board Information ▶System Date and Time Access Level</td><td>CPU Configuration ▶Graphics Configuration ▶Power Management ▶System Management ▶Thermal Management ▶Watchdog Timer ▶CSM Configuration ▶Super IO Configuration ▶Serial Console Redirection ▶USB ▶Network ▶Miscellaneous ▶Driver Health ▶Trusted Computing ▶SDIO Configuration ▶</td><td>North Bridge ▶South Bridge ▶Uncore Configuration ▶South Cluster ▶Configuration ▶</td><td>Setup Administrator Password User Password Secure Boot ▶</td><td>Boot Configuration FIXED BOOT ORDER Priorities UEFI USB Key Drive BBS Priorities</td><td>Save Change and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Boot Override</td></tr></table>

# 7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.

7.2.1. Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>ADLINK BIOS version</td></tr><tr><td>Build Date</td><td>Info only</td><td>ADLINK BIOS Build Date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Display GOP Version</td></tr><tr><td>TXE FW Version</td><td>Info only</td><td>Display TXE FW Version</td></tr><tr><td>BIOS Boot Source</td><td>Info only</td><td>Display BIOS Boot Source</td></tr></table>

7.2.2. Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board version</td><td>Info only</td><td>Display CPU Board Version.</td></tr><tr><td>CPU Board String</td><td>Info only</td><td>Display CPU Board String.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU Frequency.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Installed Memory Size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr><tr><td>SOC SKU</td><td>Info only</td><td>Display SOC SKU Version</td></tr></table>

# 7.2.3. Main > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Board Information</td><td>Submenu</td><td></td></tr><tr><td>Board Information</td><td>Info only</td><td></td></tr><tr><td>Serial Number</td><td>Info only</td><td>Display SEMA serial Number.</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Display SEMA manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Display SEMA last repair date.</td></tr><tr><td>MAC ID</td><td>Info only</td><td>Display SEMA MAC ID.</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td></td></tr><tr><td>Total Runtime</td><td>Info only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>The Boot counter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

# 7.2.4. Main >System Date/Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Info only</td><td></td></tr><tr><td>System Time</td><td>Info only</td><td></td></tr></table>

# 7.2.5. Main >Access Level

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Configuration</td><td>Info only</td><td></td></tr><tr><td>Socket 0 CPU Information</td><td>Submenu</td><td>Socket Specific CPU Information.</td></tr><tr><td>Stocket 0 CPU information</td><td>Info only</td><td></td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>Microcode Patch</td><td>Info only</td><td>Display Microcode Patch.</td></tr><tr><td>Max CPU Speed</td><td>Info only</td><td>Display Max CPU speed.</td></tr><tr><td>Min CPU speed</td><td>Info only</td><td>Display Min CPU speed.</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display Processor Cores.</td></tr><tr><td>Intel HT Technology</td><td>Info only</td><td>Display Intel HT Technology support or not.</td></tr><tr><td>Intel VT-x Technology</td><td>Info only</td><td>Display Intel VT-x Technology support or not.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>Speed</td><td>Info only</td><td>Display CPU Speed.</td></tr><tr><td>64-bit</td><td>Info only</td><td>Display 64-bit Support.</td></tr><tr><td>CPU Power Management</td><td>Submenu</td><td>CPU Power Management options.</td></tr><tr><td>CPU Power Management Configuration</td><td>Info only</td><td></td></tr><tr><td>EIST</td><td>Disabled Enabled</td><td>Enable / Disable Intel SpeedStep</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable / Disable turbo mode.</td></tr><tr><td>Boot performance mode</td><td>Max Performance Max Battery</td><td>Select the performance state that the BIOS will set before OS handoff.</td></tr><tr><td>C-States</td><td>Disabled Enabled</td><td>Enable / Disable C Sates.</td></tr><tr><td>Enhanced C-states</td><td>Disabled Enabled</td><td>Enable / Disable C1E. When enabled, CPU will switch to minimum speed when all core enter C-States.</td></tr><tr><td>Max Package C State</td><td>PC2 PC1 C0</td><td>Controls the Max Package C State that the processor will support.</td></tr><tr><td>Max Core C State</td><td>Core C6 Core C1</td><td>This option controls the Max Core C State that cores will Support.</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Un-demotion</td><td>DisabledC1</td><td>Configure C-State Auto Un-demotion</td></tr><tr><td>Power Limit 1 Enable</td><td>DisabledEnabled</td><td>Enable / Disable Power Limit 1</td></tr><tr><td>Power Limit 1</td><td>Info Only</td><td>Display Power Limit 1 Power Watts.</td></tr><tr><td>Power Limit 1 Clamp Mode</td><td>DisabledEnabled</td><td>Enable / Disable Power Limit 1 Clamp Mode.</td></tr><tr><td>Power Limit 1 Power</td><td>Auto678910111213141516171819202122232425</td><td>Power Limit 1 in Watts.Auto will program Power Limit 1 based on silicon default support value.</td></tr><tr><td>Power Limit 1 Time Windows</td><td>Auto123456781012141620242832404856648096112128</td><td>Power Limit 1 Time Windows Value in Seconds.Auto will program Power Limit 1 Time Windows base on silicon default support value.</td></tr><tr><td>Active Processor Cores</td><td>DisabledEnabled</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Intel Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>Enable / Disable CPU VT-d</td></tr><tr><td>Bi-directional PROCHOT</td><td>DisabledEnabled</td><td>When a processor thermal sensor trips (either core), the PROCHOT# will be driven.If bi-direction is enabled, external agents can drive PROCHOT# to throttle the processor.</td></tr><tr><td>Limit CPUID Maximum</td><td>DisabledEnabled</td><td>When Enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When Disabled, the processor will return the actual maximum CPUID input value</td></tr><tr><td>Execute Disable Bit</td><td>DisabledEnabled</td><td>Enable / Disable the Execute Disable Bit (XD) of the processor.With the XD bit set to enabled certain classes of malicious buffer overflow attacks can be prevented when combined with a supporting OS.</td></tr><tr><td>Thermal Monitor</td><td>DisabledEnabled</td><td>Enable / Disable Thermal Monitor.</td></tr><tr><td>Monitor Mwait</td><td>DisabledEnabledAuto</td><td>Enable / Disable Monitor Mwait.</td></tr><tr><td>Change P-STATE Coordination</td><td>HW_ALLSW_ALLSW_ANY</td><td>Change P-STATE Coordination type.</td></tr><tr><td>DTS</td><td>DisabledEnabled</td><td>Enable / Disable Digital Thermal Sensor.</td></tr></table>

# 7.3.2. Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info only</td><td></td></tr><tr><td>LVDS</td><td>Info only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bbpJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSignal LVDS bus</td><td>Signal / Dual mode select</td></tr><tr><td>DE Polaarity</td><td>Active HighActive Low</td><td>DE Polaarity Select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>LVDS Backlight Brightness</td><td>0 - 255</td><td>LVDS Backlight Brightness adjust.A change takes effect immediately.</td></tr></table>

# 7.3.3. Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Management</td><td>Info only</td><td></td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Disabled Enabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Disabled Enabled</td><td>Enable or Disable System ability to Hibernate (OS/S4 Sleep State).This option maybe not effective with some OS.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disable S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>Emulation AT/ATX</td><td>Emulation AT ATX</td><td>Select Emulation AT or ATX function.If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS.In windows XP, it will make OS show shutdown message during system shutdown.</td></tr><tr><td>Lock Legacy Resources</td><td>Disabled Enabled</td><td>Enables or Disables Lock of Legacy Resources.</td></tr><tr><td>LID Function</td><td>Disabled Enabled</td><td>Enable / Disable LID Function.</td></tr><tr><td>ECO Mode</td><td>Disabled Enabled</td><td>Reduces the power consumption of the system, but after a shutdown, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td>Power Consumption.</td></tr></table>

# 7.3.3.1. Advanced > Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info Only</td><td></td></tr><tr><td>Current Input Current</td><td>Info Only</td><td>Display Current Input Current</td></tr><tr><td>Current Input Power</td><td>Info Only</td><td>Display Current Input Power</td></tr><tr><td>VCORE</td><td>Info Only</td><td>Display VCORE Voltage</td></tr><tr><td>VGFX</td><td>Info Only</td><td>Display VGFX Voltage</td></tr><tr><td>VMEM</td><td>Info Only</td><td>Display VMEM Voltage</td></tr><tr><td>5VSB</td><td>Info Only</td><td>Display 5VSB Voltage</td></tr><tr><td>VIN</td><td>Info Only</td><td>Display VIN Voltage</td></tr><tr><td>3.3V</td><td>Info Only</td><td>Display 3.3V Voltage</td></tr><tr><td>3.3VSB</td><td>Info Only</td><td>Display 3.3VSB Voltage</td></tr><tr><td>RTC</td><td>Info Only</td><td>Display RTC Voltage</td></tr></table>

# 7.3.4. Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info Only</td><td></td></tr><tr><td>Version</td><td>Info Only</td><td>Display SEMA Module Version.</td></tr><tr><td>SEMA Firmware</td><td>Info Only</td><td>Display SEMA Firmware Version.</td></tr><tr><td>Build Date</td><td>Info Only</td><td>Display SEMA Firmware Build Date.</td></tr><tr><td>SEMA Bootloader</td><td>Info Only</td><td>Display SEMA Bootloader Version.</td></tr><tr><td>Build Date</td><td>Info Only</td><td>Display SEMA Bootloader Build Date.</td></tr><tr><td>SEMA Features</td><td>Submenu</td><td>Display SEMA Supported Features</td></tr><tr><td>SEMA Supported Features</td><td>Info only</td><td>Display SEMA Supported Features</td></tr><tr><td>Flags</td><td>Submenu</td><td>Flag</td></tr><tr><td>Flags</td><td>Info only</td><td></td></tr><tr><td>BMC Flags</td><td>Info Only</td><td></td></tr><tr><td>BIOS Select</td><td>Info Only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Info Only</td><td></td></tr><tr><td>Exception Code</td><td>Info Only</td><td></td></tr></table>

# 7.3.5. Advanced > Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Configuration Parameters</td><td>Info Only</td><td></td></tr><tr><td>Thermal and Fan Speed</td><td>Submenu</td><td></td></tr><tr><td>Smart Fan</td><td>Submenu</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr></table>

# 7.3.5.1. Advanced > Thermal Management > Thermal and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current CPU Temperature</td></tr><tr><td>Board Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current Board Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Display Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Display Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Display Max Board Temperature</td></tr><tr><td>CPU Fan Speed</td><td>Info Only</td><td>Display CPU Fan Speed</td></tr></table>

# 7.3.5.2. Advanced > Thermal Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info Only</td><td></td></tr><tr><td>CPU Smart Fan Temperature Source</td><td>CPU Sensor Board Sensor</td><td>CPU Smart Fan Temperature Source</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan) Fan Off Fan On</td><td>CPU Fan Mode</td></tr><tr><td>PWM Level</td><td>0 - 100</td><td>Control PWM Level</td></tr></table>

# 7.3.6. Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>DisabledEnabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up.</td></tr></table>

# 7.3.7. Advanced > CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Compatibility Support Module Configuration</td><td>Info only</td><td></td></tr><tr><td>CSM Support</td><td>Disabled Enabled</td><td>Enabled / Disabled CSM Support.</td></tr></table>

# 7.3.8. Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5104D</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1 (COMA).</td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2 (COMB).</td></tr><tr><td>W83627DHG</td><td>Info Only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1 (COMA).</td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2 (COMB).</td></tr></table>

7.3.8.1. Advanced > Super IO Configuration > Serial Port 1 Configuration (NCT5104D)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5104D</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1 (COMA).</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=240h; IRQ=10;IO=240h; IRQ=3,4,5,6,7,10,11,12IO=248h; IRQ=3,4,5,6,7,10,11,12IO=250h; IRQ=3,4,5,6,7,10,11,12IO=258h; IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.8.2. Advanced > Super IO Configuration > Serial Port 2 Configuration (NCT5104D)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2 (COMB).</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=248h; IRQ=11;IO=240h; IRQ=3,4,5,6,7,10,11,12IO=248h; IRQ=3,4,5,6,7,10,11,12IO=250h; IRQ=3,4,5,6,7,10,11,12IO=258h; IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.8.3. Advanced > Super IO Configuration > Serial Port 1 Configuration (W83627DHG)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1 (COMA).</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4;IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.8.4. Advanced > Super IO Configuration > Serial Port 2 Configuration (W83627DHG)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2 (COMB).</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=2F8h; IRQ=3;IO=3F8h; IRQ=3,4,5,6,7,10,11,12IO=2F8h; IRQ=3,4,5,6,7,10,11,12IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.9. Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM3</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr></table>

<table><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM4</td><td>Info only</td><td></td></tr><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>Legacy Console Redirection</td><td>Info only</td><td></td></tr><tr><td>Legacy Console Redirection Settings</td><td>Submenu</td><td>Legacy Console Redirection Settings</td></tr></table>

7.3.9.1. Advanced > Serial Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1~4 (dependent on which is enabled)</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Teriminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

# 7.3.9.2. Advanced > Serial Console Redirection > Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy Serial Redirection Port</td><td>COM1COM2COM3COM4</td><td>Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages</td></tr></table>

# 7.3.10. Advanced > USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attatcment USB deviecs.</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for Oses without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable / Disable USB Mass Storge Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.'Auto' uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.</td></tr></table>

# 7.3.11. Advanced > Network

<table><tr><td>Feature</td><td colspan="2">Options</td><td>Description</td></tr><tr><td>Onboard LAN Controller</td><td>Disable Enable</td><td colspan="2">Enable / Disable Onboard Intel I210LM Lan controller.</td></tr><tr><td>Network Stack</td><td>Disable Enable</td><td colspan="2">Enable / Disable UEFI Network Stack.</td></tr></table>

# 7.3.12. Advanced > Miscellaneous

<table><tr><td>Feature</td><td colspan="2">Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info Only</td><td colspan="2">Control the PCI Express Root Port.</td></tr><tr><td>Smart Battery Function</td><td>Disable Enable</td><td colspan="2">Enable / Disable Battery Function</td></tr></table>

# 7.3.13. Advanced > Driver Health

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Driver Name</td><td>Info only</td><td>Provides Health Status for the Drivers / Controllers.</td></tr></table>

# 7.3.14. Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>TPM20 Device Found</td><td>Info Only</td><td></td></tr><tr><td>Security Device Support</td><td>Disable Enable</td><td>Enables or Disable BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.</td></tr><tr><td>Active PCR banks</td><td>Info Only</td><td></td></tr><tr><td>Available PCR banks</td><td>Info Only</td><td></td></tr><tr><td>Pending operation</td><td>None TPM Clear</td><td>Schedule an Operation for the Security Device.NOTE: Your Computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Platform hierarchy</td><td>Disable Enable</td><td>Enable or Disable Platform Hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>Disable Enable</td><td>Enable or Disable Storage Hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>Disable Enable</td><td>Enable or Disable Endorsement Hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2TCG_2</td><td>Select the TCG2SpecVersion Support, TCG_1_2: the Compatible mode for Win8/Win10,TCG_2: Support new TCG2 protocol and event format for Win10 or later</td></tr><tr><td>Physical Presence Spec Version</td><td>1.21.3</td><td>Select to Tell O.S. to support PPI Spec Version 1.2 or 1.3.Note some HCK tests might not support 1.3.</td></tr><tr><td>TPM 20 Interface Type</td><td>Info only</td><td></td></tr><tr><td>Device Select</td><td>TPM 1.2TPM 2.0Auto</td><td>PM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated.</td></tr></table>

7.3.15. Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SDIO Configuration</td><td>Info only</td><td></td></tr><tr><td>SDIO Access Mode</td><td>AutoADMASDMAPIO</td><td>Auto Option: Access SD device in DMA mode if controller supports it,otherwise in PIO mode. DMAOption: Access SD device in DMA mode. PIO Option: Access SD device in PIO mode.</td></tr></table>

# 7.4. Chipset

# 7.4.1. Chipset > North Bridge

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Information</td><td>Info only</td><td></td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Total Memory Size.</td></tr><tr><td>Memory Vlotage</td><td>Info only</td><td>Display Memory Vlotage.</td></tr><tr><td>Memory Slot0</td><td>Info only</td><td>Display Installed Memory Slot0 Information.</td></tr><tr><td>Memory Slot1</td><td>Info only</td><td>Display Installed Memory Slot1 Information.</td></tr><tr><td>Max TOLUD</td><td>2 GB2.25 GB2.5 GB2.75 GB3 GB</td><td>Maximum Value of TOLUD.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>EnabledDisabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignemt. This is disabled automatically when Aperture Size is set to 2048MB.</td></tr><tr><td>PCIE VGA Workaround</td><td>DisableEnable</td><td>Enable it if your PCIe card cannot boot to DOS. This is for Test only.</td></tr></table>

# 7.4.2. Chipset > South Bridge

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial IRQ Mode</td><td>QuietContinuous</td><td>Configure Serial IRQ Mode.</td></tr><tr><td>SMBus Support</td><td>DisableEnable</td><td>Enable / Disable SMBus Support.</td></tr><tr><td>OS Selection</td><td>WindowsAndroidWin7Intel Linux</td><td>Select the target OS.</td></tr><tr><td>PCI CLOCK RUN</td><td>DisableEnable</td><td>Enables CLKRUN# logic to stop PCI clocks.</td></tr><tr><td>Real Time Option</td><td>RT DisabledRT Enabled, Agent IDI1RT Enabled, AgentDisabled</td><td>Select Real-Time Enable and IDI Agenet Real-Time Traffic Mask Bits.</td></tr></table>

# 7.4.3. Chipset > Uncore Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GOP Configuration</td><td>Info only</td><td></td></tr><tr><td>Active LFP Config</td><td>No LFP eDP</td><td>Active Local Flat Panel Config.</td></tr><tr><td>LVDS Backlight Mode</td><td>GTT Mode BMC Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>DDI port 1 function choose to Display Port or HDMI.</td></tr><tr><td>LFP Panel Type</td><td>Auto640x480800x6001024x7681280x10241400x1050(RB) LVDS11400x1050 LVDS21600x1200 LVDS1366x768 LVDS1680x10501920x12001440x900 LVDS1600x900 LVDS1024x768 LVDS21280x8001920x1080 LVDS2048x1536 LVDS</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>GOP Brightness Level</td><td>20406080100120140160180200220240255</td><td>Set GOP Brightness Level.</td></tr><tr><td>IGD Configuration</td><td>Info only</td><td></td></tr><tr><td>Integrated Graphics Devices</td><td>DisableEnable</td><td>Enable: Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor.Disable: Always disable IGD.</td></tr><tr><td>Primary Display</td><td>IGDPCIeHG</td><td>Select which of IGD / PCI Graphics device should be Primary Display.</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB</td><td>Select the Aperture Size.</td></tr><tr><td>DVMT Pre-Allocated</td><td>64M96M128M160M192M224M256M288M320M352M384M416M448M480M512M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device</td></tr></table>

7.4.4. Chipset > South Cluster Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD-Audio Configuration</td><td>Submenu</td><td>HD-Audio Configuration Setting.</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td>PCI Express Configuration Setting.</td></tr><tr><td>SATA Drives</td><td>Submenu</td><td>Pressto select the SATA Device Configuration Setup option.</td></tr><tr><td>SSC Configuration</td><td>Submenu</td><td>SSC Configuration Settings.</td></tr><tr><td>USB Configuration</td><td>Submenu</td><td>USB Configuration Settings.</td></tr><tr><td>Miscellaneous Configuration</td><td>Submenu</td><td>Enable / Disable Misc. Feature.</td></tr></table>

7.4.4.1. Chipset > South Cluster Configuration > HD-Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD-Audio Configuration</td><td>Info only</td><td></td></tr><tr><td>HD-Audio Support</td><td>Disable Enable</td><td>Select the target OS.</td></tr></table>

7.4.4.2. Chipset > South Cluster Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info only</td><td></td></tr><tr><td>PCIE Port assigned to LAN</td><td>Info only</td><td>Display PCIE Port assigned to LAN Information.</td></tr><tr><td>Complicace Mode</td><td>DisableEnable</td><td>Complicace Mode Enable / Disable.</td></tr><tr><td>PCIE Port 1-4 Configuration &gt;&gt;Note: Default configuration for the lanes is 3x1.Other configurations (1x2,2x1 / 2x2 / 4x1) require a customized BIOS.&lt;</td><td>3x1 Port</td><td>To configure PCI-E Port 1-4 of PCH.[4X1]:Port 1-4 (x1) and Port 8 (x1)[1x2 2x1]:Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1)[2x2]:Port 1-2 (x2) and Port 3-4 (x2)[1x4]:Port 1 (x4), Ports 2-4 (disabled)</td></tr><tr><td>PCI ExpressRoot Port 1</td><td>Submenu</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port</td></tr><tr><td>PCI ExpressRoot Port 2</td><td>Submenu</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port</td></tr><tr><td>PCI ExpressRoot Port 3</td><td>Submenu</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port</td></tr></table>

Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 1

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 1</td><td>DisableEnableAuto</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.</td></tr><tr><td>ASPM</td><td>DisableEnable</td><td>PCI Express Active State Power Management settings</td></tr><tr><td>L1 Substates</td><td>DisableL1.1L1.2L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>DisableEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>URR</td><td>DisableEnable</td><td>CI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>DisableEnable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>DisableEnable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable</td></tr><tr><td>CER</td><td>DisableEnable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable</td></tr><tr><td>CTO</td><td>Default Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisable</td><td>PCI Express Completion Timer TO Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable</td></tr><tr><td>SENFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable</td></tr><tr><td>SECE</td><td>DisableEnable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable</td></tr><tr><td>PME SCI</td><td>DisableEnable</td><td>PCI Express PME SCI Enable/Disable</td></tr><tr><td>Hot Plug</td><td>DisableEnable</td><td>PCI Express Hot Plug Enable/Disable</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisableEnable</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info only</td><td></td></tr><tr><td>PCH PCIE LTR</td><td>Disable Enable</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow</td></tr><tr><td>PCIE LTR Lock</td><td>Disable Enable</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>PCIe Selection De0emphasis</td><td>Disable Enable</td><td>When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component. 1b -3.5 dB 0b -6 dB</td></tr></table>

Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 2

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 2</td><td>DisableEnableAuto</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.</td></tr><tr><td>ASPM</td><td>DisableEnable</td><td>PCI Express Active State Power Management settings</td></tr><tr><td>L1 Substates</td><td>DisableL1.1L1.2L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>DisableEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>URR</td><td>DisableEnable</td><td>CI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>DisableEnable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>DisableEnable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable</td></tr><tr><td>CER</td><td>DisableEnable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable</td></tr><tr><td>CTO</td><td>Default Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisable</td><td>PCI Express Completion Timer TO Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable</td></tr><tr><td>SENFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable</td></tr><tr><td>SECE</td><td>DisableEnable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable</td></tr><tr><td>PME SCI</td><td>DisableEnable</td><td>PCI Express PME SCI Enable/Disable</td></tr><tr><td>Hot Plug</td><td>DisableEnable</td><td>PCI Express Hot Plug Enable/Disable</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisableEnable</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge</td></tr><tr><td>PCH PCIe LTRConfiguration</td><td>Info only</td><td></td></tr><tr><td>PCH PCIE LTR</td><td>DisableEnable</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop LatencyOverride</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow</td></tr><tr><td>PCIE LTR Lock</td><td>DisableEnable</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>PCIe SelectionDe0emphasis</td><td>DisableEnable</td><td>When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB</td></tr></table>

Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 3</td><td>DisableEnableAuto</td><td>Control the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.</td></tr><tr><td>ASPM</td><td>DisableEnable</td><td>PCI Express Active State Power Management settings</td></tr><tr><td>L1 Substates</td><td>DisableL1.1L1.2L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>DisableEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>URR</td><td>DisableEnable</td><td>CI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>DisableEnable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>DisableEnable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable</td></tr><tr><td>CER</td><td>DisableEnable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable</td></tr><tr><td>CTO</td><td>Default Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisable</td><td>PCI Express Completion Timer TO Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable</td></tr><tr><td>SENFE</td><td>DisableEnable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable</td></tr><tr><td>SECE</td><td>DisableEnable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable</td></tr><tr><td>PME SCI</td><td>DisableEnable</td><td>PCI Express PME SCI Enable/Disable</td></tr><tr><td>Hot Plug</td><td>DisableEnable</td><td>PCI Express Hot Plug Enable/Disable</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisableEnable</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge</td></tr><tr><td>PCH PCIe LTRConfiguration</td><td>Info only</td><td></td></tr><tr><td>PCH PCIE LTR</td><td>DisableEnable</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop LatencyOverride</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow</td></tr><tr><td>PCIE LTR Lock</td><td>DisableEnable</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>PCIe SelectionDe0emphasis</td><td>DisableEnable</td><td>When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB</td></tr></table>

# 7.4.4.3. Chipset > South Cluster Configuration > SATA Drives

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Drives</td><td>Info only</td><td></td></tr><tr><td>Chipset- SATA Controller Configuration</td><td>Info only</td><td></td></tr><tr><td>Chipset SATA</td><td>Disable Enable</td><td>Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port).</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Interface Speed</td><td>Gen1 Gen2 Gen3</td><td>Select SATA Interface Speed, CHV A1 always with Gen Speed.</td></tr><tr><td>SATA Test Mode</td><td>Disabled Enabled</td><td>Test Mode Enable / Disable.</td></tr><tr><td>Aggressive LPM Support</td><td>Disabled Enabled</td><td>Enable PCH to Aggressively enter link power state.</td></tr><tr><td>SATA0</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 0</td><td>Disabled Enabled</td><td>Enable / Disable SATA Port</td></tr><tr><td>SATA Port 0 Hot Plug Capability</td><td>Disabled Enabled</td><td>If enabled, SATA port will be reported as Hot Plug capable.</td></tr><tr><td>Configured as eSATA</td><td>Info only</td><td>Display Configured as eSATA support.</td></tr><tr><td>Mechanical Presence Switch</td><td>Disabled Enabled</td><td>Controls reporting if this port has a Mechanical Presence Switch. Note. Request Hardware support.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive.</td></tr><tr><td>SATA Port 0 DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 DevSlp. Board rework for LP needed before enable.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO Value</td><td>625</td><td>DITO Value.Note. DITO Value can be accessed if DITO Configuration item must enable.</td></tr><tr><td>DM Value</td><td>15</td><td>DM Value.Note. DM Value can be accessed if DITO Configuration item must enable.</td></tr><tr><td>SATA1</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 1</td><td>DisabledEnabled</td><td>Enable / Disable SATA Port</td></tr><tr><td>SATA Port 1 Hot Plug Capability</td><td>DisabledEnabled</td><td>If enabled, SATA port will be reported as Hot Plug capable.</td></tr><tr><td>Configured as eSATA</td><td>Info only</td><td>Display Configured as eSATA support.</td></tr><tr><td>Mechanical Presence Switch</td><td>DisabledEnabled</td><td>Controls reporting if this port has a Mechanical Presence Switch.Note. Request Hardware support.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive.</td></tr><tr><td>SATA Port 1 DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 1 DevSlp. Board rework for LP needed before enable.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO Value</td><td>625</td><td>DITO Value.Note. DITO Value can be accessed if DITO Configuration item must enable.</td></tr><tr><td>DM Value</td><td>15</td><td>DM Value.Note. DM Value can be accessed if DITO Configuration item must enable.</td></tr></table>

7.4.4.4. Chipset > South Cluster Configuration > SSC Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SSC SD Card Support (D27:F0)</td><td>DisabledEnabled</td><td>Enable / Disable SCC SD Card Support.</td></tr><tr><td>SCC eMMC Support (D28:F0)</td><td>DisabledEnabled</td><td>Enable / Disable SCC eMMC Support.</td></tr><tr><td>eMMC Max Speed</td><td>HS400HS200DDR50</td><td>Select the eMMC max Speed allowed.</td></tr><tr><td>SCC UFS Support (D29:F0)</td><td>DisabledEnabled</td><td>Enable / Disable UFS SDIO Support.</td></tr><tr><td>SCC SDIO Support (D30:F0)</td><td>DisabledEnabled</td><td>Enable / Disable SCC SDIO Support.</td></tr><tr><td>SDIO/GPIO</td><td>GPIO MODESDIO MODE</td><td>Select SDIO or GPIO function.</td></tr></table>

7.4.4.5. Chipset > South Cluster Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Pre-Boot Driver</td><td>DisabledEnabled</td><td>Enable / Disable XHCI Pre-Boot Driver support.</td></tr><tr><td>XHCI Mode</td><td>DisabledEnabled</td><td>Once disabled, XHCI controller would be function disabled, none of the USB devices are detectable and usable during boot and in OS. Do not disable it unless for debug purpose.</td></tr><tr><td>USB Port Disable Override</td><td>DisabledEnabled</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>XDCI Support</td><td>DisabledPCI Mode</td><td>Enable/Disable XDCI</td></tr><tr><td>XHCI Disable Compliance Mode</td><td>FALSETRUE</td><td>Option to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Complicance Mode.</td></tr><tr><td>USB HW MODE AFEComparators</td><td>DisabledEnabled</td><td>Enable/Disable USB HW MODE AFE Comparators</td></tr><tr><td>USB OTG Support</td><td>DisabledEnabled</td><td>Enable/Disable USB OTG Support</td></tr></table>

# 7.4.4.6. Chipset > South Cluster Configuration > Miscellaneous Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous Configuration</td><td>Info only</td><td></td></tr><tr><td>State After G3</td><td>S0 StateS5 StateLast State</td><td>Specify what state to go to when power is re-applied after a power failure (G3 state).S0 State: System will boot directly as soon as power applied.S5 State: System keeps in power-off state until power button is pressed.</td></tr><tr><td>Wake On Lan</td><td>DisabledEnabled</td><td>Enable or Disable the Wake on Lan.</td></tr></table>

# 7.5. Security

# 7.5.1. Security > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Setup Administrator Password</td><td>Enter Password</td><td>Set Setup Administrator Password</td></tr><tr><td>User Password</td><td>Enter Password</td><td>Set User Password</td></tr><tr><td>Secure Boot</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>Attempt Secure Control</td><td>DisabledEnabled</td><td>Secure Boot activated when Platform Key(PK) is enrolled, System mode is User / Deployed, and CSM function is disabled</td></tr></table>

# 7.6. Boot

7.6.1. Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard Number state.</td></tr><tr><td>Ouiet Boot</td><td>Disabled Enabled</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enable or Disable FastBoot features. Most probes are skipped to reduce time cost during boot.</td></tr><tr><td>New Boot Option Policy</td><td>Default Place First Place Last</td><td>Controls the placement of newly detected UEFI boot option.</td></tr><tr><td>Boot mode select</td><td>Legacy UEFI</td><td>Select boot mode LEGACY/UEFI</td></tr></table>

7.6.2. Boot > FIXED BOOT ORDER Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option #1</td><td>Hardware</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #2</td><td>CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #3</td><td>USB Hard Disk</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #4</td><td>USB CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #5</td><td>USB Key</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #6</td><td>USB Floppy</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #7</td><td>USB Lan</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #8</td><td>Network</td><td>Set the system boot order.</td></tr></table>

# 7.7. Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Change and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Change</td><td></td><td>Discard Changes fone so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

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# 8. BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

Security (SEC) – initial low-level initialization
• Pre-EFI Initialization (PEI) – memory initialization1
Driver Execution Environment (DXE) – main hardware initialization2
Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, …)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

1 Analogous to “bootblock” functionality of legacy BIOS

2 Analogous to “POST” functionality in legacy BIOS

# 8.1. Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xCF</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2. Standard Status Codes

# 8.2.1. SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2. SEC Beep Codes

None

# 8.2.3. PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4. PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

# 8.2.5. DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

# 8.2.6. DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

# 8.2.7. ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

# 8.3. OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

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# 9. Mechanical Information

# 9.1. Board-to-Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

# Tyco 3-1827253-6

# Foxconn QT002206-2131-3H

220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
This connector can be used with 5 mm through-hole standoffs (SMT type).

![Exterior view of a multi-pin electronic component with metallic leads and slots (no text or symbols visible)](.nanox-al-50-1j088-1030-13/3762996c437a0fe0f25a0f6debdf3faa155c86608d331ad4defaa45e7a189957.jpg)

# Tyco 3-6318491-6

# Foxconn QT002206-4141-3H

220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
This connector can be used with 8 mm through-hole standoffs (SMT type).

![Exterior view of a rectangular electronic component with multiple slots and mounting holes (no text or symbols visible)](.nanox-al-50-1j088-1030-13/afccbe77a1c3b0f552cefe2d8e6ed24d33cbadd1b843660f9f01387078f7e2c9.jpg)

# Common Specifications

• Current capacity: 0.5A per pin
• Rated voltage: 50 VAC
• Insulation resistance: 100M or greater @ 500 VDC
• Temperature rating: $- 4 0 ^ { \circ } \mathsf { C } \sim 8 5 ^ { \circ } \mathsf { C }$
• UL certification (ECBT2.E28476)
Copper alloy (contacts)
Housing: thermo-plastic molded compound (L.C.P.)

# 9.2. Thermal Solution

# 9.2.1. Heat Spreaders

The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.

# 9.2.2. Heat Sinks

A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.

# 9.2.3. Installation

Step 1: Place the COM Express module onto the connectors on the carrier board as shown.

![Close-up of a gloved hand inspecting a green printed circuit board with electronic components (no visible text or symbols)](.nanox-al-50-1j088-1030-13/87c0a76ab626e075c543057c719fbcf84e5c32ba2271a009818800b90b07e741.jpg)

Then press down on the module until it is firmly seated on the carrier board.

Step 2: Remove the protective membranes from the thermal pads.

![Close-up of a green leaf being sampled from tweezers into a white rectangular sample (no text or symbols visible)](.nanox-al-50-1j088-1030-13/c5eac16610e0fb525882e4136b85cb42d46c87e1465bf2be9900ca265bc20ca6.jpg)

Step 3: Put heatsink on the COM Express module and assemble the heatsink onto the COM Express module.

![Close-up of gloved hands installing a green circuit board with a metallic cooling element (no visible text or symbols)](.nanox-al-50-1j088-1030-13/a492df15e48c2a44c53080214870919b5b05510cc2d7af7b73fdf1cc3930d109.jpg)

Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module.

![Green printed circuit board with multiple electronic components and a close-up of a terminal connector (no visible text or symbols)](.nanox-al-50-1j088-1030-13/306ea51614cb1d70868a477d32f3f56edad5c2507824602753c2a6fdf48f1cc4.jpg)

# 9.3. Mounting Methods

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

Top Mounting with 5 mm connectors
![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n5 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.nanox-al-50-1j088-1030-13/4c9591c76f8281a7e27093623070bea924b3cca94faa4a604c05aee6bf91acb7.jpg)

Bottom Mounting with 5 mm connectors
![2 mm heatspreader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n5 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 14 mm\nwith spring / washer](.nanox-al-50-1j088-1030-13/9af1e933835ae507ce0966eb9a0772e745220c6ea510145b31554cee529c4ced.jpg)

Top Mounting with 8 mm connectors
![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n8 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.nanox-al-50-1j088-1030-13/68d2d642be630aa85eb2997922525e36e9a14621e69f0cf2b6d4a8b445ef505d.jpg)

Bottom Mounting with 8 mm connectors
![2 mm heatsprader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n8 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 16 mm\nwith spring / washer](.nanox-al-50-1j088-1030-13/2b6bd1effc2f94c8bc5dc20380ea7244de0c1aff784ffbae51329fb00484074c.jpg)

Figure 6: COM Express Mounting Methods

# 9.4. Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

<table><tr><td>5mm through-hole standoff (SMT type)P/N: 33-72000-0050&lt;img src="images/219cf5c717dfb3fe6c678729702fd1d06a89fc936075124a05dd4444057d9ff6.jpg"/&gt;</td><td>5mm threaded standoff (DIP type)P/N: 33-72016-0050&lt;img src="images/67bc22fa21d1074b5eafd2c3a1b4f7fe4ea1a0e14703a0e9aedb47c94ac17dfd.jpg"/&gt;</td></tr><tr><td>8mm through-hole standoff (SMT type)P/N: 33-72000-0080&lt;img src="images/d27b160b8f4e2ebb1de2231d985d42b2f083d7439e652e6288b4822656574599.jpg"/&gt;</td><td>8mm threaded standoff (DIP type)P/N: 33-72015-0050&lt;img src="images/c77f216b9ddae710390fc3b9ccbfe323e3b1da08b7e780847935bf288d170330.jpg"/&gt;</td></tr></table>

Figure 7: COM Express Standoff Types

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

• Please read these safety instructions carefully.
Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
ƒ Keep equipment properly ventilated (do not block or cover ventilation openings).
ƒ Make sure to use recommended voltage and power source settings.
ƒ Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
ƒ Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
ƒ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

<table><tr><td>Address:</td><td>9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan</td></tr><tr><td>Tel:</td><td>+886-2-8226-5877</td></tr><tr><td>Fax:</td><td>+886-2-8226-5717</td></tr><tr><td>Email:</td><td>service@adlinktech.com</td></tr></table>

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

<table><tr><td>Address:</td><td>300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China</td></tr><tr><td>Tel:</td><td>+86-21-5132-8988</td></tr><tr><td>Fax:</td><td>+86-21-5132-3588</td></tr><tr><td>Email:</td><td>market@adlinktech.com</td></tr></table>

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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