# nanoX-EL

User’s Guide

intel

![Close-up of an Intel Confidential integrated circuit chip on a green printed circuit board (no readable text or symbols beyond product labels)](.nanox-el-50m-72307-1030-13/3874e6716d48f59be67a80572b52dc05e65c45eaf34318d4a1315871df9645c1.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2021-11-24</td><td>JC</td></tr><tr><td>1.1</td><td>BIOS tables added</td><td>2023-08-21</td><td>CC</td></tr><tr><td>1.2</td><td>DDI0 port spec updated</td><td>2024-06-18</td><td>AL</td></tr><tr><td>1.3</td><td>Specifications updated</td><td>2026-01-16</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image shows a yellow triangle with a thick black border. Inside the triangle is a black exclamation point centered vertically and horizontally.](.nanox-el-50m-72307-1030-13/51994f528b91a947bac4a0ee15d9c1b81304b5b3eb29f5dd2c2e8c6b0f5cea04.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black line drawing of a wheeled trash bin that is crossed out with a large, black 'X.' Below the bin, there is a solid black rectangle.](.nanox-el-50m-72307-1030-13/3387b11bfece86822022d0570c1de98dcfecd6612d3ba1d474f12b24d5c80a47.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2026 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image features a white square icon with a red border. The bottom right corner is folded inward, resembling a dog-eared document. Inside the square, two horizontal red lines are centered vertically. There is no text.](.nanox-el-50m-72307-1030-13/c064526f7661d6a038aeb57cffce856814efcbdf6ef0941b8be7222784ac6697.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a standard warning symbol consisting of a yellow triangle with rounded corners containing a black exclamation point in the center, set against a white background.](.nanox-el-50m-72307-1030-13/59b39fb93358946634f39a4d731e4473021385bbcad71145741d5fb9621c17d6.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a red triangular warning symbol with a thin black outline. Inside the triangle is a centered white exclamation point.](.nanox-el-50m-72307-1030-13/36f414114c8151fb43e0717983784835f3fc92344f51e3664469446e9b7e715c.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

List of Figures ... .10

1. Introduction ..
2. Specifications... .12

2.1. Core System... . 12

2.2. Video.... ... 13

2.2.1. Display Interface Support.. . 14

2.3. Audio ... ... 14

2.4. Expansion Busses.. ... 14

2.5. Ethernet .. ... 15

2.6. Multi I/O and Storage... .. 16

2.7. Trusted Platform Module (TPM)... ... 17

2.8. SEMA Board Controller .. ... 18

2.9. Debug... ... 18

2.10. Power... ... 18

2.11. Mechanical and Environmental . ... 18

3. Block Diagram .. ..20
4. Pinout and Signal Descriptions ... ..21

4.1. Pin Summary .. . 21

4.2. Signal Terminology Descriptions... ... 26

4.3. AB Connector Signal Descriptions .. .. 27

4.3.1. Audio ... . 27

4.3.2. LVDS or eDP.. . 28

4.3.3. DDI0 Port... . 31

4.3.4. Gigabit Ethernet.... . 34

4.3.5. SATA .. ... 35

4.3.6. PCI Express... . 36

4.3.7. LPC Bus..... .... 38

4.3.8. USB 2.0/1.1... ... 39

4.3.9. USB 3.x Extension... .... 40

4.3.10. SPI Bus (BIOS only)... . 41

4.3.11. Miscellaneous.. .... 42

4.3.12. SMBus... .... 43

4.3.13. I2C Bus.. ... 43

4.3.14. General Purpose I/O (GPIO) . . 44

4.3.15. Serial Interface Signals.. ... 45

4.3.16. Power and System Management.. .... 46

4.3.17. Power and Ground.. . 47

5. Additional Features ...... ...48

5.1. Debug Connector... ... 49

5.2. Status LEDs... . 50

5.3. Exception Codes... . 51

5.4. BIOS Boot Select.. . 52

6. System Resources ....... .53

6.1. System Memory Map... . 53

6.2. Fixed I/O Address Range Map ... . 55

6.3. Variable I/O Address Range Map .. . 57

6.4. PCI Configuration Space Map.. . 57

6.5. PCI Interrupt Routing Map ... . 60

6.6. SMBus Address Table .. . 60

7. BIOS Configurations .... ...61

7.1. Menu Structure... . 61

7.2. Main .... ... 62

7.2.1. Main > BIOS Information . ... 62

7.2.2. Main > System Information... ... 62

7.2.3. Main > Board Information ..... ..... 63

7.2.4. Main > System Date/Time .. ... 64

7.2.5. Main > Access Levl... .... 64

7.3. Advanced ... . 65

7.3.1. Advanced > CPU Configuration . ... 65

7.3.2. Advanced > Power & Performance... ... 66

7.3.3. Advanced > Graphics Configuration . ... 75

7.3.4. Advanced> AMI Graphic Output Protocol Policy . . 77

7.3.5. Advanced > Power Management .. . 77

7.3.6. Advanced > System Management ... . 77

7.3.7. Advanced > Thermal Management ..... . 78

7.3.8. Advanced > Watchdog Timer..... . 80

7.3.9. Advanced > Super IO Configuration .. ... 80

7.3.10. Advanced > Serial Console Redirection... . 82

7.3.11. Advanced > Miscellaneous.. . 91

7.3.12. Advanced > USB Configuration... . 92

7.3.13. Advanced > Network Stack Configuration.. . 93

7.3.14. Advanced > Trusted Computing.. . 93

7.4. Chipset .. . 94

7.4.1. Chipset > System Agent (SA) Configuration.. . 94

7.4.2. Chipset > PCH-IO Configuration... ...100

7.5. Security Menu .... ..127

7.5.1. Security > Password Description. ..127

7.6. Boot Menu... ..127

7.6.1. Boot > Boot Configuration... ...127

7.6.2. Boot > FIXED BOOT ORDER Priorities.. ....128

7.7. Save & Exit Menu .. ..129

7.7.1. Save and Exit.. ..129

8. BIOS Checkpoints, Beep Codes .... . 130

8.1. Status Code Ranges . ..131

8.2. Standard Status Codes.. ..132

8.2.1. SEC Phase.. ..132

8.2.2. SEC Beep Codes... ....133

8.2.3. PEI Phase... ....133

8.2.4. PEI Beep Codes .. ..137

8.2.5. DXE Status Codes... ..138

8.2.6. DXE Beep Codes... ....142

8.2.7. ACPI/ASL Checkpoint ... ....142

8.3. OEM-Reserved Checkpoint Ranges.. ....143

9. Software Support .......... . 144

9.1. Windows 10 IoT Enterprise 64-bit.... ..144

9.2. Yocto Linux 64-bit .. ...144

10.Mechanical and Thermal... . 145

10.1. Module Dimensions . ....145

10.2. Thermal Solutions .. ....146

10.2.1. Heatspreader – Bottom Mount: HTS-nXEL-B-I.. ...146

10.2.2. Heatsink High Profile – Bottom Mount: THSH-nXEL-B-I.. ..147

10.2.3. Heatsink Low Profile – Bottom Mount: THS-nXEL-B-I . ...148

# List of Figures

Figure 1 – Module function diagram... ..20
Figure 2 - Module rear side row and pin numbering ....... ...21
Figure 3 – Module feature locations........ ...48
Figure 4 – nanoX-EL and debug modules .. ..49
Figure 5 – Module mechanical dimensions ..... .. 145
Figure 6 – Heatspreader – bottom mount: HTS-nXEL-B-I.... ... 146
Figure 7 – Heatsink High Profile –bottom mount: THSH-nXEL-B-I ... . 147
Figure 8 – Heatsink Low Profile – bottom mount: THS-nXEL-B-I............ ... 148

# 1. Introduction

The nanoX-EL is the first COM Express® COM.0 R3.0 Mini Size Type 10 module featuring the IT/OT convergence 6th Gen Intel Atom® x6000E and Pentium Celeron processors (formerly “Elkhart Lake”). The processors support up to 4 cores as well as an impressive turbo boost of up to 3.0GHz. In addition, the module is also equipped with Intel® Time Coordinated Computing (Intel® TCC) that allows several controllers to process in a synchronized manner and communicate in real time. These combined features make the nanoX-EL well suited to customers who need to manage both IT and OT in a simplified design.

The nanoX-EL supports BIOS configurable in-band ECC (IBECC) with normal memory chip or supports traditional ECC memory chip that provides ECC level error correction. A maximum 16GB LPDDR4 memory capacity, wide operating temperature range, and MIL-STD environmental specifications make it well suited for mission critical or extreme rugged applications.

Integrated Intel® Gen 11 LP Graphics includes features such as OpenGL 4.5, OpenGL ES 3.1/3.0/2.0/1.1, DirectX 12.1, OpenCL 1.2, Vulkan 1.1 APIs, Intel® Clear Video HD Technology, and support for full H.265/HEVC 10-bit, H.264, VP9, JPEG/MJPEG hardware codecs. Graphics outputs include LVDS and one DDI port supporting HDMI/DVI/DisplayPort with eDP as a BOM option. Displays of up to 4K resolution are supported on DDI/eDP interface.

Input/output features include four PCIe Gen3 lanes that can be used for NVMe SSD allowing applications to utilize the highest speed storage solutions, an optional 2.5Gigabit Ethernet port supporting Time Sensitive Network (TSN), up to two USB 3.0/2.0 ports, six USB 2.0 ports, two SATA 6 Gb/s ports and an optional onboard eMMC (16/32/64GB). Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer.

# 2. Specifications

# 2.1. Core System

# CPU

6th Gen Intel Atom® x6000E processors and Intel® Celeron® and Pentium® N & J processors (formerly “Elkhart Lake”)

Intel Atom® x6425E, 2.0(3.0) GHz, 12W, 4C/32EU (IBECC/non-ECC)
Intel Atom® x6413E, 1.5(3.0) GHz, 9W, 4C/16EU (IBECC/non-ECC)
Intel Atom® x6211E, 1.3(3.0) GHz, 6W, 2C/16EU (IBECC/non-ECC)
Intel Atom® x6425RE, 1.9 GHz, 12W, 4C/32EU (IBECC/non-ECC, Intel® TCC)
Intel Atom® x6414RE, 1.5 GHz, 9W, 4C/16EU (IBECC/non-ECC, Intel® TCC)
Intel Atom® x6212RE, 1.2 GHz, 6W, 2C/16EU (IBECC/non-ECC, Intel® TCC)
Intel Atom® x6200FE, 1.0 GHz, 4.5W, 2C/No GPU (IBECC/non-ECC, Intel® TCC)
Intel® Pentium® J6426, 2.0(3.0) GHz, 10W, 4C/32EU (non-ECC)
Intel® Celeron® J6413, 1.8(3.0) GHz, 10W, 4C/16EU (non-ECC)
Intel® Pentium® N6415, 1.2(3.0) GHz, 6.5W, 4C/16EU (non-ECC)
Intel® Celeon® N6211, 1.2(3.0) GHz, 6.5W, 2C/16EU (non-ECC)

Supporting: Intel® VT, Intel® VT-d, Intel® TXT, Intel® SSE4.2, Intel® 64 Architecture, Execute Disable Bit, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure Key (availability of features may vary between processor SKUs)

![The image features a red icon resembling a document or piece of paper with a curled bottom-right corner. Inside the red outline, there are two horizontal red lines stacked vertically.](.nanox-el-50m-72307-1030-13/ab8860125ff24449aa49f043a9b6c8957d9418774bce587c3e0b1a911be03983.jpg)

Note: SKUs with Intel® TCC feature paired with specific LAN solutions can support TSN (TBC). Pentium, Celeron and some of Atom SKUs are supported by project basis. Please contact your local ADLINK presentative.

# Memory

Up to 16GB LPDDR4

In-band ECC (IBECC) with normal memory chip support on selected SKUs. IBECC can be enabled/disabled in BIOS setup

![The image displays a red icon resembling a document or page with a folded bottom-right corner. Inside the red shape, there are two horizontal black lines.](.nanox-el-50m-72307-1030-13/11a5d6e535cd0388e592fd55c355666df3e0cb1e47e4d3177ffb11ce51632882.jpg)

Note: 8GB/16GB is supported by project basis.

# Cache

1.5MB

# Embedded BIOS

AMI Aptio V UEFI with CMOS backup in 16MB (or 32MB, TBC) MB SPI BIOS, dual BIOS by build option

# 2.2. Video

# GPU

Intel® Gen 11 LP Graphics core architecture

# GPU Feature Support

2 independent and simultaneous combinations of DisplayPort/HDMI/LVDS graphics outputs (eDP optional in place of LVDS)

Encode/transcode of HD content

Playback of HD content, including Blu-ray Disc and Blu-ray Disc 3D, using HDMI (1.4a spec compliant with 3D)

Intel® QuickSync and Intel® Clear Video HD

HEVC/H.265 10-bit/8-bit, H.264, M/JPEG, MPEG2, VC1/WMV9, VP9, VP8 HW decode

HEVC/H.265 10-bit/8-bit, H.264, M/JPEG, VP9 HW encode

DirectX up to 12.1

OpenGL up to 4.5, OpenGL ES up to 3.1

OpenCL 1.2, Vulkan 1.1 APIs

Note: Availability of features dependent on operating system (Windows 10 64-bit, Linux 64-bit)

![The image displays a red outline icon resembling a piece of paper or a document with a folded top-right corner. Inside the outline, there are three horizontal red lines stacked vertically in the center.](.nanox-el-50m-72307-1030-13/2a9610c6b6faee28fe99607b8b45ee49d05a9adeeceb18d5d30110985af2d885.jpg)

Note: Availability of features dependent on operating system (Windows 10 64-bit, Linux 64-bit).

# 2.2.1. Display Interface Support

LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, supports DE mode and Hsync/Vsync mode.

Max. resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported.

eDP: eDP 1.3 up to 4 lane support, in place of LVDS (BOM option), max. resolution 4096x2160@60Hz, 24bpp

DDI x1: Digital Display Ports (DDI) support DisplayPort 1.4, HDMI 1.4b or DVI

# 2.3. Audio

Intel® HD Audio integrated

Located on carrier miniBASE-10R (ALC262 standard support)

# 2.4. Expansion Busses

4 PCI Express x1 Gen3: Lanes 0,1,2,3 (configurable to 4 x1, 2 x2, 1 x4, 2 x1 + 1 x2, 1 x2 + 2 x1)

Other: SMBus (system), I2C (user), LPC bus (via eSPI-to-LPC bridge IC)

# 2.5. Ethernet

Integrated MAC with MaxLinear® 2.5Gigabit Ethernet PHY, GPY211 or GPY215

Supports 2.5 Gbit/s on a project basis, or 1000/100/10 Mbit/s by default

Supports TSN on Yocto Linux OS (based on GPY215 and the CPU SKUs with Intel TCC feature) (TSN may support by project basis)

# LAN LED Behavior

The following table describes the LED status behavior.

1Gbit/s (Default)

<table><tr><td>LED-Function</td><td>LED Color#</td><td>LED Status</td><td>Description</td></tr><tr><td rowspan="2">Link Speed</td><td rowspan="2">Green / Orange</td><td>Green</td><td>10/100 Mbps link speed</td></tr><tr><td>Orange</td><td>1000 Mbps link speed</td></tr><tr><td rowspan="3">Link Status &amp; Activity</td><td rowspan="3">Yellow</td><td>Off</td><td>No link</td></tr><tr><td rowspan="2">Steady on Blinking</td><td>Link established; no activity detected</td></tr><tr><td>Link established; activity detected</td></tr></table>

2.5Gbit/s

<table><tr><td>LED-Function</td><td>LED Color#</td><td>LED Status</td><td>Description</td></tr><tr><td rowspan="2">Link Speed</td><td rowspan="2">Green / Orange</td><td>Green</td><td>10/100/1000 Mbps link speed</td></tr><tr><td>Orange</td><td>2500 Mbps link speed</td></tr><tr><td rowspan="3">Link Status &amp; Activity</td><td rowspan="3">Yellow</td><td>Off</td><td>No link</td></tr><tr><td rowspan="2">Steady on Blinking</td><td>Link established; no activity detected</td></tr><tr><td>Link established; activity detected</td></tr></table>

# 2.6. Multi I/O and Storage

# USB

2x USB 3.0/2.0/1.1 (USB 0,1), 6x USB 2.0/1.1 (USB 2,3,4,5,6,7)

SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling

![The image shows a digital icon resembling a document or piece of paper. It features a white square shape with a folded top-right corner and a thick red outline. Inside the shape, two horizontal red lines are centered.](.nanox-el-50m-72307-1030-13/df0c7f5f6f7c482195de9e39473015b0a8011b56809bfb6f2a3c5dfc2d7719c0.jpg)

Note: Carrier board must be designed for Gen2 operation.

# UART

Two UART interfaces SER0 and SER1 RX/TX on module

Console Redirection COM 1 or COM 2 selectable in BIOS

Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via embedded controller 4</td><td>0x3F8</td><td>Yes</td><td></td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via embedded controller3</td><td>0x2F8</td><td>Yes</td><td></td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on carrier board 5</td><td>0x240</td><td>Yes</td><td></td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on carrier board 7</td><td>0x248</td><td>Yes</td><td></td></tr></table>

![The image shows a red icon representing a document or file. It is shaped like a square page with the top-right corner folded down. Inside the red border, against a white background, are two horizontal red bars centered in the middle, symbolizing lines of text.](.nanox-el-50m-72307-1030-13/de100abe789d89b621a1ccb2dd36f860c1cefa0ae056608c915c2635c3b86d32.jpg)

Note: SER0, SER1 from SoC HSUART are BOM option support by project basis

# LPC Bus

Low Pin Count bus extends from an eSPI-to-LPC bridge IC

# GPIO or SD

4 GPO and 4 GPI (GPI with interrupt supported on Linux), SD/GPIO muxed design, SD supported by BOM option by project basis

SD functions as storage device

![The image displays a flat icon representing a document or page. It features a white background enclosed by a thick red outline. The top right corner is folded down, creating a triangular shape. Inside the document area, there are two horizontal red lines centered vertically.](.nanox-el-50m-72307-1030-13/ae0594e579800bebb29044299a6134d62bf0cd3e9405beedf2184894d1ad35bc.jpg)

# Note: Supports 3.3V SD cards only

# SATA

2x SATA 6Gb/s (SATA 0,1)

# eMMC

16/32/64GB

![The image displays a red icon on a white background, featuring a document shape with a folded top-right corner and two horizontal lines centered within it.](.nanox-el-50m-72307-1030-13/69f0a0d3ccd6a12ab596c3f4302c3930a994e17b4412a9a05968ae2ba32b9c3c.jpg)

Note: Boot device support may vary between operating systems.

Combinations (CPU SKUs, memory capacity, eMMC capacity) not listed as standard will be supported by project basis.

Boot Device Support

<table><tr><td></td><td></td><td>Windows 10 Enterprise</td><td>Linux (Yotco)</td><td>Linux (Ubuntu)</td><td>VxWorks</td></tr><tr><td rowspan="2">OS Installation</td><td>eMMC</td><td>Yes</td><td>Yes</td><td>TBC</td><td>TBC</td></tr><tr><td>SD</td><td>No</td><td>No</td><td>No</td><td>No</td></tr></table>

![The image displays a red icon resembling a square document or page with rounded corners and a folded top-right corner. Inside the red shape, centered horizontally, are two horizontal lines stacked vertically, similar to an equals sign. The background is white.](.nanox-el-50m-72307-1030-13/3f8bfe750dd693bc40bb019eefc4ac2187f04e4f7df3b58ecf194613967d5b80.jpg)

Note: eMMC and SD functionality as an OS installation device may change dependent on Intel updates. Please contact your local sales representative for more information.

# 2.7. Trusted Platform Module (TPM)

Chipset: Infineon solution

Type: TPM 2.0 (SPI bus based)

TPM chip is BOM option

# 2.8. SEMA Board Controller

Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2C, failsafe BIOS (dual BIOS, opt. support), watchdog timer and fan control

# 2.9. Debug

30-pin flat cable connector for use with DB-30 x86 debug module

Supports BIOS POST code LED, embedded controller access, SPI BIOS flashing, internal power rail test points, debug LEDs

# 2.10. Power

Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)

Standard Voltage Input: ATX: 12V±5% / 5Vsb ±5% or AT: 12V±5%

Wide Voltage Input: ATX: 4.75-20V, 5Vsb ±5% or AT: 4.75-20V

Power Management: ACPI 5.0 compliant, Smart Battery support

Power States: C1-C6, S0, S1, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)

ECO Mode support for deep S5 for 5Vsb power saving

# Power Consumption

Please contact our ADLINK representative for the document “COM Express Module Power Consumption.”

# 2.11. Mechanical and Environmental

# Form Factor and specification

PICMG COM Express Rev 3.0 (COM.0 R3.0), Type 6, Mini size 84 x 55 mm

# Operating Temperature

<table><tr><td>Standard</td><td>0°C to +60°C (Wide Voltage Input)</td><td>Storage: -20°C to +80°C</td></tr><tr><td>Extreme Rugged(Selected SoC SKUs)</td><td>-40°C to +85°C (Standard Voltage Input)</td><td>Storage: -40°C to +85°C</td></tr></table>

# Humidity

5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# HALT tested

Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

# 3. Block Diagram

![This block diagram illustrates the connectivity of the **6th Generation Intel Atom® x6000E Processor ('Elkhart Lake')**.\n\n**Central Processor and Memory:**\n*   The central block is the **6th Generation Intel Atom® x6000E Processor ('Elkhart Lake')**.\n*   Connected to the top are four blocks labeled **LPDDR4 16/32Gb**. A note at the top right states: 'Note: Maximum supported memory configuration shown'.\n*   Connected via a dashed line to the bottom right is a block labeled **eMMC 5.1 16GB-64GB build option**.\n\n**Left-Side Interfaces and Connections:**\nA grey column on the left lists various interfaces, connected to the processor or intermediate blocks:\n*   **DDI 0**: Connects directly to the processor.\n*   **eDP/LVDS**: Connects to the processor's **eDP** port and an intermediate box labeled **eDP to LVDS**. A dashed line labeled 'build option, eDP 4 lanes' also connects here.\n*   **USB 3.0 Lane 0-1**: Connects to the processor's **2 USB 3.0** port.\n*   **USB 2.0 Lane 0-7**: Connects to the processor edge.\n*   **SATA Port 0-1**: Connects to the processor's **2 SATA 6Gb/s** port.\n*   **Max. 2.5GbE**: Connects to a box labeled **LAN PHY (GPY 215, 211)**, which connects to the processor's **SGMII** port.\n*   **PCIe Lane 0-3**: Connects to the processor's **4 PCIe Gen3** port. A label nearby reads 'x4, x2, x1 config.'.\n*   **HDA**: Listed in the column.\n*   **SPI**: Connects to a box labeled **TPM 2.0** (with a label 'build option') and a box labeled **BIOS**. The **BIOS** box connects to the processor's **eSPI** port.\n*   **SMBus**: Connects to the **Embedded Controller**.\n*   **I2C**: Connects to the processor's **I2C** port and the **Embedded Controller**.\n*   **GPIO/SDIO**: Connects to the processor's **SDIO 3.0** port and the **Embedded Controller**.\n*   **UART 0-1/CAN**: Connects to the processor's **HSUART** port and the **Embedded Controller**.\n*   **LPC/eSPI**: Connects to a box labeled **eSPI to LPC**, which connects to the **Embedded Controller** and the processor's **eSPI** port.\n\n**Embedded Controller Area:**\n*   A large blue box labeled **Embedded Controller** is located at the bottom.\n*   It connects to the **I2C**, **GPIO/SDIO**, **UART 0-1/CAN**, **SMBus**, and **eSPI to LPC** blocks.\n*   It connects to two small blue boxes labeled **Thermal sensor (SOC)** and **Thermal sensor (board)**.](.nanox-el-50m-72307-1030-13/c635e9c1631d606d5e186f3cff8aba486158dfe42ffa72778a3fe7d214183411.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# 4.1. Pin Summary

The table below is a comprehensive list of all signal pins supported on the single 220-pin COM Express connectors as defined for Type 10 in the PICMG COM.0 R3.0 specification. Signals described in the specification but not supported on the nanoX-EL are strikethrough STRIKETHROUGH.

![CD\nB1\nAB\nA110\nA1](.nanox-el-50m-72307-1030-13/0bb97aa0c2e672158f6ef2b1585882157c6d83bc2a0d59fb550e6eb7d42a6cb0.jpg)

Figure 2 - Module rear side row and pin numbering

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td></tr><tr><td>A1</td><td>GND (FIXED)</td><td></td><td>B1</td><td>GND (FIXED)</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td></td><td>B2</td><td>GBE0_ACT#</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td></td><td>B3</td><td>LPC_FRAME#/ESPI_CS0#</td></tr><tr><td>A4</td><td>GBE0_LINK100#</td><td></td><td>B4</td><td>LPC_AD0/ESPI_IO_0</td></tr><tr><td>A5</td><td>GBE0_LINK1000#</td><td></td><td>B5</td><td>LPC_AD1/ESPI_IO_1</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td></td><td>B6</td><td>LPC_AD2/ESPI_IO_2</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td></td><td>B7</td><td>LPC_AD3/ESPI_IO_3</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td></td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td></td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td></td><td>B10</td><td>LPC_CLK/ESPI_CK</td></tr><tr><td>A11</td><td>GND (FIXED)</td><td></td><td>B11</td><td>GND (FIXED)</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td></td><td>B12</td><td>PWRBTN#</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td></td><td>B13</td><td>SMB_CK</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td></td><td>B14</td><td>SMB_DAT</td></tr><tr><td>A15</td><td>SUS_S3#</td><td></td><td>B15</td><td>SMB_ALERT#</td></tr><tr><td>A16</td><td>SATAO_TX+</td><td></td><td>B16</td><td>SATA1_TX+</td></tr><tr><td>A17</td><td>SATAO_TX-</td><td></td><td>B17</td><td>SATA1_TX-</td></tr><tr><td>A18</td><td>SUS_S4#</td><td></td><td>B18</td><td>SUS_STAT#/ESPI_RESET#</td></tr><tr><td>A19</td><td>SATAO_RX+</td><td></td><td>B19</td><td>SATA1_RX+</td></tr><tr><td>A20</td><td>SATAO_RX-</td><td></td><td>B20</td><td>SATA1_RX-</td></tr><tr><td>A21</td><td>GND (FIXED)</td><td></td><td>B21</td><td>GND (FIXED)</td></tr><tr><td>A22</td><td>USB_SSRX0-</td><td></td><td>B22</td><td>USB_SSTX0-</td></tr><tr><td>A23</td><td>USB_SSRX0+</td><td></td><td>B23</td><td>USB_SSTX0+</td></tr><tr><td>A24</td><td>SUS_S5#</td><td></td><td>B24</td><td>PWR_OK</td></tr><tr><td>A25</td><td>USB_SSRX1-</td><td></td><td>B25</td><td>USB_SSTX1-</td></tr><tr><td>A26</td><td>USB_SSRX1+</td><td></td><td>B26</td><td>USB_SSTX1+</td></tr><tr><td>A27</td><td>BATLOW#</td><td></td><td>B27</td><td>WDT</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td></td><td>B28</td><td>AC/HDA_SDIN2</td></tr><tr><td>A29</td><td>HDA_SYNC</td><td></td><td>B29</td><td>AC/HDA_SDIN1</td></tr><tr><td>A30</td><td>HDA_RST#</td><td></td><td>B30</td><td>AC/HDA_SDINO</td></tr><tr><td>A31</td><td>GND (FIXED)</td><td></td><td>B31</td><td>GND (FIXED)</td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td></td><td>B32</td><td>SPKR</td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td></td><td>B33</td><td>I2C_CK</td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS</td><td></td><td>B34</td><td>I2C_DAT</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td></td><td>B35</td><td>THRM#</td></tr><tr><td>A36</td><td>USB6-</td><td></td><td>B36</td><td>USB7-</td></tr><tr><td>A37</td><td>USB6+</td><td></td><td>B37</td><td>USB7+</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td></td><td>B38</td><td>USB_4_5_OC#</td></tr><tr><td>A39</td><td>USB4-</td><td></td><td>B39</td><td>USB5-</td></tr><tr><td>A40</td><td>USB4+</td><td></td><td>B40</td><td>USB5+</td></tr><tr><td>A41</td><td>GND (FIXED)</td><td></td><td>B41</td><td>GND (FIXED)</td></tr><tr><td>A42</td><td>USB2-</td><td></td><td>B42</td><td>USB3-</td></tr><tr><td>A43</td><td>USB2+</td><td></td><td>B43</td><td>USB3+</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td></td><td>B44</td><td>USB_0_1_OC#</td></tr><tr><td>A45</td><td>USB0-</td><td></td><td>B45</td><td>USB1-</td></tr><tr><td>A46</td><td>USB0+</td><td></td><td>B46</td><td>USB1+</td></tr><tr><td>A47</td><td>VCC_RTC</td><td></td><td>B47</td><td>ESPI_EN#</td></tr><tr><td>A48</td><td>RSVD</td><td></td><td>B48</td><td>USB0_HOST_PRSNT</td></tr><tr><td>A49</td><td>GBE0_SDP</td><td></td><td>B49</td><td>SYS_RESET#</td></tr><tr><td>A50</td><td>LPC_SERIRQ/ESPI_CS1#</td><td></td><td>B50</td><td>CB_RESET#</td></tr><tr><td>A51</td><td>GND (FIXED)</td><td></td><td>B51</td><td>GND (FIXED)</td></tr><tr><td>A52</td><td>RSVD</td><td></td><td>B52</td><td>RSVD</td></tr><tr><td>A53</td><td>RSVD</td><td></td><td>B53</td><td>RSVD</td></tr><tr><td>A54</td><td>GPIO</td><td></td><td>B54</td><td>GPO1</td></tr><tr><td>A55</td><td>RSVD</td><td></td><td>B55</td><td>RSVD</td></tr><tr><td>A56</td><td>RSVD</td><td></td><td>B56</td><td>RSVD-</td></tr><tr><td>A57</td><td>GND</td><td></td><td>B57</td><td>GPO2</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td></td><td>B58</td><td>PCIE_RX3+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td></td><td>B59</td><td>PCIE_RX3-</td></tr><tr><td>A60</td><td>GND (FIXED)</td><td></td><td>B60</td><td>GND (FIXED)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td></td><td>B61</td><td>PCIE_RX2+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td></td><td>B62</td><td>PCIE_RX2-</td></tr><tr><td>A63</td><td>GPI1</td><td></td><td>B63</td><td>GPO3</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td></td><td>B64</td><td>PCIE_RX1+</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td></td><td>B65</td><td>PCIE_RX1-</td></tr><tr><td>A66</td><td>GND</td><td></td><td>B66</td><td>WAKE0#</td></tr><tr><td>A67</td><td>GPI2</td><td></td><td>B67</td><td>WAKE1#</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td></td><td>B68</td><td>PCIE_RX0+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td></td><td>B69</td><td>PCIE_RX0-</td></tr><tr><td>A70</td><td>GND (FIXED)</td><td></td><td>B70</td><td>GND (FIXED)</td></tr><tr><td>A71</td><td>LVDS_A0+ / eDP_TX2+ *</td><td></td><td>B71</td><td>DDI0_PAIR0+</td></tr><tr><td>A72</td><td>LVDS_A0- / eDP_TX2- *</td><td></td><td>B72</td><td>DDI0_PAIR0-</td></tr><tr><td>A73</td><td>LVDS_A1+ / eDP_TX1+ *</td><td></td><td>B73</td><td>DDI0_PAIR1+</td></tr><tr><td>A74</td><td>LVDS_A1- / eDP_TX1- *</td><td></td><td>B74</td><td>DDI0_PAIR1-</td></tr><tr><td>A75</td><td>LVDS_A2+ / eDP_TX0+ *</td><td></td><td>B75</td><td>DDI0_PAIR2+</td></tr><tr><td>A76</td><td>LVDS_A2- / eDP_TX0- *</td><td></td><td>B76</td><td>DDI0_PAIR2-</td></tr><tr><td>A77</td><td>LVDS_VDD_EN / eDP_VDD_EN *</td><td></td><td>B77</td><td>DDI0_PAIR4+</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td></td><td>B78</td><td>DDI0_PAIR4-</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td></td><td>B79</td><td>LVDS_BKLT_EN *</td></tr><tr><td>A80</td><td>GND (FIXED)</td><td></td><td>B80</td><td>GND (FIXED)</td></tr><tr><td>A81</td><td>LVDS_A_CK+ / eDP_TX3+ *</td><td></td><td>B81</td><td>DDI0_PAIR3+</td></tr><tr><td>A82</td><td>LVDS_A_CK- / eDP_TX3- *</td><td></td><td>B82</td><td>DDI0_PAIR3-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK / eDP_AUX+ *</td><td></td><td>B83</td><td>LVDS_BKLT_CTRL / eDP_BKLT_CTRL *</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT / eDP_AUX- *</td><td></td><td>B84</td><td>VCC_5V_SBY</td></tr><tr><td>A85</td><td>GPI3</td><td></td><td>B85</td><td>VCC_5V_SBY</td></tr><tr><td>A86</td><td>RSVD</td><td></td><td>B86</td><td>VCC_5V_SBY</td></tr><tr><td>A87</td><td>eDP_HPD *</td><td></td><td>B87</td><td>VCC_5V_SBY</td></tr><tr><td>A88</td><td>PCIE0_CK_REF+</td><td></td><td>B88</td><td>BIOS_DIS1#</td></tr><tr><td>A89</td><td>PCIE0_CK_REF-</td><td></td><td>B89</td><td>DDI0_HPD</td></tr><tr><td>A90</td><td>GND (FIXED)</td><td></td><td>B90</td><td>GND (FIXED)</td></tr><tr><td>A91</td><td>SPI_POWER</td><td></td><td>B91</td><td>DDI0_PAIR5+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td></td><td>B92</td><td>DDI0_PAIR5-</td></tr><tr><td>A93</td><td>GPO0</td><td></td><td>B93</td><td>DDI0_PAIR6+</td></tr><tr><td>A94</td><td>SPI_CLK</td><td></td><td>B94</td><td>DDI0_PAIR6-</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td></td><td>B95</td><td>DDI0_DDC_AUX_SEL</td></tr><tr><td>A96</td><td>TPM_PP</td><td></td><td>B96</td><td>USB7_HOST_PRSNT</td></tr><tr><td>A97</td><td>TYPE10#</td><td></td><td>B97</td><td>SPI_CS#</td></tr><tr><td>A98</td><td>SER0_TX</td><td></td><td>B98</td><td>DDI0_CTRLCLK_AUX+</td></tr><tr><td>A99</td><td>SER0_RX</td><td></td><td>B99</td><td>DDI0_CTRLDATA_AUX-</td></tr><tr><td>A100</td><td>GND (FIXED)</td><td></td><td>B100</td><td>GND (FIXED)</td></tr><tr><td>A101</td><td>SER1_TX/CAN_TX</td><td></td><td>B101</td><td>FAN_PWMOUT</td></tr><tr><td>A102</td><td>SER1_RX/CAN_RX</td><td></td><td>B102</td><td>FAN_TACHIN</td></tr><tr><td>A103</td><td>LID#</td><td></td><td>B103</td><td>SLEEP#</td></tr><tr><td>A104</td><td>VCC_12V</td><td></td><td>B104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td></td><td>B105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td></td><td>B106</td><td>VCC_12V</td></tr><tr><td>A107</td><td>VCC_12V</td><td></td><td>B107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td></td><td>B108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td></td><td>B109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND (FIXED)</td><td></td><td>B110</td><td>GND (FIXED)</td></tr></table>

![A red icon featuring a document shape with a folded top-right corner and two horizontal lines inside.](.nanox-el-50m-72307-1030-13/c7817e98fb478ffef07130451ebf2f8f52218dc658813b559fbc339b6c192825.jpg)

Note: STRIKETHROUGH strike-through entries are not supported functions on this product eDP (in place of LVDS) is BOM option support by project basis

SD (in place of GPIO) is BOM option support by project basis

# 4.2. Signal Terminology Descriptions

Meaning of the terms used for signal description tables

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional Input / Output</td></tr><tr><td>OD</td><td>Open drain output from the module</td></tr><tr><td></td><td></td></tr><tr><td>I 3.3V</td><td>Input 3.3V tolerant</td></tr><tr><td>I 5V</td><td>Input 5V tolerant</td></tr><tr><td>O 3.3V</td><td>Output 3.3V signal level</td></tr><tr><td>O 5V</td><td>Output 5V signal level</td></tr><tr><td>I/O 3.3V</td><td>Bi-directional signal 3.3V tolerant</td></tr><tr><td>I/O 5V</td><td>Bi-directional signal 5V tolerant</td></tr><tr><td>I/O  $3.3V_{SB}$ </td><td>Input or output 3.3V tolerant active in standby state</td></tr><tr><td></td><td></td></tr><tr><td>DDC</td><td>Display Data Channel</td></tr><tr><td>PCIE</td><td>PCI Express compatible differential signal</td></tr><tr><td>PEG</td><td>PCI Express Graphics</td></tr><tr><td>SATA</td><td>Serial ATA specification Revision 2.6 and 3</td></tr><tr><td>LVDS</td><td>Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal</td></tr><tr><td></td><td></td></tr><tr><td>P</td><td>Power Input / Output</td></tr><tr><td>REF</td><td>Reference voltage output. May be sourced from a Module power plane.</td></tr><tr><td>PDS</td><td>Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.</td></tr><tr><td></td><td></td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr></table>

# 4.3. AB Connector Signal Descriptions

4.3.1. Audio

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>AC_RST# / HDA_RST#</td><td>A30</td><td>Reset output to CODEC, active low.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>AC_SYNC / HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the CODEC(s).</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>AC_BITCLK / HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external CODEC(s).</td><td>I/O 3.3V</td><td></td><td></td></tr><tr><td>AC_SDOUT / HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the CODEC.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>AC_SDIN[2:0] / HDA_SDIN[2:0]</td><td>B28- B30</td><td>Serial TDM data inputs from up to 3 CODECs.</td><td>I/O 3.3VSB</td><td></td><td>B28 (SDIN2) Not supported Elkhart Lake doesn’t offer this pin</td></tr></table>

# 4.3.2. LVDS or eDP

The module supports a single channel LVDS display panel with up to 24-bit colors by default.

There is a BOM option that removes the eDP-to-LVDS bridge IC and outputs the eDP signals directly. eDP vs LVDS pin mapping is described below.

<table><tr><td>Pin #</td><td>LVDS mode</td><td>eDP mode</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td>eDP_TX2+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td>eDP_TX2-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td>eDP_TX1+</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td>eDP_TX1-</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td>eDP_TX0+</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td>eDP_TX0-</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>-</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>-</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td>eDP_TX3+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td>eDP_TX3-</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td>eDP_VDD_EN</td></tr><tr><td>B79</td><td>LVDS_BKLT_EN</td><td>eDP_BKLT_EN</td></tr><tr><td>B83</td><td>LVDS_BKLT_CTRL</td><td>eDP_BKLT_CTRL</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td>eDP_AUX+</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td>eDP_AUX-</td></tr><tr><td>A87</td><td>-</td><td>eDP_HPD</td></tr></table>

![The image displays a simple icon of a document or page. It features a thick red outline on a white background. Inside the red border, there are two horizontal red lines centered in the middle. The bottom right corner of the document is folded inward, creating a triangular shape.](.nanox-el-50m-72307-1030-13/4dabcbc0735ff86d27b3526858a932b6691aa45862daeff7b14c67543e75b978.jpg)

Note: LVDS is default, eDP is BOM option by project basis

4.3.2.1. Single/Dual Channel LVDS (default)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LVDS_A0+</td><td>A71</td><td>LVDS Channel A differential pairs</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A0-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3+</td><td>A78</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3-</td><td>A79</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A_CK+</td><td>A81</td><td>LVDS Channel A differential clock</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A_CK-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>LVDS_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>LVDS_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>LVDS_I2C_CK</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

4.3.2.2. 4-lane eDP (optional)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>eDP_TX3+</td><td>A81</td><td>eDP differential pairs</td><td>O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_TX3-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2+</td><td>A71</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_VDD_EN</td><td>A77</td><td>eDP power enable</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>eDP_BKLT_EN</td><td>B79</td><td>eDP backlight enable</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>eDP_BKLT_CTRL</td><td>B83</td><td>eDP backlight brightness control</td><td>O 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>eDP_AUX+</td><td>A83</td><td>eDP AUX+</td><td>I/O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_AUX-</td><td>A84</td><td>eDP AUX-</td><td>I/O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_HPD</td><td>A87</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100k</td><td>PD 100k on this pin when eDP is supported</td></tr></table>

# 4.3.3. DDI0 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI0_PAIR0+</td><td>B71</td><td>DPO_LANE0+</td><td>TMDS0_DATA2+</td></tr><tr><td>DDI0_PAIR0-</td><td>B72</td><td>DPO_LANE0-</td><td>TMDS0_DATA2-</td></tr><tr><td>DDI0_PAIR1+</td><td>B73</td><td>DPO_LANE1+</td><td>TMDS0_DATA1+</td></tr><tr><td>DDI0_PAIR1-</td><td>B74</td><td>DPO_LANE1-</td><td>TMDS0_DATA1-</td></tr><tr><td>DDI0_PAIR2+</td><td>B75</td><td>DPO_LANE2+</td><td>TMDS0_DATA0+</td></tr><tr><td>DDI0_PAIR2-</td><td>B76</td><td>DPO_LANE2-</td><td>TMDS0_DATA0-</td></tr><tr><td>DDI0_PAIR3+</td><td>B81</td><td>DPO_LANE3+</td><td>TMDS0_CLK+</td></tr><tr><td>DDI0_PAIR3-</td><td>B82</td><td>DPO_LANE3-</td><td>TMDS0_CLK-</td></tr><tr><td>DDI0_PAIR4+</td><td>B77</td><td>-</td><td>-</td></tr><tr><td>DDI0_PAIR4-</td><td>B78</td><td></td><td></td></tr><tr><td>DDI0_PAIR5+</td><td>B91</td><td>-</td><td>-</td></tr><tr><td>DDI0_PAIR5-</td><td>B92</td><td></td><td></td></tr><tr><td>DDI0_PAIR6+</td><td>B93</td><td>-</td><td>-</td></tr><tr><td>DDI0_PAIR6-</td><td>B94</td><td></td><td></td></tr><tr><td>DDI0_HPD</td><td>B89</td><td>DPO_HPD</td><td>HDMI0_HPD</td></tr><tr><td>DDI0_CTRLCLK_AUX+</td><td>B98</td><td>DPO_AUX+</td><td>HMDI0_CTRLCLK</td></tr><tr><td>DDI0_CTRLCLK_AUX-</td><td>B99</td><td>DPO_AUX-</td><td>HMDI0_CTRLDATA</td></tr><tr><td>DDI0_DDC_AUX_SEL</td><td>B95</td><td>DDI0_DDC_AUX_SEL</td><td>DDI0_DDC_AUX_SEL</td></tr></table>

![The image displays a simple, flat-style icon outlined in red. It is a square shape with rounded corners, featuring a folded bottom-right corner that mimics a piece of paper. Inside the square, there are two horizontal lines stacked vertically, resembling text or a list. The interior of the icon is white.](.nanox-el-50m-72307-1030-13/4bdfea9a2e748441027de994153851b8e95ee89214dcee42b8425c7912d687cd.jpg)

Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SoCs that natively implement this capability. With such SoCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches may be used to resolve this problem. The FET gates can be controlled by the AUX\_SEL pin function.

4.3.3.1. DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>DP0_LANE0+</td><td>B71</td><td>DP Port 1, differential pair data lines</td><td>O PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP0_LANE0-</td><td>B72</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP0_LANE1+</td><td>B73</td><td></td><td></td><td></td></tr><tr><td>DP0_LANE1-</td><td>B74</td><td></td><td></td><td></td></tr><tr><td>DP0_LANE2+</td><td>B75</td><td></td><td></td><td></td></tr><tr><td>DP0_LANE2-</td><td>B76</td><td></td><td></td><td></td></tr><tr><td>DP0_LANE3+</td><td>B81</td><td></td><td></td><td></td></tr><tr><td>DP0_LANE3-</td><td>B82</td><td></td><td></td><td></td></tr><tr><td>DP0_HPD</td><td>B89</td><td>DP Port 1, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100k</td><td>Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.</td></tr><tr><td>DP0_AUX+</td><td>B98</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PD 100k</td><td>AC coupled on Module</td></tr><tr><td>DP0_AUX-</td><td>B99</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PU 100k</td><td>AC coupled on Module</td></tr><tr><td>DDI0_DDC_AUX_SEL</td><td>B95</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and floating on the carrier enable DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.3.3.2. HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TMDS0_DATA2+</td><td>B71</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIE</td><td rowspan="6"></td><td rowspan="6">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>TMDS0_DATA2-</td><td>B72</td></tr><tr><td>TMDS0_DATA1+</td><td>B73</td></tr><tr><td>TMDS0_DATA1-</td><td>B74</td></tr><tr><td>TMDS0_DATA0+</td><td>B75</td></tr><tr><td>TMDS0_DATA0-</td><td>B76</td></tr><tr><td>TMDS0_CLK+</td><td>B81</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS0_CLK-</td><td>B82</td></tr><tr><td>HDMI0_HPD</td><td>B89</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100k</td><td></td></tr><tr><td>HDMI0_CTRLCLK</td><td>B98</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2k</td><td>AC couple on Module</td></tr><tr><td>HDMI0_CTRLDATA</td><td>B99</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2k</td><td>AC couple on Module</td></tr><tr><td>DDI0_DDC_AUX_SEL</td><td>B95</td><td>Strapping Signal to select HDMI or DP output.1M pull-down on the module and pull-high on the carrier enable HDMI mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

# 4.3.4. Gigabit Ethernet

<table><tr><td>Name</td><td>Pin #</td><td colspan="4">Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="9"></td></tr><tr><td>GBE0_MDI0+</td><td>A13</td><td rowspan="3" colspan="4">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="8">I/O Analog</td><td rowspan="8"></td><td rowspan="8">Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_MDI0-</td><td>A12</td></tr><tr><td>GBE0_MDI1+</td><td>A10</td></tr><tr><td>GBE0_MDI1-</td><td>A9</td><td colspan="2">1000</td><td>100</td><td>10</td></tr><tr><td>GBE0_MDI2+</td><td>A7</td><td>MDI[0]+/-</td><td>B1_DA+/-</td><td>TX+/-</td><td>TX+/-</td></tr><tr><td>GBE0_MDI2-</td><td>A6</td><td>MDI[1]+/-</td><td>B1_DB+/-</td><td>RX+/-</td><td>RX+/-</td></tr><tr><td>GBE0_MDI3+</td><td>A3</td><td>MDI[2]+/-</td><td>B1_DC+/-</td><td></td><td></td></tr><tr><td>GBE0_MDI3-</td><td>A2</td><td>MDI[3]+/-</td><td>B1_DD+/-</td><td></td><td></td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td colspan="4">Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td colspan="4">Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK100#</td><td>A4</td><td colspan="4">Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK1000#</td><td>A5</td><td colspan="4">Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td colspan="4">Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>REFGND min3.3V max</td><td></td><td>Not supported</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td colspan="4">Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.</td><td>IO 3.3VSB</td><td>GBE0_SDP</td><td>Depends on the selection of LAN controller</td></tr></table>

![A red icon on a white background depicting a memo or document with a folded bottom-right corner. Inside the red outline are two horizontal red lines.](.nanox-el-50m-72307-1030-13/200cac92b98e87ab00ad344b994fd6f8fd062ae2fd0b5401af239661ae6f67d3.jpg)

Note: TSN supported by GPY 215 PHY and Yocto Linux OS on selected CPU SKUs. The GPY 215 supports speeds up to 2.5 GbE, and the PHY firmware for 2.5 GbE is a different version.

GBE0\_LINK1000# will be active to indicate 2.5GbE speed.

GBE0\_LINK100# will be active to indicate 1GbE speed or lower.

4.3.5. SATA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10k 3.3V</td><td>AC coupled on Module</td></tr></table>

4.3.5.1. PCH HSIO Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SOC</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>SATA0</td><td>HSIO 10</td><td></td></tr><tr><td>SATA1</td><td>HSIO 11</td><td></td></tr></table>

4.3.6. PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O PCIE</td><td></td><td></td></tr></table>

4.3.6.1. PCH HSIO Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SOC</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>PCIE0</td><td>HSIO 2</td><td></td></tr><tr><td>PCIE1</td><td>HSIO 3</td><td></td></tr><tr><td>PCIE2</td><td>HSIO 4</td><td></td></tr><tr><td>PCIE3</td><td>HSIO 5</td><td></td></tr></table>

# 4.3.7. LPC Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LPC_AD0</td><td>B4</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_AD1</td><td>B5</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD2</td><td>B6</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD3</td><td>B7</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_DRQ0#</td><td>B8</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>Not connected</td></tr><tr><td>LPC_DRQ1#</td><td>B9</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O 3.3VSB</td><td>PU 8.2k3.3VSB</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3VSB</td><td></td><td>The LPC_CLK frequency is 24MHz on this platform</td></tr></table>

![The image displays a red icon resembling a chat bubble or a document with a folded top-right corner. Inside the red outline, there are two horizontal white lines.](.nanox-el-50m-72307-1030-13/e26395010d2f416685b60d2d24c0b3902ac99069bf612c155155e55f6f56146f.jpg)

Note: LPC Bus is supported by a eSPI-to-LPC bridge IC

4.3.8. USB 2.0/1.1

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 2</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 3</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 4</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 5</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 6</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1 (see *Note)</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3 (see *Note)</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5 (see *Note)</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7 (see *Note)</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr><tr><td>USB7_HOST_PRSNT</td><td>B96</td><td>Module USB client may detect the presence of a USB host on USB7. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr></table>

![The image displays a simple red icon on a white background. It depicts a rectangular shape resembling a piece of paper or a document, featuring a 'folded' or 'dog-eared' corner at the bottom right. Inside the red outline, there are two horizontal red lines, suggesting text or a list.](.nanox-el-50m-72307-1030-13/26d34a1ccc81ae0f416c6930f1199491bfb73ae69b8ad8004a292195c69084a9.jpg)

\*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

4.3.9. USB 3.x Extension

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>A22A23</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>B22B23</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>A25A26</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>B25B26</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr></table>

4.3.9.1. USB 3.x Extension Root Segmentation

<table><tr><td>Name</td><td>HSIO name on SOC</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>USB 0</td><td>HSIO 0</td><td>from XHCI controller</td></tr><tr><td>USB 1</td><td>HSIO 1</td><td>from XHCI controller</td></tr></table>

4.3.10. SPI Bus (BIOS only)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>O P 3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10k3.3VSB</td><td>Carrier shall pull to GND or leave not- connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10k3.3VSB</td><td>Carrier shall pull to GND or leave not- connected</td></tr></table>

4.3.11. Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the &quot;speaker&quot; in PC-AT systems</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>THRMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan&#x27;s RPM.</td><td>O OD 3.3V</td><td></td><td>There shall be PD on carrier board</td></tr><tr><td>FAN_TACHIN</td><td>B102</td><td>Fan tachometer input for a fan with a two-pulse output.</td><td>I OD 3.3V</td><td>PU 47k 3.3V</td><td></td></tr><tr><td>TPM_PP</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100k</td><td>PD only when TPM on module. Modules implementing a TPM shall pull down</td></tr></table>

4.3.12. SMBus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2k3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2k3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 10k3.3VSB</td><td></td></tr></table>

![The image features a square icon with rounded corners and a folded bottom-right corner, resembling a document or note. It has a thick red border and a white interior. Inside, there are two red horizontal lines stacked vertically, resembling two equals signs.](.nanox-el-50m-72307-1030-13/be2ed7910bda887edcab969c33e885d460d8d622991830e5e6134830c2583ead.jpg)
Note: SMBus from EC is BOM option supported by project basis

4.3.13. I2C Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2.2k 3.3VSB</td><td>Source SEMA BMC as default (chipset by BOM option)</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2.2k 3.3VSB</td><td>Source SEMA BMC as default (chipset by BOM option)</td></tr></table>

![The image displays a simple red icon on a white background. It depicts the outline of a document or memo pad with the bottom-right corner folded upward (a 'dog-ear'). Inside the red border, there are two horizontal red lines centered vertically. There is no text in the image.](.nanox-el-50m-72307-1030-13/4cdd5657269e3294aa59f781bbeb620677ead7ea851e4e4ac15408285aeabecb.jpg)
Note: I2C from 6th Gen Intel Atom® x6000E processor is BOM option supported by project basis

4.3.14. General Purpose I/O (GPIO)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10k 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10k 3.3V</td><td></td></tr></table>

![The image displays a simple icon of a document. It features a red outline of a vertical rectangle with rounded corners and a folded 'dog-ear' at the bottom right corner. Inside the red border, there are two horizontal red lines centered within the shape, representing text or content. The background is white.](.nanox-el-50m-72307-1030-13/bd64e45304993063bbbc837c709adfcd3d5ea6ec7bb1591677f313ed5b9dd85f.jpg)

Note: 8x GPIO from 6th Gen Intel Atom® x6000E processor is BOM option supported by project basis (TBC).

GPO[0:3] PU 10k 3.3V is by build option for programming these pins to be GPI.

GPI [0:3] PD 10k is by build option for programming these pins to be GPO.

4.3.15. Serial Interface Signals

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SER0_TX</td><td>A98</td><td>General purpose serial port transmitter</td><td>O CMOS3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER0_RX</td><td>A99</td><td>General purpose serial port receiver</td><td>I CMOS3.3V</td><td>PU 47k 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter</td><td>O CMOS3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver</td><td>I CMOS3.3V</td><td>PU 47k 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr></table>

![The image features a red line-art icon resembling a document or page. It has a square shape with rounded corners, and the bottom-right corner is folded inward to create a 'dog-ear' effect. Inside the main outline, two horizontal red lines are centered near the top. The background is white.](.nanox-el-50m-72307-1030-13/6230cc44be5a39fcf18520a69b46aa6a1cfee6362bde5057230644547dd44658.jpg)

Note: 2x UART from 6th Gen Intel Atom® x6000E processor are BOM option support by project basis

4.3.16. Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Should have weak pull up.</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates imminent suspend operation; used to notify LPC devices.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as &quot;PS_ON&quot;) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O 3.3VSB</td><td>PD 100k</td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates system is in Suspend to Disk state. Active low output.</td><td>O 3.3VSB</td><td>PD 100k</td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates system is in Soft Off state.</td><td>O 3.3VSB</td><td>PD 100k</td><td></td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake up signal.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10k 3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal used by the ACPI operating system for a LID switch.</td><td>I OD 3.3VSB</td><td>PU 47k 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>I OD 3.3VSB</td><td>PU 47k 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr></table>

4.3.17. Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109</td><td>Primary power input supports wide range 5~20V inputAll available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>4.75-20 V</td></tr><tr><td>VCC_5V_SBY</td><td>B84, B85, B86, B87</td><td>Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as below:

![30-pin\nDebug\nConnector\nStatus\nLEDs\nBIOS Default\nReset Button](.nanox-el-50m-72307-1030-13/365320fd369403691cf4de1d64b08d1074f6a75b2a6775b45b1fe01bd1ebcd9f.jpg)

Figure 3 – Module feature locations

# 5.1. Debug Connector

This connector is particularly useful during carrier design and bring up phase. It offers access to the following critical parts of the module:

 Test points measurement of internal power rails
 I2C bus for BIOS POST code readout
 SPI BIOS programming interface
 Embedded Controller programming interface

![Two electronic circuit boards connected via a cable, one showing internal components and the other showing a network of connected components (no readable text or symbols)](.nanox-el-50m-72307-1030-13/82bc39b0aa3d8134ce4de46b1890b4ff7047efe16aafb875253c963449816224.jpg)

Figure 4 – nanoX-EL and debug modules

# 5.2. Status LEDs

Status LED’s are mounted on the module to facilitate easier maintenance.

LED3 LED2 LED1

![Green printed circuit board with various electronic components and a circular component (no visible text or symbols)](.nanox-el-50m-72307-1030-13/284b4a7feeaee026cb38662e1b85e4484cc7b4d753c4202639a8c6e6181209f5.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC output</td><td>Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>BMC output and same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

# 5.3. Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>7</td><td>RESET_FAIL</td></tr><tr><td>8</td><td>RESETIN_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>15</td><td>NO_V1P05A_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>18</td><td>NO_V5SBY</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>20</td><td>NO_V5_DUAL</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr><tr><td>22</td><td>NO_P_5V_3V3_S0_PG</td></tr><tr><td>23</td><td>NO_SAME_CHANNEL</td></tr><tr><td>24</td><td>NO_PCH_PG</td></tr></table>

![The image displays a simple icon of a document or file. It features a red outline in the shape of a piece of paper with the top-right corner folded down. Inside the white interior of the icon, there are two horizontal red lines centered vertically, representing text.](.nanox-el-50m-72307-1030-13/9386c97dca9aacc9e2b5291afc08f0b89c7189fca4655f0e2f47688482ddd65f.jpg)

Note: Exception codes in STRIKETHROUGH are not used by the nanoX-EL module.

# 5.4. BIOS Boot Select

The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2.

Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.

In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (default)</td><td>On</td><td>-</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>-</td></tr><tr><td>Set BIOS to PICMG mode (default)</td><td>-</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode</td><td>-</td><td>Off</td></tr></table>

# 6. System Resources

6.1. System Memory Map

<table><tr><td>Memory Range</td><td>Target</td><td>Dependency / Comments</td></tr><tr><td>000E 0000h-000E FFFFh</td><td>SPI</td><td>Bit6 in BIOS Decode Enable register is set</td></tr><tr><td>0000F 0000h-0000F FFFFh</td><td>SPI</td><td>Bit7 in BIOS Decode Enable register is set</td></tr><tr><td>FECX X000h-FECX X040h</td><td>IO(x) APIC inside PCH</td><td>XX controlled via APIC Range Select (ASEL) field and APIC Enable IOAC.AE bit.</td></tr><tr><td>FEC1 0000h-FEC1 7FFFh</td><td>PCI Express* Port 1</td><td>PCI Express Root Port 1 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC1 8000h-FEC1 FFFFh</td><td>PCI Express* Port 2</td><td>PCI Express Root Port 2 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC2 0000h-FEC2 7FFFh</td><td>PCI Express* Port 3</td><td>PCI Express Root Port 3 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC2 8000h-FEC2 FFFFh</td><td>PCI Express* Port 4</td><td>PCI Express Root Port 4 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC3 8000h-FEC3 FFFFh</td><td>PCI Express* Port 5</td><td>PCI Express Root Port 5 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC3 8000h-FEC3 FFFFh</td><td>PCI Express* Port 6</td><td>PCI Express Root Port 6 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC4 0000h-FEC4 7FFFh</td><td>PCI Express* Port 7</td><td>PCI Express* Root Port 7 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEF0 0000h-FEFF FFFFh</td><td>SPI</td><td>uCode Patch Region Enable UCPR.UPRE is set</td></tr><tr><td>FEC0 0000h-FFC7 FFFFhFF80 0000h-FF87 FFFFh</td><td>SPI</td><td>Bit 8 in BIOS Decode Enable register is set</td></tr><tr><td>FFC8 0000h-FFCF FFFFhFF88 0000h-FF8F</td><td>SPI</td><td>Bit 9 in BIOS Decode Enable register is set</td></tr><tr><td>FED0 0000h-FFD7 FFFFhFF90 0000h-FF97 FFFFh</td><td>SPI</td><td>Bit 10 in BIOS Decode Enable register is set</td></tr><tr><td>FFD8 0000h-FFDF FFFFhFF98 0000h-FF9F FFFFh</td><td>SPI</td><td>Bit11 in BIOS Decode Enable register is set</td></tr><tr><td>FFE0 0000h-FFE7 FFFFhFFA0 0000h-FFA7 FFFFh</td><td>SPI</td><td>Bit 12 in BIOS Decode Enable register is set</td></tr><tr><td>FFE8 0000h-FFEF FFFFhFFA8 0000h-FFAF FFFFh</td><td>SPI</td><td>Bit 13 in BIOS Decode Enable register is set</td></tr><tr><td>FFF0 0000h-FFF7 FFFFhFFB0 0000h-FFB7 FFFFh</td><td>SPI</td><td>Bit 14 in BIOS Decode Enable register is set</td></tr><tr><td>FFFC 0000h-FFFFh</td><td>SPI</td><td>Always Enabled.</td></tr><tr><td>FFF8 0000h-FFFB FFFFhFFB8 0000h-FFBF FFFFh</td><td>SPI</td><td>Always enabled.</td></tr><tr><td>FF70 0000h-FF7F FFFFhFF30 0000h-FF3F FFFFh</td><td>SPI</td><td>Bit 3 in BIOS Decode Enable register is set</td></tr><tr><td>FF60 0000h-FF6F FFFFhFF20 0000h-FF2F FFFFh</td><td>SPI</td><td>Bit 2 in BIOS Decode Enable register is set</td></tr><tr><td>FF50 0000h-FF5F FFFFhFF10 0000h-FF1F FFFFh</td><td>SPI(</td><td>Bit 1 in BIOS Decode Enable register is set</td></tr><tr><td>FF40 0000h-FF4F FFFFhFF00 0000h-FF0F FFFFh</td><td>SPI</td><td>Bit 0 in BIOS Decode Enable register is set</td></tr><tr><td>FED0 X000h-FED0 X3FFh</td><td>HPET</td><td>BIOS determines "fixed" location which is one of four 1KB ranges where X (in the first column) is 0h,1h,2h,or 3h.</td></tr><tr><td>FED4 0000h-FED4 7FFFh</td><td>SPI or CSE(set by strap)</td><td>TPM and Trusted Mobile KBC</td></tr><tr><td>FED4 C000h-FED4 FFFFh</td><td>PCH Internal(PSE Error Handler)</td><td>Always Enable</td></tr><tr><td>FED5 0000h-FED5 FFFFh</td><td>CSE</td><td>Always Enable</td></tr><tr><td>FED6 0000h-FED6 1FFFh</td><td>XHCI</td><td>NOT positively decoded in PCH(OPI/PSF)</td></tr><tr><td>FED7 0000h-FED7 4FFFh</td><td>Internal Device</td><td>Security feature related</td></tr><tr><td>64Kb(MBAR) anywhere in 64-bit address range</td><td>XHCI</td><td>Enable via standard PCI mechanism(D20:F0)</td></tr><tr><td>2MB(BAR)&amp;4Kb(BAR1) anywhere in 64-bit address range</td><td>USB extensible Device Controller Interface(xDCI)</td><td>Enable via standard PCI mechanism(D20:F1)</td></tr><tr><td>16kB(HDAxBA),4kB(SPCxBA)&amp;1MB(ADSPxBA) anywhere in 64-bit address range</td><td>Converged Audio, Video Speech(cAVS) Controller</td><td>Enable via standard PCI mechanism(D20:F3)</td></tr><tr><td>64 KB anywhere in 4 GB range</td><td>eSPI</td><td>LPC Generic Memory Range. Enable via setting bit[0] of the LPC Generic Memory Range Register(D31:F0:offset98h).</td></tr><tr><td>32B(SMBBAR) anywhere in 64-bit address range</td><td>SM Bus</td><td>Enable via standard PCI mechanism(D31:F4)</td></tr><tr><td>2 KB anywhere above 64 KB to 4 GB range</td><td>SATA Controller(AHCI)</td><td>Enable via standard PCI mechanism(D23:F0)</td></tr><tr><td>Memory Base/Limit anywhere in 4 GB range</td><td>PCI Express Root Ports1-7</td><td>Enable via standard PCI mechanism(D28:F[0:6])</td></tr><tr><td>Pre-fetchable Memory Base/Limit anywhere in 64-bit address range</td><td>PCI Express Root Ports1-7</td><td>Enable via standard PCI mechanism(D28:F[0:6])</td></tr><tr><td>16B(HECIx_MMIO_BAR) anywhere in 64-bit address range</td><td>HECI #0,#1,#2,#4</td><td>Enable via standard PCI mechanism(D22:F[0:1,4:5])</td></tr><tr><td>16 MB(SBREG_BAR) anywhere in 64-bit address range</td><td>P2SB</td><td>Enable via standard PCI mechanism(D31:F1)</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Intel(R) Serial I/O Controllers</td><td>Enable via standard PCI mechanism(D30:F[0:3,D25:F[0:2],D21:F[0:3],D18:F0,D16:F[1:0])</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit</td><td>Embedded Multi Media Card(eMMC)</td><td>Enable via standard PCI mechanism(D26:F0)</td></tr><tr><td>address range</td><td>Controller</td><td></td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Secure Digital (SD) &amp; Secure Digital I/O Controller</td><td>Enable via standard PCI mechanism(D26:F1)</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Universal Flash Storage(UFS) Controller</td><td>Enable via standard PCI mechanism(D18:F[5,7])</td></tr></table>

6.2. Fixed I/O Address Range Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>020-021</td><td>Interrupt Controller</td></tr><tr><td>024-025</td><td>Interrupt Controller</td></tr><tr><td>028-029</td><td>Interrupt Controller</td></tr><tr><td>02C-02D</td><td>Interrupt Controller</td></tr><tr><td>02E-02F</td><td>Super I/O</td></tr><tr><td>030-031</td><td>Interrupt Controller</td></tr><tr><td>034-035</td><td>Interrupt Controller</td></tr><tr><td>038-039</td><td>Interrupt Controller</td></tr><tr><td>03C-03D</td><td>Interrupt Controller</td></tr><tr><td>040</td><td>Timer/Counter</td></tr><tr><td>042-043</td><td>Timer/Counter</td></tr><tr><td>04E-04F</td><td>Microcontroller</td></tr><tr><td>050</td><td>Timer/Counter</td></tr><tr><td>052-053</td><td>Timer/Counter</td></tr><tr><td>060</td><td>Keyboard Controller</td></tr><tr><td>061</td><td>NMI Controller</td></tr><tr><td>062</td><td>Microcontroller</td></tr><tr><td>063</td><td>NMI Controller</td></tr><tr><td>064</td><td>Keyboard Controller</td></tr><tr><td>065</td><td>NMI Controller</td></tr><tr><td>066</td><td>Microcontroller</td></tr><tr><td>067</td><td>NMI Controller</td></tr><tr><td>070</td><td>RTC Controller</td></tr><tr><td>071</td><td>RTC Controller</td></tr><tr><td>072</td><td>RTC Controller</td></tr><tr><td>073</td><td>RTC Controller</td></tr><tr><td>074</td><td>RTC Controller</td></tr><tr><td>075</td><td>RTC Controller</td></tr><tr><td>076-077</td><td>RTC Controller</td></tr><tr><td>080</td><td>eSPI or PCIe</td></tr><tr><td>084-086</td><td>eSPI or PCIe</td></tr><tr><td>088</td><td>eSPI or PCIe</td></tr><tr><td>08C-08E</td><td>eSPI or PCIe</td></tr><tr><td>090</td><td>eSPI</td></tr><tr><td>092</td><td>Reset Generator</td></tr><tr><td>094-096</td><td>eSPI</td></tr><tr><td>098</td><td>eSPI</td></tr><tr><td>09C-09E</td><td>eSPI</td></tr><tr><td>0A0-0A1</td><td>Interrupt Controller</td></tr><tr><td>0A4-0A5</td><td></td></tr><tr><td>0A8-0A9</td><td></td></tr><tr><td>0AC-0AD</td><td></td></tr><tr><td>0B0-0B1</td><td>Interrupt Controller</td></tr><tr><td>0B2-0B3</td><td>Power Management</td></tr><tr><td>0B4-0B5</td><td>Interrupt Controller</td></tr><tr><td>0B8-0B9</td><td></td></tr><tr><td>0BC-0BD</td><td></td></tr><tr><td>200-207</td><td>Gameport Low</td></tr><tr><td>208-20F</td><td>Gameport High</td></tr><tr><td>4D0-4D1</td><td>Interrupt Controller</td></tr><tr><td>CF9</td><td>Reset Generator</td></tr></table>

# 6.3. Variable I/O Address Range Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>ACPI</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>SMBus</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>TCO</td></tr><tr><td>3 ranges in 64 KB I/O Space</td><td>Parallel Port</td></tr><tr><td>8 ranges in 64 KB I/O Space</td><td>Serial Port1</td></tr><tr><td>8 ranges in 64 KB I/O Space</td><td>Serial Port2</td></tr><tr><td>2 ranges in 64 KB I/O Space</td><td>Serial Port3</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>Floppy Disk Controller</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 1</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 2</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 3</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 4</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>Serial ATA Index/Data Pair</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>PCI Express Root Ports</td></tr></table>

# 6.4. PCI Configuration Space Map

PCH Global Device IDs

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Dependency / Comments</td></tr><tr><td>00h</td><td>31h</td><td>00h</td><td>Enhanced Serial Peripheral Interface(eSPI) Controller</td></tr><tr><td>00h</td><td>31h</td><td>01h</td><td>Primary to Sideband Bridge(P2SB)</td></tr><tr><td>00h</td><td>31h</td><td>02h</td><td>Power Management Controller(PMC)</td></tr><tr><td>00h</td><td>31h</td><td>03h</td><td>Converged Audio, Video, Speech(cAVS) Controller</td></tr><tr><td>00h</td><td>31h</td><td>04h</td><td>System Management Bus(SMBus) Controller</td></tr><tr><td>00h</td><td>31h</td><td>05h</td><td>Serial Peripheral Interface(SPI) Controller for Flash &amp; TPM</td></tr><tr><td>00h</td><td>31h</td><td>07h</td><td>Intel(R) Trace Hub</td></tr><tr><td>00h</td><td>30h</td><td>00h</td><td>Intel(R) Serial I/O: Universal Asynchronous Receiver/Transmitter(UART) Controller #0</td></tr><tr><td>00h</td><td>30h</td><td>01h</td><td>Intel(R) Serial I/O: UART Controller #1</td></tr><tr><td>00h</td><td>30h</td><td>02h</td><td>Intel(R) Serial I/O: Serial Peripheral Interface(SPI) Controller #0</td></tr><tr><td>00h</td><td>30h</td><td>03h</td><td>Intel(R) Serial I/O:SPI Controller #1</td></tr><tr><td>00h</td><td>30h</td><td>04h</td><td>Gigabit Ethernet TSN Controller</td></tr><tr><td>00h</td><td>30h</td><td>06h</td><td>High Precision Event Timer(HPET)</td></tr><tr><td>00h</td><td>30h</td><td>07h</td><td>I/O Advanced Programmable Interrupt Controller(IOAPIC)</td></tr><tr><td>00h</td><td>29h</td><td>00h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE):Local Host to PSE(LH2OSE) IPC</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE):Gigabit Ethernet TSN Controller #0(RGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) PSE: Gigabit Ethernet TSN Controller #0(SGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) PSE: Gigabit Ethernet TSN Controller #0(SGMII:2.5 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE: Gigabit Ethernet Time Sensitive Networking(TSN) Controller #1(RGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE: Gigabit Ethernet TSN Controller #1(SGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE: Gigabit Ethernet TSN Controller #1(SGMII:2.5 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>03h</td><td>Intel(R) PSE: Direct Memory Access (DMA) Controller #0</td></tr><tr><td>00h</td><td>29h</td><td>04h</td><td>Intel(R) PSE: DMA Controller #1</td></tr><tr><td>00h</td><td>29h</td><td>05h</td><td>Intel(R) PSE: DMA Controller #2</td></tr><tr><td>00h</td><td>29h</td><td>06h</td><td>Intel(R) PSE: Pulse Width Modulation(PWM) Controller</td></tr><tr><td>00h</td><td>29h</td><td>07h</td><td>Intel(R) PSE: Analog to Digital Converter(ADC)</td></tr><tr><td>00h</td><td>28h</td><td>00h</td><td>PCI Express*(PCIe*) Root Port #0(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>01h</td><td>PCIe* Root Port #1(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>02h</td><td>PCIe* Root Port #2(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>03h</td><td>PCIe* Root Port #3(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>04h</td><td>PCIe* Root Port #4(PCIe 0,Multi VC)</td></tr><tr><td>00h</td><td>28h</td><td>05h</td><td>PCIe* Root Port #5(PCIe 0, Multi VC)</td></tr><tr><td>00h</td><td>28h</td><td>06h</td><td>PCIe* Root Port #6(PCIe 0, Multi VC)</td></tr><tr><td>00h</td><td>27h</td><td>00h</td><td>Intel(R) PSE: Inter-Integrated Circuit(I2C) Controller #0</td></tr><tr><td>00h</td><td>27h</td><td>01h</td><td>Intel(R) PSE: I2C Controller #1</td></tr><tr><td>00h</td><td>27h</td><td>02h</td><td>Intel(R) PSE: I2C Controller #2</td></tr><tr><td>00h</td><td>27h</td><td>03h</td><td>Intel(R) PSE: I2C Controller #3</td></tr><tr><td>00h</td><td>27h</td><td>04h</td><td>Intel(R) PSE: I2C Controller #4</td></tr><tr><td>00h</td><td>27h</td><td>05h</td><td>Intel(R) PSE: I2C Controller #5</td></tr><tr><td>00h</td><td>27h</td><td>06h</td><td>Intel(R) PSE: I2C Controller #6</td></tr><tr><td>00h</td><td>26h</td><td>00h</td><td>Embedded Multi Media Card (eMMC) Controller</td></tr><tr><td>00h</td><td>26h</td><td>01h</td><td>Secure Digital (SD) &amp; Secure Digital I/O Controller</td></tr><tr><td>00h</td><td>26h</td><td>03h</td><td>Intel(R) Safely Island(Intel(R) SI) Controller</td></tr><tr><td>00h</td><td>25h</td><td>00h</td><td>Intel(R) Serial I/O: Inter-Integrated Circuit(I2C) Controller #4</td></tr><tr><td>00h</td><td>25h</td><td>01h</td><td>Intel(R) Serial I/O I2C Controller #5</td></tr><tr><td>00h</td><td>25h</td><td>02h</td><td>Intel(R) Serial I/O: Universal Asynchronous Receiver/Transmitter(UART) Controller #2</td></tr><tr><td>00h</td><td>24h</td><td>00h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE:I2C Controller #7</td></tr><tr><td>00h</td><td>24h</td><td>01h</td><td>Intel(R) PSE: Controller Area Network (CAN) Controller #0</td></tr><tr><td>00h</td><td>24h</td><td>02h</td><td>Intel(R) PSE: CAN Controller #1</td></tr><tr><td>00h</td><td>24h</td><td>03h</td><td>Intel(R) PSE: Quadrature Encoder Peripheral,(QEP) Controller #0</td></tr><tr><td>00h</td><td>24h</td><td>04h</td><td>Intel(R) PSE:QEP Controller #1</td></tr><tr><td>00h</td><td>24h</td><td>05h</td><td>Intel(R) PSE: QEP Controller #2</td></tr><tr><td>00h</td><td>24h</td><td>06h</td><td>Intel(R) PSE: QEP Controller #3</td></tr><tr><td>00h</td><td>22h</td><td>00h</td><td>Intel(R)</td></tr><tr><td>00h</td><td>22h</td><td>01h</td><td>Intel(R) CSE:HECI #1</td></tr><tr><td>00h</td><td>22h</td><td>04h</td><td>Intel(R) CSE:HECI #2</td></tr><tr><td>00h</td><td>22h</td><td>05h</td><td>Intel(R) CSE:HECI #3</td></tr><tr><td>00h</td><td>21h</td><td>00h</td><td>Intel(R) Serial I/O: Inter-Integrated Circuit(I2C) Controller #0</td></tr><tr><td>00h</td><td>21h</td><td>01h</td><td></td></tr><tr><td>00h</td><td>21h</td><td>02h</td><td>Intel(R) Serial I/O:I2C Controller #1</td></tr><tr><td>00h</td><td>21h</td><td>03h</td><td>Intel(R) Serial I/O:I2C Controller #2</td></tr><tr><td>00h</td><td>21h</td><td>07h</td><td>Intel(R) Serial I/O:I2C Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Intel(R) PSE: Serial Peripheral Interface(SPI) Controller #0</td></tr><tr><td>00h</td><td>19h</td><td>01h</td><td>Intel(R) PSE: SPI Controller #1</td></tr><tr><td>00h</td><td>19h</td><td>02h</td><td>Intel(R) PSE: SPI Controller #2</td></tr><tr><td>00h</td><td>19h</td><td>03h</td><td>Intel(R) PSE: SPI Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>04h</td><td>Intel(R) PSE: General Purpose Input Output(GPIO) Controller #0</td></tr><tr><td>00h</td><td>19h</td><td>05h</td><td>Intel(R) PSE: General Purpose Input Output(GPIO) Controller #1</td></tr><tr><td>00h</td><td>18h</td><td>00h</td><td>Intel(R) Serial I/O:SPI Controller #2</td></tr><tr><td>00h</td><td>18h</td><td>03h</td><td>Intel(R) Converged Security Engine(Intel(R) CSE):UMA Access</td></tr><tr><td>00h</td><td>18h</td><td>04h</td><td>Intel(R) CSE: Intel(R) PTT DMA Controller</td></tr><tr><td>00h</td><td>18h</td><td>05h</td><td>Universal Flash Storage(UFS) Controller #0</td></tr><tr><td>00h</td><td>18h</td><td>07h</td><td>UFS Controller #1</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Intel(R) PSE: Universal Asynchronous Receiver/Transmitter(UART) Controller#0</td></tr><tr><td>00h</td><td>17h</td><td>01h</td><td>Intel(R) PSE: UART Controller #1</td></tr><tr><td>00h</td><td>17h</td><td>02h</td><td>Intel(R) PSE: UART Controller #2</td></tr><tr><td>00h</td><td>17h</td><td>03h</td><td>Intel(R) PSE :UART Controller #3</td></tr><tr><td>00h</td><td>17h</td><td>04h</td><td>Intel(R) PSE: UART Controller #4</td></tr><tr><td>00h</td><td>17h</td><td>05h</td><td>Intel(R) PSE: UART Controller #5</td></tr><tr><td>00h</td><td>17h</td><td>06h</td><td>Intel(R) PSE: Inter-Integrated Circuit Sound(I2S) Controller #0</td></tr><tr><td>00h</td><td>17h</td><td>07h</td><td>Intel(R) PSE: I2S Controller #1</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Intel(R) Serial I/O: Inter-Integrated Circuit(I2C) Controller #6</td></tr><tr><td>00h</td><td>16h</td><td>01h</td><td>Intel(R) Serial I/O: I2C Controller #7</td></tr><tr><td>00h</td><td>16h</td><td>05h</td><td>Integrated Error Handler(IEH)</td></tr></table>

# 6.5. PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>xHCI Controller</td><td>SATA Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td></td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td></td></tr><tr><td>Int3</td><td>INTD:19</td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>PCIe Port 1</td><td>PCIe Port 2</td><td>PCIe Port 3</td><td>PCIe Port 4</td><td>PCIe Port 5</td><td>PCIe Port 6</td><td>PCIe Port 7</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td></tr></table>

# 6.6. SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>PTN3460</td><td>C0h</td></tr></table>

# 7. BIOS Configurations

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information System Information Board Information System Date and Time Access Level</td><td>CPU Configuration Power &amp; Performance Graphics Configuration AMI Graphic Output Protocol Policy Power Management System Management Thermal Management Watchdog Timer Super IO Configuration Miscellaneous USB Configuration Serial Port Console Redirection Network Stack Configuration Trusted Computing</td><td>System Agent (SA) Configuration PCH-IO Configuration</td><td>Setup Administrator Password User Password Secure Boot</td><td>Boot Configuration FIXED BOOT ORDER Priorities UEFI USB Key Drive BBS Priorities</td><td>Save Change and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Boot Override</td></tr></table>

# 7.2. Main

7.2.1. Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>ADLINK BIOS version</td></tr><tr><td>Build Date</td><td>Info only</td><td>ADLINK BIOS Build Date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Display GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display ME FW Version</td></tr><tr><td>BIOS Boot Source</td><td>Info only</td><td>Display BIOS Boot Source</td></tr></table>

7.2.2. Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board version</td><td>Info only</td><td>Display CPU Board Version.</td></tr><tr><td>CPU Board String</td><td>Info only</td><td>Display CPU Board String.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU Frequency.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Installed Memory Size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH SKU Version</td></tr></table>

7.2.3. Main > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Board Information</td><td>Info only</td><td></td></tr><tr><td>Serial Number</td><td>Info only</td><td>Display SEMA serial Number.</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Display SEMA manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Display SEMA last repair date.</td></tr><tr><td>MAC ID</td><td>Info only</td><td>Display SEMA MAC ID.</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td></td></tr><tr><td>Total Runtime</td><td>Info only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>The Boot counter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

# 7.2.4. Main > System Date/Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Info only</td><td></td></tr><tr><td>System Time</td><td>Info only</td><td></td></tr></table>

# 7.2.5. Main > Access Levl

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Configuration</td><td>Info only</td><td></td></tr><tr><td>Type</td><td>Info only</td><td>Socket Specific CPU Information.</td></tr><tr><td>ID</td><td>Info only</td><td>Display Microcode Patch.</td></tr><tr><td>Speed</td><td>Info only</td><td>Display Max CPU speed.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display Min CPU stepping.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display VMX support info.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display SMX/TXT support info.</td></tr><tr><td>Intel Virtualization Technology</td><td>Disabled Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Processor Cores</td><td>ALL 1 2 3</td><td>Number of cores to enable in each processor package.</td></tr></table>

7.3.2. Advanced > Power & Performance

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU – Power Management Control</td><td>Submenu</td><td>CPU- Power Management Control Options</td></tr><tr><td>GT – Power Management Control</td><td>Submenu</td><td>GT- Power Management Control</td></tr></table>

7.3.2.1. Advanced > Power & Performance > CPU – Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU – Power Management Control</td><td>Info only</td><td></td></tr><tr><td>P0 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P1 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P2 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P3 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td>Boot performance mode</td><td>Max BatteryMax Non-Turbo PerformanceTurbo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>DisabledEnabled</td><td>Allows more than two frequency ranges to be supported</td></tr><tr><td>Race To Halt (RTH)</td><td>DisabledEnabled</td><td>Enable/Disable Race To Halt features. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>DisabledEnabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>DisabledEnabled</td><td>Enable EPP grouping (default bit 29 = 0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (BIT 29 =1, command 0x11) Autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>DisabledEnabled</td><td>Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b, subcommand 0x3 to1. This will allow OOB EPB PECI override control</td></tr><tr><td>HwP Fast MSR Support</td><td>DisabledEnabled</td><td>Enable/Disable HwP Fast MSR Support for IA32_HwP_REQUEST MSR.</td></tr><tr><td>HDC Control</td><td>DisabledEnabled</td><td>This option allows HDC configuration. Disabled: Disable HDC Enabled: Can be enabled by OS if OS native support is available.</td></tr><tr><td>View/Configure Turbo Options</td><td>Submenu</td><td>View/Configure Turbo Options</td></tr><tr><td>CPU VR Settings</td><td>Submenu</td><td>CPU VR Settings</td></tr><tr><td>Platform PL1 Enable</td><td>DisabledEnabled</td><td>Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Power Limit 4 override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Enhanced C-states</td><td>DisabledEnabled</td><td>Enable/DISABLE C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Un-demotion</td><td>DisabledC1</td><td>Configure C-State Un-demotion</td></tr><tr><td>Package C-State Demotion</td><td>Disabled</td><td>Package C-State Demotion</td></tr><tr><td></td><td>Enabled</td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td>Package C-State Un-demotion</td><td>DisabledEnabled</td><td>Package C-State Un-demotion</td></tr><tr><td>CState Pre-Wake</td><td>DisabledEnabled</td><td>Disable – Sets bit 30 of POWER_CTL MSR(0x1FC) to 1 to disable the Cstate Pre-Wake</td></tr><tr><td>IO MWAIT Redirection</td><td>DisabledEnabled</td><td>When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset)</td></tr><tr><td>Package C State Limit</td><td>C0/C1C2C3C6C7C7SC8C9C10Cpu DefaultAuto</td><td>Maximum Package C State Limit Setting. CPU Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit.</td></tr><tr><td>C6/C7 Short Latency Control(MSR 0x60B)</td><td>Info only</td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C6/C7 Long Latency Control(MSR 0x60C)</td><td>Info only</td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C8 Latency Control(MSR 0x633)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C9 Latency Control(MSR 0x634)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C10 Latency Control(MSR 0x635)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>Thermal Monitor</td><td>DisabledEnabled</td><td>Enable/Disable Thermal Monitor</td></tr><tr><td>Interrupt Redirection mode Selection</td><td>Fixed PriorityRound robinHash VectorNo Change</td><td>Interrupt Redirection Mode Select for Logical Interrupts</td></tr><tr><td>Timed MWAIT</td><td>DisabledEnabled</td><td>Enable/Disable Timed MWAIT Support</td></tr><tr><td>Custom P-state Table</td><td>Submenu</td><td></td></tr><tr><td>EC Turbo Control Mode</td><td>DisabledEnabled</td><td>Enable/Disable EC Turbo Control mode</td></tr><tr><td>Energy Performance Gain</td><td>DisabledEnabled</td><td>Enable/Disable Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>26</td><td>Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis.</td></tr><tr><td>EPG DIMM ldd3P</td><td>11</td><td>Active power-down current(Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis.</td></tr><tr><td>Power Limit 3 Settings</td><td>Submenu</td><td></td></tr><tr><td>CPU Lock Configuration</td><td>Submenu</td><td>CPU Lock Configuration</td></tr></table>

7.3.2.1.1. Advanced > Power & Performance > CPU – Power Management Control > View/Configure Turbo Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Current Turbo Settings</td><td>Info only</td><td></td></tr><tr><td>Max Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Min Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Package TDP Limit</td><td>Info only</td><td></td></tr><tr><td>Power Limit 1</td><td>Info only</td><td></td></tr><tr><td>Power Limit 2</td><td>Info only</td><td></td></tr><tr><td>1-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>2-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>3-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>4-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>Energy Efficient P-state</td><td>DisabledEnabled</td><td>Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR</td></tr><tr><td>Package Power Limit MSR Lock</td><td>DisabledEnabled</td><td>Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.</td></tr><tr><td>Power Limit 1 Override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 1 override. If this option is disabled, BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.</td></tr><tr><td>Power Limit 2 Override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2.</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in milliWatts. BIOS will round tothe nearest 1/8W when programming. If the value is 0, BIOS will program this value as 1.25*TDP. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td>1-Core Ratio Limit Override</td><td>19</td><td>1-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.</td></tr><tr><td>2-Core Ratio Limit Override</td><td>19</td><td>2-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>3-Core Ratio Limit Override</td><td>19</td><td>3-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>4-Core Ratio Limit Override</td><td>19</td><td>4-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>Energy Efficient Turbo</td><td>DisabledEnabled</td><td>Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.</td></tr></table>

# 7.3.2.1.2. Advanced > Power & Performance > CPU – Power Management Control > CPU VR Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU VR Settings</td><td>Info only</td><td></td></tr><tr><td>PSYS Slope</td><td>0</td><td></td></tr><tr><td>PSYS Offset</td><td>0</td><td></td></tr><tr><td>PSYS PMax Power</td><td>+ -</td><td></td></tr><tr><td>Acoustic Noise Settings</td><td>Submenu</td><td>Configure Acoustic Noise Settings for IA, GT and SA domains</td></tr><tr><td>VccIn VR Settings</td><td>Submenu</td><td>VccIn VR Settings</td></tr><tr><td>RFI Settings</td><td>Submenu</td><td>RFI Settings</td></tr></table>

# 7.3.2.1.3. Advanced > Power & Performance > CPU – Power Management Control > Custom P-state Table

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Custom P-state Table</td><td>Info only</td><td></td></tr><tr><td>Number of P states</td><td>0</td><td>Sets the number of custom P-states. At least 2 states must be present.</td></tr></table>

# 7.3.2.1.4. Advanced > Power & Performance > CPU – Power Management Control > CPU Lock Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CFG Lock</td><td>Disabled</td><td>Configure MSR 0xE2[15], CFG Lock bit</td></tr><tr><td></td><td>Enabled</td><td></td></tr><tr><td>Overclocking Lock</td><td>Disabled Enabled</td><td>Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR</td></tr></table>

7.3.2.2. Advanced > Power & Performance > GT – Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GT – Power Management Control</td><td>Info only</td><td></td></tr><tr><td>RC6(Render Standby)</td><td>DisabledEnabled</td><td></td></tr><tr><td>Maximum GT frequency</td><td>Default Max Frequency100Mhz150Mhz200Mhz250Mhz300Mhz350Mhz400Mhz450Mhz500Mhz550Mhz600Mhz650Mhz700Mhz750Mhz800Mhz850Mhz900Mhz950Mhz1000Mhz1050Mhz1100Mhz1150Mhz1200Mhz</td><td>Maximum GT frequency limited by the user. Choose between 400MHz (RPN) and 400MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU</td></tr><tr><td>Disable Turbo GT frequency</td><td>EnabledDisabled</td><td>Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited</td></tr></table>

7.3.3. Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>LVDS Backlight Mode</td><td>EC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight</td><td>Submenu</td><td></td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort WithHDMI/DVI Compatible</td><td>DDI port 1 function choose to Display Port or HDMI</td></tr><tr><td>DDI port 2</td><td>No DeviceDisplay PortHDMIDisplayPort WithHDMI/DVI Compatible</td><td>DDI port 2 function choose to Display Port or HDMI</td></tr></table>

7.3.3.1. Advanced > Graphics Configuration > LVDS Backlight

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS Backlight</td><td>Info Only</td><td></td></tr><tr><td>LVDS Backlight Brightness</td><td>0-255</td><td>A change takes effect immediately.The value range starts by 0 and ends by 255.</td></tr></table>

7.3.4. Advanced> AMI Graphic Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel (R) Graphics Controller</td><td>Info Only</td><td></td></tr><tr><td>Intel (R) GOP Driver</td><td>Info Only</td><td></td></tr><tr><td>Output Select</td><td>DP1[ACTIVE Current]</td><td>Output Interface</td></tr></table>

7.3.5. Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Management</td><td>Info Only</td><td></td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables or Disables BIOS ACPI Auto Configuration</td></tr></table>

7.3.6. Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info Only</td><td></td></tr><tr><td>Version</td><td>Info Only</td><td>Display SEMA Module Version.</td></tr><tr><td>SEMA Firmware</td><td>Info Only</td><td>Display SEMA Firmware Version.</td></tr><tr><td>SEMA Flags</td><td>Submenu</td><td>Display SEMA Flags</td></tr><tr><td>SEMA Features</td><td>Info</td><td>Display SEMA Supported Features</td></tr></table>

7.3.6.1. Advanced > System Management > SEMA Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Flags</td><td>Info Only</td><td></td></tr><tr><td>BIOS Select</td><td>Info Only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Info Only</td><td></td></tr></table>

7.3.7. Advanced > Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info Only</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C100 C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Active Cooling Trip Point</td><td>40 C50 C60 C70 CRefer to BMC</td><td>This value is the temperature threshold of the active cooling trip point.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled</td></tr><tr><td>Temperature and Fan Speed</td><td>Submenu</td><td></td></tr></table>

7.3.7.1. Advanced > Thermal Management > Thermal and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current CPU Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Display Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Display Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Display Max Board Temperature</td></tr><tr><td>CPU Fan Speed</td><td>Info Only</td><td>Display CPU Fan Speed</td></tr><tr><td>Smart Fan</td><td>Submenu</td><td></td></tr></table>

7.3.7.1.1 Advanced > Thermal Management > Thermal and Fan Speed > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info Only</td><td></td></tr><tr><td>CPU Smart Fan Temperature Source</td><td>CPU Sensor Board Sensor</td><td>CPU Smart Fan Temperature Source</td></tr><tr><td>Trigger Point 1/2/3/4</td><td>Info Only</td><td></td></tr><tr><td>Trigger Temperature</td><td>40/55/70/85</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>25/50/75/100</td><td>PWM Level</td></tr></table>

7.3.8. Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>DisabledEnabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up.Pressing F12 druing start up disables the Power Up Watchdog</td></tr><tr><td>Timeout</td><td>65535</td><td>Here you can enter the time the Power Up Watchdog should wait until it resets the system.The value range starts by 24 and ends by 65535</td></tr><tr><td>RunTime Watchdog</td><td>DisabledEnabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>30</td><td>Here you can enter the time the Runtime Watchdog should wait until it resets the system.The value range starts by 30 and ends by 65535.</td></tr></table>

7.3.9. Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>IT5121E Super IO Configuration</td><td>Submenu</td><td>System Super IO Chip Parameters.</td></tr><tr><td>W83627DHGSEC Super IO Configuration</td><td>Submenu</td><td>System Super IO Chip Parameters.</td></tr></table>

7.3.9.1. Advanced > Super IO Configuration > IT5121E Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IT5121E Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1/2</td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h/2F8h; IRQ=4;IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr><tr><td>Change Settings</td><td>NormalHigh Speed</td><td>Select an optimal settings for Super IO Device</td></tr></table>

7.3.9.2. Advanced > Super IO Configuration > W83627DHGSEC Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2 (COMB).</td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=248h; IRQ=11;IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.10. Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM3</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM4</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>Legacy Console Redirection</td><td>Info only</td><td></td></tr><tr><td>Legacy Console Redirection Settings</td><td>Submenu</td><td>Legacy Console Redirection Settings</td></tr></table>

7.3.10.1. Advanced > Serial Console Redirection > Console Redirection Settings (w/ COM1 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS.When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.3.10.2. Advanced > Serial Console Redirection > Console Redirection Settings (w/ COM2 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, functionkeys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.3.10.3. Advanced > Serial Console Redirection > Console Redirection Settings (w/ COM3 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM3</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Teriminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad onPutty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always Enable BootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.3.10.4. Advanced > Serial Console Redirection > Console Redirection Settings (w/ COM4 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM4</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as anadditional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.3.10.5. Advanced > Serial Console Redirection > Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy Serial Redirection Port</td><td>COM1COM2COM3COM4</td><td>Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages</td></tr></table>

7.3.11. Advanced > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info Only</td><td></td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions (S3 &amp; S4) to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. ATX: OS will turn off system power when shutdown.</td></tr><tr><td>I2C Speed Control</td><td>100 kbps400 kbps</td><td>I2C Speed Control</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr><tr><td>SD Card/GPIO Mode</td><td>GPIOSD Card</td><td>Select SD Card or GPIO function.</td></tr><tr><td>WOL From S5</td><td>ONOFF</td><td>Select SMBUS Routine</td></tr></table>

7.3.12. Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attachment USB devices.</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for Oses without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable / Disable USB Mass Storage Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.&#x27;Auto&#x27; uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.</td></tr></table>

# 7.3.13. Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Disable Enable</td><td>Enable / Disable UEFI Network Stack.</td></tr></table>

# 7.3.14. Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>TPM20 Device Found</td><td>Info Only</td><td></td></tr><tr><td>Security Device Support</td><td>Disable Enable</td><td>Enables or Disable BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.</td></tr></table>

# 7.4. Chipset

7.4.1. Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td>Graphics Configuration</td></tr><tr><td>VT-D</td><td>DisabledEnabled</td><td>VT-d capability</td></tr><tr><td>GNA Device</td><td>DisabledEnabled</td><td>Enable/Disable SA GNA Device.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>DisabledEnabled</td><td>Enable/Disable above 4GB Memory / Mapped I/O BIOS assignment. This is enabled automatically when Aperture Size is set to 2048MB.</td></tr></table>

7.4.1.1. Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Thermal Configuration</td><td>Submenu</td><td>Memory Thermal Configuration</td></tr><tr><td>Memory Training Algorithms</td><td>Submenu</td><td>Enable/Disable Memory Training Algorithms.</td></tr><tr><td>Memory Configuration</td><td>Info Only</td><td></td></tr><tr><td>Memory RC Version</td><td>Info Only</td><td></td></tr><tr><td>Memory Data Rate</td><td>Info Only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info Only</td><td></td></tr><tr><td>Channel 0 Slot 0</td><td>Info Only</td><td></td></tr><tr><td>Channel 0 Slot 1</td><td>Info Only</td><td></td></tr><tr><td>Channel 1 Slot 0</td><td>Info Only</td><td></td></tr><tr><td>Size</td><td>Info Only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info Only</td><td></td></tr><tr><td>Manufacturer</td><td>Info Only</td><td></td></tr><tr><td>Channel 1 Slot 1</td><td>Info Only</td><td></td></tr><tr><td>Memory ratio/reference clock options moved to Overclock-&gt;Memory-&gt;Custom Profile menu</td><td>Info Only</td><td></td></tr><tr><td>MRC ULT Safe Config</td><td>DisabledEnabled</td><td>MRC ULT Safe Config for P0</td></tr><tr><td>Safe Mode Support</td><td>DisabledEnabled</td><td>Safe Mode enable support. Option will be used for changes/WAs that may affect an stable MRC</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067120013331400......4267</td><td>Maximum Memory Frequency in Mhz. Must divide by 133 or 100 according to the refclk. In Gear2 must divide by 266 or 200. Lowest Gear2 speed is 2133</td></tr><tr><td>HOB Buffer Size</td><td>Auto1B1KBMax (assuming 63KB total HOB size)</td><td>Size to set HOB Buffer</td></tr><tr><td>Max TOLUD</td><td>Dynamioc1 GB1.25 GB......3.5GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller</td></tr><tr><td>SA GV</td><td>DisabledFixed LowFixed Mid Fixed High Enabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency switching.</td></tr><tr><td>DDR Speed Control</td><td>Auto Manual</td><td>DDR Frequency and Gear1 / Gear2 control for all SAGV points</td></tr><tr><td>Retrain on Fast Fail</td><td>Disabled Enabled</td><td>Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled</td></tr><tr><td>DDR4_1DPC</td><td>Disabled Enabled on DIMM0 only Enabled on DIMM1 only Enabled</td><td>DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, or on both</td></tr><tr><td>Enable RH Prevention</td><td>Disabled Enabled</td><td>Actively prevent Row Hammer</td></tr><tr><td>REFRESH_PANIC_WM</td><td>9</td><td>Range 1-9, default 9</td></tr><tr><td>REFRESH_HP_WM</td><td>8</td><td>Range 1-9, default 8</td></tr><tr><td>Exit On Failure (MRC)</td><td>Disabled Enabled</td><td>Exit On Failure for MRC training steps</td></tr><tr><td>Enable/Disable IED (Intel Enhanced Debug)</td><td>Enabled Disabled</td><td>Intel Enhanced Debug requires 4MB Runtime memory</td></tr><tr><td>Ch Hash Support</td><td>Disabled Enabled</td><td>Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode</td></tr><tr><td>Ch Hash Mask</td><td>12492</td><td>Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6}</td></tr><tr><td>Ch Hash Interleaved Bit</td><td>BIT8</td><td>Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlace the channels at a 2 cache line granularity, BIT8 at 4 and BIT9 at 8</td></tr><tr><td>Extended Bank Hashing</td><td>Disabled Enabled</td><td>Extended Bank Hashing</td></tr><tr><td>Per Bank Refresh</td><td>Disabled Enabled</td><td>Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR3, LPDDR4.</td></tr><tr><td>Power Down Mode</td><td>AutoNo Power DownAPDPPD-DLLoff</td><td>CKE Power Down Mode Control</td></tr><tr><td>Page Close Idle Timeout</td><td>EnabledDisabled</td><td>Page Close Idle Timeout Control</td></tr><tr><td>Memory Scrambler</td><td>DisabledEnabled</td><td>Enable/Disable Memory Scrambler support.</td></tr><tr><td>Force ColdReset</td><td>EnabledDisabled</td><td>Force ColdReset OR Choose MrcColdBoot mode, when Coldboot is required during MRC execution. Note: If ME 5.0MB is present, ForceColdReset is required!</td></tr><tr><td>Channel 0 DIMM Control</td><td>Enable both DIMMsDisable DIMM0Disable DIMM1Disable both DIMMS</td><td>Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel 0.</td></tr><tr><td>Channel 1 DIMM Control</td><td>Enable both DIMMsDisable DIMM0Disable DIMM1Disable both DIMMS</td><td>Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel 1.</td></tr><tr><td>Force Single Rank</td><td>DisabledEnabled</td><td>When enabled, only Rank 0 will be used in each DIMM</td></tr><tr><td>Force Single Sub Channel</td><td>DisabledEnabled</td><td>When enabled, single Sub channel will be used in each DIMM</td></tr><tr><td>MRC TASK Debug Print Enable</td><td>0</td><td>This enable debug print for specific MRC task. Please consult value from BWG</td></tr><tr><td>Memory Remap</td><td>EnabledDisabled</td><td>Enable/Disable Memory Remap above 4GB</td></tr><tr><td>Time Measure</td><td>DisabledEnabled</td><td>Enable/Disable printing of the time it takes to execute MRC.</td></tr><tr><td>DLL Weak Lock Support</td><td>DisabledEnabled</td><td>Enable/Disable Dll Weaklock support</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enable/Disable fast path thru the MRC</td></tr><tr><td>Train On Warm boot</td><td>DisabledEnabled</td><td>Enable/Disable training on warm boot</td></tr><tr><td>Rank Margin Tool Per Task</td><td>DisabledEnabled</td><td>Enables/Disables RMT running at every major training step</td></tr><tr><td>Training Tracing</td><td>DisabledEnabled</td><td>Enables/Disables printing of the current trained state at every major training step.</td></tr><tr><td>Lpddr Mem WL Set</td><td>Set ASet B</td><td>Only applicable to LPDDR, Memory Write Latency Set selection (A is default, B will be used if memory devices support it)</td></tr><tr><td>BDAT Memory Test Type</td><td>Rang Margin Tool Rank</td><td>Indicates the type of Memory Training data to populate into the BDAT ACPI table.</td></tr><tr><td>Rank Margin Tool Loop Count</td><td>0</td><td>Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO</td></tr><tr><td>Low Supply for LPDDR4 Data</td><td>DisabledEnabled</td><td>Low Supply for LPDDR4 Data</td></tr><tr><td>Low Supply for LPDDR4 Clock/Command/Control</td><td>DisabledEnabled</td><td>Low Supply for LPDDR4 Clock/Command/Control</td></tr><tr><td>Memory Test on Warm Boot</td><td>DisabledEnabled</td><td>Enable Or Disable Base Memory Test Run on Warm Boot</td></tr></table>

7.4.1.2. Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info Only</td><td></td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIe</td><td>Select which of IGFX/PEG/PCIe Graphics device should be Primary Display Or select HG for HybridGfx.</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>Submenu</td><td>External Gfx Card Primary Display Configuration</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M46M96M128M......60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128256MAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>Intel Graphics Pei Display Peim</td><td>EnabledDisabled</td><td>Enable/Disable Pei (Early) Display</td></tr></table>

# 7.4.1.2.1 Advanced > System Agent (SA) Configuration > Graphics Configuration > External Gfx Card Primary Display Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>Info Only</td><td></td></tr><tr><td>Primary PCIE</td><td>Auto</td><td>SelectAuto/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7 of D28:F0/F1/F2/F3/F4/F5/F6/F7,PCIE8/PCIE9/PCIE10/PCIE11/PCIE12/PCIE13/PCIE14/PCIE15 of D29:F0/F1/F2/F3/F4/F5/F6/F7,PCIE16/PCIE17/PCIE18/PCIE19 ofD27:F0/F1/F2/F3, Graphics device should be Primary PCIE.</td></tr></table>

# 7.4.2. Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH-IO Configuration</td><td>Info Only</td><td>Memory Configuration Parameters</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td>PCI Express Configuration setting</td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td>SATA Device Options Settings</td></tr><tr><td>USB Configuration</td><td>Submenu</td><td>USB Configuration settings</td></tr><tr><td>Security Configuration</td><td>Submenu</td><td>Security Configuration setting</td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td>HD Audio Subsystem Configuration Settings</td></tr><tr><td>Seriallo Configuration</td><td>Submenu</td><td>Seriallo Configuration Settings</td></tr><tr><td>SCS Configuration</td><td>Submenu</td><td>Storage and Communication Subsystem (SCS) Configuration</td></tr><tr><td>PSE Configuration</td><td>Submenu</td><td>Programmable Service Engine (PSE) Configuration</td></tr><tr><td>TSN GBE Configuration</td><td>Submenu</td><td>Time Sensitive Network GBE Configuration</td></tr><tr><td>Enhance Port 80h LPC Decoding</td><td>DisabledEnabled</td><td>Support the word/dword decoding of port 80h behind LPC</td></tr><tr><td>Enable TCO Timer</td><td>DisabledEnabled</td><td>Enable/Disable TCO timer. When disabled, it disables PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.</td></tr><tr><td>Pcie PII SSC</td><td>Auto</td><td>Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.</td></tr><tr><td>SPD Write Disable</td><td>TRUEFALSE</td><td>Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr></table>

7.4.2.1. Chipset > PCH-IO Configuration > PCIE Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info Only</td><td></td></tr><tr><td>DMI Link ASPM Control</td><td>DisabledL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>PCIE Ports 1-4 Configuration</td><td>4x1 Port1x2 2x1 Port2x2 Port1x4 Port</td><td>To configure PCI-E Port 1-4 of PCH.[4X1]:Port 1-4 (x1) and Port 8 (x1) / [1x2 2x1]:Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1) / [2x2]:Port 1-2 (x2) and Port 3-4 (x2) / [1x4]:Port 1 (x4), Ports 2-4 (disabled)</td></tr><tr><td>Port8xh Decode</td><td>DisabledEnabled</td><td></td></tr><tr><td>Peer Memory Write Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td></td></tr><tr><td>PCH PCI Express Clock Gating</td><td>Platform-POREnabledDisabled</td><td></td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td></td></tr><tr><td>PCIe EQ settings</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 1/2/3/4/5/6/7</td><td>Submenu</td><td></td></tr><tr><td>PCIE clocks</td><td>Submenu</td><td></td></tr></table>

# 7.4.2.1.1 Advanced > PCH-IO Configuration > PCI Express Configuration > PCIe EQ settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe EQ override</td><td>DisabledEnabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

# 7.4.2.1.2 Advanced > PCH-IO Configuration > PCI Express Configuration > PCIe Express Root Port 1/2/3/4/5/6/7/

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 1/2/3/4/5/6/7/</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Build-inSlot</td><td>Built-In: a built-in device is connected to this root port.Slot Implemented bit will be clear. Slot: this root port connects to user-accessible slot. Slot Implemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level:Force L0s – Force all links to L0s StateAuto – BIOS auto configureDISABLE – Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>DisabledEnabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>DisabledEnabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>DisabledEnabled</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>DisabledEnabled</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>DisabledEnabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>DisabledEnabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>DisabledEnabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>DisabledEnabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>DisabledEnabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td></td><td>Enabled</td><td></td></tr><tr><td>Advanced Error Reporting</td><td>Disabled Enabled</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Halt Swing</td><td>Disabled Enabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info Only</td><td></td></tr><tr><td>LTR</td><td>Disabled Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manual enter override values. Auto (default): Maintain default bios flow.</td></tr><tr><td>Force LTR Override</td><td>Disabled Enabled</td><td>Force LTR Override for PCH PCIE.</td></tr><tr><td>LTR Lock</td><td>DisabledEnabled</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>Extra options</td><td>Submenu</td><td></td></tr></table>

# 7.4.2.1.2.1 Advanced > PCH-IO Configuration > PCI Express Configuration > PCIe Express Root Port 1/2/3/4/5/6/7 > Extra options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Detect Non-Compliance Device/</td><td>DisabledEnabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr><tr><td>Prefetchable Memory</td><td>10</td><td>Prefetchable Memory Range for this Root Bridge.</td></tr><tr><td>Reserved Memory Alignment</td><td>1</td><td>Reserved Memory Alignment (0 - 31 bits)</td></tr><tr><td>Prefetchable Memory Alignment</td><td>1</td><td>Prefetchable Memory Alignment (0 - 31 bits)</td></tr></table>

# 7.4.2.1.3 Advanced > PCH-IO Configuration > PCI Express Configuration > PCIE clocks

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Clock0 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock0</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock1 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock1</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled =CLKREQ will not be used.</td></tr><tr><td>Clock2 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock2</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock3 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock3</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock4 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock4</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock5 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock5</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr></table>

7.4.2.2. Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Configuration</td><td>Info Only</td><td></td></tr><tr><td>SATA Controller</td><td>Submenu</td><td>PCI Express Configuration setting</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Ports Multiplier</td><td>EnabledDisabled</td><td>Ports Multiplier Enable/Disable</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td>RST Legacy OROM/RST UEFI driver will refer to the SWFM configuration to enable/disable the storage features.</td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>Serial ATA Port x</td><td>Info Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info Only</td><td></td></tr><tr><td>Port0</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td>Info Only</td><td></td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this optionenabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td>Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2</td></tr><tr><td>SATA Portx DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>SATA Portx RxPolarity</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 RxPolarity. Default should disable, please check board design before enable it.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO value</td><td>Info Only</td><td></td></tr><tr><td>DM Value</td><td>Info Only</td><td></td></tr></table>

7.4.2.2.1 Advanced > PCH-IO Configuration > SATA Configuration > Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Software Feature Mask Configuration</td><td>Info Only</td><td></td></tr><tr><td>HDD Unlock</td><td>DisabledEnabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>DisabledEnabled</td><td>If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.</td></tr></table>

7.4.2.3. Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>XHCI Compliance Mode</td><td>DisabledEnabled</td><td>Option to enable Compliance Mode. Default is to disable Compliance Mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>xDCI Support</td><td>DisabledEnabled</td><td>Enable/Disable xDCI (USB OTG Device).</td></tr><tr><td>USB2 PHY Sus Well Power Gating</td><td>GEN1GEN2</td><td>Select &#x27;Enabled&#x27; to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H</td></tr><tr><td>USB3 Link Speed Selection</td><td>DisabledEnabled</td><td>This option is to select USB3 Link Speed GEN1 or GEN2</td></tr><tr><td>USB PD0 Programming</td><td>DisabledEnabled</td><td>Select &#x27;Enabled&#x27; if Port Disable Override functionality is used.</td></tr><tr><td>USB Overcurrent</td><td>DisabledEnabled</td><td>Select &#x27;Disabled&#x27; for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>DisabledEnabled</td><td>Select &#x27;Enabled&#x27; if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Port Disable Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB Device/HOST Mode Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB 2.0 and USB 3.0 port device mode</td></tr><tr><td>USB UCSI ACPI device</td><td>DisabledEnabled</td><td>Enable/Disable USB UCSI ACPI device</td></tr></table>

7.4.2.4. Chipset > PCH-IO Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Configuration</td><td>Info Only</td><td></td></tr><tr><td>RTC Memory Lock</td><td>DisabledEnabled</td><td>Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>DisabledEnabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr><tr><td>Force unlock on all GPIO pads</td><td>DisabledEnabled</td><td>If Enabled BIOS will force all GPIO pads to be in unlocked state</td></tr></table>

7.4.2.5. Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio Subsystem Configuration Settings</td><td>Info Only</td><td></td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled.</td></tr></table>

7.4.2.6. Chipset > PCH-IO Configuration > SerialIo Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Seriallo Configuration</td><td>Info Only</td><td></td></tr><tr><td>I2C0 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C1 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C2 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C3 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C4 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C5 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C6 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C7 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>SPI0 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>SPI1 Controller</td><td>DisabledEnabledPost Code Only</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>SPI2 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART0 Controller</td><td>DisabledEnabledCommunication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART1 Controller</td><td>DisabledEnabledCommunication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>UART2 Controller</td><td>DisabledEnabledCommunication port (COM)</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>GPIO IRQ Route</td><td>IRQ14IRQ15</td><td>Route all GPIOs to one of the IRQ.</td></tr><tr><td>Serial IO I2C0 Settings</td><td>Submenu</td><td>Configure Seriallo Controller</td></tr><tr><td>Serial IO SPI1 Settings</td><td>Submenu</td><td>Configure Seriallo Controller</td></tr><tr><td>Serial IO UART0 Settings</td><td>Submenu</td><td>Configure Seriallo Controller</td></tr><tr><td>Serial IO UART1 Settings</td><td>Submenu</td><td>Configure Seriallo Controller</td></tr><tr><td>Serial IO UART2 Settings</td><td>Submenu</td><td>Configure Seriallo Controller</td></tr><tr><td>WITT/MITT I2C Test Device</td><td>DisabledEnabled</td><td>Enable SIO I2C WITT Device and select which are all controller used it</td></tr><tr><td>WITT/MITT SPI Test Device</td><td>DisabledEnabled</td><td>Enable SIO SPI WITT Device and select which are all controller used it</td></tr><tr><td>UART Test Device</td><td>DisabledEnabled</td><td>Enable SIO UART Test Device and select which are all controller used it</td></tr><tr><td>LPSS Device D3 State</td><td>DisabledEnabled</td><td>Enable/Disable the LPSS D3 before entering to OS.</td></tr><tr><td>Additional Serial IO devices</td><td>DisabledEnabled</td><td>When enabled, ACPI will report additional devices connected to Serial IO.</td></tr><tr><td>SerialIO timing parameters</td><td>DisabledEnabled</td><td>Enables additional timing parameters for all SeraialIO controllers.</td></tr></table>

7.4.2.6.1 Advanced > PCH-IO Configuration > SerialIo Configuration > Serial IO I2C0 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial io i2c0 Settings</td><td>Info Only</td><td></td></tr><tr><td>Set Serial IO I2C #0 Speed</td><td>Standard ModeFast ModeFast Plus ModeHigh Speed Mode</td><td>Select Serial IO I2C #0 Speed</td></tr><tr><td>Timing parameters</td><td></td><td></td></tr><tr><td>StandardSpeed SCL High</td><td>429</td><td></td></tr><tr><td>StandardSpeed SCL Low</td><td>495</td><td></td></tr><tr><td>StandardSpeed SDA Hold</td><td>30</td><td></td></tr><tr><td>FastSpeed SCL High</td><td>81</td><td></td></tr><tr><td>FastSpeed SCL Low</td><td>153</td><td></td></tr><tr><td>FastSpeed SDA Hold</td><td>30</td><td></td></tr><tr><td>FastSpeedPlus SCL High</td><td>9</td><td></td></tr><tr><td>FastSpeedPlus SCL Low</td><td>16</td><td></td></tr><tr><td>FastSpeedPlus SDA Hold</td><td>11</td><td></td></tr><tr><td>HighSpeed SCL High</td><td>8</td><td></td></tr><tr><td>HighSpeed SCL Low</td><td>16</td><td></td></tr><tr><td>HighSpeed SDA Hold</td><td>8</td><td></td></tr><tr><td>D0-&gt;D3 idle timeout (screen off)</td><td>200</td><td></td></tr><tr><td>D0-&gt;D3 idle timeout (screen on)</td><td>2000</td><td></td></tr></table>

7.4.2.6.2 Advanced > PCH-IO Configuration > SerialIo Configuration > Serial IO SPI1 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial io SPI1 Settings</td><td>Info Only</td><td></td></tr><tr><td>ChipSelect 0 polarity</td><td>Active LowActive High</td><td>Sets initial polarity for ChipSelect signal</td></tr><tr><td>ChipSelect 1 polarity</td><td>Active LowActive High</td><td>Sets initial polarity for ChipSelect signal</td></tr><tr><td>Delay Rx Clock</td><td>As IsInternalTx ClockRx Clock</td><td>Configure the SPI Delayed Rx Clock option:</td></tr><tr><td>Chip Select 0</td><td>DisabledEnabled</td><td>This enabled SPI device for testing purpose. This option has dependency on WITT device. If WITT device is enabled with SPI, this option will grey out.</td></tr><tr><td>Chip Select 1</td><td>DisabledEnabled</td><td>This enabled SPI device for testing purpose. This option has dependency on WITT device. If WITT device is enabled with SPI, this option will grey out.</td></tr><tr><td>Timing parameters</td><td>Info Only</td><td></td></tr><tr><td>D0-&gt;D3 idle timeout (screen off)</td><td>200</td><td></td></tr><tr><td>D0-&gt;D3 idle timeout (screen on)</td><td>2000</td><td></td></tr></table>

7.4.2.6.3 Advanced > PCH-IO Configuration > SerialIo Configuration > Serial IO UART0 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial io UART0 Settings</td><td>Info Only</td><td></td></tr><tr><td>Hardware Flow Control</td><td>DisabledEnabled</td><td></td></tr><tr><td>DMA Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Timing Parameters</td><td>Info Only</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen off)</td><td>200</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen on)</td><td>200</td><td></td></tr></table>

7.4.2.6.4 Advanced > PCH-IO Configuration > SerialIo Configuration > Serial IO UART1 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial io UART1 Settings</td><td>Info Only</td><td></td></tr><tr><td>Hardware Flow Control</td><td>DisabledEnabled</td><td></td></tr><tr><td>DMA Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Timing Parameters</td><td>Info Only</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen off)</td><td>200</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen on)</td><td>200</td><td></td></tr></table>

7.4.2.6.5 Advanced > PCH-IO Configuration > SerialIo Configuration > Serial IO UART2 Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial I/O UART2 Settings</td><td>Info Only</td><td></td></tr><tr><td>Hardware Flow Control</td><td>DisabledEnabled</td><td></td></tr><tr><td>DMA Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Timing Parameters</td><td>Info Only</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen off)</td><td>200</td><td></td></tr><tr><td>D0-&gt;D3 idle Timeout (screen on)</td><td>200</td><td></td></tr></table>

7.4.2.7. Chipset > PCH-IO Configuration > SCS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>eMMC 5.1 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.1 Controller</td></tr><tr><td>eMMC 5.1 HS400 Mode</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.1 HS400 Mode</td></tr><tr><td>Enable HS400 software tuning</td><td>DisabledEnabled</td><td>Software tuning should improve eMMC HS400 stability at the expense of boot time</td></tr><tr><td>Driver Strength</td><td>33 0hm40 0hm50 0hm</td><td>Sets I/O driver strength</td></tr><tr><td>SDCard 3.0 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS SDHC 3.0 Controller</td></tr></table>

7.4.2.8. Chipset > PCH-IO Configuration > PSE Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PSE Controller</td><td>DisabledEnabled</td><td>Enables/Disables Programmable Service Engine (PSE) Device</td></tr><tr><td>PSE Dash Board Configuration</td><td>Info Only</td><td></td></tr><tr><td>LOG OUTPUT CHANNEL</td><td>3</td><td>Determine the PSE log output channel</td></tr><tr><td>LOG PUTPUT OFFSET</td><td>0</td><td>Determine the PSE log output region offset in memory</td></tr><tr><td>LOT OUTPUT SIZE</td><td>0</td><td>Determine the PSE log output region size limitation in memory</td></tr><tr><td>Shell</td><td>DisabledEnabled</td><td>Enable/Disable PSE Shell</td></tr><tr><td>Eclite</td><td>DisabledEnabled</td><td>Enable/Disable PSE Eclite Service</td></tr><tr><td>OOB</td><td>DisabledEnabled</td><td>Enable/Disable PSE OOB Service</td></tr><tr><td>WOL</td><td>DisabledEnabled</td><td>Enable/Disable PSE GBE WoL</td></tr><tr><td>PSE Debug (JTAGSWD) Enable</td><td>DisabledEnabled</td><td>PSE JTAG/SWD Debug enable. Set to enable. Unset to disable</td></tr><tr><td>PSE JTAG/SWD PIN MUX</td><td>DisabledEnabled</td><td>Enable/Disable PSE Jtag Pin Mux. Grayed out if Sci Pin Mux is enabled</td></tr><tr><td>PSE Add-In-Card</td><td>DisabledEnabled</td><td>Enable/Disable PSE Add-In-Card</td></tr><tr><td>PSE IP Ownership and GPIO Mux Assignment Configuration</td><td>Info Only</td><td></td></tr><tr><td>I2S0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>I2S0 has pin conflict with CAN0, CAN1, TGPIO 14-17.I2S1 does not have conflict.If it is grayed out, check the above option.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>PSE I2S0 PIN Assignment</td><td>Group EGroup R</td><td>PSE I2S0 PIN Assignment. Choose I2S0 pin out to GPIO Group E or Group R</td></tr><tr><td>I2S1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>I2S0 has pin conflict with CAN0, CAN1, TGPIO 14-17.I2S1 does not have conflict.If it is grayed out, check the above option.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>PWM</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>PWM has pin conflict with UART3, SPI0, SPI1, I2C5 and TGPIO.If it is grayed out, check the above options.The sam pin cannot be assigned to multiple IP.I2S1 does not have conflict.</td></tr><tr><td>PWM Pin Mux Selection</td><td>Submenu</td><td>Enable individual pin as PWM</td></tr><tr><td>UART0</td><td>NonePSE owned with pinmuxedHost owned with pin muxed</td><td>If UART0 is disabled, UART1-5 will be disabled too due to sharing same function</td></tr><tr><td>HSUART0/RS485</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select this to enable UART to support HSUART/RS485.Each HSUART pin conflict dependency is similar to UART.</td></tr><tr><td>UART1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE UART0 to host owned because UART0 is the function 0 of this device.</td></tr><tr><td>HSUART1RS485</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select this to enable UART to support HSUART/RS485.Each HSUART pin conflict dependency is similar to UART.</td></tr><tr><td>UART3</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>UART3 has pin conflict with GBE0-1, PWM, TGPIO, and Seriallo controller.</td></tr><tr><td>HSUART3/RS485</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select this to enable UART to support HSUART/RS485.</td></tr><tr><td>UART4</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE UART0 to host owned because UART0 is the function 0 of this device.</td></tr><tr><td>UART5</td><td>NonePSE owned with pinmuxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE UART0 to host owned because UART0 is thefunction 0 of this device.</td></tr><tr><td>QEP0</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.If it is grayed out, check the above options.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>QEP1</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.If it is grayed out, check the above options.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>QEP2</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.If it is grayed out, check the above options.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>QEP3</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.If it is grayed out, check the above options.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>I2C0</td><td>NonePSE owned with pin muxed</td><td>If I2C0 is not set to host owned, I2C 1-6 could not be set to host owned too due to sharing same function</td></tr><tr><td>I2C1</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.</td></tr><tr><td>I2C2</td><td>NonePSE owned with pin muxed</td><td>Grayed out to reserve for ECLite</td></tr><tr><td>I2C3</td><td>I2C3 is not configurable as it is shared with SMBUS</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.</td></tr><tr><td>I2C4</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.</td></tr><tr><td>I2C5</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.</td></tr><tr><td>I2C6</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.</td></tr><tr><td>I2C7</td><td>NonePSE owned with pin muxed</td><td>If I2C7 is not set to host owned, all PSE CAN and QEP devices could not be set to host owned too due to sharing same function.</td></tr><tr><td>SPI0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>SPI0 has pin conflict with PWM pin 3, TGPIO pin 10-13 and 39, serial SPI 2.</td></tr><tr><td>SPI0 CS0</td><td>DisabledEnabled</td><td>Set SPI CS pin to PSE SPI CS native function</td></tr><tr><td>SPI0 CS1</td><td>DisabledEnabled</td><td>Set SPI CS pin to PSE SPI CS native function</td></tr><tr><td>SPI1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE SPI0 to host owned because SPI0 is the function 0 of this device.</td></tr><tr><td>SPI2</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>SPI2 has pin conflict with WWAN WAKE GPIO.</td></tr><tr><td>SPI3</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE SPI0 to host owned because SPI0 is the function 0 of this device.</td></tr><tr><td>CAN0</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.</td></tr><tr><td>CAN1</td><td>NonePSE owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.</td></tr><tr><td>DMA0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for DMA.</td></tr><tr><td>DMA1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for DMA.</td></tr><tr><td>DMA2</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for DMA.</td></tr><tr><td>GBE0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for GBE</td></tr><tr><td>GBE1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for GBE</td></tr><tr><td>PSE GBE1 DLL Overrid</td><td>DisabledEnabled</td><td>Enable/Disable PSE GBE1 DLL.To Enable this GBE1 must be Enabled</td></tr><tr><td>GPIO/TGPIO 0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Owner of GPIO/TGPIO 0 Controller(PSE or HOST owned).</td></tr><tr><td>GPIO/TGPIO 0 MUX SELECTION</td><td>LOWERMIDTOPAll pins are GPIO</td><td>Choose Top, Mid, Lower or All mux for GPIO/TGPIO 1 Controller Instance.</td></tr><tr><td>GPIO/TGPIO 0 Pin Selection</td><td>Submenu</td><td>Enable individual GPIO/TGPIO pin</td></tr><tr><td>GPIO/TGPIO 1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Owner of GPIO/TGPIO 1 Controller(PSE or HOST owned).</td></tr><tr><td>GPIO/TGPIO 1 MUX SELECTION</td><td>LOWERMIDTOPAll pins are GPIO</td><td>Choose Top, Mid, Lower or All mux for GPIO/TGPIO 1 Controller Instance.</td></tr><tr><td>GPIO/TGPIO 1 Pin SELECTION</td><td>Submenu</td><td>Enable individual GPIO/TGPIO pin</td></tr><tr><td>PSE Interrupt Assignment Configuration</td><td>Info Only</td><td></td></tr><tr><td>I2S0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2S1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>PWM</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART2</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART3</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART4</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART5</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>HSUART0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>HSUART1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>HSUART2</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>HSUART3</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>QEP0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>QEP1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>QEP2</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>QEP3</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C2</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C3</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C4</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C5</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C6</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C7</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>SPI0</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>SPI1</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>SPI2</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>SPI3</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>DMA0</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>DMA1</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>DMA2</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>LH2PSE</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>CAN0</td><td>Disabled Enabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>CAN1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>DMA Test</td><td>DisabledEnabled</td><td>Enable/Disable DMA test Device</td></tr><tr><td>PSE I2C Test Device</td><td>DisabledEnabled</td><td>Enable PSE I2C WITT Device and select which are all controller used it</td></tr><tr><td>PSE SPI Test Device</td><td>DisabledEnabled</td><td>Enable PSE SPI WITT Device and select which are all controller used it</td></tr><tr><td>PSE UART Test Device</td><td>DisabledEnabled</td><td>Enable PSE UART Test Device and select which are all controller used it</td></tr></table>

7.4.2.9. Chipset > PCH-IO Configuration > TSN GBE Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH TSN LAN Controller</td><td>EnabledDisabled</td><td>Enable/Disable TSN LAN.</td></tr><tr><td>PCH TSN GBE Multi-Vc</td><td>EnabledDisabled</td><td>Enable/Disable TSN Multi Virtual Channels.</td></tr><tr><td>PCH TSN GBE SGMII Support</td><td>EnabledDisabled</td><td>Enable/Disable SGMII mode for PCH TSN GBE. Ports in SGMII mode with the same PLL common lane must use the same link speed. SATA or UFS may need to be disabled if TSN port is using the same PLL common lane. Please make sure IFWI has proper straps set for SGMII. Make sure Flex IO Lane Assignment is not NONE.</td></tr><tr><td>PCH TSN Link Speed</td><td>RefClk 24Mhz 2.5GbpsRefClk 24Mhz 1GbpsRefClk 38.4Mhz 2.5GbpsRefClk 38.4Mhz 1Gbps</td><td>PCH TSN Link Speed configuration.</td></tr><tr><td>Flex IO Lane Assignment:</td><td>Info Only</td><td></td></tr><tr><td>PSE TSN GBE 0 Multi-Vc</td><td>EnabledDisabled</td><td>Enable/Disable TSN Multi Virtual Channels. TSN GBE must be host owned.</td></tr><tr><td>PSE TSN GBE 0 SGMII Support</td><td>EnabledDisabled</td><td>Enable/Disable Modphy support for SGMII mode for PSE TSN GBE 0. Ports in SGMII mode with the same PLL common lane must use the same link speed. UFS will need to be disabled as this TSN port uses the same PLL common lane. Please make sure IFWI has proper straps set for SGMII. Make sure Flex IO Lane Assignment is not NONE.</td></tr><tr><td>PSE TSN GBE 0 Link Speed</td><td>RefClk 24Mhz 2.5GbpsRefClk 24Mhz 1GbpsRefClk 38.4Mhz 2.5GbpsRefClk 38.4Mhz 1Gbps</td><td>PSE TSN GBE 0 Link Speed configuration.</td></tr><tr><td>PSE TSN GBE1 Multi-Vc</td><td>EnabledDisabled</td><td>Enable/Disable TSN Multi Virtual Channels. TSN GBE must be host owned.</td></tr><tr><td>PSE TSN GBE1 SGMII Support</td><td>EnabledDisabled</td><td>Enable/Disable Modphy support for SGMII mode for PSE TSN GBE 1. Ports in SGMII mode with the same PLL common lane must use the same link Speed.SATA or UFS may need to be disabled if TSN port is using the same PLL common lane. Please make sure IFWI has proper straps set for SGMII. Make sure Flex IO Lane Assignment is not NONE.</td></tr><tr><td>PSE TSN GBE 1 Link Speed</td><td>RefClk 24Mhz 2.5GbpsRefClk 24Mhz 1GbpsRefClk 38.4Mhz 2.5GbpsRefClk 38.4Mhz 1Gbps</td><td>PSE TSN GBE 1 Link Speed configuration.</td></tr><tr><td>Flex IO Lane Assignment:</td><td>Info Only</td><td></td></tr><tr><td>PLL Common Lane 1</td><td>Info Only</td><td></td></tr><tr><td>GBE AIC Status</td><td>ConnectedNot Connected</td><td>GBE Add In Card connection status.</td></tr></table>

# 7.5. Security Menu

7.5.1. Security > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Setup Administrator Password</td><td>Enter Password</td><td>Set Setup Administrator Password</td></tr><tr><td>User Password</td><td>Enter Password</td><td>Set User Password</td></tr><tr><td>Secure Boot</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>Secure Boot Control</td><td>DisabledEnabled</td><td>Secure Boot activated when Platform Key(PK) is en-rolled, System mode is User / Deployed, and CSM function is disabled</td></tr></table>

# 7.6. Boot Menu

7.6.1. Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard Number state.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enable or Disable FastBoot features.Most probes are skipped to reduce time cost during boot.</td></tr><tr><td>New Boot Option Policy</td><td>DefaultPlace FirstPlace Last</td><td>Controls the placement of newly detected UEFI boot option.</td></tr><tr><td>Boot Mode select</td><td>LEGACYUEFI</td><td>Select boot mode LEGACY/UEFI</td></tr></table>

7.6.2. Boot > FIXED BOOT ORDER Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option #1</td><td>Hardware</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #2</td><td>CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #3</td><td>USB Hard Disk</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #4</td><td>USB CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #5</td><td>USB Key</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #6</td><td>USB Floppy</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #7</td><td>USB Lan</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #8</td><td>Network</td><td>Set the system boot order.</td></tr></table>

# 7.7. Save & Exit Menu

7.7.1. Save and Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Change and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

# 8. BIOS Checkpoints, Beep Codes

This section of this document lists status codes, namely checkpoints and beep codes, generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions

A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. The Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes.

Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but the Aptio 5.x core can be configured to send checkpoints to a variety of sources. The Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware.

A beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process.

![The image displays a red outline icon on a white background. It depicts a rectangular shape resembling a document or piece of paper with a folded top-right corner. Inside the red outline, there are three horizontal red bars stacked vertically.](.nanox-el-50m-72307-1030-13/5a0c25db7af3251b7d084055c99eabd8aa4b587371002f148d0fe62301b251c8.jpg)

Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify the user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes

# Viewing Checkpoints

Checkpoints generated by the Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-on cards show the value of I/O port 80h on an LED display.

# Aptio V Checkpoint and Beep Codes

Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes

8.1. Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xCF</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2. Standard Status Codes

# 8.2.1. SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr></table>

<table><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2. SEC Beep Codes

None

8.2.3. PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self-test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4. PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (Install Pei Memory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5. DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (Load Image returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (Start Image returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

8.2.6. DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

8.2.7. ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is inPIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

8.3. OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xFC</td><td>OEM BDS initialization codes</td></tr></table>

# 9. Software Support

9.1. Windows 10 IoT Enterprise 64-bit
9.2. Yocto Linux 64-bit

https://github.com/ADLINK/meta-adlink-x86-64bit

# 10. Mechanical and Thermal

# 10.1. Module Dimensions

![This image is a technical drawing featuring a 'Top View' and a 'Side View' of a rectangular mechanical component.\n\n**Top View:**\n*   **Main Shape:** A large rectangle representing the top surface of the object.\n*   **Features:** Four circles with crosshairs are located at the corners (mounting holes). A long, rectangular component with dense horizontal lines (resembling a connector or socket) is positioned near the top edge.\n*   **Annotations:**\n    *   Top left corner: Vertical stack of numbers '55', '51', and '49' with leader lines pointing to the top edge and the top-left hole.\n    *   Left side: Numbers '4' and '0' positioned near the left edge.\n    *   Bottom left corner: Vertical numbers '04' and '10'.\n    *   Bottom right corner: Vertical numbers '68', '80', and '84'.\n    *   Bottom right hole: Leader lines pointing to the circles with labels 'Ø 6' (outer diameter) and 'Ø 3' (inner diameter).\n\n**Side View:**\n*   **Label:** 'Side View' on the left.\n*   **Main Shape:** A thin horizontal profile showing the thickness of the object.\n*   **Annotation:** A vertical dimension line on the left labeled '2'.](.nanox-el-50m-72307-1030-13/7cfcddb5e88fecd81ffe4008e5bdec02636e883ffa80b985985be3d7e1ea21ff.jpg)

All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances on the module connector locating peg holes (dimensions [9.8, 49]) should be ± 0.10mm.

Dimensions: mm

Figure 5 – Module mechanical dimensions

# 10.2. Thermal Solutions

# 10.2.1. Heatspreader – Bottom Mount: HTS-nXEL-B-I

Heatspreader with threaded standoffs for bottom mounting

![This image is a technical engineering drawing of a rectangular plate component, presented in multiple views with dimensions in millimeters.\n\n**Top Section:**\nTwo isometric views are shown. The left view displays the underside of the plate featuring four cylindrical feet. The right view displays the top side, showing a central rectangular recess, four cylindrical feet (or bosses) near the corners, and threaded holes.\n\n**Left Section:**\n*   **Side View:** A profile view above the main plan view shows the plate's thickness and the height of the feet, labeled with the dimension **4.3**.\n*   **Front/Plan View:** A rectangular outline shows the layout of holes and features.\n    *   **Horizontal Dimensions:** **84**, **76**, **66**.\n    *   **Vertical Dimensions:** **55**, **47**, **30.5**.\n    *   **Labels:** The letter **B** appears next to four holes.\n    *   **Text:** **Hair line direction** is centered with a double-headed arrow.\n\n**Center/Right Section:**\n*   **Profile View:** A narrow side view shows dimensions **11** and **7±0.1**.\n*   **Top/Plan View:** A detailed view of the top surface with hole positions and precise coordinates.\n    *   **Labels:** The letter **A** appears at the corners.\n    *   **Text Block:**\n        *   **A = M2.5 threaded through x4**\n        *   **B = M3.0 threaded through x4**\n    *   **Dimension:** **4-Ø5.0** points to the bottom-left hole.\n    *   **Vertical Dimensions (Right):** **34.9**, **25.4**, **20.4**, **10.9**, **0**.\n    *   **Horizontal Dimensions (Bottom):** **59.4**, **57.4**, **26.4**, **24.4**, **0**.\n\n**General:**\nThe text **Dimensions: mm** appears on the far right.](.nanox-el-50m-72307-1030-13/85cd61fb33fceb54772f7acf44e94462504fccd57aa09f96accbb5a8af583d59.jpg)
A = M2.5 threaded through x4
B = M3.0 threaded through x4

Dimensions: mm

Figure 6 – Heatspreader – bottom mount: HTS-nXEL-B-I

# 10.2.2. Heatsink High Profile – Bottom Mount: THSH-nXEL-B-I

High profile heatsink with threaded standoffs for bottom mounting

![This image is a technical engineering drawing of a heat sink, presenting multiple views including isometric projections and orthographic projections with dimensional data.\n\n**Top Row:**\n*   **Left:** A side profile view of the heat sink showing the fin height and thickness. Dimensions include '2.25' and '8.5±0.2'.\n*   **Center:** An isometric view showing the array of vertical cooling fins and four mounting feet.\n*   **Right:** An isometric view from underneath, displaying the base plate, a central cutout, and four threaded mounting posts.\n\n**Bottom Row:**\n*   **Left:** A front elevation view detailing the vertical fins. Annotations include 'R3' for a radius, and vertical dimensions '55', '51', '47', '28.5', '26.5'. Horizontal spacing dimensions include '8', '0', '4', '8', and bottom spacing '76', '80', '84'.\n*   **Center:** A side elevation view showing the depth of the unit. Dimensions are '33±0.3' and '5±0.1'.\n*   **Right:** A bottom plan view showing the mounting hole pattern and base geometry.\n    *   Text reads: 'A = M2.5 threaded through x4' and 'Dimensions: mm'.\n    *   Dimensions include '34.9', '25.4', '20.4', '10.9', '0' (vertical), and '59.4', '57.4', '26.4', '24.4', '0' (horizontal).\n    *   A note indicates '4-Ø5.0' for the mounting holes, labeled with 'A'.](.nanox-el-50m-72307-1030-13/102d4df7462373c15ce0257e42a3aeff0de9b8e0b9c1fe098d1bf8afe19fbf36.jpg)
Figure 7 – Heatsink High Profile –bottom mount: THSH-nXEL-B-I

# 10.2.3. Heatsink Low Profile – Bottom Mount: THS-nXEL-B-I

Low profile heatsink with threaded standoffs for bottom mounting

![The image displays technical drawings of a heat sink with various dimensions and annotations. The text in the image is as follows:\n\n2.25\n8.5±0.2\nA = M2.5 threaded through x4\nR3\n55\n51\n47\n28.5\n26.5\n8\n0\n4\n76\n80\n84\n0\n4\n8\n18±0.3\n5±0.1\nA\n4-Ø5.0\n34.9\n25.4\n20.4\n10.9\n0\n59.4\n57.4\n26.4\n24.4\n0](.nanox-el-50m-72307-1030-13/6f63f7e54ee73582534e26030dabbf0e558e7bb55e5d309bd7c8d17dbc9aa04e.jpg)
Dimensions: mm
Figure 8 – Heatsink Low Profile – bottom mount: THS-nXEL-B-I
[🔗 Link to the original document](.nanox-el-50m-72307-1030-13/nanox-el-50m-72307-1030-13.pdf)