# OSM-IMX93

User’s Guide

![The image displays the logo for the company NXP. The text consists of the letters 'NXP' in a bold, sans-serif typeface. The letters are stylized and overlap each other in a horizontal arrangement. The colors used are yellow, brown, blue, and green. The letter 'N' on the left features a yellow vertical bar and a brown diagonal. The letter 'X' in the center is formed by blue and green sections. The letter 'P' on the right is colored green. The background is white.](.osm-imx93-50m-76102-1010-11/b7d24d72d3f78650079a948d38f297129785c79e7435dccb7e56456e42122387.jpg)

![3KC77\nD8FDD\nADLINK®\nPIMX9352CVVXMAB\n.21P87F\nSBCK2375P\nKOREA\nNXP\n52375\nTP2\nGL050G\nXRA0160\n11S3091\nMADE IN TAIWAN\nN9300460ZAB7M30E020](.osm-imx93-50m-76102-1010-11/cb81107e06e7e432f4d306acfdaf454b273f3272b037b5730df3f223dbbc1844.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-08-14</td><td>AL</td></tr><tr><td>1.1</td><td>Specifications, block diagram, and pinouts and signal descriptions updated</td><td>2025-11-06</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangular warning sign with a thick black border containing a large black exclamation point in the center.](.osm-imx93-50m-76102-1010-11/be014fb72160902ff7061f3d285651e650c449b7bbe1e3c5243e08e13e480251.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![The image displays a red-outlined icon of a document or page against a white background. The bottom-right corner of the document is folded upwards. Inside the document shape, there are two horizontal red lines centered horizontally.](.osm-imx93-50m-76102-1010-11/61e8b48df0a2fa79493d275b782f5f5e73dbcb4acec6db3d3e8db95704a7bdb3.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image shows a standard yellow triangular warning symbol. Inside the triangle is a white exclamation point. There is no text present.](.osm-imx93-50m-76102-1010-11/b0c09d0700f4c06c0fa34e7cf2411fd8b23380e0c8283ab0f92b14b0de6d6ec7.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a red, upward-pointing triangle with rounded corners. Inside the triangle is a white exclamation mark ('!'). This is a standard warning or hazard symbol.](.osm-imx93-50m-76102-1010-11/e0e4695a49c734746b5acd6ef56583f3cdbbab4ac706586a1526c7ccc0761f64.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

Table of Contents ..

List of Figures .. . 9

1. Introduction ...... ..10

1.1. The OSM Form Factor.... .... 10

1.2. Latest OSM SGET Documents to be Used .. . 11

1.3. Module Feature List... . 11

2. Specifications.. .12

2.1. Core System... .. 12

2.2. Video.. .. 12

2.2.1 GPU.. . 12

2.2.2 Display Interface Support.. . 13

2.3. Camera.... .... 13

2.4. Audio .... .... 13

2.5. Dual Wired Ethernet ... .. 13

2.6. WiFi/Bluetooth... .. 14

2.7. Expansion Buses... .... 14

2.8. System Storage .. ... 15

2.9. FAN Control .. ... 15

2.10. Power.... ... 15

2.11. Mechanical and Environmental . .. 16

3. Block Diagram .. 17

4. Pinout and Signal Descriptions ... .18

4.1. Pin Summary .. ... 18

4.2. Signal Terminology Descriptions... . 20

4.3. Signal Description by Function.. . 21

4.3.1 LVDS Display Interface.. . 21

4.3.2 MIPI Camera Support. . 23

4.3.3 Audio Interfaces... . 25

4.3.4 USB Ports.... . 26

4.3.5 Optional USB Ports (Active Only with Onboard USB Hub).... . 27

4.3.6 PCIe.. . 27

# OSM-IMX93 User’s Guide

# SGET COM R0.1

4.3.7 Dual LAN Ports.. . 28
4.3.8 SDIO Card (4-Bit).. . 30
4.3.9 SPI Interfaces . . 31
4.3.10 GPIO.. . 32
4.3.11 CAN Bus .. ... 33
4.3.12 ADC.. ... 33
4.3.13 Power + Boot Select ... . 34

5. Software Support .......... ...38

5.1. Yocto.. . 38
5.2. SEMA.. . 38

6. Mechanical... ..39

6.1. Module Dimensions . . 39

7. Thermal Solutions... ..40

7.1. Heatspreader: HTS .. . 40
7.2. Heatsink: THS .. . 40

# List of Figures

Figure 1 – Module function diagram... .17

Figure 2 – Module size grid.... ..18

Figure 3 – Module pinout grid ............. ..19

Figure 4 – Placement and cut-out area – Size (L) ... ..39

# 1. Introduction

# 1.1. The OSM Form Factor

The OSM (“Open Standard Module”) Open Standard Module™ specification facilitates the development, production, and distribution of embedded modules tailored for renowned MCU32, ARM, and x86 architectures. This standard is increasingly relevant for IoT applications, as it merges the benefits of modular embedded computing with the growing demands for cost efficiency, compactness, and versatile interfaces.

The modules serve as building blocks for portable and stationary embedded systems. They integrate the core CPU and support circuits, including DRAM, boot flash, power sequencing, and CPU power supplies. The modules are used with application-specific carrier boards to implement features such as audio CODECs, touch controllers, wireless devices, PHY, and more. The modular design not only promotes scalability and fast time to market but also ensures upgradability, all while maintaining low costs, low power consumption, and a compact physical size.

![The image displays the text 'SGeT'. The letters 'S', 'G', and 'T' are uppercase and colored lime green. The letter 'e' is lowercase, colored magenta, and is positioned below the 'G' and to the left of the 'T'.](.osm-imx93-50m-76102-1010-11/0b1dfd51b967c1fcfb480a916bc0f5ea942eb72aa4fa4599dda27cb55200bacd.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

OSM module and carrier specifications are available online at: https://sget.org/standards/osm/

# 1.2. Latest OSM SGET Documents to be Used

OSM 1.0 / 1.1

![The image displays a simple icon featuring a thick red outline of a document or piece of paper with a folded top-right corner (a 'dog-ear'). Inside the white space, there are two horizontal red lines centered horizontally, representing lines of text.](.osm-imx93-50m-76102-1010-11/c0a3e125c45e2c107e36d5fa6c9cd252b9aca7d328295a8b106b096ac07f9e9e.jpg)

Note: This module is compliant with 1.1 specs

# 1.3. Module Feature List

Memory: LPDDR4 0.5 to 2GB

eMMC: BGA 32 to 128 GB

WIFI / BT: Industry-standard M.2 1216 footprint available; connected via SDIO interface

GPIOs: 14x available GPIOs

LAN: Dual RGMII interfaces

POWER: NXP PMIC solution

Graphics: Connects DSI and LVDS to the carrier

USB: Provides OTG straight from SoC; includes a 2nd USB straight from SOC

AUDIO: I 2 S to the carrier

CAN: Supports 2x CAN FD direct from SOC

BOOT SELECT: Booting from SD-card and eMMC is supported

SECURITY: Features built in HAB

# 2. Specifications

# 2.1. Core System

# CPU

2x ARM Cortex-A55 @1.7 GHz | 1x Cortex M33 @250Mhz | Arm® Ethos™ U-65 microNPU ARM Cortex-A55 MP Core processors are high-performance and optimized for low power consumption.

# Memory

0.5 up to 2GB LPDDR4-solder down memory

# L2 Cache

64KB system L2 cache per core

# Security

Arm® TrustZone® EdgeLock® secure enclave

# 2.2. Video

# 2.2.1 GPU

# GPU Core

No discrete GPU in the i.MX93 parts

# Graphics Feature Support

1x 1080p60 MIPI-DSI (4-lane, 1.5Gbps/lane) with PHY 1x 720p60 LVDS (4-lane)

# 2.2.2 Display Interface Support

# MIPI DSI

1x MIPI DSI 4 lane compliant to MIPI-DSI standard v1.2

Maximum resolution 1080p60 with 24-bit RGB

# LVDS

4 channel LVDS port resolutions up to 720p60

# HDMI

Not available

# 2.3. Camera

One 2-lane MIPI CSI2 camera input

# 2.4. Audio

I2 S to carrier

# 2.5. Dual Wired Ethernet

# Primary LAN

RGMII 10/100/1000 Ethernet interface

Supports 10/100/1000-Mbps data transfer rates in both full-duplex and half-duplex modes

# Secondary LAN

RGMii10/100/1000 Ethernet interface

Supports 10/100/1000-Mbps data transfer rates in both full-duplex and half-duplex modes

# 2.6. Wi-Fi/Bluetooth

Optional M.2 12-16 industry-standard footprint, supporting solder down modules for SDIO/UART.

# 2.7. Expansion Buses

# USB

3x USB 2.0, 1x USB 2.0 OTG (Optional USB hub available)

# UART

4x UART interfaces (UART A/B has TX/RX/CTS/RTS; C has TX/RX; plus 1x console)

# CAN bus

2x CAN: Supports CAN FD mode with a data bit rate up to 8 Mbps

# SPI

2x SPI

# I 2 S

1x I2 S interface with audio resolution from 16-bits to 32-bits and sample rate up to 192KHz (see Audio Codec support)

# I 2 C

2x I2 C interfaces

\- Supports for 7-bit mode

\- Software programmable clock frequency of 100 kbit/s in Standard-mode, 400 kbit/s in Fast-mode or 1 Mbit/s in Fast-mode Plus

# GPIO

14x GPIO with interrupt

# 2.8. System Storage

# SDIO

1x SDIO (4-bit) compatible with SD3.0 to carrier

# eMMC

32 GB, 64 GB, 128 GB (build option)

Compatible with eMMC specifications 5.0 and 5.1

# 2.9. FAN Control

None, only passive cooling is needed.

# 2.10. Power

# Power Modes

ON / OFF / SUSPEND

Power on / off behavior same as x86 AT (always boot)

# Voltage Input

5.0V +/- 5%

# Operating Temperatures (vs power input)

Standard Operating Temperature: 0 to 60°C

Extreme Rugged Operating Temperature: -40 to +85°C

Commercial grade BOM (memory, eMMC, SOC)

Industrial grade BOM (memory, eMMC, SOC)

# 2.11. Mechanical and Environmental

# Environmental Humidity

• 5-90% RH operating, non-condensing
• 5-95% RH storage (and operating with conformal coating)

# EMI

EN55022 Class B inside an enclosure

# Shock and Vibration

HALT Testing, including test report confirming the extended operating temperature range during and after vibration. A separate shock test report in accordance with MIL-STD-202F, Method 213B, Table 213-I, Condition A.

IN ADDITION: When installed on a baseboard, the device shall operate under 18 sawtooth mechanical shocks

(3 shocks in each direction) with a peak acceleration of 40g for a duration of 18 ms each, and 75g for a duration of 6 ms each.

Capable of supporting random vibration: MIL-STD-202F, Method 214A, Table 214-I, Condition D. If HALT testing shows equal or better performance, a separate vibration test report is not necessary.

# 3. Block Diagram

![The flowchart is a block diagram centered around a large pink rectangular block labeled **NXP i.MX93** (with **OSM L** written below it inside the block). It details the connections between the processor and various external components.\n\n**Labeled Blocks:**\n*   **Central Block:** NXP i.MX93, OSM L\n*   **Top Blocks:** eMMC 5.1 32/64/128 GB, LPDDR4 1GB / 2GB, WIFI/BT 1216\n*   **Left Side Blocks:** DSI 4L, LVDS 4L, CSI 2L, ETH_A, ETH_B, USB_A, OTG, USB_1, USB_2, USB_B, USB hub, USB_C, USB_D, SDIO_A, SD2, I2S_A, SAI3, SPI_A, SPI_1, SPI_B, SPI_7\n*   **Right Side Blocks:** UART_1, Console, UART_5, UART_A 4w, UART_7, UART_B 4w, UART_2, UART_C 2w, I2C_1, I2C_A, I2C_2, I2C_B, IO exp, GPIO_A 6x, GPIO_B 8x, CAN_1, CAN_A, CAN_2, CAN_B, PWM, PWM x2, JTAG, ADC_IN, ADC x2\n*   **Bottom Label:** Optional features\n\n**Connections:**\n*   **Top Connections:**\n    *   **eMMC 5.1 32/64/128 GB** connects to the top of the **NXP i.MX93** block.\n    *   **LPDDR4 1GB / 2GB** connects to the top of the **NXP i.MX93** block.\n    *   **WIFI/BT 1216** connects to the top of the **NXP i.MX93** block.\n\n*   **Left Side Connections:**\n    *   **DSI 4L** connects to **DSI 4L**.\n    *   **LVDS 4L** connects to **LVDS**.\n    *   **CSI 2L** connects to **CSI**.\n    *   **ETH_A** connects to **RGMii_0**.\n    *   **ETH_B** connects to **RGMii_1**.\n    *   **USB_A** connects to **USB_1** (the line is labeled **OTG**).\n    *   **USB_2** connects to the **USB hub**.\n    *   **USB hub** connects to **USB_B**, **USB_C**, and **USB_D**.\n    *   **SDIO_A** connects to **SD2**.\n    *   **I2S_A** connects to **SAI3**.\n    *   **SPI_A** connects to **SPI_1**.\n    *   **SPI_B** connects to **SPI_7**.\n\n*   **Right Side Connections:**\n    *   **UART_1** connects to **Console**.\n    *   **UART_5** connects to **UART_A 4w**.\n    *   **UART_7** connects to **UART_B 4w**.\n    *   **UART_2** connects to **UART_C 2w**.\n    *   **I2C_1** connects to **I2C_A**.\n    *   **I2C_2** connects to **I2C_B**.\n    *   **I2C_2** connects to **IO exp**.\n    *   **IO exp** connects to **GPIO_A 6x** and **GPIO_B 8x**.\n    *   **CAN_1** connects to **CAN_A**.\n    *   **CAN_2** connects to **CAN_B**.\n    *   **PWM** connects to **PWM x2**.\n    *   **JTAG** connects to **JTAG**.\n    *   **ADC_IN** connects to **ADC x2**.\n\n*   **Bottom Label:** A yellow bar labeled **Optional features** is at the bottom of the diagram.](.osm-imx93-50m-76102-1010-11/0e69e4cd0d04e92d126f7b83b19ed06bd9ed7022564e7b6f3047e529667b464f.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# 4.1. Pin Summary

Size-0 -“Zero": 30 mm x 15 mm
Size-S- "Small": 30 mm x 30 mm
Size-M-“Medium": 30 mm x 45 mm
Size-L-“Large": 45 mm x 45 mm

![45 mm\n30 mm\n45 mm](.osm-imx93-50m-76102-1010-11/ec068a9c6ea0cbf57e55468236c704b685f4b3a3d6cd0ef60690b32201b4f7e0.jpg)

Figure 2 – Module size grid

![The image displays a microarray or gene chip layout with red labels and a grid of grey circles (spots).\n\n**Top Labels:**\nRed numbers arranged in two rows:\nTop row: 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34\nBottom row: 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35\nVertical lines connect these numbers to columns in the grid.\n\n**Left Labels:**\nRed letters arranged vertically, with horizontal lines connecting to rows:\nTop section: A B C D E F G H J K L M N P R T U V W Y\nBottom section: AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR\n(Note: Letters I, O, Q, and S are skipped).\n\n**Center Grid:**\nA large rectangular area containing grey circles arranged in specific blocks:\n*   **Upper Section (Rows A-N):** Three vertical columns of spots located at Columns 1-10, 11-16, and 21-26.\n*   **Lower Section (Rows AA-AR):** A complex arrangement resembling a 'U' shape with internal vertical bars.\n    *   Left vertical bar (Columns 1-6).\n    *   Right vertical bar (Columns 31-35).\n    *   Bottom horizontal bar (Rows AM-AR, spanning Columns 11-35).\n    *   Two internal vertical bars (Columns 11-16 and 21-26).\n    *   A bottom-left extension (Rows AM-AR, Columns 1-10).](.osm-imx93-50m-76102-1010-11/5b0ac0fc160e9ae7d9912f8bc54d0a1c750af2da6eae145968f7c4d8ee919b89.jpg)
Figure 3 – Module pinout grid

# 4.2. Signal Terminology Descriptions

The following information provides descriptions of the terms used in the signal description table:

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the Module</td></tr><tr><td>O</td><td>Output from the Module</td></tr><tr><td>I/O</td><td>Bi-directional input/output</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>PU</td><td>PU (pull-up) resistor</td></tr><tr><td>PD</td><td>PD (pull-down) resistor</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analogue signaling for gigabit media dependent interface</td></tr><tr><td>DP</td><td>Low voltage differential signal for DisplayPort interface</td></tr><tr><td>D-PHY</td><td>Low voltage differential signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>M-PHY</td><td>Low voltage differential signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS</td><td>Low voltage differential signal for LCD displays</td></tr><tr><td>PCIE</td><td>Low voltage differential signal for PCIe</td></tr><tr><td>SATA</td><td>Low voltage differential signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition minimized differential signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signaling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>VDD_IN</td><td>Main power source from Carrier to Module</td></tr><tr><td>3.3V</td><td>3.3V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>Sleep</td><td>Module is in its lowest power state</td></tr><tr><td>Runtime</td><td>Module is full on. CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>Standby</td><td>Module is in standby state or higher</td></tr></table>

# 4.3. Signal Description by Function

# 4.3.1 LVDS Display Interface

For information on LVDS support for a single channel with 4 lanes, please refer to the details below:

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>LVDS_I2C_CLK</td><td>AM11</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>AM12</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>LVDS_VDD_EN</td><td>AN14</td><td>LVDS channel power enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_BL_PWM</td><td>AN22</td><td>LVDS channel brightness control through pulse width modulation</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_BL_EN</td><td>AN23</td><td>LVDS channel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_A_CLK_P</td><td>AN13</td><td>LVDS channel A differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_CLK_N</td><td>AN12</td><td>LVDS channel A differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE0_P</td><td>AP18</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE0_N</td><td>AP17</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE1_P</td><td>AR16</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE1_N</td><td>AR15</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE2_P</td><td>AP15</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE2_N</td><td>AP14</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE3_P</td><td>AP12</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE3_N</td><td>AP11</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr></table>

4.3.1.1. DSI0 Mode

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>DSI_DATA0_N</td><td>AB11</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA0_P</td><td>AB10</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA1_N</td><td>AC9</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA1_P</td><td>AC8</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA2_N</td><td>AC6</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA2_P</td><td>AC5</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA3_N</td><td>AB5</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA3_P</td><td>AB4</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_CLOCK_N</td><td>AB8</td><td>DSI differential clock output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_CLOCK_P</td><td>AB7</td><td>DSI differential clock output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_TE</td><td>AA3</td><td>DSI panel tearing effect signal</td><td>ICMOS</td><td>1.8V</td><td>-</td><td></td></tr><tr><td>DISP_VDD_EN / GPIO_C_4</td><td>F3</td><td>Primary Display power enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>DISP_BL_EN / GPIO_C_5</td><td>F4</td><td>Primary Display backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>DISP_BL_PWM / PWM_0</td><td>E18</td><td>Primary Display brightness control through pulse width modulation</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

# 4.3.1.2. eDP0 / eDP1 Mode

NA

# 4.3.1.3. HDMI Mode

NA

# 4.3.1.4. DP++ Mode

NA

# 4.3.2 MIPI Camera Support

4.3.2.1. CSI (2 Lanes)

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI_DATA0_N</td><td>C1</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY/ I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA0_P</td><td>B1</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA1_N</td><td>A2</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA1_P</td><td>A3</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA2_N</td><td>A5</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA2_P</td><td>A6</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr></table>

OSM-IMX93 User’s Guide

SGET COM R0.1

<table><tr><td>CSI_DATA3_N</td><td>B6</td><td>CSI differential input (point to point)</td><td>I_LVDS_D-PHY / I_LVDS_M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA3_P</td><td>B7</td><td>CSI differential input (point to point)</td><td>I_LVDS_D-PHY / I_LVDS_M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_CLOCK_N</td><td>B3</td><td>CSI differential clock input (point to point)</td><td>I_LVDS_D-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_CLOCK_P</td><td>B4</td><td>CSI differential clock input (point to point)</td><td>I_LVDS_D-PHY</td><td></td><td></td><td></td></tr><tr><td>CAM_MCK</td><td>C2</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td rowspan="2">I2C_CAM_SDA / CSI_TX_N</td><td rowspan="2">C3</td><td rowspan="2">I2C data for serial camera data support link or differential data lane</td><td rowspan="2">I/O OD CMOS / O LVDS M- PHY</td><td rowspan="2">1.8V</td><td rowspan="2">PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM_SDA</td></tr><tr><td>MIPI-CSI 3.0 mode uses CSI_TX_N</td></tr><tr><td rowspan="2">I2C_CAM_SCL / CSI_TX_P</td><td rowspan="2">C4</td><td rowspan="2">I2C clock for serial camera data support link or differential data lane</td><td>I/O OD CMOS</td><td rowspan="2">1.8V</td><td rowspan="2">PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM_SCL</td></tr><tr><td>/ O LVDS M-PHY</td><td>MIPI-CSI 3.0 mode uses CSI_TX_P</td></tr><tr><td>CAM_PWR / GPIO_C_6</td><td>G3</td><td>Camera 0 Power Enable, active high output.</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAM_RST# / GPIO_C_7</td><td>G4</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

# 4.3.3 Audio Interfaces

4.3.3.1. I2S0

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td> $I^{2}S\_A\_DATA\_IN$ </td><td>V21</td><td> $I^{2}S$  A Digital audio Input</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td> $I^{2}S\_A\_DATA\_OUT$ </td><td>W21</td><td> $I^{2}S$  A Digital audio Output</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td> $I^{2}S\_B\_DATA\_IN$ </td><td>V19</td><td> $I^{2}S$  B Digital audio Input</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td> $I^{2}S\_B\_DATA\_OUT$ </td><td>W19</td><td> $I^{2}S$  B Digital audio Output</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td> $I^{2}S\_MCLK$ </td><td>V18</td><td>Master clock output to  $I^{2}S$  codec(s)</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td> $I^{2}S\_LRCLK$ </td><td>W18</td><td> $I^{2}S$  Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td>Module Output if CPU acts in Master Mode; Module Input if CPU acts in Slave Mode</td></tr><tr><td> $I^{2}S\_BITCLK$ </td><td>W20</td><td> $I^{2}S$  Digital audio clock</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td>Module Output if CPU acts in Master Mode; Module Input if CPU acts in Slave Mode</td></tr></table>

4.3.4 USB Ports

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB_A_D_N</td><td>AB13</td><td>USB differential data pairs for port A</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_A_D_P</td><td>AC14</td><td>USB differential data pairs for port A</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_A_ID</td><td>AB14</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td></td></tr><tr><td>USB_A_OC#</td><td>AC15</td><td>USB over current for port A</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>-</td></tr><tr><td>USB_A_VBUS</td><td>AB16</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td></td><td></td></tr><tr><td>USB_A_EN</td><td>AC16</td><td>Power (enabled) for USB VBUS voltage</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>USB_B_D_N</td><td>AB23</td><td>USB differential data pairs for port B</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_B_D_P</td><td>AC22</td><td>USB differential data pairs for port B</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_B_ID</td><td>AB22</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>-</td></tr><tr><td>USB_B_OC#</td><td>AC21</td><td>USB over-current for port B</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td></td></tr><tr><td>USB_B_VBUS</td><td>AB20</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td>-</td><td>-</td></tr><tr><td>USB_B_EN</td><td>AC20</td><td>Power (enabled) for USB VBUS voltage</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

4.3.5 Optional USB Ports (Active Only with Onboard USB Hub)

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB_C_D_N</td><td>D11</td><td>USB differential data pairs for port C</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_C_D_P</td><td>D10</td><td>USB differential data pairs for port C</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_C_OC#</td><td>C8</td><td>USB over-current for port C</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td></td></tr><tr><td>USB_C_EN</td><td>C10</td><td>Enables power to USB VBUS voltage line</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>USB_D_D_N</td><td>D26</td><td>USB differential data pairs for port D</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_D_D_P</td><td>D25</td><td>USB differential data pairs for port D</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_D_OC#</td><td>C28</td><td>USB over-current for port D</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td></td></tr><tr><td>USB_D_EN</td><td>C26</td><td>Enables power to USB VBUS voltage line</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

# 4.3.6 PCIe

NA

# 4.3.7 Dual LAN Ports

4.3.7.1. GBE0 (RGMII)

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_A_(R)(G)MII_CRS</td><td>E16</td><td>Carrier Sense port A</td><td>I-CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_A_(R)(G)MII_COL</td><td>F15</td><td>Collision detects (half speed only) port A</td><td>I-CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD0</td><td>H15</td><td>Transmit data bit 0 (transmitted first) port A</td><td>O CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD1</td><td>G15</td><td>Transmit data bit 1 port A</td><td>O CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD2</td><td>H16</td><td>Transmit data bit 2 port A</td><td>O CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD3</td><td>G16</td><td>Transmit data bit 3 port A</td><td>O CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_A_(R)(G)MII_TX_EN(ER)</td><td>K16</td><td>Transmit enable (Error) port A</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_TX_CLK</td><td>J15</td><td>Transmit clock port A</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD0</td><td>K15</td><td>Receive data bit 0 (received first) port A</td><td>I CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD1</td><td>L15</td><td>Receive data bit 1 port A</td><td>I CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_A_(R)(G)MII_RXD2</td><td>N15</td><td>Receive data bit 2 port A</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RXD3</td><td>P15</td><td>Receive data bit 3 port A</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RX_ER</td><td>L16</td><td>Receive error port A</td><td>I-CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_A_(R)(G)MII_RX_DV(ER)</td><td>M15</td><td>Receive data valid port A</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RX_CLK</td><td>R15</td><td>Receive clock port A</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_A_SDP</td><td>N16</td><td>Ethernet port A System Defined Contact</td><td>O-CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_MDIO</td><td>T15</td><td>Management bus data signal for Ethernet</td><td>I/O CMOS</td><td>1.8V</td><td></td><td>Can be used for all ETH ports or for A exclusively</td></tr><tr><td>ETH_MDC</td><td>T16</td><td>Management bus clock signal for Ethernet</td><td>O CMOS</td><td>1.8V</td><td></td><td>Can be used for all ETH ports or for A exclusively</td></tr><tr><td>ETH_IOPWR</td><td>M17</td><td>ETH voltage is used to provide the IO voltage level for all Ethernet interfaces.</td><td>P</td><td>1.8V</td><td></td><td>Minimum current: 100mA</td></tr></table>

4.3.7.2. GBE1 (RGMII)

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_B_(R)(G)MII_CRS</td><td>D2</td><td>Carrier Sense port B</td><td>I CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_B_(R)(G)MII_COL</td><td>E1</td><td>Collision detects (half speed only) port B</td><td>I CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD0</td><td>G1</td><td>Transmit data bit 0 (transmitted first) port B</td><td>O CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD1</td><td>F1</td><td>Transmit data bit 1 port B</td><td>O CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD2</td><td>G2</td><td>Transmit data bit 2 port B</td><td>O CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD3</td><td>F2</td><td>Transmit data bit 3 port B</td><td>O CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_B_(R)(G)MII_TX_EN(ER)</td><td>J2</td><td>Transmit enable (Error) port B</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_TX_CLK</td><td>H1</td><td>Transmit clock port B</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_(S)(R)(G)MII_RXD0</td><td>J1</td><td>Receive data bit 0 (received first) port B</td><td>I CMOS</td><td>1.8V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_RXD1</td><td>K1</td><td>Receive data bit 1 port B</td><td>I CMOS</td><td>1.8V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_B_(R)(G)MII_RXD2</td><td>M1</td><td>Receive data bit 2 port B</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RXD3</td><td>N1</td><td>Receive data bit 3 port B</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RX_ER</td><td>K2</td><td>Receive error port B</td><td>I CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>ETH_B_(R)(G)MII_RX_DV(ER)</td><td>L1</td><td>Receive data valid (Error) port B</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RX_CLK</td><td>P1</td><td>Receive clock port B</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>ETH_B_SDP</td><td>M2</td><td>Ethernet port B System Defined Contact</td><td>O CMOS</td><td>1.8V</td><td>-</td><td></td></tr><tr><td>ETH_B_MDIO</td><td>C7</td><td>Management bus data signal for Ethernet B</td><td>I/O CMOS</td><td>1.8V</td><td></td><td>Optional use</td></tr><tr><td>ETH_B_MDC</td><td>C6</td><td>Management bus clock signal for Ethernet B</td><td>O CMOS</td><td>1.8V</td><td></td><td>Optional use</td></tr></table>

# 4.3.8 SDIO Card (4-Bit)

The carrier SDIO card can be selected as the boot device.

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SDIO_A_CMD</td><td>E20</td><td>SDIO A Command/Response: This signal is used for card initialization and for command transfers. During initialization mode, this signal is open-drain. During command transfer, this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_CLK</td><td>F21</td><td>SDIO A Clock: With each cycle of this signal, a one-bit transfer occurs on the command and each data line.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D0</td><td>G20</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D1</td><td>G21</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D2</td><td>H20</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D3</td><td>H21</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_CD#</td><td>J21</td><td>SDIO A Card Detect: This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td></td></tr><tr><td>SDIO_A_WP</td><td>D20</td><td>SDIO A Write Protect: This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td>Tie to GND on carrier, if not used</td></tr><tr><td>SDIO_A_PWR_EN</td><td>D21</td><td>SDIO A Power Enable: This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_IOPWR</td><td>C20</td><td>DIO A Voltage:: It is used to provide the IO Voltage Level</td><td>P</td><td>1.8V or 3.3V</td><td>-</td><td>Minimum current: 100mA</td></tr></table>

# 4.3.9 SPI Interfaces

4.3.9.1. SPI A/B

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI_A_SDI_(IO0)</td><td>U15</td><td>SPI A Serial Data Input</td><td>IO CMOS</td><td>1.8V</td><td></td><td>Alternate use: Quad SPI IO0</td></tr><tr><td>SPI_A_SDO_(IO1)</td><td>V15</td><td>SPI A Serial Data Output</td><td>IO CMOS</td><td>1.8V</td><td></td><td>Alternate use: Quad SPI IO1</td></tr><tr><td>SPI_A_AWP_(IO2)</td><td>W16</td><td>SPI A Write Protect</td><td>IO CMOS</td><td>1.8V</td><td>-</td><td>Alternate use: Quad SPI IO2</td></tr><tr><td>SPI_A_/HOLD_(IO3)</td><td>W15</td><td>SPI A Suspends Serial Input</td><td>IO CMOS</td><td>1.8V</td><td>-</td><td>Alternate use: Quad SPI IO3</td></tr><tr><td>SPI_A_CS0#</td><td>Y15</td><td>SPI A Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_A_CS1# / GPIO_A_6</td><td>K17</td><td>SPI A Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>SPI_A_SCK</td><td>U16</td><td>SPI A Serial Data Clock</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_SDI</td><td>Y22</td><td>SPI B Serial Data Input</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_SDO</td><td>Y23</td><td>SPI B Serial Data Output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_CS0#</td><td>AA23</td><td>SPI B Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_CS1# / GPIO_A_7</td><td>L17</td><td>SPI B Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>-</td><td>-</td></tr><tr><td>SPI_B_SCK</td><td>Y21</td><td>SPI B Serial Data Clock</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_SDI</td><td>C29</td><td>SPI C Serial Data Input</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_SDO</td><td>D30</td><td>SPI C Serial Data Output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_CS0#</td><td>C30</td><td>SPI C Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_CS1# / GPIO_D_7</td><td>Y33</td><td>SPI C Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_SCK</td><td>D29</td><td>SPI C Serial Data Clock</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

4.3.10 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO_A_0</td><td>D17</td><td>General purpose I/O Contact A0</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_1</td><td>E17</td><td>General purpose I/O Contact A1</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_2</td><td>F17</td><td>General purpose I/O Contact A2</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_3</td><td>G17</td><td>General purpose I/O Contact A3</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_4</td><td>H17</td><td>General purpose I/O Contact A4</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_5</td><td>J17</td><td>General purpose I/O Contact A5</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_0</td><td>D19</td><td>General purpose I/O Contact B0</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_1</td><td>E19</td><td>General purpose I/O Contact B1</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_2</td><td>F19</td><td>General purpose I/O Contact B2</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_3</td><td>G19</td><td>General purpose I/O Contact B3</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_4</td><td>H19</td><td>General purpose I/O Contact B4</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_5</td><td>J19</td><td>General purpose I/O Contact B5</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_6</td><td>K19</td><td>General purpose I/O Contact B6</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_7</td><td>L19</td><td>General purpose I/O Contact B7</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

4.3.11 CAN Bus

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size- 0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CAN_A_TX</td><td>AC17</td><td>CAN port A transmits output</td><td>O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_A_RX</td><td>AB17</td><td>CAN port A receives input</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_B_TX</td><td>AC19</td><td>CAN port B transmits output</td><td>O CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_B_RX</td><td>AB19</td><td>CAN port B receives input</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

4.3.12 ADC

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ADC_0</td><td>M18</td><td>Analog Digital Converter 0</td><td>Analog</td><td>0V – 1.8V</td><td></td><td></td></tr><tr><td>ADC_1</td><td>N18</td><td>Analog Digital Converter 1</td><td>Analog</td><td>0V – 1.8V</td><td></td><td></td></tr></table>

4.3.13 Power + Boot Select

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VCC_2_TEST $^{2}$ </td><td>M19</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_3_TEST</td><td>Y16</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_4_TEST</td><td>Y20</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_IN_5V</td><td>Y17</td><td>Module power input voltage of 5V – Primary voltage rail for size S, M, and L modules</td><td>P</td><td></td><td></td><td>Tolerance: 5V +-5%</td></tr><tr><td>VCC_IN_3V3</td><td>Y19</td><td>Module power input voltage of 3.3V – Primary voltage rail for 0 size modules</td><td>P</td><td></td><td></td><td>Tolerance: 3.3V +- 5%</td></tr><tr><td>V_BAT</td><td>AA18, AB18</td><td>Module power input battery voltage</td><td>P</td><td>-</td><td>-</td><td>-</td></tr><tr><td>GND</td><td>D18, E15, E21, F16, F20, J16, J20, L18, M16, M20, P18, R16, R20, V16, V20, Y18, AA14, AA17, AA19, AA22, AB15, AB21</td><td>Module signal and power return, and GND reference</td><td>P</td><td></td><td></td><td></td></tr><tr><td>SYS_RST#</td><td>U17</td><td>Reset input from the carrier board. The carrier drives low to force a module reset, floats the line otherwise.</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10K</td><td></td></tr><tr><td>CARRIER_PWR_EN</td><td>V17</td><td>Carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td rowspan="2">VCC_OUT_IO</td><td rowspan="2">U18</td><td rowspan="2">Can provide IO voltage level for several interfaces to connect</td><td rowspan="2">P</td><td rowspan="2">1.8V/3.3V</td><td rowspan="2"></td><td>Only applicable in size 0 – minimum current: 100mA;</td></tr><tr><td>All other sizes or features are not applicable: NC</td></tr><tr><td>RTC_PWR</td><td>W17</td><td>Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P</td><td>-</td><td>-</td><td>-</td></tr><tr><td>BOOT_SEL0#</td><td>U19</td><td></td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>The boot medium is the choice of the module vendor.</td></tr><tr><td>BOOT_SEL1#</td><td>R18</td><td></td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>The boot medium is the choice of the module vendor.</td></tr><tr><td>FORCE_RECOVERY#</td><td>T17</td><td>When the signal is low on the carrier board, the module enters recovery mode.</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>The recovery mode should be specified by module vendor.</td></tr><tr><td>VCC_5_TEST</td><td>Y3</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_6_TEST</td><td>C5</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2">VCC_IN_5V</td><td rowspan="2">Y8, Y9, Y10, Y11</td><td rowspan="2">Module power input voltage of 5V</td><td rowspan="2">P</td><td rowspan="2"></td><td rowspan="2"></td><td>Tolerance:</td></tr><tr><td>5V +-5%</td></tr><tr><td rowspan="2">GND</td><td>A4, A7, A10, B2, B5, B8, B9, C11, D1, D5, D8, E2,</td><td rowspan="2">Module signal and power return, and GND reference</td><td rowspan="2">P</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>H2, H4, L2, L4, P2, P4, R1, U2, U4, V1, W3, Y2, AA1, AA4, AA7, AA8, AA10, AA11, AB3, AB6, AB9, AC4, AC7,</td></tr><tr><td></td><td>AC10</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2">PWR_BTN#</td><td rowspan="2">AA9</td><td>Power-button input from the carrier board. The carrier floats the line in the inactive state.</td><td rowspan="2">I OD CMOS</td><td rowspan="2">1.8 to 5V</td><td rowspan="2">PU 10K</td><td rowspan="2"></td></tr><tr><td>Active low, level sensitive. Should be de-bounced on the module.</td></tr><tr><td>VCC_7_TEST</td><td>AA33</td><td>Module power voltage test point</td><td>P</td><td>-</td><td>-</td><td>-</td></tr><tr><td>VCC_8_TEST</td><td>B29</td><td>Module power voltage test point</td><td>P</td><td>-</td><td>-</td><td>-</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VCC_IN_5V</td><td>Y25, Y26, Y27, Y28</td><td>Module power input voltage of 5V</td><td>P</td><td></td><td></td><td>Tolerance: 5V +-5%</td></tr><tr><td rowspan="5">GND</td><td>C25, C32, C35, D28, D34, F33, F35,</td><td>Module signal and power return and GND reference</td><td rowspan="5">P</td><td rowspan="5"></td><td rowspan="5"></td><td rowspan="5"></td></tr><tr><td>G34, H32, J33, J35, K34, M35, N34,</td><td></td></tr><tr><td>T34, W34, AA25, AA26, AA27, AA28,</td><td></td></tr><tr><td>AA32, AB28, AB31, AB34, AC27, AC30,</td><td></td></tr><tr><td>AC33</td><td></td></tr><tr><td rowspan="2">VCC_IN_5V</td><td rowspan="2">AE4, AF4, AG4, AH3, AH4, AJ3, AJ4,</td><td rowspan="2">Module power input voltage of 5V</td><td rowspan="2">P</td><td rowspan="2"></td><td rowspan="2"></td><td>Tolerance: 5V</td></tr><tr><td>-0.05</td></tr><tr><td></td><td>AK4</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>GND</td><td>AE2, AE34, AF35, AG3, AH2, AH34, AJ35, AK3, AL2, AL34, AM13, AM16, AM19, AM22, AM35, AN3, AN6, AN9, AN11, AN15, AN18, AN21, AN33, AP2, AP5, AP8, AP13, AP16, AP19, AP22, AP25, AP28, AP31, AP34, AR14, AR17, AR20, AR26, AR29, AR32</td><td>Module signal and power return, and GND reference</td><td>P</td><td></td><td></td><td></td></tr></table>

# 5. Software Support

# 5.1. Yocto

Available on ADLINK GitHub Site (https://github.com/ADLINK/meta-adlink-nxp )

• Yocto meta layer with u-boot, kernel, root filesystem and middleware (MRAA/UPM library) recipes
• Yocto binary image for quick evaluation.
• A user guide to build BSP & deploy binary image

# 5.2. SEMA

NA

# 6. Mechanical

# 6.1. Module Dimensions

Module OSM L Size 45x 45mm

![28.00\n10.25\n6.75\n10.25\nR1\nR1\n6.75\n45.00\n30.50\n16.50\n7.75\n16.50\n6.75\n31.50\nR1\n45.00](.osm-imx93-50m-76102-1010-11/fe977569ab622122fa452c22cd0e81c05404a96c6c63cebc02a7a0d01de4f81c.jpg)

![27.50\n11.25\n6.25\n11.25\nR1\nR1\n6.25\n30.00\n17.50\n45.00\n8.75\n17.50\n6.25\n32.50\n45.00](.osm-imx93-50m-76102-1010-11/10d640687e4a0476c6e96fcfd947a81fc053347a23f73232bb0168588d3de3db.jpg)

Figure 4 – Placement and cut-out area – Size (L)

# 7. Thermal Solutions

# 7.1. Heatspreader: HTS

To be defined on the carrier.

# 7.2. Heatsink: THS

To be defined on the carrier.
[🔗 Link to the original document](.osm-imx93-50m-76102-1010-11/osm-imx93-50m-76102-1010-11.pdf)