# OSM-MTK510

User’s Guide

Powered by

MediaTek

![51-76103-0A00\nMEDIATEK\n2362-Z4HHAH\nMT8370AV\nBTTWRY12-A\nABM\nMT63651DW\n2424-BGEN\nATG66W40\nD601\nMEDIATEK\nMT63651DW\n2424-BGEN\nATG66W40\nD601\neMMC\nPTE4A0SP-32GE\n004028050\n14](.osm-mtk510-50m-76103-1010-11/37db326c78f08fd024d6f56446bdb7ff40a7abf96e300b905aa9894f80507eb3.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-11-25</td><td>AL</td></tr><tr><td>1.1</td><td>Specifications and block diagram updated</td><td>2026-02-12</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border containing a centered black exclamation point.](.osm-mtk510-50m-76103-1010-11/950c77da3f87a95cbba7d0f1326ec99ecac1583d6fb6a8f4408ca8f93c22ed4c.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black and white pictogram of a trash bin with a lid, handle, and wheels. A large 'X' is superimposed over the bin, indicating it should not be disposed of in general waste. Below the symbol is a solid black rectangular block. There is no text present.](.osm-mtk510-50m-76103-1010-11/bf37d69eac47b8198aa216a32dbf414cb0d8e7606dd73504bb3aa9be5d7e2d95.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2026 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a red icon resembling a folded document or page. It features a thick red border with a curled bottom-right corner. Inside the white interior, two horizontal red lines are centered, resembling an equals sign.](.osm-mtk510-50m-76103-1010-11/2b68bd0a9373d49a58401e5779ca179f5c2498eba2b77dfc9679d30dca1cfcb1.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image shows a standard yellow warning symbol. It features a yellow equilateral triangle pointing upward, with a black exclamation mark centered inside it.](.osm-mtk510-50m-76103-1010-11/54d0798342a80e6619790c7b890883db6ddf553cbfd09a60c90a92c86729f5e6.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a red triangular warning sign with rounded corners. Inside the triangle is a white exclamation point centered vertically.](.osm-mtk510-50m-76103-1010-11/27f11d667e62bd385c231e0526c0d2ce19c0f7cd1ba7dfc8359491bd5c8886f3.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

1. Introduction .. . 8

1.1 The OSM Form Factor.... ...8
1.2 Brief ... ..8

2. Specifications.. . 9

2.1 Core System... ..9
2.2 Video.... . 10

2.2.1 GPU.. . 10
2.2.2 Display Interfaces... . 10

2.3 Camera.... . 11
2.4 Audio .. . 11
2.5 Wired Ethernet.... . 11
2.6 Extension busses.. . 11
2.7 System Storage .. ... 12
2.8 Power... ... 13

3. Block Diagram .. .14
4. Pinout and Signal Descriptions .... .15

4.1 Pin Summary .. . 15
4.2 Signal Terminology Descriptions.. . 17
4.3 Full Signal to Pad Table .. . 18
4.4 Signal Description by Function... . 37

4.4.1 DSIO ... . 37
4.4.2 eDP A .. ... 38
4.4.3 eDP B.... ... 39
4.4.4 DP/HDMI.. .... 40
4.4.5 MIPI Camera support.. .... 40
4.4.6 Audio Interfaces .. . 41
4.4.7 USB Ports.. . 42
4.4.8 PCIe... .... 43
4.4.9 LAN Port . . 44
4.4.10 SDIO ... ... 45

4.4.11 SPI Interfaces . ... 46

4.4.12 GPIO ... .... 48

4.4.13 Power.. .... 49

5. Software Support ... ..51

5.1 Yocto.. . 51

5.2 Canonical Ubuntu.. . 51

6. Mechanical... .52

6.1 Module Dimensions . . 52

7. Thermal Solutions... .53

7.1 Heatspreader: HTS . . 53

7.2 Heatsink: THS .. . 53

# List of Figures

Figure 1 – Module function diagram... .14
Figure 2 – Module size grid.... .15
Figure 3 – Module pinout grid... ...16
Figure 4 – Mechanical dimensions .. .52

# 1. Introduction

# 1.1 The OSM Form Factor

The OSM (“Open Standard Module”) Open Standard Module™ specification facilitates the development, production, and distribution of embedded modules tailored for renowned MCU32, ARM, and x86 architectures. This standard is increasingly relevant for IoT applications, as it merges the benefits of modular embedded computing with the growing demands for cost efficiency, compactness, and versatile interfaces.

The modules serve as building blocks for portable and stationary embedded systems. They integrate the core CPU and support circuits, including DRAM, boot flash, power sequencing, and CPU power supplies. The modules are used with application-specific carrier boards to implement features such as audio CODECs, touch controllers, wireless devices, PHY, and more. The modular design not only promotes scalability and fast time to market but also ensures upgradability, all while maintaining low costs, low power consumption, and a compact physical size.

# 1.2 Brief

The OSM-MT510 is an OSM (Open Standard Module) size-L form factor for small-sized, low-cost embedded computer modules that are fully compliant with the SGET (Standardization Group for Embedded Technologies) OSM Specification Version 1.1.

OSM modules help combine the advantages of modular embedded computing with the increasing requirements for cost, space, and interfaces. The core of the OSM-MT510 is the MT8370 CPU, which integrates an ARM processor core, graphics, LPDDR4x memory controller, and I/O interfaces into a single system-on-chip solution. The OSM-MT510 also includes contemporary high-bandwidth interfaces such as PCI Express, USB 3.0/2.0, Gigabit Ethernet, CSI, I2S, HDMI, DP, eDP, DSI, and SDIO/eMMC.

![The image displays a logo consisting of the text 'SGeT'. The uppercase letters 'S', 'G', and 'T' are large, bold, sans-serif characters colored in a bright yellow. The lowercase letter 'e' is a smaller, bold, sans-serif character colored in magenta. It is positioned below the 'T' and slightly overlaps the bottom right portion of the 'G'.](.osm-mtk510-50m-76103-1010-11/7d6a710ec90a000dd58df4ebdf7a2463020b39297a0a6d3c67a66d8182d24059.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

OSM module and carrier specifications are available online at: https://sget.org/standards/osm/

# 2. Specifications

# 2.1 Core System

# CPU

2x ARM Cortex-A78 @2.0 GHz | 4x Cortex A55 @2.0 GHz

Ethos™ U-VP6 AI processing unit

ARM Cortex-A78 / A55 MP Core processors are high-performance and optimized for low power.

# Memory

• LPDDR4-solder down memory, single chip
• 32-bit DRAM interface. Up to 8 GB

# L2 Cache

64KB instruction L1 cache

64KB data cache

256KB L2 cache

Each core has its own cache

# Security

• Arm TrustZone
• Security Boot (RSA4096)
• Crypto Engine
• RNG

# 2.2 Video

# 2.2.1 GPU

GPU Core

Mali G57 MC2

# Graphics Feature Support

2x display video data processing pipelines, with the following support:

DP >4K @ 60H

eDP 1920 x 1440 @ 60H

HDMI 4K @ 60H

DSI FHD @60HZ

![The image displays a red icon on a white background. It depicts a rectangular shape with a folded bottom-right corner, resembling a document or page. Inside the shape are two horizontal red bars centered vertically.](.osm-mtk510-50m-76103-1010-11/01a81b7df4f7f63862c57ae831da9c8ec1a7f496d346b20b4916ca741c9b2992.jpg)

Note: DP/HDMI are BOM options.

# 2.2.2 Display Interfaces

MIPI DSI

1x MIPI DSI 4 lane Compliant to MIPI-DSI standard v1.2

Maximum resolution 1080p60 with 24-bit RGB

HDMI/DP

Maximum resolution up to 4K @60HZ

eDP

Maximum resolution 1920 x 1440 @ 60H

# 2.3 Camera

one 4-lane MIPI CSI2 camera input.

# 2.4 Audio

I2S to carrier

# 2.5 Wired Ethernet

# LAN

Built in MAC 10/100/1000

Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex

# 2.6 Extension busses

# USB

1x USB 2.0, 1x USB 2.0 OTG, 1x USB 3.0

# UART

4x UART interfaces (A: TX/RX/CTS/RTS; C & D: TX/RX; 1× console: TX/RX)

# SPI

3x SPI

# I2S

1x I2S interface supporting audio codec on carrier

# I2C

6x I2C interfaces

- Support for 7-bit mode
- Software programmable clock frequency of 100 kbit/s in Standard-mode,
400 kbit/s in the Fast-mode or 1 Mbit/s in Fast-mode Plus

# GPIO

19x GPIOs with interrupts

# 2.7 System Storage

# SDIO

2x SDIO (4-bit) compatible with SD3.0

# eMMC

32\~ 256 GB (build option)

Compatible with eMMC specification 4.41, 4.51, 5.0 and 5.1

# 2.8 Power

<table><tr><td>Power Modes:</td><td>ON / OFF / SUSPEND</td></tr><tr><td>Power on / off behaviour same as x86</td><td>ATX (hold off boot until PWRBTN) / AT (always boot)</td></tr><tr><td>Voltage Input:</td><td>5.0V +/- 5%</td></tr><tr><td colspan="2">Operating Temperatures</td></tr><tr><td>Standard Operating Temperature:</td><td>0°C to 60°C commercial grade BOM (memory, eMMC, SOC)</td></tr><tr><td>Extreme Rugged Operating Temperature:</td><td>-40°C + 85°C industrial grade BOM (memory, eMMC, SOC)</td></tr><tr><td colspan="2">Derating for two different BOMs</td></tr><tr><td colspan="2">Environmental</td></tr><tr><td rowspan="2">Humidity:</td><td>5-90% RH operating, non-condensing</td></tr><tr><td>5-95% RH storage (and operating with conformal coating).</td></tr><tr><td>EMI:</td><td>EN55022 Class B inside an enclosure</td></tr><tr><td rowspan="2">Shock and Vibration:</td><td>HALT Testing, with test report that confirms Extended Operating Temp range during and after vibration. Separate Shock test report to MIL-STD-202F, Method 213B, Table 213-I, Condition A.IN ADDITION: When installed on baseboard shall operate under 18 sawtooth mechanical shocks (3 shocks in each direction) with a peak acceleration of 40g for a duration of 18 msec each and 75g for a duration of 6 msec each.</td></tr><tr><td>Capable of supporting Random Vibration: MIL-STD-202F, Method 214A, Table 214-I, Condition D. If HALT testing shows equal or better performance, a separate vibration test report is not necessary.</td></tr><tr><td>MTBF :</td><td>300,000 hrs (at 40°C), 100,000 hrs (at 85°C),</td></tr><tr><td>Two different BOM</td><td>0°C-60°C-40°C+85°C</td></tr></table>

# 3. Block Diagram

![The diagram depicts a system architecture centered around a block labeled **OSM**. Inside the central OSM block are smaller blocks labeled **LPDDR4**, **I510**, **eMMC 32/65/128/256 GB**, and **DP on a Reserved Pin**.\n\nThe diagram shows connections between external ports on the far left, internal OSM pins (left and right columns), and external ports on the far right. Red 'X' marks indicate disconnected lines.\n\n**Left-Side Connections (Inputs to OSM):**\n*   **HDMI** connects to **eDP_A**\n*   **eDP** connects to **eDP_B**\n*   **LVDS** connects via a red X (disconnected)\n*   **RGB** connects via a red X (disconnected)\n*   **DSI** connects to **DSI**\n*   **CSI** connects to **CSI**\n*   **RGMii** connects to **ETH_A**\n*   **ETH_B**, **ETH_C**, **ETH_D**, and **ETH_E** connect via red X marks (disconnected)\n*   **USB_A** connects to **USB_A**\n*   **USB_B** connects to **USB_B**\n*   **USB_C** connects to **USB_C**\n*   **USB_D** connects via a red X (disconnected)\n*   **PCIE_A** connects to **PCIe_A**\n*   **PCIe_B**, **PCIe_C**, and **PCIe_D** connect via red X marks (disconnected)\n*   **UFS** has no connecting line\n*   **PWM** connects to **PWM**\n*   **ADC x2** connects to **ADC**\n\n**Right-Side Connections (Outputs from OSM):**\n*   **Console** connects to **OSM-DEBUG 2W**\n*   **UART_A** connects to **UART_A 4W**\n*   **UART_B** connects via a red X (disconnected)\n*   **UART_C** connects to **UART_C 2W**\n*   **UART_D** connects to **UART_D 2W**\n*   **SPI_A** connects to **SPI_A**\n*   **SPI_B** connects to **SPI_B**\n*   **SPI_C** connects to **SPI_C**\n*   **I2C_A** connects to **I2C_A**\n*   **I2C_B** connects to **I2C_B**\n*   **I2S_A** connects to **I2S_A**\n*   **SDIO_A** connects to **SDIO_A**\n*   **SDIO_B** connects to **SDIO_B**\n*   **CAN_A** and **CAN_B** connect via red X marks (disconnected)\n*   **GPIO_A** connects to **GPIO_A 6x**\n*   **GPIO_B** connects to **GPIO_B 8x**\n*   **GPIO_C** connects to **GPIO_C 4x**\n*   **GPIO_D** connects to **GPIO_D 1x**\n*   **GPIO_E** connects via a red X (disconnected)](.osm-mtk510-50m-76103-1010-11/453d03eae2b50f0fda7574ac33c0a946f7187bf71f98781cbcdaec6b17d4d32d.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# 4.1 Pin Summary

The tables below are a list of all signals to the LGA pads following the OSM 1.2 specifications.

Size-0 -"Zero": 30 mm x 15 mm
Size-S - "Small": 30 mm x 30 mm
1 Size-M-“Medium": 30 mm x 45 mm
Size-L-“Large": 45 mm x 45 mm

![45 mm\n30 mm\n45 mm](.osm-mtk510-50m-76103-1010-11/e27b68e08579f51122b5bd033118a8f1efe7169e89f41190643fed97877e97ca.jpg)

Figure 2 – Module size grid

![| Category | Value |\n|---|---|\n| A | 1 |\n| B | 3 |\n| C | 5 |\n| D | 7 |\n| E | 9 |\n| F | 11 |\n| G | 13 |\n| H | 15 |\n| J | 17 |\n| K | 19 |\n| L | 21 |\n| M | 23 |\n| N | 25 |\n| P | 27 |\n| R | 29 |\n| T | 31 |\n| U | 33 |\n| V | 35 |\n| W | 34 |\n| Y | 33 |\n| AA | 32 |\n| AB | 31 |\n| AC | 30 |\n| AD | 29 |\n| AE | 28 |\n| AF | 27 |\n| AG | 26 |\n| AH | 25 |\n| AJ | 24 |\n| AK | 23 |\n| AL | 22 |\n| AM | 21 |\n| AN | 20 |\n| AP | 19 |\n| AR | 18 |](.osm-mtk510-50m-76103-1010-11/4421d108f421243bd1878f21c15c381086282696698f49b15df2a98f0d561e58.jpg)

Figure 21: Contact Grid (all sizes) (view from top, through the module)
Figure 3 – Module pinout grid

# 4.2 Signal Terminology Descriptions

Meaning of the terms used for signal description tables. Signals described in the specification but not supported on the OSM-MTK510 are marked with strikethrough STRIKETHROUGH.

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional input/output</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>PU</td><td>PU (pull-up) resistor</td></tr><tr><td>PD</td><td>PD (pull-down) resistor</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analogue signalling for gigabit media dependent interface</td></tr><tr><td>DP</td><td>Low voltage differential signal for DisplayPort interface</td></tr><tr><td>D-PHY</td><td>Low voltage differential signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>M-PHY</td><td>Low voltage differential signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS</td><td>Low voltage differential signal for LCD displays</td></tr><tr><td>PCIE</td><td>Low voltage differential signal for PCIe</td></tr><tr><td>SATA</td><td>Low voltage differential signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition minimized differential signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signalling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>VDD_IN</td><td>Main power source from Carrier to module</td></tr><tr><td>3.3V</td><td>3.3V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e., both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>Sleep</td><td>The module is in its lowest power state</td></tr><tr><td>Runtime</td><td>The module is full on. CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>Standby</td><td>The module is in standby state or higher</td></tr></table>

4.3 Full Signal to Pad Table

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module OSM-MTK510</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>GND</td><td>D18, E15, E21, F16, F20, J16, J20, L18, M16, M20, P18, R16, R20, V16, V20, Y18, AA14, AA17, AA19, AA22, AB15, AB21</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module signal and power return and GND reference</td></tr><tr><td>RESET_OUT#</td><td>T18</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>OSM_nRST_OUT</td><td>Logic IC</td><td></td><td>Reset output from the CPU to reset peripherals on the carrier.</td></tr><tr><td>RESET_IN#</td><td>U17</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>OSM_nRST_IN</td><td>Logic IC</td><td></td><td>Reset input from the carrier board. The carrier drives the line low to force a module reset and leaves the line floating otherwise.</td></tr><tr><td>CARRIER_PWR_EN</td><td>V17</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>CARRIER_PWR_EN</td><td>Logic IC</td><td></td><td>The carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal.</td></tr><tr><td>VCC_OUT_IO</td><td>U18</td><td>P</td><td>1.8V / 3.3V</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>Can provide I/O voltage level for several interfaces to connect</td></tr><tr><td>RTC_PWR</td><td>W17</td><td>P</td><td></td><td></td><td>VRTC28</td><td>MTK MT6365</td><td>L13</td><td>Low current RTC circuit backup power - 3.0V nominal. May be sourced from a carrier based Lithium cell or Super Cap.</td></tr><tr><td>BOOT_SEL0#</td><td>U19</td><td>I ODCMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>BOOT_SEL0_N</td><td>MOSFET</td><td></td><td></td></tr><tr><td>FORCE_RECOVERY#</td><td>T17</td><td>I ODCMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>FORCE_RECOV#</td><td>MTKMT8370</td><td>KPCOL0</td><td>If low on the carrier board, the module enters recovery mode.</td></tr><tr><td>JTAG_TCK(SWCLK)</td><td>N17</td><td>I CMOS</td><td rowspan="5">VCC_OUT_IO</td><td></td><td>MT8370_JTCK</td><td>MTKMT8370</td><td>JTCK</td><td>Test Clock</td></tr><tr><td>JTAG_TMS(SWDIO)</td><td>N19</td><td>I CMOS</td><td></td><td>MT8370_JTMS</td><td>MTKMT8370</td><td>JTMS</td><td>Test Mode Select</td></tr><tr><td>JTAG_TDI</td><td>P17</td><td>I CMOS</td><td></td><td>MT8370_JTDI</td><td>MTKMT8370</td><td>JTDI</td><td>Test Data Input</td></tr><tr><td>JTAG_TDO(SWO)</td><td>R17</td><td>O CMOS</td><td></td><td>MT8370_JTDO</td><td>MTKMT8370</td><td>JTDO</td><td>Test Data Output</td></tr><tr><td>JTAG_nTRST</td><td>R19</td><td>I CMOS</td><td></td><td>MT8370_JTRST</td><td>MTKMT8370</td><td>JTRST</td><td>Test Reset, Active Low</td></tr><tr><td>UART_A_RX</td><td>A14</td><td>I CMOS</td><td rowspan="4">VCC_OUT_IO</td><td></td><td>UART1_RXD</td><td>MTKMT8370</td><td>UART1_RXD</td><td>Asynchronous serial data input port A</td></tr><tr><td>UART_A_TX</td><td>B13</td><td>O CMOS</td><td></td><td>UART1_TXD</td><td>MTKMT8370</td><td>UART1_TXD</td><td>Asynchronous serial data output port A</td></tr><tr><td>UART_A_RTS</td><td>C13</td><td>O CMOS</td><td></td><td>UART1_RTS</td><td>MTKMT8370</td><td>GPIO02</td><td>Request to Send handshake line for port A</td></tr><tr><td>UART_A_CTS</td><td>C14</td><td>I CMOS</td><td></td><td>UART1_CTS</td><td>MTKMT8370</td><td>GPIO03</td><td>Clear to Send handshake line for port A</td></tr><tr><td>UART_C_RX</td><td>A22</td><td>I CMOS</td><td rowspan="2">VCC_OUT_IO</td><td></td><td>UART2_RXD</td><td>MTKMT8370</td><td>UART2_RXD</td><td>Asynchronous serial data input port C</td></tr><tr><td>UART_C_TX</td><td>B23</td><td>O CMOS</td><td></td><td>UART2_TXD</td><td>MTKMT8370</td><td>UART2_TXD</td><td>Asynchronous serial data output port C</td></tr><tr><td>UART_D_RX</td><td>C22</td><td>I CMOS</td><td>VCC_OUT_IO</td><td></td><td>UART3_RXD</td><td>MTKMT8370</td><td>I2SO2_D3</td><td>Asynchronous serial data input port D</td></tr><tr><td>UART_D_TX</td><td>C23</td><td>O CMOS</td><td></td><td></td><td>UART3_TXD</td><td>MTK MT8370</td><td>I2SO2_D2</td><td>Asynchronous serial data output port D</td></tr><tr><td>UART_CON_RX</td><td>D22</td><td>I CMOS</td><td rowspan="2">VCC_OUT_IO</td><td></td><td>UART0_RXD</td><td>MTK MT8370</td><td>UART0_RXD</td><td>Asynchronous serial data input port console</td></tr><tr><td>UART_CON_TX</td><td>D23</td><td>O CMOS</td><td></td><td>UART0_TXD</td><td>MTK MT8370</td><td>UART0_TXD</td><td>Asynchronous serial data output port console</td></tr><tr><td>ETH_A_(R)(G)MII_COL</td><td>F15</td><td>I CMOS</td><td rowspan="11">1.8V /2.5V / 3.3V</td><td></td><td>GBE_COL_1V8</td><td>MTK MT8370</td><td>DPI_HSYNC</td><td>Collision detects (half speed only) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD0</td><td>H15</td><td>O CMOS</td><td></td><td>GBE_TXD0_1V8</td><td>MTK MT8370</td><td>DPI_D3</td><td>Transmit data bit 0 (transmitted first) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD1</td><td>G15</td><td>O CMOS</td><td></td><td>GBE_TXD1_1V8</td><td>MTK MT8370</td><td>DPI_D2</td><td>Transmit data bit 1 port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD2</td><td>H16</td><td>O CMOS</td><td></td><td>GBE_TXD2_1V8</td><td>MTK MT8370</td><td>DPI_D1</td><td>Transmit data bit 2 port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD3</td><td>G16</td><td>O CMOS</td><td></td><td>GBE_TXD3_1V8</td><td>MTK MT8370</td><td>DPI_D0</td><td>Transmit data bit 3 port A</td></tr><tr><td>ETH_A_(R)(G)MII_TX_EN(ER)</td><td>K16</td><td>O CMOS</td><td></td><td>GBE_TXEN_1V8</td><td>MTK MT8370</td><td>DPI_D11</td><td>Transmit enable (Error) port A</td></tr><tr><td>ETH_A_(R)(G)MII_TX_CLK</td><td>J15</td><td>I/O CMOS</td><td></td><td>GBE_TXC_1V8</td><td>MTK MT8370</td><td>DPI_D8</td><td>Transmit clock port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD0</td><td>K15</td><td>I CMOS</td><td></td><td>GBE_RXD0_1V8</td><td>MTK MT8370</td><td>DPI_D7</td><td>Receive data bit 0 (received first) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD1</td><td>L15</td><td>I CMOS</td><td></td><td>GBE_RXD1_1V8</td><td>MTK MT8370</td><td>DPI_D6</td><td>Receive data bit 1 port A</td></tr><tr><td>TH_A_(R)(G)MII_RXD2</td><td>N15</td><td>I CMOS</td><td></td><td>GBE_RXD2_1V8</td><td>MTK MT8370</td><td>DPI_D5</td><td>Receive data bit 2 port A</td></tr><tr><td>ETH_A_(R)(G)MII_RXD3</td><td>P15</td><td>I CMOS</td><td></td><td>GBE_RXD3_1V8</td><td>MTK MT8370</td><td>DPI_D4</td><td>Receive data bit 3 port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_ER</td><td>L16</td><td>I CMOS</td><td rowspan="6"></td><td></td><td>GBE_RXER_1V8</td><td>MTK MT8370</td><td>DPI_D15</td><td>Receive error port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_DV(ER)</td><td>M15</td><td>I CMOS</td><td></td><td>GBE_RXDV_1V8</td><td>MTK MT8370</td><td>DPI_D10</td><td>Receive data valid port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_CLK</td><td>R15</td><td>I/O CMOS</td><td></td><td>GBE_RXC_1V8</td><td>MTK MT8370</td><td>DPI_D9</td><td>Receive clock port A</td></tr><tr><td>ETH_MDIO</td><td>T15</td><td>I/O CMOS</td><td></td><td>GBE_MDIO_1V8</td><td>MTK MT8370</td><td>DPI_D13</td><td>Management bus data signal for Ethernet</td></tr><tr><td>ETH_MDC</td><td>T16</td><td>O CMOS</td><td></td><td>GBE_MDC_1V8</td><td>MTK MT8370</td><td>DPI_D12</td><td>Management bus clock signal for Ethernet</td></tr><tr><td>ETH_IOPWR</td><td>M17</td><td>PO</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>ETH voltage. It is used to provide the I/O Voltage Level for all Ethernet interfaces.</td></tr><tr><td>GPIO_A_0</td><td>D17</td><td>I/O CMOS</td><td rowspan="8">VCC_OUT_IO</td><td></td><td>GPIO_02</td><td>MTK MT8370</td><td>SPIM0_MOSI</td><td>General purpose I/O Contact A0</td></tr><tr><td>GPIO_A_1</td><td>E17</td><td></td><td></td><td>GPIO_04</td><td>MTK MT8370</td><td>SPIM0_MIO2</td><td>General purpose I/O Contact A1</td></tr><tr><td>GPIO_A_2</td><td>F17</td><td></td><td></td><td>GPIO_05</td><td>MTK MT8370</td><td>SPIM0_MIO3</td><td>General purpose I/O Contact A2</td></tr><tr><td>GPIO_A_3</td><td>G17</td><td></td><td></td><td>GPIO_03</td><td>MTK MT8370</td><td>SPIM0_MIO1</td><td>General purpose I/O Contact A3</td></tr><tr><td>GPIO_A_4</td><td>H17</td><td></td><td></td><td>GBE_TXER_1V8</td><td>MTK MT8370</td><td>DPI_D14</td><td>General purpose I/O Contact A4</td></tr><tr><td>GPIO_A_5</td><td>J17</td><td></td><td></td><td>GBE_INTR_1V8</td><td>MTK MT8370</td><td>DPI_D15</td><td>General purpose I/O Contact A5</td></tr><tr><td>GPIO_B_0</td><td>D19</td><td></td><td></td><td>GPIO_12</td><td>MTK MT8370</td><td>GPIO12</td><td>General purpose I/O Contact B0</td></tr><tr><td>GPIO_B_1</td><td>E19</td><td></td><td></td><td>GPIO_13</td><td>MTK MT8370</td><td>GPIO13</td><td>General purpose I/O Contact B1</td></tr><tr><td>GPIO_B_2</td><td>F19</td><td></td><td rowspan="6"></td><td></td><td>GPIO_14</td><td>MTK MT8370</td><td>GPIO14</td><td>General purpose I/O Contact B2</td></tr><tr><td>GPIO_B_3</td><td>G19</td><td></td><td></td><td>GPIO_15</td><td>MTK MT8370</td><td>GPIO15</td><td>General purpose I/O Contact B3</td></tr><tr><td>GPIO_B_4</td><td>H19</td><td></td><td></td><td>GPIO_17</td><td>MTK MT8370</td><td>I2SIN_WS</td><td>General purpose I/O Contact B4</td></tr><tr><td>GPIO_B_5</td><td>J19</td><td></td><td></td><td>GPIO_08</td><td>MTK MT8370</td><td>CMMRST1</td><td>General purpose I/O Contact B5</td></tr><tr><td>GPIO_B_6</td><td>K19</td><td></td><td></td><td>GPIO_06</td><td>MTK MT8370</td><td>CMMPDN1</td><td>General purpose I/O Contact B6</td></tr><tr><td>GPIO_B_7</td><td>L19</td><td></td><td></td><td>GPIO_01</td><td>MTK MT8370</td><td>GPIO01</td><td>General purpose I/O Contact B7</td></tr><tr><td>SDIO_A_CMD</td><td>E20</td><td>I/O CMOS</td><td rowspan="4">1.8V / 3.3V</td><td></td><td>MSDC1_CMD</td><td>MTK MT8370</td><td>MSDC1_CMD</td><td>SDIO A Command/Response: This signal is used for card initialization and for command transfers. During initialization, this signal is open-drain. During command transfers, this signal is in push-pull mode.</td></tr><tr><td>SDIO_A_CLK</td><td>F21</td><td>O CMOS</td><td></td><td>MSDC1_CLK</td><td>MTK MT8370</td><td>MSDC1_CLK</td><td>SDIO A Clock: With each cycle of this signal, a one-bit transfer occurs on the command and each of the data line.</td></tr><tr><td>SDIO_A_D0</td><td>G20</td><td>I/O CMOS</td><td></td><td>MSDC1_DAT0</td><td>MTK MT8370</td><td>MSDC1_DAT0</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D1</td><td>G21</td><td>I/O CMOS</td><td></td><td>MSDC1_DAT1</td><td>MTK MT8370</td><td>MSDC1_DAT1</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D2</td><td>H20</td><td>I/O CMOS</td><td rowspan="7"></td><td></td><td>MSDC1_DAT2</td><td>MTK MT8370</td><td>MSDC1_DAT2</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D3</td><td>H21</td><td>I/O CMOS</td><td></td><td>MSDC1_DAT3</td><td>MTK MT8370</td><td>MSDC1_DAT3</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_CD#</td><td>J21</td><td>I OD CMOS</td><td>PU 10K</td><td>MSDC1_INSI</td><td>MTK MT8370</td><td>GPIO06</td><td>SDIO A Card Detect: This signal indicates when a SDIO/MMC card is present.</td></tr><tr><td>SDIO_A_WP</td><td>D20</td><td>I OD CMOS</td><td>PU 10K</td><td>MSDC1_WP</td><td>MTK MT8370</td><td>GPIO05</td><td>SDIO A Write Protect: This signal denotes the state of the write-protect tab on SD cards.</td></tr><tr><td>SDIO_A_PWR_EN</td><td>D21</td><td>O CMOS</td><td></td><td>EXT_VMSDC1_EN</td><td>MTK MT8370</td><td>GPIO04</td><td>SDIO A Power Enabled: This signal is used to enable the power being supplied to a SD/MMC card device.</td></tr><tr><td>SDIO_A_IOPWR</td><td>C20</td><td>PO</td><td></td><td>VSIM1_PMU</td><td>MTK MT6365</td><td>VSIM1</td><td>SDIO A Voltage: It is used to provide the I/O Voltage Level</td></tr><tr><td>SDIO_B_CLK</td><td>K20</td><td>O CMOS</td><td></td><td>MSDC2_CLK</td><td>MTK MT8370</td><td>MSDC2_CLK</td><td>SDIO B Clock: With each cycle of this signal, a one-bit transfer occurs on the command and each of the data line.</td></tr><tr><td>SDIO_B_CMD</td><td>K21</td><td>I/O CMOS</td><td rowspan="6"></td><td></td><td>MSDC2_CMD</td><td>MTK MT8370</td><td>MSDC2_CMD</td><td>SDIO B Command/Response: This signal is used for card initialization and for command transfers. During initialization, this signal is open-drain. During the command transfers, this signal is in push-pull mode.</td></tr><tr><td>SDIO_B_D0</td><td>L20</td><td>I/O CMOS</td><td></td><td>MSDC2_DAT0</td><td>MTK MT8370</td><td>MSDC2_DAT0</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D1</td><td>L21</td><td>I/O CMOS</td><td></td><td>MSDC2_DAT1</td><td>MTK MT8370</td><td>MSDC2_DAT1</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D2</td><td>M21</td><td>I/O CMOS</td><td></td><td>MSDC2_DAT2</td><td>MTK MT8370</td><td>MSDC2_DAT2</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D3</td><td>N20</td><td>I/O CMOS</td><td></td><td>MSDC2_DAT3</td><td>MTK MT8370</td><td>MSDC2_DAT3</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_IOPWR</td><td>T20</td><td>PO</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>SDIO B Voltage: It is used to provide the I/O Voltage Level</td></tr><tr><td>PWM_0</td><td>E18</td><td>O CMOS</td><td rowspan="5">VCC_OUT_IO</td><td></td><td>DSIO_DISP_PWM</td><td>MTK MT8370</td><td>DISP_PWM0</td><td>Pulse width modulation 0</td></tr><tr><td>PWM_1</td><td>F18</td><td>O CMOS</td><td></td><td>OSM_PWM_1</td><td>MTK MT8370</td><td>CMMCLK1</td><td>Pulse width modulation 1</td></tr><tr><td>PWM_2</td><td>G18</td><td>O CMOS</td><td></td><td>OSM_PWM_2</td><td>MTK MT8370</td><td>CMMCLK2</td><td>Pulse width modulation 2</td></tr><tr><td>PWM_3</td><td>H18</td><td>O CMOS</td><td></td><td>OSM_PWM_3</td><td>MTK MT8370</td><td>GPIO09</td><td>Pulse width modulation 3</td></tr><tr><td>PWM_4</td><td>J18</td><td>O CMOS</td><td></td><td>OSM_PWM_4</td><td>MTK MT8370</td><td>GPIO10</td><td>Pulse width modulation 4</td></tr><tr><td>ADC_0</td><td>M18</td><td>Analog</td><td rowspan="2">0V - 1.8V</td><td></td><td>AUXIN1_1V8</td><td>MTK MT8370</td><td>AUXIN1</td><td>Analog Digital Converter 0</td></tr><tr><td>ADC_1</td><td>N18</td><td>Analog</td><td></td><td>AUXIN2_1V8</td><td>MTK MT8370</td><td>AUXIN2</td><td>Analog Digital Converter 1</td></tr><tr><td>SPI_A_SDI_(IO0)</td><td>U15</td><td>I/O CMOS</td><td rowspan="10">VCC_OUT_IO</td><td></td><td>SPINOR_IO0</td><td>MTK MT8370</td><td>DMIC1_DAT_R</td><td>SPI A Serial Data Input</td></tr><tr><td>SPI_A_SDO_(IO1)</td><td>V15</td><td>I/O CMOS</td><td></td><td>SPINOR_IO1</td><td>MTK MT8370</td><td>DMIC2_CLK</td><td>SPI A Serial Data Output</td></tr><tr><td>SPI_A/WP_(IO2)</td><td>W16</td><td>I/O CMOS</td><td></td><td>SPINOR_IO2</td><td>MTK MT8370</td><td>DMIC2_DAT</td><td>SPI A Write Protect</td></tr><tr><td>SPI_A/HOLD_(IO3)</td><td>W15</td><td>I/O CMOS</td><td></td><td>SPINOR_IO3</td><td>MTK MT8370</td><td>DMIC2_DAT_R</td><td>SPI A Suspends Serial Input</td></tr><tr><td>SPI_A_CS0#</td><td>Y15</td><td>O CMOS</td><td></td><td>SPINOR_CS_N</td><td>MTK MT8370</td><td>DMIC1_DAT</td><td>SPI A Master Chip Select 0</td></tr><tr><td>SPI_A_SCK</td><td>U16</td><td>O CMOS</td><td></td><td>SPINOR_CLK</td><td>MTK MT8370</td><td>DMIC1_CLK</td><td>SPI A Serial Data Clock</td></tr><tr><td>SPI_B_SDI</td><td>Y22</td><td>I CMOS</td><td></td><td>SPIM1_MOSI</td><td>MTK MT8370</td><td>SPIM1_MOSI</td><td>SPI B Serial Data Input</td></tr><tr><td>SPI_B_SDO</td><td>Y23</td><td>O CMOS</td><td></td><td>SPIM1_MISO</td><td>MTK MT8370</td><td>SPIM1_MISO</td><td>SPI B Serial Data Output</td></tr><tr><td>SPI_B_CS0#</td><td>AA23</td><td>O CMOS</td><td></td><td>SPIM1_CS_N</td><td>MTK MT8370</td><td>SPIM1_CS</td><td>SPI B Master Chip Select 0</td></tr><tr><td>SPI_B_SCK</td><td>Y21</td><td>O CMOS</td><td></td><td>SPIM1_CLK</td><td>MTK MT8370</td><td>SPIM1_CLK</td><td>SPI B Serial Data Clock</td></tr><tr><td>I2S_A_DATA_IN</td><td>V21</td><td>I/O CMOS</td><td rowspan="3">VCC_OUT_IO</td><td></td><td>I2S_IN_D0</td><td>MTK MT8370</td><td>I2SIN_D0</td><td>I2S A Digital audio Input</td></tr><tr><td>I2S_A_DATA_OUT</td><td>W21</td><td></td><td></td><td>I2S_OUT_D0</td><td>MTK MT8370</td><td>I2SO2_D0</td><td>I2S A Digital audio Output</td></tr><tr><td>I2S_B_DATA_IN</td><td>V19</td><td></td><td></td><td></td><td></td><td></td><td>I2S B Digital audio Input</td></tr><tr><td>I2S_B_DATA_OUT</td><td>W19</td><td></td><td rowspan="4"></td><td></td><td></td><td></td><td></td><td>I2S B Digital audio Output</td></tr><tr><td>I2S_MCLK</td><td>V18</td><td></td><td></td><td>I2S_IO_MCK</td><td>MTK MT8370</td><td>I2SO2_MCK</td><td>Master clock output to I2S codec(s)</td></tr><tr><td>I2S_LRCLK</td><td>W18</td><td></td><td></td><td>I2S_IO_WS</td><td>MTK MT8370</td><td>I2SO2_WS</td><td>I2S Left &amp; Right synchronization clock</td></tr><tr><td>I2S_BITCLK</td><td>W20</td><td></td><td></td><td>I2S_IO_BCK</td><td>MTK MT8370</td><td>I2SO2_BCK</td><td>I2S Digital audio clock</td></tr><tr><td>USB_A_D_N</td><td>AB13</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P0</td><td>MTK MT8370</td><td>USB_DM_P0</td><td>USB differential data pairs for port A</td></tr><tr><td>USB_A_D_P</td><td>AC14</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P0</td><td>MTK MT8370</td><td>USB_DP_P0</td><td>USB differential data pairs for port A</td></tr><tr><td>USB_A_ID</td><td>AB14</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>USB0_IDDIG</td><td>MTK MT8370</td><td>USB0_IDDIG</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td></tr><tr><td>USB_A_OC#</td><td>AC15</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>USB0_OC_N</td><td>MTK MT8370</td><td>KPCOL1</td><td>USB over-current for port A</td></tr><tr><td>USB_A_VBUS</td><td>AB16</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB0_VBUS_5V</td><td>MTK MT8370</td><td>USB0_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_A_EN</td><td>AC16</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>USB0_DRV_VBUS</td><td>MTK MT8370</td><td>USB0_DRV_VBUS</td><td>Power enables for USB VBUS voltage</td></tr><tr><td>USB_B_D_N</td><td>AB23</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P2</td><td>MTK MT8370</td><td>USB_DM_P2</td><td>USB differential data pairs for port B</td></tr><tr><td>USB_B_D_P</td><td>AC22</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P2</td><td>MTK MT8370</td><td>USB_DP_P2</td><td>USB differential data pairs for port B</td></tr><tr><td>USB_B_ID</td><td>AB22</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>USB2_IDDIG</td><td>MTK MT8370</td><td>USB2_IDDIG</td><td>Input Contact to announce OTG device insertion on th eUSB 2.0 port</td></tr><tr><td>USB_B_OC#</td><td>AC21</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>USB2_OC_N</td><td>MTK MT8370</td><td>SPIMO_CLK</td><td>USB over-current for port B</td></tr><tr><td>USB_B_VBUS</td><td>AB20</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB2_VBUS_5V</td><td>MTK MT8370</td><td>USB2_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_B_EN</td><td>AC20</td><td>O CMOS</td><td>1.8V</td><td></td><td>USB2_DRV_VBUS</td><td>MTK MT8370</td><td>USB2_DRV_VBUS</td><td>Power enable for USB VBUS voltage</td></tr><tr><td>I2C_A_SCL</td><td>AA15</td><td>I/O OD CMOS</td><td>VCC_OUT_IO, Size-0 only 1.8V, &gt;Size-0</td><td>PU 2k2</td><td>SCL0_A</td><td>MTK MT8370</td><td>SCL0</td><td>I2C Port A Clock Signal</td></tr><tr><td>I2C_A_SDA</td><td>AA16</td><td></td><td></td><td></td><td>SDA0_A</td><td>MTK MT8370</td><td>SDA0</td><td>I2C Port A Data Signal</td></tr><tr><td>I2C_B_SCL</td><td>AA20</td><td></td><td></td><td></td><td>SCL2_B</td><td>MTK MT8370</td><td>SCL2</td><td>I2C Port B Clock Signal</td></tr><tr><td>I2C_B_SDA</td><td>AA21</td><td></td><td></td><td></td><td>SDA2_B</td><td>MTK MT8370</td><td>SDA2</td><td>I2C Port B Data Signal</td></tr><tr><td>RESERVED</td><td>T19, Y13, Y14, AA13</td><td></td><td></td><td></td><td></td><td></td><td></td><td>Reserved for future use</td></tr><tr><td>Vendor Defined</td><td>B22, C16, P16</td><td></td><td></td><td></td><td></td><td></td><td></td><td>Defined by module manufacturer</td></tr><tr><td>GND</td><td>A4, A7, A10, B2, B5, B8, B9, C11, D1, D5, D8, E2, H2, H4, L2, L4, P2, P4, R1, U2, U4, V1, W3, Y2, AA1, AA4, AA7, AA8, AA10, AA11, AB3, AB6, AB9, AC4, AC7, AC10</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module signal and power return and GND reference</td></tr><tr><td>PWR_BTN#</td><td>AA9</td><td>I ODCMOS</td><td>1.8 to 5V</td><td>PU 10K</td><td>PWR_KEY_N</td><td>MTKMT6365</td><td>PWRKEY</td><td>Power-button input from the carrier board. The carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the module.</td></tr><tr><td>GPIO_C_0</td><td>D3</td><td>I/O CMOS</td><td rowspan="6">VCC_OUT_IO</td><td></td><td>GPIO_00</td><td>MTKMT8370</td><td>GPIO00</td><td>General purpose I/O Contact C0</td></tr><tr><td>GPIO_C_1</td><td>D4</td><td>I/O CMOS</td><td></td><td>GPIO_11</td><td>MTKMT8370</td><td>GPIO11</td><td>General purpose I/O Contact C1</td></tr><tr><td>GPIO_C_2</td><td>E3</td><td>I/O CMOS</td><td></td><td>GPIO_09</td><td>MTKMT8370</td><td>DSI1_LCM_RST</td><td>General purpose I/O Contact C2</td></tr><tr><td>GPIO_C_3</td><td>E4</td><td>I/O CMOS</td><td></td><td>GPIO_07</td><td>MTKMT8370</td><td>GPIO07</td><td>General purpose I/O Contact C3</td></tr><tr><td>GPIO_C_4</td><td>F3</td><td>I/O CMOS</td><td></td><td>DISP_VDD_EN</td><td>MTKMT8370</td><td>I2SIN_D1</td><td>General purpose I/O Contact C4</td></tr><tr><td>GPIO_C_5</td><td>F4</td><td>I/O CMOS</td><td></td><td>DISP_BL_EN</td><td>MTKMT8370</td><td>KPROW1</td><td>General purpose I/O Contact C5</td></tr><tr><td>DSI_DATA0_N</td><td>AB11</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D0N</td><td>MTKMT8370</td><td>DSI0_D0N_T1A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA0_P</td><td>AB10</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D0P</td><td>MTKMT8370</td><td>DSI0_D0P_T0C</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA1_N</td><td>AC9</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D1N</td><td>MTKMT8370</td><td>DSI0_D1N_T2B</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA1_P</td><td>AC8</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D1P</td><td>MTKMT8370</td><td>DSI0_D1P_T2A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA2_N</td><td>AC6</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D2N</td><td>MTKMT8370</td><td>DSI0_D2N_T0B</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA2_P</td><td>AC5</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D2P</td><td>MTKMT8370</td><td>DSI0_D2P_T0A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA3_N</td><td>AB5</td><td>O LVDSD-PHY</td><td></td><td></td><td>DSI0_D3N</td><td>MTKMT8370</td><td>DSI0_D3N</td><td>DSI differential output(point to point)</td></tr><tr><td>DSI_DATA3_P</td><td>AB4</td><td>O LVDSD-PHY</td><td></td><td></td><td>DSI0_D3P</td><td>MTKMT8370</td><td>DSI0_D3P_T2C</td><td>DSI differential output(point to point)</td></tr><tr><td>DSI_CLOCK_N</td><td>AB8</td><td>O LVDSD-PHY</td><td></td><td></td><td>DSI0_CKN</td><td>MTKMT8370</td><td>DSI0_CKN_T1C</td><td>DSI differential clockoutput (point to point)</td></tr><tr><td>DSI_CLOCK_P</td><td>AB7</td><td>O LVDSD-PHY</td><td></td><td></td><td>DSI0_CKP</td><td>MTKMT8370</td><td>DSI0_CKP_T1B</td><td>DSI differential clockoutput (point to point)</td></tr><tr><td>DSI_TE</td><td>AA3</td><td>I CMOS</td><td>VCC_OUT_IO</td><td></td><td>DSI0_TE</td><td>MTKMT8370</td><td>DSI0_DSI_TE</td><td>DSI panel tearing effectsignal</td></tr><tr><td>DISP_VDD_EN / GPIO_C_4</td><td>F3</td><td>OCMOS</td><td>VCC_OUT_IO</td><td></td><td>DISP_VDD_EN</td><td>MTKMT8370</td><td>I2SIN_D1</td><td>Primary Display power enable, active high</td></tr><tr><td>DISP_BL_EN / GPIO_C_5</td><td>F4</td><td>OCMOS</td><td>VCC_OUT_IO</td><td></td><td>DISP_BL_EN</td><td>MTKMT8370</td><td>KPROW1</td><td>Primary Displaybacklight enable, activehigh</td></tr><tr><td>CSI_DATA0_N</td><td>C1</td><td>I LVDSD-PHY/I LVDSM-PHY</td><td></td><td></td><td>CSI0_DAT0_N</td><td>MTKMT8370</td><td>CSI0A_L1N_T1A</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA0_P</td><td>B1</td><td></td><td></td><td></td><td>CSI0_DAT0_P</td><td>MTKMT8370</td><td>CSI0A_L1P_T0C</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA1_N</td><td>A2</td><td></td><td></td><td></td><td>CSI0_DAT1_N</td><td>MTKMT8370</td><td>CSI0B_L0N_T0B</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA1_P</td><td>A3</td><td></td><td></td><td></td><td>CSI0_DAT1_P</td><td>MTKMT8370</td><td>CSI0B_L0P_T0A</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA2_N</td><td>A5</td><td></td><td></td><td></td><td>CSI0_DAT2_N</td><td>MTKMT8370</td><td>CSI0A_L0N_T0A</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA2_P</td><td>A6</td><td></td><td></td><td></td><td>CSI0_DAT2_P</td><td>MTKMT8370</td><td>CSI0A_L0P_T0B</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA3_N</td><td>B6</td><td></td><td></td><td></td><td>CSI0_DAT3_N</td><td>MTKMT8370</td><td>CSI0B_L1N_T1A</td><td>CSI differential input(point to point)</td></tr><tr><td>CSI_DATA3_P</td><td>B7</td><td></td><td></td><td></td><td>CSI0_DAT3_P</td><td>MTK MT8370</td><td>CSI0B_L1P_T0C</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_CLOCK_N</td><td>B3</td><td>I LVDS D-PHY</td><td></td><td></td><td>CSI0_CLK_N</td><td>MTK MT8370</td><td>CSI0A_L2N_T1C</td><td>CSI differential clock input (point to point)</td></tr><tr><td>CSI_CLOCK_P</td><td>B4</td><td>I LVDS D-PHY</td><td></td><td></td><td>CSI0_CLK_P</td><td>MTK MT8370</td><td>CSI0A_L2P_T1B</td><td>CSI differential clock input (point to point)</td></tr><tr><td>CAM_MCK</td><td>C2</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>CMMCLK0</td><td>MTK MT8370</td><td>CMMCLK0</td><td>Master clock output</td></tr><tr><td>I2C_CAM_SDA / CSI_TX_N</td><td>C3</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA5_CAM</td><td>MTK MT8370</td><td>SDA5</td><td>I2C data for serial camera data support link or differential data lane</td></tr><tr><td>I2C_CAM_SCL / CSI_TX_P</td><td>C4</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL5_CAM</td><td>MTK MT8370</td><td>SCL5</td><td>I2C clock for serial camera data support link or differential data lane</td></tr><tr><td>CAM_PWR / GPIO_C_6</td><td>G3</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>CAM_PWR_EN</td><td>MTK MT8370</td><td>CMMPDN0</td><td>Camera 0 Power Enable, active high output.</td></tr><tr><td>CAM_RST# / GPIO_C_7</td><td>G4</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>CMMRST0_N</td><td>MTK MT8370</td><td>CMMRST0</td><td>Camera 0 reset, active low output</td></tr><tr><td>USB_C_D_N</td><td>D11</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P1</td><td>MTK MT8370</td><td>USB_DM_P1</td><td>USB differential data pairs for port C</td></tr><tr><td>USB_C_D_P</td><td>D10</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P1</td><td>MTK MT8370</td><td>USB_DP_P1</td><td>USB differential data pairs for port C</td></tr><tr><td>USB_C_ID</td><td>D9</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>USB1_IDDIG</td><td>MTK MT8370</td><td>USB1_IDDIG</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td></tr><tr><td>USB_C_OC#</td><td>C8</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>USB1_OC_N</td><td>MTK MT8370</td><td>KPROW0</td><td>USB over-current for port C</td></tr><tr><td>USB_C_VBUS</td><td>C9</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB1_VBUS_5V</td><td>MTK MT8370</td><td>USB1_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_C_EN</td><td>C10</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>USB1_DRV_VBUS</td><td>MTK MT8370</td><td>USB1_DRV_VBUS</td><td>Power enable for USB VBUS voltage</td></tr><tr><td>USB_C_SSTX_N</td><td>A9</td><td>O USB SS</td><td>USB SS</td><td></td><td>SSUSB_TXN_P1</td><td>MTK MT8370</td><td>SSUSB_TXN</td><td>Transmit signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSTX_P</td><td>A8</td><td>O USB SS</td><td>USB SS</td><td></td><td>SSUSB_TXP_P1</td><td>MTK MT8370</td><td>SSUSB_TXP</td><td>Transmit signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSRX_N</td><td>B11</td><td>I USB SS</td><td>USB SS</td><td></td><td>SSUSB_RXN_P1</td><td>MTK MT8370</td><td>SSUSB_RXN</td><td>Receive signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSRX_P</td><td>B10</td><td>I USB SS</td><td>USB SS</td><td></td><td>SSUSB_RXP_P1</td><td>MTK MT8370</td><td>SSUSB_RXP</td><td>Receive signal differential pairs for SuperSpeed on port C</td></tr><tr><td>PCIe_A_HSI0_P</td><td>AB1</td><td>I LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_RXP</td><td>MTK MT8370</td><td>PCIE_LNO_RXP</td><td>Differential PCIe link A receive data pair</td></tr><tr><td>PCIe_A_HSI0_N</td><td>AB2</td><td>I LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_RXN</td><td>MTK MT8370</td><td>PCIE_LNO_RXN</td><td>Differential PCIe link A receive data pair</td></tr><tr><td>PCIe_A_HSO0_P</td><td>AC2</td><td>O LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_TXP</td><td>MTK MT8370</td><td>PCIE_LNO_TXP</td><td>Differential PCIe link A transmit data pair</td></tr><tr><td>PCIe_A_HSO0_N</td><td>AC3</td><td>O LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_TXN</td><td>MTK MT8370</td><td>PCIE_LNO_TXN</td><td>Differential PCIe link A transmit data pair</td></tr><tr><td>PCIe_CLKREQ#</td><td>W2</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>PCIEG2_CLKREQ_N</td><td>MTK MT8370</td><td>PCIE_CLKREQ</td><td>PCIe reference clock request</td></tr><tr><td>PCIe_A_PERST#</td><td>V21</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>PCIEG2_PERESET_N</td><td>MTK MT8370</td><td>PCIE_PERESET</td><td>PCIe Port A reset output</td></tr><tr><td>PCIe_REFCLK_P</td><td>W1</td><td>O LVDS PCIE</td><td></td><td>PD 49.9 (MTK request)</td><td>PCIEG2_CLK_P</td><td>MTK MT8370</td><td>PCIE_CKP</td><td>Differential PCIe reference clock output</td></tr><tr><td>PCIe_REFCLK_N</td><td>Y1</td><td>O LVDS PCIE</td><td></td><td>PD 49.9 (MTK request)</td><td>PCIEG2_CLK_N</td><td>MTK MT8370</td><td>PCIE_CKN</td><td>Differential PCIe reference clock output</td></tr><tr><td>PCIe_WAKE#</td><td>T2</td><td>I ODCMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>PCIEG2_WAKE_N</td><td>MTKMT8370</td><td>PCIE_WAKE</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td></tr><tr><td>PCIe_SMDAT</td><td>U1</td><td>I/O ODCMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA3_PCIE</td><td>MTKMT8370</td><td>SDA3</td><td>System management I2C bus DATA</td></tr><tr><td>PCIe_SMCLK</td><td>T1</td><td>O ODCMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL3_PCIE</td><td>MTKMT8370</td><td>SCL3</td><td>System management I2C bus CLK</td></tr><tr><td>PCIe_SM_ALERT#</td><td>R2</td><td>I ODCMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>PCIE_SM_ALERT_N</td><td>MTKMT8370</td><td>SPIM0_CS</td><td>SMBus Alert# (interrupt) signal</td></tr><tr><td>DSI0_RST (Vendor Defined)</td><td>D6</td><td>O</td><td>1.8V</td><td></td><td>DSI0_RST</td><td>MTKMT8370</td><td>DSI0_LCM_RST</td><td>Defined by module manufacturer</td></tr><tr><td>VCC_IN_5V</td><td>Y25, Y26, Y27, Y28</td><td>P</td><td></td><td></td><td>VCC_IN_5V</td><td>Buck IC</td><td></td><td>Module power input voltage of 5V</td></tr><tr><td>GND</td><td>A26, A29, A32, B27, B28, B30, B33, C25, C32, C35, D28, D34, F33, F35, G34, H32, J33, J35, K34, M35, N34, T34, W34, AA25, AA26, AA27, AA28, AA32, AB28, AB31, AB34, AC27, AC30, AC33</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module signal and power return and GND reference</td></tr><tr><td>GPIO_D_0</td><td>U32</td><td>I/OCMOS</td><td>1.8V</td><td></td><td>GPIO_16</td><td>MTKMT8370</td><td>DSI1_DSI_TE</td><td>General purpose I/O Contact D0</td></tr><tr><td>SPI_C_SDI</td><td>C29</td><td>I CMOS</td><td>1.8V</td><td></td><td>SPIM2_MOSI</td><td>MTKMT8370</td><td>SPIM2_MOSI</td><td>SPI C Serial Data Input</td></tr><tr><td>SPI_C_SDO</td><td>D30</td><td>OCMOS</td><td>1.8V</td><td></td><td>SPIM2_MISO</td><td>MTKMT8370</td><td>SPIM2_MISO</td><td>SPI C Serial Data Output</td></tr><tr><td>SPI_C_CS0#</td><td>C30</td><td>OCMOS</td><td>1.8V</td><td></td><td>SPIM2_CS_N</td><td>MTKMT8370</td><td>SPIM2_CS</td><td>SPI C Master Chip Select 0</td></tr><tr><td>SPI_C_SCK</td><td>D29</td><td>O CMOS</td><td>1.8V</td><td></td><td>SPIM2_CLK</td><td>MTK MT8370</td><td>SPIM2_CLK</td><td>SPI C Serial Data Clock</td></tr><tr><td>eDP_A_LANE0_P</td><td>A30</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH0_P</td><td>MTK MT8370</td><td>HDMITX21_CH0_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE0_N</td><td>A31</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH0_M</td><td>MTK MT8370</td><td>HDMITX21_CH0_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE1_P</td><td>B31</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH1_P</td><td>MTK MT8370</td><td>HDMITX21_CH1_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE1_N</td><td>B32</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH1_M</td><td>MTK MT8370</td><td>HDMITX21_CH1_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE2_P</td><td>A33</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH2_P</td><td>MTK MT8370</td><td>HDMITX21_CH2_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE2_N</td><td>A34</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH2_M</td><td>MTK MT8370</td><td>HDMITX21_CH2_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE3_P</td><td>B34</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CLK_P</td><td>MTK MT8370</td><td>HDMITX21_CLK_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE3_N</td><td>B35</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CLK_M</td><td>MTK MT8370</td><td>HDMITX21_CLK_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_AUX_P</td><td>C33</td><td>I/O LVDS DP</td><td>1.8V (HDMI)</td><td>PD 100k PU 2k2 (HDMI)</td><td>HDMI_TX_SDA</td><td>MTK MT8370</td><td>HDMITX_SDA</td><td>Primary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_A_AUX_N</td><td>C34</td><td>I/O LVDS DP</td><td>1.8V (HDMI)</td><td>PD 100k PU 2k2 (HDMI)</td><td>HDMI_TX_SCL</td><td>MTK MT8370</td><td>HDMITX_SCL</td><td>Primary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_A_BL_HPD</td><td>D33</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>PD 1M</td><td>HDMI_TX_HPD</td><td>MTK MT8370</td><td>HDMITX_HTPLG</td><td>Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer.</td></tr><tr><td>eDP_A_BL_EN</td><td>D31</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>HDMI_TX_PWR_EN</td><td>MTK MT8370</td><td>HDMITX_PWR5V</td><td>Primary eDP panel backlight enabled, active high</td></tr><tr><td>eDP_A_BL_PWM</td><td>C31</td><td>O CMOS</td><td>VCC_OUT_IO</td><td>PU 4k7 (HDMI)</td><td>HDMI_TX_CEC</td><td>MTK MT8370</td><td>HDMITX_CEC</td><td>Primary eDP panel brightness control through pulse width modulation</td></tr><tr><td>eDP_B_LANE0_P</td><td>D35</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L0_TXP</td><td>MTK MT8370</td><td>EDP_LN0_TXP</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE0_N</td><td>E35</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L0_TXN</td><td>MTK MT8370</td><td>EDP_LN0_TXN</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE1_P</td><td>E34</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L1_TXP</td><td>MTK MT8370</td><td>EDP_LN1_TXP</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE1_N</td><td>F34</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L1_TXN</td><td>MTK MT8370</td><td>EDP_LN1_TXN</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_AUX_P</td><td>G33</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>EDP_AUX_P</td><td>MTK MT8370</td><td>EDPAUXP</td><td>Secondary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_B_AUX_N</td><td>H33</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>EDP_AUX_N</td><td>MTK MT8370</td><td>EDPAUXN</td><td>Secondary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_B_BL_HPD</td><td>G32</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>PD 1M</td><td>EDP_HPD</td><td>MTK MT8370</td><td>GPIO17</td><td>Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer.</td></tr><tr><td>eDP_B_BL_EN</td><td>E32</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>EDP_BL_EN</td><td>MTK MT8370</td><td>GPIO08</td><td>Secondary eDP panel backlight enabled, active high</td></tr><tr><td>eDP_B_BL_PWM</td><td>E33</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>EDP_BL_PWM</td><td>MTK MT8370</td><td>DISP_PWM1</td><td>Secondary eDP panel brightness control through pulse width modulation</td></tr><tr><td>PCM_CLK (Vendor Defined)</td><td>Y29</td><td>DIO</td><td rowspan="4">1.8V</td><td></td><td>PCM_CLK_1V8</td><td>MTK MT8370</td><td>PCM_CLK</td><td>Defined by module manufacturer (PCM clock)</td></tr><tr><td>PCM_SYNC (Vendor Defined)</td><td>Y30</td><td>DIO</td><td></td><td>PCM_SYNC_1V8</td><td>MTK MT8370</td><td>PCM_SYNC</td><td>Defined by module manufacturer (PCM synchronization)</td></tr><tr><td>PCM_DO (Vendor Defined)</td><td>Y31</td><td>DO</td><td></td><td>PCM_DO_1V8</td><td>MTK MT8370</td><td>PCM_DO</td><td>Defined by module manufacturer (PCM data output)</td></tr><tr><td>PCM_DI (Vendor Defined)</td><td>AA29</td><td>DI</td><td></td><td>PCM_DI_1V8</td><td>MTK MT8370</td><td>PCM_DI</td><td>Defined by module manufacturer (PCM data input)</td></tr><tr><td>VCC_IN_5V</td><td>AE4, AF4, AG4, AH3, AH4, AJ3, AJ4, AK4</td><td>P</td><td></td><td></td><td>VCC_IN_5V</td><td>Buck IC</td><td></td><td>Module power input voltage of 5V</td></tr><tr><td>GND</td><td>AE2, AE34, AF35, AG3, AH2, AH34, AJ35, AK3, AL2, AL34, AM13, AM16, AM19, AM22, AM35, AN3, AN6, AN9, AN11, AN15, AN18, AN21, AN33, AP2, AP5, AP8, AP13, AP16, AP19, AP22, AP25, AP28, AP31, AP34, AR14, AR17, AR20, AR26, AR29, AR32</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module signal and power return and GND reference</td></tr><tr><td>RESERVED</td><td>AL3</td><td>AIO</td><td></td><td></td><td>DPTX_L0_TXP</td><td>MTK MT8370</td><td>DP_LN0_TXP</td><td>DPTX lane 0 (Positive)</td></tr><tr><td>RESERVED</td><td>AL4</td><td>AIO</td><td></td><td></td><td>DPTX_L0_TXN</td><td>MTK MT8370</td><td>DP_LN0_TXN</td><td>DPTX lane 0 (Negative)</td></tr><tr><td>RESERVED</td><td>AM3</td><td>AIO</td><td></td><td></td><td>DPTX_L1_TXP</td><td>MTK MT8370</td><td>DP_LN1_TXP</td><td>DPTX lane 1 (Positive)</td></tr><tr><td>RESERVED</td><td>AM4</td><td>AIO</td><td></td><td></td><td>DPTX_L1_TXN</td><td>MTK MT8370</td><td>DP_LN1_TXN</td><td>DPTX lane 1 (Negative)</td></tr><tr><td>RESERVED</td><td>AM5</td><td>AIO</td><td></td><td></td><td>DPTX_L2_TXP</td><td>MTK MT8370</td><td>DP_LN2_TXP</td><td>DPTX lane 2 (Positive)</td></tr><tr><td>RESERVED</td><td>AM6</td><td>AIO</td><td></td><td></td><td>DPTX_L2_TXN</td><td>MTK MT8370</td><td>DP_LN2_TXN</td><td>DPTX lane 2 (Negative)</td></tr><tr><td>RESERVED</td><td>AM7</td><td>AIO</td><td></td><td></td><td>DPTX_L3_TXP</td><td>MTK MT8370</td><td>DP_LN3_TXP</td><td>DPTX lane 3 (Positive)</td></tr><tr><td>RESERVED</td><td>AM8</td><td>AIO</td><td></td><td></td><td>DPTX_L3_TXN</td><td>MTK MT8370</td><td>DP_LN3_TXN</td><td>DPTX lane 3 (Negative)</td></tr><tr><td>RESERVED</td><td>AM9</td><td>AIO</td><td></td><td>PD 100k</td><td>DPTX_AUX_P</td><td>MTK MT8370</td><td>DPAUXP</td><td>DPTX auxiliary channel (Positive)</td></tr><tr><td>RESERVED</td><td>AM10</td><td>AIO</td><td></td><td>PD 100k</td><td>DPTX_AUX_N</td><td>MTK MT8370</td><td>DPAUXN</td><td>DPTX auxiliary channel (Negative)</td></tr><tr><td>RESERVED</td><td>AM23</td><td>DI</td><td></td><td>PD 1M</td><td>DPTX_HPD</td><td>MTK MT8370</td><td>DPTX_HPD</td><td>DPTX hot plug detect</td></tr><tr><td>SCL4 (Vendor Defined)</td><td>AK32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SCL4</td><td>MTK MT8370</td><td>SCL4</td><td>I2C4 Clock Signal</td></tr><tr><td>SDA4 (Vendor Defined)</td><td>AK33</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SDA4</td><td>MTK MT8370</td><td>SDA4</td><td>I2C4 Data Signal</td></tr><tr><td>SCL6 (Vendor Defined)</td><td>AL32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SCL6</td><td>MTK MT8370</td><td>SCL6</td><td>I2C6 Clock Signal</td></tr><tr><td>SDA6 (Vendor Defined)</td><td>AL33</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SDA6</td><td>MTK MT8370</td><td>SDA6</td><td>I2C6 Data Signal</td></tr><tr><td>Vendor Defined</td><td>AM32</td><td>AO</td><td></td><td></td><td>AU_LOLN</td><td>MTK MT6365</td><td>AU_LOLN</td><td>Defined by the module manufacturer (Audio Lineout)</td></tr><tr><td>Vendor Defined</td><td>AM33</td><td>AO</td><td></td><td></td><td>AU_LOLP</td><td>MTK MT6365</td><td>AU_LOLP</td><td>Defined by the module manufacturer (Audio Lineout)</td></tr></table>

# 4.4 Signal Description by Function

4.4.1 DSIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>DSI_DATA0_N</td><td>AB11</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D0N</td><td>MTK MT8370</td><td>DSI0_D0N_T1A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA0_P</td><td>AB10</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D0P</td><td>MTK MT8370</td><td>DSI0_D0P_T0C</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA1_N</td><td>AC9</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D1N</td><td>MTK MT8370</td><td>DSI0_D1N_T2B</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA1_P</td><td>AC8</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D1P</td><td>MTK MT8370</td><td>DSI0_D1P_T2A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA2_N</td><td>AC6</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D2N</td><td>MTK MT8370</td><td>DSI0_D2N_T0B</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA2_P</td><td>AC5</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D2P</td><td>MTK MT8370</td><td>DSI0_D2P_T0A</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA3_N</td><td>AB5</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D3N</td><td>MTK MT8370</td><td>DSI0_D3N</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_DATA3_P</td><td>AB4</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_D3P</td><td>MTK MT8370</td><td>DSI0_D3P_T2C</td><td>DSI differential output (point to point)</td></tr><tr><td>DSI_CLOCK_N</td><td>AB8</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_CKN</td><td>MTK MT8370</td><td>DSI0_CKN_T1C</td><td>DSI differential clock output (point to point)</td></tr><tr><td>DSI_CLOCK_P</td><td>AB7</td><td>O LVDS D-PHY</td><td></td><td></td><td>DSI0_CKP</td><td>MTK MT8370</td><td>DSI0_CKP_T1B</td><td>DSI differential clock output (point to point)</td></tr><tr><td>DSI_TE</td><td>AA3</td><td>I CMOS</td><td>VCC_OUT_IO</td><td></td><td>DSI0_TE</td><td>MTK MT8370</td><td>DSI0_DSI_TE</td><td>DSI panel tearing effect signal</td></tr><tr><td>DSI0_RST (Vendor Defined)</td><td>D6</td><td>O</td><td>1.8V</td><td></td><td>DSI0_RST</td><td>MTK MT8370</td><td>DSI0_LCM_RST</td><td>Defined by module manufacturer</td></tr></table>

4.4.2 eDP A

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>eDP_A_LANE0_P</td><td>A30</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH0_P</td><td>MTK MT8370</td><td>HDMITX21_CH0_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE0_N</td><td>A31</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH0_M</td><td>MTK MT8370</td><td>HDMITX21_CH0_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE1_P</td><td>B31</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH1_P</td><td>MTK MT8370</td><td>HDMITX21_CH1_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE1_N</td><td>B32</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH1_M</td><td>MTK MT8370</td><td>HDMITX21_CH1_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE2_P</td><td>A33</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH2_P</td><td>MTK MT8370</td><td>HDMITX21_CH2_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE2_N</td><td>A34</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CH2_M</td><td>MTK MT8370</td><td>HDMITX21_CH2_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE3_P</td><td>B34</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CLK_P</td><td>MTK MT8370</td><td>HDMITX21_CLK_P</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_LANE3_N</td><td>B35</td><td>O LVDS DP</td><td></td><td></td><td>HDMI_TX_CLK_M</td><td>MTK MT8370</td><td>HDMITX21_CLK_M</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_A_AUX_P</td><td>C33</td><td>I/O LVDS DP</td><td>1.8V (HDMI)</td><td>PD 100k PU 2k2 (HDMI)</td><td>HDMI_TX_SDA</td><td>MTK MT8370</td><td>HDMITX_SDA</td><td>Primary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_A_AUX_N</td><td>C34</td><td>I/O LVDS DP</td><td>1.8V (HDMI)</td><td>PD 100k PU 2k2 (HDMI)</td><td>HDMI_TX_SCL</td><td>MTK MT8370</td><td>HDMITX_SCL</td><td>Primary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_A_BL_HPD</td><td>D33</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>PD 1M</td><td>HDMI_TX_HPD</td><td>MTK MT8370</td><td>HDMITX_HTPLG</td><td>Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer.</td></tr><tr><td>eDP_A_BL_EN</td><td>D31</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>HDMI_TX_PWR_EN</td><td>MTK MT8370</td><td>HDMITX_PWR5V</td><td>Primary eDP panel backlight enabled, active high</td></tr><tr><td>eDP_A_BL_PWM</td><td>C31</td><td>O CMOS</td><td>VCC_OUT_IO</td><td>PU 4k7 (HDMI)</td><td>HDMI_TX_CEC</td><td>MTK MT8370</td><td>HDMITX_CEC</td><td>Primary eDP panel brightness control through pulse width modulation</td></tr></table>

4.4.3 eDP B

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>eDP_B_LANE0_P</td><td>D35</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L0_TXP</td><td>MTK MT8370</td><td>EDP_LN0_TXP</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE0_N</td><td>E35</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L0_TXN</td><td>MTK MT8370</td><td>EDP_LN0_TXN</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE1_P</td><td>E34</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L1_TXP</td><td>MTK MT8370</td><td>EDP_LN1_TXP</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_LANE1_N</td><td>F34</td><td>O LVDS DP</td><td></td><td></td><td>EDP_L1_TXN</td><td>MTK MT8370</td><td>EDP_LN1_TXN</td><td>Primary 4-lane eDP differential pair data lines</td></tr><tr><td>eDP_B_AUX_P</td><td>G33</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>EDP_AUX_P</td><td>MTK MT8370</td><td>EDPAUXP</td><td>Secondary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_B_AUX_N</td><td>H33</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>EDP_AUX_N</td><td>MTK MT8370</td><td>EDPAUXN</td><td>Secondary bidirectional eDP channel used for link management and device control</td></tr><tr><td>eDP_B_BL_HPD</td><td>G32</td><td>I CMOS</td><td>VCC_OUT_IO</td><td>PD 1M</td><td>EDP_HPD</td><td>MTK MT8370</td><td>GPIO17</td><td>Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer.</td></tr><tr><td>eDP_B_BL_EN</td><td>E32</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>EDP_BL_EN</td><td>MTK MT8370</td><td>GPIO08</td><td>Secondary eDP panel backlight enabled, active high</td></tr><tr><td>eDP_B_BL_PWM</td><td>E33</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>EDP_BL_PWM</td><td>MTK MT8370</td><td>DISP_PWM1</td><td>Secondary eDP panel brightness control through pulse width modulation</td></tr></table>

4.4.4 DP/HDMI

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>RESERVED</td><td>AL3</td><td>AIO</td><td></td><td></td><td>DPTX_L0_TXP</td><td>MTK MT8370</td><td>DP_LN0_TXP</td><td>DPTX lane 0 (Positive)</td></tr><tr><td>RESERVED</td><td>AL4</td><td>AIO</td><td></td><td></td><td>DPTX_L0_TXN</td><td>MTK MT8370</td><td>DP_LN0_TXN</td><td>DPTX lane 0 (Negative)</td></tr><tr><td>RESERVED</td><td>AM3</td><td>AIO</td><td></td><td></td><td>DPTX_L1_TXP</td><td>MTK MT8370</td><td>DP_LN1_TXP</td><td>DPTX lane 1 (Positive)</td></tr><tr><td>RESERVED</td><td>AM4</td><td>AIO</td><td></td><td></td><td>DPTX_L1_TXN</td><td>MTK MT8370</td><td>DP_LN1_TXN</td><td>DPTX lane 1 (Negative)</td></tr><tr><td>RESERVED</td><td>AM5</td><td>AIO</td><td></td><td></td><td>DPTX_L2_TXP</td><td>MTK MT8370</td><td>DP_LN2_TXP</td><td>DPTX lane 2 (Positive)</td></tr><tr><td>RESERVED</td><td>AM6</td><td>AIO</td><td></td><td></td><td>DPTX_L2_TXN</td><td>MTK MT8370</td><td>DP_LN2_TXN</td><td>DPTX lane 2 (Negative)</td></tr><tr><td>RESERVED</td><td>AM7</td><td>AIO</td><td></td><td></td><td>DPTX_L3_TXP</td><td>MTK MT8370</td><td>DP_LN3_TXP</td><td>DPTX lane 3 (Positive)</td></tr><tr><td>RESERVED</td><td>AM8</td><td>AIO</td><td></td><td></td><td>DPTX_L3_TXN</td><td>MTK MT8370</td><td>DP_LN3_TXN</td><td>DPTX lane 3 (Negative)</td></tr><tr><td>RESERVED</td><td>AM9</td><td>AIO</td><td></td><td>PD 100k</td><td>DPTX_AUX_P</td><td>MTK MT8370</td><td>DPAUXP</td><td>DPTX auxiliary channel (Positive)</td></tr><tr><td>RESERVED</td><td>AM10</td><td>AIO</td><td></td><td>PD 100k</td><td>DPTX_AUX_N</td><td>MTK MT8370</td><td>DPAUXN</td><td>DPTX auxiliary channel (Negative)</td></tr><tr><td>RESERVED</td><td>AM23</td><td>DI</td><td></td><td>PD 1M</td><td>DPTX_HPD</td><td>MTK MT8370</td><td>DPTX_HPD</td><td>DPTX hot plug detect</td></tr></table>

# 4.4.5 MIPI Camera support

4.4.5.1 CSI (4 lanes)

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>CSI_DATA0_N</td><td>C1</td><td rowspan="6">I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td>CSI0_DAT0_N</td><td>MTK MT8370</td><td>CSI0A_L1N_T1A</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA0_P</td><td>B1</td><td></td><td></td><td>CSI0_DAT0_P</td><td>MTK MT8370</td><td>CSI0A_L1P_T0C</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA1_N</td><td>A2</td><td></td><td></td><td>CSI0_DAT1_N</td><td>MTK MT8370</td><td>CSI0B_L0N_T0B</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA1_P</td><td>A3</td><td></td><td></td><td>CSI0_DAT1_P</td><td>MTK MT8370</td><td>CSI0B_L0P_T0A</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA2_N</td><td>A5</td><td></td><td></td><td>CSI0_DAT2_N</td><td>MTK MT8370</td><td>CSI0A_L0N_T0A</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA2_P</td><td>A6</td><td></td><td></td><td>CSI0_DAT2_P</td><td>MTK MT8370</td><td>CSI0A_L0P_T0B</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA3_N</td><td>B6</td><td rowspan="2"></td><td></td><td></td><td>CSI0_DAT3_N</td><td>MTK MT8370</td><td>CSI0B_L1N_T1A</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_DATA3_P</td><td>B7</td><td></td><td></td><td>CSI0_DAT3_P</td><td>MTK MT8370</td><td>CSI0B_L1P_T0C</td><td>CSI differential input (point to point)</td></tr><tr><td>CSI_CLOCK_N</td><td>B3</td><td>I LVDS D-PHY</td><td></td><td></td><td>CSI0_CLK_N</td><td>MTK MT8370</td><td>CSI0A_L2N_T1C</td><td>CSI differential clock input (point to point)</td></tr><tr><td>CSI_CLOCK_P</td><td>B4</td><td>I LVDS D-PHY</td><td></td><td></td><td>CSI0_CLK_P</td><td>MTK MT8370</td><td>CSI0A_L2P_T1B</td><td>CSI differential clock input (point to point)</td></tr><tr><td>I2C_CAM_SDA / CSI_TX_N</td><td>C3</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA5_CAM</td><td>MTK MT8370</td><td>SDA5</td><td>I2C data for serial camera data support link or differential data lane</td></tr><tr><td>I2C_CAM_SCL / CSI_TX_P</td><td>C4</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL5_CAM</td><td>MTK MT8370</td><td>SCL5</td><td>I2C clock for serial camera data support link or differential data lane</td></tr></table>

# 4.4.6 Audio Interfaces

4.4.6.1 I2S0

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>I2S_A_DATA_IN</td><td>V21</td><td rowspan="7">I/O CMOS</td><td rowspan="7">VCC_OUT_IO</td><td></td><td>I2S_IN_D0</td><td>MTK MT8370</td><td>I2SIN_D0</td><td>I2S A Digital audio Input</td></tr><tr><td>I2S_A_DATA_OUT</td><td>W21</td><td></td><td>I2S_OUT_D0</td><td>MTK MT8370</td><td>I2SO2_D0</td><td>I2S A Digital audio Output</td></tr><tr><td>I2S_B_DATA_IN</td><td>V19</td><td></td><td></td><td></td><td></td><td>I2S B Digital audio Input</td></tr><tr><td>I2S_B_DATA_OUT</td><td>W19</td><td></td><td></td><td></td><td></td><td>I2S B Digital audio Output</td></tr><tr><td>I2S_MCLK</td><td>V18</td><td></td><td>I2S_IO_MCK</td><td>MTK MT8370</td><td>I2SO2_MCK</td><td>Master clock output to I2S codec(s)</td></tr><tr><td>I2S_LRCLK</td><td>W18</td><td></td><td>I2S_IO_WS</td><td>MTK MT8370</td><td>I2SO2_WS</td><td>I2S Left &amp; Right synchronization clock</td></tr><tr><td>I2S_BITCLK</td><td>W20</td><td></td><td>I2S_IO_BCK</td><td>MTK MT8370</td><td>I2SO2_BCK</td><td>I2S Digital audio clock</td></tr></table>

4.4.7 USB Ports

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>USB_A_D_N</td><td>AB13</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P0</td><td>MTK MT8370</td><td>USB_DM_P0</td><td>USB differential data pairs for port A</td></tr><tr><td>USB_A_D_P</td><td>AC14</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P0</td><td>MTK MT8370</td><td>USB_DP_P0</td><td>USB differential data pairs for port A</td></tr><tr><td>USB_A_ID</td><td>AB14</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>USB0_IDDIG</td><td>MTK MT8370</td><td>USB0_IDDIG</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td></tr><tr><td>USB_A_OC#</td><td>AC15</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>USB0_OC_N</td><td>MTK MT8370</td><td>KPCOL1</td><td>USB over-current for port A</td></tr><tr><td>USB_A_VBUS</td><td>AB16</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB0_VBUS_5V</td><td>MTK MT8370</td><td>USB0_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_A_EN</td><td>AC16</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>USB0_DRV_VBUS</td><td>MTK MT8370</td><td>USB0_DRV_VBUS</td><td>Power enable for USB VBUS voltage</td></tr><tr><td>USB_B_D_N</td><td>AB23</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P2</td><td>MTK MT8370</td><td>USB_DM_P2</td><td>USB differential data pairs for port B</td></tr><tr><td>USB_B_D_P</td><td>AC22</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P2</td><td>MTK MT8370</td><td>USB_DP_P2</td><td>USB differential data pairs for port B</td></tr><tr><td>USB_B_ID</td><td>AB22</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>USB2_IDDIG</td><td>MTK MT8370</td><td>USB2_IDDIG</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td></tr><tr><td>USB_B_OC#</td><td>AC21</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>USB2_OC_N</td><td>MTK MT8370</td><td>SPIM0_CLK</td><td>USB over-current for port B</td></tr><tr><td>USB_B_VBUS</td><td>AB20</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB2_VBUS_5V</td><td>MTK MT8370</td><td>USB2_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_B_EN</td><td>AC20</td><td>O CMOS</td><td>1.8V</td><td></td><td>USB2_DRV_VBUS</td><td>MTK MT8370</td><td>USB2_DRV_VBUS</td><td>Power enabled for USB VBUS voltage</td></tr><tr><td>USB_C_D_N</td><td>D11</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DM_P1</td><td>MTK MT8370</td><td>USB_DM_P1</td><td>USB differential data pairs for port C</td></tr><tr><td>USB_C_D_P</td><td>D10</td><td>I/O USB</td><td>USB</td><td></td><td>USB_DP_P1</td><td>MTK MT8370</td><td>USB_DP_P1</td><td>USB differential data pairs for port C</td></tr><tr><td>USB_C_ID</td><td>D9</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>USB1_IDDIG</td><td>MTK MT8370</td><td>USB1_IDDIG</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td></tr><tr><td>USB_C_OC#</td><td>C8</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10K</td><td>USB1_OC_N</td><td>MTK MT8370</td><td>KPROW0</td><td>USB over-current for port C</td></tr><tr><td>USB_C_VBUS</td><td>C9</td><td>I USB VBUS 5V</td><td>5V</td><td></td><td>USB1_VBUS_5V</td><td>MTK MT8370</td><td>USB1_VBUS_VALID</td><td>USB port 0 port power detection</td></tr><tr><td>USB_C_EN</td><td>C10</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>USB1_DRV_VBUS</td><td>MTK MT8370</td><td>USB1_DRV_VBUS</td><td>Power enabled for USB VBUS voltage</td></tr><tr><td>USB_C_SSTX_N</td><td>A9</td><td>O USB SS</td><td>USB SS</td><td></td><td>SSUSB_TXN_P1</td><td>MTK MT8370</td><td>SSUSB_TXN</td><td>Transmit signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSTX_P</td><td>A8</td><td>O USB SS</td><td>USB SS</td><td></td><td>SSUSB_TXP_P1</td><td>MTK MT8370</td><td>SSUSB_TXP</td><td>Transmit signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSRX_N</td><td>B11</td><td>I USB SS</td><td>USB SS</td><td></td><td>SSUSB_RXN_P1</td><td>MTK MT8370</td><td>SSUSB_RXN</td><td>Receive signal differential pairs for SuperSpeed on port C</td></tr><tr><td>USB_C_SSRX_P</td><td>B10</td><td>I USB SS</td><td>USB SS</td><td></td><td>SSUSB_RXP_P1</td><td>MTK MT8370</td><td>SSUSB_RXP</td><td>Receive signal differential pairs for SuperSpeed on port C</td></tr></table>

![The image displays a red icon on a white background. The icon is shaped like a document or file with a folded bottom-right corner. Inside the red outline, there are two horizontal lines centered horizontally.](.osm-mtk510-50m-76103-1010-11/193737d840be0ce5ca79bcede085615faebdfb37cbf09b93181c73c2803d467b.jpg)
Note: 1. USB A and B have OTG 2. USB C carries SS signals

4.4.8 PCIe

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>PCIe_A_HSI0_P</td><td>AB1</td><td>I LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_RXP</td><td>MTK MT8370</td><td>PCIE_LN0_RXP</td><td>Differential PCIe link A receive data pair</td></tr><tr><td>PCIe_A_HSI0_N</td><td>AB2</td><td>I LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_RXN</td><td>MTK MT8370</td><td>PCIE_LN0_RXN</td><td>Differential PCIe link A receive data pair</td></tr><tr><td>PCIe_A_HSO0_P</td><td>AC2</td><td>O LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_TXP</td><td>MTK MT8370</td><td>PCIE_LN0_TXP</td><td>Differential PCIe link A transmit data pair</td></tr><tr><td>PCIe_A_HSO0_N</td><td>AC3</td><td>O LVDS PCIE</td><td></td><td></td><td>PCIEG2_L0_TXN</td><td>MTK MT8370</td><td>PCIE_LN0_TXN</td><td>Differential PCIe link A transmit data pair</td></tr><tr><td>PCIe_CLKREQ#</td><td>W2</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>PCIEG2_CLKREQ_N</td><td>MTK MT8370</td><td>PCIE_CLKREQ</td><td>PCIe reference clock request</td></tr><tr><td>PCIe_A_PERST#</td><td>V21</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>PCIEG2_PERESET_N</td><td>MTK MT8370</td><td>PCIE_PERESET</td><td>PCIe Port A reset output</td></tr><tr><td>PCIe_REFCLK_P</td><td>W1</td><td>O LVDS PCIE</td><td></td><td>PD 49.9 (MTK request)</td><td>PCIEG2_CLK_P</td><td>MTK MT8370</td><td>PCIE_CKP</td><td>Differential PCIe reference clock output</td></tr><tr><td>PCIe_REFCLK_N</td><td>Y1</td><td>O LVDS PCIE</td><td></td><td>PD 49.9 (MTK request)</td><td>PCIEG2_CLK_N</td><td>MTK MT8370</td><td>PCIE_CKN</td><td>Differential PCIe reference clock output</td></tr><tr><td>PCIe_WAKE#</td><td>T2</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 10k</td><td>PCIEG2_WAKE_N</td><td>MTK MT8370</td><td>PCIE_WAKE</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td></tr><tr><td>PCIe_SMDAT</td><td>U1</td><td>I/O OD CMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA3_PCIE</td><td>MTK MT8370</td><td>SDA3</td><td>System management I2C bus DATA</td></tr><tr><td>PCIe_SMCLK</td><td>T1</td><td>O OD CMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL3_PCIE</td><td>MTK MT8370</td><td>SCL3</td><td>System management I2C bus CLK</td></tr><tr><td>PCIe_SM_ALERT#</td><td>R2</td><td>I OD CMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>PCIE_SM_ALERT_N</td><td>MTK MT8370</td><td>SPIMO_CS</td><td>SMBus Alert# (interrupt) signal</td></tr></table>

4.4.9 LAN Port

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>ETH_A_(R)(G)MII_COL</td><td>F15</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_COL_1V8</td><td>MTK MT8370</td><td>DPI_HSYNC</td><td>Collision detects (half speed only) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD0</td><td>H15</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXD0_1V8</td><td>MTK MT8370</td><td>DPI_D3</td><td>Transmit data bit 0 (transmitted first) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD1</td><td>G15</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXD1_1V8</td><td>MTK MT8370</td><td>DPI_D2</td><td>Transmit data bit 1 port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD2</td><td>H16</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXD2_1V8</td><td>MTK MT8370</td><td>DPI_D1</td><td>Transmit data bit 2 port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD3</td><td>G16</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXD3_1V8</td><td>MTK MT8370</td><td>DPI_D0</td><td>Transmit data bit 3 port A</td></tr><tr><td>ETH_A_(R)(G)MII_TX_EN(ER)</td><td>K16</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXEN_1V8</td><td>MTK MT8370</td><td>DPI_D11</td><td>Transmit enable (Error) port A</td></tr><tr><td>ETH_A_(R)(G)MII_TX_CLK</td><td>J15</td><td>I/O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_TXC_1V8</td><td>MTK MT8370</td><td>DPI_D8</td><td>Transmit clock port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD0</td><td>K15</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXD0_1V8</td><td>MTK MT8370</td><td>DPI_D7</td><td>Receive data bit 0 (received first) port A</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD1</td><td>L15</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXD1_1V8</td><td>MTK MT8370</td><td>DPI_D6</td><td>Receive data bit 1 port A</td></tr><tr><td>ETH_A_(R)(G)MII_RXD3</td><td>P15</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXD3_1V8</td><td>MTK MT8370</td><td>DPI_D4</td><td>Receive data bit 3 port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_ER</td><td>L16</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXER_1V8</td><td>MTK MT8370</td><td>DPI_D15</td><td>Receive error port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_DV(ER)</td><td>M15</td><td>I CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXDV_1V8</td><td>MTK MT8370</td><td>DPI_D10</td><td>Receive data valid port A</td></tr><tr><td>ETH_A_(R)(G)MII_RX_CLK</td><td>R15</td><td>I/O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_RXC_1V8</td><td>MTK MT8370</td><td>DPI_D9</td><td>Receive clock port A</td></tr><tr><td>ETH_MDIO</td><td>T15</td><td>I/O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_MDIO_1V8</td><td>MTK MT8370</td><td>DPI_D13</td><td>Management bus data signal for Ethernet</td></tr><tr><td>ETH_MDC</td><td>T16</td><td>O CMOS</td><td>1.8V /2.5V / 3.3V</td><td></td><td>GBE_MDC_1V8</td><td>MTK MT8370</td><td>DPI_D12</td><td>Management bus clock signal for Ethernet</td></tr><tr><td>ETH_IOPWR</td><td>M17</td><td>PO</td><td>1.8V /2.5V / 3.3V</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>ETH voltage. It is used to provide the I/O Voltage Level for all Ethernet interfaces.</td></tr></table>

4.4.10 SDIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>SDIO_A_CMD</td><td>E20</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_CMD</td><td>MTK MT8370</td><td>MSDC1_CMD</td><td>SDIO A Command/Response: This signal is used for card initialization and for command transfers. During initialization, this signal is open-drain. During command transfers, this signal is in push-pull mode.</td></tr><tr><td>SDIO_A_CLK</td><td>F21</td><td>O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_CLK</td><td>MTK MT8370</td><td>MSDC1_CLK</td><td>SDIO A Clock: With each cycle of this signal, a one-bit transfer occurs on the command and each of the data line.</td></tr><tr><td>SDIO_A_D0</td><td>G20</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_DAT0</td><td>MTK MT8370</td><td>MSDC1_DAT0</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D1</td><td>G21</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_DAT1</td><td>MTK MT8370</td><td>MSDC1_DAT1</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D2</td><td>H20</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_DAT2</td><td>MTK MT8370</td><td>MSDC1_DAT2</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_D3</td><td>H21</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC1_DAT3</td><td>MTK MT8370</td><td>MSDC1_DAT3</td><td>SDIO A Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_A_CD#</td><td>J21</td><td>I OD CMOS</td><td>1.8V / 3.3V</td><td>PU 10K</td><td>MSDC1_INSI</td><td>MTK MT8370</td><td>GPIO06</td><td>SDIO A Card Detect: This signal indicates when a SDIO/MMC card is present.</td></tr><tr><td>SDIO_A_WP</td><td>D20</td><td>I OD CMOS</td><td>1.8V / 3.3V</td><td>PU 10K</td><td>MSDC1_WP</td><td>MTK MT8370</td><td>GPIO05</td><td>SDIO A Write Protect: This signal denotes the state of the write-protect tab on SD cards.</td></tr><tr><td>SDIO_A_PWR_EN</td><td>D21</td><td>O CMOS</td><td>1.8V / 3.3V</td><td></td><td>EXT_VMSDC1_EN</td><td>MTK MT8370</td><td>GPIO04</td><td>SDIO A Power Enable: This signal is used to enable the power being supplied to a SD/MMC card device.</td></tr><tr><td>SDIO_A_IOPWR</td><td>C20</td><td>PO</td><td>1.8V / 3.3V</td><td></td><td>VSIM1_PMU</td><td>MTK MT6365</td><td>VSIM1</td><td>SDIO A Voltage: It is used to provide the IO Voltage Level</td></tr><tr><td>SDIO_B_CLK</td><td>K20</td><td>O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_CLK</td><td>MTK MT8370</td><td>MSDC2_CLK</td><td>SDIO B Clock: With each cycle of this signal, a one-bit transfer occurs on the command and each of the data line.</td></tr><tr><td>SDIO_B_CMD</td><td>K21</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_CMD</td><td>MTK MT8370</td><td>MSDC2_CMD</td><td>SDIO B Command/Response: This signal is used for card initialization and for command transfers. During initialization, this signal is open-drain. During command transfers, this signal is in push-pull mode.</td></tr><tr><td>SDIO_B_D0</td><td>L20</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_DAT0</td><td>MTK MT8370</td><td>MSDC2_DAT0</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D1</td><td>L21</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_DAT1</td><td>MTK MT8370</td><td>MSDC2_DAT1</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D2</td><td>M21</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_DAT2</td><td>MTK MT8370</td><td>MSDC2_DAT2</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_D3</td><td>N20</td><td>I/O CMOS</td><td>1.8V / 3.3V</td><td></td><td>MSDC2_DAT3</td><td>MTK MT8370</td><td>MSDC2_DAT3</td><td>SDIO B Data lines: These signals operate in push-pull mode.</td></tr><tr><td>SDIO_B_IOPWR</td><td>T20</td><td>PO</td><td>1.8V / 3.3V</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>SDIO B Voltage: It is used to provide the I/O Voltage Level</td></tr></table>

The carrier SDIO card may be selected as the boot device.

# 4.4.11 SPI Interfaces

4.4.11.1 SPI A/B/C

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>SPI_A_SDI_(IO0)</td><td>U15</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_IO0</td><td>MTK MT8370</td><td>DMIC1_DAT_R</td><td>SPI A Serial Data Input</td></tr><tr><td>SPI_A_SDO_(IO1)</td><td>V15</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_IO1</td><td>MTK MT8370</td><td>DMIC2_CLK</td><td>SPI A Serial Data Output</td></tr><tr><td>SPI_A_/WP_(IO2)</td><td>W16</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_IO2</td><td>MTK MT8370</td><td>DMIC2_DAT</td><td>SPI A Write Protect</td></tr><tr><td>SPI_A_/HOLD_(IO3)</td><td>W15</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_IO3</td><td>MTK MT8370</td><td>DMIC2_DAT_R</td><td>SPI A Suspend Serial Input</td></tr><tr><td>SPI_A_CS0#</td><td>Y15</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_CS_N</td><td>MTK MT8370</td><td>DMIC1_DAT</td><td>SPI A Master Chip Select 0</td></tr><tr><td>SPI_A_SCK</td><td>U16</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPINOR_CLK</td><td>MTK MT8370</td><td>DMIC1_CLK</td><td>SPI A Serial Data Clock</td></tr><tr><td>SPI_B_SDI</td><td>Y22</td><td>I CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPIM1_MOSI</td><td>MTK MT8370</td><td>SPIM1_MOSI</td><td>SPI B Serial Data Input</td></tr><tr><td>SPI_B_SDO</td><td>Y23</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPIM1_MISO</td><td>MTK MT8370</td><td>SPIM1_MISO</td><td>SPI B Serial Data Output</td></tr><tr><td>SPI_B_CS0#</td><td>AA23</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPIM1_CS_N</td><td>MTK MT8370</td><td>SPIM1_CS</td><td>SPI B Master Chip Select 0</td></tr><tr><td>SPI_B_SCK</td><td>Y21</td><td>O CMOS</td><td>VCC_OUT_IO</td><td></td><td>SPIM1_CLK</td><td>MTK MT8370</td><td>SPIM1_CLK</td><td>SPI B Serial Data Clock</td></tr><tr><td>SPI_C_SDI</td><td>C29</td><td>I CMOS</td><td>1.8V</td><td></td><td>SPIM2_MOSI</td><td>MTK MT8370</td><td>SPIM2_MOSI</td><td>SPI C Serial Data Input</td></tr><tr><td>SPI_C_SDO</td><td>D30</td><td>O CMOS</td><td>1.8V</td><td></td><td>SPIM2_MISO</td><td>MTK MT8370</td><td>SPIM2_MISO</td><td>SPI C Serial Data Output</td></tr><tr><td>SPI_C_CS0#</td><td>C30</td><td>O CMOS</td><td>1.8V</td><td></td><td>SPIM2_CS_N</td><td>MTK MT8370</td><td>SPIM2_CS</td><td>SPI C Master Chip Select 0</td></tr><tr><td>SPI_C_SCK</td><td>D29</td><td>O CMOS</td><td>1.8V</td><td></td><td>SPIM2_CLK</td><td>MTK MT8370</td><td>SPIM2_CLK</td><td>SPI C Serial Data Clock</td></tr></table>

4.4.11.2 I2C

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>I2C_A_SCL</td><td>AA15</td><td rowspan="4">I/O OD CMOS</td><td rowspan="4">VCC_OUT_IO, Size-0 only 1.8V, &gt;Size-0</td><td rowspan="4">PU 2k2</td><td>SCL0_A</td><td>MTK MT8370</td><td>SCL0</td><td>I2C Port A Clock Signal</td></tr><tr><td>I2C_A_SDA</td><td>AA16</td><td>SDA0_A</td><td>MTK MT8370</td><td>SDA0</td><td>I2C Port A Data Signal</td></tr><tr><td>I2C_B_SCL</td><td>AA20</td><td>SCL2_B</td><td>MTK MT8370</td><td>SCL2</td><td>I2C Port B Clock Signal</td></tr><tr><td>I2C_B_SDA</td><td>AA21</td><td>SDA2_B</td><td>MTK MT8370</td><td>SDA2</td><td>I2C Port B Data Signal</td></tr><tr><td>I2C_CAM_SDA / CSI_TX_N</td><td>C3</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA5_CAM</td><td>MTK MT8370</td><td>SDA5</td><td>I2C data for serial camera data support link or differential data lane</td></tr><tr><td>I2C_CAM_SCL / CSI_TX_P</td><td>C4</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL5_CAM</td><td>MTK MT8370</td><td>SCL5</td><td>I2C clock for serial camera data support link or differential data lane</td></tr><tr><td>SCL4 (Vendor Defined)</td><td>AK32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SCL4</td><td>MTK MT8370</td><td>SCL4</td><td>I2C4 Clock Signal</td></tr><tr><td>SDA4 (Vendor Defined)</td><td>AK32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SDA4</td><td>MTK MT8370</td><td>SDA4</td><td>I2C4 Data Signal</td></tr><tr><td>SCL6 (Vendor Defined)</td><td>AK32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SCL6</td><td>MTK MT8370</td><td>SCL6</td><td>I2C6 Clock Signal</td></tr><tr><td>SDA6 (Vendor Defined)</td><td>AK32</td><td>I/O OD CMOS</td><td></td><td>PU 2k2</td><td>SDA6</td><td>MTK MT8370</td><td>SDA6</td><td>I2C6 Data Signal</td></tr><tr><td>PCIe_SMDAT</td><td>U1</td><td>I/O OD CMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SDA3_PCIE</td><td>MTK MT8370</td><td>SDA3</td><td>System management I2C bus DATA</td></tr><tr><td>PCIe_SMCLK</td><td>T1</td><td>O OD CMOS</td><td>VCC_OUT_IO</td><td>PU 2k2</td><td>SCL3_PCIE</td><td>MTK MT8370</td><td>SCL3</td><td>System management I2C bus CLK</td></tr></table>

![The image displays a red icon on a white background. It features a vertical rectangular outline resembling a piece of paper or a document, with a rounded bottom-right corner. Inside the outline, there are two horizontal red bars centered in the middle.](.osm-mtk510-50m-76103-1010-11/c95905052ca938eb929045b8fffe453a03d62ea57ba4db7e533f64fad68ce8ff.jpg)

Note: MIPI-CSI 2.0 mode uses I2C\_CAM\_SDA /MIPI-CSI 3.0 mode uses CSI\_TX\_N

MIPI-CSI 2.0 mode uses I2C\_CAM\_SCL /MIPI-CSI 3.0 mode uses CSI\_TX\_P

4.4.12 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>GPIO_A_0</td><td>D17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_02</td><td>MTK MT8370</td><td>SPIM0_MOSI</td><td>General purpose I/O Contact A0</td></tr><tr><td>GPIO_A_1</td><td>E17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_04</td><td>MTK MT8370</td><td>SPIM0_MIO2</td><td>General purpose I/O Contact A1</td></tr><tr><td>GPIO_A_2</td><td>F17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_05</td><td>MTK MT8370</td><td>SPIM0_MIO3</td><td>General purpose I/O Contact A2</td></tr><tr><td>GPIO_A_3</td><td>G17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_03</td><td>MTK MT8370</td><td>SPIM0_MIO1</td><td>General purpose I/O Contact A3</td></tr><tr><td>GPIO_A_4</td><td>H17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GBE_TXER_1V8</td><td>MTK MT8370</td><td>DPI_D14</td><td>General purpose I/O Contact A4</td></tr><tr><td>GPIO_A_5</td><td>J17</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GBE_INTR_1V8</td><td>MTK MT8370</td><td>DPI_D15</td><td>General purpose I/O Contact A5</td></tr><tr><td>GPIO_B_0</td><td>D19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_12</td><td>MTK MT8370</td><td>GPIO12</td><td>General purpose I/O Contact B0</td></tr><tr><td>GPIO_B_1</td><td>E19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_13</td><td>MTK MT8370</td><td>GPIO13</td><td>General purpose I/O Contact B1</td></tr><tr><td>GPIO_B_2</td><td>F19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_14</td><td>MTK MT8370</td><td>GPIO14</td><td>General purpose I/O Contact B2</td></tr><tr><td>GPIO_B_3</td><td>G19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_15</td><td>MTK MT8370</td><td>GPIO15</td><td>General purpose I/O Contact B3</td></tr><tr><td>GPIO_B_4</td><td>H19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_17</td><td>MTK MT8370</td><td>I2SIN_WS</td><td>General purpose I/O Contact B4</td></tr><tr><td>GPIO_B_5</td><td>J19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_08</td><td>MTK MT8370</td><td>CMMRST1</td><td>General purpose I/O Contact B5</td></tr><tr><td>GPIO_B_6</td><td>K19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_06</td><td>MTK MT8370</td><td>CMMPDN1</td><td>General purpose I/O Contact B6</td></tr><tr><td>GPIO_B_7</td><td>L19</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_01</td><td>MTK MT8370</td><td>GPIO01</td><td>General purpose I/O Contact B7</td></tr><tr><td>GPIO_C_0</td><td>D3</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_00</td><td>MTK MT8370</td><td>GPIO00</td><td>General purpose I/O Contact C0</td></tr><tr><td>GPIO_C_1</td><td>D4</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_11</td><td>MTK MT8370</td><td>GPIO11</td><td>General purpose I/O Contact C1</td></tr><tr><td>GPIO_C_2</td><td>E3</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_09</td><td>MTK MT8370</td><td>DSI1_LCM_RST</td><td>General purpose I/O Contact C2</td></tr><tr><td>GPIO_C_3</td><td>E4</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>GPIO_07</td><td>MTK MT8370</td><td>GPIO07</td><td>General purpose I/O Contact C3</td></tr><tr><td>GPIO_C_4</td><td>F3</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>DISP_VDD_EN</td><td>MTK MT8370</td><td>I2SIN_D1</td><td>Dual function: DISP_VDD_EN</td></tr><tr><td>GPIO_C_5</td><td>F4</td><td>I/O CMOS</td><td>VCC_OUT_IO</td><td></td><td>DISP_BL_EN</td><td>MTK MT8370</td><td>KPROW1</td><td>Dual function: DISP_BL_EN</td></tr><tr><td>GPIO_D_0</td><td>U32</td><td>I/O CMOS</td><td>1.8V</td><td></td><td>GPIO_16</td><td>MTK MT8370</td><td>DSI1_DSI_TE</td><td>General purpose I/O Contact D0</td></tr></table>

4.4.13 Power

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>VCC_OUT_IO</td><td>U18</td><td>P</td><td>1.8V / 3.3V</td><td></td><td>VIO18_PMU</td><td>MTK MT6365</td><td>VIO18</td><td>Can provide IO voltage level for several interfaces to connect</td></tr><tr><td>VCC_IN_5V</td><td>Y25, Y26, Y27, Y28</td><td>P</td><td></td><td></td><td>VCC_IN_5V</td><td>Buck IC</td><td></td><td>Module power input voltage of 5V</td></tr><tr><td>VCC_IN_5V</td><td>AE4, AF4, AG4, AH3, AH4, AJ3, AJ4, AK4</td><td>P</td><td></td><td></td><td>VCC_IN_5V</td><td>Buck IC</td><td></td><td>Module power input voltage of 5V</td></tr><tr><td>Contact Name</td><td>Contact Acronym</td><td>I/O Type</td><td>I/O Level</td><td>PU/PD</td><td>Net Name of Module</td><td>Controller</td><td>Controller Pin Name</td><td>Description</td></tr><tr><td>GND</td><td>D18, E15, E21, F16, F20, J16, J20, L18, M16, M20, P18, R16, R20, V16, V20, Y18, AA14, AA17, AA19, AA22, AB15, AB21</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module Signal and power return and GND reference</td></tr><tr><td>GND</td><td>A4, A7, A10, B2, B5, B8, B9, C11, D1, D5, D8, E2, H2, H4, L2, L4, P2, P4, R1, U2, U4, V1, W3, Y2, AA1, AA4, AA7, AA8, AA10, AA11, AB3, AB6, AB9, AC4, AC7, AC10</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module Signal and power return and GND reference</td></tr><tr><td>GND</td><td>A26, A29, A32, B27, B28, B30, B33, C25, C32, C35, D28, D34, F33, F35, G34, H32, J33, J35, K34, M35, N34, T34, W34, AA25, AA26, AA27, AA28, AA32, AB28, AB31, AB34, AC27, AC30, AC33</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module Signal and power return and GND reference</td></tr><tr><td>GND</td><td>AE2, AE34, AF35, AG3, AH2, AH34, AJ35, AK3, AL2, AL34, AM13, AM16, AM19, AM22, AM35, AN3, AN6, AN9, AN11, AN15, AN18, AN21, AN33, AP2, AP5, AP8, AP13, AP16, AP19, AP22, AP25, AP28, AP31, AP34, AR14, AR17, AR20, AR26, AR29, AR32</td><td>P</td><td></td><td></td><td>GND</td><td></td><td></td><td>Module Signal and power return and GND reference</td></tr></table>

# 5. Software Support

# 5.1 Yocto

Yocto is the main OS supplied for this product, this is based upon the MediaTek Genio releases

MediaTek Releases > https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/

ADLINK Releases > https://github.com/ADLINK/meta-adlink-mtk

# 5.2 Canonical Ubuntu

Ubuntu will be supported in a later stage on this platform, based upon the official Canonical/MediaTek releases https://ubuntu.com/download/mediatek-genio

# 6. Mechanical

# 6.1 Module Dimensions

![28.00\n10.25\n6.75\n10.25\nR1\nR1\n6.75\n6.75\n45.00\n30.50\n16.50\n16.50\n7.75\n6.75\n31.50\nR1\n45.00](.osm-mtk510-50m-76103-1010-11/dd7c80aacd644c850d8481965370482c646c16a82fcad68f077c01126f3ae286.jpg)

![27.50\n11.25\n6.25\n11.25\nR1\nR1\n6.25\n30.00\n17.50\n45.00\n8.75\n6.25\n32.50\n45.00\n17.50](.osm-mtk510-50m-76103-1010-11/e06c20cab87357b2db07c449817699f3c81de30dd1889a990b1a7ce69b40340f.jpg)

Figure 16: Placement Area (left) and Cut-Out Area (right) - Size L (view from bottom)
Figure 4 – Mechanical dimensions

# 7. Thermal Solutions

# 7.1 Heatspreader: HTS

To define on the carrier, follow the carrier mounting points for off-the-shelf designs.

# 7.2 Heatsink: THS

To define on the carrier, follow the carrier mounting points for off-the-shelf designs.
[🔗 Link to the original document](.osm-mtk510-50m-76103-1010-11/osm-mtk510-50m-76103-1010-11.pdf)