| Counter Name | Width | Description | Note |
| UI_counter | 32-bit | Update Interval.Defines the update interval between each data output. | Update Interval = UI_counter / Timebase*. |
| UC_counter | 32-bit | Update Counts.Defines the number of data in a waveform. | When value in UC_counter is smaller than the size of waveform patterns, the waveform is generated piece-wisely. |
| IC_counter | 32-bit | Iteration Counts.Defines how many times the waveform is generated. | |
| DLY1_counter | 32-bit | Defines the delay time for waveform generation after the trigger signal. | Delay Time = (DLY1_counter / Clock Timebase) |
| DLY2_counter | 32-bit | Defines the delay time to separate consecutive waveform generation. This is applicable only in Iterative Waveform Generation mode. | Delay Time = (DLY2_counter / Clock Timebase) |
| Trig_counter | 32-bit | Defines the acceptable start trigger count when re-trigger function is enabled | |
Table 4-2: Summary of Counters for Waveform Generation
Timebase $^{*}$ = 80M
# NOTE
The maximum D/A update rate is 1 MHz, and the minimum setting of UI\_counter is 80.
Figure 4-5: Typical D/A Timing of Waveform Generation
# Trigger Modes
# Post-Trigger Generation
Use post-trigger generation when you want to generate a waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC\_counter\* IC\_counter and is illustrated in Figure 4-6.
Figure 4-6: Post-Trigger Generation
# Delay-Trigger Generation
Use delay-trigger when you want to delay the waveform generation after the trigger signal. The delay time is determined by DLY1\_counter, as illustrated in Figure 4-7.
The counter counts down on the rising edges of DLY1\_counter clock source after the start trigger signal. When the count reaches zero, card will start to generate the waveform. The DLY1\_counter clock source can be selected via software application using the internal 80 MHz timebase.
Figure 4-7: Delay-Trigger Generation
# Post-Trigger or Delay-Trigger with Retrigger
Use post-trigger or delay-trigger with retrigger when you want to generate multiple waveforms with respect to multiple incoming trigger signals. You can set Trig\_counter to specify the number of acceptable trigger signals. Refer to Figure 4-8.
In this example, two waveforms are generated after the first trigger signal. The board then waits for another trigger signal.
When the next trigger signal is asserted, the board generates two more waveforms.
After two trigger signals, as specified in Trig\_Counter, no more triggers signals will be accepted unless trigger reset command is executed. For more information on Iterative Waveform Generation that is used in this example, refer to the next section.
Figure 4-8: Post-Trigger with Retrigger Generation
# NOTE
Start Trigger signals asserted during the waveform generation process will be ignored.
# Iterative Waveform Generation
You can set the IC\_counter to generate iterative waveforms no matter which trigger mode is used. The IC\_counter stores the iteration number. Examples are shown in Figure 4-9 and Figure 4-10. When IC\_counter is enabled and set to 0, the waveform generation will not stop until IC\_counter is disabled.
An onboard data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host computer's memory, the data in FIFO will be reused when a single waveform generation is completed and will not occupy the PCI bandwidth afterwards.
However, if the size of a single waveform is larger than that of the FIFO, it needs to be intermittently loaded from the host computer's memory via DMA, and will occupy the PCI bandwidth.
Figure 4-9: Finite Iterative Waveform Generation with Post-trigger
In conjunction with different trigger modes and counter setups, you can manipulate a single waveform to generate different and more complex waveforms.
Figure 4-10: Infinite Iterative Waveform Generation with Post-trigger
# DLY2 Counter in Iterative Waveform Generation
To expand the flexibility of iterative waveform generation, DLY2\_counter was implemented to separate consecutive waveform generations.
The DLY2\_counter starts counting down right after a single waveform generation is completed. When it reaches zero, the next iteration of waveform generation will start as shown in Figure 4-5. If you generate the waveform piece-wisely, the next piece of waveform will be generated.
# 4.3 General Purpose Digital D/O
The PCI-6202 offers comprehensive support to various digital I/O provided by an FPGA chip. These digital I/O include general purpose digital input and output, PWM, Timer/Counter, and Application Function Interface (AFI).
# General Purpose DIO
PCI-6202 provides 8 channel DI and 8 channel DO. All I/O are static TTL-compliant. You can read/write these I/O line by software polling. In this way, the sample and update rate is fully controlled by software timing.
| Pin | Function | Note |
| AFI0 | External convert signal out | Configured as a DA convert source. |
| External digital trigger in | Used for one of all DA output trigger source. |
| External digital trigger out | Export a digital trigger based on a software trigger. |
| Encoder position trigger out | This function is combined with encoder0 input. When encoder counts up for a specific value that you have set, AFI0 will export a digital high signal. |
| AFI1 | External convert signal out | AFI1 can be configured as a DA convert source. |
| Digital trigger in | Used for one of all DA output trigger source. |
| Digital trigger out | Export a digital trigger based on software trigger. |
| Encoder position trigger out | This function is combined with encoder1 input. When encoder counts up for a specific value that you have set, AFI1 will export a digital high signal. |
| AFI2 | Encoder position trigger out | This function is combined with encoder2 input. When encoder counts up for a specific value that you have set, AFI2 will export a digital high signal. |
Table 4-4: AFI Functions
# PWM Output
The PCI-6202 provides four dedicated PWM outputs, each consisting of two parameters: high level and low level width. These two parameters have a 24-bit count width that can be used. The PWM base clock is 80MHz.
Figure 4-11 shows the high and low level definition of the PWM output. HV is high level width count value while LV is low level count value.
Figure 4-11: PWM Output Parameters
The period width time value is shown in this formula:
$$
P e r i o d \_ t i m e \_ v a l u e = \frac {H V + L V}{8 0 M H z}
$$
HV and LV can also set the PWM duty cycle:
$$
H i g h \_ l e v e l \_ d u t y c y c l e = \frac {H V}{H V + L V}
$$
$$
L o w \_ l e v e l \_ d u t y c y c l e = \frac {L V}{H V + L V}
$$
# General Purpose Timer/Counter
PCI-6202 comes with three general purpose timer/counter sets featuring:
▶ Count up/down controlled by hardware or software
▶ Programmable counter clock source (internal clock up to 80MHz, external clock up to 10MHz)
▶ Programmable gate selection (hardware or software control)
▶ Programmable input and output signal polarities (high active or low active)
▶ Initial Count can be loaded from a software application
▶ Current count value can be read-back by software without affecting circuit operation.