NuDAQÒ

PCI-7348/7396

48/96-CH Digital I/O Cards

DIN-96DI, DIN-96DO

User’s Guide

©Copyright 2002 ADLINK Technology Inc.

All Rights Reserved.

Manual Rev. 1.22 June 7, 2002

Pato No : 50-11107-200

The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

NuDAQ, DAQBench are registered trademarks of ADLINK Technology Inc.

Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting service from ADLINK

Customer Satisfaction is always the most important thing for ADLINK Tech Inc. If you need any help or service, please contact us and get it.

<table><tr><td colspan="4">ADLINK Technology Inc.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">service@adlinktech.com</td></tr><tr><td rowspan="4">Technical Support</td><td>NuDAQ</td><td colspan="2">nudaq@adlinktech.com</td></tr><tr><td>automation</td><td colspan="2">automation@adlinktech.com</td></tr><tr><td>NuIPC</td><td colspan="2">nuipc@adlinktech.com</td></tr><tr><td>NuPRO/EBC</td><td colspan="2">nupro@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan,</td></tr></table>

Please inform or FAX us of your detailed information for a prompt, satisfactory and constant service.

<table><tr><td colspan="4">Detailed Company Information</td></tr><tr><td>Company/Organization</td><td colspan="3"></td></tr><tr><td>Contact Person</td><td colspan="3"></td></tr><tr><td>E-mail Address</td><td colspan="3"></td></tr><tr><td>Address</td><td colspan="3"></td></tr><tr><td>Country</td><td colspan="3"></td></tr><tr><td>TEL</td><td></td><td>FAX</td><td></td></tr><tr><td>Web Site</td><td colspan="3"></td></tr><tr><td colspan="4">Questions</td></tr><tr><td>Product Model</td><td colspan="3"></td></tr><tr><td>Environment to Use</td><td colspan="3">OS: ____Computer ____M/B: CPU:Chipset: BIOS:Video Card:Network Interface Card:Other:</td></tr><tr><td>Challenge Description</td><td colspan="3"></td></tr><tr><td>Suggestions to ADLINK</td><td colspan="3"></td></tr></table>

# Table of Contents

# Chapter 1 Introduction.........

1.1 Features....

1.1.1 Digital I/O Ports ...

1.1.2 Timer / Counter and Interrupt System .. 2

1.1.3 Miscellaneous..

1.2 Applications .... 2

1.3 Specifications.... . 3

1.4 Software Supporting .... . 4

1.4.1 Programming Library . 4

1.4.2 PCIS-LVIEW: LabVIEW® Driver..... 5

1.4.3 PCIS-VEE: HP-VEE Driver .... 5

1.4.4 DAQBenchTM: ActiveX Controls.. . 5

1.4.5 PCIS-DDE: DDE Server and InTouchTM.. 5

1.4.6 PCIS-ISG: ISaGRAFTM driver ... . 5

1.4.7 PCIS-ICL: InControlTM Driver ... . 6

1.4.8 PCIS-OPC: OPC Server... 6

# Chapter 2 Installation......

2.1 What You Have ........

2.2 Unpacking...... . 8

2.3 PCI-7396 Layout .. 9

2.4 Hardware Installation Outline .. . 10

2.5 Connectors’ Pin Assignment of PCI-7348... 11

2.6 Connectors’ Pin Assignment of PCI-7396... . 12

2.7 Jumpers’ Description...... .. 13

2.7.1 Power-on-state . .13

2.8 Termination Boards Supporting......... .. 14

2.8.1 Connect with DIN-100S... .14

2.8.2 Connect with DIN-96DI... .14

2.8.3 Connect with DIN-96DO... .14

# Chapter 3 Registers Format ....... ....15

3.1 PCI PnP Registers ..... .. 15

3.2 I/O Address Map.... . 17

3.3 Digital Data Registers .. . 18

3.4 Control Register .... .. 19

3.5 External Trigger Enable Register ..... . 19
3.6 External Trigger Disable Register ..... ... 20
3.7 Change of State (COS) Control Register ...... ... 20
3.8 Interrupt Source Control (ISC) Register .... ... 21
3.9 Clear Interrupt Register ... . 22
3.10 Timer/Counter Register... . 22
3.11 High Level Programming...... . 22

# Chapter 4 Operation Theorem.......... ...23

4.1 Digital I/O Ports ..... .. 23

4.1.1 Introduction.. .23
4.1.2 External Trigger ... .23

4.2 8254 Timer/Counter Operation ... . 25

4.2.1 Introduction... . 25
4.2.2 Cascaded 32 bits Timer... . 25
4.2.3 Event Counter and Edge Control... .25

4.3 Interrupt Circuit... ... 26

4.3.1 System Architecture .. . 26
4.3.2 IRQ Level Setting.... .. 26
4.3.3 Dual Interrupt System.. .27
4.3.4 Interrupt Source Control (ISC) .. .28
4.3.5 Change of State (COS) Interrupt ... . 29

4.4 12V and 5V Power Supply ...... .. 30

# Chapter 5 C/C++ Libraries......... ...31

5.1 Libraries Installation .... .. 31
5.2 Programming Guide ... .. 32

5.2.1 Naming Convention .. .32
5.2.2 Data Types .. .32

5.3 \_7396\_Initial .. .. 33
5.4 \_7396\_DI ... .. 34
5.5 \_7396\_DO ... .. 36
5.6 \_7396\_Config\_Port ... . 37
5.7 \_7396\_Software\_Reset ... . 39
5.8 \_7396\_INT\_Source\_Control... .. 40
5.9 \_7396\_COSIRQ\_Control.... ... 41
5.10 \_7396\_CLR\_IRQ ... ... 42
5.11 \_7396\_Set\_Event\_Edge .... .. 43
5.12 \_7396\_Cascaded\_Timer.... ... 44
5.13 \_7396\_Timer\_Start .... .. 45

5.14 \_7396\_Timer\_Read .. ... 46

# Appendix 1 DIN-96DI ..... ..47

A1.1 Introductions ..... .. 47

A1.2 Features ......... .. 47

A1.3 Specifications ..... .. 47

A1.4 Layout of DIN-96DI .. .. 49

A1.5 DI Circuits and Wiring ..... .. 50

# Appendix 2 DIN-96DO....... ...51

A2.1 Introductions ..... ... 51

A2.2 Features ... .. 51

A2.3 Specifications ..... ... 51

A2.4 Layout of DIN-96DO... .. 53

A2.5 Circuits and Wiring ..... .. 54

# Warranty Policy ........... .....56

# How to Use This Guide

This manual is designed to help you use the PCI-7396. It describes how to modify and control various functions on the PCI-7396 card to meet your requirements. It is divided into three chapters:

Chapter 1, "Introduction," gives an overview of the product features. applications, and specifications.
Chapter 2, "Installation," describes how to install the PCI-7396. The layout of PCI-7396 is shown. The jumper settings, the connectors’ pin assignment, and the other notes for installation are described.
Chapter 3, "Registers’ Format," describes the details of registers’ format and structure of the PCI-7396, this information is very important for the programmers who want to control the hardware by low-level programming language.
Chapter 4, "Operation Theorem" describes more details about the versatile functions, including DIO, timer / counter, and interrupt systems.
Chapter 5, "C/C++ Software Libraries" specifies the software libraries of C/C++ language under DOS environment that make you operate the functions of this card easily.

# 1

# Introduction

The PCI-7396 is a 48/96-bit parallel digital input/output (DIO) card designed for industrial applications. The plug and play feature of PCI-Bus architecture make it easy for users to install their systems quickly.

The PCI-7396 emulates two/four 8255 Programmable Peripheral Interface (PPI) chips. Each PPI offers 3 8-bit DIO ports which can be accessed simultaneously. The total 6/12 ports can be programmed as input or output independently.

The PCI-7396 supports external trigger to latch the digital input data. The function of “Change of State” (COS) interrupt is provided. It means when anyone of these digital inputs changes its state, an interrupt will be generated for user to handle this external event.

# 1.1 Features

The PCI-7396 Digital I/O boards provide the following advanced features:

# 1.1.1 Digital I/O Ports

u 48/96 TTL compatible digital I/O lines
u SCSI-type 100-pin connector (AMP-787082-9)
u 48mA High current driving capability per channel
u Output status read-back
u Support external trigger to latch digital input data (PCI-7348 only)

# 1.1.2 Timer / Counter and Interrupt System

u A programmable 32-bit timer to generate timer interrupt
u A programmable 16-bit event counter to generate event interrupt
u 48/96-bit change of state (COS) interrupt
u Dual interrupt system

# 1.1.3 Miscellaneous

Provide 12V and 5V power supply on SCSI-type 100-pin connectors(only for PCI-7348)
On board resettable fuses to protect power supply from external damage. (only for PCI-7348)

# 1.2 Applications

u Programmable mixed digital input & output
u Industrial monitoring and controlling
u LED indicator driving
u Parallel data transfer
u TTL,DTL, and CMOS logic sensing

# 1.3 Specifications

<table><tr><td>I/O channels</td><td>48-bit for PCI-734896-bit for PCI-7396</td><td></td></tr><tr><td rowspan="4">Input Signal</td><td>Logic High Voltage</td><td>: 2.0 V to 5.25V</td></tr><tr><td>Logic Low Voltage</td><td>: 0.0 V to 0.80V</td></tr><tr><td>Logic High Current</td><td>: 0.1 uA</td></tr><tr><td>Logic Low Current</td><td>:-8 mA</td></tr><tr><td rowspan="4">Output Signal</td><td>Logic High Voltage</td><td>: Typical 3.3 V: Minimum 2.4 V</td></tr><tr><td>Logic Low Voltage</td><td>: Maximum 0.5V</td></tr><tr><td>Logic High Current</td><td>:-15.0 mA</td></tr><tr><td>Logic Low Current</td><td>: 48.0 mA</td></tr><tr><td>Operating Temperature</td><td colspan="2">0° ~ 60°C</td></tr><tr><td>Storage Temperature</td><td colspan="2">-20° ~ 80°C</td></tr><tr><td>Humidity</td><td colspan="2">5% ~ 95% non-condensing</td></tr><tr><td>I/O Connectors</td><td colspan="2">100-pin SCSI connector</td></tr><tr><td>Bus</td><td colspan="2">PCI bus, rev 2.1</td></tr><tr><td>IRQ Level</td><td colspan="2">Set by PCI BIOS</td></tr><tr><td>I/O port address</td><td colspan="2">Set by PCI BIOS</td></tr><tr><td>Power Consumption</td><td colspan="2">PCI-7348 :350mA (TYP)</td></tr><tr><td>(without external devices)</td><td colspan="2">PCI-7396 : 450mA (TYP)</td></tr><tr><td>Transfer Rate</td><td colspan="2">1M bytes/sec (Typical)</td></tr><tr><td>Size</td><td colspan="2">Half-size PCB : 158 mm x 107 mm</td></tr></table>

# 1.4 Software Supporting

ADLink provides versatile software drivers and packages for users’ different approach to built-up a system. We not only provide programming library such as DLL for many Windows systems, but also provide drivers for many software package such as LabVIEW®, HP VEETM, DASYLabTM, InTouchTM, InControlTM, ISaGRAFTM, and so on.

All the software options are included in the ADLink CD. The non-free software drivers are protected with serial licensed code. Without the software serial number, you can still install them and run the demo version for two hours for demonstration purpose. Please contact with your dealer to purchase the formal license serial code.

# 1.4.1 Programming Library

For customers who are writing their own programs, we provide function libraries for many different operating systems, including:

DOS Library: Borland C/C++ and Microsoft C++, the functions descriptions are included in this user’s guide.
Windows 95 DLL: For VB, VC++, Delphi, BC5, the functions descriptions are included in this user’s guide.
PCIS-DASK: Include device drivers and DLL for Windows 98, Windows NT and Windows 2000. DLL is binary compatible across Windows 98, Windows NT and Windows 2000. That means all applications developed with PCIS-DASK are compatible across Windows 98, Windows NT and Windows 2000. The developing environment can be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The user’s guide and function reference manual of PCIS-DASK are in the CD. Please refer the PDF manual files under (\\Manual\_PDF\Software\PCIS-DASK)
PCIS-DASK/X: Include device drivers and shared library for Linux. The developing environment can be Gnu C/C++ or any programming language that allows linking to a shared library. The user's guide and function reference manual of PCIS-DASK/X are in the CD. (\\Manual\_PDF\Software\PCIS-DASK-X.)

The above software drivers are shipped with the board. Please refer to the “Software Installation Guide” to install these drivers.

# 1.4.2 PCIS-LVIEW: LabVIEW® Driver

PCIS-LVIEW contains the VIs, which are used to interface with NI’s LabVIEW® software package. The PCIS-LVIEW supports Windows 95/98/NT/2000. The LabVIEW® drivers are free shipped with the board. You can install and use them without license. For detail information about PCIS-LVIEW, please refer to the user’s guide in the CD.

(\\Manual\_PDF\Software\PCIS-LVIEW)

# 1.4.3 PCIS-VEE: HP-VEE Driver

The PCIS-VEE includes the user objects, which are used to interface with HP VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE drivers are free shipped with the board. You can install and use them without license. For detail information about PCIS-VEE, please refer to the user’s guide in the CD.

(\\Manual\_PDF\Software\PCIS-VEE)

# 1.4.4 DAQBenchTM: ActiveX Controls

We suggest the customers who are familiar with ActiveX controls and VB/VC++ programming use the DAQBenchTM ActiveX Control components library for developing applications. The DAQBenchTM is designed under Windows NT/98. For more detailed information about DAQBench, please refer to the user’s guide in the CD.

(\\Manual\_PDF\Software\DAQBench\DAQBench Manual.PDF)

# 1.4.5 PCIS-DDE: DDE Server and InTouchTM

DDE stands for Dynamic Data Exchange specifications. The PCIS-DDE includes the PCI cards’ DDE server. The PCIS-DDE server is included in the ADLINK CD. It needs license. The DDE server can be used conjunction with any DDE client under Windows NT.

# 1.4.6 PCIS-ISG: ISaGRAFTM driver

The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG includes ADLink products’ target drivers for ISaGRAF under Windows NT environment. The PCIS-ISG is included in the ADLINK CD. It needs license.

# 1.4.7 PCIS-ICL: InControlTM Driver

PCIS-ICL is the InControl driver which support the Windows NT. The PCIS-ICL is included in the ADLINK CD. It needs license.

# 1.4.8 PCIS-OPC: OPC Server

PCIS-OPC is an OPC Server, which can link with the OPC clients. There are many software packages on the market can provide the OPC clients now. The PCIS-OPC supports the Windows NT. It needs license.

# 2

# Installation

This chapter describes how to install the PCI-7396. The contents in the package and unpacking information that you should be careful are described.

Please follow the steps to install the PCI-7348/7396.

u Check what you have (section 2.1)
u Unpacking (section 2.2)
u Check the PCB (section 2.3)
u Install the hardware (section 2.4)
u Please refer to the “Software Installation Guide” to install the software drivers.

# 2.1 What You Have

In addition to this User's Manual, the package includes the following items:

u PCI-7396 96-bits Parallel Digital I/O Card
u ADLINK CD
u Software Installation Guide

If any of these items is missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

# 2.2 Unpacking

Your PCI-7396 card contains sensitive electronic components that can be easily damaged by static electricity.

The card should be done on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handing damages on the module before processing.

After opening the card module carton, exact the system module and place it only on a grounded anti-static surface component side up.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

You are now ready to install your PCI-7396.

# 2.3 PCI-7396 Layout

![SILK_TOP\nA1\n845\n7341\n6329\n5932\n5741\n5431\n5241\n5041\n4844\n3741\n3541\n3341\n3141\n2941\n2741\n2541\n2341\n2141\n1941\n1741\n1541\n1341\n1141\n941\n831\n731\n631\n531\n431\n331\n231\n131\n91\n80\n70\n60\n50\n40\n30\n20\n10\n0\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGR050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050\nPGr050](.pci-7348-7396-manual-3-en/70c41109e97a947121b4264b3298c68bcb6fd875ab11592e512f430d325ec337.jpg)

Figure 2.1 PCI-7396 Layout

# 2.4 Hardware Installation Outline

# Hardware configuration

The PCI cards (or CompactPCI cards) are equipped with plug and play PCI controller, it can request base addresses and interrupt according to PCI standard. The system BIOS will install the system resource based on the PCI cards’ configuration registers and system parameters (which are set by system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can be assigned by system BIOS only. These system resource assignments are done on a board-by-board basis. It is not suggested to assign the system resource by any other methods.

# PCI slot selection

The PCI card can be inserted to any PCI slot without any configuration for system resource.

# Installation Procedures

1 Turn off your computer
2 Turn off all accessories (printer, modem, monitor, etc.) connected to your computer.
3 Remove the cover from your computer.
4 Setup jumpers on the PCI or CompactPCI card.
5 Select a 32-bit PCI slot. PCI slot are short than ISA or EISA slots, and are usually white or ivory.
6 Before handling the PCI cards, discharge any static buildup on your body by touching the metal case of the computer. Hold the edge and do not touch the components.
7 Position the board into the PCI slot you selected.
8 Secure the card in place at the rear panel of the system.

# 2.5 Connectors’ Pin Assignment of PCI-7348

The I/O pin assignment of PCI-7348 is shown in the Figure 2.2.

![| Row | Column | Value |\n|---|---|---|\n| 1 | P1A0 | 26 |\n| 1 | P2A0 | 51 |\n| 1 | EVENT | 76 |\n| 1 | GND | |\n| 2 | P1A1 | 27 |\n| 2 | P2A1 | 52 |\n| 2 | GND | 77 |\n| 2 | GND | |\n| 3 | P1A2 | 28 |\n| 3 | P2A2 | 53 |\n| 3 | GND | 78 |\n| 3 | GND | |\n| 4 | P1A3 | 29 |\n| 4 | P2A3 | 54 |\n| 4 | GND | 79 |\n| 4 | GND | |\n| 5 | P1A4 | 30 |\n| 5 | P2A4 | 55 |\n| 5 | GND | 80 |\n| 5 | GND | |\n| 6 | P1A5 | 31 |\n| 6 | P2A5 | 56 |\n| 6 | GND | 81 |\n| 6 | GND | |\n| 7 | P1A6 | 32 |\n| 7 | P2A6 | 57 |\n| 7 | GND | 82 |\n| 7 | GND | |\n| 8 | P1A7 | 33 |\n| 8 | P2A7 | 58 |\n| 8 | GND | 83 |\n| 8 | GND | |\n| 9 | P1B0 | 34 |\n| 9 | P2B0 | 59 |\n| 9 | GND | 84 |\n| 9 | GND | |\n| 10 | P1B1 | 35 |\n| 10 | P2B1 | 60 |\n| 10 | GND | 85 |\n| 10 | GND | |\n| 11 | P1B2 | 36 |\n| 11 | P2B2 | 61 |\n| 11 | GND | 86 |\n| 11 | GND | |\n| 12 | P1B3 | 37 |\n| 12 | P2B3 | 62 |\n| 12 | GND | 87 |\n| 12 | GND | |\n| 13 | P1B4 | 38 |\n| 13 | P2B4 | 63 |\n| 13 | GND | 88 |\n| 13 | GND | |\n| 14 | P1B5 | 39 |\n| 14 | P2B5 | 64 |\n| 14 | GND | 89 |\n| 14 | GND | |\n| 15 | P1B6 | 40 |\n| 15 | P2B6 | 65 |\n| 15 | GND | 90 |\n| 15 | GND | |\n| 16 | P1B7 | 41 |\n| 16 | P2B7 | 66 |\n| 16 | GND | 91 |\n| 16 | GND | |\n| 17 | P1C0 | 42 |\n| 17 | P2C0 | 67 |\n| 17 | GND | 92 |\n| 17 | GND | |\n| 18 | P1C1 | 43 |\n| 18 | P2C1 | 68 |\n| 18 | GND | 93 |\n| 18 | GND | |\n| 19 | P1C2 | 44 |\n| 19 | P2C2 | 69 |\n| 19 | GND | 94 |\n| 19 | GND | |\n| 20 | P1C3 | 45 |\n| 20 | P2C3 | 70 |\n| 20 | GND | 95 |\n| 20 | GND | |\n| 21 | P1C4 | 46 |\n| 21 | P2C4 | 71 |\n| 21 | GND | 96 |\n| 21 | GND | |\n| 22 | P1C5 | 47 |\n| 22 | P2C5 | 72 |\n| 22 | GND | 97 |\n| 22 | GND | |\n| 23 | P1C6 | 48 |\n| 23 | P2C6 | 73 |\n| 23 | GND | 98 |\n| 23 | GND | |\n| 24 | P1C7 | 49 |\n| 24 | P2C7 | 74 |\n| 24 | GND | (99) EXTTRG\n(25) V5V (50) +12V (75) V5V (100) +12V](.pci-7348-7396-manual-3-en/3bf9a77c60e0a58f67d45ba3d3e8871afccbfd2ca1112618fdc277487286bb88.jpg)

The DIO pin names are specified as PnXb, where

n : means the PPI number of the PCI-7348, n=1\~2

X : means the port name of the PPI, X= ‘A’ , ‘B’ or ‘C’

b: means the bit number of the port, b=0\~7

For example, P1C4 means bit 4 of port C on PPI1.

EXTTRG : External trigger signal to latch digital input data

EVENT : External event source for counter 0

V5V : +5V power supply output

+12V : +12v power supply output

GND : Ground

Note : The power supply pins are protected by resettable fuses. Refer to section 4.4 for details of the power supply.

# 2.6 Connectors’ Pin Assignment of PCI-7396

![(1)\n(2)\n(3)\n(51)\n(52)\n(53)\n(48)\n(49)\n(50)\n(98)\n(99)\n(100)](.pci-7348-7396-manual-3-en/2173c82270413bfb5d29c100afd9ba32f0df620dacc140b17fa66b7d4e27d82d.jpg)

(1) P1A0(26) P2A0(51) P3A0/EVENT (76) P4A0
(2) P1A1(27) P2A1(52) P3A1(77) P4A1
(3) P1A2(28) P2A2(53) P3A2(78) P4A2
(4) P1A3(29) P2A3(54) P3A3(79) P4A3
(5) P1A4(30) P2A4(55) P3A4(80) P4A4
(6) P1A5(31) P2A5(56) P3A5(81) P4A5
(7) P1A6(32) P2A6(57) P3A6(82) P4A6
(8) P1A7(33) P2A7(58) P3A7(83) P4A7
(9) P1B0(34) P2B0(59) P3B0(84) P4B0
(10) P1B1(35) P2B1(60) P3B1(85) P4B1
(11)P1B2(36) P2B2(61) P3B2(86) P4B2
(12) P1B3(37) P2B3(62) P3B3(87) P4B3
(13) P1B4(38) P2B4(63) P3B4(88) P4B4
(14) P1B5(39) P2B5(64) P3B5(89) P4B5
(15) P1B6(40) P2B6(65) P3B6(90) P4B6
(16) P1B7(41) P2B7(66) P3B7(91) P4B7
(17) P1C0(42) P2C0(67) P3C0(92) P4C0
(18) P1C1(43) P2C1(68) P3C1(93) P4C1
(19) P1C2(44) P2C2 (69) P3C2(94) P4C2
(20) P1C3(45) P2C3(70) P3C3(95) P4C3
(21) P1C4(46) P2C4(71) P3C4(96) P4C4
(22) P1C5(47) P2C5(72) P3C5(97) P4C5
(23) P1C6(48) P2C6(73) P3C6(98) P4C6
(24) P1C7(49) P2C7(74) P3C7(99) P4C7/EXTTRG
(25) GND (50) GND (75) GND (100) GND

Figure 2.3 Connectors Pin Assignment of PCI-7396

The DIO pin names are specified as PnXb, where

n : means the PPI number of the PCI-7396, n=1\~4

X : means the port name of the PPI, X= ‘A’ , ‘B’ or ‘C’

b: means the bit number of the port, b=0\~7

For example, P1C4 means bit 4 of port C on PPI1.

EXTTRG: External trigger signal to latch digital input data

EVENT: External event source for counter 0

GND: Ground

# 2.7 Jumpers’ Description

The PCI-7396 is a ‘plug and play’ add-on card using PCI bus. It is unnecessary for user to setup its base address and IRQ level to fit the hardware of your computer system. However, to fit users’ versatile operation, there are still a few jumpers to set the power-on-states of all I/O ports.

# 2.7.1 Power-on-state

For all I/O ports of the PCI-7396, the power-on-states could be pulled high, pulled low, or floating. It is depended on the jumper settings. Table 2.1 lists the reference numbers of jumpers and their corresponding port names.

<table><tr><td>Jumper</td><td>Port Name</td><td>Jumper</td><td>Port Name</td></tr><tr><td>JA1</td><td>P1A</td><td>JA3</td><td>P3A</td></tr><tr><td>JB1</td><td>P1B</td><td>JB3</td><td>P3B</td></tr><tr><td>JC1</td><td>P1C</td><td>JC3</td><td>P3C</td></tr><tr><td>JA2</td><td>P2A</td><td>JA4</td><td>P4A</td></tr><tr><td>JB2</td><td>P2B</td><td>JB4</td><td>P4B</td></tr><tr><td>JC2</td><td>P2C</td><td>JC4</td><td>P4C</td></tr></table>

Table 2.1 Jumpers and port names list

All the jumpers are identical physically. The power-on-state of each port can be set independently. To pull all signals low is the default settings. The following diagram use JA1 as an example to show the possible settings.

![JA1\nPort A of PPI1 is pulled low.(default setting)\nJA1\nPort A of PPI1 is pulled high.](.pci-7348-7396-manual-3-en/a62412673d04e533839ee6275e965092e79fb4429039570f624ebe92254990b7.jpg)

When the jumper cap is removed, the power-on-state is floating.

# 2.8 Termination Boards Supporting

PCI-7396 can be connected with several different daughter boards, including DIN-100S, DIN-96DI, and DIN-96DO. The functionality and connections are specified as follows.

# 2.8.1 Connect with DIN-100S

DIN-100S is a direct connector for the add-on card that is equipped with SCSI-100 connector. It is suitable for the simple applications that do not need isolated connection in front of the digital inputs or outputs of PCI-7396.

# 2.8.2 Connect with DIN-96DI

DIN-96DI digital input termination board features high-voltage opto-isolation on all inputs to prevent floating potential and ground loop problems from damaging your PC system. It is composed of one TB-96 base board, one TB-96DI daughter board, and one DIN socket for easy maintenance, wiring, and installation. It provides 96 channels that are accessed through a SCSI-100 connector.(see Appendix A1)

# 2.8.3 Connect with DIN-96DO

DIN-96DO digital output termination board features high-voltage optoisolation on all outputs to prevent floating potential and ground loop problems from damaging your PC system. It is composed of one TB-96 base board, one TB-96DO daughter board, and one DIN socket for easy maintenance, wiring, and installation. It provides 96 channels that are accessed through a SCSI-100 connector. (see Appendix A2).

#

# Registers Format

The detailed descriptions of the registers format are specified in this chapter. This information is quite useful for the programmers who wish to handle the card by low-level programming. However, we suggest user have to understand more about the PCI interface then start any low-level programming. In addition, the contents of this chapter can help users understand how to use software driver to manipulate this card.

# 3.1 PCI PnP Registers

This PCI card functions as a 32-bit PCI target device to any master on the PCI bus. There are three types of registers: PCI Configuration Registers (PCR), Local Configuration Registers (LCR) and PCI-6308 registers.

The PCR, which is compliant to the PCI-bus specifications, is initialized and controlled by the plug & play (PnP) PCI BIOS. User‘s can study the PCI BIOS specification to understand the operation of the PCR. Please contact with PCISIG to acquire the specifications of the PCI interface.

The PCI bus controller PCI-9050 is provided by PLX technology Inc. (www.plxtech.com). For more detailed information of LCR, please visit PLX technology’s web site to download relative information. It is not necessary for users to understand the details of the LCR if you use the software library. The PCI PnP BIOS assigns the base address of the LCR. The assigned address is located at offset 14h of PCR.

The PCI-6308 registers are shown in the next section. The base address, which is also assigned by the PCI PnP BIOS, is located at offset 18h of PCR. Therefore, users can read the 18h of PCR to know the base address by using the BIOS function call.

Please do not try to modify the base address and interrupt which assigned by the PCI PnP BIOS, it may cause resource confliction in your system.

# 3.2 I/O Address Map

Most of the PCI-7396 registers are 32 bits. The users can access these registers by 32 bits I/O instructions. The following table shows the registers map, including descriptions and their offset addresses relative to the base address.

<table><tr><td>Offset</td><td>Write</td><td>Read</td></tr><tr><td>0x00</td><td>P1ABC</td><td>P1ABC</td></tr><tr><td>0x04</td><td>P1Control</td><td>No used</td></tr><tr><td>0x08</td><td>P1EXTTRG Enable</td><td>No used</td></tr><tr><td>0x0C</td><td>P1EXTTRG Disable</td><td>No used</td></tr><tr><td>0x10</td><td>P2ABC</td><td>P2ABC</td></tr><tr><td>0x14</td><td>P2Control</td><td>No used</td></tr><tr><td>0x18</td><td>P2EXTTRG Enable</td><td>No used</td></tr><tr><td>0x1C</td><td>P2EXTTRG Disable</td><td>No used</td></tr><tr><td>0x20</td><td>P3ABC</td><td>P3ABC</td></tr><tr><td>0x24</td><td>P3Control</td><td>No used</td></tr><tr><td>0x28</td><td>P3EXTTRG Enable</td><td>No used</td></tr><tr><td>0x2C</td><td>P3EXTTRG Disable</td><td>No used</td></tr><tr><td>0x30</td><td>P4ABC</td><td>P4ABC</td></tr><tr><td>0x34</td><td>P4Control</td><td>No used</td></tr><tr><td>0x38</td><td>P4EXTTRG Enable</td><td>No used</td></tr><tr><td>0x3C</td><td>P4EXTTRG Disable</td><td>No used</td></tr><tr><td>0x40</td><td>Timer/Counter #0</td><td>Timer/Counter #0</td></tr><tr><td>0x44</td><td>Timer/Counter #1</td><td>Timer/Counter #1</td></tr><tr><td>0x48</td><td>Timer/Counter #2</td><td>Timer/Counter #2</td></tr><tr><td>0x4C</td><td>Timer/Counter Mode Control</td><td>Timer/Counter Mode Status</td></tr><tr><td>0x50</td><td>ISC: Interrupt Source Control</td><td>No used</td></tr><tr><td>0x54</td><td>Clear Interrupt</td><td>No used</td></tr><tr><td>0x60</td><td>P1 COS Control</td><td>No used</td></tr><tr><td>0x64</td><td>P2 COS Control</td><td>No used</td></tr><tr><td>0x68</td><td>P3 COS Control</td><td>No used</td></tr><tr><td>0x6C</td><td>P4 COS Control</td><td>No used</td></tr></table>

Table 3.1 Register Map

The PCI-7396 has 2/4 PPIs on board. Each PPI contains 5 registers, including Digital Data Register, Control Register, External Trigger Enable Register, External Trigger Disable Register, and COS Interrupt Control Register.

In the following sections, the 5 registers of PPI1 will be introduced respectively. The registers of the other 3 PPIs are of the same configuration which will not be repeated in this manual.

# 3.3 Digital Data Registers

The 24-bit I/O data of the PCI-7396 is accessed from/to this register by software. The digital data can also be read back through this register.

Address: BASE + 00h

Attribute: read and write

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+00h</td><td>P1A7</td><td>P1A6</td><td>P1A5</td><td>P1A4</td><td>P1A3</td><td>P1A2</td><td>P1A1</td><td>P1A0</td></tr><tr><td>BASE+01h</td><td>P1B7</td><td>P1B6</td><td>P1B5</td><td>P1B4</td><td>P1B3</td><td>P1B2</td><td>P1B1</td><td>P1B0</td></tr><tr><td>BASE+02h</td><td>P1C7</td><td>P1C6</td><td>P1C5</td><td>P1C4</td><td>P1C3</td><td>P1C2</td><td>P1C1</td><td>P1C0</td></tr><tr><td>BASE+03h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

P1X7\~P1X0: Digital I/O data X:A\~C.

# 3.4 Control Register

Each PPI’s control register is used to set its three ports to be as input or output one independently.

Address: BASE + 04h

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+ 04h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>P1C</td><td>P1B</td><td>P1A</td></tr><tr><td>BASE+ 05h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+ 06h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+ 07h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

P1n : n: port number

Set to be $\scriptstyle { \mathfrak { O } } ^ { \prime }$ for input port , ‘1’ for output port

# 3.5 External Trigger Enable Register

Users can write anything to this register to enable the external trigger to latch the input data of port A,B and C simultaneously. Note that when this register is enabled, the settings of the previous control register are disabled.

Address: BASE + 08h

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+08h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+09h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+0Ah</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+0Bh</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

# 3.6 External Trigger Disable Register

Users can write anything to this register to disable the function of external trigger.

Address: BASE + 0Ch

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+0Ch</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+0Dh</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+0Eh</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+0Fh</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

# 3.7 Change of State (COS) Control Register

This register is used to configure the COS interrupt.

Address: BASE + 60h

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+60h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>P1C</td><td>P1B</td><td>P1A</td></tr><tr><td>BASE+61h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+62h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+64h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

P1n : n: port number

Set to be ‘0’ to disable COS , ‘1’ to enable COS

# 3.8 Interrupt Source Control (ISC) Register

The PCI-7396 has a dual interrupt system, two interrupt sources can be generated and be distinguished by software setting. This register is used to select the interrupt sources.

Address: BASE + 50h

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+50h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>C2_1</td><td>C2_0</td><td>C1_1</td><td>C1_0</td></tr><tr><td>BASE+51h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+52h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+54h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

C1\_0,C1\_1 : Select source INT 1

C2\_0,C2\_1 : Select source INT 2

<table><tr><td>INT1</td><td>C1_1</td><td>C1_0</td><td>IRQ Sources</td><td>IRQ Trigger Condition</td></tr><tr><td>Mode 1</td><td>0</td><td>0</td><td>COS P1&amp;P2 (48bits)</td><td>Change of State for PCI-7396 P1 &amp; P2</td></tr><tr><td>Mode 2</td><td>0</td><td>1</td><td>P1C0 OR ~P1C3</td><td>(see Table 4.2)</td></tr><tr><td>Mode 3</td><td>1</td><td>0</td><td>~P1C0</td><td>falling edge of P1C0</td></tr><tr><td>Mode 4</td><td>1</td><td>1</td><td>Event Counter</td><td>Counter count down to 0</td></tr><tr><td>INT2</td><td>C2_1</td><td>C2_0</td><td>IRQ Sources</td><td>IRQ Trigger Condition</td></tr><tr><td>Mode 1</td><td>0</td><td>0</td><td>COS P3&amp;P4(48bits)</td><td>Change of State for PCI-7396 P3 &amp; P4</td></tr><tr><td>Mode 2</td><td>0</td><td>1</td><td>P2C0 OR ~P2C3</td><td>(see Table 4.2)</td></tr><tr><td>Mode 3</td><td>1</td><td>0</td><td>~P2C0</td><td>falling edge of P2C0</td></tr><tr><td>Mode 4</td><td>1</td><td>1</td><td>32-bit Timer</td><td>Timer count down to 0</td></tr></table>

# 3.9 Clear Interrupt Register

Users can write anything to this register to clear the interrupt request of the PCI-7396.

Address: BASE + 54h

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+54h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+55h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+56h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr><tr><td>BASE+57h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

# 3.10 Timer/Counter Register

The 8254 chip occupies 4 I/O addresses in the PCI-7396. Please refer to NEC's or Intel's data sheet for the full description of the 8254 operation.

Address : BASE + 40h \~ BASE + 4Ch

Attribute : read / write

Data Format :

<table><tr><td>Base + 40h</td><td>Bit 7~Bit 0: Counter 0 Register</td></tr><tr><td>Base + 44h</td><td>Bit 7~Bit 0: Counter 1 Register</td></tr><tr><td>Base + 48h</td><td>Bit 7~Bit 0: Counter 2 Register</td></tr><tr><td>Base + 4Ch</td><td>Bit 7~Bit 0: Control Register</td></tr></table>

# 3.11 High Level Programming

To operate the PCI-7396 quickly, you can bypass the detailed register structures and use the high-level application programming interface (API) directly. The DOS library for Borland C/C++ is included in the ADLINK CD. Please refer to chapter 5 for more detailed information.

4

# Operation Theorem

The operation theorem of the functions on PCI-7396 card is described in this chapter. The operation theorem can help you to understand how to manipulate or to program the PCI-7396.

# 4.1 Digital I/O Ports

# 4.1.1 Introduction

The PCI-7396 has 2/4 PPIs on board. Each 24-bit PPI is divided into three 8-bit I/O ports: A, B, and C. All of these 6/12 ports can be programmed as input or output independent.

# 4.1.2 External Trigger

The pin-99 EXTTRG support user to receive an external trigger to latch input data. User can use function \_7396\_Set\_Event\_Edge to set EXTTRG pin to be active high or active low.

![This diagram depicts a central, blank vertical rectangle connected to various inputs and an output via arrows.\n\n**Labeled Blocks and Connections:**\n\n*   **Central Block:** A vertical rectangle in the center.\n*   **Left Inputs (pointing into the rectangle):**\n    *   A thick black arrow labeled **INPUT**.\n    *   A thin black arrow labeled **EXTTR** with the text **Edge Control** positioned above the arrow shaft.\n    *   A thin black arrow labeled **Read Data**.\n*   **Right Output (pointing away from the rectangle):**\n    *   A thick black arrow labeled **DATA to PC**.](.pci-7348-7396-manual-3-en/a02bb6d114c01ea036c20df7497df4217e70d5d85f2f61b427b9dd86895893c2.jpg)

Figure 4.1 External Trigger Function Block

EXTTRG

![The image displays a black and white line drawing, likely a schematic symbol. On the left side, there is a thick vertical black line. Extending to the right from the top of this vertical line is a thinner horizontal black line. Positioned to the right of the thick vertical line and below the top horizontal line is an arrow pointing upward, consisting of a vertical shaft and a triangular arrowhead. The composition suggests a diagram indicating upward flow or direction relative to a vertical reference line.](.pci-7348-7396-manual-3-en/cd92a571918a9e277795b1638e86aa2e6119741226069908e0c2d91788703840.jpg)

Latch Data (Latch input data to

Read Data (Read date from registers

Figure 4.2 Read Data use External Trigger

# 4.2 8254 Timer/Counter Operation

# 4.2.1 Introduction

One 8254 programmable timer/counter chip is installed in the PCI-7396. There are three counters in one 8254 chip and 6 possible operation modes for each counter. The block diagram of the timer /counter system is shown in Figure 4.3.

![Based on the provided flowchart/block diagram, here is an accurate and concise description:\n\n**Main Component:**\n*   **8254 Chip**: A large rectangular block divided into three internal sections: 'Counter #0' (top), 'Timer #1' (middle), and 'Timer #2' (bottom).\n\n**Inputs and Connections:**\n*   **EVENT (PIN 51)**: This text points to a box labeled **'Event Edge Control'**.\n*   From **'Event Edge Control'**, an arrow points to the **'Counter #0'** block. The text **'Gate='H''** appears near this connection.\n*   **'2 MHz Clock'**: An arrow points from this text into the **'Timer #1'** block. The text **'Gate='H''** appears near this connection.\n*   **Internal Link**: A line exits the right side of **'Timer #1'**, goes down, turns right, and enters the left side of **'Timer #2'**, indicating a cascade connection.\n*   **Bottom Left Box**: A box labeled **'Gate='H''** is situated below the timers. A line extends from it to the right and up, connecting to the input area of the **'Timer #2'** section.\n\n**Outputs:**\n*   **Event IRQ**: An arrow exits the right side of **'Counter #0'**.\n*   **Timer IRQ**: An arrow exits the right side of **'Timer #2'**.](.pci-7348-7396-manual-3-en/a1dd57969aa3912ca35328f7eff026e01fac6cdd021d5981f2b05847e566352e.jpg)

Figure 4.3 Timer / counter system of PCI-7396.

Timer #1 and timer #2 of the 8254 chip are cascaded as a 32-bits programmable timer. In the software library, timer #1 and #2 are always set as mode 2 (rate generator). Counter #0 is used as an event counter, that is, there is an interrupt on the terminal count of 8254 mode 0.

# 4.2.2 Cascaded 32 bits Timer

The base frequency of input clock for the cascaded timer is 2MHz. The output is send to be the timer interrupt. To set the maximum and minimum frequency of the timer, please refer to the function \_7348\_Cascaded\_Timer or \_7396\_Cascaded\_Timer.

# 4.2.3 Event Counter and Edge Control

The counter #0 of 8254 is used to be an event counter. The input is pin-51 of CN1. The trigger edge of counter clock is programmable. The gate control fixs high (enable). The output is send to be the event interrupt. That means If counter #0 is set as 8254 mode 0, the event IRQ asserts as the counter counts down to zero.

# 4.3 Interrupt Circuit

# 4.3.1 System Architecture

The PCI-7396‘s interrupt system is powerful and flexible, which is suitable for many applications. It is a Dual Interrupt System. The dual interrupt means the hardware can generate two interrupt request signals in the same time and the software can service these two request signals by ISR. Note that the dual interrupt do not mean the card occupy two IRQ levels.

The two interrupt request signals (INT1 and INT2) comes from digital inputs or the timer/counter outputs. Two multiplexers (MUX) are used to select the IRQ sources. Fig 4.4 shows the interrupt system.

# 4.3.2 IRQ Level Setting

There is only one IRQ level needed in the PCI-7396, although it is a dual interrupt system. This card uses INT #A interrupt request signal on PCI bus. The mother board circuits will transfer INT #A to one of the AT bus IRQ levels. The IRQ level is set by the PCI plug and play BIOS and saved in the PCI controller. It is not necessary for users to set the IRQ level. Users can get the IRQ level by software library.

# 4.3.3 Dual Interrupt System

The PCI controller can receive two hardware IRQ requests. However, only one IRQ will be sent to PCI bus, the two IRQ requests must be distinguished by user’s interrupt service routine (ISR).

The two IRQ requests are named as INT1 and INT2. INT1 comes from COS P1 & P2, P1C0, P1C3, or the event counter interrupt. INT2 comes from COS P3 & P4, P2C0, P2C3, or the timer interrupt. The sources of INT1 and INT2 is selectable by using the Interrupt Source Control (ISC) Register.

![This block diagram illustrates the signal flow for interrupt handling. The labeled blocks and connections are:\n\n**Blocks:**\n*   **PCI Controller** (Left)\n*   **IRQ Flip-Flops** (Center)\n*   **INT1 MUX** (Top Right)\n*   **INT2 MUX** (Bottom Right)\n\n**Connections:**\n*   **INT #A**: An arrow pointing left from the **PCI Controller**.\n*   **INT1**: An arrow pointing left from the **IRQ Flip-Flops** to the **PCI Controller**.\n*   **INT2**: An arrow pointing left from the **IRQ Flip-Flops** to the **PCI Controller**.\n*   **Clear IRQ**: An arrow pointing up into the bottom of the **IRQ Flip-Flops**.\n*   **INT1 MUX Inputs**: Four arrows pointing left into the **INT1 MUX** labeled **~P1C0**, **P1C0/~/P1C3**, **COS P1 & P2**, and **Event IRQ**. The output of this block points left to the **IRQ Flip-Flops**.\n*   **INT2 MUX Inputs**: Four arrows pointing left into the **INT2 MUX** labeled **~P2C0**, **P2C0/~/P2C**, **COS P3 & P4**, and **Timer IRQ**. The output of this block points left to the **IRQ Flip-Flops**.](.pci-7348-7396-manual-3-en/71562a8d0bb1a9e61bfeaa9d3ba1d2f2697f45c4a73fa6b233c48dfab9abc8d5.jpg)

Figure 4.4 Dual Interrupt System of PCI-7396

# 4.3.4 Interrupt Source Control (ISC)

There are four bits to control the IRQ sources of INT1 and INT2. Table 4.1 shows the selection of the IRQ sources and the interrupt trigger condition.

If the application needs one IRQ only, you can disable one of the IRQ sources by software. You can also disable both the two interrupts If you do not need any IRQ source. However, the PCI BIOS still assign a IRQ level to the PCI card and occupy the PC resource if you only disable the IRQ sources without change the initial condition of the PCI controller.

<table><tr><td>INT1</td><td>C1</td><td>C2</td><td>IRQ Sources</td><td>IRQ Trigger Condition</td></tr><tr><td>Disable</td><td>4</td><td>X</td><td>INT1 disable</td><td>--</td></tr><tr><td>Mode 1</td><td>0</td><td>X</td><td>COS P1&amp;P2 (48bits)</td><td>Change of State for PCI-7396</td></tr><tr><td>Mode 2</td><td>1</td><td>X</td><td>P1C0 OR ~P1C3</td><td>(see following)</td></tr><tr><td>Mode 3</td><td>2</td><td>X</td><td>~P1C0</td><td>falling edge of P1C0</td></tr><tr><td>Mode 4</td><td>3</td><td>X</td><td>Event Counter</td><td>Counter count down to 0</td></tr><tr><td>INT2</td><td>C1</td><td>C2</td><td>IRQ Sources</td><td>IRQ Trigger Condition</td></tr><tr><td>Disable</td><td>X</td><td>4</td><td>INT2 disable</td><td>--</td></tr><tr><td>Mode 1</td><td>X</td><td>0</td><td>COS P3&amp;P4 (48bits)</td><td>Change of State for PCI-7396</td></tr><tr><td>Mode 2</td><td>X</td><td>1</td><td>P2C0 OR ~P2C3</td><td>(see following)</td></tr><tr><td>Mode 3</td><td>X</td><td>2</td><td>~P2C0</td><td>falling edge of P2C0</td></tr><tr><td>Mode 4</td><td>X</td><td>3</td><td>Timer Output</td><td>Timer count down to 0</td></tr></table>

Table 4.1 ISC register format

![The image displays a simple, horizontal rectangle with a thick black border and a solid light gray fill. There is no text present in the image.](.pci-7348-7396-manual-3-en/8f899d4d80ac2c583bc658770c469e66865ceb47ce6ca3a2823f4e4199709708.jpg)

# Default settings

When the IRQ sources is set as “P1C0 OR \~P1C3” or “P2C0 OR \~P2C3”, the IRQ trigger conditions are summarized in Table 4.2,

<table><tr><td>P1C0</td><td>P1C3</td><td>IRQ Trigger Condition</td></tr><tr><td>High</td><td>X</td><td>P1C0=&#x27;H&#x27; disable all IRQ</td></tr><tr><td>X</td><td>Low</td><td>P1C3=&#x27;L&#x27; disable all IRQ</td></tr><tr><td>Low</td><td>1-&gt;0</td><td>P1C3 falling edge trigger when P1C0=L</td></tr><tr><td>0-&gt;1</td><td>High</td><td>P1C0 rising edge trigger when P1C3=H</td></tr><tr><td>P2C0</td><td>P2C3</td><td>IRQ Trigger Condition</td></tr><tr><td>High</td><td>X</td><td>P2C0=&#x27;H&#x27; disable all IRQ</td></tr><tr><td>X</td><td>Low</td><td>P2C3=&#x27;L&#x27; disable all IRQ</td></tr><tr><td>Low</td><td>1-&gt;0</td><td>P2C3 falling edge trigger when P2C0=L</td></tr><tr><td>0-&gt;1</td><td>High</td><td>P2C0 rising edge trigger when P2C3=H</td></tr></table>

Table 4.2 IRQ Trigger conditions

By using the four signals: P1C0, P2C0, P1C3, and P2C3, user can utilize their combination to generate a proper IRQ for versatile applications.

# 4.3.5 Change of State (COS) Interrupt

# What is COS?

The COS (Change of State) means when the input state (logic level) is changed from low to high, or from high to low. The COS detection circuit will detect the edge of level change. In the PCI-7396 card, the COS detection circuit is applied to all the input channels. When any channel changes its logic level, the COS detection circuit generates an interrupt request to PCI controller.

![P1A\nP2A0\nCOS\nCO\nINT1\nClear_IRQ Clear_IRQ Clear_IRQ](.pci-7348-7396-manual-3-en/3660c83b4f28070fdd7cc6cf4b48917e86f8c5d210550bccffdf69a94c45c475.jpg)

# COS Detection

The following timing is an example of COS operation. All the DI signals’ level change will be detected and then take an ‘OR’ operation to generate the INT1 or INT2 IRQ request.

If INT1 or INT2 IRQ request generates, the signal will be latched. User should apply the function “\_7396\_CLR\_IRQ” or “\_7348\_CLR\_IRQ” to reset its state, after the corresponding ISR is finished,

# 4.4 12V and 5V Power Supply

The SCSI-100 connector CN1 provides +12V and +5V power supply (only for PCI-7348) for external devices. To avoid the short circuit or the overload of the power supply, the resettable fuses are added on all the power supply signals.

The maximum current for 5V power supply is 0.5 A. If the load current is larger than this limitation, the resistance of the resettable fuse will increase for the reason of the rising temperature. The rising resistance will further cause the power supply to reduce the load current. After the condition of overload or short circuit is removed, the fuse will return to its normal condition. It is unnecessary to replace the fuse.

The maximum current of 12V power supply is 0.5A, too. The action of the fuse is the same as that of +5V power supply.

# 5

# C/C++ Libraries

This chapter describes the software library for operating this card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included in ADLINK CD, for the descriptions of the Windows 98/NT/2000 DLL functions.

The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95). For Windows 95 DLL, the developing environment can be Visual Basic 4.0 or above, Visual C/C++ 4.0 or above, Borland C++ 5.0 or above, Borland Delphi 2.x (32-bit) or above, or any Windows programming language that allows calls to a DLL. It provides the C/C++, VB, and Delphi include files.

# 5.1 Libraries Installation

Please refer to the “Software Installation Guide” for the detail information about how to install the software libraries for DOS, or Windows 95 DLL, or PCIS-DASK for Windows 98/NT/2000.

The device drivers and DLL functions of Windows 98/NT/2000 are included in the PCIS-DASK. Please refer the PCIS-DASK user’s guide and function reference, which included in the ADLINK CD, for detailed programming information.

# 5.2 Programming Guide

# 5.2.1 Naming Convention

The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using full-names to represent the functions' real meaning. The naming convention rules are:

In DOS Environment :

\_{hardware\_model}\_{action\_name}. e.g. \_7396\_Initial().

In order to recognize the difference between DOS library and Windows 95 library, a capital "W" is put on the head of each function name of the Windows 95 DLL driver. e.g. W\_7396\_Initial().

# 5.2.2 Data Types

We defined some data type in Pci\_7396.h (DOS) and Acl\_pci.h (Windows 95). These data types are used by NuDAQ Cards’ library. We suggest you to use these data types in your application programs. The following table shows the data type names and their range.

<table><tr><td>Type Name</td><td>Description</td><td>Range</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td></tr><tr><td>U32</td><td>32-bit single-precision floating-point</td><td>0 to 4294967295</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>-1.797683134862315E308 to 1.797683134862315E309</td></tr><tr><td>Boolean</td><td>Boolean logic value</td><td>TRUE, FALSE</td></tr></table>

# 5.3 \_7396\_Initial

# @ Description

This function is used to initialize the PCI-7396. Every PCI-7396 has to be initialized by this function before calling other functions.

# @ Syntax

```c
C/C++ (DOS)
U16 _7396_Initial (U16 *existCards, PCI_INFO *pciInfo)
C/C++ (Windows 95)
U16 W_7396_Initial (U16 *existCards, PCI_INFO *pciInfo)
Visual Basic (Windows 95)
W_7396_Initial (existCards As Integer, pciInfo As PCI_INFO) As Integer
```

# @ Argument

```txt
existCards: The numbers of installed PCI-7396 cards. The returned value shows how many PCI-7396 cards are installed in your system.
```

```txt
pciinfo: It is a structure to memorize the PCI bus plug and play initialization information which is decided by P&P BIOS. The PCI_INFO structure is defined in ACL_PCI.H. The base I/O address and the interrupt channel number is stored in this variable.
```

# @ Return Code

```txt
ERR_NoError
ERR_PCIBiosNotExist
```

# 5.4 \_7396\_DI

# @ Description

This function is used to read the 24-bit digital inputs data from the input port of the PCI-7396.The written data and read in data is 24 bits data. Each data is mapped to a signal as the table below.

<table><tr><td>D7</td><td>D6</td><td>D5</td><td>D4</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td>PA7</td><td>PA6</td><td>PA5</td><td>PA4</td><td>PA3</td><td>PA2</td><td>PA1</td><td>PA0</td></tr><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>D11</td><td>D10</td><td>D9</td><td>D8</td></tr><tr><td>PB7</td><td>PB6</td><td>PB5</td><td>PB4</td><td>PB3</td><td>PB2</td><td>PB1</td><td>PB0</td></tr><tr><td>D23</td><td>D22</td><td>D21</td><td>D20</td><td>D19</td><td>D18</td><td>D17</td><td>D16</td></tr><tr><td>PC7</td><td>PC6</td><td>PC5</td><td>PC4</td><td>PC3</td><td>PC2</td><td>PC1</td><td>PC0</td></tr></table>

# @ Syntax

```csv
C/C++ (DOS)
U16 _7396_DI (U16 cardNo, U16 channelPort, U32 *diData)
C/C++ (Windows 95)
U16 W_7396_DI (U16 cardNo, U16 channelPort, U32 *diData)
Visual Basic (Windows 95)
W_7396_DI (ByVal cardNo As Integer, ByVal channelPort As Integer, diData As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI7396 card initialized.
channelPort: port of each channel
P1_A : CH1's Port A
P1_B : CH1's Port B
P1_C : CH1's Port C
P1_ABC: CH1's Port A, Port B, Port C
P2_A : CH2's Port A
P2_B : CH2's Port B
P2_C : CH2's Port C
P2_ABC: CH2's Port A, Port B, Port C

(The following items are for PCI-7396 only.)
P3_A : CH3's Port A
P3_B : CH3's Port B
P3_C : CH3's Port C
P3_ABC: CH3's Port A, Port B, Port C
P4_A : CH4's Port A
P4_B : CH4's Port B
P4_C : CH4's Port C
P4_ABC: CH4's Port A, Port B, Port C
diData: returned 24-bit value from digital port.
```

@ Return Code

ERR\_NoError

# 5.5 \_7396\_DO

# @ Description

This function is used to write data to digital output ports. There are 6 ports (P1A, P1B, P1C, P2A, P2B, P2C) could be configured as digital outputs on the PCI-7348. And there are totally 12 digital output ports (P1A, P1B, P1C, P2A, P2B, P2C, P3A, P3B, P3C, P4A, P4B, P4C) could be configured as digital outputs on the PCI-7396.

# @ Syntax

```csv
C/C++ (DOS)
U16 _7396_DO (U16 cardNo, U16 channelPort, U32 doData)
C/C++ (Windows 95)
U16 W_7396_DO (U16 cardNo, U16 channelPort, U32 doData)
Visual Basic (Windows 95)
W_7396_DO (ByVal cardNo As Integer, ByVal channelPort As Integer, ByVal doData As Integer) As Integer
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
channelPort: The same as the arguments in the previous section.
doData : value will be written to digital output port
```

# @ Return Code

ERR\_NoError

# 5.6 \_7396\_Config\_Port

# @ Description

This function is used to configure the Input or Ouput of each Port. Each I/O Port of PCI-7396 is either input or output, so it has to configure as input or output before I/O operations are applied.

# @ Syntax

```txt
C/C++ (DOS)
U16 _7396_Config_Port (U16 cardNo, int ctrlValue)
C/C++ (Windows 95)
U16 W_7396_Config_Port (U16 cardNo, int ctrlValue)
Visual Basic (Windows 95)
W_7396_Config_Port (ByVal cardNo As Integer, ByVal channelPort As Integer, ByVal direction As Integer) As Integer
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
ctrlValue :
P1ARD : CH1's Port A input port
P1BRD : CH1's Port B input port
P1CRD : CH1's Port C input port
P1RD : CH1's Port A,B,C input port
E_P1RD : CH1's Port A,B,C input port use external clock to latch data
P1AWR : CH1's Port A output port
P1BWR : CH1's Port B output port
P1CWR : CH1's Port C output port
P1WR : CH1's Port A,B,C output port
P2ARD : CH2's Port A input port
P2BRD : CH2's Port B input port
P2CRD : CH2's Port C input port
P2RD : CH2's Port A,B,C input port
E_P2RD : CH2's Port A,B,C input port use external clock to latch data
P2AWR : CH2's Port A output port
P2BWR : CH2's Port B output port
P2CWR : CH2's Port C output port
P2WR : CH2's Port A,B,C output port
P3ARD : CH3's Port A input port
P3BRD : CH3's Port B input port
P3CRD : CH3's Port C input port
P3RD : CH3's Port A,B,C input port
E_P3RD : CH3's Port A,B,C input port use external clock to latch data
P3AWR : CH3's Port A output port
P3BWR : CH3's Port B output port
```

```csv
P3CWR : CH3's Port C output port
P3WR : CH3's Port A,B,C output port

P4ARD : CH4's Port A input port
P4BRD : CH4's Port B input port
P4CRD : CH4's Port C input port
P4RD : CH4's Port A,B,C input port
E_P4RD : CH4's Port A,B,C input port use external clock to latch data
P4AWR : CH4's Port A output port
P4BWR : CH4's Port B output port
P4CWR : CH4's Port C output port
P4WR : CH4's Port A,B,C output port
```

@ Return Code

ERR\_NoError

# 5.7 \_7396\_Software\_Reset

# @ Description

This function is used to reset the I/O port configuration. After resetting PCI-7396, all ports will be set as input ones. Note that this function will not re-start the PCI bus and all the hardware settings will not be changed, neither.

# @ Syntax

```txt
C/C++ (DOS)
U16 _7396_Software_Reset (U16 cardNo)
C/C++ (DOS, Windows 95)
U16 W_7396_Software_Reset (U16 cardNo)
Visual Basic (Windows 95)
W_7396_Software_Reset (ByVal cardNo As Integer) As Integer
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.8 \_7396\_INT\_Source\_Control

# @ Description

The PCI-7396 has dual interrupts system, two interrupt sources can be generated and be checked by software. This function is used to select and control PCI-7396’s interrupt sources by writing associated data to interrupt control register.

# @ Syntax

```c
C/C++ (DOS)
void _7396_INT_Source_Control (U16 cardNo, U16 c1, U16 c2)
C/C++ (Windows 95)
void W_7396_INT_Source_Control (U16 cardNo, U16 c1, U16 c2)
Visual Basic (Windows 95)
W_7396_INT_Source_Control (ByVal cardNo As Integer, ByVal c1 As Integer, ByVal c2 As Integer)
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
c1 : INT1# interrupt source
c2 : INT2# interrupt source
For the C1,C2 settings, please refer to Table3.3.1
```

# @ Return Code

ERR\_NoError

# 5.9 \_7396\_COSIRQ\_Control

# @ Description

This function is used to programe every channel port A,B,C‘s COS is enable or disable.

# @ Syntax

```c
C/C++ (DOS)
void _7396_COSIRQ_Control (U16 cardNo, int ch_no, int A, Int B, int C)
C/C++ (Windows 95)
void W_7396_COSIRQ_Control (U16 cardNo, int ch_no, int A, Int B, int C)
Visual Basic (Windows 95)
W_7396_COSIRQ_Control (ByVal cardNo As Integer, ByVal ch_no As Integer, ByVal A As Integer, ByVal B As Integer, ByVal C As Integer)
```

# @ Argument

```txt
cardNo: The card number of PCI7396 card initialized.
ch_no : channel number set 1 or 2 or 3 or 4
A: port A control (enable set 1, disable set 0)
B: port B control (enable set 1, disable set 0)
C: port C control (enable set 1, disable set 0)
```

# @ Return Code

ERR\_NoError

# 5.10 \_7396\_CLR\_IRQ

# @ Description

This function is used to clear the interrupt request of PCI-7396.

# @ Syntax

```c
C/C++ (DOS)
void _7396_CLR_IRQ (U16 cardNo)
C/C++ (Windows 95)
void W_7396_CLR_IRQ (U16 cardNo)
Visual Basic(Windows 95)
W_7396_CLR_IRQ (ByVal cardNo As Integer)
```

# @ Argument

cardNo :The card number of PCI7396 card initialized.

# @ Return Code

None

# 5.11 \_7396\_Set\_Event\_Edge

# @ Description

This function is used to set the edge trigger of event signal (Pin51) and external trigger signal (Pin99). The following table shows the possible settings.

<table><tr><td>Set_Event_Edge C0</td><td>0</td><td>1</td></tr><tr><td>External Trigger (Pin99)</td><td>Active Low</td><td>Active High</td></tr><tr><td>Event (Pin51)</td><td>Rising Edge Count</td><td>Falling Edge Count</td></tr></table>

# @ Syntax

```c
C/C++ (DOS)
U16 _7396_Set_Event_Edge (U16 cardNo, U16 *c0)
C/C++ (Windows 95)
U16 W_7396_Set_Event_Edge (U16 cardNo, U16 *c0)
Visual Basic (Windows 95)
W_7396_Set_Event_Edge (ByVal cardNo As Integer, c0 As Integer)
As Integer
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
c0: The event signal and external clock signal setting.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.12 \_7396\_Cascaded\_Timer

# @ Description

The function is used to program the timer#1 & timer#2 of 8254, the 32bit timer, to generate the timer interrupt .

# @ Syntax

```txt
C/C++ (DOS)
U16 _7396_Cascaded_Timer (U16 *existCards, U16 c1, U16 c2)
C/C++ (Windows 95)
U16 W_7396_Cascaded_Timer (U16 *existCards, U16 c1, U16 c2)
Visual Basic (Windows 95)
W_7396_Initial (existCards As Integer, ByVal c1 As Integer, ByVal c2 As Integer)
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
c1 : frequency divider of timer #1
c2 : frequency divider of timer #2
About the settings of C1 & C2, please refer to section 3.2.2
```

# @ Return Code

```txt
ERR_NoError
ERR_PCIBiosNotExist
```

# 5.13 \_7396\_Timer\_Start

# @ Description

The function is used to program the timer#0 of 8254, 16bit timer, to generate the event interrupt .

# @ Syntax

```c
C/C++ (DOS, Windows 95)
U16 _7396_Timer_Start (U16 *existCards, U16 timer_mode, U16 c0)
C/C++ (DOS, Windows 95)
U16 W_7396_Timer_Start (U16 *existCards, U16 timer_mode, U16 c0)
Visual Basic (Windows 95)
W_7396_Initial (existCards As Integer, ByVal timer_mode As Integer, ByVal c0 As Integer)
```

# @ Argument

```txt
cardNo: The card number of PCI7396 card initialized.
timer_mode: 8254 operating mode
c0: frequency divider of timer #0
```

# @ Return Code

```txt
ERR_NoError
ERR_PCIBiosNotExist
```

# 5.14 \_7396\_Timer\_Read

# @ Description

This function is used to read the counter value of the Counter#0.

# @ Syntax

```txt
C/C++ (DOS)
U16 _7396_Timer_Read (U16 cardNo, U16 *c0)
C/C++ (Windows 95)
U16 W_7396_Timer_Read (U16 cardNo, U16 *c0)
Visual Basic (Windows 95)
W_7396_Timer_Read (ByVal cardNo As Integer, c0 As Integer) As Integer
```

# @ Argument

```txt
cardNo : The card number of PCI7396 card initialized.
c0: count value of counter#0
```

# @ Return Code

```txt
ERR_NoError
```

# Appendix 1 DIN-96DI

# A1.1 Introductions

DIN-96DI digital input termination board features high-voltage opto-isolation on all inputs to prevent floating potential and ground loop problems from damaging your PC system. It is composed of one TB-96 base board, one TB-96DI daughter board, and one DIN socket for easy maintenance, wiring, and installation. It provides 96 channels that are accessed through a SCSI-100 connector.

# A1.2 Features

u 96 Opto-Isolated digital input channels
u For use with the PCI-7396
u AC or DC polarity-free digital input
u Screw terminals for easy field wiring

# A1.3 Specifications

u Numbers of channel: 96
u Opto-isolator: PC3H4
u Input impedance: 4.7K Ohms
u Input voltage range: 0\~24VDC
u Threshold voltage:
w 20VDC for 24V PS
w 8.8VDC for 12V PS
w 1.8VDC for 5V PS

u Isolation voltage: 2,500 Vdc channel-to-ground

u Connector: 100-Pin SCSI-type connector

u Dimensions: 112.7 mm x 225.0 mm

u Operating temp.: 0° \~ 60°C

u Storage temp.: -20° \~ 80°C

u Humidity: 5\~95%, non-condensing

u Power consumption:

w 490mA(max.) for 24V PS
w 250mA(max.) for 12V PS
w 102mA(max.) for 5V PS

A1.4 Layout of DIN-96DI
![49 50 51 52\n94 95 96 G G\nTB96\n4 X\n3 X\nTB-96DI\nX →\n2 X\nCN1\nG 5 48 47 46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\nG P 6 P 6 P\nP 6 P 6 P\n5 4 3 2 1](.pci-7348-7396-manual-3-en/ff0030f66886436d92285cdb81558cd7508322dd5e85396a58d152f531872804.jpg)

Legend:

CN1 : SCSI II 100 pin connector to connect PCI-7396 and DIN-96DI

X1\~X4: 50 pin Opto-22 connectors to connect TB96 and Tb96DI

n(1\~96): Input signal n

G: External ground

P: External power (5\~24V)

# A1.5 DI Circuits and Wiring

The outputs of the opto-isolated digital input circuits are open collector transistors. PCI-7396 should provide pull-high resistors by correct jumper setting. The connection between outside signal and PCI-7396 as well as the jumper setting are shown below.

![Power 24V\n2.4K Ohm\nInput\nPCI-7396\nDIn](.pci-7348-7396-manual-3-en/8b3c24304f99b8cce10a676b7738a6f2c8c0e3b886438168c7a51c37dc3e830a.jpg)

Figure A1.1: opto-isolated input circuit

![PCI-7396\nDIn\nTTL Device\nJPxx\nVcc\nGND](.pci-7348-7396-manual-3-en/351411934981ea479add9cfee8876084b57fba8b9f242d5baea4eb6d18d45883.jpg)

Figure A1.2: PCI-7396 jumper setting for DIN-96DI

# Appendix 2 DIN-96DO

# A2.1 Introductions

DIN-96DO digital output termination board features high-voltage optoisolation on all outputs to prevent floating potential and ground loop problems from damaging your PC system. It is composed of one TB-96 base board, one TB-96DO daughter board, and one DIN socket for easy maintenance, wiring, and installation. It provides 96 channels that are accessed through a SCSI-100 connector.

# A2.2 Features

u 96 Opto-Isolated digital output channels
u For use with the PCI-7396
u On-board relay driver circuitry
u Screw terminals for easy field wiring

# A2.3 Specifications

u Numbers of channel: 96
u Opto-isolator: PC3H7
u Output type: Darlingtoin transistors, open collector up to 35Vdc
u Sink current:

w 350mA max.@ 100% duty, one of transistors device ON
w 370mA @ duty 10% for all transistors devices ON
w 140mA @ duty 50% for all transistors devices ON
w 60mA @ duty 100% for all transistors devices ON

u Isolation voltage: 2500 Vrms
u Dimensions: 112.7 mm x 225.0 mm
u Operating temp.: $0 ^ { \circ } \sim 6 0 ^ { \circ } \mathrm { C }$
u Storage temp.: $\cdot 2 0 ^ { \circ } \sim 8 0 ^ { \circ } { \mathsf C }$
u Humidity: 5\~95%, non-condensing
u Power consumption:

w 4.294A(max.) for 24VPS
w 4.244A(max.) for 12VPS
w 4.215A(max.) for 12VPS
w 102mA(max.) from cable

A2.4 Layout of DIN-96DO
![49 50 51 52\n49 50 51 52\n4 94 95 96 G G\nTB96\nTB-96DO\n3 X\nX\nX\n2 X\nCN1\nG G 48 47 46\n5 43 2 1](.pci-7348-7396-manual-3-en/2965f04389af577adee7826f75e1861a0f9c742d7f5afc93f0a69a1e88f1ddd6.jpg)

Legend:

CN1 : SCSI II 100 pin connector to connect PCI-7396 and DIN-96DO

X1\~X4: 50 pin Opto-22 connectors to connect TB96 and Tb96DO

n(1\~96): Output signal n

G: External ground

P: External power (5\~24V)

# A2.5 Circuits and Wiring

The connection of isolated digital output is shown as the following diagram. The DIN-96DO need external 5\~24V DC power from the POWER pin to provide the power source of the digital output circuit. The POWER pin is used as “fly-wheel” diode, which can protect the driver if the loading is inductance loading such as relay, motor or solenoid. If the loading is resistance loading such as resistor or LED, the connection to fly-wheel diode is not necessary.

Therefore, the first step for connecting the output with external device is to distinguish the type of loading. For example, if the loading is LED or resistor, you can use the following wiring diagram.

![Power\nResistive\nLoading\nGND\nVDD\n5-24V](.pci-7348-7396-manual-3-en/77cd5d20a000b825c4b4d2cbda08751a2fc37cd05c31d1200a77131bbf3c96c9.jpg)

Figure A2.1: opto-isolated output circuit for resistance loading

If the loading is a inductance loading such as relay, you can use the following wiring diagram. The POWER must connect to the external power to form a fly-wheel current loop.

![Power\nInductance\nLoading\nVDD\n5-24V\nGND](.pci-7348-7396-manual-3-en/a724677d1835090e49ae1f6f8a85efdda7247798e3e7c6963c79a5a10530f668.jpg)

Figure A2.2: opto-isolated output circuit for inductance loading

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK’s products, please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form.
2. All ADLINK products come with a two-year guarantee,free of repair charge.

The warranty period starts from the product’s shipment date from ADLINK’s factory
Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers’ warranty
End users requiring maintenance services should contact their local dealers. Local warranty conditions will depend on the local dealers3.Our repair service does not cover two-year guarantee while damages are caused by the following:

a. Damage caused by not following instructions on user menus.
b. Damage caused by carelessness on the users’ part during product transportation.
c. Damage caused by fire, earthquakes, floods, lightening, pollution and incorrect usage of voltage transformers.
d. Damage caused by unsuitable storage environments with high temperatures, high humidity or volatile chemicals.
e. Damage caused by leakage of battery fluid when changing batteries.
f. Damages from improper repair by unauthorized technicians.
g. Products with altered and damaged serial numbers are not entitled to our service.
h. Other categories not protected under our guarantees.4. Customers are responsible for the fees regarding transportation of damaged products to our company or to the sales office.

5. To ensure the speed and quality of product repair, please download an RMA application form from our company website www.adlinktech.com. Damaged products with RMA forms attached receive priority.

For further questions, please contact our FAE staff.

ADLINK: service@adlinktech.com

Test & Measurement Product Segment: NuDAQ@adlinktech.com

Automation Product Segment: Automation@adlinktech.com

Computer & Communication Product Segment: NuPRO@adlinktech.com ; NuIPC@adlinktech.com
[🔗 Link to the original document](.pci-7348-7396-manual-3-en/pci-7348-7396-manual-3-en.pdf)