# PCI-8246

Dual Gigabit Ethernet Ports

PCI-X Card with Bypass Capability

User’s Guide ©Copyright 2004 ADLINK Technology Inc. All Rights Reserved.

Manual Rev. 1.00 October 11, 2004

Part No: 50-15032-100

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright laws. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

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All product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

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# Table of Contents

# Chapter 1 Introduction .........

1.1 Block Diagram .... 1
1.2 Features... .2
1.3 Specifications.... 2
1.4 Communication States.... .4
1.5 WDT and Bypass Control Logic . .5

# Chapter 2 Connectors and Hardware Settings ...........7

2.1 Card Panel...
2.2 Gigabit Ethernet Connectors .... .. 8
2.3 Control Switch and Header.. ..8
2.4 PXE Boot Flash Enable Jumper.... ..9
2.5 Status LED Control Header ..... ..10

# Chapter 3 Programming Information .........................11

3.1 SDP Register .. .11
3.2 Bypass Control Priority .. .13
3.3 DOS Utilities for Evaluation - Utilities List... ..14
3.4 WDT Library Installation for Windows 2000 and XP ...........15
3.5 Function Reference of WDT Library........ ..18

# Chapter 4 GbE Driver Installation ....... .23

# Warranty Policy ......... ...25

# How to use this guide

This manual is designed to assist the user in using the PCI-8246 series modules.

The contents are as follows:

# Chapter 1 Introduction

Overview of product features and specifications.

# Chapter 2 Getting Started on Hardware

Describes the unpacking procedures and illustrates the connector pin assignments.

# Chapter 3 Getting Started on Software Programming

Programming information.

# Chapter 4 Driver Installation

Describes the driver installation.

![1](.pci-8246-manual-4/322f004a728aca8034c4d5fdf7254e33479abf1538ef697cd2799bd113a10e19.jpg)

# Introduction

PCI-8246 is a high performance 2-port Gigabit Ethernet (GbE) PCI-X card providing bypass capability, which can connect GbE signals on the two GbE connectors while the system is powered down or under software halt.

# 1.1 Block Diagram

![**Labeled Blocks:**\n\n*   **PCI-X Bus**\n*   **82546EB Dual GbE** (containing the label **SDP (GPIO)** at the bottom)\n*   **Transformer** (appears twice)\n*   **Relay Array**\n*   **RJ-45** (appears twice)\n*   **GbE #1**\n*   **GbE #2**\n*   **WDT & Bypass Control Logic Circuit**\n*   **Relay Drivers**\n*   **Status Feedback**\n*   **LED Status**\n*   **Onboard header**\n*   **Onboard Switch** (labeled **1 2** and **ON**)\n\n**Connections:**\n\n*   **PCI-X Bus** connects bidirectionally to **82546EB Dual GbE**.\n*   **82546EB Dual GbE** connects bidirectionally to two **Transformer** blocks.\n*   **Transformer** blocks connect bidirectionally to **Relay Array**.\n*   **Relay Array** connects bidirectionally to two **RJ-45** blocks.\n*   **RJ-45** blocks connect bidirectionally to **GbE #1** and **GbE #2**.\n*   **WDT & Bypass Control Logic Circuit** sends **Status Feedback** (indicated by a thick arrow) to **SDP (GPIO)** at the bottom of the **82546EB Dual GbE** block.\n*   **WDT & Bypass Control Logic Circuit** connects to **Relay Drivers**, which then connects to the **Relay Array**.\n*   **WDT & Bypass Control Logic Circuit** connects to **LED Status** (arrow pointing left).\n*   **WDT & Bypass Control Logic Circuit** connects to **Onboard header** (arrow pointing up).\n*   **WDT & Bypass Control Logic Circuit** connects to **Onboard Switch** (arrow pointing up).](.pci-8246-manual-4/f27bcc44655a1728c4997956f286d5a0c0a490c95f2b6da7790189cb194867aa.jpg)

Figure 1: Block Diagram

The PCI-8246 is based on the Intel® 82546EB dual port Gigabit Ethernet controller. The Intel® 82546EB is a highly integrated chip, includes Ethernet

MAC, PHY, and provides PCI-X 133 capability. Please refer to the Intel® 82546EB datasheet for more information on the GbE ports.

The PCI-8246’s bypass capability uses a mechanical relay array to control the physical routing of the GbE signals. There are two communications states for the GbE signal routing: 1) Normal State, 2) Bypass State. Please refer to section 1.4 for block diagrams of the two states.

watchdog timer (WDT) and bypass control logic circuits are used to control the relay and communication states. The programmer can control those functions via the Software Definable Pins (SDP) on the Intel® 82546EB by programming its registers. Please refer to section 1.5 for a block diagram of the bypass control circuits.

# 1.2 Features

Dual Gigabit Ethernet Ports
Supports up to PCI-X 133Mhz
Bypass capability during system power-off or software halt
Software programmable bypass control
• Programmable watchdog timer, WDT status read-back
• Intel Boot Agent BIOS
• Low-profile bracket available for OEM requirements

# 1.3 Specifications

# • PCI bus architecture

Bus Type: PCI/PCI-X
• Bus Width: 32- or 64-bit
Bus Speed: 33/66/100/133 MHz
Interrupt Level: INTA
Data Transfer Mode: Bus-master DMA
PCI Voltage: 3.3V or 5V universal

# • Ethernet Controller

• Intel® 82546 Gigabit Ethernet Controller, Dual GbE ports
Data rates supported (per port): 10,100,1000Mbps
IEEE Standard/Network Topology: 10BASE-T, 100BASE-TX, 1000BASE-T
IEEE 802.3ab compliant

# • Ethernet Ports

• Connector: Two RJ-45
Wiring: Cat-5, 4-pair
Cable Distance: 100 meters (normal mode) or 40 meters (bypass mode)

# • Bypass Capability and Watchdog Timer

• A relay array controls signal routing of the two GbE ports
• Normal State: GbE signals are straight-through to GbE controller
Bypass State: GbE signals are connected to another port and bypass the GbE controller
Power off status is Bypass State
Programmable watchdog timer (WDT) can switch relay array to Bypass State during a software halt
WDT time out value is programmable as 1, 2, 4, or 8 seconds by DIP switch or by software programmable

# Ethernet LED

• Two LED on each RJ-45 connector
• For each port, two LED for 1000Mbps indication and Link / Active
• LED header reserved for custom chassis front panel LED connection

# • Boot ROM Feature

• LAN Boot ROM: 128KB onboard
Support INTEL® Preboot Execution Environment (PXE) for remote boot

# • OS Support:

• Microsoft® Windows® Server 2003 and 2000
• Microsoft® Windows® XP 32- and 64-bit Editions
Windows® NT 4.0
• Linux 2.4.x or later
FreeBSD 4.x or later
• Novell NetWare® 4.11, 4.2, 5.0, 5.1, 6.0
• UnixWare® 7.x and OpenUNIX 8 (ddi8), SCO5\*

# • Network Management

Intel® Boot Agent
ACPI Power Management
• PXE 2.0 (Network Management does not support Wake on LAN)

# • Compliant Standards

CE Certification:
EMI Test: European Standard EN 55022 Class B
ƒ Harmonic Test: European Standard EN 61 000-3-2
Voltage fluctuations Test: European Standard EN 61 000-3-3
ƒ EMS Test: European Standard EN 50 082-1:1997
• FCC Approval: Standard for Methods of Measurement
ƒ ANSI C63.4 – 1992
Compliance with CISPR PUB. 22 and FCC Part 15

# • Environment

Operating Temperature: 0 to $5 5 ^ { \circ } \mathsf { C }$
Storage Temperature: -20 to $8 0 ^ { \circ } \mathsf { C }$
Humidity: 10% to 90% non condensing

# • Dimensions

• PCI half-sized, low profile card
174.63 mm x 64.41 mm (L x W)
Height of Full-height Panel Bracket: 12.1cm (4.75in)

# 1.4 Communication States

The following diagram illustrates the Normal State: where the two GbE signals are straight-through connected to the GbE ports via the transformers. The two GbE ports work independently as normal dual GbE ports.

![The diagram depicts a bidirectional data flow from left to right involving the following labeled blocks and connections:\n\n**Blocks:**\n*   **PCI-X Bus**\n*   **82546EB Dual GbE**\n*   **Trans-former** (appears twice, once with a blue border and once with a red border)\n*   **Relay Array**\n*   **RJ-45** (appears twice, once with a blue border and once with a red border)\n*   **GbE #1**\n*   **GbE #2**\n\n**Connections:**\n1.  **PCI-X Bus** is connected via a double-headed black arrow to **82546EB Dual GbE**.\n2.  **82546EB Dual GbE** splits into two paths:\n    *   A blue path connects to the top **Trans-former** via a double-headed blue arrow.\n    *   A red path connects to the bottom **Trans-former** via a double-headed red arrow.\n3.  Both **Trans-former** blocks connect to the **Relay Array** (double-headed blue and red arrows respectively). Inside the Relay Array, a curved grey arrow indicates a switching mechanism, and dotted lines show internal path connections.\n4.  From the **Relay Array**:\n    *   The blue path connects to the top **RJ-45** block via a double-headed blue arrow.\n    *   The red path connects to the bottom **RJ-45** block via a double-headed red arrow.\n5.  Finally, the **RJ-45** blocks connect to the external labels:\n    *   The top **RJ-45** connects to **GbE #1** via a double-headed blue arrow.\n    *   The bottom **RJ-45** connects to **GbE #2** via a double-headed red arrow.](.pci-8246-manual-4/10eaa464936ac3cb0ca7bf827daada361f7de05821b419819c2eaa662a023f87.jpg)

Figure 2: Communication States: Normal

The following diagram shows the Bypass State: where the two GbE signal are cross-over connected to each other so that the Ethernet connection

# 4 • Introduction

bypasses the computer or the network appliance where this PCI card is installed in.

![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n*   **PCI-X Bus**\n*   **82546EB Dual GbE**\n*   **Transformer** (two instances, stacked vertically)\n*   **Relay Array**\n*   **RJ-45** (two instances, stacked vertically)\n*   **GbE #1**\n*   **GbE #2**\n\n**Connections:**\n1.  A double-headed black arrow connects the **PCI-X Bus** to the **82546EB Dual GbE** block.\n2.  Dotted lines connect the right side of the **82546EB Dual GbE** block to the two **Transformer** blocks (one line to the top transformer, one to the bottom).\n3.  Dotted lines connect the two **Transformer** blocks to the left side of the **Relay Array** block.\n4.  Inside the **Relay Array**, blue arrows indicate signal switching between the input and output lines.\n5.  Blue arrows connect the right side of the **Relay Array** to the two **RJ-45** blocks (bidirectional arrows).\n6.  A double-headed black arrow connects the top **RJ-45** block to the text **GbE #1**.\n7.  A double-headed black arrow connects the bottom **RJ-45** block to the text **GbE #2**.](.pci-8246-manual-4/61d9cfdeaffeaece71552faf50d8396e8452b1362ca41192651d680fb306823c.jpg)

Figure 3: Communication States: Bypass

The relay array is driven by the relay divers which are controlled by the watchdog timer and bypass control logic circuits.

# 1.5 WDT and Bypass Control Logic

The block diagram of the WDT and bypass control logic circuits is as follows:

![**Labeled Blocks:**\n*   **82546EB**: Contains internal labels SPDB6, SPDB(0:1), SPDA7, SPDA0, SPDA1, SPDA6, and SPDA7.\n*   **WDT**\n*   **Bypass Control Logic**\n*   **Control Relay Array** (Output destination)\n*   **Switches**: Includes a block labeled 1, 2, ON with connections WDT_VS0 and WDT_VS1. Includes a switch block with connections PONSTS, BYPASS, NORMAL, and WDT_DIS.\n\n**Connections:**\n*   **82546EB** sends **Bypass State feedback** to **Bypass Control Logic**.\n*   **Bypass Control Logic** sends **MODE(0:1)** and **PCI_RESET** to **82546EB**.\n*   **82546EB** sends **WDT_EN**, **WDT_RL**, **WDT_VP0**, and **WDT_VP1** to **WDT**.\n*   **WDT** sends **Time Out status feedback** to **82546EB**.\n*   **WDT** sends **WDT Time Out** to **Bypass Control Logic**.\n*   **CLK** input connects to **WDT**.\n*   **WDT_VS0** and **WDT_VS1** inputs connect to **WDT**.\n*   **PONSTS**, **BYPASS**, **NORMAL**, and **WDT_DIS** inputs connect to **Bypass Control Logic**.\n*   **Bypass Control Logic** outputs to **Control Relay Array**.](.pci-8246-manual-4/46b4b9abf54ec3251fa1c9d67dc5ddec04b2771cb0ae882d82375e6d67872713.jpg)

Figure 4: WDT and Bypass Control Logic

Please refer to chapter 2 for switch and jumper setting definition; chapter 3 for programming information including the WDT control.

# 2

# Connectors and Hardware Settings

# 2.1 Card Panel

![Bypass Status LED (green)\nWDT LED (yellow)\nGbE Port #2\nGbE Port #1](.pci-8246-manual-4/a23528c2866d5aa4344a74ee1fcdc40f3ec5c17c44b5c39328afb96a60c5417a.jpg)

Figure 5: Card Panel

# 2.2 Gigabit Ethernet Connectors

![LED 2\nPin 1\nPin 2\nPin 3\nPin 6\nLED 1](.pci-8246-manual-4/446dc0c78d2b2b415bb96f8f27c20aff466cbc58959c1475637f6a91f0cb3dfb.jpg)

<table><tr><td>PIN</td><td>LAN1 SIGNAL</td><td>LAN2 SIGNAL</td><td>FUNCTION</td></tr><tr><td>1</td><td>LAN1_TDP1</td><td>LAN2_TDP1</td><td>Transmit Data1 +</td></tr><tr><td>2</td><td>LAN1_TDN1</td><td>LAN2_TDN1</td><td>Transmit Data1 -</td></tr><tr><td>3</td><td>LAN1_RDP2</td><td>LAN2_RDP2</td><td>Receive Data2 +</td></tr><tr><td>4</td><td>LAN1_RDP3</td><td>LAN2_RDP3</td><td>Receive Data3 +</td></tr><tr><td>5</td><td>LAN1_RDN3</td><td>LAN2_RDN3</td><td>Receive Data3 -</td></tr><tr><td>6</td><td>LAN1_RDN2</td><td>LAN2_RDN2</td><td>Receive Data2 +</td></tr><tr><td>7</td><td>LAN1_TDP4</td><td>LAN2_TDP4</td><td>Transmit Data4 +</td></tr><tr><td>8</td><td>LAN1_TDN4</td><td>LAN2_TDN4</td><td>Transmit Data4 -</td></tr></table>

LED Definitions for LAN1/LAN2 (CN3/CN4)

<table><tr><td colspan="2">Status</td><td>LED 1</td><td>LED 2</td></tr><tr><td colspan="2">Network link is not established</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps(10 BaseT)</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps(100 BaseTX)</td><td>Link</td><td>ON</td><td>OFF</td></tr><tr><td>Active</td><td>Blinking</td><td>OFF</td></tr><tr><td rowspan="2">1000 Mbps(1000 BaseT)</td><td>Link</td><td>Blinking</td><td>ON</td></tr><tr><td>Active</td><td>Blinking</td><td>Blinking</td></tr></table>

# 2.3 Control Switch and Header

# Control Switch SW2

![The image displays a schematic symbol labeled 'SW2' at the top. Below the label is a rectangular box containing the following elements arranged horizontally:\n- On the left, the numbers '1' and '2' are stacked vertically.\n- In the center, there are two square symbols stacked vertically, each containing a smaller grid-like pattern inside.\n- On the right, the word 'ON' is written vertically.](.pci-8246-manual-4/4f59189e6e1a4e75f30d89adc550233c8537b090cd4a1b678fb29f9626135e67.jpg)

<table><tr><td>Position</td><td>Name</td><td>Description(* Factory default setting)</td></tr><tr><td>SW2-1</td><td>WDT_VS0</td><td>WDT time out value bit 0</td></tr><tr><td>SW2-2</td><td>WDT_VS1</td><td>WDT time out value bit 1</td></tr></table>

<table><tr><td>WDT_VS1</td><td>WDT_VS0</td><td>WDT time out value</td></tr><tr><td>OFF*</td><td>OFF*</td><td>8 second</td></tr><tr><td>OFF</td><td>ON</td><td>4 seconds</td></tr><tr><td>ON</td><td>OFF</td><td>2 seconds</td></tr><tr><td>ON</td><td>ON</td><td>1 seconds</td></tr></table>

The WDT\_VS0/1 switches are used to set the WDT time out value. Please note that the user can also use software to control the WDT value. Please refer to Chapter 3 for detail programmable WDT setting.

# Control Header

The Control Header (CN1) is used to enforce Normal and Bypass states as shown below.

<table><tr><td rowspan="5">CN1</td><td>Jumper</td><td>Name</td><td>Description (* Factory default setting)</td></tr><tr><td>1-5</td><td>PONSTS</td><td>Closed: Power-on Normal StateOpen: Power-on Bypass State*</td></tr><tr><td>2-6</td><td>BYPASS</td><td>Closed: Force relay array to Bypass StateOpen: No enforcement*</td></tr><tr><td>3-7</td><td>NORMAL</td><td>Closed: Force relay array to Normal StateOpen: No enforcement*</td></tr><tr><td>4-8</td><td>WDT_DIS</td><td>Closed: Force WDT disableOpen: No enforcement*</td></tr></table>

# Enforcement Priority

The Control Header has priority over all software enforcement. Please refer to sections 3.1 and 3.2 for further information on priority.

# 2.4 PXE Boot Flash Enable Jumper

The PCI-8246 supports remote boot via the PREBOOT EXECUTION ENVIRONMENT (PXE) function by installing a boot ROM. The boot ROM is installed but disabled by default.

JP1: Boot Flash Enable & Disable setting

<table><tr><td>Description</td><td>Disable BOOT Flash</td><td>Enable BOOT Flash</td></tr><tr><td>JP1</td><td>1 – 2 (*)</td><td>2 – 3</td></tr></table>

\*: Factory Default Setting

# 2.5 Status LED Signal Header

The status LED signal header CN2 collects six status signals so that the system integrator can power additional LEDs that can be installed elsewhere on the chassis. The onboard LED driving circuit can sink up to 10mA current for each signal.

CN2
![(Pin1) +3.3V\nLAN2 LED2\nLAN1 LED2\nReserved\nGround\nReserved\nLAN2 LED1\nLAN1 LED1\nReserved\nGround\nBypass status\nWDT status](.pci-8246-manual-4/8ab76237dd4d17be8a0b71bad85333b5c15485575f8ad6b0029a770a23db3a8e.jpg)

Figure 6: Status LED Signal Header

<table><tr><td>Pins</td><td>Signal</td><td>Meaning</td></tr><tr><td rowspan="2">Bypass status</td><td>ON</td><td>Normal State</td></tr><tr><td>OFF</td><td>Bypass State or Power off</td></tr><tr><td rowspan="3">WDT status</td><td>ON</td><td>WDT time out</td></tr><tr><td>Blinking</td><td>WDT running (enabled)</td></tr><tr><td>OFF</td><td>WDT disable</td></tr></table>

<table><tr><td colspan="2">LAN1/LAN2 Status</td><td>LED1</td><td>LED2</td></tr><tr><td colspan="2">Network link is not established</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps(10 BaseT)</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps(100 BaseTX)</td><td>Link</td><td>ON</td><td>OFF</td></tr><tr><td>Active</td><td>Blinking</td><td>OFF</td></tr><tr><td rowspan="2">1000 Mbps(1000 BaseT)</td><td>Link</td><td>Blinking</td><td>ON</td></tr><tr><td>Active</td><td>Blinking</td><td>Blinking</td></tr></table>

# 3

# Programming Information

# 3.1 SDP Register

# Block Diagram and 82546EB

The following block diagram (identical to the one in Section 1.5) illustrates the bypass control signals. Programmers need to know how to access the 82546EB PCI controller and its Software Defined Pins (SDP). Please refer to the 82546EB programming document for detailed information.

![Based on the provided block diagram, here is the accurate description of the blocks and connections:\n\n**Blocks:**\n*   **82546EB** (Top Left)\n*   **WDT** (Center)\n*   **Bypass Control Logic** (Right)\n\n**Connections and Labels (Verbatim):**\n\n**1. 82546EB Block:**\n*   **Inputs/Outputs:**\n    *   **Bypass State feedback**: Arrow points from the right (originating from Bypass Control Logic) to the left, pointing to **SPDB6**.\n    *   **MODE(0:1)**: Arrow points from **SPDB(0:1)** to the right, towards **Bypass Control Logic**.\n    *   **PCI_RESET**: Arrow points from the left towards **Bypass Control Logic**.\n    *   **Time Out status feedback**: Arrow points from the right (originating from WDT) to the left, pointing to **SPDA7**.\n    *   **WDT_EN**: Arrow points from **SPDA7** to the right, into **WDT**.\n    *   **WDT_RL**: Arrow points from **SPDA0** to the right, into **WDT**.\n    *   **WDT_VP0**: Arrow points from **SPDA1** to the right, into **WDT**.\n    *   **WDT_VP1**: Arrow points from **SPDA6** to the right, into **WDT**.\n    *   **CLK**: Arrow points from the left into **WDT**.\n\n**2. WDT Block:**\n*   **Inputs:** **WDT_EN**, **WDT_RL**, **WDT_VP0**, **WDT_VP1**, **CLK**, **WDTV SEL** (from Bypass Control Logic).\n*   **Outputs:** **Time Out status feedback** (to 82546EB), **WDT Time Out** (to Bypass Control Logic).\n\n**3. Bypass Control Logic Block:**\n*   **Inputs:** **MODE(0:1)**, **PCI_RESET**, **WDT Time Out**, **PONSTS**, **BYPASS**, **NORMAL**, **WDT_DIS** (from bottom right pins).\n*   **Outputs:** **Bypass State feedback** (to 82546EB), **WDTV SEL** (to WDT), **Control Relay Array** (output to the right).\n\n**4. Bottom Right Section:**\n*   Pins labeled: **PONSTS**, **BYPASS**, **NORMAL**, **WDT_DIS**.\n*   Switch labels: **1 2**, **ON**.\n*   Arrows point from these pins/switches upwards into **Bypass Control Logic**.](.pci-8246-manual-4/3bbb01d38bb4cd0267f2a0ef2fe48a2f5dcdb4f6a3820094eaf57dbb6697bf31.jpg)

Figure 7: Block Diagram and 82546EB

# SDP Registers Definition

The bits in SDP registers are all readable and writable. The following table shows the register definition.

<table><tr><td>SPD Bit</td><td>Name</td><td>R/W</td><td>Description</td></tr><tr><td>SDPB0</td><td>MODE0</td><td>RW</td><td rowspan="2">Bypass control mode bit 0 and 1</td></tr><tr><td>SDPB1</td><td>MODE1</td><td>RW</td></tr><tr><td>SDPB6</td><td>Bypass Status</td><td>R</td><td>Bypass status read back0: Bypass1: Normal</td></tr><tr><td>SDPB7</td><td>WDT Status</td><td>R</td><td>WDT status read back0: WDT running or stop1: WDT Time Out</td></tr><tr><td>SDPA0</td><td>WDT_CTRL</td><td>RW</td><td>WDT control bit</td></tr><tr><td>SDPA1</td><td>WDT_RL</td><td>RW</td><td>Reload WDT to avoid timeout</td></tr><tr><td>SDPA6</td><td>WDT_VP0</td><td>RW</td><td rowspan="2">WDT time out value bit 0 and 1</td></tr><tr><td>SDPA7</td><td>WDT_VP1</td><td>RW</td></tr></table>

# WDT Enable

<table><tr><td>WDT_EN</td><td>Functions</td></tr><tr><td>0</td><td>WDT is disabled.</td></tr><tr><td>1</td><td>WDT is enabled.</td></tr></table>

Power On Default

# Bypass Control Mode

<table><tr><td>MODE0</td><td>MODE1</td><td>Functions</td></tr><tr><td>0</td><td>0</td><td>No enforcement. Set WDT reload from the switch setting WDT_VS[1:0]</td></tr><tr><td>0</td><td>1</td><td>No enforcement. Set WDT reload from the programmable WDT_VP[1:0]</td></tr><tr><td>1</td><td>0</td><td>Disable WDT, force relay array to Bypass State (1)</td></tr><tr><td>1</td><td>1</td><td>Disable WDT, force relay array to Normal State (2)</td></tr></table>

Power On Default

Note 1: If the relay array is forced to Normal State by jumper settings in the Control Header, then this setting is void (see Section 2.3).

Note 2: If the relay array is forced to Bypass State by jumper settings in the Control Header, then this setting is void (see Section 2.3).

# WDT Reload

<table><tr><td>WDT_RL</td><td>Functions</td></tr><tr><td>0 -&gt; 1 -&gt; 0</td><td>Reload WDT to avoid timeout</td></tr></table>

When WDT is reload, the circuit will load the WDT value from either WDT\_VP[1:0] or WDV\_VS[1:0] dependent on the control modes setting.

# WDT Time Out Value Setting

<table><tr><td>WDT_VP1</td><td>WDT_VP0</td><td>WDT time out value</td></tr><tr><td>0</td><td>0</td><td>1 second</td></tr><tr><td>0</td><td>1</td><td>2 seconds</td></tr><tr><td>1</td><td>0</td><td>4 seconds</td></tr><tr><td>1</td><td>1</td><td>8 seconds</td></tr></table>

Power On Default

# 3.2 Bypass Control Priority

The relay array is controlled by reset, WDT time out, bypass control mode bits, and external settings from the header. Please refer to the following block diagram.

![The image displays a block diagram centered around a large rectangle labeled **'Bypass Control Logic'**.\n\n**Inputs (Left Side):**\nThree arrows point into the left side of the central block:\n*   **'MODE(0:1)'** (top arrow)\n*   **'PCI_RESET'** (middle arrow)\n*   **'WDT Time Out'** (bottom arrow, text is split across two lines)\n\n**Output (Right Side):**\n*   One arrow points out from the right side of the block. Above it is the text **'Control Relay'**.\n\n**Bottom Section:**\n*   On the far left is a grid of six circles (arranged in two columns and three rows). Dotted lines extend from this grid towards the right.\n*   Three upward-pointing arrows enter the bottom edge of the **'Bypass Control Logic'** block.\n*   To the right of these arrows are three horizontal lines with labels and black dots:\n    *   **'PONSTS'**\n    *   **'BYPASS'**\n    *   **'NORMAL'**](.pci-8246-manual-4/cdfe0d5c43f5876bdae57d9ffb2b3dcd174d86b3ac6169f21677418060283cd2.jpg)

Figure 8: Bypass Control Priority

The control priority is as follows. The setting with higher priority will override the lower priority setting (or status)

<table><tr><td>Bypass Control Priority</td><td>Control source</td></tr><tr><td rowspan="5">Highest</td><td>Reset</td></tr><tr><td>BYPASS state enforcement jumper</td></tr><tr><td>NORMAL state enforcement jumper</td></tr><tr><td>Bypass control mode setting MODE[0:1]</td></tr><tr><td>WDT time out</td></tr></table>

# 3.3 DOS Utilities for Evaluation - Utilities List

Before programming this card, users can evaluate the PCI-8246 bypass capability using the DOS test utility - 8246util.exe:

# 8246util e:

Enable the WDT. The relay array will be switched to Normal State when executing the command. If the user does not reload the WDT before time out in 1, 2, 4, or 8 seconds depending on the DIP switch setting, then the relay array will be switched to the Bypass State. A ‘click’ can be heard when the relay switches.

# 8246util e [x]:

Enable the WDT. Users can determine the time out value by typing the parameter [x]; only 1, 2, 4, or 8 is valid for [x]. The relay array will be switched to Normal State when executing the command. If the user does not reload the WDT before time out in 1, 2, 4 or 8 seconds depending on the setting, then the relay array will be switched to the Bypass State. A ‘click’ can be heard when the relay switches.

# 8246util d:

Disable and stop WDT. The relay array will stay in the same state.

# 8246util w:

Enable WDT and keep reloading WDT. The WDT would keep running unless the program stops running or powers off. The WDT status LED would blink and the relay array would be in the Normal State. The user can adjust the real panel switch to enforce to Bypass State; then adjust the BYPASS switch Off to switch back to the Normal State. The WDT would continue to run. The user can then power off and the relay array will switch back to the Bypass State.

# 8246util n:

Enforce the relay array to Normal State and WDT will be disabled. The user can set Control Header (CN1) jumpers to force the relay array to Bypass State.

# 8246util b:

Enforce the relay array to Bypass State and WDT will be disabled. User can adjust set Control Header (CN1) jumpers to force the relay array to Normal State.

# 3.4 WDT Library Installation for Windows 2000 and XP

ADLINK provides a setup program for installing the PCI-8246 WDT library, driver, and sample program under Windows 2000 or XP. Please follow the instructions below.

1. Place the ADLINK All-in-One CD into the appropriate CD-ROM drive.
2. Execute:

X:\PCI\PCI-8246\WDTutility\2K\_XP\SETUP

(X indicates the CD-ROM drive letter)

3. A Welcome dialog box appears, click Next to start installation.
4. Setup then prompts with the following dialog box for the user to specify the destination directory. The default path is C:\ADLINK\PCI8246 WDT. To install PCI-8246 WDT for Windows software in another directory, click Browse… to change the destination directory.

![Choose Destination Location\nSetup will install PCI-8246\WDT in the following directory.\nTo install to this directory, click Next.\nTo install to a different directory, click Browse and select another directory.\nYou can choose not to install PCI-8246\WDT by clicking Cancel to exit Setup.\nDestination Directory\nC:\ADLink\PCI8246\WDT\nBrowse...\n( Back	Next )	Cancel](.pci-8246-manual-4/39aa40abbbb8a207cd5a1c6ef15e43364fbbfae933478891f6ef92b6695b338d.jpg)

5. Click Next to begin installing PCI-8246 WDT for Windows.
6. The user will be prompted to restart Windows after the software installation process is completed.

Once the installation process is complete, the PCI-8246 WDT directory should contain the following files and sub-directories:

<table><tr><td>File/Subdirectory</td><td>Description</td></tr><tr><td>LIB</td><td>PCI-8246 WDT import libraries and DLL</td></tr><tr><td>INCLUDE</td><td>Include files for application programming</td></tr><tr><td>SAMPLE</td><td>Sample program</td></tr></table>

PCI-8246 WDT's DLL is also copied into the Windows System directory (default: C:\Winnt\System32). The driver file PCI8246.SYS is also copied into the Windows System Drivers directory (default: C:\Winnt\System32\Drivers).

To check whether or not installation was successful after installing the PCI-8246 WDT software and re-booting the system, follow the steps below:

1. Right click My Computer and select Properties. The System Properties Window will appear. Select the Hardware Page.

![System Properties\nGeneral | Network Identification | Hardware | User Profiles | Advanced |\nHardware Wizard\nThe Hardware wizard helps you install, uninstall, repair,\nunplug, eject, and configure your hardware.\nHardware Wizard...\nDevice Manager\nThe Device Manager lists all the hardware devices installed\non your computer. Use the Device Manager to change the\nproperties of any device.\nDriver Signing... Device Manager...\nHardware Profiles\nHardware profiles provide a way for you to set up and store\ndifferent hardware configurations.\nHardware Profiles...\nOK Cancel Apply](.pci-8246-manual-4/54f9af926293381edd02994b92222040a4ba15289b0b0bd6144065ecce33cb08.jpg)

2. Click the Device Manager button. Click the View menu and select Show hidden devices to display Non-Plug and Play devices.

![Device Manager\nAction View\nDVD/CD-ROM drives\nFloppy disk controllers\nFloppy disk drives\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nNon-Plug and Play Drivers\nAFD Networking Support Environment\nBeep\nDiskperf\ndmboot\ndmload\nFips\nFs_Rec\nGeneric Packet Classifier\nIPSEC driver\nKSecDD\nmnmdd\nmountmgr\nNDIS System Driver\nNDProxy\nNetBEUI Protocol\nNetBios over Tcpip\nNetDetect\nNull\npartmgr\nParVdm\nPci8246\nRemote Access Auto Connection Driver\nRemote Access IP ARP Driver\nTCP/IP Protocol Driver\nvga](.pci-8246-manual-4/86fdcc50461a94d87ef8c3237f4a993185546f01804884437750525f800a2f94.jpg)

3. If Pci8246 is listed then the driver is working.

The Visual C++ sample program located in &lt;PCI-8246 WDT directory&gt;\SAMPLE demonstrates the usage of the PCI-8246 WDT Windows Library.

![8246 WDT Sample\nCard\n1\nEnable Mode Control\n● Software Enable\n● Hardware □ Auto Reloading\nEnforce Mode Switch\nNORMAL BYPASS\nOK\nCancel\nReload Disable\nSoftware Timeout Value\n○ 1s ○ 2s ○ 4s ○ 8s\nSet](.pci-8246-manual-4/8602d08bd6451e87627d9ac3937cb24d2a92d670d96300d53207d5a5760c3db6.jpg)

# 3.5 Function Reference of WDT Library for Windows and Linux

# WDT Functions Overview

WDT functions are grouped into the following classes:

• General Functions

GetCardCount
LanWdtSetTimer
LanWdtReload

• Enable/Disable control

• LanWdtEnable
• LanWdtDisable
LanWdtEnableReload

• Mode Enforcement control

LanWdtForceNormal
LanWdtForceBypass

Data Type

<table><tr><td>Type Name</td><td>Description</td><td>Range</td><td>C/C++ Type (for 32-bit compiler)</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td><td>Short</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td><td>unsigned short</td></tr></table>

# Function Reference

# GetCardCount

Prototype:

I16 \_stdcall GetCardCount(void);

Description:

The GetCardCount returns the card count which are installed on the system. User can call this routine to determine how many PCI-8246 card are present.

Parameter:

No

Return Value:

The count of the 8246 cards

# LanWdtSetTimer

Prototype:

I16 \_stdcall LanWdtSetTimer(U16 card\_number, U16 interval);

Description:

The LanWdtSetTimer can set the software timeout value and switch to Mode 2 (software timeout) for selected card.

Parameter:

card\_number:

The index of card. On a single card installed system, always use '0'.

interval:

The timeout setting value. Only 1, 2, 4, 8 are vaild.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtReload

Prototype:

I16 \_stdcall LanWdtReload(U16 card\_number);

Description:

The LanWdtReload can reload/reset the counter on selected card. User should use this frequently to prevent watchdog timeout.

Parameter:

card\_number:

The index of card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtEnable

Prototype:

I16 \_stdcall LanWdtEnable(U16 card\_number);

Description:

The LanWdtEnable can enable watchdog function on selected card.

Parameter:

card\_number:

The index of card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtDisable

Prototype:

I16 \_stdcall LanWdtDisable(U16 card\_number);

Description:

The LanWdtDisable can disable watchdog function and switch to mode 0 (hardware timeout) on selected card.

Parameter:

card\_number:

The index of card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtEnableReload

Prototype:

I16 \_stdcall LanWdtEnableReload(U16 card\_number);

Description:

The LanWdtEnableReload can enable watchdog timer and reload/reset periodly the counter on selected card. This routine will set up a system timer and poll the watchdog automatically.

Parameter:

card\_number:

The index of the card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtForceNormal

Prototype:

I16 \_stdcall LanWdtForceNormal(U16 card\_number);

Description:

The LanWdtForceNormal can enforce the relay array into normal mode on selected card.

Parameter:

card\_number:

The index of card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# LanWdtForceBypass

Prototype:

I16 \_stdcall LanWdtForceBypass(U16 card\_number);

Description:

The LanWdtForceBypass can enforce the relay array into bypass mode on selected card.

Parameter:

card\_number:

The index of the card. On a single card installed system, always use '0'.

Return Value:

ERR\_NoError, ERR\_InvalidBoardNumber, ERR\_OpenDriverFail, ERR\_IoctlFail.

# Functions Return Code

<table><tr><td>Status Code</td><td>Status Name</td><td>Description</td></tr><tr><td>0</td><td>ERR_NoError</td><td>No error occurred</td></tr><tr><td>-2</td><td>ERR_InvalidBoardNumber</td><td>The CardNumber argument is out of range (larger than 31).</td></tr><tr><td>-3</td><td>ERR_OpenDriverFail</td><td>Failed to open the device driver.</td></tr><tr><td>-6</td><td>ERR_loctlFail</td><td>Failed to perform the IOCTCL on the device driver.</td></tr></table>

![4](.pci-8246-manual-4/1b278a18db7d575164e7f1573330d429e67ec7aa3ae0f52219256f8464ba5f65.jpg)

# GbE Driver Installation

This section describes the LAN driver installation for the Intel® 82546EB onboard Ethernet controller. The relevant drivers are located on the ADLINK All-in-One CD:

1. Boot Windows 2000/XP/Windows Server 2003.
2. The driver is included in the driver CD. Run pro2kxp.exe under the following directory: X:\PCI\PCI-8246\Driver\82546EB\Win2kxp
3. On the license agreement - read the license agreement. Click 'I accept the terms in the license agreement’ if you agree to continue.
4. Location to Save Files, click Next to save files in folder.

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the aftersales services we offer, please read the following carefully.

1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/.

2. All ADLINK products come with a two-year guarantee

• The warranty period starts from the product’s shipment date from ADLINK’s factory.
Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for loss of data.
Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.
For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's two-year guarantee in the following situations:

• Damage caused by not following instructions in the user's manual.
Damage caused by carelessness on the user's part during product transportation.
Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
Damage caused by leakage of battery fluid during or after change of batteries by customer/user.
• Damage from improper repair by unauthorized technicians.
• Products with altered and/or damaged serial numbers are not entitled to our service.
• Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please download an RMA application form from our company website: http://rma.adlinktech.com/policy. Damaged products with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff: service@adlinktech.com.
[🔗 Link to the original document](.pci-8246-manual-4/pci-8246-manual-4.pdf)