# cPCI/PCI-8554/Râ

# Multi-functions

# Counter / Timer Card

# User’s Guide

©Copyright 1998\~2002 ADLINK Technology Inc,

All Rights Reserved.

Manual Rev. 1.02: July 31, 2002

Part No: 50-11130-100

The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

NuDAQ, DAQBench are registered trademarks of ADLINK Inc.,

Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting service from ADLINK

Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us.

<table><tr><td colspan="4">ADLINK Technology Inc.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">Service@adlinktech.com</td></tr><tr><td rowspan="4">Technical Support</td><td>NuDAQ + USBDAQ</td><td colspan="2">nudaq@adlinktech.com</td></tr><tr><td>Automation</td><td colspan="2">automation@adlinktech.com</td></tr><tr><td>NulPC</td><td colspan="2">nuipc@adlinktech.com</td></tr><tr><td>NuPRO / EBC</td><td colspan="2">nupro@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan.</td></tr></table>

Please email or FAX us of your detailed information for a prompt, satisfactory and constant service.

<table><tr><td colspan="4">Detailed Company Information</td></tr><tr><td>Company/Organization</td><td colspan="3"></td></tr><tr><td>Contact Person</td><td colspan="3"></td></tr><tr><td>E-mail Address</td><td colspan="3"></td></tr><tr><td>Address</td><td colspan="3"></td></tr><tr><td>Country</td><td colspan="3"></td></tr><tr><td>TEL</td><td></td><td>FAX</td><td></td></tr><tr><td>Web Site</td><td colspan="3"></td></tr><tr><td colspan="4">Questions</td></tr><tr><td>Product Model</td><td colspan="3"></td></tr><tr><td>Environment to Use</td><td colspan="3">OS:Computer Brand:M/B: CPU:Chipset: BIOS:Video Card:Network Interface Card:Other:</td></tr><tr><td>Detail Description</td><td colspan="3"></td></tr><tr><td>Suggestions to ADLINK</td><td colspan="3"></td></tr></table>

# Table of Contents

# Tables ........ iii

# Figures......... ...iv

# How to Use This Guide.......... ....v

# Chapter 1 Introduction............ ..

1.1 Features..
1.2 Applications..
1.3 Specifications ..
1.4 Software Supporting.. .5

1.4.1 Programming Library . .5
1.4.2 PCIS-LVIEW: LabVIEW® Driver....
1.4.3 PCIS-VEE: HP-VEE Driver... .6
1.4.4 DAQBenchTM: ActiveX Controls .. .6

# Chapter 2 Getting Started........ ..

2.1 What You Have .
2.2 Unpacking ..
2.3 PCB Layout of cPCI/PCI-8554/R .8
2.4 Default Jumper Setting ... 9
2.5 cPCI/PCI-8554/R Installation. .11

2.5.1 Hardware configuration .. .11

2.6 Device Installation for Windows Systems.. .. 12
2.7 Pin Assignment of Connector.. . 13
2.8 Clock System . . 15
2.9 Counters Architecture.. .15

2.9.1 Independent Counters (Counter 1\~10)... .17
2.9.2 Cascaded Counters ... .17
2.9.3 User Configurable Cascaded Counters... . 18

2.10 Clock Source Configurations .. .19
2.11 Gate Control Configurations . .20
2.12 Counter Outputs . . 20
2.13 Debounce System.. .21
2.14 Interrupt System .... .22
2.15 Digital Input and Output.. .23
2.16 12V and 5V Power Supply.. .24

# Chapter 3 Registers....... .....25

3.1 PCI PnP Registers... .. 25
3.2 I/O Address Map.. .26
3.3 Timer/Counter Registers.. .27

3.4 Timer / Counter Clock Mode Control.. . 28

3.5 Digital Input Register.. . 28

3.6 Digital Output Register.. .. 29

# Chapter 4 Signal Connections & Applications ....................30

4.1 Connectors Pin Assignment.. .30

4.2 Digital I/O Connection . .. 30

4.3 Timer/Counter Connection.. .31

4.4 Frequency Generator... .32

4.4.1 To generate a 250 KHz Square Wave.. . 32

4.4.2 To generate a 1 pulse/1 hour signal .. . 33

4.5 Pulse Width Measurement.. . 34

4.6 Frequency Measurement.. .35

4.7 Event Counter .. .37

4.8 Dual Interrupt System.. . 38

# Chapter 5 C/C++ Library.......... ..39

5.1 Libraries Installation.. .39

5.2 Programming Guide.. ... 40

5.2.1 Naming Convention... .40

5.2.2 Data Types.. .40

5.3 \_8554\_Initial .. .. 41

5.4 \_8554\_Write\_Counter.. . 42

5.5 \_8554\_Read\_Counter.. .43

5.6 \_8554\_Stop\_Counter.. .. 44

5.7 \_8554\_Read\_Status . . 45

5.8 \_8554\_DO... .46

5.9 \_8554\_DI.. ... 47

5.10 \_8554\_SET\_cntCLK. . 48

5.11 \_8554\_SET\_CK1 . .. 49

5.12 \_8554\_SET\_DBCLK.. .50

5.13 \_8554\_Set\_INT\_Control.. .51

5.14 \_8554\_Get\_IRQ\_Status.. . 52

5.15 \_8554\_INT\_Enable.. . 53

5.16 \_8554\_INT\_Disable . .54

5.17 \_8554\_CLR\_IRQ1 . .. 54

5.18 \_8554\_CLR\_IRQ2 . . 55

# Warranty Policy ........ ....56

# Tables

Table 1. Default Jumper Settings on PCI-8554.. ...10

Table 2. Extra Default Jumper Setting on cPCI-8554/R .. ...10

Table 3. Counters label relationship.... ...15

Table 4. I/O Address Map of cPCI/PCI-8554/R ...26

Table 5. Timer/Counter Registers . ..27

Table 6. Timer/Counter Clock Mode Control Register... ...28

Table 7. Digital Input Register ... ...28

Table 8. Digital Output Register ... ...29

Table 9. Data types and their ranges ...40

# Figures

Figure 1: Functional Block diagram . .2
Figure 2: PCB Layout of PCI-8554.. .8
Figure 3: PCB Layout of cPCI-8554/R.. .9
Figure 4: Pin Assignment of PCI-8554 Connector CN1.. ...13
Figure 5: Pin Assignment of cPCI-8554/R Connector CN1.. .....14
Figure 6: Block Diagram of 8254 Counter ... ...16
Figure 7: Default Counters Architectural . ...16
Figure 8: Example of ‘independent counters’. ...17
Figure 9: JP14/JP15 (For cPCI-8554/R only)... ...17
Figure 10: Cascaded Counter Configuration .. ...18
Figure 11: User Programmable Cascaded Counters .... ...18
Figure 12: Clock Source of Counter n ... ...19
Figure 13: Clock Source of CK1.. ...19
Figure 14: Gate source of counter 1 \~ 10... ...20
Figure 15: Structure of JP1 \~ JP11 ... ...21
Figure 16: Clock Source of DB\_CLK.. ...21
Figure 17: Basic Timing of the debounce system ... ...22
Figure 18: Dual Interrupt System of cPCI/PCI-8554/R .. ...22
Figure 19: Digital I/O Connection... ...30
Figure 20: Example of a frequency generator (1)... ..32
Figure 21: Example of frequency generator (2).. ...33
Figure 22: Example of pulse width measurement.. ...34
Figure 23: Example of frequency measurement (1)... ...36
Figure 24: Example of event counter.. ...37
Figure 25: Example of dual interrupt system ... ...38

# How to Use This Guide

This manual is designed to help you use the cPCI/PCI-8554/R. The manual describes how to modify various settings on the cPCI/PCI-8554/R card to meet your requirements. It is divided into 5 chapters:

Chapter 1, “Introduction,” gives an overview of the product features, applications, and specifications.

Chapter 2, “Installation & Configurations” describes the operation method and multi-functions of the cPCI/PCI-8554/R. Users should read through this chapter to understand the configurations of the cPCI/PCI-8554/R. The chapter will also outline how to install the cPCI/PCI-8554/R.

Chapter 3, “Registers,” describes the details of each register of the cPCI/PCI-8554/R; this information will assist programmers who want to control the hardware with low-level programming.

Chapter 4, “Signal Connection & Applications,” describes the connectors' pin assignment and how to connect the outside signal and devices to / from the cPCI/PCI-8554/R. Some applications also are introduced.

Chapter 5, “High-level Programming,” introduces the Clanguage library for operating the cPCI/PCI-8554/R. Some examples are shown too.

#

# Introduction

cPCI/PCI-8554/R is a general-purpose counter / timer and digital I/O card. The card is designed with four 8254, a programmable interval timer/counter chip, totally, providing twelve 16-bit down counter or frequency dividers. Three different types of interface are available: PCI (PCI-8554), CompactPCI (cPCI-8554), and CompactPCI with rear I/O connection (cPCI-8554R) for various platforms and applications.

The card has multi-configurations. Its counters can be set in an independent or cascaded configuration. The gate controls for the counter can come from either the internal default enable signal or from external sources. The clock source of the counters can be set from an internal or external clock source, when an external clock source is used, users can configure the jumper as to disable or enable the debounce function.

The card also provides digital input and output ports. There are 8 digital output and 8 digital input channels, which can be used to control or monitor external devices.

The cPCI/PCI-8554/R provides an interrupt signal, which is generated by the counter output. External interrupt signals can also be used. The interrupt can be used for watchdog timers or others applications. The maximum interrupt time interval can be 536 seconds.

The I/O signals are provided via the 100-pin SCSI-II connector. Figure 1 shows the functional block diagram of the cPCI/PCI-8554/R. The cPCI/PCI-8554/R uses ASIC PCI controller to interface the board to the PCI bus. The ASIC fully implements the PCI local bus specification Rev 2.1. The BIOS software automatically controls all bus relative configurations, such as base memory and interrupt assignment. This removes the burden of searching for a conflict, which can be very time consuming and difficult with some bus standards.

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   PCI Bus\n*   PCI Controle\n*   Interrupt system\n*   clock system\n*   8 bits input/output\n*   8254 chip #1\n*   8254 chip #2\n*   8254 chip #3\n*   8254 chip #4\n*   Debounce system\n*   100 pin SCSI -\n\n**Connections:**\n*   **PCI Bus** connects to **PCI Controle** via 'data bus', 'Address bus', and 'Interru' (bidirectional arrows).\n*   **PCI Controle** connects to **Interrupt system** (bidirectional arrow).\n*   **PCI Controle** connects to the right-side column blocks (**8 bits input/output**, **8254 chip #1**, **8254 chip #2**, **8254 chip #3**, **8254 chip #4**) via bidirectional arrows.\n*   **8 bits input/output** connects to **100 pin SCSI -** via two bidirectional arrows labeled '8'.\n*   **8254 chip #1** connects to **100 pin SCSI -** via 'COUT1 ~ COUT3' and 'GATE1 ~ GATE3'.\n*   **8254 chip #2** connects to **100 pin SCSI -** via 'COUT4 ~ COUT6' and 'GATE4 ~ GATE6'.\n*   **8254 chip #3** connects to **100 pin SCSI -** via 'COUT7 ~ COUT9' and 'GATE7 ~ GATE9'.\n*   **8254 chip #4** connects to **100 pin SCSI -** via 'COUT10 ~ COUT12' and 'GATE10 ~'.\n*   **8254 chip #4** connects to **Debounce system** (bidirectional arrow).\n*   **8254 chip #4** connects to **Interrupt system** via a line labeled 'COUT12' (arrow points to Interrupt system).\n*   **Debounce system** connects to **100 pin SCSI -** via 'ECLK1 ~ ECLK10' and 'E_INT'.](.pci-8554-manual-1/92bf234137b5f422d27c7fbff96d20a99b87566851408bf504dec2e024fc14c4.jpg)

Figure 1: Functional Block diagram

# 1.1 Features

The cPCI/PCI-8554/R Counter / Timer and digital I/O Card provides the following advanced features:

• Four 8254 chips provide twelve 16 bits down counters
Multi-configurations of counters / timers:
Flexible setting for each independent counter, the clock source could be external, internal or cascaded. The gate signal is external controlled or internal enabled.
Provide debounce function with flexible setting to prevent from bounce phenomenon when using external clocks.
• 8 digital output channels
• 8 digital input channels
Dual interrupt sources
√ From output of counter #12, or
P From external source.
100-pin SCSI-II female connector.
PCI-Bus

# 1.2 Applications

Event counter
• Frequency generator
• Frequency synthesizer
• Pulse width measurement
• Low level pulse generator
Time delay
Industry automation
Watchdog timer

# 1.3 Specifications

# Programmable Counter / Timer

Device: 82C54x4
Number of Counters/timers:
P 10 independent timers / counters
P 2 cascaded timers / counters
√ Cascaded 32-bit counters with fixed 8MHz internal clock

Counter mode: 16-bit down counter

Maximum input frequency: 8 MHz

Clock sources of independent counters:

P External clock
P Prior counter output
P Clock #10 output
P CK1 (Programmable)

CK1 clock sources: (Programmable)

P 8MHz internal base clock
P Programmable counter 11 output

Gate control: default enable or external control

# Digital Filter Circuits

Device: MC14490
De-bounce clock: (Programmable)
√ 8MHz internal base clock
P Programmable counter 11 output

# Digital I/O (DIO)

No. of input channels : 8 channels
• No. of output channels : 8 channels (dedicated output)
Characteristics: TTL compatible signal

# General Specifications

Connector: 100-pin SCSI-II female connector
Operating Temperature: $0 ^ { \circ } \mathsf C \sim 6 0 ^ { \circ } \mathsf C$
Storage Temperature: $\mathbf { \partial } \cdot 2 0 ^ { \circ } \mathsf { C } \sim 8 0 ^ { \circ } \mathsf { C }$
• Humidity: 5 \~ 95%, non-condensing
• Power Consumption: +5 V @ 350 mA typical
Dimension: 134mm(L) X 107mm(W)

# 1.4 Software Supporting

ADLINK provides versatile software drivers and packages for users’ different approach to building a system. ADLINK not only provides programming libraries such as DLL for most Windows based systems, but also provide drivers for many other software packages such as LabVIEW®, HP VEETM, DASYLabTM, InTouchTM, InControlTM, ISaGRAFTM, and so on.

All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes. Without the software code, you can install and run the demo version for two hours for trial/demonstration purposes. Please contact ADLINK dealers to purchase the formal license.

# 1.4.1 Programming Library

For customers who are writing their own programs, we provide function libraries for many different operating systems, including:

DOS Library: Borland C/C++ and Microsoft C++, the functional descriptions are included in this user’s guide.

Windows 95 DLL: For VB, VC++, Delphi, BC5, the functional descriptions are included in this user’s guide.

PCIS-DASK: Include device drivers and DLL for Windows 98, Windows NT and Windows 2000. DLL is binary compatible across Windows 98, Windows NT and Windows 2000. This means all applications developed with PCIS-DASK are compatible with Windows 98, Windows NT and Windows 2000. The developing environment can be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The user’s guide and function reference manual of PCIS-DASK are included in the CD. Please refer to the PDF files under \\Manual\_PDF\Software\PCIS-DASK

PCIS-DASK/X: Include device drivers and shared library for Linux. The developing environment can be Gnu C/C++ or any programming language that allows linking to a shared library. The user's guide and function reference manual of D2K-DASK/X are included in the CD. (\Manual\_PDF\Software\D2K-DASK-X.)

The above software drivers are shipped with the board. Please refer to the “Software Installation Guide” for installation procedures.

# 1.4.2 PCIS-LVIEW: LabVIEW® Driver

PCIS-LVIEW contains the VIs, which is used to interface with the NI LabVIEW® software package. The PCIS-LVIEW supports Windows 95/98/NT/2000. The LabVIEW® drivers are shipped free with the board. For more information about PCIS-LVIEW, please refer to the user’s guide in the CD. (\\Manual\_PDF\Software\PCIS-LVIEW)

# 1.4.3 PCIS-VEE: HP-VEE Driver

The PCIS-VEE includes user objects, which are used to interface with the HP VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE drivers are shipped free with the board. For more information about PCIS-VEE, please refer to the user’s guide in the CD. (\\Manual\_PDF\Software\PCIS-VEE)

# 1.4.4 DAQBenchTM: ActiveX Controls

We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use the DAQBenchTM ActiveX Control components library for developing applications. The DAQBenchTM is designed under Windows NT/98. For more information about DAQBench, please refer to the user’s guide in the CD. (\\Manual\_PDF\Software\DAQBench\DAQBench Manual.PDF)

#

# Getting Started

This chapter discusses how to setup the cPCI/PCI-8554R and configure the card to meet the requirements of your application. The contents of the package and unpacking information that you should be aware off are outlined first.

# 2.1 What You Have

In addition to this User's Manual, the package should includes the following items:

cPCI/PCI-8554/R Enhanced Multi-function Counter / Timer Card
ADLINK CD
Software Installation Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

# 2.2 Unpacking

Your cPCI/PCI-8554/R card contains electro-static sensitive components that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damages. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module placed on a firm flat surface.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

You are now ready to install your cPCI/PCI-8554/R.

# 2.3 PCB Layout of cPCI/PCI-8554/R

![PD-854\nREV-A2\nP0008](.pci-8554-manual-1/1b098906832b404c6eda6a7038968a15d17269e4bd3f2ce221b7fca7ad2e8ec3.jpg)

Figure 2: PCB Layout of PCI-8554

![Circuit board layout diagram with labeled components and connections](.pci-8554-manual-1/13a76f0c24ac2967a1b4bc851b9e37d5a80e85b1892c53ec295b287ff01bbb3c.jpg)

Figure 3: PCB Layout of cPCI-8554/R

# 2.4 Default Jumper Setting

To operate the cPCI/PCI-8554/R correctly, users need to understand the structure of cPCI/PCI-8554/R and details of the possible configurations. The functional block diagram of the cPCI/PCI-8554/R is shown in figure 1 of chapter 1. The following section lists the default jumper setting on the cPCI/PCI-8554/R.

<table><tr><td>Items</td><td>Default Configuration</td><td>Set by</td></tr><tr><td>ECLK1</td><td>No Debounce function</td><td>JP1</td></tr><tr><td>ECLK2</td><td>No Debounce function</td><td>JP2</td></tr><tr><td>ECLK3</td><td>No Debounce function</td><td>JP3</td></tr><tr><td>ECLK4</td><td>No Debounce function</td><td>JP4</td></tr><tr><td>ECLK5</td><td>No Debounce function</td><td>JP5</td></tr><tr><td>ECLK6</td><td>No Debounce function</td><td>JP6</td></tr><tr><td>ECLK7</td><td>No Debounce function</td><td>JP7</td></tr><tr><td>ECLK8</td><td>No Debounce function</td><td>JP8</td></tr><tr><td>ECLK9</td><td>No Debounce function</td><td>JP9</td></tr><tr><td>ECLK10</td><td>No Debounce function</td><td>JP10</td></tr><tr><td>E_INT</td><td>No Debounce function</td><td>JP11</td></tr><tr><td>ECLK11</td><td>Internal 8MHz Clock</td><td>JP12</td></tr><tr><td>ECLK12</td><td>Output of CLK11</td><td>JP13</td></tr></table>

Table 1. Default Jumper Settings on PCI-8554

<table><tr><td>Items</td><td>Default Configuration</td><td>Set by</td></tr><tr><td>GATE11</td><td>Vcc</td><td>JP14</td></tr><tr><td>GATE12</td><td>Vcc</td><td>JP15</td></tr></table>

Table 2. Extra Default Jumper Setting on cPCI-8554/R

There are 13 jumpers available on the PCI-8554, and 15 jumpers on the cPCI-8554/R, the first 11 jumpers are used to select the debounce function. JP12 and JP13 are used for selecting the clock source for Counter No. 11 and 12. The default setting for counter No. 11 and 12 are cascaded for frequency division. Refer to section 2.9 for more details. JP14 and JP15 are used for selecting the gate voltages of counter No. 11 and 12 (only for cPCI-8554/R). Users can change the cPCI/PCI-8554/R's default configuration by setting jumpers on the card to suit the application. The card's jumpers are preset at the factory.

Before changing the default configuration, users must fully understand the operation of the debounce function. The setting and the basic operation theory are not discussed in this chapter. Refer to section 2.12 for details of the operation theory and than refer to chapter 4 for application notes.

# 2.5 cPCI/PCI-8554/R Installation

# 2.5.1 Hardware configuration

The PCI cards (or CompactPCI cards) is equipped with the plug and play PCI controller, it has the ability to request base addresses and interrupts according to the PCI standard. The systems BIOS will install the system resources based on the PCI cards’ configuration registers and system parameters (which are set by system BIOS). Interrupt assignments and memory usage (I/O port locations) of the PCI cards are also assigned by system BIOS. This system resource assignment is done on a board-byboard basis. It is not suggested to assign system resources by any other methods.

The PCI card can be inserted into any PCI slot without the need for any system resource configuration.

# 2.5.1.1 Installation Procedures

1. Turn off your computer
2. Turn off all accessories (printer, modem, monitor, etc.) connected to your computer.
3. Remove the cover from your computer.
4. Setup jumpers on the PCI or CompactPCI card.
5. Select a 32-bit PCI slot. PCI slot are shorter than ISA or EISA slots, and are usually white or ivory in color.
6. Before handling the PCI cards, discharge any static buildup on your body by touching the metal case of the computer. Hold the edge and do not touch the components.
7. Position the board into the PCI slot you selected.
8. Secure the card in place at the rear panel of the system.

# 2.6 Device Installation for Windows Systems

Once Windows 95/98/2000 has started, the Plug and Play function of the Windows OS will find the new NuDAQ/NuIPC cards. If this is the first time a NuDAQ/NuIPC cards is installed into the computer system. The Windows operating system will inform you to input the device information source. Please refer to the “Software Installation Guide” for installation procedures.

# 2.7 Pin Assignment of Connector

![(1)\n(2)\n(3)\n(51)\n(52)\n(53)\n(48)\n(49)\n(50)\n(98)\n(99)\n(100)](.pci-8554-manual-1/2d6e6600bdd8619f0f9ba3fb475c63d0a4dbc6c3d937d0bb2bd2096ae1c35485.jpg)

<table><tr><td>(1) +12V</td><td>(26) GND</td><td>(51) GND</td><td>(76) ECLK9</td></tr><tr><td>(2) +12V</td><td>(27) GND</td><td>(52) GOUT2</td><td>(77) COUT8</td></tr><tr><td>(3) +12V</td><td>(28) GND</td><td>(53) GIN2</td><td>(78) GATE8</td></tr><tr><td>(4) Vcc</td><td>(29) GND</td><td>(54) GND</td><td>(79) ECLK8</td></tr><tr><td>(5) Vcc</td><td>(30) GND</td><td>(55) GOUT1</td><td>(80) COUT7</td></tr><tr><td>(6) Vcc</td><td>(31) GND</td><td>(56) GIN1</td><td>(81) GATE7</td></tr><tr><td>(7) NC</td><td>(32) GND</td><td>(57) E_INT</td><td>(82) ECLK7</td></tr><tr><td>(8) DI_6</td><td>(33) GND</td><td>(58) DI7</td><td>(83) COUT6</td></tr><tr><td>(9) DI_4</td><td>(34) GND</td><td>(59) DI5</td><td>(84) GATE6</td></tr><tr><td>(10) DI_2</td><td>(35) GND</td><td>(60) DI3</td><td>(85) ECLK6</td></tr><tr><td>(11) DI_0</td><td>(36) GND</td><td>(61) DI1</td><td>(86) COUT5</td></tr><tr><td>(12) DO_6</td><td>(37) GND</td><td>(62) DO7</td><td>(87) GATE5</td></tr><tr><td>(13) DO_4</td><td>(38) GND</td><td>(63) DO5</td><td>(88) ECLK5</td></tr><tr><td>(14) DO_2</td><td>(39) GND</td><td>(64) DO3</td><td>(89) COUT4</td></tr><tr><td>(15) DO_0</td><td>(40) GND</td><td>(65) DO1</td><td>(90) GATE4</td></tr><tr><td>(16) NC</td><td>(41) GND</td><td>(66) ECLK12</td><td>(91) ECLK4</td></tr><tr><td>(17) GND</td><td>(42) GND</td><td>(67) COUT12</td><td>(92) COUT3</td></tr><tr><td>(18) GND</td><td>(43) GND</td><td>(68) ECLK11</td><td>(93) GATE3</td></tr><tr><td>(19) GND</td><td>(44) GND</td><td>(69) COUT11</td><td>(94) ECLK3</td></tr><tr><td>(20) GND</td><td>(45) GND</td><td>(70) GND</td><td>(95) COUT2</td></tr><tr><td>(21) GND</td><td>(46) GND</td><td>(71) COUT10</td><td>(96) GATE2</td></tr><tr><td>(22) GND</td><td>(47) GND</td><td>(72) GATE10</td><td>(97) ECLK2</td></tr><tr><td>(23) GND</td><td>(48) GND</td><td>(73) ECLK10</td><td>(98) COUT1</td></tr><tr><td>(24) GND</td><td>(49) GND</td><td>(74) COUT9</td><td>(99) GATE1</td></tr><tr><td>(25) GND</td><td>(50) GND</td><td>(75) GATE9</td><td>(100) ECLK1</td></tr></table>

Figure 4: Pin Assignment of PCI-8554 Connector CN1

Legend:

<table><tr><td>ECLK n:</td><td>External clock source for counter #n</td></tr><tr><td>ExtG n:</td><td>External gate signal for counter #n</td></tr><tr><td>COUT n:</td><td>Counter / Timer output of counter #n</td></tr><tr><td>DO_m:</td><td>Digital output port channel #m</td></tr><tr><td>DI_m:</td><td>Digital input port channel #m</td></tr><tr><td>E_int:</td><td>External interrupt signal input</td></tr><tr><td>GOUT1:</td><td>Inverse TTL signal of GIN1</td></tr><tr><td>GOUT2:</td><td>Inverse TTL signal of GIN2</td></tr><tr><td>NC:</td><td>No Connection</td></tr></table>

![(1)\n(2)\n(3)\n(51)\n(52)\n(53)\n(48)\n(49)\n(50)\n(98)\n(99)\n(100)](.pci-8554-manual-1/df6e104fc9e467617372fc575bef1b67ffb7940b3df4b6b64e000b4774e57648.jpg)

<table><tr><td>(1) +12V</td><td>(26) GND</td><td>(51) GND</td><td>(76) ECLK9</td></tr><tr><td>(2) +12V</td><td>(27) GND</td><td>(52) GOUT2</td><td>(77) COUT8</td></tr><tr><td>(3) +12V</td><td>(28) GND</td><td>(53) GIN2</td><td>(78) GATE8</td></tr><tr><td>(4) Vcc</td><td>(29) GND</td><td>(54) GND</td><td>(79) ECLK8</td></tr><tr><td>(5) Vcc</td><td>(30) GND</td><td>(55) GOUT1</td><td>(80) COUT7</td></tr><tr><td>(6) Vcc</td><td>(31) GND</td><td>(56) GIN1</td><td>(81) GATE7</td></tr><tr><td>(7) GATE12</td><td>(32) GND</td><td>(57) E_INT</td><td>(82) ECLK7</td></tr><tr><td>(8) DI_6</td><td>(33) GND</td><td>(58) DI7</td><td>(83) COUT6</td></tr><tr><td>(9) DI_4</td><td>(34) GND</td><td>(59) DI5</td><td>(84) GATE6</td></tr><tr><td>(10) DI_2</td><td>(35) GND</td><td>(60) DI3</td><td>(85) ECLK6</td></tr><tr><td>(11) DI_0</td><td>(36) GND</td><td>(61) DI1</td><td>(86) COUT5</td></tr><tr><td>(12) DO_6</td><td>(37) GND</td><td>(62) DO7</td><td>(87) GATE5</td></tr><tr><td>(13) DO_4</td><td>(38) GND</td><td>(63) DO5</td><td>(88) ECLK5</td></tr><tr><td>(14) DO_2</td><td>(39) GND</td><td>(64) DO3</td><td>(89) COUT4</td></tr><tr><td>(15) DO_0</td><td>(40) GND</td><td>(65) DO1</td><td>(90) GATE4</td></tr><tr><td>(16) GATE11</td><td>(41) GND</td><td>(66) ECLK12</td><td>(91) ECLK4</td></tr><tr><td>(17) GND</td><td>(42) GND</td><td>(67) COUT12</td><td>(92) COUT3</td></tr><tr><td>(18) GND</td><td>(43) GND</td><td>(68) ECLK11</td><td>(93) GATE3</td></tr><tr><td>(19) GND</td><td>(44) GND</td><td>(69) COUT11</td><td>(94) ECLK3</td></tr><tr><td>(20) GND</td><td>(45) GND</td><td>(70) GND</td><td>(95) COUT2</td></tr><tr><td>(21) GND</td><td>(46) GND</td><td>(71) COUT10</td><td>(96) GATE2</td></tr><tr><td>(22) GND</td><td>(47) GND</td><td>(72) GATE10</td><td>(97) ECLK2</td></tr><tr><td>(23) GND</td><td>(48) GND</td><td>(73) ECLK10</td><td>(98) COUT1</td></tr><tr><td>(24) GND</td><td>(49)GND</td><td>(74) COUT9</td><td>(99) GATE1</td></tr><tr><td>(25) GND</td><td>(50) GND</td><td>(75) GATE9</td><td>(100) ECLK1</td></tr></table>

Figure 5: Pin Assignment of cPCI-8554/R Connector CN1

# Legend:

ECLK n: External clock source for counter #n

ExtG n: External gate signal for counter #n

COUT n: Counter / Timer output of counter #n

DO\_m: Digital output port channel #m

DI\_ m: Digital input port channel #m

E\_int: External interrupt signal input

GOUT1: Inverse TTL signal of GIN1

GOUT2: Inverse TTL signal of GIN2

Note: pin-7and pin-16 is different from the definition in PCI-8554.

# 2.8 Clock System

The clock system of the cPCI/PCI-8554/R provides the internal clock source for the 8254 chips. The clock for counter/timer 1 \~ 10 can be one of 4 sources; an external clock source, a cascaded source from the ‘last’ channel, CK1 or COUT10. The next section will outline details on setting the clock for each counter/timer and CK1. The clock of counter/timer 11 is fixed at 8Mhz, and the clock of counter/timer 12 is connected to COUT11

# 2.9 Counters Architecture

There are four 8254 programmable timer/counter chips on the cPCI/PCI-8554/R card. Each 8254 chip contains 3 counter/timer and are labeled from 1 to 12. Counters 11 and 12 are default cascaded counters, but can be set for independent operation through jumpers JP12 & JP13. Counters 1 \~ 10 can also be set as an independent or cascaded counters. Table 3 illustrates the relationship between the reference 8254-chip label and the counter labels.

<table><tr><td>8254 Chip Label</td><td>Reference Number</td><td>Counter Label</td><td>Type of Counter</td></tr><tr><td rowspan="3">Chip 1</td><td rowspan="3">U3</td><td>Counter 1</td><td>Independent or Cascaded</td></tr><tr><td>Counter 2</td><td>Independent or Cascaded</td></tr><tr><td>Counter 3</td><td>Independent or Cascaded</td></tr><tr><td rowspan="3">Chip 2</td><td rowspan="3">U4</td><td>Counter 4</td><td>Independent or Cascaded</td></tr><tr><td>Counter 5</td><td>Independent or Cascaded</td></tr><tr><td>Counter 6</td><td>Independent or Cascaded</td></tr><tr><td rowspan="3">Chip 3</td><td rowspan="3">U5</td><td>Counter 7</td><td>Independent or Cascaded</td></tr><tr><td>Counter 8</td><td>Independent or Cascaded</td></tr><tr><td>Counter 9</td><td>Independent or Cascaded</td></tr><tr><td rowspan="3">Chip 4</td><td rowspan="3">U6</td><td>Counter 10</td><td>Independent or Cascaded</td></tr><tr><td>Counter 11</td><td>Independent or Cascaded</td></tr><tr><td>Counter 12</td><td>Independent or Cascaded</td></tr></table>

Table 3. Counters label relationship

There are three signals (2 input and 1 output) for each counter, a clock input signal, a gate control signal, and an output signal. Figure 6 illustrates the block diagram of the 8254 counter. CLK1 \~ CLK12 are clock sources, GATE1 \~ GATE12 are gate control signals and COUT1 \~ COUT12 are outputs of the counters. Figure 7 shows the interconnection of the 8254 counters and the labels associated to each counter.

![This block diagram features a central rectangular block labeled **'8254 Chip'** at the top and **'Counter'** in the center.\n\n**Connections:**\n*   An arrow from the text **'Clock Source Input'** points to the input terminal labeled **'C'** on the left side of the block.\n*   An arrow from the text **'Gate Control Input'** points to the input terminal labeled **'G'** directly below 'C'.\n*   An arrow extends from the output terminal labeled **'O'** on the right side of the block to the text **'Counter / Timer Output'**.](.pci-8554-manual-1/3ad1f6a77ef961b6f031ac82477b1778390ff2320a62e82daed4bade9906fd5d.jpg)

Figure 6: Block Diagram of 8254 Counter

![The diagram depicts a block labeled **8254 Chip #2** containing three vertically stacked sub-blocks.\n\n**Labeled Blocks:**\n*   **Counter #4**\n*   **Counter #5**\n*   **Counter #6**\n\n**Connections:**\n*   **For Counter #4:**\n    *   An arrow from **CLK4** points to the label **C**.\n    *   An arrow from **GATE4** points to the label **G**.\n    *   An output arrow labeled **COUT4** points to the right.\n*   **For Counter #5:**\n    *   An arrow from **CLK5** points to the label **C**.\n    *   An arrow from **GATE5** points to the label **G**.\n    *   An output arrow labeled **COUT5** points to the right.\n*   **For Counter #6:**\n    *   An arrow from **CLK6** points to the label **C**.\n    *   An arrow from **GATE6** points to the label **G**.\n    *   An output arrow labeled **COUT6** points to the right.](.pci-8554-manual-1/7b8b9b1e59b3ead6546bf7f36da5fbbaa6ed80a7393fbae46ae0ddbe38ce8cb7.jpg)

![The diagram features a central rectangular block labeled **8254 Chip #1**. Inside this block are three vertically stacked sub-blocks:\n\n*   **Counter #1**\n*   **Counter #2**\n*   **Counter #3**\n\nEach sub-block has input labels on the left (**C** and **G**) and an output on the right. The specific connections are as follows:\n\n**For Counter #1:**\n*   Input lines labeled **CLK1** and **GATE1** point into the **C** and **G** inputs respectively.\n*   An output line labeled **COUT1** points to the right.\n\n**For Counter #2:**\n*   Input lines labeled **CLK2** and **GATE2** point into the **C** and **G** inputs respectively.\n*   An output line labeled **COUT2** points to the right.\n\n**For Counter #3:**\n*   Input lines labeled **CLK3** and **GATE3** point into the **C** and **G** inputs respectively.\n*   An output line labeled **COUT3** points to the right.](.pci-8554-manual-1/fd71aa1c54cd82d9d2971506015f3df8aa85b1356f9fe172009fa9e4da066cbd.jpg)

![Based on the provided flowchart/block diagram, here is the accurate description:\n\n**Main Component:**\nA large rectangular block labeled **8254 Chip #4**.\n\n**Internal Blocks (Counters):**\nInside the main block, there are three vertically stacked counters:\n*   **Counter #10** (with input pins labeled **C** and **G**)\n*   **Counter #11** (with input pins labeled **C** and **G**)\n*   **Counter #12** (with input pins labeled **C** and **G**)\n\n**Connections and Inputs:**\n*   **Counter #10:**\n    *   **CLK10** connects to the **C** input.\n    *   **GATE10** connects to the **G** input.\n*   **Counter #11:**\n    *   **8M HZ** connects to the **C** input.\n    *   **VCC** connects to the **G** input.\n*   **Counter #12:**\n    *   The **C** input is connected to the output line **COUT11** (which loops back from Counter #11).\n    *   The **G** input is connected to **VCC**.\n\n**Outputs:**\n*   **COUT10** exits from Counter #10.\n*   **COUT11** exits from Counter #11.\n*   **COUT12** exits from Counter #12.](.pci-8554-manual-1/31f84984b96e5dc4907d1c49a7925beb35488f3f4cb753527c03b9dd986b6a1d.jpg)

![This diagram depicts a block labeled **8254 Chip #3** containing three internal counters.\n\n**Top Section:**\n*   **Inputs:** On the left, arrows from **CLK7** and **GATE7** point into the block.\n*   **Internal Labels:** Inside the block, the text **C** is at the top, **Counter #7** is in the middle, and **G** is at the bottom.\n*   **Output:** On the right, an arrow from a small circle on the block's edge points right to **COUT7**.\n\n**Middle Section:**\n*   **Inputs:** On the left, arrows from **CLK8** and **GATE8** point into the block.\n*   **Internal Labels:** Inside the block, the text **C** is at the top, **Counter #8** is in the middle, and **G** is at the bottom.\n*   **Output:** On the right, an arrow from a small circle on the block's edge points right to **COUT8**.\n\n**Bottom Section:**\n*   **Inputs:** On the left, arrows from **CLK9** and **GATE9** point into the block.\n*   **Internal Labels:** Inside the block, the text **C** is at the top, **Counter #9** is in the middle, and **G** is at the bottom.\n*   **Output:** On the right, an arrow from a small circle on the block's edge points right to **COUT9**.](.pci-8554-manual-1/3ff277fabc96c8207339b51b128d01edd01bc64aec8074fc6e66d9ca9a679aab.jpg)

Figure 7: Default Counters Architectural

# 2.9.1 Independent Counters (Counter 1\~10)

Counters 1 to 10 are independent counters because the clock source and gate control of those counters can be set independently (Thus named Independent Counter).

![This diagram depicts a logic block representing a counter.\n\n**Central Block:**\nA rectangular box is labeled '8254 Chip #1' at the top and 'Counter #1' in the center.\n\n**Inputs (Left Side):**\nTwo arrows point into the left side of the box:\n*   **CLK1**: Points to a terminal labeled **C**.\n*   **GATE1**: Points to a terminal labeled **G**.\n\n**Output (Right Side):**\n*   An arrow exits the right side from a terminal labeled **O**, labeled **COUT1**.](.pci-8554-manual-1/2b41e7609d7b82c0994d22e641935adbe21b70cfdb46383741b3276d85d32294.jpg)

Figure 8: Example of ‘independent counters’

# 2.9.2 Cascaded Counters

The connection of Counter 11 and 12 are different from the independent counters. These two counters are cascaded counters by default settings. The clock source of counter 11 is set to the internal 8 MHz clock by JP12, while JP13 connects its output to counter 12. In fact, counter 11and 12 are designed for frequency division by using the 8254's square wave generator mode. The gates of these counters are by default tied to logic high (‘H’) to enable these counters at all times. Users can change JP14 and JP15 to tie the signal to the GATE pins.

![JP14 / JP15\nVcc\nGATE11/12\nGate of Counter\n#11 / #12](.pci-8554-manual-1/af7d4226d1bf2147fc30c3a953a26b08b744f85fcc98c5c27d78fbec8c5596b7.jpg)

Figure 9: JP14/JP15 (For cPCI-8554/R only)

COUT12 can precisely generate frequencies up to 2MHz and as low as 0.00186 Hz. Note that the COUT12 signal can also be used as an interrupt source. See ‘Interrupt Sources’ section for details. Figure 10 illustrates the cascaded counters - counters 11 and 12. Sometimes, you may require all 12 counters to operate independently. For such a case, you can break the default connection by reconfiguring jumpers J12 and J13. Note that both counters 11 and 12 only have 2 selectable clock sources. It can be either the 8 MHz internal clock source or an external clock source.

![8MHz\nJP12\nECLK11\nECLK12\nJP13\n8254 Chip #4\nCounter 11 O\nCounter 12 O](.pci-8554-manual-1/745a5256101919b814348beab9cb572ec30e7fe56a9bf23693796e3b93907e4c.jpg)

Figure 10: Cascaded Counter Configuration

# 2.9.3 User Configurable Cascaded Counters

Although by default there is only one cascaded counter, users can configure the independent counters to be in a cascaded arrangement by using the \_SET\_cntCLK\_ function. . Figure 11 illustrates the user programmable-cascaded counter. Refer to the next section for details of the clock source options.

![The diagram depicts a block labeled **8254 Chip #1** containing two sub-blocks: **Counter #1** and **Counter #2**.\n\n**Inputs and Connections:**\n*   **Counter #1:**\n    *   **CLK1** connects to input **C**.\n    *   **GATE1** connects to input **G**.\n*   **Counter #2:**\n    *   **VCC** connects to input **C**.\n    *   **CLK2** connects to input **C**.\n    *   **GATE2** connects to input **G**.\n\n**Outputs and Feedback:**\n*   **Counter #1** output **O** is labeled **COUT1**.\n*   **Counter #2** output **O** is labeled **COUT2**.\n*   **COUT1** and **COUT2** are connected together.\n*   This combined line exits to the right and is labeled **Cascaded Counters Output**.\n*   The **Cascaded Counters Output** line loops back to the bottom left and connects to an input labeled **VCC**.\n*   A switch connects this bottom **VCC** line to the **CLK2** line (indicated by an arrow pointing towards **CLK2**).\n*   Below the switch is the text: `selectable by function '_SET_cntCLK_'`.](.pci-8554-manual-1/d78ba07a1b1ddec31ff029ecdad5d6685447e26c5f3dd8d0805ad893063443d1.jpg)

Figure 11: User Programmable Cascaded Counters

# 2.10 Clock Source Configurations

For each independent counter, one of four different clock sources maybe selected using the software. The clock source of counter n can be either an external clock source (ECLK n), a cascaded counter output (COUTn-1), CK1 or COUT10.

# Note:

1. The clock source of cascaded counter 11 is set at C8M (8MHz) and counter 12 is set to COUT11.
2. The external clock source labelled ECK n comes from JP1 \~ JP10, see section 2.12 for details

![This diagram depicts a multiplexer (switch) with four inputs and one output.\n\n**Labeled Blocks (Inputs):**\nThe four inputs on the left side are:\n*   `ECK n`\n*   `COUT n-1`\n*   `CK1`\n*   `COUT10`\n\n**Connections:**\n*   Arrows from each of the four input labels point to the four input terminals of the switch.\n*   The output of the switch connects to a node that leads to the right, labeled `CLK n`.\n\n**Labels and Annotations:**\n*   Above the switch: `n=1~9`\n*   Below the switch: An arrow points upward to the switch mechanism. The text reads:\n    *   `select by function`\n    *   `'_8554_SET_cntCLK'`](.pci-8554-manual-1/97cc8c2fa390ddf8fde0eb3d709b475708035c947639645019b367e46673f54a.jpg)

![The diagram depicts a 4-to-1 multiplexer with the following components and connections:\n\n*   **Inputs:** Four input lines on the left connect to the multiplexer terminals. They are labeled (from top to bottom) 'ECK10', 'COUT9', 'CK1', and 'C8M'.\n*   **Output:** A single output line on the right connects from the multiplexer and is labeled 'CLK10'.\n*   **Control:** An arrow points upward into the multiplexer's selection mechanism. Below the arrow is the text: select by function '_8554_SET_cntCLK'](.pci-8554-manual-1/85d1f666162c43a3693b682d7184339faf4a53e34dc79431603069dea5c847da.jpg)

Figure 12: Clock Source of Counter n

![Based on the provided image, here is the description of the block diagram:\n\n**Labeled Blocks/Text:**\n*   **C8M**\n*   **COUT11**\n*   **CK1**\n*   **select by function**\n*   **'_8554_SET_CK1'**\n\n**Connections:**\n*   An arrow connects **C8M** to the top input terminal of a switch/multiplexer symbol.\n*   An arrow connects **COUT11** to the bottom input terminal of the switch/multiplexer symbol.\n*   An arrow connects the output of the switch symbol to **CK1**.\n*   A vertical arrow points upward from the text **select by function** and **'_8554_SET_CK1'** into the center of the switch mechanism, indicating control.](.pci-8554-manual-1/6904e00f4fa235c5e071d3e5d96a83fcef0224e8bc15f507c1b0183185ad3546.jpg)

Figure 13: Clock Source of CK1

The internal clock sources of CK1 can be either C8M or COUT11, and is selected by using the “\_8554\_SET\_CK1” function. If the counters are set in a cascaded configuration, then the clock source will be from the output of the previous counter (Counter n-1). For example, COUT1 is cascaded to CLK2; COUT3 is cascaded to CLK4 and so on. (Note: If counter 1 is set in cascaded mode, CLK1 is connected to GND because COUT0 doesn’t exist).

# 2.11 Gate Control Configurations

The gate control signals of each independent counter is internally pulled high hence they are Enabled by default if no external gate is used. When an external gate signal is used, the counters can be used for pulse width measurements. Therefore, the period of the gate signal can be precisely controlled and frequency measurement is possible. Figure 14 shows the settings for the gate signals of counters 1\~ 10. (Note: The gate signals of counter 11 and 12 are always pulled high)

![VCC\nGATE n( From 100 pin )\nSCSI-II Connector )\n→ GATE n( To 8254 )](.pci-8554-manual-1/32c76aae81e84881394433e93f08474b2de152cf9367f8007155ed22a80769b6.jpg)

Figure 14: Gate source of counter 1 \~ 10

# 2.12 Counter Outputs

The clock source, gate signal and software programming controls the timer/counter output signal “COUT n”. All outputs from the 12 counters are routed to the 100-pin connector. Refer to the figure 4 and 5 for the corresponding signal pin number.

In addition, the output signal may be used as a clock source for cascaded configuration, see the above sections for details. It is possible to cascade all ten counters using the software settings, see 2.8 for reference. The output COUT12 can also be used as an internal interrupt source (refers to 'Interrupt System' for details).

# 2.13 Debounce System

The debounce system is used to eliminate the affects of bounce phenomenons. If an external clock is used, user can set JP1 \~ JP11 to select, whether or not to used the debounce system. If the debounce system is used, the debounce output signal will be in the same state as the input only if the input signal maintains the same state for four DB\_CLK cycles, otherwise the input signal will be treated as a glitch and the debounce output signal will maintain its present state, figure 15 illustrates how to set these jumpers, figure 16 illustrates how to select the DB\_CLK. Figure 17 illustrates the basic timing of the debounce system. (Note: DB\_CLK can’t be higher than 2MHz).

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n*   **DB_CLK**: Text at the top left.\n*   **debounce system**: A rectangular block in the center left.\n*   **JP n**: A vertical switch-like component on the right, enclosed in a rectangle.\n*   **n=1~10**: Text to the right of the switch component.\n*   **ECLK n**: Text at the bottom left.\n*   **ECK n**: Text on the far right.\n\n**Connections:**\n*   An arrow labeled **DB_CLK** points downward into the top of the **debounce system** block.\n*   An arrow exits the right side of the **debounce system** block and points to the top terminal of the **JP n** switch.\n*   An arrow originates from **ECLK n**, pointing upward into the bottom terminal of the **JP n** switch.\n*   An arrow originates from the middle terminal of the **JP n** switch and points to the right, ending at **ECK n**.](.pci-8554-manual-1/4e223e24b2bf8f0323ca7e14b281f873b984dced2941d873c809048b67a513ef.jpg)

![**Labeled Blocks:**\n*   DB_CLK\n*   debounce system\n*   JP11\n*   E INT\n*   EXTINT\n\n**Connections:**\n*   An arrow points from **DB_CLK** down to **debounce system**.\n*   An arrow points from **debounce system** to the top pin of **JP11**.\n*   An arrow points from **E INT** up to **debounce system**.\n*   An arrow points from **E INT** to the bottom pin of **JP11**.\n*   An arrow points from the middle pin of **JP11** to **EXTINT**.](.pci-8554-manual-1/7b5d1e0397f5c86cab4048d2976ab7df156c4fae8bd94eb694f0cdc9c9cd09fd.jpg)

Figure 15: Structure of JP1 \~ JP11

![The diagram depicts a multiplexer with two inputs and a single output, controlled by a specific function.\n\n**Labeled Blocks/Text:**\n*   **COUT11** (top input)\n*   **2MHz** (bottom input)\n*   **DB_CLK** (output)\n*   **select by function** (control label)\n*   **_8554_SET_DBCLK** (control label)\n\n**Connections:**\n*   An arrow from **COUT11** points to the top input of the multiplexer.\n*   An arrow from **2MHz** points to the bottom input of the multiplexer.\n*   A vertical arrow points upward to the multiplexer's control line (the diagonal selector bar), corresponding to the text **select by function** and **_8554_SET_DBCLK**.\n*   An arrow extends from the output of the multiplexer to the right, labeled **DB_CLK**.](.pci-8554-manual-1/74380949a54e5fe005a1278870e4f9a513044d5067903378a05f2ca871898f85.jpg)

Figure 16: Clock Source of DB\_CLK

![DB_CLK\ninput\nsignal\noutput\nsignal\nglitch is\neliminated](.pci-8554-manual-1/069131764e4d7be04c9246e8afa35dff51fabd49564e045fb4c193dbded672a8.jpg)

Figure 17: Basic Timing of the debounce system

# 2.14 Interrupt System

The cPCI/PCI-8554/R‘s interrupt system is a powerful and flexible system, which is suitable for many applications. The system is a Dual Interrupt System. Dual Interrupt means the hardware can generate two interrupt request signals simultaneously and the software is able to respond and invoke the ISR. Note that dual interrupt do not mean the card will occupy two IRQ levels. These two interrupt request signals INT1 and INT2 are generated by the external interrupt signal EXTINT and the timer/counter 12 output. Figure 18 shows the structure of interrupt system.

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **8254 Chip #4 Counter #11** (Top Left)\n*   **8254 Chip #4 Counter #12** (Center)\n*   **IRQ Flip-Flops** (Top Right)\n*   **debounce system** (Bottom Left)\n*   **JP11** (Small connector block)\n*   **IRQ Flip-Flops** (Bottom Center)\n*   **PCI Controller** (Right)\n\n**Connections:**\n*   **8MHz** and **'H'** connect to **8254 Chip #4 Counter #11**.\n*   The output from **8254 Chip #4 Counter #11** connects to **8254 Chip #4 Counter #12**.\n*   **'H'** connects to **8254 Chip #4 Counter #12**.\n*   The output labeled **COUT12** from **8254 Chip #4 Counter #12** connects to the top **IRQ Flip-Flops**.\n*   **Clear by '8554_CLR_IRQ1'** connects to the top **IRQ Flip-Flops**.\n*   There is a feedback connection looping from the right side of the top **IRQ Flip-Flops** back to its bottom input.\n*   The output labeled **INT1** from the top **IRQ Flip-Flops** connects to the **PCI Controller**.\n*   **DB_CLK** and **E_INT** connect to the **debounce system**.\n*   The output from the **debounce system** connects to **JP11**.\n*   The output labeled **EXTINT** from **JP11** connects to the bottom **IRQ Flip-Flops**.\n*   **Clear by '8554_CLR_IRQ2'** connects to the bottom **IRQ Flip-Flops**.\n*   The output labeled **INT2** from the bottom **IRQ Flip-Flops** connects to the **PCI Controller**.\n*   The output labeled **INT #A** originates from the **PCI Controller**.](.pci-8554-manual-1/c0521f8eeea91d89ea5e3c4c5f80a58d66536db386d36f8822e434aa569fe7f7.jpg)

Figure 18: Dual Interrupt System of cPCI/PCI-8554/R

Even though it is a dual interrupt system, only one interrupt level is ever used. The card uses the INT #A interrupt request signal on the PCI bus. The motherboards circuits will then transfer INT #A to one of the AT bus IRQ levels. The IRQ level is set by the PCI plug and play BIOS and is saved in the PCI controller. It is not necessary for users to set the IRQ level. Users can however read back the IRQ level setting by using the software library. Refer to the section 5.4 .

The PCI controller of cPCI/PCI-8554/R can receive two hardware IRQ sources. However, a PCI controller can generate only one IRQ to the PCI bus, the two IRQ sources are distinguished by the ISR software. If both IRQ are in use, the application software will invoke the “\_8554\_GET\_IRQ\_Status” function to distinguish which interrupt is inserted and servicing that IRQ. Users must then clear the current IRQ to allow the next IRQ be processed.

If the application needs only one IRQ, the other IRQ source can be disabled by software. If your application does not require any IRQ sources, you can disable both interrupts. However, the PCI BIOS will still assign an IRQ level to the PCI card and hence will still occupy the PC’s resources if you only disable the IRQ sources without changing the initial conditions of the PCI controller. It is however, not recommended that the user re-design the initial condition of the PCI card with the users’ own application software. If users want to disable the IRQ level, user can use the ADLINK utility ‘INIT8554.EXE’ to change the interrupt settings.

# 2.15 Digital Input and Output

To program the digital I/O operation is fairly straightforward. The digital input operation is used for reading data from its corresponding registers, and the digital output operation is used for writing data to its corresponding registers. The digital I/O registers‘ are discussed in section 3.4 and 3.5.

# 2.16 12V and 5V Power Supply

The 100-pin SCSI-II connector provides +12 and +5 volt power sources. To avoid shorts or overloads of the power sources, thermistors are added to all power supply rails. The current rating of the +5 volt supply thermistor is 500 mA. If the load current is larger than 500mA, the resistance of the thermistors will increase due to the temperature rise. The rising resistance drops the supply voltage and hence reduces the current. If the overload or short condition is cleared, the thermistor will return to normal operation. The +12V supply thermistor also has the same current rating characteristics as the +5V supply.

# 3

# Registers

Detailed descriptions of the registers are specified in this chapter. This information is useful for programmers who wish to handle the card with low-level programming. However, we suggest users to an understanding of the PCI interface before starting any low-level programming. In addition, the contents of this chapter will also help users understand how to use the software drivers to configure this card.

# 3.1 PCI PnP Registers

This PCI card functions as a 32-bit PCI target device to any master on the PCI bus. There are three types of registers: PCI Configuration Registers (PCR), Local Configuration Registers (LCR) and cPCI/PCI-8554/R registers.

The PCR, which is PCI-bus specifications compliant, is initialized and controlled by the plug & play (PnP) PCI BIOS. Users may obtain more information on the PCI BIOS specification to better understand the operation of the PCR. Please contact PCISIG to acquire the specifications of the PCI interface.

The PCI bus controller PCI-9030/9050 is provided by PLX technology Inc. (www.plxtech.com). For more information about the LCR, please visit PLX technology’s web site to download relative information. It is not necessary for users to fully understand the details of the LCR if the software library provided is used. The PCI PnP BIOS assigns the base address of the LCR. The assigned address is located at an offset of 14h from the PCR.

The cPCI/PCI-8554/R registers are discussed in the next section. The base address, which is also assigned by the PCI PnP BIOS, is located at an offset of 18h from the PCR. Therefore, users can read the address 18h from the PCR to obtain its base address by using the BIOS function call. Do not attempt to modify the base address and interrupt that have been assigned by the PCI PnP BIOS, it may cause resource conflicts with your system.

# 3.2 I/O Address Map

All cPCI/PCI-8554/R registers are 8 bits long. Users can access these registers using 8-bit I/O instructions. The following table shows the registers address map, including descriptions and their offset addresses relative to the base address.

<table><tr><td>I/O Address</td><td>Write</td><td>Read</td></tr><tr><td>Base + 0x00 ~ 0x03</td><td>Counter 1~3 &amp; Mode Control</td><td>Counter 1 ~ 3</td></tr><tr><td>Base + 0x04 ~ 0x07</td><td>Counter 4~6 &amp; Mode Control</td><td>Counter 4 ~ 6</td></tr><tr><td>Base + 0x08 ~ 0x0B</td><td>Counter 7~9 &amp; Mode Control</td><td>Counter 7 ~ 9</td></tr><tr><td>Base + 0x0C ~0x0F</td><td>Counter 10~12 &amp; Mode Control</td><td>Counter 10 ~ 12</td></tr><tr><td>Base + 0x10 ~ 0x12</td><td>Clock Mode Control</td><td>--</td></tr><tr><td>Base + 0x18</td><td>Digital Output</td><td>Digital Input</td></tr></table>

Table 4. I/O Address Map of cPCI/PCI-8554/R

# 3.3 Timer/Counter Registers

The 8254-chips occupies 4 I/O address locations on the cPCI/PCI-8554/R as shown below. Users can refer to Tundra's or Intel's data sheet for a full description of the 8254 features available at the following websites:

“http://support.intel.com/support/controllers/peripheral/231164.htm” or http://www.tundra.com (for Tundra’s 82C54 datasheet.)

Address: BASE + 0x00 \~ BASE + 0x0F

Attribute: read / write

Data Format:

<table><tr><td>Base + 0</td><td>Counter 1 Register (R/W)</td></tr><tr><td>Base + 1</td><td>Counter 2 Register (R/W)</td></tr><tr><td>Base + 2</td><td>Counter 3 Register (R/W)</td></tr><tr><td>Base + 3</td><td>8254 Mode Control Register (W)8254 Read Back Register (R)</td></tr><tr><td>Base + 4</td><td>Counter 4 Register (R/W)</td></tr><tr><td>Base + 5</td><td>Counter 5 Register (R/W)</td></tr><tr><td>Base + 6</td><td>Counter 6 Register (R/W)</td></tr><tr><td>Base + 7</td><td>8254 Mode Control Register (W)8254 Read Back Register (R)</td></tr><tr><td>Base + 8</td><td>Counter 7 Register (R/W)</td></tr><tr><td>Base + 9</td><td>Counter 8 Register (R/W)</td></tr><tr><td>Base + A</td><td>Counter 9 Register (R/W)</td></tr><tr><td>Base + B</td><td>8254 Mode Control Register (W)8254 Read Back Register (R)</td></tr><tr><td>Base + C</td><td>Counter 10 Register (R/W)</td></tr><tr><td>Base + D</td><td>Counter 11 Register (R/W)</td></tr><tr><td>Base + E</td><td>Counter 12 Register (R/W)</td></tr><tr><td>Base + F</td><td>8254 Mode Control Register (W)8254 Read Back Register (R)</td></tr></table>

Table 5. Timer/Counter Registers

# 3.4 Timer / Counter Clock Mode Control

There are a total of twenty-two bits on the cPCI/PCI-8554/R used for selecting clock sources for Timer/Counter 1 \~ 10, CK1 and the debounce system.

Address: BASE + 0x10 \~ 0x12

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Base+0x10</td><td>C4N2</td><td>C4N1</td><td>C3N2</td><td>C3N1</td><td>C2N2</td><td>C2N1</td><td>C1N2</td><td>C1N1</td></tr><tr><td>Base+0x11</td><td>C8N2</td><td>C8N1</td><td>C7N2</td><td>C7N1</td><td>C6N2</td><td>C6N1</td><td>C5N2</td><td>C5N1</td></tr><tr><td>Base+0x12</td><td>-</td><td>DBCSEL</td><td>-</td><td>CK1SEL</td><td>C10N2</td><td>C10N1</td><td>C9N2</td><td>C9N1</td></tr></table>

Table 6. Timer/Counter Clock Mode Control Register

CnN1and CnN2: These two bits are used to control clock source of Timer/Counter n, n = 1 \~ 10

CK1SEL: select source of CK1

DBCSEL: select debounce clock

# 3.5 Digital Input Register

There are 8 digital input channels on the cPCI/PCI-8554/R.

Address: BASE + 0x18

Attribute: read only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Base+0x18</td><td>DI7</td><td>DI6</td><td>DI5</td><td>DI4</td><td>DI3</td><td>DI2</td><td>DI1</td><td>DI0</td></tr></table>

Table 7. Digital Input Register

# 3.6 Digital Output Register

This register is a general-purpose 8 bits digital output port. These signals can be used to control external devices.

Address: BASE + 0x18

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Base+0x18</td><td>DO7</td><td>DO6</td><td>DO5</td><td>DO4</td><td>DO3</td><td>DO2</td><td>DO1</td><td>DO0</td></tr></table>

Table 8. Digital Output Register

4

# Signal Connections & Applications

This chapter describes the connectors and applications of the cPCI/PCI-8554/R including signal connections between the cPCI/PCI-8554/R and external devices.

# 4.1 Connectors Pin Assignment

The cPCI/PCI-8554/R comes equipped with a 100-pin SCSI-II female connector (CN1). CN1 is located at the rear plate. The pin assignment of the connector is illustrated in the Figure 4 and 5 of section 2.1.

# 4.2 Digital I/O Connection

The cPCI/PCI-8554/R provides 8 digital input and 8 digital output channels through CN1. The digital I/O signals are fully TTL compatible.

![Digital Input(DI)\nFrom TTL Devices\nDigital Output (DO)\nTo TTL Devices\nGND\nCPCI/PCI-8554/R\nOutside Device](.pci-8554-manual-1/69182d84ca19cc0736c9bd8c1e483ba0c7faba72b67ab41bf0002921f8a0e6bb.jpg)

Figure 19: Digital I/O Connection

# 4.3 Timer/Counter Connection

The cPCI/PCI-8554/R has four 8254 chips on board. It can offer 10 independent 16-bit programmable down counters with the option of cascading the counters. To implement your application, the following procedures should be followed.

1. Does the application require a fixed frequency, if answer is ‘No’, an external clock source must be used. Go to step 3.
2. Calculate the frequency of the clock according to your application requirements, then decide which clock source to use (internal, external, or cascaded), and then decide which counters to use.
3. If an external clock source is chosen, generate a clock signal external to the cPCI/PCI-8554/R card and measure its frequency. Determine whether the debounce function should be enabled or disabled, and then set JP1 \~ JP10. If reserved counters 11 and 12 are required, set JP12 and JP13 to pin 2-3.
4. Decide the gate control source: always enable or external controls, if gate control is necessary, connect the gate signal.

Note: Gate control of counter 11 and 12 are always enabled (tied to logic high) and there are no gate control pins for counters 11 and 12 on CN1.

5. Program the counter/timer using the desired mode.

# 4.4 Frequency Generator

# 4.4.1 To generate a 250 KHz Square Wave.

Step 1: Use a fixed clock source because the output is a fixed frequency.

Step 2: The internal 8MHz clock is capable of generating the 250KHz frequency. Use Counter 1 for this application.

$$
? 2 5 0 \mathrm{kHz} = 8 \mathrm{MHz} / 3 2
$$

Step 3: The gate source should be set to “enable” always and therefore GATE1 is let open (pin 99 of CN1).

Step 4: Connect the counter output to an external device and write the control program. Refer to $\mathrm { ^ { * } D E M O 1 . C } ,$ source code.

![The diagram depicts a logic circuit centered around a digital counter.\n\n**Main Component:**\n*   A rectangular block labeled '8254 Chip #1' at the top and 'Counter #1' inside.\n*   It has two inputs labeled 'C' (top) and 'G' (bottom).\n*   It has one output labeled 'o' (a small circle), which has a thick arrow pointing right labeled **COUT1**.\n\n**Inputs and Connections:**\n*   **Input 'C':** Connected to a small circle. This connection line is pointed to by the text `set by function '8554_SET_cntCLK'`.\n    *   The signal feeding into this circle comes from a cluster of vertical labels: **ECK1**, **GND**, **CK1**, and **COUT10**. Each label has a line ending in a small open circle.\n    *   Specifically, the line under **CK1** connects to the circle feeding input 'C'.\n*   **Input 'G':** Connected to a line labeled **'H'** with an adjacent **X**.\n\n**Left Side Signals:**\n*   Two input lines labeled **8MHz** and **COUT11** enter small circles on the far left.\n*   This section is annotated with `set by function '_8554_SET_CK1'`.\n*   Diagonal lines connect these left-most circles to the middle cluster (specifically towards the **CK1** and **COUT10** lines), suggesting a multiplexing or routing function controlled by the first function.](.pci-8554-manual-1/a46d4cd8806244a8f18765a47f75d31eb60a2d12c235011ab9c99becf6526edc.jpg)

Figure 20: Example of a frequency generator (1)

# 4.4.2 To generate a 1 pulse/1 hour signal

Step 1: Use a fixed clock source because the output is a fixed frequency.

Step 2: As the desired frequency is too slow, one counter will be unable to produce the desired frequency (1/3600sec=0.000278Hz. Therefore to reach this low frequency, cascade the independent counters 1, 2 and 3. Set the clock source of counter 1 to the internal 8MHz. Connect COUT1 to clock source of counter 2, and connect COUT2 to clock source of counter 3.

Step 3: Using the counter divider function, set counter 1 to 4000, counter 2 to 2000, and counter 3 to 3600.

$$
? 8 \mathrm{MHz} / 4 0 0 0 / 2 0 0 0 / 3 6 0 0 = 1 / 3 6 0 0,
$$

Hence COUT3 will generate a pulse every hour.

Step 4: The gate sources to enable always, hence GATE1, GATE2, and GATE3 are open.

Step 5: Write and verify the control program. Refer to ‘DEMO2.C’ source code.

![The diagram depicts a cascaded counter system composed of three identical blocks, each labeled '8254 Chip #1' and containing a specific counter.\n\n**Labeled Blocks:**\n*   **8254 Chip #1 / Counter #1** (Top)\n*   **8254 Chip #1 / Counter #2** (Middle)\n*   **8254 Chip #1 / Counter #3** (Bottom)\n\n**Connections:**\n\n**1. Top Section (Counter #1)**\n*   Inputs **8MHz** and **COUT11** merge at a node.\n*   This node connects to a switch with terminals labeled **ECK1**, **GND**, **CK1**, and **COUT10**.\n*   An arrow labeled 'set by function '_8554_SET_CK1'' points to the **CK1** terminal.\n*   The output connects to a second switch. An arrow labeled 'set by function '8554_SET_cntCLK'' points to the top input of this switch.\n*   An input labeled **'H'** (with an 'x' next to it) is present.\n*   The output enters **Counter #1**.\n*   Output **COUT1** exits to the right and loops back to the second section.\n\n**2. Middle Section (Counter #2)**\n*   Input **COUT1** (from the first counter) connects to a switch with terminals labeled **ECK2**, **COUT1**, **CK1**, and **COUT10**.\n*   An arrow points to the **COUT1** terminal.\n*   The output connects to a second switch. An arrow labeled 'set by function '8554_SET_cntCLK'' points to the top input of this switch.\n*   An input labeled **'H'** (with an 'x' next to it) is present.\n*   The output enters **Counter #2**.\n*   Output **COUT2** exits to the right and loops back to the third section.\n\n**3. Bottom Section (Counter #3)**\n*   Input **COUT2** (from the second counter) connects to a switch with terminals labeled **ECK3**, **COUT2**, **CK1**, and **COUT10**.\n*   An arrow points to the **COUT2** terminal.\n*   The output connects to a second switch. An arrow labeled 'set by function '8554_SET_cntCLK'' points to the top input of this switch.\n*   An input labeled **'H'** (with an 'x' next to it) is present.\n*   The output enters **Counter #3**.\n*   Output **COUT3** exits to the right.](.pci-8554-manual-1/ce53201da965d886af7e708e9587f58e2fcc255dea838846ad27a43413a9b6c4.jpg)

Figure 21: Example of frequency generator (2)

# 4.5 Pulse Width Measurement

Step 1: Use a fixed clock source as base time interval (or base frequency).

Step 2: Assuming an internal 2MHz clock is used. The time base is:

$$
D t = 1 / 2 \mathrm{M} = 5 \times 1 0 \mathrm{e} - 7 \mathrm{sec}
$$

The count range for measuring the pulse width is:

$$
D t &lt;   \text { pulse   width } &lt;   D t * 6 5 5 3 5 (= 3 2. 7 6 8 \mathrm{msec})
$$

If the specification of the pulse width to be measured is within the range, the 2MHz can be used.

Otherwise change the base frequency of the counter, for example, you can set counter 2 to cascaded mode, and use counter 2 to measure the pulse width. The count range will increase but the resolution will decrease. Counter 1, 2, and 3 are used in this example.

Step 3: Connect GATE1 to the signal to be measured.

Step 4: Write and verify the control program. Refer to ‘DEMO3.C’ source code.

![The flowchart depicts a digital circuit involving clock selection, debouncing, and pulse measurement using an 8254 chip.\n\n**Labeled Blocks:**\n*   **debounce system**: A rectangular block.\n*   **JP1**: A two-pin connector header.\n*   **8254 Chip #1**: A rectangular block containing the text 'Counter #1'.\n*   **Switches**: Two selector switches (one on the left, one rotary switch on the right).\n*   **Waveform**: A pulse diagram at the bottom.\n\n**Connections and Text:**\n*   **Left Side (Clock Selection & Debouncing):**\n    *   A switch selects between inputs labeled **2MHz** and **COUT11**.\n    *   An annotation points to this switch reading: `selectable by function '_8554_SET_DBCLK'`.\n    *   The output of this switch connects to the **debounce system**. This connection is labeled **DB_CLK**.\n    *   An input labeled **ECLK1** (with an arrow pointing down) connects into the **debounce system**.\n    *   The **debounce system** output connects to connector **JP1**.\n\n*   **Right Side (Counter Clock & Gate):**\n    *   A rotary switch selects between inputs labeled **ECK1**, **GND**, **CK1**, and **COUT10**.\n    *   An annotation points to this switch reading: `set by function '_8554_SET_cntCLK'`.\n    *   The output of this switch connects to the input labeled **c** of **8254 Chip #1**.\n    *   A line labeled **Signal to be measured** connects to the input labeled **G** of **Counter #1**.\n    *   The output labeled **o** of **Counter #1** exits the block as **COUT1**.\n\n*   **Bottom (Measurement Indication):**\n    *   A waveform diagram shows a pulse labeled **Pulse Width**.\n    *   An annotation points to the falling edge of the pulse reading: `Polling D/I for c end of a pulse`.](.pci-8554-manual-1/eb1f6620088c9a85434cd2b4f5135be9d5f4179e15bcb1eaa4dde82647a4e1f3.jpg)

Figure 22: Example of pulse width measurement

# 4.6 Frequency Measurement

To measure a frequency around 1\~100 KHz the following steps can be followed.

Step 1: This application requires two counters. One counter is used to generate a pulse with a precise time interval. The pulse is then used to enable the second counter (Counting counter). In this example the gate control is from COUT3 and cascaded counters configuration is used. The pulse generator is set to counter 3 (clock from COUT2) and counter 1 is used to measure the frequency.

Step 2: The maximum value of the counting counter is 65535. To measure a 100 KHz signal, the time interval must be within 1/100 KHz x 65535 = 0.655 seconds. If the time interval is wider, then the measurement resolution is better, however, the counting value will overflow if the time interval is too large. This means the low pulse width for counter 3 output should be shorter than 0.655 sec.

Step 3: Connect the signal to be measured to ECLK1 and adjust JP1 to allow the debounce function.

Step 4: Connect GATE1 to /COUT3.

Step 5: The following block diagram illustrates the application. Write and verify the control program. The frequency of the signal is:

Frequency = Counting value of counter 1/precise time interval

Refer to ‘DEMO4.C’ source code.

![This block diagram illustrates a digital timing circuit featuring two counters within a single chip (labeled '8254 Chip #1') and associated logic for clock selection and signal conditioning.\n\n**Labeled Blocks:**\n*   **8254 Chip #1 Counter #2** (Top block)\n*   **8254 Chip #1 Counter #1** (Bottom block)\n*   **debounce system**\n*   **JP1** (Connector)\n*   **XOR gates** (Top left logic)\n*   **Switches** (Four switch symbols distributed across the diagram)\n*   **Inverter** (Triangle symbol in the bottom right dashed box)\n\n**Text Labels:**\n*   'set by function '_8554_SET_CK1''\n*   '8MHz'\n*   'COUT11'\n*   'set by function '_8554_SET_cntCLK'' (appears twice)\n*   'ECK2', 'COUT1', 'CK1', 'COUT10' (Near top XOR gates)\n*   'Precise Time Interv'\n*   ''H''\n*   'ECLK1'\n*   'frequency to be measured'\n*   'DB_CLK'\n*   'ECK1', 'GND', 'CK1', 'COUT10' (Near JP1)\n*   '2MHz'\n*   'selectable by function '_8554_SET_DBCLK''\n*   'COUT1'\n*   '/COUT2'\n*   'connect by'\n*   ''H' enable counter #1'\n\n**Connections:**\n*   **Top Clock Generation:** Inputs '8MHz' and 'COUT11' feed into an XOR gate (labeled 'set by function '_8554_SET_CK1'''). The output feeds into a second XOR gate (labeled 'set by function '_8554_SET_cntCLK'''). The output of this chain goes to a switch, which then connects to the 'c' (Clock) input of **8254 Chip #1 Counter #2**. The output 'o' of this counter is labeled 'COUT2' and annotated with 'Precise Time Interv'.\n*   **Bottom Input Conditioning:** Input 'ECLK1 (frequency to be measured)' connects to the **debounce system**. A switch (labeled 'selectable by function '_8554_SET_DBCLK''') selects between '2MHz' and 'COUT11' and connects to the debounce system. The output 'DB_CLK' from the debounce system goes to connector **JP1** (specifically pin 'ECK1'). JP1 pins are labeled 'ECK1', 'GND', 'CK1', and 'COUT10'.\n*   **Counter #1 Clock:** Signal 'ECK1' from JP1 feeds into a switch (labeled 'set by function '_8554_SET_cntCLK'''). The output of this switch connects to the 'c' (Clock) input of **8254 Chip #1 Counter #1**. The output 'o' of this counter is labeled 'COUT1'.\n*   **Counter #1 Gate Enable:** The 'G' (Gate) input of Counter #1 is connected via a dashed line loop. This loop takes the 'COUT2' signal from the top counter, labels it '/COUT2', passes it through an inverter (triangle), and connects it to a terminal labeled 'connect by'. This terminal connects to the 'G' input. The text ''H' enable counter #1' indicates that a High signal enables this counter.](.pci-8554-manual-1/e90ed70f0ddf95708a4c6549168d5e3bcee54ec6ef9d6166cbca28fa9d8deac1.jpg)

Figure 23: Example of frequency measurement (1)

# 4.7 Event Counter

This example counts how many external events in 1 second

Step 1: This application requires one counter to generate a time base of 1 second and the second counter to count the event. Cascaded counters 11and 12 are used as a watchdog timer. Counter 1 is used in this example to count the external events. The clock source of counter 1 is the event signal so the frequency is not fixed.

Step 2: Connect ECLK1 to the signal to be measured and adjust JP1 to enable the debounce function.

Step 4: The gate source of counter 1 is always enabled, so the external gate is open.

Step 5: Write the control program. Refer to‘DEMO5.C’ source code.

![Based on the provided block diagram, here is the accurate description:\n\n**Top Section: Clock Selection and Debouncing**\n*   **Switch 1:** A switch labeled 'selectable by function '_8554_SET_DBCLK'' selects between inputs **2MHz** and **COUT11**. Its output is labeled **DB_CLK**.\n*   **Debounce System:** The **DB_CLK** signal and **ECLK1 ( Event Signal )** feed into the **debounce system** block.\n*   **Connector JP1:** The **ECLK1 ( Event Signal )** connects to the top of connector **JP1**. The **debounce system** outputs **ECK1** to the middle of **JP1** and connects to the bottom of **JP1**.\n*   **Switch 2:** A switch labeled 'selectable by function' selects from a vertical list of inputs: **ECK1**, **GND**, **CK1**, and **COUT10**. The output of this switch connects to the 'c' input of the next block.\n\n**Middle Section: Counter #1**\n*   **Block:** Labeled **8254 Chip #1** and **Counter #1**.\n*   **Connections:** The 'c' input receives the signal from Switch 2. The 'G' input is connected to **'H'**.\n*   **Output:** The output is labeled **COUT1**.\n\n**Bottom Section: Counter Chain**\n*   **Block 1:** Labeled **8254 Chip #4** and **Counter #11**.\n    *   Inputs: **8MHz** connects to 'c', and **'H'** connects to 'G'.\n    *   Output: Connects to the 'c' input of the next block.\n*   **Block 2:** Labeled **8254 Chip #4** and **Counter #12**.\n    *   Inputs: 'c' receives the output from Counter #11. **'H'** connects to 'G'.\n    *   Output: The final output is labeled **COUT12**.](.pci-8554-manual-1/b41a657c9ec12c81cb8ce4af41d5dde4a87018a96650ec14b26585e1161fceac.jpg)

Figure 24: Example of event counter

# 4.8 Dual Interrupt System

The cPCI/PCI-8554/R provides a dual interrupt source (one internal plus one external), which can be very useful in some applications. For example, most applications require a watchdog timer to monitor the system periodically; hence, an IRQ channel is used. An emergency control may also be necessary; therefore the external IRQ channel will come in handy.

![Based on the provided block diagram, here is a concise description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **8254 Chip #4** (containing **Counter #11**)\n*   **8254 Chip #4** (containing **Counter #12**)\n*   **IRQ Flip-Flops** (top right)\n*   **debounce system** (bottom left)\n*   **JP11** (connector)\n*   **IRQ Flip-Flops** (bottom middle)\n*   **PCI Controller** (bottom right)\n\n**Connections:**\n*   **Inputs to Counter #11:** '8MHz' and ''H'' connect to terminals **C** and **G** respectively.\n*   **Counter #11 to Counter #12:** Output **0** from Counter #11 connects to terminal **C** of Counter #12.\n*   **Inputs to Counter #12:** ''H'' connects to terminal **G**.\n*   **Counter #12 to IRQ Flip-Flops (top):** Output **COUT12** connects to the top **IRQ Flip-Flops**.\n*   **Clear Signal (top):** 'Clear by '8554_CLR_IRQ'' connects to the top **IRQ Flip-Flops**.\n*   **IRQ Flip-Flops (top) to PCI Controller:** Output connects to the **PCI Controller** via line labeled **INT1**.\n*   **Inputs to debounce system:** 'E_INT' and **DB_CLK** connect to the **debounce system**.\n*   **debounce system to JP11:** Output from the **debounce system** connects to input **JP11**.\n*   **JP11 to IRQ Flip-Flops (bottom):** Output **EXTINT** connects to the bottom **IRQ Flip-Flops**.\n*   **Clear Signal (bottom):** 'Clear by '8554_CLR_IRQ2'' connects to the bottom **IRQ Flip-Flops**.\n*   **IRQ Flip-Flops (bottom) to PCI Controller:** Output connects to the **PCI Controller** via line labeled **INT2**.](.pci-8554-manual-1/a6c0577942735a90702624e62f45a30e6cd750c65cc072eef5ee0bc15e861de6.jpg)

Figure 25: Example of dual interrupt system

# 5

# C/C++ Library

This chapter describes the software libraries for operating this card. Only the functions in the DOS library and Windows 95 DLL are described. Refer to the PCIS-DASK function reference manual, which is included in the ADLINK CD, for descriptions of Windows 98/NT/2000 DLL functions.

The function prototypes and useful constants are defined in the header files located in the LIB directory (DOS) and INCLUDE directory (Windows 95). For Windows 95 DLL, the developing environment can be Visual Basic 4.0 or above, Visual C/C++ 4.0 or above, Borland C++ 5.0 or above, Borland Delphi 2.x (32-bit) or above, or any Windows programming language that allows calls to a DLL.

# 5.1 Libraries Installation

Refer to the “Software Installation Guide” for information regarding software installation of libraries for DOS, Windows 95 DLL, or PCIS-DASK for Windows 98/NT/2000.

The device drivers and DLL functions for Windows 98/NT/2000 are included in the PCIS-DASK. Refer to the PCIS-DASK user’s guide and function reference, which is included in the ADLINK CD, for programming information.

# 5.2 Programming Guide

# 5.2.1 Naming Convention

The functions of the NuDAQ PCI or NuIPC CompactPCI card software drivers uses full-names to represent the functions' real meaning. The naming convention rules are:

# In DOS Environment:

\_{hardware\_model}\_{action\_name}. e.g. \_8554\_Initial().

In order to recognize the difference between the DOS library and Windows 95 library, a capital "W" is placed at the start of each function name for Windows 95 DLL drivers. e.g. W\_8554\_Initial().

# 5.2.2 Data Types

We have defined some data types in the Pci\_8554.h (DOS) and Acl\_pci.h (Windows 95) header files. These data types are used by the NuDAQ Cards’ library. We recommend you use these data types in your application programs. The following table shows the data type names and their range.

&lt;table&gt;<tr><td>Type Name</td><td>Description</td><td>Range</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td></tr><tr><td>U32</td><td>32-bit single-precision floating-point</td><td>0 to 4294967295</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>-1.797683134862315E308 to 1.797683134862315E309</td></tr><tr><td>Boolean</td><td>Boolean logic value</td><td>TRUE, FALSE</td></tr></table>

Table 9. Data types and their ranges

# 5.3 \_8554\_Initial

# @ Description

The cPCI/PCI-8554/R cards are initialized by this function. The software library could be used to control multiple cPCI/PCI-8554/R cards. Because the cPCI/PCI-8554/R is designed with the PCI bus architecture and meets the plug and play specifications, the IRQ and I/O address are assigned by system BIOS directly.

# @ Syntax

C/C++ (DOS)

U16 \_8554\_Initial (U16 \*existCards, PCI\_INFO \*pciinfo)

C/C++ (Windows 95)

U16 W\_8554\_Initial (U16 \*existCards, PCI\_INFO \*pciinfo)

# Visual Basic (Windows 95)

W\_8554\_Initial (existCards As Integer, pciInfo As PCI\_INFO) As Integer

# @ Arguments

# existCards:

The numbers of installed cPCI/PCI-8554/R cards. The returned value shows how many cPCI/PCI-8554/R cards are installed in the system.

# pciinfo:

This structure stores the PCI bus plug and play initialization information, which is determined by PnP BIOS. The PCI\_INFO structure is defined in the PCI\_8554.H header file. The base I/O address and the interrupt channel number is stored in pciinfo for reference.

# @ Return Value

ERR\_NoError, ERR\_PCIBiosNotExist

# 5.4 \_8554\_Write\_Counter

# @ Description

User can directly write commands to counters 1\~12 using this function. Using this function, user can also re-assign the counter numbers 1\~12 in any order

# @ Syntax

```txt
C/C++ (DOS)
```

U16 \_8554\_Write\_Counter (U16 cardNo, U16 cntNo, U16 mode, U16 cntrVal)

```txt
C/C++ (Windows 95)
```

U16 W\_8554\_Write\_Counter (U16 cardNo, U16 cntNo, U16 mode, U16 cntrVal)

# Visual Basic (Windows 95)

W\_8554\_Write\_Counter (ByVal cardNo As Integer, ByVal cntNo As Integer, ByVal mode As Integer, ByVal cntrVal As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

cntNo: Counter/Timer number. This value must be between 1 and 12.

mode: Counter operation mode. This value must be between 0 and 5.

cntrVal: The counter value to be written to the counter.

# @ Return Value

```txt
ERR_NoError
```

```txt
ERR_BoardNoInit
```

ERR\_InvalidCounterNo: cntNo is out of range.

ERR\_TimerMode: mode is out of range

# 5.5 \_8554\_Read\_Counter

# @ Description

User can directly read counter information with this function.

# @ Syntax

C/C++ (DOS)

U16 \_8554\_Read\_Counter (U16 cardNo, U16 cntNo, U16 \*mode, U16 \*cntrVal)

C/C++ (Windows 95)

U16 W\_8554\_Read\_Counter (U16 cardNo, U16 cntNo, U16 \*mode, U16 \*cntrVal)

# Visual Basic (Windows 95)

W\_8554\_Read\_Counter (ByVal cardNo As Integer, ByVal cntNo As Integer, mode As Integer, cntrVal As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

cntNo: Counter/Timer number. This value must be between 1 and 12.

mode: Counter operation mode.

cntrVal: Counter value read back from counter

# @ Return Value

ERR\_NoError, ERR\_BoardNoInit

ERR\_InvalidCounterNo: cntNo is out of range.

# 5.6 \_8554\_Stop\_Counter

# @ Description

User can directly stop the counter with this function. This function will stop the counter by setting the counter to mode 5.

# @ Syntax

```txt
C/C++ (DOS)
```

U16 \_8554\_Stop\_Counter (U16 cardNo,U16 cntNo,U16 \*cntrVal)

```txt
C/C++ (Windows 95)
```

U16 W\_8554\_Stop\_Counter (U16 cardNo,U16 cntNo,U16 \*cntrVal)

# Visual Basic (Windows 95)

W\_8554\_Stop\_Counter (ByVal cardNo As Integer, ByVal cntNo As Integer, cntrVal As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

cntNo: Counter/Timer number. This value must be between 1 and 12.

cntrVal: Counter value read back from counter

# @ Return Value

ERR\_NoError , ERR\_BoardNoInit

ERR\_InvalidCounterNo: if cntNo is not in the range of 1 \~ 12

# 5.7 \_8554\_Read\_Status

# @ Description

User can directly read current counter status with this function.

# @ Syntax

C/C++ (DOS)

U16 \_8554\_Read\_Status (U16 cardNo, U16 cntNo, U16 \* cntrVal, U16 \*status)

C/C++ (Windows 95)

U16 W\_8554\_ Read\_Status (U16 cardNo, U16 cntNo, U16 \* cntrVal, U16 \*status)

# Visual Basic (Windows 95)

W\_8554\_Read\_Status (ByVal cardNo As Integer, ByVal cntNo As Integer, cntrVal As Integer, status As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

cntNo: Counter/Timer number. This value must be between 1 and 12.

cntrVal: Counter value read back from counter

status: current status read back from counter, refer to 8254’s datasheet for more information

# @ Return Value

ERR\_NoError, ERR\_BoardNoInit

ERR\_InvalidCounterNo: if cntNo is not in the range of 1 \~ 12

# 5.8 \_8554\_DO

# @ Description

Write an 8 -bit data to the digital output port.

# @ Syntax

C/C++ (DOS)

U16 \_8554\_DO (U16 cardNo, U16 doData)

C/C++ (Windows 95)

U16 W\_8554\_DO (U16 cardNo, U16 doData)

# Visual Basic (Windows 95)

W\_8554\_DO (ByVal cardNo As Integer, ByVal doData As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

doData: the value to be written to d igital output port

# @ Return Value

ERR\_NoError

ERR\_PCIBiosNotExist

# 5.9 \_8554\_DI

@ Description

Read an 8 -bit data from the digital input port.

@ Syntax

C/C++ (DOS)

U16 \_8554\_DI (U16 cardNo, U16 \*diData)

C/C++ (Windows 95)

U16 W\_8554\_DI (U16 cardNo, U16 \*diData)

Visual Basic (Windows 95)

W\_8554\_DI (ByVal cardNo As Integer, diData As Integer) As Integer

@ Arguments

cardNo: card number to be selected

doData: the value read from the digital input port

@ Return Value

ERR\_NoError, ERR\_BoardNoInit

# 5.10 \_8554\_SET\_cntCLK

# @ Description

This function is used to select the clock source for counters 1\~10 (Clock source for counter 11 is 8MHz and clock source of counter 12 is from COUT11, both clock sources are fixed).

# @ Syntax

```txt
C/C++ (DOS)
```

U16 \_8554\_DI (U16 cardNo, U16 cntNo, U16 clkMODE)

```txt
C/C++ (Windows 95)
```

U16 W\_8554\_DI (U16 cardNo, U16 cntNo, U16 clkMODE)

# Visual Basic (Windows 95)

W\_8554\_SET\_cntCLK (ByVal cardNo As Integer, ByVal cntNo As Integer, ByVal clkMODE As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

cntNo: Counter/Timer number. This value must be between 1 and 10.

clkMODE: Select clock sources:

```txt
“0” = ECLKn.
```

```txt
“1” = COUTn-1.
```

```txt
“2” = CK1.
```

```txt
“3” = COUT10.
```

# @ Return Value

ERR\_NoError

ERR\_BoardNoInit

ERR\_InvalidCounterNo: cntNo is not in the range of 1 \~ 12

ERR\_InvalidMode: clkMODE is not in the range of 0 \~ 3

# 5.11 \_8554\_SET\_CK1

@ Description

Select source for CK1.

@ Syntax

C/C++ (DOS)

U16 \_8554\_SET\_CK1 (U16 cardNo, U16 selCK1)

C/C++ (Windows 95)

U16 W\_8554\_SET\_CK1 (U16 cardNo, U16 selCK1)

Visual Basic (Windows 95)

W\_8554\_SET\_CK1 (ByVal cardNo As Integer, ByVal selCK1 As Integer) As Integer

@ Arguments

cardNo: card number to be selected

selCK1: if selCK1 is set to “0” then CK1 = C8M, and if set to “1” then CK1 = COUT11

@ Return Value

ERR\_NoError

ERR\_BoardNoInit

ERR\_InvalidMode: selCK1 is out of range

# 5.12 \_8554\_SET\_DBCLK

@ Description

Select debounce clock.

@ Syntax

C/C++ (DOS)

U16 \_8554\_SET\_DBCLK (U16 cardNo, U16 DBCLK)

C/C++ (Windows 95)

U16 W\_8554\_SET\_DBCLK (U16 cardNo, U16 DBCLK)

Visual Basic (Windows 95)

W\_8554\_SET\_DBCLK (ByVal cardNo As Integer, ByVal DBCLK As Integer) As Integer

@ Arguments

cardNo: card number to be selected

DBCLK: if dbclk is set to “0” then DB\_CLK = COUT11, and if set to “1” then DB\_CLK = 2MHz

@ Return Value

ERR\_NoErro, ERR\_BoardNoInit

ERR\_InvalidMode: DBCLK is out of range

# 5.13 \_8554\_Set\_INT\_Control

# @ Description

The cPCI/PCI-8554/R has a dual interrupts system. Two interrupt sources can be generated and be checked by the software. This function is used to select and control the cPCI/PCI-8554/R interrupt sources. The interrupt source can either come from counter 12’s output, COUT12 (INT1) or from an external interrupt signal EXTINT (INT2).

# @ Syntax

```txt
C/C++ (DOS)
```

```txt
U16 _8554_Set_INT_Control (U16 cardNo, U16 int1Flag, U16 int2Flag)
```

```txt
C/C++ (Windows 95)
```

```txt
U16 W_8554_Set_INT_Control (U16 cardNo, U16 int1Flag, U16 int2Flag)
```

# Visual Basic (Windows 95)

W\_8554\_Set\_INT\_Control (ByVal cardNo As Integer, ByVal int1Falg As Integer, ByVal int2Falg As Integer)

# @ Arguments

cardNo: card number to be selected

int1Flag: INT1 setting; 0: disable, 1: enable

int2Flag: INT2 setting; 0: disable, 1: enable

# 5.14 \_8554\_Get\_IRQ\_Status

# @ Description

The cPCI/PCI-8554/R has dual interrupts system. Two interrupt sources can be generated and be checked by the software. This function is used to distinguish which interrupt has been inserted if both INT1 and INT2 interrupts are used.

# @ Syntax

C/C++ (DOS)

U16 \_8554\_Get\_IRQ\_Status (U16 cardNo, U16 \*ch1, U16 \*ch2)

C/C++ (Windows 95)

U16 W\_8554\_Get\_IRQ\_Status (U16 cardNo, U16 \*ch1, U16 \*ch2)

# Visual Basic (Windows 95)

W\_8554\_Get\_IRQ\_Status (ByVal cardNo As Integer, ch1 As Integer, ch2 As Integer)

# @ Arguments

cardNo: card number to be selected

ch1: INT1 status; 0: interrupt is not from INT1, 1: interrupt is from INT1

ch2: INT2 status; 0: interrupt is not from INT2, 1: interrupt is from INT2

# 5.15 \_8554\_INT\_Enable

# @ Description

This function is only available to the Windows 95 driver. It is used to activate the interrupt controller. After calling this function, every time an interrupt request signal is generated, a software event is signaled.

# @ Syntax

C/C++ (Windows 95)

U16 W\_8554\_INT\_Enable (U16 cardNo, HANDLE \*hEvent)

# Visual Basic (Windows 95)

W\_8554\_INT\_Enable (ByVal cardNo As Integer, hEvent As Long) As Integer

# @ Arguments

cardNo: card number to be selected

hEvent: the address of an array for two handles. HEvent[0] and hEvent[1] are the events for interrupt signals INT1 and INT2 respectively.

# @ Return Value

ERR\_NoError

ERR\_BoardNoInit

# 5.16 \_8554\_INT\_Disable

# @ Description

This function is only available to the Windows 95 driver. It is used to disable the generation of an interrupt signal.

# @ Syntax

C/C++ (Windows 95)

U16 W\_8554\_INT\_Disable (U16 cardNo)

# Visual Basic (Windows 95)

W\_8554\_INT\_Disable (ByVal cardNo As Integer) As Integer

# @ Arguments

cardNo: card number to be selected

# @ Return Value

ERR\_NoError, ERR\_BoardNoInit

# 5.17 \_8554\_CLR\_IRQ1

# @ Description

This function is only available to the DOS driver. It is used to clear the interrupt request, which is generated by INT1. You should use this function to clear the interrupt request status; otherwise the new incoming interrupt will not be generated.

# @ Syntax

C/C++ (Windows 95)

U16 \_8554\_CLR\_IRQ1 (U16 cardNo)

# @ Arguments

cardNo: card number to be selected

# 5.18 \_8554\_CLR\_IRQ2

# @ Description

This function is only available to the DOS driver. It is used to clear the interrupt request, which is generated by INT2. You should use this function to clear the interrupt request status; otherwise the new incoming interrupt will not be generated.

# @ Syntax

C/C++ (Windows 95)

U16 \_8554\_CLR\_IRQ2 (U16 cardNo)

# @ Arguments

cardNo: card number to be selected

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK’s products, please read the user manual and follow the instructions carefully. When sending in damaged products for repair, please attach an RMA application form.
2. All ADLINK products come with a two-year guarantee, free of repair charge.

The warranty period starts from the product’s shipment date from ADLINK’s factory
Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers’ warranty
End users requiring maintenance services should contact their local dealers. Local warranty conditions will depend on the local dealers

3. Our repair service does not cover the two-year guarantee while damages are caused by the following:

a. Damage caused by not following instructions in the user menus.
b. Damage caused by carelessness on the users’ part during product transportation.
c. Damage caused by fire, earthquakes, floods, lightening, pollution and incorrect usage of voltage transformers.
d. Damage caused by unsuitable storage environments with high temperatures, high humidity or volatile chemicals.
e. Damage caused by leakage of battery fluid when changing batteries.
f. Damages from improper repair by unauthorized technicians.
g. Products with altered and damaged serial numbers are not entitled to our service.
h. Other categories not protected under our guarantees.

4. Customers are responsible for the fees regarding transportation of damaged products to our company or to the sales office.

5. To ensure the speed and quality of product repair, please download an RMA application form from our company website www.adlinktech.com. Damaged products with RMA forms attached receive priority.

For further questions, please contact our FAE staff.

ADLINK: service@adlinktech.com

Test & Measurement Product Segment: NuDAQ@adlinktech.com

Automation Product Segment: Automation@adlinktech.com

Computer & Communication Product Segment:

NuPRO@adlinktech.com; NuIPC@adlinktech.com
[🔗 Link to the original document](.pci-8554-manual-1/pci-8554-manual-1.pdf)