# NuDAQ® PCI-9111DG/HR

# Multifunction

# Data Acquisition Card

User's Manual

Manual Revision: 2.6

Revision Date: March 16, 2022

Part No: 50M-00069-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.50</td><td>April 4, 2003</td><td>Updated release</td></tr><tr><td>2.6</td><td>March 16, 2022</td><td>Product update release</td></tr></table>

# Preface

Copyright © 2022 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental Protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays an icon featuring a white document sheet with a folded upper-left corner and faint horizontal lines running across the bottom portion. A large, bold red checkmark is superimposed over the center of the document, angled upwards from left to right.](.pci-9111-50m-00069-1000-26/dd9d3f15bc8c2e7860e67765875a764621889547d84ba782c7f6d6e556d8957c.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a thick black border containing a large black exclamation point in the center.](.pci-9111-50m-00069-1000-26/72dc39bbe8a805d88e088c00291d08c12c4297d46b373a26ab26ced75a1d07ec.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image features a red triangle containing a white exclamation mark (!).](.pci-9111-50m-00069-1000-26/1a9436ded069856fd1f53c8d306ff320d56c018aaf6bbdffddcccd295cf0fb11.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface.... iii

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 3
1.4 Software Support 5

# 2 Getting Started 11

2.1 Package Contents 12
2.2 Device Layout and I/O Connectors.... 13
2.3 Jumper Settings.... 14
2.4 Connector Pin Assignments 15
2.5 Hardware Installation Outline.... 18
2.6 Device Installation for Windows Systems 20
2.7 Daughter Board Connection 21

# 3 Operation Theory 25

3.1 A/D Conversion.... 26
3.2 Extended Digital I/O Port 38
3.3 D/A Conversion.... 39
3.4 Digital Input and Output 41
3.5 Timer/Counter Operation 42

# Important Safety Instructions 43

# Getting Service.... 47

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# 1 Introduction

The PCI-9111 is an advanced data acquisition card based on the 32-bit PCI bus architecture. High performance designs and state-of-the-art technology make this card ideal for data logging and signal analysis applications in areas like medicine and process control.

# 1.1 Features

The PCI-9111 PCI bus advanced data acquisition card provides the following advanced features:

▶ 32-bit PCI bus
▶ 12-bit analog input resolution for PCI-9111DG
16-bit analog input resolution for PCI-9111HR
▶ Auto-scanning channel selection up to 256 channels
▶ Up to 100KHz A/D sampling rates
▶ 16 single-ended analog input channels
▶ Bipolar input signals
▶ Programmable gain of x1, x2, x4, x8, x16
Input Range: ±10V, ±5V, ±2.5V, ±1.25V, ±0.625V
▶ On-chip sample & hold
▶ One 12-bit monolithic multiplying analog output channel
▶ 16 digital output and 16 digital input channels
▶ 4 extended digital input and digital output channels on the 37-pin connector
▶ 3 independent programmable 16-bit down counters
▶ Three A/D trigger modes: software trigger, programmable pacer trigger, and external pulse trigger
▶ Pre-trigger & Post-trigger Control
▶ Integral DC-to-DC converter for stable analog power source
▶ 37-pin D-type connector
▶ Compact size: half-size PCB

# 1.2 Applications

▶ Industrial and laboratory ON/OFF control
▶ Energy management
▶ Communication
▶ 16 TTL/DTL compatible digital input channels
▶ Security controller
▶ Product testing
▶ Event and frequency counting
▶ Waveform and pulse generation
▶ BCD interface driver

# 1.3 Specifications

<table><tr><td colspan="4">Analog Input (A/D)</td></tr><tr><td>Converter</td><td colspan="3">B.B. ADS7805 / ADS7804 or equivalent, successive approximation type</td></tr><tr><td>Resolution</td><td colspan="3">12-bit/16-bit</td></tr><tr><td>Input Channels</td><td colspan="3">16 Single-ended</td></tr><tr><td>Analog Signal Input Range (Programmable)</td><td colspan="3">Bipolar: ±10V, ± 5V, ±2.5V, ±1.25V, ±0.625V</td></tr><tr><td>Conversion Time</td><td colspan="3">8 μ sec</td></tr><tr><td>Over-voltage Protection</td><td colspan="3">Continuous ±35V max.</td></tr><tr><td rowspan="6">Accuracy</td><td>Gain</td><td>Range</td><td>Accuracy (mv)</td></tr><tr><td>1</td><td>±10v</td><td>1±0.3051</td></tr><tr><td>2</td><td>±5v</td><td>0.5±0.1525</td></tr><tr><td>4</td><td>±2.5v</td><td>0.5±0.0763</td></tr><tr><td>8</td><td>±1.25v</td><td>0.25±0.0381</td></tr><tr><td>16</td><td>±0.625v</td><td>0.25±0.019</td></tr><tr><td>Input Impedance</td><td colspan="3">10 MΩ</td></tr><tr><td>Trigger Modes</td><td colspan="3">Software, Timer Pacer, and External trigger</td></tr><tr><td>Data Transfer</td><td colspan="3">Pooling, FIFO half-full Interrupt</td></tr><tr><td>Data Throughput</td><td colspan="3">110KHz (maximum)</td></tr><tr><td>FIFO Depth</td><td colspan="3">1024 samples</td></tr><tr><td colspan="4">Analog Output (D/A)</td></tr><tr><td>Output Channels</td><td colspan="3">1</td></tr><tr><td>Resolution</td><td colspan="3">12-bit</td></tr><tr><td>Output Range (jumper selectable)</td><td colspan="3">Unipolar: 0-10VBipolar: -10V to +10V</td></tr><tr><td>Converter</td><td colspan="3">DAC7541 or equivalent, monolithic multiplying</td></tr><tr><td>Settling Time</td><td colspan="3">30 μ sec</td></tr><tr><td>Linearity</td><td colspan="3">±1/2-bit LSB</td></tr><tr><td>Output Driving Capability</td><td colspan="3">±5mA max.</td></tr></table>

<table><tr><td colspan="2">Digital I/O (DIO)</td></tr><tr><td>Channels</td><td>16 TTL compatible inputs and outputs</td></tr><tr><td>Input Voltage</td><td>Low: Min. 0V, Max. 0.8VHigh: Min. +2.0V, Max. 5.5V</td></tr><tr><td>Input Load</td><td>Low: +0.8V at -0.2mA max.High: +2.7V at +20mA max.</td></tr><tr><td>Output Voltage</td><td>Low: Min. 0V, Max. 0.4VHigh: Min. +2.4V, Max. 5.5V</td></tr><tr><td>Driving Capacity</td><td>Low: Max. +0.5V at 8.0mA (Sink)High: Min. +2.7V at 0.4mA (Source)</td></tr><tr><td colspan="2">Extended Digital I/O (EDIO)</td></tr><tr><td>Channels</td><td>4 inputs and outputs</td></tr><tr><td>Input Voltage</td><td>Low: +0.8V @ -10μA max.High: +3.5V @ +10μA max.</td></tr><tr><td>Input Load</td><td>Low: Min: -0.5V; Max. 0.8VHigh: Min: +1.7V; Max. 5.75V</td></tr><tr><td>Output Driving Capability</td><td>Low: Max. +0.4V @ 8.0mA (Sink)High: Min. 2.4V @ 4.0mA (Source)</td></tr><tr><td colspan="2">Programmable Counter</td></tr><tr><td>A/D pacer timer</td><td>32-bit timer (two 16-bit counters cascaded together) with a 2MHz time base</td></tr><tr><td>Pacer Frequency Range</td><td>0.00046 Hz to 100K Hz</td></tr><tr><td>Pre-trigger Counter</td><td>One 16-bit counter for AD Conversion Pulse</td></tr><tr><td colspan="2">General</td></tr><tr><td>Connector</td><td>37-pin D-type connector</td></tr><tr><td>Operating Temperature</td><td>0°C to 60°C</td></tr><tr><td>Storage Temperature</td><td>-20°C to 80°C</td></tr><tr><td>Humidity</td><td>5% to 90% relative humidity, non-condensing</td></tr><tr><td>Power Requirement</td><td>+5 V @ 570 mA typical</td></tr><tr><td>Dimensions</td><td>105mm (H) X 175mm (L)</td></tr></table>

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license. The ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platform. By leveraging the sophisticated architecture in low-level kernel management and user friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![This diagram illustrates a software and hardware architecture stack, divided into three main horizontal sections.\n\n**Top Section (Software Layers)**\nThis section is divided into a left column and three right-hand columns.\n\n*   **Left Column (Red Background):** Titled 'MAPS Core Device Management,' this column contains four stacked grey blocks reading:\n    *   'Device Manager (ACE)'\n    *   'PXI Platform Resource Mgmt. Utility'\n    *   'PXI Platform ChassisWatch Utility'\n    *   'DAQ/IO Module Function Test Utility'\n*   **Right Section (White Background):** Three columns represent application development environments. Above each is a 'User APPs' block, and below it is a corresponding SDK block:\n    *   **Column 1:** Top text 'User APPs in C/C++'. Below is an orange block labeled 'MAPS/C' with text 'C/C++ SDK for DAQ/IO module'.\n    *   **Column 2:** Top text 'User APPs in LabVIEW'. Below is a green block labeled 'MAPS/LV' with text 'LabVIEW SDK for DAQ/IO module'.\n    *   **Column 3:** Top text 'User APPs in C#'. Below is a purple block labeled 'MAPS/C#' with text 'C# SDK for DAQ/IO module' and 'Coming soon'.\n\n**Middle Section (Runtime Layer)**\nA red horizontal bar separates the software and hardware layers.\n*   On the left, it is labeled 'MAPS Core -Device Runtime'.\n*   On the right, it lists services: 'PXI Platform Service', 'DAQ/IO Module Device Driver', and 'DAQ/IO Module Runtime Library'.\n\n**Bottom Section (Hardware Layer)**\nA blue horizontal section displays images of physical hardware devices. From left to right, the labels beneath the images are:\n*   'Digitizers'\n*   'DAQ'\n*   'Edge Platform'\n*   'PXle Controllers'\n*   'PXle/PCI Chassis'](.pci-9111-50m-00069-1000-26/cb51952cb81091010cda659fb3524d51a2a420deb99f90dee058d17f5c581f44.jpg)

Figure 1-1: ADLINK MAPS Architecture

# 1.4.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed in a user-provided PC, the operating system can identify ADLINK's devices and assign necessary resources for low-level access, such as IO read/write or direct memory access. MAPS/Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCI9111 Device 'PCI-9'\nUSB\nGeneral\nSettings\nAlias Name PCI-9111-1-0\nVendor ADLINK Technology Inc.\nModel PCI9111 Device\nPCI Bus 5\nPCI Device 0\nPCI Function 0\nDMA Buffer\nAI 64 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch](.pci-9111-50m-00069-1000-26/91e05bbab95c1da2c954358128e832a9f8315f31b2490df9dde00845fc4fe8d8.jpg)

Figure 1-2: ADLINK MAPS Core

MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules. For example, the user can reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCI9111 Device 'PCI-9'\nUSB\nGeneral\nSettings\nAlias Name PCI-9111-1-0\nVendor ADLINK Technology Inc.\nModel PCI9111 Device\nPCI Bus 5\nPCI Device 0\nPCI Function 0\nDMA Buffer\nAI 64 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nUtility\nSoftFrontPanel Launch](.pci-9111-50m-00069-1000-26/77bc923dcfaf59a8d76744b40167ee6aeea87368ebd1687402d954866f4740ae.jpg)

Figure 1-3: ADLINK Connection Explorer (ACE)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. By clicking the Launch button in the lowest "Utility" block, this soft-front panel allows users to control digitizers through the UI and display the acquired waveform/data on the screen.

![| Time (Sec) | Voltage (Vpp) |\n| ---------- | ------------- |\n| 0.00       | 4             |\n| 0.01       | 0             |\n| 0.02       | -4            |\n| 0.03       | -6            |\n| 0.04       | -4            |\n| 0.05       | 0             |\n| 0.06       | 4             |\n| 0.07       | 6             |\n| 0.08       | 4             |\n| 0.09       | 0             |\n| 0.10       | -6            |](.pci-9111-50m-00069-1000-26/19ac198c748f859a06b5720adfe2df6ea84a90131a02bd0af815623d077a0c93.jpg)

Figure 1-4: ACE Soft Front Panel

# 1.4.2 MAPS/LV, LabVIEW Support

Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual:

https://www.adlinktech.com/Products/Data\_Acquisition/DAQSoftware\_Utility/MAPS\_LV

# 1.4.3 MAPS/C, C & C++ Support

Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

https://www.adlinktech.com/Products/Data\_Acquisition/DAQSoftware\_Utility/MAPS\_C

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# 2 Getting Started

This chapter describes the proper installation environment, installation procedures, package contents and basic information users should be aware of.

![The image displays a graphic of a white document featuring horizontal lines and a folded top-right corner. A large, bold red checkmark is superimposed over the center of the document.](.pci-9111-50m-00069-1000-26/6fb159eed295afceda12b6211620ba9c3b30c2e6d9f9d8e71e0b73ed37afa835.jpg)
NOTE:

Diagrams and images of equipment illustrated are for reference only. Actual system configuration and specifications may vary.

# 2.1 Package Contents

Before continuing, check the package contents for any damage and check if the following items are included in the packaging:

PCI-9111 Multifunction Data Acquisition Card
ADLINK CD
PCI-9111 User's Manual

The card contains electro-static sensitive components that can easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Inspect the module for any damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

![The image displays a standard warning sign. It features a red triangle with a white exclamation point in the center. Below the triangle, the word 'WARNING' is written in black capital letters.](.pci-9111-50m-00069-1000-26/6b1937cde6d445cc74d1236adfbf8579d67437095b05ec8ed0499f237bf8790e.jpg)

WARNING: DO NOT install or apply power to equipment that is damaged or if there are missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Device Layout and I/O Connectors

![Circuit schematic diagram with labeled components and connectors, including ICs, resistors, capacitors, and connectors](.pci-9111-50m-00069-1000-26/36a8538a32af77486e55df200cc8bc17a7fc9a704ed1c8bf19c5226e2e026f34.jpg)

Figure 2-1: PCB Layout

# 2.3 Jumper Settings

There is only one configurable jumper (JP1) available on the PCI-9111 card used to set the range for the analog output channel. The analog output range can be uni-polar (0 to 10V) or bi-polar (-10V to +10V). The default setting is bi-polar. See table below for setting possibilities.

<table><tr><td>Bi-polar analog output range -10V to +10V</td><td>&lt;img src="images/2cf048fcee3f5ad54d0bd72d59248ef51a19f8816555ec26f1e37b05548cd184.jpg"/&gt;</td></tr><tr><td>Uni-polar analog output range 0V to +10V</td><td>&lt;img src="images/8b975e0be58260297b7c09d324f0bf03787eb882644c11afe7888ad752ee7d4b.jpg"/&gt;</td></tr></table>

Table 2-1: Analog Output Range Setting

# 2.4 Connector Pin Assignments

The PCI-9111 comes equipped with two 20-pin insulation displacement connectors (CN1 and CN2) and one 37-pin D-type connector (CN3). CN1 and CN2 are located on the board and CN3 is located on the faceplate.

CN1 is for digital signal input, CN2 is for digital signal output, and CN3 is for analog input/output, extended digital I/O, and timer/counter signals.

# 2.4.1 CN1/CN2: Digital Signal Input/Output

CN1 and CN2 are 20-pin insulation displacement connectors for digital signal input/output with the following pin assignments.

![DI 0 —— 1 2 —— DI 1\nDI 2 —— 3 4 —— DI 3\nDI 4 —— 5 6 —— DI 5\nDI 6 —— 7 8 —— DI 7\nDI 8 —— 9 10 —— DI 9\nDI 10 —— 11 12 —— DI 11\nDI 12 —— 13 14 —— DI 13\nDI 14 —— 15 16 —— DI 15\nGND —— 17 18 —— GND\n+5V —— 19 20 —— +12V](.pci-9111-50m-00069-1000-26/9c6ad7744f588ddb98265dfcce000e156a09e1039bd292144d39e907b2860aaf.jpg)

Figure 2-2: CN1 Pin Assignments

![DO 0 —— 1 2 —— DO 1\nDO 2 —— 3 4 —— DO 3\nDO 4 —— 5 6 —— DO 5\nDO 6 —— 7 8 —— DO 7\nDO 8 —— 9 10 —— DO 9\nDO 10 —— 11 12 —— DO 11\nDO 12 —— 13 14 —— DO 13\nDO 14 —— 15 16 —— DO 15\nGND —— 17 18 —— GND\n+5V —— 19 20 —— +12V](.pci-9111-50m-00069-1000-26/6745c0ddf4e231c1c5c564dd56723b5be24f01094a18b7488d67fa2c9701b28f.jpg)

Figure 2-3: CN2 Pin Assignments

<table><tr><td>Signal Name</td><td>Description</td></tr><tr><td>DI n</td><td>Digital Input signal channel n</td></tr><tr><td>DO n</td><td>Digital Output signal channel n</td></tr><tr><td>GND</td><td>Digital Ground</td></tr></table>

Table 2-2: CN1/CN2 Pin Assignment Legend

# 2.4.2 CN3: Analog Input/Output, Extended I/O Connector

CN3 is a 37-pin D-type connector with the following pin assignments.

![| Category | Pin Number |\n|---|---|\n| N/C | 37 |\n| EDO2 | 36 |\n| EDO0 | 35 |\n| EDI3 | 34 |\n| EDI2 | 33 |\n| EDI1 | 32 |\n| EDI0 | 31 |\n| DA Out | 30 |\n| A.GND | 29 |\n| A.GND | 28 |\n| AI15 | 27 |\n| AI14 | 26 |\n| AI13 | 25 |\n| AI12 | 24 |\n| AI11 | 23 |\n| AI10 | 22 |\n| AI9 | 21 |\n| AI8 | 20 |\n19 | +5V |\n| 18 | EDO3 |\n| 17 | EDO1 |\n| 16 | ExtTrg |\n| 15 | D.GND |\n| 14 | D.GND |\n| 13 | +12V |\n| 12 | PreTrg |\n| 11 | N/C |\n| 10 | A.GND |\n| 9 | A.GND |\n| 8 | AI7 |\n| 7 | AI6 |\n| 6 | AI5 |\n| 5 | AI4 |\n| 4 | AI3 |\n| 3 | AI2 |\n| 2 | AI1 |\n| 1 | AI0 |](.pci-9111-50m-00069-1000-26/0657495f98eeb04221331e4f739994de9b3059b39cf19ac27394ef2b6ebe3900.jpg)

Figure 2-4: CN3 Pin Assignments

<table><tr><td>Signal Name</td><td>Description</td></tr><tr><td>AI n</td><td>Analog Input Channel n (single-ended)</td></tr><tr><td>DA Out</td><td>Analog Output Channel</td></tr><tr><td>ExtTrg</td><td>External A/D Trigger Signal</td></tr><tr><td>PreTrg</td><td>Pre-Trigger Stop or Post-Trigger Start Signal</td></tr><tr><td>EDI n</td><td>Extended Digital Input Channel n (0 to 3)</td></tr><tr><td>EDO n</td><td>Extended Digital Output Channel n (0 to 3)</td></tr><tr><td>A.GND</td><td>Analog Ground</td></tr><tr><td>D.GND</td><td>Digital Ground</td></tr><tr><td>N.C.</td><td>No connection</td></tr></table>

Table 2-3: CN3 Pin Assignment Legend

# 2.5 Hardware Installation Outline

# 2.5.1 PCI Configuration

PCI cards (or CompactPCI cards) are equipped with plug and play PCI controllers and can request base addresses and interrupts according to PCI standards. The system BIOS will install the system resources based on the PCI cards' configuration registers and system parameters (which are set by the system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can only be assigned by system BIOS. These system resource assignments are done on a board-by-board basis. It is not suggested to assign the system resource by any other methods.

# 2.5.2 PCI Slot Selection

A PCI card can be inserted into any PCI slot without any configuration modification to the system resources.

![The image shows a simple icon of a white document or piece of paper with horizontal grey lines, resembling a list or notepad. The top-left corner of the paper is folded down. A large, bold red checkmark is superimposed over the center of the document.](.pci-9111-50m-00069-1000-26/99c6c7f32c8692cdf00be9a85673d801129013e5680905fa16d0636afdc2b922.jpg)
NOTE:

The PCI system board and slot must provide bus-mastering capabilities to operate at an optimum level.

# 2.5.3 Installation Procedures

1. Turn off your computer.
2. Turn off all peripherals connected to your computer (printer, monitor, etc.).
3. Remove the cover from your computer.
4. Set up jumpers on the PCI or CompactPCI card.
5. Select a 32-bit PCI slot. PCI slot are shorter than ISA or EISA slots, and are usually white or ivory.
6. Before handling PCI cards, discharge any static buildup on your body by touching the metal case of the computer. Hold the edge and do not touch the components.
7. Position the board into the PCI slot you have selected.
8. Secure the card in place at the rear panel of the system.

# 2.6 Device Installation for Windows Systems

Once Windows 7/10 has started, the Plug and Play function of Windows system will find the new NuDAQ cards. If this is the first time the NuDAQ cards are running on your Windows system, you will be prompted to input the device information source. Please refer to the Software Installation Guide for step-by-step installation procedures.

# 2.7 Daughter Board Connection

The PCI-9111 can be connected with five different daughter boards. The following are compatible: ACLD-8125, 9137, 9138, 9182, 9185, and 9188. The functionality and connections are specified in the following sections.

# 2.7.1 Connect with ACLD-8125

The ACLD-8125 has a 37-pin D-sub connector, which can connect to the PCI-9111 through the 37-pin assemble cable. The most outstanding feature of this daughter board is the onboard CJC (cold junction compensation) circuit. You can directly connect a thermocouple to the ACL-8125 board. The CJC is only suitable for High Gain version boards.

# 2.7.2 Connect with ACLD-9137

The ACLD-9137 is directly connected to cards, which are equipped with 37-pin D-sub connectors. It is suitable for simple applications that do not need complex signaling conditions before an A/D conversion is performed.

# 2.7.3 Connect with ACLD-9182

The ACLD-9182 is a 16-channel isolated digital input board. This board is connected to CN1 of the PCI-9111 via the 20-pin flat cable. The ACLD-9182 provides 500V DC isolation voltage protection, thus protecting your PC system from damage in event that abnormal input signals occur.

![ACLD-9182\nCN2\nCN1\nPCI-9111](.pci-9111-50m-00069-1000-26/b65df707b940ad097da980a97f9d7403160dc1687185041e8f77b7baee91d7ea.jpg)

Figure 2-5: ACLD-9182 Daughter Board Connection

# 2.7.4 Connect with ACLD-9185

The ACLD-9185 is a 16-channel SPDT relay output board. This board is connected to CN2 of the PCI-9111 via a 20-pin flat cable. By using this board, you can control external devices through the digital output signals.

![ACLD-9185\nCN2\nCN1\nPCI-9111](.pci-9111-50m-00069-1000-26/f2c0f153aa718e0e0f394f7a9c0679b70c0837428d259a4801a5ebb3943db5c3.jpg)

# 2.7.5 Connect with ACLD-9138/ACLD-9188

ACLD-9138 and ACLD-9188 are general-purpose terminal boards equipped with a 37-pin D-sub connector. The ACLD-9138 has an LED indicator to indicate the power ON/OFF status of your computer system.

![The image displays a block diagram consisting of two rectangular units connected by a cable.\n\n**Labeled Blocks:**\n*   **Left Block:** A large rectangle labeled **PCI-9111** at the bottom. Inside, the labels **CN2** and **CN1** appear vertically on the left side, while **CN3** is located near the right edge.\n*   **Right Block:** A smaller rectangle labeled **ACLD-9188**. It contains two horizontal gray bars, one above and one below the label.\n\n**Connections:**\n*   A thick black cable connects the connector area labeled **CN3** on the **PCI-9111** block to the corresponding connector on the left side of the **ACLD-9188** block.](.pci-9111-50m-00069-1000-26/33b89a5aae111e112a38be325cd28269e605150b213a64e0baee008c7ae2c132.jpg)

Figure 2-6: ACLD-9138/9188 Daughter Board Connection

![The image displays a standard safety warning sign featuring a yellow triangle with a thick black border and a black exclamation point in the center. Below the triangle, the word 'CAUTION:' is printed in black capital letters on a white background.](.pci-9111-50m-00069-1000-26/ebe7af214ee1342af1df3dbf3f930ed0e27c82f4ec8883bb39662a9138ead020.jpg)

Protection on the EDI, EDO, and DA output are not provided. It is highly recommended that users implement a protection circuit of their own to avoid any possible damage to the card.

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# 3 Operation Theory

This chapter describes the operation theory of the PCI-9111 card functions. The functions include A/D conversion, D/A conversion, Digital I/O and counter/timer usage. The operation theory can help you to understand how to configure or to program the PCI-9111.

# 3.1 A/D Conversion

Before programming the PCI-9111 to perform any A/D conversions, you should have an understanding of the following:

▶ A/D Conversion Procedure
▶ A/D Trigger Source Control
▶ A/D Data Transfer Modes
▶ A/D Pre-trigger Control
▶ A/D Post-trigger Control
▶ A/D Data Format

# 3.1.1 A/D Conversion Procedure

To use the A/D converter, users first need to know the properties of the signal being measured. Users then can decide on which channels to use on the PCI-9111. See “Connector Pin Assignments” on page 15.

After deciding on the A/D signal source, users must decide how to trigger the A/D conversion and define/control the trigger source. The A/D converter will start to convert analog signals to a digital value when a trigger signal is on a rising edge. See “A/D Trigger Source Control” on page 29. for all possible trigger modes.

A/D data is required to be transferred to the PC's memory for further processing. The data can be read either by an I/O instruction set, which is handled directly by software, or transferred to memory via an interrupt routine. See “A/D Data Transfer Modes” on page 30. for more information regarding multi-configurations for the A/D data transfer process.

Some applications may require obtaining the data only before or after a special hardware event, in which case a Pre-Trigger is useful to stop the A/D operation. See “Pre-Trigger Control” on page 32. for configuring the PCI-9111 for Pre-Trigger Mode.

To process the A/D data, programmers should have an understanding of the A/D data format. See “Post-Trigger Control” on page 34. for details.

# Analog Input Signal Connection

The PCI-9111 provides 16 single-ended analog input channels. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and to obtain accurate measurements of A/D values, it is important to understand the signal source type. The single-ended mode has only one input relative to ground and is suitable for connecting with a floating signal source. A floating source is one that does not have any connection to ground. Figure 3-1 shows a single-ended connection. Note that when more than two floating sources are connected, the sources must have a common ground.

![This block diagram illustrates a signal processing chain flowing from left to right:\n\n1.  **Left Side:** A label **Floating Signal Source** sits above two circles containing sine waves labeled **V1** and **V2**, followed by an ellipsis (**...**).\n2.  **Middle Section:** Horizontal lines connect these sources to a vertical bar containing a series of black dots. The top of the bar is labeled **AIN** and the bottom dot is labeled **AGND**. Below the bar is the text **n = 0, ..., 15**.\n3.  **Right Side:** The vertical bar connects to a rectangular block labeled **Input Multiplexer**. This block connects to a triangle symbol labeled **Operational Amplifier**. Finally, the output of the amplifier connects to the text **To A/D Converter**.](.pci-9111-50m-00069-1000-26/8f0a67e0ca2b61fce9f8181911a35952447e8e1ca829a53076f60257e13f9c82.jpg)

Figure 3-1: Analog Input Signal Connection

# Signal Channel Control

There are two ways to control the channel number, either by a software program or by auto channel scanning which is controlled by the ASCAN bit in the AD mode control register. As ASCAN is cleared (0), the value of the AD channel MUX register defines the channel to be selected. Only one channel can be selected in this situation.

When ASCAN is set (1), the value in the AD channel MUX register defines the ending channel number of the auto-scanning operation. Under auto scan mode, the channels are scanned from channel 0 to the ending channel. Whenever a trigger signal is on the rising edge, the channel number to be selected will increase automatically. For example, if the ending channel number is 3, the auto channel scanning sequence is 0, 1, 2, 3, 0, 1, 2..., until the ASCAN bit is cleared.

![The image features an icon of a document or checklist. It shows a white piece of paper with a folded upper-left corner and faint gray horizontal lines. A large, bold red checkmark is overlaid diagonally across the center of the paper.](.pci-9111-50m-00069-1000-26/e98f16cb754c73e4b9199acfbfc954cc3b0f6f383336b8244a362017a4c064e2.jpg)
NOTE:

The current A/D channel number can be read back from the A/D data register on the 12-bit PCI-9111DG but it is not possible with the 16-bit PCI-9111HR.
The MUX register is 8 bits long. The 4 LSB is used to select the multiplexer onboard. The 4 MSB can be sent out via the EDO pins of the CN3 connector to select an external daughter board. At most 16-daughter boards can be selected and a total of 256 channels can be selected without extra circuits.

# Signal Range

A properly define signal range is important in any data acquisition process. The input signal may be saturated if the A/D gain is too large or the resolution may be not enough if the signal is small. The maximum A/D signal range of the PCI-9111 is +/- 10 volts when the A/D gain value is 1. The A/D gain control register controls the maximum signal input range. The signal gain is programmable with 5 levels (1, 2, 4, 8, 16). The signal ranges of the 16 channels are identical at all times.

The available signal polarity on PCI-9111 is bi-polar. However, the bi-polar input range can still cover a uni-polar application. In addition, the high resolution of the PCI-9111HR can cover most applications.

# 3.1.2 A/D Trigger Source Control

There are 3 different trigger conditions available to the PCI-9111. The different trigger conditions are specified below.

# Software Trigger

The trigger source is software controllable in this mode. That is, the A/D conversion is started when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversions. Under this mode, the timing of the A/D conversion is fully controlled by the software. However, it is difficult to control a fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger.

# Timer Pacer Trigger

The onboard timer/counter chip is used to provide a trigger source for an A/D conversion at a fixed rate. Two counters are cascaded together to generate a trigger pulse at precise periods. See “Timer/Counter Operation” on page 42. for timer/counter operations. This mode is ideal for high speed A/D conversion. It can be combined with the FIFO half full interrupt or EOC interrupt to transfer data. The A/D trigger, A/D data transfer and Interrupt can be set independently, thus most complex applications can be covered. It's recommended that this mode be used if the application requires a fixed and precise A/D sampling rate.

# External Trigger

Through Pin 16 of CN3 (ExtTrig), an A/D conversion can also be triggered by an external signal. The A/D conversion starts when ExtTrig changes from a high to a low level. The conversion rate in this mode is more flexible depending on the available trigger options of the external device. The external trigger can be also combined with the FIFO half interrupt, EOC interrupt or program FIFO polling for transferring data.

# 3.1.3 A/D Data Transfer Modes

The A/D data are buffered in the FIFO memory. The FIFO size of the PCI-9111 is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO can buffer 10.24 ms of analog signal. Data transferred to the FIFO after the FIFO is full will be lost. The software must read out the FIFO data before it becomes full.

The data must be transferred to the host memory after the data is ready and before the FIFO is full. With the PCI-9111, different transfer modes can be used. The different transfer modes are described below.

# Software Data Polling

Software data polling is the easiest way to transfer A/D data. This mode can be used with software A/D trigger mode. After the A/D conversion is triggered by software, the software should poll the FF\_EF bit of the A/D status register until it becomes low level.

If the FIFO is empty before the A/D start, the FF\_EF bit will be low. After the A/D is completed, the A/D data is written to FIFO immediately, therefore the FF\_EF becomes high. You can consider the FF\_EF bit as converted data ready status. That is, when FF\_EF is high, the data is ready. Note that, while A/D is being converted, the ADBUSY bit is low. After A/D conversion, ADBUSY becomes high to indicate it is not busy. DO NOT use this bit to poll the AD data.

It is possible to read A/D converted data without polling. The A/D conversion time will not exceed 8.5 $\mu$ s on the PCI-9111 card. Hence, after a software trigger, the software can wait for at least 8.5 $\mu$ s then read the A/D register without polling.

Data polling transferring is suitable for applications that need to process AD data in real time. Especially when combining with the timer interrupt generation, the timer interrupt service routine can use the data polling method to get multi-channel A/D data in real time under fixed data sampling rates.

# FIFO Half-Full Interrupt Transfer

Sometimes, applications do not need real-time processing, but the foreground program is too busy to poll the FIFO data. This is when the FIFO half-full interrupt transfer mode is useful. In addition, as the external A/D trigger source is used, the sampling rate may not be easy to predict, then the method can be applied because the CPU is only interrupted when the FIFO is half-full, thus reserving CPU load.

Under this mode, an interrupt signal is generated when FIFO becomes half-full, meaning there is 512 word data in the FIFO already. The ISR can read a block of data at every time an interrupt occurs. This method is convenient for reading the A/D In size of a “block” (512 words) and is beneficial for software programming.

# 3.1.4 Pre-Trigger Control

In certain applications, data acquisition is applied and stops under a special hardware signal. Without the Pre-Trigger function, the software can start the A/D at any time, but it is very difficult to stop the A/D in real-time with software. Under “Pre-Trigger” mode, the pre-trigger (PTRG) signal (from Pin 12 of CN3) and the 0 counter are used to “STOP” the A/D sampling.

After setting up the Pre-Trigger mode, the hardware is continuously acquiring A/D data and waiting for the pre-trigger signal. Before the pre-trigger signal is inserted, the software must read the FIFO data to prevent FIFO becoming full. Additionally, software should store usable data as much as possible to the host PC's memory.

When the pre-trigger signal is inserted, the counter starts to count down from the initial counter value N to count the number of the A/D conversion trigger signal. The A/D trigger will be disabled automatically when the counter value reaches zero. The value of N can be 1 to 65535 and the last N A/D data is sampled after the pre-trigger signal. The software must continuously read data out from the FIFO to prevent the FIFO becoming full. The software also should poll the counter value to check if the A/D sampling has stopped.

To set up Pre-Trigger mode, the following steps should be followed.

1. Set Pre-Trigger Mode Off: PTRG = OFF.
2. Set Counter #0 value N (N=1-65535). Note that the larger the counter value, the more host memory buffer is needed.
3. Set up A/D data acquisition, including, A/D range, channel scan, data transfer mode and so on.
4. Set Pre-Trigger Mode On: PTRG = ON.
5. Read A/D data into host PC memory buffer with a data transfer method, otherwise the FIFO will become full. At the same time, wait for the pre-trigger signal and check if the Counter # 0 value is down to zero.
6. If A/D has stopped, set the Pre-Trigger Mode off and process the data stored in the host memory.
7. Go to Step 1 to set the Pre-Trigger mode and wait for the next pre-trigger event.

The Pre-Trigger timing is shown as follows.

![This flowchart illustrates a timeline of data acquisition steps, represented by a horizontal blue arrow pointing right labeled **'Time'**.\n\nThe process flows from left to right as follows:\n\n1.  **Start:** An arrow points downward from **'Set Pre-Trigger mode'** to the beginning of the timeline. Below the timeline, a boxed section reads: **'Acquire Infinite A/D data before Pre-Trigger Signal is Inserted'**.\n2.  **Middle:** An arrow points downward from **'External Pre-Trigger Signal is Inserted'** to a point on the timeline. Above the timeline, text reads: **'Counter # 0 counting from N down to 0'**. Below the timeline, a boxed section reads: **'Acquire N A/D data after Pre-trigger Signal is Inserted'**.\n3.  **End:** An arrow points downward from **'A/D Data Acquisition Stop'** to a point further along the timeline.](.pci-9111-50m-00069-1000-26/d097a775e528b5ad43ba415f0c59bc21b0fea78e9dea2b007096c23ea0e6fb0e.jpg)

Figure 3-2: Pre-Trigger Timing

If the application acquires data after the pre-trigger signal, only the last N data needs to be stored. The maximum value of N is 65535. If the application only needs to acquire data before the pre-trigger signal, set N=1, then just one more data will be sampled after pre-trigger signal and infinite data before pre-trigger signal can be stored.

# 3.1.5 Post-Trigger Control

Another useful trigger mode is Post-Trigger. Under “Post-Trigger” mode, the post-trigger (POTRG) signal (from Pin 12 of CN3) is used to “START” the A/D sampling.

After setting up Post-Trigger mode, the A/D converter will not acquire data until the post-trigger signal is asserted. Users can poll the FIFO empty bit (FF\_EF) to detect whether the Post-Trigger signal is asserted or not. Once the post-trigger is asserted, the hardware will begin to acquire data. Different from Pre-Trigger control mode, users can acquire data continuously until the Post-Trigger mode is disabled.

The following steps can be referenced for Post-Trigger control

1. Disable all A/D trigger sources, e.g.: Timer-Pacer / Software trigger (TPST = 0) and External / Internal trigger (EITS = 0). Set Post-Trigger mode ON: POTRG = ON.
2. Set up A/D data acquisition, including, A/D range, channel scan, data transfer mode and so on.
3. Reset FIFO.
4. Enable the selected A/D trigger source (Timer-Pacer, Software or external trigger).
5. Waiting for Post-Trigger signal to be asserted. Users can poll the FIFO empty bit to see if the post-trigger signal has started.
6. Once the post-trigger signal is asserted, data processing begins. To stop data acquisition, disable the A/D trigger source.
7. Go to step 1 to start the next Post-Trigger acquisition.

The Post Trigger timing is shown as follows.

![The diagram displays a timeline labeled 'Time' with four instructional blocks pointing to specific moments, along with two signal waveforms below.\n\n**Labeled Blocks and Connections:**\n*   **Block 1:** Contains the text '1. Disable the A/D trigger source and set the Post-trigger ON. 2. Set up A/D acquire mode. 3. Reset FIFO.' An arrow points from this block to the beginning of the timeline.\n*   **Block 4:** Contains the text '4. Enable A/D trigger source.' An arrow points from this block to a point on the timeline slightly after Block 1.\n*   **Block 5:** Contains the text '5. Post-triigger signal assert.' An arrow points from this block to the rising edge of the signal line below.\n*   **Block 6:** Contains the text '6. Disable A/D trigger source to stop acquiring data.' An arrow points from this block to the end of the signal sequence.\n\n**Signal Waveforms:**\n*   **POTRG Signal:** Shown below the timeline, this signal goes high (asserted) at the point indicated by Block 5.\n*   **A/D conversion signal:** Shown at the bottom, this signal displays a series of pulses that begin after the POTRG signal asserts and continue until the point indicated by Block 6.](.pci-9111-50m-00069-1000-26/166f90028b75797add32e7e87035227d204940a2311c5e664dcfd2d3d767d27c.jpg)

Figure 3-3: Post Trigger Timing

Under pre-trigger or post-trigger control schemes, the TRGEVENT flag signal can come in handy. When the pre-trigger or post-trigger signal is inserted, the TRGEVENT will be set to 1. After an acquisition or before the next trigger signal is inserted, the trigger event flag must be cleared by the user in order to set the correct flag status for the next incoming trigger event.

![The image shows a white document icon with a folded top-left corner. Faint horizontal gray lines run across the document, suggesting text. A large red checkmark is drawn diagonally across the center of the document.](.pci-9111-50m-00069-1000-26/6b6a1f4e499fc5c43822d7d6f949327c447a530e8475b99dee114724c97bead1.jpg)
NOTE:

Either the pre-trigger mode or post-trigger mode can be enabled at any one time, but not both. The post-trigger mode is only available with hardware revision B2.

# 3.1.6 A/D Data Format

The A/D data read from the FIFO is in two formats. As the A/D gain is 1, the A/D signal range is roughly +10V to -10V bi-polar. In the PCI-9111HR, the whole 16-bit A/D data are available. The relationship between voltage and the A/D data value is shown in the following table.

<table><tr><td>A/D Data (Hex)</td><td>Decimal Value</td><td>Voltage (Volts)</td></tr><tr><td>7FFF</td><td>+32767</td><td>+9.99969</td></tr><tr><td>4000</td><td>+16384</td><td>+5.00000</td></tr><tr><td>0001</td><td>1</td><td>+0.00031</td></tr><tr><td>0000</td><td>0</td><td>0.00000</td></tr><tr><td>FFFF</td><td>-1</td><td>-0.00031</td></tr><tr><td>C000</td><td>-16384</td><td>-5.00000</td></tr><tr><td>8001</td><td>-32767</td><td>-9.99969</td></tr><tr><td>8000</td><td>-32768</td><td>-10.00031</td></tr></table>

Figure 3-4: Relationship between voltage and A/D data value

![The image shows a white sheet of paper with faint horizontal grey lines. A large red checkmark is overlaid on the center of the paper, and the top left corner is folded down.](.pci-9111-50m-00069-1000-26/850cc297b2868d1a4206300c77fd599e5a8cc326ef184c085e0358f82724adbb.jpg)
NOTE:

The decimal value of the A/D data is in the same sign with the bi-polar voltage. Therefore, the sign extension conversion is not necessary.

The A/D converted data of the 12-bit PCI-9111DG is on the 12 MSB of the A/D data. The 4 LSB of the 16 bits A/D data are the channel number and must be truncated by the software. The relationship between voltage and the A/D converted data value is shown in the following table.

<table><tr><td>A/D Data (Hex)</td><td>Decimal Value</td><td>Voltage (Volts)</td></tr><tr><td>7FF</td><td>+2047</td><td>+9.9951</td></tr><tr><td>400</td><td>+1024</td><td>+5.0000</td></tr><tr><td>001</td><td>1</td><td>+0.0049</td></tr><tr><td>000</td><td>0</td><td>0.0000</td></tr><tr><td>FFF</td><td>-1</td><td>-0.0049</td></tr><tr><td>C00</td><td>-1024</td><td>-5.0000</td></tr><tr><td>801</td><td>-2047</td><td>-9.9951</td></tr><tr><td>800</td><td>-2048</td><td>-10.0000</td></tr></table>

Figure 3-5: Relationship between voltage and A/D converted data

The formula between the A/D converted data and the voltage value is:

$$
V o l t a g e = A D \_ d a t a \times \frac {1}{K} \times \frac {1 0}{g a i n}
$$

Where gain is the value of the A/D gain control register, K=32768 for PCI-9111HR, and K=2048 for PCI-9111DG.

# 3.2 Extended Digital I/O Port

There are 4 extended digital input (EDI) signals and 4 extended digital output (EDO) signals on the CN3 connector. The 4 EDI signals are dedicated as input signals, however the 4 EDO signals can be used as digital input (Mode 1), digital output (Mode 2) or channel number output (Mode 3).

Note that when setting the EDO function as channel number output (Mode 3), it presents the high nibble (4 MSBs) of the channel number whether using manual scan, or auto scan mode.

# 3.3 D/A Conversion

The PCI-9111 has one analog output channel. The signal range can be uni-polar or bi-polar, set by JP1.

![Based on the provided block diagram, here is the accurate and concise description:\n\n**Labeled Blocks:**\n*   **D/A Converter**: A rectangular block on the left.\n*   **Operational Amplifier**: A triangle symbol in the center with inputs labeled **'-'** (inverting) and **'+'** (non-inverting).\n*   **Terminal Block**: A vertical rectangle on the right with two connection dots.\n\n**Connections:**\n*   **Input:** The text **'-10V Ref In'** has a line extending downwards that connects to the left side of the **'D/A Converter'** block.\n*   **DAC to Op-Amp:** A line connects the right side of the **'D/A Converter'** block to the **'- '** input of the operational amplifier.\n*   **Feedback Loop:** A wire originates from the operational amplifier output (the right tip), loops upwards and to the left, and connects to the vertical wire associated with **'-10V Ref In'**.\n*   **Ground Connections:**\n    *   A line connects the bottom of the **'D/A Converter'** block to a horizontal ground rail.\n    *   The **'+'** input of the operational amplifier connects to this same horizontal ground rail.\n    *   The horizontal ground rail connects to an inverted triangle ground symbol.\n    *   The horizontal ground rail connects to the bottom dot of the terminal block.\n*   **Output Connections:**\n    *   The top dot of the terminal block connects to the operational amplifier output line.\n    *   The bottom dot of the terminal block connects to the horizontal ground rail.\n\n**Text Labels:**\n*   **'-10V Ref In'** (top left)\n*   **'D/A Converter'** (inside the box)\n*   **'Pin 30 (DA Out)'** (top right, above the top terminal)\n*   **'To D/A Output'** (middle right, next to an arrow pointing right)\n*   **'Analog GND'** (bottom right, next to an arrow pointing right)](.pci-9111-50m-00069-1000-26/adc6c6b8758304e156ba657e13cb2e555f7f810a2342a17338c24597dfc3525a.jpg)

Figure 3-6: D/A Conversion Circuit

The operation of the D/A conversion is much simpler than the A/D operation. You only need to write a digital value into the D/A data registers and the corresponding voltage will be outputted on DAOut (Pin 30 of CN3). The mathematical relationship between the digital data DAn and the output voltage is formulated as follows.

$$
V _ {\text { out }} = \text { span } \times \text { DAn } / 4 0 9 6 - \text { Unipolar }
$$

$$
V _ {\text { out }} = \text { span } \times \text { DAn } / 4 0 9 6 + (- 1 0) - \text { Bipolar }
$$

Where span is the span in volts. If your output range is -10V to 10V (Bipolar), then span is 20; if your output range is 0 to 10V (Unipolar), then span is 10. Vout is the output voltage, and DAn is the digital data value in the D/A data registers.

Before performing the D/A conversion, users should take note of the D/A output range, which is set by JP1. See “Jumper Settings” on page 14.

<table><tr><td rowspan="2">Digital Data Input</td><td colspan="2">Analog Output</td></tr><tr><td>Unipolar 0V to 10V</td><td>Bipolar -10V to 10V</td></tr><tr><td>FFF hex</td><td>+9.9976V</td><td>+9.9951V</td></tr><tr><td>800 hex</td><td>+5.0000V</td><td>0.0000V</td></tr><tr><td>7FF hex</td><td>+4.9976V</td><td>-0.0049V</td></tr><tr><td>000 hex</td><td>0.0000V</td><td>-10.0000V</td></tr><tr><td>1 LSB</td><td>2.44mV</td><td>4.88mV</td></tr></table>

Figure 3-7: Relationship between DI and AO

# 3.4 Digital Input and Output

To program the digital I/O operation is fairly straightforward. The digital input operation just reads data from its corresponding registers, and the digital output operation writes data to its corresponding registers. Note that the DIO data channel can only be read or written in the form of 16 bits. It is impossible to access individual bits.

The PCI-9111 provides 16 digital input and 16 digital output channels through CN1 and CN2. The digital I/O signals are fully TTL/DTL compatible. Detailed digital I/O signal specifications can be referred to in section 2.4.1.

![Digital Input(DI)\nFrom TTL Signal\nDigital Output (DO)\nTo TTL Devices\nDigital GND (DGND)\nPCI-9111	Outside Device](.pci-9111-50m-00069-1000-26/273bf538d1bf9f6c9bbcdd7edaa8958415df10b03e28531094bf9cf2c2aa0bff.jpg)

Figure 3-8: Digital Input and Output Circuit

# 3.5 Timer/Counter Operation

One programmable interval timer/counter chip is integrated on the PCI-9111. There are three counters available to the timer/counter chip and 6 possible operation modes for each counter. Figure 3-9 illustrates the block diagram of the timer/counter system.

![The diagram depicts a digital control system consisting of a 'Pre-Trigger Control' block and a 'Timer/Counter Chip' containing three sub-blocks: 'Counter #0', 'Timer #1', and 'Timer #2'.\n\n**Inputs:**\n*   **Pre-Trigger Signal (Pin 12 of CN3):** An arrow points from this label into the 'Pre-Trigger Control' block.\n*   **Internal 2 MHz Clock:** A line connects to the 'C' inputs of both 'Timer #1' and 'Timer #2'. The label ''H'' appears next to these connection points.\n\n**Connections and Outputs:**\n*   **Pre-Trigger Control Outputs:** Two arrows originate from the 'Pre-Trigger Control' block. One is labeled 'AD Trigger Signal' and points to the 'C' input of 'Counter #0'. The other is labeled 'Gate Control' and points to the 'G' input of 'Counter #0'.\n*   **Counter #0 Feedback:** A line exits the 'O' output of 'Counter #0' and loops back to the top of the 'Pre-Trigger Control' block.\n*   **Timer #1 Output:** A line exits the 'O' output of 'Timer #1' pointing to the right, labeled 'Internal Timer Pacer'.\n*   **Timer #2 Feedback:** A line exits the 'O' output of 'Timer #2' and loops back to its own 'G' input.](.pci-9111-50m-00069-1000-26/75454c12ad0cd015d99a8260fcd0699c212407a68ef2e3de0ddefcf19cf1719e.jpg)

Figure 3-9: Timer/Counter Block Diagram

# Pacer Trigger Source

Timers 1 and 2 are cascaded together to generate the timer pacer trigger for A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4 = 500KHz which exceeds the maximum A/D conversion rate of the PCI-9111. The minimum signal rate is 2MHz/65535/65535, which is a very low frequency. Users are advised not to use it.

# 3.5.1 Pre-Trigger Counter

Timer #0 is used as a pre-trigger counter. The clock source of counter 0 is from the A/D trigger source so that the timer/counter can count the A/D trigger numbers after the pre-trigger signal (Pin 12 of CN3) is inserted. The gate control is set when the pre-trigger signal changes from 'H' to 'L', and is cleared when the counter counts down to zero. In the software library, timer #0 is always set as mode 0 (event counter).

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing:
▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power

▶ To avoid electrical shock and/or damage to device:

▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▷ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools

▶ A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![A yellow triangular warning sign with a black border containing a black exclamation point, with the text 'CAUTION:' printed below it in black capital letters.](.pci-9111-50m-00069-1000-26/e961ffd6fe236139f430e8a4954e8c925925381f34b19af045ef716dd337019e.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d'explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up

It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required
▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

▶ If PoE (Power over Ethernet) is enabled for the device, the system can ONLY be deployed indoors. Unless otherwise noted, the PoE system is NOT designed to withstand the rigors of outdoor use.

![Yellow triangular warning sign with black smoke symbol indicating thermal hazard](.pci-9111-50m-00069-1000-26/a1d358ec3162dc5be93d9740178ddbcca577317cc9987b20d9a985f12f20ef81.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

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# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you:
[🔗 Link to the original document](.pci-9111-50m-00069-1000-26/pci-9111-50m-00069-1000-26.pdf)