# NuDAQ®

# PCI-9114(A) DG/HG

# Enhanced Multi-Functions

# Data Acquisition Card

# User's Guide

©Copyright 1997\~2003 ADLINK Technology Inc.;

All Rights Reserved.

Manual Rev. 1.40: April 28, 2003

Part No. 50-11114-202

The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

NuDAQ $^{®}$ , NuIPC $^{®}$ are registered trademarks of ADLINK Technology Inc. Other products names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting service from ADLINK

Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us.

<table><tr><td colspan="4">ADLINK Technology Inc.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">Service@adlinktech.com</td></tr><tr><td rowspan="4">Technical Support</td><td>NuDAQ + USBDAQ + PXI</td><td colspan="2">nudaq@adlinktech.com</td></tr><tr><td>Automation</td><td colspan="2">automation@adlinktech.com</td></tr><tr><td>NuIPC</td><td colspan="2">nuipc@adlinktech.com</td></tr><tr><td>NuPRO / EBC</td><td colspan="2">nupro@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan.</td></tr></table>

Please email or FAX us of your detailed information for a prompt, satisfactory and constant service.

<table><tr><td colspan="4">Detailed Company Information</td></tr><tr><td>Company/Organization</td><td colspan="3"></td></tr><tr><td>Contact Person</td><td colspan="3"></td></tr><tr><td>E-mail Address</td><td colspan="3"></td></tr><tr><td>Address</td><td colspan="3"></td></tr><tr><td>Country</td><td colspan="3"></td></tr><tr><td>TEL</td><td></td><td>FAX</td><td></td></tr><tr><td>Web Site</td><td colspan="3"></td></tr><tr><td colspan="4">Questions</td></tr><tr><td>Product Model</td><td colspan="3"></td></tr><tr><td>Environment to Use</td><td colspan="3">OS:Computer Brand:M/B: CPU:Chipset: BIOS:Video Card:Network Interface Card:Other:</td></tr><tr><td>Detail Description</td><td colspan="3"></td></tr><tr><td>Suggestions to ADLINK</td><td colspan="3"></td></tr></table>

# Table of Contents

# Chapter 1 Introduction ...... 1

1.1 Features....2
1.2 Applications.... 2
1.3 Specifications 3
1.4 Supporting Software....5

1.4.1 Programming Library 5
1.4.2 PCIS-LVIEW: LabVIEW $^{®}$ Driver 6
1.4.3 PCIS-VEE: HP-VEE Driver 6
1.4.4 DAQBenchTM: ActiveX Controls.... 6
1.4.5 DASYLabTM PRO....6
1.4.6 PCIS-DDE: DDE Server and InTouchTM 6
1.4.7 PCIS-ISG: ISaGRAF $^{TM}$ driver....6
1.4.8 PCIS-ICL: InControl™ Driver 7
1.4.9 PCIS-OPC: OPC Server 7

# Chapter 2 Installation 8

2.1 What You Have 8
2.2 Unpacking 9
2.3 PCB Layout of PCI-9114(A) 10

2.3.1 PCI-9114 Rev. B1.... 10
2.3.2 PCI-9114 Rev. C2 and PCI-9114A Rev.A2 10

2.4 Hardware Installation.... 11

2.4.1 PCI configuration.... 11
2.4.2 PCI slot selection.... 11
2.4.3 Installation Procedures 11

2.5 Device Installation for Windows Systems 12
2.6 Connector Pin Assignments 12

2.6.1 Pin Assignment of CN1 12
2.6.2 Pin Assignments for CN2 & CN3 13
2.6.3 Pin Assignment for CN4 14

2.7 Jumper Descriptions 15

2.7.1 Analog Input Signal Type Selection (JP1) 15
2.7.2 Cold Junction Sensor Selection (JP2) 15
2.7.3 Counter #0 Function Selection (JP4).... 16

2.8 Termination Board Connection.... 17

# Chapter 3 Registers....18

3.1 PCI PnP Registers 18
3.2 I/O Address Map 19
3.3 A/D Data Registers 20
3.4 A/D Channel Control Register 20
3.5 A/D Input Signal Range Control Register 21
3.6 A/D Status Read-back Register 21
3.7 Trigger Mode Control and Read-back Register 21
3.8 Interrupt Control and Read-back Register 23
3.9 Software Trigger Register 24
3.10 Hardware Interrupt Clear Registers 24
3.11 Timer/Counter Register 25
3.12 High Level Programming.... 25

# Chapter 4 Operation Theory ...... 26

4.1 A/D Conversion 26

4.1.1 A/D Conversion Procedure 27
4.1.2 A/D Signal Source Control 27
4.1.3 A/D Trigger Source Control 29
4.1.4 A/D Data Transfer Modes 30
4.1.5 Pre-Trigger Control 32
4.1.6 A/D Data Format 34

4.2 Interrupt Control 35

4.2.1 System Architecture 35
4.2.2 IRQ Level Setting 35
4.2.3 Dual Interrupt System 36
4.2.4 Interrupt Source Control 36

4.3 Isolated Digital Input 37
4.4 Isolated Digital Output 38
4.5 Timer/Counter Operation.... 40

4.5.1 Introduction.... 40
4.5.2 Pacer Trigger Source 40

# Chapter 5 C/C++ Library....41

5.1 Libraries Installation 41
5.2 Programming Guide 42

5.2.1 Naming Convention 42

5.2.2 Data Types 42

5.3 9114 Initial 43
5.4 9114 Software Reset 43
5.5 9114 DO....44
5.6 9114 DI....44
5.7 9114 AD Read Data 45
5.8 9114 AD Read Data Repeat.... 46
5.9 9114 AD Read Data MUX 47
5.10 9114 AD Read Data Repeat MUX 48
5.11 9114 AD Set Channel....49
5.12 9114 AD Set Range 50
5.13 9114\_AD\_Get\_Range 51
5.14 9114 AD Get Status 52
5.15 9114 AD Set Mode 53
5.16 9114 AD Get Mode.... 54
5.17 9114\_INT\_Set\_Reg 55
5.18 9114\_AD\_Get\_Reg....56
5.19 9114 Reset FIFO 57
5.20 9114\_AD\_Soft\_Trigger....58
5.21 9114 Set 8254....58
5.22 9114 Get 8254 59
5.23 9114 AD Timer 60
5.24 9114 Counter Start 61
5.25 9114 Counter Read 62
5.26 \_9114 Counter Stop 63
5.27 9114 INT Source Control....64
5.28 9114 CLR IRQ1....65
5.29 9114 CLR IRQ2....65
5.30 9114 Get IRQ Channel....66
5.31 9114 Get IRQ Status....67
5.32 9114 AD FFHF Polling 68
5.33 9114\_AD\_FFHF\_Polling\_MUX....69
5.34 \_9114\_AD\_Aquire....70
5.35 9114 AD Aquire MUX 71
5.36 9114 AD INT Start....72
5.37 9114 AD FFHF INT Start....73
5.38 9114 AD INT Status 75
5.39 9114 AD FFHF INT Status 76
5.40 9114 AD FFHF INT Restart....77
5.41 9114\_AD\_INT\_Stop 78

# Chapter 6 Calibration & Utilities....79

6.1 Calibration 79

6.1.1 What do you need? 79
6.1.2 VR Assignment....80
6.1.3 A/D Adjustment 80
6.1.4 Software A/D Offset Calibration 82

6.2 Utility 82

6.2.1 9114util (For PCI-9114 Rev. B2 Only) 82
6.2.2 9114AUtl....86
6.2.3 I\_EEPROM....89

# Appendix A. 8254 Programmable Interval Timer....90

A.1 The 8254 Timer / Counter Chip....90
A.2 The Control Byte 91

# Appendix B. Signal Wiring Diagrams....93

# Warranty Policy....96

# Outline of Chapters

This manual is designed to help the user to understand and configure the PCI-9114(A). The manual describes the programming functions and the operation theory of the PCI-9114(A) card. It is divided into six chapters

Chapter 1, “Introduction”, gives an overview of the product features, applications, and specifications.

Chapter 2, “Installation”, describes how to install the PCI-9114(A). The layout of the PCI-9114(A) is shown, and the jumper settings for analog input channel configurations are specified. The connector pin assignments and termination board connections are described.

Chapter 3, “Registers”, describes the details of the register structures of the PCI-9114(A), this information can be useful for programmers wanting to control the hardware using low-level programming.

Chapter 4, “Operation Theory”, describes how to operate the PCI-9114(A). The A/D and timer/counter functions are introduced as well as some programming concepts are specified in this chapter.

Chapter 5, “C/C++ Library”, describes high-level programming interface in C/C++ language. It will aid programmers with controlling the PCI-9114(A) using high-level programming language

Chapter 6, “Calibration”, describes how to calibrate the PCI-9114(A), for accurate measurements.

![The image displays a white square with a thick black border containing the bold black number '1' centered within it. Partial outlines of adjacent squares are visible to the right and below, suggesting a grid layout.](.pci-9114series-manual-4/7884209e32a407fef5d865a34ac8b9be75962e5b06200fe1a552ba088f715cef.jpg)

# Introduction

The PCI-9114(A) is an advanced data acquisition card based on the 32-bit PCI Bus architecture. High performance design with state-of-the-art technology makes this card ideal for data logging and signal analysis applications in areas like medicine and process control. The following illustration shows the fundamental function blocks of the PCI-9114(A).

![Based on the provided flowchart, here is the description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   32 SE/ 16DI MUX\n*   PGA Gain=1,10 100,1000 or 1,2,4,8\n*   16 bits AD\n*   1K FIFO\n*   AD Controller ASIC\n*   Cold Junction Sensor\n*   8254 Timer\n*   PCI Controller\n*   16 Channels Isolated DI\n*   16 Channels Isolated DO\n*   32 bits PCI Bus\n\n**Connections:**\n*   **Inputs to MUX:** Four horizontal arrows and a vertical dotted line with a right-pointing arrow enter the left side of the '32 SE/ 16DI MUX'. An upward arrow connects the 'Cold Junction Sensor' to the bottom of the '32 SE/ 16DI MUX'.\n*   **Signal Path:** A rightward arrow connects the '32 SE/ 16DI MUX' to the 'PGA Gain=1,10 100,1000 or 1,2,4,8' block. A rightward arrow connects the 'PGA' block to the '16 bits AD' block. A downward arrow connects the '16 bits AD' block to the '1K FIFO' block.\n*   **Controller Connections:** A vertical line connects the 'AD Controller ASIC' upward to the signal line between the 'PGA' and '16 bits AD' blocks. From a junction dot on this vertical line, an arrow points left to the '32 SE/ 16DI MUX'.\n*   **Data Flow:** A downward arrow connects the '1K FIFO' block to the 'PCI Controller'.\n*   **Peripheral Connections:**\n    *   A bidirectional (double-headed) arrow connects the 'PCI Controller' to the '32 bits PCI Bus' below it.\n    *   A bidirectional arrow connects the 'PCI Controller' to the '8254 Timer'.\n    *   A bidirectional arrow connects the '8254 Timer' to the 'AD Controller ASIC'.\n    *   A leftward arrow connects the '16 Channels Isolated DI' block to the 'PCI Controller'.\n    *   A rightward arrow connects the 'PCI Controller' to the '16 Channels Isolated DO' block.](.pci-9114series-manual-4/34f2d840cd3fef61898165110d6839ee17b381f1ff4a4ee3c99294f6def4910e.jpg)

Figure 1. PCI-1114(A) Fundamental function block

# 1.1 Features

The PCI-9114(A) PCI-Bus Advanced Data Acquisition Card provides the following advanced features:

• 32-bit PCI-Bus, Plug and Play
• 32 single-ended or 16 differential analog inputs channels
• 16-bits high resolution AD conversion
• High amplification gain of 1, 10, 100, 1000 for PCI-9114(A) HG
• Normal gain of 1, 2, 4, 8 for PCI-9114(A) DG
• Single channel sampling rate up to 100 KHz for PCI-9114
• Single channel sampling rate up to 250 KHz for PCI-9114A
• Multi-AD trigger mode: software trigger, timer pacer trigger
- On-board A/D 1K WORDS FIFO memory
• Auto-scanning channel selection
- One user configurable general purpose Timer/Counter (Only available in PCI-9114A and PCI-9114 Rev. C2 or later)
• 16 Isolated Digital Input Channels
• 16 Isolated Digital Output Channels with high driving capability
• 5000 V rms high voltage isolation for DIO channels

# 1.2 Applications

• Industrial process control
• Transducer, thermocouple, RTD
- Power monitor
• Medical instrument
• Biomedical measurement

# 1.3 Specifications

# ♦ Analog Input (A/D)

- Converter: LTC1605 (LTC1606 for PCI-9114A) or equivalent, successive approximation type
• Resolution: 16 bits
- Input channels: 32 single-ended or 16 differential input channels
• Input Range: (Programmable)

√ Bipolar: 10V, ±1V, ±100 mV, ±10 mV (PCI-9114(A) HG)
√ Bipolar:±10V, ±5V, ±2.5, ±1.25V (PCI-9114(A) DG)

# - Throughput:

√ Single channel 100 KHz max for PCI-9114
√ Single channel 250 KHz max for PCI-9114A

# • Over Voltage Protection for Analog inputs:

√ Continuous ±35V maximum

• Input Impedance: 10 MΩ
• A/D Trigger Modes: Software and Timer pacer trigger
• Data Transfer Mode: Pooling, EOC Interrupt, FIFO Half-full Interrupt
• FIFO Buffer Size: 1024 samples

# ♦ Isolated Digital Input (IDI)

• Number of input channels: 16
• Input voltage: 0\~24 VDC

√ Logic L: 0\~1.5V
√ Logic H: 3\~24V
• Input resistance: 4.7 KΩ @ 0.5W
• Isolation voltage: 5000 V rms
• Throughput: 10 KHz

# ♦ Isolated Digital Output (IDO)

• Number of output channels: 16 channels current source
• Output type: open emitter 0.5 to 50 $V_{DC}$
- Source Current:

√ Single channel sources 500 mA maximum
√ 8 channels source 60mA maximum simultaneously

• Isolation voltage: 5000 V rms
• Throughput: 10 KHz

# ♦ General Specifications

- Connector: 37-pin D-type connector
• Operating Temperature: 0°C \~ 60°C
• Storage Temperature: $-20^{\circ}$ C \~ $80^{\circ}$ C
• Humidity: 5 \~ 95%, non-condensing
• Power Consumption:

√ +5 V @ 600 mA (typical)
√ +12 V @ 100 mA (typical)

# - Dimension:

√ Length:

7.88" (200 mm) for PCI-9114 Rev. B1

6.89" (175 mm) for PCI-9114 Rev. C2 and PCI-9114A

√ Width:4.18" (106 mm)(W)

# 1.4 Supporting Software

ADLINK provides versatile software drivers and packages for users' different approach to building a system. ADLINK not only provides programming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW $^{®}$ , HP VEE $^{TM}$ , DASYLab $^{TM}$ , InTouch $^{TM}$ , InControl $^{TM}$ , ISaGRAF $^{TM}$ , and so on.

All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes. Without the software code, you can install and run the demo version for two hours for trial/demonstration purposes. Please contact ADLINK dealers to purchase the formal license

# 1.4.1 Programming Library

For customers who are writing their own programs, we provide function libraries for many different operating systems, including:

- DOS Library: Borland C/C++ and Microsoft C++. Functional descriptions are included in this user's guide.
- Windows 95 DLL: For VB, VC++, Delphi, and BC5. Functional descriptions are included in this user's guide.
- PCIS-DASK: Include device drivers and DLL for Windows 98, Windows NT and Windows 2000. DLL is binary compatible across Windows 98, Windows NT and Windows 2000. That means all applications developed with PCIS-DASK are compatible across Windows 98, Windows NT and Windows 2000. The developing environment can be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The user's guide and function reference manual of PCIS-DASK are in the CD. Please refer the PDF manual files under \\Manual\_PDF\Software\PCIS-DASK
- PCIS-DASK/X: Include device drivers and shared libraries for Linux. The developing environment can be Gnu C/C++ or any programming language that allows linking to a shared library. The user's guide and function reference manual of PCIS-DASK/X are in the CD. Please refer the PDF manual files under. (\Manual\_PDF\Software\PCIS-DASK-X.)

The above software drivers are shipped with the board. Please refer to the "Software Installation Guide" for installation procedures.

# 1.4.2 PCIS-LVIEW: LabVIEW® Driver

PCIS-LVIEW contains the VIs, which is used to interface with NI's LabVIEW $^{\textregistered}$ software package. The PCIS-LVIEW supports Windows 95/98/NT/2000. The LabVIEW $^{\textregistered}$ drivers is shipped free with the board. You can install and use them without a license. For more information about PCIS-LVIEW, please refer to the user's guide in the CD. (\Manual\_PDF\Software\PCIS-LVIEW)

# 1.4.3 PCIS-VEE: HP-VEE Driver

The PCIS-VEE includes user objects, which are used to interface with HP's VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE drivers are shipped free with the board. You can install and use them without a license. For more information about PCIS-VEE, please refer to the user's guide in the CD. (\Manual\_PDF\Software\PCIS-VEE)

# 1.4.4 DAQBench™: ActiveX Controls

We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use the DAQBench™ ActiveX Control component library for developing applications. The DAQBench™ is designed under Windows NT/98. For more information about DAQBench, please refer to the user's guide in the CD. (\Manual\_PDF\Software\DAQBench\DAQBench Manual.PDF)

# 1.4.5 DASYLabTM PRO

DASYLab is an easy-to-use software package, which provides easy-setup instrument functions such as FFT analysis. Please contact ADLINK to purchase a copy of DASYLab PRO, which includes DASYLab and ADLINK hardware drivers.

# 1.4.6 PCIS-DDE: DDE Server and InTouch™

DDE stands for Dynamic Data Exchange. The PCIS-DDE includes the PCI cards' DDE server. The PCIS-DDE server is included in the ADLINK CD. It needs a license. The DDE server can be used in conjunction with any DDE client under Windows NT.

# 1.4.7 PCIS-ISG: ISaGRAF™ driver

The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG includes ADLINK product drivers for ISaGRAF under Windows NT environment. The PCIS-ISG is included in the ADLINK CD. A license is needed to use the drivers.

# 1.4.8 PCIS-ICL: InControl™ Driver

PCIS-ICL is the InControl driver, which supports Windows NT. The PCIS-ICL is included in the ADLINK CD. A license is needed to use the drivers.

# 1.4.9 PCIS-OPC: OPC Server

PCIS-OPC is an OPC Server, which can link with OPC clients. There are several software packages on the market, which can provide the OPC clients. The PCIS-OPC supports Windows NT and requires a license to operate.

# 2

# Installation

This chapter describes how to install the PCI-9114(A). Follow the steps carefully.

• Check what you have (section 2.1)
• Unpacking (section 2.2)
- Check the PCB and jumper location (section 2.3)
• Install the hardware and setup and jumpers (section 2.4, 2.7)
• Install the software drivers and run utility to test (section 2.5)
• Cabling with external devices (section 2.6, 2.8)

# 2.1 What You Have

In addition to this user's guide, the package should include the following items:

• PCI-9114(A) Enhanced Multi-function Data Acquisition Card
- ADLINK CD
• Software Installation Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

# 2.2 Unpacking

The card contains electro-static sensitive components that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damages. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

Note: DO NOT ATTEMPT TO INSTALL A DAMAGED BOARD IN THE COMPUTER.

You are now ready to install your card.

# 2.3 PCB Layout of PCI-9114(A)

2.3.1 PCI-9114 Rev. B1
![Based on the provided image, here is the accurate description of the labeled blocks and their layout. Note that explicit connecting lines (arrows) are not drawn between the major blocks, suggesting this is a physical layout or block diagram where proximity implies relationship.\n\n**Labeled Blocks:**\n*   CN1\n*   PGA\n*   MUX (appears twice)\n*   JP1\n*   DC/DC Converter (appears twice)\n*   PCI Controller\n*   Boot Rom\n*   8254\n*   FIFO (appears twice)\n*   Crystal\n*   CPLD\n*   Photo-Isolators (appears twice)\n*   TDS62783 (appears twice)\n*   CN2\n*   CN3\n*   VR1, VR2, VR3, VR4\n*   ADC\n*   JP2\n*   TP1\n*   TP2\n*   Cold Junction Sensor\n\n**Layout and Groupings:**\n\n*   **Left Section:** On the far left is a large vertical block labeled **CN1**. To its right are stacked blocks for **PGA**, two **MUX** blocks, **JP1**, and a **DC/DC Converter**. Above these are **ADC**, **JP2**, **TP1**, **TP2**, and a **Cold Junction Sensor**. At the top left edge, four vertical blocks are labeled **VR4**, **VR3**, **VR2**, and **VR1**.\n*   **Center Section:** The central area is dominated by a large block labeled **PCI Controller**. Directly above it is a group labeled **Boot Rom**, which contains an **8254** block and two **FIFO** blocks. To the right of the PCI Controller is an oval labeled **Crystal** and a large block labeled **CPLD**. Below the CPLD is a smaller **DC/DC Converter** block.\n*   **Right Section:** On the far right are connectors labeled **CN2** (top) and **CN3** (bottom). Between the center and the right edge are two vertical blocks labeled **TDS62783** and columns of small rectangles labeled **Photo-Isolators**. A second group of **Photo-Isolators** is located at the top right.](.pci-9114series-manual-4/2d34a1d7273d16070b7f28c34394acdab7e2a14865fe0ce8ea6750b8d6128882.jpg)

Figure 2. PCB Layout of PCI-9114 Rev. B1

2.3.2 PCI-9114 Rev. C2 and PCI-9114A Rev.A2
![This block diagram illustrates the physical layout and component placement of an electronic circuit board. The labeled blocks and their spatial arrangement are as follows:\n\n**Left Side and Top Left:**\n*   **CN1**: A large connector running along the far left edge.\n*   **TP2**: A test point at the very top left.\n*   **VR1, VR2, VR3, VR4, VR5**: A vertical column of five components (likely variable resistors or regulators).\n*   **Cold Junction Sensor**: Located below TP2.\n*   **JP2**: A jumper next to the Cold Junction Sensor.\n*   **TP1**: A test point below JP2.\n*   **ADC**: A vertical rectangular block to the right of the VR column.\n*   **PGA**: A horizontal block below the ADC area.\n*   **MUX**: Two stacked horizontal blocks below PGA.\n\n**Center Area:**\n*   **DC/DC Converter**: A large central block.\n*   **JP1**: A small jumper to the right of the PGA/MUX blocks.\n*   **Boot Rom**: A small horizontal block above JP1.\n*   **JP4**: A small jumper to the right of the Boot Rom.\n*   **Four FIFO blocks**: Arranged in a 2x2 grid above the CPLD.\n*   **8254**: A block located below the bottom-right FIFO block.\n*   **PCI Controller**: A large square block at the bottom center.\n\n**Top Right Area:**\n*   **CPLD**: A large square block.\n*   **Crystal**: An oval component below the CPLD.\n\n**Right Side:**\n*   **CN2**: A large connector at the top right.\n*   **Photo-Isolators**: Two groups of blocks with this label, oriented vertically.\n*   **TDS62783**: Text appearing vertically twice, situated between the Photo-Isolators and CN3.\n*   **CN3**: A large connector below CN2.\n*   **DC/DC Converter**: A small block near the bottom right corner.\n*   **CN4**: A connector below the bottom-right DC/DC converter.](.pci-9114series-manual-4/d2c2a6dd4e612efe717ed07be4bf9267ee7e825b334c2646836f21560b80d274.jpg)

Figure 3. PCB Layout of PCI-9114 Rev. C2 and PCI-9114A Rev.A2

# 2.4 Hardware Installation

# 2.4.1 PCI configuration

The PCI cards (or CompactPCI cards) are equipped with plug and play PCI controllers, it can request base addresses and interrupts according to PCI standards. The system BIOS will install the system resources based on the PCI cards' configuration registers and system parameters (which are set by the system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can only be assigned by system BIOS. These system resource assignments are done on a board-by-board basis. It is not suggested to assign the system resource by any other methods.

# 2.4.2 PCI slot selection

The PCI card can be inserted into any PCI slot without any configuration modification to the system resources. Please note that the PCI system board and slot must provide bus-mastering capability to operate at its optimum level.

# 2.4.3 Installation Procedures

1. Turn off your computer.
2. Turn off all accessories (printer, modem, monitor, etc.) connected to your computer.
3. Remove the cover from your computer.
4. Setup jumpers on the PCI or CompactPCI card.
5. Select a 32-bit PCI slot. PCI slot are shorter than ISA or EISA slots, and are usually white or ivory.
6. Before handling the PCI cards, discharge any static buildup on your body by touching the metal case of the computer. Hold the edge and do not touch the components.
7. Position the board into the PCI slot you have selected.
8. Secure the card in place at the rear panel of the system.

# 2.5 Device Installation for Windows Systems

Once Windows 95/98/2000 has started, the Plug and Play function of Windows will find the new NuDAQ/NuIPC cards. If this is the first time the NuDAQ/NuIPC cards are running on your Windows system, you will be prompted to input the device information source. Please refer to the “Software Installation Guide” for step-by-step installation procedures.

# 2.6 Connector Pin Assignments

# 2.6.1 Pin Assignment of CN1

The PCI-9114(A) comes equipped with a 37-pin D-type connector (CN1). The pin assignment for CN1 is illustrated in Figure 4.

![CN1 (for Single-Ended Input)\nAI0 19 37 AI16\nAI1 18 36 AI17\nAI2 17 35 AI18\nAI3 16 34 AI19\nAI4 15 33 AI20\nAI5 14 32 AI21\nAI6 13 31 AI22\nAI7 12 30 AI23\nAGND 11 29 AGND\nAI8 10 28 AI24\nAI9 9 27 AI25\nAI10 8 26 AI26\nAI11 7 25 AI27\nAI12 6 24 AI28\nAI13 5 23 AI29\nAI14 4 22 AI30\nAI15 3 21 AI31\n-12V 2 20 GND\n+12V 1](.pci-9114series-manual-4/47c39edf976eb56b67ed22b1162879f5f656cc95e37d36121c4e632cc6d8634f.jpg)

![CN1 (for Differential Input mode)\nA10H 19 37 AI0L\nA11H 18 36 AI1L\nA12H 17 35 AI2L\nA13H 16 34 AI3L\nA14H 15 33 AI4L\nA15H 14 32 AI5L\nA16H 13 31 AI6L\nA17H 12 30 AI7L\nAGND 11 29 AGND\nA18H 10 28 AI8L\nA19H 9 27 AI9L\nA110H 8 26 AI10L\nA111H 7 25 AI11L\nA112H 6 24 AI12L\nA113H 5 23 AI13L\nA114H 4 22 AI14L\nA115H 3 21 AI15L\n-12V 2 20 AI15L\n+12V 1 GND](.pci-9114series-manual-4/3e8c07bb6afeb156117ee3b5d312539e600b72403440a09cf3ece76c1ad424c1.jpg)

Figure 4. Pin Assignment of CN1

# Legend:

AIn: Analog Input Channel #n (for single-ended mode, n=0\~15)

AIxH: Analog Input Channel #x (for differential positive input, x=0-31)

AixL: Analog Input Channel #x (for differential negative input, x=0-31)

AGND: Ground plane for analog signals

+12V: +12V power supply output (with fuse protection)

-12V: -12V power supply output (with fuse protection)

GND: Ground Plane

# 2.6.2 Pin Assignments for CN2 & CN3

CN2 and CN3 are used for Isolated Digital input and output signals respectively. The pin assignment for CN2 and CN3 is illustrated in Figure 5.

CN3 (for Isolation Digital Output)
![Vpower 20\nEOGND 18\nDO_15 16\nDO_14 14\nDO_13 12\nDO_12 10\nDO_11 8\nDO_10 6\nDO_9 4\nDO_8 2\n19 Vpower\n17 EOGND\n15 DO_7\n13 DO_6\n11 DO_5\n9 DO_4\n7 DO_3\n5 DO_2\n3 DO_1\n1 DO_0](.pci-9114series-manual-4/8141329e969b3c3a2137d9a6e711d39d7036b05b1611f4deac214b2254c1a33f.jpg)

CN2 (for Isolation Digital Input)
![EICOM4 20\nEICOM3 18\nDI_15 16\nDI_14 14\nDI_13 12\nDI_12 10\nDI_11 8\nDI_10 6\nDI_9 4\nDI_8 2\n19 EICOM2\n17 EICOM1\n15 DI_7\n13 DI_6\n11 DI_5\n9 DI_4\n7 DI_3\n5 DI_2\n3 DI_1\n1 DI_0](.pci-9114series-manual-4/f342cefcc11e8781bbbe02b9e412aecffeb7373c75eafca1fe0dcb8fa834a8df.jpg)

Figure 5. Pin Assignments of CN2 & CN3

# Legend:

Din: Isolated Digital Input Channel #n (n=0\~15)

EICOMx: Common plane for Isolated Input group #x (x=1\~4)

Don: Isolated Digital Output Channel #n

EOGND: Isolated Output Signal Ground

Vpower: Isolated Output Driver's Power Supply

# 2.6.3 Pin Assignment for CN4

CN4 is only supported on PCI-9114A and PCI-9114 Rev. C2 or later. CN4 is used for external signal connections. The pin assignment for CN4 is illustrated in Figure 6

![N.C.\nClk_2M\n+5V\nExt_Trg\nN.C.\n2\n10\n9\nExt_Clk\nCnt_Out\nCnt_Gate\nGND\nPreTrg](.pci-9114series-manual-4/9017e229c38a7d8d342647cdb4b9dd4156c0d52386b6cbc1ef1c372c3fa2ef54.jpg)

Figure 6. Figure 2.3 Pin Assignment of CN4

# Legend:

Ext\_Clk: External Clock for Counter #0

N.C.: No Connection

Cnt\_Out: Output of Counter #0

Clk\_2M: Internal 2MHz Clock

Cnt\_Gate: External Gate Control Signal for Counter #0

+5V: +5V power supply

GND: Ground Plane

Ext\_Trg: External A/D Trigger Signal

PreTrg: External Pre-trigger Signal

# 2.7 Jumper Descriptions

# 2.7.1 Analog Input Signal Type Selection (JP1)

JP1 is only supported on PCI-9114A or PCI-9114 Rev. C2 and later. JP1 is use to select the analog input signal type. It can be either Single-Ended or Differential Input. The following diagram shows possible configurations.

![The image is a simple black-and-white line drawing of a stove. At the top, there are two small circles side-by-side, representing control knobs. Below that, there is a 2x2 grid of four larger circles, representing electric coil burners or heating elements.](.pci-9114series-manual-4/6f873f480ee522a093797221b9a47b28c1753d09cb416f59f8566e75a6c230ba.jpg)

DI

JP1: Single-Ended Input (Default)

SE

# 2.7.2 Cold Junction Sensor Selection (JP2)

JP2 is used to set the cold junction sensor. Note that JP2 is used in conjunction with JP1. The following diagrams illustrate possible configurations.

• C.J. Sensor Disabled (Default)

![The image is a black and white line drawing of a rectangular panel. The top section features three circles arranged horizontally in a row. The bottom section is a larger rectangle divided into four quadrants by intersecting vertical and horizontal lines, with a circle centered in each quadrant.](.pci-9114series-manual-4/709ef1a563f1df89e774e5f2f594bdda4fc48fc4d371ced79467e7d539c411e1.jpg)

C.J. Senor Enabled

C.J. Sensor Disabled (Default)

\- Connecting the C.J. sensor to an AD Channel under Differential Input mode. Note if JP1 is wrongly set as SE mode, the C.J sensor will be connected to CH#0 and CH#16 is connected to the ground plane. The following diagram illustrates the correct setting under D.I. mode with the C.J. sensor enabled.

![The image displays a simple black-and-white line drawing of a kitchen range (stove and oven).\n\n*   **Top Section:** The upper portion depicts a stovetop enclosed in a square. It features four burners arranged in a 2x2 grid. Each burner is illustrated as a circle with a four-pointed star or cross shape inside it.\n*   **Bottom Section:** Below a horizontal line, the lower portion represents the oven. Inside this section, there are two large circles positioned side-by-side.\n*   **Overall:** The entire appliance is framed within a rectangular border.](.pci-9114series-manual-4/afd3029fc72c8a2d16feb97df86c0c3246d8d7802aa49ac622f5347d1a493361.jpg)

DI

JP1: Differential Input

SE

![The image shows a line drawing of a vertical rectangular panel, likely an elevator control board. Inside the upper portion, a border encloses four squares arranged in a 2x2 grid. Each square contains a circle with a cross (+) in its center. Below this grid, two empty circles are positioned side-by-side.](.pci-9114series-manual-4/d8dc5b0569257ee1dde69200ada6b018896fb22485e682e952a51ed0cb218b7b.jpg)

Enable C.J.

Disable

(Normal)

JP2: Enable C.J. Sensor

\- Connecting the C.J. Sensor to an AD Channel under Single-Ended Input mode. CH#16 is used as normal single-ended input.

![The image is a simple line drawing of a rectangular electrical outlet panel.\n\n- **Top Section:** Two small, empty circles are positioned side-by-side near the top.\n- **Middle Divider:** A horizontal line separates the top section from the bottom.\n- **Bottom Section:** This area is divided vertically into two columns. Inside each column, there are two circular sockets stacked vertically. Each socket is depicted as a large circle containing a central dot flanked by two smaller dots on the left and right sides.](.pci-9114series-manual-4/ed19270bf11d93af7fe4dfa6d69ecb780598c400632929c4d05d813e6bec8cdf.jpg)

DI

JP1: Single-Ended Input (Default)

SE

![The image is a black and white schematic diagram featuring a large vertical rectangle divided into two main sections by a vertical line.\n\n**Left Section:**\n*   At the top, there is a single empty circle.\n*   Below that is a smaller rectangular box containing two circles stacked vertically. Both of these circles contain a pattern of four small black dots arranged in a 2x2 grid.\n\n**Right Section:**\n*   This section consists of a tall rectangular box.\n*   Inside, there are three circles stacked vertically.\n*   The top circle is an empty outline.\n*   The middle circle contains the same 2x2 grid of small black dots.\n*   The bottom circle also contains the same 2x2 grid of small black dots.](.pci-9114series-manual-4/42eb9aa472edd1b18b7285fa5ae9fdcca18286461d3a179bd3b52da1f3cecf91.jpg)

Enable C.J.

JP2: Enable C.J. Senor (S.E. mode)

Disable

(Normal)

# 2.7.3 Counter #0 Function Selection (JP4)

JP4 is only supported on PCI-9114A or PCI-9114 Rev. C2 and later. JP4 is used to set the operation mode for Counter #0. Counter #0 can be set to either a Pre-trigger controller or a user configurable Timer/Counter. When Counter #0 is set as a user configurable Timer/Counter, the Clock input, Gate control signal and the Counter Output of Counter #0 can be connected via CN4.

![The image displays a schematic diagram with two vertical text labels at the top: 'User' on the left and 'PreTg' on the right. Below these labels is a rectangular box containing three circles arranged horizontally. The circle on the far left is empty, while the two circles to its right are filled with a mesh or cross-hatch pattern.](.pci-9114series-manual-4/13b4437d36cb51e6049d7be21d7abda31e72fb44264428f11b1142c3e548597c.jpg)

JP4: Set Counter #0 as a

Pre-Trigger Controller (Default)

![The image is a black-and-white schematic drawing. At the bottom, there is a rectangular outline containing three circles arranged horizontally. The two circles on the left contain a cross or 'x' symbol inside them, resembling terminal points, while the circle on the far right is empty.\n\nAbove the rectangular box, there are two labels written vertically, reading from bottom to top. The text 'User' is positioned above the left two circles, and the text 'PreTrg' is positioned above the rightmost circle.](.pci-9114series-manual-4/bbace81a5da05247486e47efd37aaef6bcd9f02e2df20034fe6f90dd854d5033.jpg)

JP4: Set Counter #0 as

a User Configurable

# 2.8 Termination Board Connection

The PCI-9114(A) is equipped with a DB-37 connector. The available termination boards include:

# Connection to ACLD-9137

The ACLD-9137 can be directly connected to the card, which is equipped with a 37-pin D-sub connector. It is suitable for simple applications that do not need complex signaling conditions before an A/D conversion is performed.

# Connect with ACLD-9188

The ACLD-9188 is a general-purpose terminal board. It is equipped with a 37-pin D-sub connector. The ACLD-9138 contains LED indicators to indicate the ON/OFF status of the computer system.

# Connect with ACLD-9178

ACLD-9178 is a general purposed terminal board compatible with all cards, which comes equipped with two 20-pin header connectors.

# Connect with DIN-37D

DIN-37D is a general purposed 37-pin screw terminal with a DIN-socket. This provides for easy installation. The DIN-37D is shipped with a 37-pin cable.

![The image shows a stack of white rectangular cards. On the topmost card, the number '3' is printed in a large, bold, black font, centered within the frame. The edges of the cards beneath are visible, creating a sense of depth.](.pci-9114series-manual-4/13e83a22919e0568c8748c6c0e991cf66ff282e7ecf5f4b6ed2704e711b882e1.jpg)

# Registers

The descriptions of the registers and structure of the CI-9114(A) are outlined in this chapter. The information in this chapter will assist programmers wishing to handle the card with low-level programs.

Therefore, the low level programming syntax is introduced. This information can help assist in programming the card in the shortest possible time.

# 3.1 PCI PnP Registers

The PCI-9114(A) functions as a 32-bit PCI target device to any master on the PCI bus. It supports burst transfer to memory space by using 32-bit data. All data read and write is base on 32-bit data. There are three types of registers on the PCI-9114(A): The PCI Configuration Registers (PCR), Local Configuration Registers (LCR) and the 9111 registers.

The PCR is compliant to the PCI-bus specifications. It is initialized and controlled by the plug & play (PnP) PCI BIOS. User can study the PCI BIOS specification to understand the operation of the PCR. Please contact PCISIG to acquire the specifications of the PCI interface.

The PCI bus controller (PCI-9050) is provided by PLX technology Inc. (www.plxtech.com). For more detailed information of the LCR, please visit PLX technology's web site. It is not necessary for users to fully understand in detail the LCR if the software library is used. The PCI PnP BIOS assigns the base address of the LCR. The assigned address is located at 14h of PCR.

The PCI-9114(A) registers are shown in the next section. The base address, which is also assigned by the PCI PnP BIOS, is located at an offset of 18h of the PCR. Do not try to modify the base address and interrupt which is assigned by the PCI PnP BIOS; it may cause resource conflicts in your system

# 3.2 I/O Address Map

Most of the PCI-9114(A) registers are 16 bits. Users may access these registers with 16-bit I/O instructions. There is one 32-bit register on the PCI-9114(A). This 32-bit register occupies a LCR address space; its base address is #2. The base address is allocated by the PCI BIOS and is located at an offset 1Ch of the PCR. Users may read the PCR to obtain the LCR base address and the two PCI-9114(A) base addresses by using the PCI BIOS function call.

<table><tr><td>I/O Base Address #1</td><td>Write</td><td>Read</td></tr><tr><td>Base + 00h</td><td>Isolated DO port</td><td>Isolated DI port</td></tr><tr><td>Base + 02h</td><td>AD MUX channel no.</td><td>AD MUX channel no setting</td></tr><tr><td>Base + 04h</td><td>AD range control</td><td>AD range control read back</td></tr><tr><td>Base + 06h</td><td>AD trigger mode</td><td>AD trigger mode read back</td></tr><tr><td>Base + 08h</td><td>Interrupt control</td><td>Interrupt control read back</td></tr><tr><td>Base + 0Ah</td><td>Software AD trigger</td><td>FIFO status read back</td></tr><tr><td>Base + 0Ch</td><td>Clear H/W IRQ1</td><td>--</td></tr><tr><td>Base + 0Eh</td><td>Clear H/W IRQ2</td><td>--</td></tr><tr><td>Base + 20h</td><td>8254 Counter #0</td><td>8254 Counter #0</td></tr><tr><td>Base + 22h</td><td>8254 Counter #1</td><td>8254 Counter #1</td></tr><tr><td>Base + 24h</td><td>8254 Counter #2</td><td>8254 Counter #2</td></tr><tr><td>Base + 26h</td><td>8254 Control Registers</td><td>8254 Status Registers</td></tr><tr><td>I/O Base Address #2</td><td>Write</td><td>Read</td></tr><tr><td>Base 2 + 40h</td><td>--</td><td>32 bits AD FIFO data and channel number read</td></tr></table>

Table 1: I/O Addresses

# 3.3 A/D Data Registers

The PCI-9114(A) A/D data is stored in the FIFO buffer after conversion. The data can be transferred to the host memory by software only. 16-bit input port instructions can read the AD value. The A/D data can also be read back with the channel number together. Users will know exactly the channel number of the A/D data. However, it a 32-bit reading port instruction must be issued.

Address: BASE2 +40h

Attribute: read only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE2+40h</td><td>AD7</td><td>AD6</td><td>AD5</td><td>AD4</td><td>AD3</td><td>AD2</td><td>AD1</td><td>AD0</td></tr><tr><td>BASE2+41h</td><td>AD15</td><td>AD14</td><td>AD13</td><td>AD12</td><td>AD11</td><td>AD10</td><td>AD9</td><td>AD8</td></tr><tr><td>BASE2+42h</td><td>X</td><td>X</td><td>X</td><td>CH4</td><td>CH3</td><td>CH2</td><td>CH1</td><td>CH0</td></tr><tr><td>BASE2+43h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

AD15\~AD0: Analog to digital data. AD15 is the Most Significant Bit (MSB). AD0 is the Least Significant Bit (LSB). CH4\~CH0: Channel number of the A/D data.

# 3.4 A/D Channel Control Register

The PCI-9114(A) provides 32 SE or 16 DI channels. The channel control register is used to set the A/D channels to be converted. The 5 LSBs of this register controls the channel number. Under non-auto scanning mode, the register sets the channel number for conversion. Under auto-scanning mode, the register sets the ending channel number. Note that the read back value is the setting value and not the current selected AD channel number.

Address: BASE + 02h

Attribute: write and read

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+02h</td><td>X</td><td>X</td><td>x</td><td>CN4</td><td>CN3</td><td>CN2</td><td>CN1</td><td>CN0</td></tr><tr><td>BASE+03h</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td></tr></table>

CNn: channel number of multiplexer.

CN4 is MSB, and CN0 is LSB.

# 3.5 A/D Input Signal Range Control Register

The A/D range register is used to adjust the analog input ranges. This register directly controls the PGA (programmable gain amplifier). When a different gain value is set, the analog input range will be changed to its corresponding value accordingly.

Address: BASE + 04h

Attribute: write and read

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+04h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>G1</td><td>G0</td></tr><tr><td>BASE+05h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

The relationship between the gain setting and its A/D range is listed in the table below.

<table><tr><td>G1</td><td>G0</td><td>Gain HG/ DG</td><td>Analog Input Range of PCI-9114(A)HG</td><td>Analog Input Range of PCI-9114(A)DG</td></tr><tr><td>0</td><td>0</td><td>1 / 1</td><td>±10V</td><td>±10V</td></tr><tr><td>0</td><td>1</td><td>10 / 2</td><td>±1V</td><td>±5V</td></tr><tr><td>1</td><td>0</td><td>100 / 4</td><td>±100 mV</td><td>±2.5V</td></tr><tr><td>1</td><td>1</td><td>1000 / 8</td><td>±10 mV</td><td>±1.25V</td></tr></table>

# 3.6 A/D Status Read-back Register

The A/D FIFO buffer status can be read back from this register.

Address: BASE + 0Ah

Attribute: read only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+0Ah</td><td>X</td><td>X</td><td>X</td><td>X</td><td>AD_BUSY</td><td>FF_FF</td><td>FF_HF</td><td>FF_EF</td></tr><tr><td>BASE+0Bh</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td> $\overline{X}$ </td><td> $\overline{X}$ </td><td>X</td></tr></table>

FF\_EF: '0' means FIFO is empty

FF\_HF: '0' means FIFO is half-full

FF\_FF: '0' means FIFO is full, A/D data may have been loss

AD\_BUSY: '0' means AD is busy, the A/D data has not been latched in FIFO yet. If AD\_BUSY changes from '0' to '1', A/D data is written into FIFO.

# 3.7 Trigger Mode Control and Read-back Register

This register is used to control or read back the A/D trigger control setting and the AD range setting.

# Address: BASE + 06h

Attribute: write and read

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+06h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>PTRG</td><td>EITS</td><td>TSSEL</td><td>ASCAN</td></tr><tr><td>BASE+07h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

PTRG: Pre-trigger ON/OFF control (Only available on PCI-9114A or PCI-9114 Rev. C2 and later)

1: Pre-Trigger ON
0: Pre-Trigger OFF

EITS: External / Internal Trigger Source (Only available on PCI-9114A or PCI-9114 Rev. C2 and later)

1: External Trigger Source
0: Internal Trigger Source

TSSEL: Timer Pacer / Software Trigger

1: Timer Pacer Trigger
0: Software Trigger

ASCAN: Auto Scan Control

1: Auto Scan ON
0: Auto Scan OFF

The modes listed below applies to the PCI-9114(A) card only:

<table><tr><td>Bit 3PTRG</td><td>Bit 2EITS</td><td>Bit 1TPST</td><td>Bit 0ASCAN</td><td>Mode Description</td></tr><tr><td>0/1</td><td>0</td><td>0</td><td>0/1</td><td>Software Trigger</td></tr><tr><td>0/1</td><td>0</td><td>1</td><td>0/1</td><td>Timer Pacer Trigger</td></tr><tr><td>0/1</td><td>1</td><td>X</td><td>0/1</td><td>External Trigger</td></tr></table>

# 3.8 Interrupt Control and Read-back Register

The PCI-9114(A) has a dual interrupt system, thus two interrupt sources can be generated and be checked by the software. This register is used to select the interrupt sources.

Address: BASE + 08h

Attribute: write and read

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+08h</td><td>X</td><td>X</td><td>X</td><td>X</td><td>MUX</td><td>FFEN</td><td>ISC1</td><td>ISC0</td></tr></table>

ISC0: IRQ0 signal select

0: IRQ on the ending of the AD conversion (EOC)

1: IRQ when FIFO is half full

ISC1: IRQ1 signal select (Timer Interrupt only)

FFEN: FIFO enable pin

0: FIFO Enable (Power On default value)

1: FIFO Disable

(To reset FIFO, set FFEN sequence as 0 -> 1 -> 0)

MUX: This is a read-only bit and it indicates the setting of JP1.

1: Single-ended

0: Differential-input

# 3.9 Software Trigger Register

To generate a trigger pulse to the PCI-9114(A) to initiate a A/D conversion, write any data to this register, this will trigger the A/D converter.

Address: BASE + 0Ah

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+0Ah</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr><tr><td>BASE+0Bh</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

# 3.10 Hardware Interrupt Clear Registers

Since the PCI interrupt signal is level triggered, the interrupt clear register must be written to in order to clear the flag after processing an interrupt request event; otherwise, any further interrupt request inserted will cause the software to hang on processing the interrupt event.

There are two interrupt clear registers. The two registers are used to clear IRQ1 and IRQ2 respectively.

Address: BASE + 0Ch

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+0Ch</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

Address: BASE + 0Eh

Attribute: write only

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>BASE+0Eh</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td></tr></table>

# 3.11 Timer/Counter Register

The 8254 chip occupies 4 I/O address locations in the PCI-9114(A) as shown below. Refer to NEC's or Intel's data sheet for full description of the 8254 features. Data sheets are available for download from the following web sites:

1. http://support.intel.com/support/controllers/peripheral/231164.htm
2. http://www.tundra.com

Address: BASE + 20h \~ BASE + 26h

Attribute: read / write

Data Format:

<table><tr><td>Base + 20h</td><td>Counter 0 Register ( R/W)</td></tr><tr><td>Base + 22h</td><td>Counter 1 Register ( R/W)</td></tr><tr><td>Base + 24h</td><td>Counter 2 Register ( R/W)</td></tr><tr><td>Base + 26h</td><td>8254 CONTROL BYTE (W)</td></tr></table>

# 3.12 High Level Programming

To operate the PCI-9114(A), the register structures can be bypassed, if high-level application programming interface (API) is used to control the PCI-9114(A) card. The software library including a DOS library for Borland C/C++ is available in the All-in-one CD. Refer to chapter 5 for more information.

![The image displays a white square card featuring the number **4** in a large, bold, black font centered inside. The card has a thick black border and appears to be part of a stack, with layers of identical cards visible behind the top one.](.pci-9114series-manual-4/48c5c3256bdecf363954ebade36574e4002280c645072ac64f45e0618823dffc.jpg)

# Operation Theory

The operation theory of the PCI-9114(A) card is described in this chapter. This will help assist in understanding how to manipulate or to program the PCI-9114(A).

# 4.1 A/D Conversion

Before programming the PCI-9114(A) to perform any A/D conversion, the following topics need to be understood:

• A/D conversion procedure
• A/D signal source control
• A/D trigger source control
• A/D data transfer mode
- Interrupt System (refer to section 4.2)
• A/D data format

Note: Since some A/D data transfer modes will use system interrupt resources; an understanding of the interrupt system (section 4.2) is required.

# 4.1.1 A/D Conversion Procedure

To use the A/D converter, the properties of the signal to be measured must first be understood. A decision on which channels to use, to connect signals to must be made. Refer to the chapter 2. In addition, the A/D signal sources, including the A/D channel, A/D gain, and A/D signal types must also be defined. Refer to section 4.1.2 for A/D signal source control information.

After deciding on the A/D signal source, the trigger source must be defined. The A/D converter will start to convert signals to a digital value when a trigger signal is on the rising edge. Refer to section 4.1.3 for details of the two available trigger sources.

The A/D data is then transferred into the PC's memory for further processing. The data can be read back using I/O instructions, which is handled by the software or transferred to memory via the interrupt. Refer to section 4.1.4 for information about multi-configurations of A/D data transfers.

To process the A/D data, an understanding of the A/D data format is required. Refer to section 4.1.5 for details.

# 4.1.2 A/D Signal Source Control

To control the A/D signal source, the signal type, signal channel and signal range must be considered.

# Signal Type

The A/D signal sources of the PCI-9114(A) can be single ended (SE) or differential input (DI). There are 32 SE or 16 DI A/D channels available. To avoid ground loops and to obtain the most accurate measurement for the A/D conversion, it is important to understand the signal source type.

Single-ended (SE) mode means the voltage of the signal to be measured is relative to an isolated ground (IGND), therefore is suitable in conditions where there is a floating signal source. A floating source means the signal source have no connection to real ground or to the PC ground. Figure 7 illustrates a single-ended Analog Input signal connection. Note that when more than two floating sources are connected, the sources must have a common ground.

Differential input (DI) mode means the voltage of the signal to be measured is a pair of signals, for example, AI3L and AI3H is a differential pair. The AD circuit measures the voltage difference between the differential pair. Common mode noise can be reduced under this mode. Note that the differential signal pair must have a common ground. Figure 8 illustrates a differential analog signal input connection. By using differential input mode, the common mode noise on AIHn and AILn is reduced.

![This diagram illustrates a signal acquisition chain.\n\n**Labeled Blocks:**\n*   **Floating Signal Sources:** A group of circles on the left.\n*   **Analog Input Multiplexer:** A rectangular block in the center.\n*   **Operational Amplifier:** A triangular block on the right.\n\n**Labels and Connections:**\n*   Above the signal sources is the text **n = 0, ..., 31**.\n*   Inside the signal source group, circles are labeled **V1** and **V2**, with **...** indicating intermediate sources.\n*   Lines extend from the top of each source circle to the left side of the multiplexer. These inputs are represented by a vertical column of black dots. The top input dot is labeled **AI1**.\n*   A common line connects the bottom terminals of the source circles, leading down to a **ground** symbol (a triangle pointing downwards).\n*   A single line exits the right side of the **Analog Input Multiplexer** and enters the flat base of the **Operational Amplifier** triangle.\n*   A line exits the tip of the triangle and leads to the right, labeled **To A/D Converter**.](.pci-9114series-manual-4/cbab0613bf04b0833874cf50d48d5f9360e64b62acd5eb35bddf26ca1e2ea5d0.jpg)

Figure 7. Signal sources and single-ended connection

![n = 0, ..., 8\nGrounded\nSignal\nSources\nA/Hn\n+\n-\nTo A/D\nConverter\nA/Ln\nGND\nVcm = VG1 - VG2\nVG1\nVG2](.pci-9114series-manual-4/52f56bcf37bc2d56b6e242dd1ee4cd60a050b189dea60186c83a62d791e56ae5.jpg)

Figure 8. Grounded source and differential input

# Signal Channel Control

There are two ways to control the channel number. Either by software programming or by auto channel scanning which is controlled by the ASCAN bit in the AD trigger mode control register. When ASCAN is cleared (0), the value of the AD Channel Control register defines the channel to be selected.

When ASCAN is set to 1, the value in the AD channel control register defines the ending channel number for the auto-scanning operation. Under auto scan mode, channels are scanned from channel 0 to the ending channel. Whenever a trigger signal is on the rising edge, the channel number to be selected will increase automatically. For example, if the ending channel number is 3, the auto channel scanning sequence is 0,1,2,3,0,1,2,3, ..., until the ASCAN bit is cleared.

# Signal Range

The proper setting for the signal range is important in data acquisition. e.g. the input signal may be saturated if the A/D gain is too large or the resolution is to small if the signal is at very low level. The maximum A/D signal range for the PCI-9114(A) is $+/-$ 10 volts when the programmable gain value is 1. The A/D gain control register controls the maximum signal input range. The signal gain is programmable with 4 different levels (1,10,100,1000) or (1,2,4,8). The signal range for the 32 channels is the same for all channels. The available signal polarity on the PCI-9114(A) is bi-polar only, however, the 16-bit high resolution PCI-9114(A) can cover all 12-bit uni-polar applications.

# 4.1.3 A/D Trigger Source Control

An A/D conversion is initiated by a trigger source; the A/D converter will then start to convert analog signals to a digital value. With the PCI-9114(A), two internal sources can be selected: a software trigger or the timer pacer trigger. The A/D operation mode is controlled by the A/D trigger mode register. In total there are two trigger sources provided by the PCI-9114(A). Different trigger conditions are specified below:

# Software trigger (TSSEL=0)

The trigger source is software controlled in this mode. That is, the A/D conversion is initiated when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled by the software. However, it is difficult to control a fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger. Refer to the interrupt control section (section 4.2) for fixed rate timer interrupt operation.

# Timer Pacer Trigger (TSSEL=1)

An on-board 8254-timer / counter chip is available and is able to provide a trigger source for an A/D conversion at a fixed rate. The 2 counters of the 8254 chip are cascaded together to generate a trigger pulse at precise intervals. Refer to section 4.3 for information about the 8254 architecture. This mode is ideal for high speed A/D conversion. It can be combined with the FIFO half-full interrupt or EOC interrupt to transfer data. It is also possible to use software FIFO polling to transfer data. It's recommended that this mode be used if your application needs a fixed and accurate A/D sampling rate.

# External Trigger (EITS=1, TPST=don't care)

Through pin-4 of CN4 (ExtTrig), an A/D conversion can also be triggered by an external signal. An A/D conversion starts when ExtTrig changes from high to low. The conversion rate of this mode tends to be more flexible than the previous two modes because external devices often are more flexible in functions. An external trigger can be combined with FIFO half interrupt, EOC interrupt or program FIFO polling for data transfers.

# 4.1.4 A/D Data Transfer Modes

The A/D data are buffered in the FIFO memory. The FIFO size of the PCI-9114(A) is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO can buffer 10.24 ms of analog signals. After the FIFO is full, the lasting incoming data will be lost. The software must read out the FIFO data before it becomes full.

The data must be transferred to the host memory when the data is ready and before the FIFO is full. With the PCI-9114(A), many data transfer modes can be used. The different transfer modes are in the following section:

# Software Data Polling

The software data polling is the easiest way to transfer A/D data. This mode can be used with software A/D trigger mode. After the software triggers the A/D conversion, the software polls the FF\_EF bit of the A/D status register until it becomes low.

If the FIFO is empty before the A/D starts, the FF\_EF bit will be low. After the A/D conversion is completed, the A/D data is written into FIFO buffer immediately, thus the FF\_EF becomes high. The FF\_EF bit can be considered to be a flag to indicate converted data ready status. That is, FF\_EF is high means the data is ready. Note that, while A/D is converted, the ADBUSY bit is low. After A/D conversion, the ADBUSY becomes high to indicate not busy. DO NOT use this bit to poll the AD data.

It is possible to read A/D converted data without polling. The A/D conversion time will not exceed $10\mu \mathrm{s}$ on the PCI-9114 card, and $4\mu \mathrm{s}$ on PCI-9114A card. Hence, after a software trigger, the software can wait for at least $10\mu \mathrm{s}$ or $4\mu \mathrm{s}$ before reading the A/D register without polling.

The data polling transfer is suitable for applications that requires to process AD data in real time. Especially, when combined with a timer interrupt, the timer interrupt service routine can use the data polling method to get multi-channel A/D data in real time and with a fixed data sampling rate.

# FIFO Half-Full Polling

The FIFO half-full polling mode is the most powerful AD data transfer mode. The 1K-word FIFO buffer can store up to 10.24 ms of analog data with a 100KHz-sampling rate (10.24ms = 1024 / 100KHz), or 4.096 ms of analog data under a 250KHz-sampling rate (4.096ms = 1024 / 250KHz). Theoretically, the software can poll the FIFO buffer every 10 or 4 ms.

It's recommended that users check their system to find out the user software's priority in special application. If the application software is at the highest priority, polling the FIFO every 10 ms is suitable. However, the user's program must check the FIFO if it is full or empty every time the data is read.

To avoid problems, the half-full polling method is used. If the A/D trigger rate is 100KHz, the FIFO will be half-full (512 words) in 5.12 ms. If the user's software checks the FIFO for half full signals every 5 ms and the FIFO is not half-full, the software does not read the data. When the FIFO is full, the AD FIFO is overflowing. This means the sampling rate is higher than what the users' expects or the polling rate is too slow. It is also possible due to system occupation of CPU resources thus reducing the polling rate. When the FIFO is half-full and not full, the software can read one “block” (512 words) of A/D data without checking the FIFO status.

Usually, the timer trigger is used under this mode; therefore the sampling rate is fixed. This method also utilizes the minimal CPU resources because it does not necessary need to be the highest priority. The other benefit with this method is it does not use any hardware interrupt resources. Therefore, the interrupt is reserved for system clocks or emergency external interrupt requests.

# EOC Interrupt Transfer

The PCI-9114(A) provides traditional hardware end-of-conversion (EOC) interrupt capabilities. Under this mode, an interrupt signal is generated when the A/D conversion is ended and the data is ready to be read from the FIFO. It is useful to combine the EOC interrupt transfer with the timer pacer trigger mode. After an A/D conversion is completed, the hardware interrupt will be inserted and its corresponding ISR (Interrupt Service Routine) will be invoked and executed. The ISR program can read the converted data. This method is most suitable for data processing applications under real-time and fixed sampling rates.

# FIFO Half-Full Interrupt Transfer

Sometimes, the applications do not need real-time processing, but the foreground program is too busy to poll the FIFO data, then the FIFO half-full interrupt transfer mode is useful. In addition, if an external A/D trigger source is used, the sampling rate may not be easy to predict, then this method could be applied because the CPU only be interrupted when the FIFO is half-full, thus reserving the CPU load.

Under this mode, an interrupt signal is generated when FIFO become half-full, that means there are 512 word data in the FIFO already. The ISR can read a block of data at every interrupt occurring. This method is very convenient to read A/D in size of a “block” (512 words) and it is benefit for software programming.

# 4.1.5 Pre-Trigger Control

# (Only available in PCI-9114A or PCI-9114 Rev.C2 and later)

In certain applications, the data acquisition is applied and stopped under special hardware signals. Without Pre-Trigger functions, the software can start the A/D at any time, but it is very difficult to stop the A/D in real-time using a software application. Under “Pre-Trigger” mode, the pre-trigger (PTRG) signal (pin-9 of CN4) and the 8254 counter are used to “STOP” the A/D sampling.

After setting up the Pre-Trigger mode, the hardware continuously acquires A/D data and waits for the pre-trigger signal. Before the pre-trigger signal is inserted, the software must read data from the FIFO buffer to prevent the FIFO buffer from becoming full.

When the pre-trigger signal is inserted, the counter starts to count down from the initial counter value N and counts the number of A/D conversion trigger signals. The A/D trigger will be disabled automatically when the counter value reaches zero. The value of N can be 1 to 65535 and the last A/D data is sampled after the pre-trigger signal. The software must continuously read data out from the FIFO buffer to prevent the FIFO from becoming full. The software should also poll the counter value to check if the A/D sampling has stopped.

To set up Pre-Trigger mode, the following steps should be followed:

1. Set Pre-Trigger Mode Off: PTRG = OFF.
2. Set 8254 Counter #0 value N (N=1\~65535). Note that the larger the counter value, the more host memory buffer is needed.
3. Set up A/D data acquire, including, A/D range, channel scan, data transfer mode and so on.
4. Set Pre-Trigger Mode On: PTRG = ON.
5. Read A/D data into host PC memory using appropriate data transfer method otherwise the FIFO can become full. At the same time, wait for the pre-trigger signal and check if the 8254 Counter # 0 value is at zero.
6. If the A/D is stopped, set the Pre-Trigger Mode off and process the data, which is stored in the host memory.
7. Go to Step 1 to set the Pre-Trigger mode and wait the next pre-trigger event.

The Pre-Trigger timing is shown as following:

![The flowchart depicts a process involving pre-trigger and post-trigger phases, organized around a central horizontal timeline.\n\n**Labeled Blocks:**\n*   'Set Pre-Trigger mode'\n*   'External Pre-Trigger Signal is Inserted'\n*   'Counter # 0 counting from N down to 0'\n*   'Acquire Infinite A/D data before Pre-Trigger Signal is inserted'\n*   'Acquire N A/D data after Pre-trigger Signal is inserted'\n\n**Connections:**\n*   A downward arrow connects 'Set Pre-Trigger mode' to a central horizontal blue line.\n*   A downward arrow connects 'External Pre-Trigger Signal is Inserted' to the central horizontal blue line.\n*   The text 'Counter # 0 counting from N down to 0' is positioned above the central horizontal blue line without a connecting arrow.\n*   A downward arrow on the far right connects to the central horizontal blue line.\n*   Below the central horizontal blue line, a bracket-like structure of blue lines connects to the timeline.\n    *   A vertical line drops from the left side of the central line.\n    *   A vertical line rises from the middle of the bottom structure up to the central line.\n    *   A vertical line rises from the right side of the bottom structure up to the central line.\n*   The text 'Acquire Infinite A/D data before Pre-Trigger Signal is inserted' is located in the left section defined by the bottom structure.\n*   The text 'Acquire N A/D data after Pre-trigger Signal is inserted' is located in the right section defined by the bottom structure.](.pci-9114series-manual-4/b2f55d97a85647ac87b094e7cb37196df68e988eb7458a69924ddd0609d0f76c.jpg)

If the application acquires data after the pre-trigger signal, only the last N data needs to be stored. The maximum value of N is 65535. If the application only needs to acquire data before the pre-trigger signal, set N=1. Only one extra data will be sampled after the pre-trigger signal.

# 4.1.6 A/D Data Format

The range for the A/D data read from the FIFO port is from -32768 to 32767. If the A/D gain is 1, the A/D signal range is $-10\mathrm{V} \sim +10\mathrm{V}$ . The relationship between the voltage and its decimal value is shown in the following table:

<table><tr><td rowspan="2">A/D Data (Hex)</td><td rowspan="2">Decimal Value</td><td>Voltage (Volts)</td></tr><tr><td>±10V (Bipolar)</td></tr><tr><td>7FFF</td><td>32767</td><td>+9.9997</td></tr><tr><td>4000</td><td>16384</td><td>+5.0000</td></tr><tr><td>0001</td><td>1</td><td>+0.0003</td></tr><tr><td>0000</td><td>0</td><td>+0.0000</td></tr><tr><td>FFFF</td><td>-1</td><td>-0.0003</td></tr><tr><td>C000</td><td>-16385</td><td>-5.0000</td></tr><tr><td>8001</td><td>-32767</td><td>-9.9997</td></tr><tr><td>8000</td><td>-32768</td><td>-10.0000</td></tr></table>

The formula between the A/D data and its analog value is:

$$
\text { Voltage } = (A D \_ D a t a * 1 0) / (3 2 7 6 8 * \text { gain }) \quad - - B i p o l a r
$$

Where the gain is 1,10,100, 1000 for HG version and 1,2,4,8 for DG version.

# 4.2 Interrupt Control

# 4.2.1 System Architecture

The PCI-9114(A)'s interrupt system is a powerful and flexible system, which is suitable for A/D data acquisition and many applications. The system is a Dual Interrupt System. The dual interrupt means the hardware can generate two interrupt request signals at the same time and the software can service these two request signals using ISR. Note that the dual interrupt does not mean the card occupies two IRQ levels.

The two interrupt request signals (INT1 and INT2) come from the digital input signals or the timer/counter output. An interrupt source multiplexer (MUX) is used to select the IRQ sources. Fig 9 shows the interrupt system

![Based on the provided block diagram, here is the accurate description of the labeled blocks and connections:\n\n**Blocks:**\n*   **PCI Controller** (Left)\n*   **IRQ Flip-Flops** (Center)\n*   **INT1 MUX** (Right)\n\n**Connections:**\n*   **INT #A**: An arrow points left from the **PCI Controller**.\n*   **INT1** and **INT2**: Two arrows point left from the **IRQ Flip-Flops** to the **PCI Controller**, labeled **INT1** (top) and **INT2** (bottom).\n*   **INT1 MUX to IRQ Flip-Flops**: An arrow points left from the **INT1 MUX** to the **IRQ Flip-Flops**.\n*   **Timer Pacer**: An arrow points left into the **IRQ Flip-Flops**.\n*   **AD EOC** and **FIFO Half-full**: Two arrows point left into the **INT1 MUX**.\n*   **Clear IRQ#1, #2**: An arrow points up from the bottom into the **IRQ Flip-Flops**.](.pci-9114series-manual-4/b8480fdc990089ee25b96d11686b45bc5469c981ad981b36a49ba52634bad56c.jpg)

Figure 9. Dual Interrupt System of PCI-9114(A)

# 4.2.2 IRQ Level Setting

There is only one IRQ level is used by this card, although it is a dual interrupt system. This card uses INT #A interrupt request signal on the PCI bus. The motherboard circuits will transfer INT #A to one of the AT bus IRQ levels. The IRQ level is set by the PCI plug and play BIOS and is saved in the PCI controller. It is not necessary for users to set the IRQ level.

# 4.2.3 Dual Interrupt System

The PCI controller of the PCI-9114 can receive two hardware IRQ sources. However, a PCI controller can generate only one IRQ on the PCI bus, the two IRQ sources must be distinguished by the ISR of the application software if the two IRQ are both used.

The application software can use the “\_9114\_Get\_Irq\_Status” function to distinguish which interrupt is inserted. After servicing an IRQ signal, users must check if another IRQ is also asserted, then clear the current IRQ to allow the next IRQ to occur.

The two IRQs are named as INT1 and INT2. INT1 comes from AD EOC or the FIFO half-full flag. INT2 comes from timer's pacer output or the external interrupt request. The sources of INT1 and INT2 are selective by the Interrupt Control (ISC) Register.

Because the PCI-9114 is a dual interrupt system, you can use the FIFO half-full and external interrupt at the same time if your software ISR can distinguish these two events.

# 4.2.4 Interrupt Source Control

There are two bits to control the IRQ sources of INT1 and INT2. Refer to section 4.9 for details of these bits. In addition, the PCI controller itself can also control the usage of the interrupt. To manipulate the interrupt system more easily, ADLINK recommend you to use the function \_9114\_INT\_Source\_Control to control the IRQ source so that you can disable one or two of the IRQ sources.

Note that even if you disable both IRQ sources without changing the initial condition of the PCI controller, the PCI BIOS will still assign an IRQ level to the PCI card and it will still occupy the PC's resources. It is not recommended that the PCI cards initial condition be re-design with a users' application software. If users want to disable the IRQ level, please use the ADLINK software utility to change the interrupt settings

# 4.3 Isolated Digital Input

There are 16 Isolated Digital input signals. Each digital input signal is connect to a photo isolator such that the signal is isolated from the ground or the power plane of the host PC. Figure 10 illustrates a single digital input circuits.

![DI_n R=2.4K Ohm\nPhoto Isolator\nto digital circuits](.pci-9114series-manual-4/c40ef8f5119abc8ebd3f07cc1f5d95ffe22a769e1ef15775df3351cba5766063.jpg)

Figure 10. Isolated Input Circuits

The Isolated Digital input could be an AC input. The isolation voltage is 5000 V rms. The input resistance is 1.2K Ohm.

Note that the 16 DI signals are partitioned into 4 groups. Each group is based on a common plane. Every two groups are mutual isolated. Refer the Figure 11 and the Table 2 for the four groups.

<table><tr><td>Signal Names</td><td>Common Signal</td></tr><tr><td>ID_0~ID_3</td><td>EICOM1</td></tr><tr><td>ID_4~ID_7</td><td>EICOM2</td></tr><tr><td>ID_8~ID_11</td><td>EICOM3</td></tr><tr><td>ID_12~ID_15</td><td>EICOM4</td></tr></table>

Table 2: Digital input signals and ground plane

The common plane could be either common power or common ground. The following diagram shows the EICOM as common ground. An external device or circuit will provide the power source or current source.

![Isolated Input 2.4K Ohm\nEICOM](.pci-9114series-manual-4/2b499a68e596f53d779405d862b616d28c049b79ec39128ada6e1e80ccc08e7c.jpg)

Figure 11. Common ground

The following diagram shows the EICOM as common power. An external device or circuit will provide the power source and current sink. Most open collector output devices can be connected to the PCI-9114(A) using this configuration.

![Isolated Input\n2.4K Ohm\nEICOM](.pci-9114series-manual-4/e74de6f6c1353bb0b156229d9a7c8492462b9c4714f52d0839d32610321837a2.jpg)

Figure 12. Common power

# 4.4 Isolated Digital Output

There are 16 Isolated Digital output signals. Darlington transistors drive the digital output signals. Figure 13 shows the output circuits.

Note that the 16 DO signals uses a common ground and common external power source.

![From digital circuits\nVpower\nDO_n\nEOGND](.pci-9114series-manual-4/126b8ab3d9d5b5e32d418075b3e7b9608120c29c7596f20462550c41f7201f3c.jpg)

Figure 13. Digital output circuits

The EOGND pin is used via a (fly-wheel) diode, this will protect the driver if an inductive load from such as a relay, motor or solenoid is present. If the loading is resistive such as from resistors or LEDs, the connection to the fly-wheel diode is not necessary.

The first step in connecting the output to an external device is to distinguish the type of load. For example, if the load is a LED or a resistor, connection diagram below can be used.

![From digital circuits\nVpower\nPower Supply\nDO_n\nLoad\nEOGND](.pci-9114series-manual-4/967c5f105fdf8c95ee66de4791b517fc736a06dc944696e6f33a0ac621eced08.jpg)

Figure 14. Opto-isolated output circuit for resistive loads

If the load is inductive such as from a relay, the diagram below can be used. The power supply must be from an external source in order to form a fly-wheel current loop.

![From digital circuits\nVpower\nPower Supply\nDO_n\nLoad\nEOGND](.pci-9114series-manual-4/4abcabac4a0370940f519386578bd89f1e0519ef65ee627795f2122a79d88608.jpg)

Figure 15. Opto-isolated output circuit for inductive loads

# 4.5 Timer/Counter Operation

# 4.5.1 Introduction

One 8254 programmable timer/counter chip is integrated into the PCI-9114(A). The 8254 chip supports 3 counters and can operate in 6 different operation modes for each counter. The block diagram of the timer/counter system is shown in the diagram below.

![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Blocks and Labels:**\n*   **AD Trigger Signal**: An input signal at the top left.\n*   **Connector Block**: A small box with three pins.\n*   **(CN3 Pin#1)**: Label near the connector block.\n*   **Pre-Trigger Signal**: An input signal on the left.\n*   **(CN4 Pin#9)**: Label below 'Pre-Trigger Signal'.\n*   **Pre-Trigger Controller**: A rectangular block receiving the pre-trigger signal.\n*   **(CN4 Pin#5)**: Label near the 'Gate Control' text.\n*   **Gate Control**: Text describing a signal line.\n*   **8254 Chip**: A large rectangular block containing three sections:\n    *   **Counter #0**: Top section with inputs 'C' and 'G', and output 'O'.\n    *   **Timer #1**: Middle section with inputs 'C' and 'G', and output 'O'.\n    *   **Timer #2**: Bottom section with inputs 'C' and 'G', and output 'O'.\n*   **(CN4 Pin#3)**: Label near the output of Counter #0.\n*   **Internal Timer Pacer**: Output label from Timer #1.\n*   **Internal 2 MHz Clock**: Input signal label.\n*   **'H'**: Labels appearing twice near the connections to the timer inputs.\n*   **Note**: Text at the bottom reading 'Note: Counter #0 only available in PCI-9114A and PCI-9114 Rev. C2 or later'.\n\n**Connections:**\n*   **AD Trigger Signal** connects to the small connector block (labeled with 3 pins). The output of this block connects to the 'C' input of **Counter #0**. The text **(CN3 Pin#1)** is associated with this path.\n*   **Pre-Trigger Signal** and **(CN4 Pin#9)** connect to the **Pre-Trigger Controller**. The output of the controller connects to a line labeled **Gate Control**, which then connects to the 'G' input of **Counter #0**. The text **(CN4 Pin#5)** is located above the 'Gate Control' label.\n*   The **8254 Chip** has two outputs:\n    *   The 'O' output of **Counter #0** connects to **(CN4 Pin#3)**.\n    *   The 'O' output of **Timer #1** connects to **Internal Timer Pacer**.\n*   The **Internal 2 MHz Clock** signal splits and connects to the 'C' inputs of both **Timer #1** and **Timer #2**. These connections are labeled with **'H'**.\n*   The 'O' output of **Timer #2** loops back to its own 'G' input.](.pci-9114series-manual-4/8e96a30b126d59882a2497f7e90c201160c258a4f6975467d941437aabb79322.jpg)

Figure 16. Timer/Counter system of PCI-9114(A).

# 4.5.2 Pacer Trigger Source

Timer #1 and #2 are cascaded together to generate the timer pacer trigger for the A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4=500K, which exceeds the maximum A/D conversion rate of the PCI-9114(A) (80KHz). The minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that may never be used. The output of the programmable timer can be used as a pacer interrupt source or a timer pacer trigger source for an A/D conversion. In the software library, timer #1 and #2 is set as mode 2 (rate generator).

# 5

# C/C++ Library

This chapter describes the software library that operates the PCI-9114. Only functions in the DOS library and Windows 95 DLL are described. Refer to the PCIS-DASK function reference manual, which is included in ADLINK CD, for details of Windows 98/NT/2000 DLL functions.

The function prototypes and useful constants are defined in the header files in the LIB (DOS) and INCLUDE (Windows 95) directories. For Windows 95 DLL, the developing environment can be Visual Basic 4.0 or above, Visual C/C++ 4.0 or above, Borland C++ 5.0 or above, Borland Delphi 2.x (32-bit) or above, or any Windows programming language that allows calls to a DLL.

# 5.1 Libraries Installation

Refer to the “Software Installation Guide” for details about how to install the software libraries for DOS, Windows 95 DLL, or PCIS-DASK for Windows 98/NT/2000.

The device drivers and DLL functions for Windows 98/NT/2000 are included in the PCIS-DASK. Refer to the PCIS-DASK user's guide and function reference, which is included in the ADLINK CD, for detail programming information.

# 5.2 Programming Guide

# 5.2.1 Naming Convention

The functions of the NuDAQ PCI or NuIPC CompactPCI card software drivers uses full-names to represent the functions' real meaning. The naming convention rules are:

Under a DOS Environment:

\_{hardware\_model}\_{action\_name}. e.g. \_9114\_Initial().

All functions in the PCI-9114(A) driver begin with 9114 as {hardware\_model} and can be used by the PCI-9114(A)DG and PCI-9114(A)HG models.

In order to recognize the difference between a DOS library and a Windows 95 library, a capital "W" is placed at the start of each function name for Windows 95 DLL drivers, e.g. w\_9114\_Initial().

# 5.2.2 Data Types

We have defined some data type in Pci\_9114.h (DOS) and Acl\_pci.h (Windows 95). These data types are used by the NuDAQ Card's library. We suggest you use these data types in your application programs. The following table shows the data type names and their range.

<table><tr><td>Type Name</td><td>Description</td><td>Range</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td></tr><tr><td>U32</td><td>32-bit unsigned integer</td><td>0 to 4294967295</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>-1.797683134862315E308 to 1.797683134862315E309</td></tr><tr><td>Boolean</td><td>Boolean logic value</td><td>TRUE, FALSE</td></tr></table>

# 5.3 \_9114\_Initial

# @ Description

This function is used to initialize the PCI\_9114(A). Each PCI\_9114(A) card must be initialized by this function before other function calls are permitted.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_Initial (U16 *existCards, PCI_INFO *info)
C/C++ (Windows 95)
U16 W_9114_Initial (U16 *existCards, PCI_INFO *info)
Visual Basic (Windows 95)
W_9114_Initial (existCards As Integer, info As PCI_INFO) As Integer
```

# @ Argument

```txt
existCards: numbers of existing PCI-9114(A) cards
info: relative information of the PCI-9114(A) cards
```

# @ Return Code

```txt
ERR_NoError
ERR_BoardNoInit
ERR_PCIBiosNotExist
```

# 5.4 \_9114\_Software\_Reset

# @ Description

This function is used to reset the I/O port configuration. Note that this function does not reset the PCI bus and the hardware setting won't be changed.

# @ Syntax

```c
C/C++ (DOS)
void _9114_Software_Reset (U16 cardNo)
C/C++ (Windows 95)
void W_9114_Software_Reset (U16 cardNo)
Visual Basic (Windows 95)
W_9114_Software_Reset (ByVal cardNo As Integer)
```

# @ Argument

```txt
cardNo: The card number of initialized PCI-9114(A) card
```

# @ Return Code

None

# 5.5 \_9114\_DO

# @ Description

This function is used to write data to the digital output port. There are 16 digital output channels supported by the PCI-9114(A).

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_DO (U16 cardNo, U16 DOData);
C/C++ (Windows 95)
U16 W_9114_DO (U16 cardNo, U16 DOData)
Visual Basic (Windows 95)
W_9114_DO (ByVal cardNo As Integer, ByVal DOData As Integer)
As Integer
```

# @ Argument

```txt
cardNo: The card number of initialized PCI-9114(A) card
DOData: The value will be written to digital output port
```

# @ Return Code

```txt
ERR_NoError
```

# 5.6 \_9114\_DI

# @ Description

This function is used to read data from the digital input port. There are 16 digital input channels supported by the PCI-9114(A). The digital input status can be accessed using this function.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_DI (U16 cardNo, U16 far *DIData)
C/C++ (Windows 95)
U16 W_9114_DI (U16 cardNo, U16 *DIData)
Visual Basic (Windows 95)
W_9114_DI (ByVal cardNo As Integer, DIData As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of initialized PCI-9114(A) card
DIData: The value accessed from digital input port
```

# @ Return Code

```txt
ERR_NoError
```

# 5.7 \_9114\_AD\_Read\_Data

# @ Description

This function is used to read AD converted data from the AD Data register. The resolution of the A/D converted data is 16 bits.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Read_Data (U16 cardNo, U16 far *ADData)
```

```txt
C/C++ (Windows 95)
U16 W_9114_AD_Read_Data (U16 cardNo, U16 *ADData)
```

Visual Basic (Windows 95)
```c
W_9114_AD_Read_Data (ByVal cardNo As Integer, ADData As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of initialized PCI-9114(A) card ADData: A/D converted value. Bit 0 is the LSB of A/D converted data and bit 15 is the MSB of A/D converted data.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.8 \_9114\_AD\_Read\_Data\_Repeat

# @ Description

This function is used to read AD converted data from the data register n times continuously.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Read_Data_Repeat (U16 cardNo, I16 far *ADData, U16 n)
C/C++ (Windows 95)
U16 W_9114_AD_Read_Data_Repeat (U16 cardNo, I16 *ADData, U16 n)
Visual Basic (Windows 95)
W_9114_AD_Read_Data_Repeat (ByVal cardNo As Integer, ADData As Integer, ByVal n As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized ADData: A/D converted value. Bit 0 is the LSB of A/D converted data and bit 15 is the MSB of A/D converted data.
n: The number of times to read the AD conversion data
```

# @ Return Code

```txt
ERR_NoError
```

# 5.9 \_9114\_AD\_Read\_Data\_MUX

# @ Description

This function is used to read data from the A/D Data Registers. The A/D Data and Channel Number Register is a 32-bit register. Refer to section 4.2 for descriptions of the A/D Data and Channel Number Register.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Read_Data_MUX (U16 cardNo, U32 far *ADData)
C/C++ (Windows 95)
U16 W_9114_AD_Read_Data_MUX (U16 cardNo, U32 *ADData)
```

# Visual Basic (Windows 95)

```txt
W_9114_AD_Read_Data_MUX (ByVal cardNo As Integer, ADData As Long) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized ADData: A/D converted value. The resolution of A/D conversion data is 16-bit. The unsigned integer data format of ADData is as follows:
bit 0~15:A/D converted data
bit 16~20:converted channel no.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.10 \_9114\_AD\_Read\_Data\_Repeat\_MUX

# @ Description

This function is used to read data from the A/D Data and Channel Number Register n times continuously. The A/D Data and Channel Number Register is a 32-bit register. Refer to section 4.2 for descriptions of the A/D Data and Channel Number Register.

@ Syntax
```csv
C/C++ (DOS)
U16 _9114_AD_Read_Data_Repeat_MUX (U16 cardNo, U32 far *ADData, U16 n)

C/C++ (Windows 95)
U16 W_9114_AD_Read_Data_Repeat_MUX (U16 cardNo, U32 *ADData, U16 n)

C/C++ (Windows 95)
W_9114_AD_Read_Data_Repeat_MUX (ByVal cardNo As Integer, ADData As Long, ByVal n As Integer) As Integer
```

@ Argument
```txt
cardNo: The card number of PCI-9114(A) card initialized
ADData: A/D converted value. The resolution of the AD conversion data is 16-bit. The unsigned integer data format of ADData is as follows:
bit 0~15:A/D converted data
bit 16~20:converted channel no.
n: The timer of times to read the AD conversion data.
```

@ Return Code
```txt
ERR_NoError
```

# 5.11 \_9114\_AD\_Set\_Channel

# @ Description

This function is used to set the AD channel by means of writing data to the channel control register. There are 32 single-ended A/D channels supported by the PCI-9114(A), therefore the channel number can be set between 0 and 31. Under non-auto scan mode, the ADChannelNo stores the channel number setting. Under auto-scan mode, the ADChannelNo records the channel number of the ending channel.

# @ Syntax

```txt
C/C++ (DOS)
U16_9114_AD_Set_Channel (U16 cardNo, U16 ADChannelNo)

C/C++ (Windows 95)
U16 W_9114_AD_Set_Channel (U16 cardNo, U16 ADChannelNo)

Visual Basic (Windows 95)
W_9114_AD_Set_Channel (ByVal cardNo As Integer, ByVal ADChannelNo As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
ADChannelNo: The selected channel number or the ending channel number to perform A/D conversion.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.12 \_9114\_AD\_Set\_Range

# @ Description

This function is used to set the A/D range by means of writing data to the AD range control register. The initial value of the gain is '1' which is the default setting for the PCI-9114(A) hardware. The following tables specify the relationship between the gain and the input voltage range:

For PCI9114HG:

<table><tr><td>Input Range (V)</td><td>Gain</td><td>Gain Code</td></tr><tr><td>±10 V</td><td>X 1</td><td>AD_B_10_V</td></tr><tr><td>±1 V</td><td>X 10</td><td>AD_B_1_V</td></tr><tr><td>±100m V</td><td>X 100</td><td>AD_B_0_1_V</td></tr><tr><td>±10m V</td><td>X 1000</td><td>AD_B_0_01_V</td></tr></table>

For PCI9114DG:

<table><tr><td>Input Range (V)</td><td>Gain</td><td>Gain Code</td></tr><tr><td>±10 V</td><td>X 1</td><td>AD_B_10_V</td></tr><tr><td>±5 V</td><td>X 2</td><td>AD_B_5_V</td></tr><tr><td>±2.5 V</td><td>X 4</td><td>AD_B_2_5_V</td></tr><tr><td>±1.25 V</td><td>X 8</td><td>AD_B_1_25_V</td></tr></table>

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Set_Range (U16 cardNo, U16 ADRange)
C/C++ (Windows 95)
U16 W_9114_AD_Set_Range (U16 cardNo, U16 ADRange)
Visual Basic (Windows 95)
W_9114_AD_Set_Range (ByVal cardNo As Integer, ByVal ADRange
As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized ADRange: The programmable gain of A/D conversion, the possible values are: AD_B_10_V, AD_B_1_V, AD_B_0_1_V, AD_B_0_01_V, AD_B_5_V, AD_B_2_5_V, AD_B_1_25_V,
```

# @ Return Code

```txt
ERR_NoError
```

# 5.13 \_9114\_AD\_Get\_Range

# @ Description

This function is used to obtain the A/D range from the AD range control register. Refer to the previous section for possible ranges.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Get_Range (U16 cardNo, U16 *ADRange)
C/C++ (Windows 95)
U16 W_9114_AD_Get_Range (U16 cardNo, U16 *ADRange)
Visual Basic (Windows 95)
W_9114_AD_Get_Range (ByVal cardNo As Integer, ADRange As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized ADRange: The programmable gain of A/D conversion, the possible values are: AD_B_10_V, AD_B_1_V, AD_B_0_1_V, AD_B_0_01_V, AD_B_5_V, AD_B_2_5_V, AD_B_1_25_V
```

# @ Return Code

```txt
ERR_NoError
```

# 5.14 \_9114\_AD\_Get\_Status

# @ Description

This function is used to obtain the AD FIFO status from the status read back register.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_AD_Get_Status (U16 cardNo, U16 *ADStatus)
```

```txt
C/C++ (Windows 95)
U16 W_9114_AD_Get_Status (U16 cardNo, U16 *ADStatus)
```

Visual Basic (Windows 95)
```txt
W_9114_AD_Get_Status (ByVal cardNo As Integer, ADStatus As Integer) As Integer
```

# @ Argument

```makefile
cardNo: The card number of PCI-9114(A) card initialized
ADStatus: The status of AD FIFO. The AD FIFO status could be one of the following:
ADSTS_FF_EF: FIFO is not empty
ADSTS_FF_HF: FIFO is not half-full
ADSTS_FF_FF: FIFO is not full
ADSTS_BUSY: AD is not busy
```

# @ Return Code

```txt
ERR_NoError
```

# 5.15 \_9114\_AD\_Set\_Mode

# @ Description

This function is used to set the AD trigger mode. Refer to section 5.1.3 for descriptions of the AD trigger modes.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Set_Mode (U16 cardNo, U16 ADMode)
C/C++ (Windows 95)
U16 W_9114_AD_Set_Mode (U16 cardNo, U16 ADMode)
Visual Basic (Windows 95)
W_9114_AD_Set_Mode (ByVal cardNo As Integer, ByVal ADMode As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized
ADMode: The value of AD mode.
The returned value could be one or a combination of the following modes:
A_9114_AD_TimerTrig, A_9114_AD_SoftTrig
A_9114_AD_AutoScan
```

# @ Return Code

```txt
ERR_NoError
```

# 5.16 \_9114\_AD\_Get\_Mode

# @ Description

This function is used to retrieve the AD mode from the AD trigger mode control register. Refer to section 5.1.3 for details of the AD trigger modes.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_AD_Get_Mode (U16 cardNo, U16 *ADMode)
C/C++ (Windows 95)
U16 W_9114_AD_Get_Mode (U16 cardNo, U16 *ADMode)
Visual Basic (Windows 95)
W_9114_AD_Get_Mode (ByVal cardNo As Integer, ADMode As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized
ADMode: The value of AD mode
The returned value could be one or a combination of the following modes:
A_9114_AD_TimerTrig, A_9114_AD_SoftTrig
A_9114_AD_AutoScan
```

# @ Return Code

```txt
ERR_NoError
```

# 5.17 \_9114\_INT\_Set\_Reg

# @ Description

This function is used to select the interrupt sources by writing data to the interrupt control register. Refer to section 4.9 for details of using the interrupt control register.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_INT_Set_Reg (U16 cardNo, U16 INTC)
C/C++ (Windows 95)
U16 W_9114_INT_Set_Reg (U16 cardNo, U16 INTC)
```

# Visual Basic (Windows 95)

```txt
W_9114_INT_Set_Reg (ByVal cardNo As Integer, ByVal INTC As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized
INTC: The value written to the interrupt control register
```

# @ Return Code

```txt
ERR_NoError
```

# 5.18 \_9114\_AD\_Get\_Reg

# @ Description

This function is used to retrieve the AD mode setting and interrupt control setting by reading data from the Interrupt control read back register. The settings returned are stored in INTC. Refer to section 4.7 and section 4.9 for details of each bit of the returned data.

@ Syntax
```txt
C/C++ (DOS)
U16 _9114_INT_Get_Reg (U16 cardNo, U16 *INTC)
C/C++ (Windows 95)
U16 W_9114_INT_Get_Reg (U16 cardNo, U16 *INTC)
Visual Basic (Windows 95)
W_9114_INT_Get_Reg (ByVal cardNo As Integer, INTC As Integer)
As Integer
```

@ Argument
```txt
cardNo: The card number of PCI-9114(A) card initialized.
INTC: The value returned from the interrupt control register.
```

@ Return Code
```txt
ERR_NoError
```

# 5.19 \_9114\_Reset\_FIFO

# @ Description

The PCI-9114(A)'s A/D data are stored in the FIFO buffer after conversion. This function is used to reset the A/D FIFO buffer. This function should be called before performing any A/D conversion to clear any old data stored in the FIFO buffer.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_Reset_FIFO (U16 cardNo)
C/C++ (Windows 95)
U16 W_9114_Reset_FIFO (U16 cardNo)
Visual Basic (Windows 95)
W_9114_Reset_FIFO (ByVal cardNo As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.20 \_9114\_AD\_Soft\_Trigger

# @ Description

This function is used to trigger the A/D conversion using the software. When this function is called, a trigger pulse will be generated and the converted data will be stored in the data register.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_AD_Soft_Trigger (U16 cardNo)
C/C++ (Windows 95)
U16 W_9114_AD_Soft_Trigger (U16 cardNo)
Visual Basic (Windows 95)
W_9114_AD_Soft_Trigger (ByVal cardNo As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.21 \_9114\_Set\_8254

# @ Description

This function is used to write to the PCI-9114(A)'s 8254 Programmable Timer.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_Set_8254 (U16 cardNo, U16 tmr_ch, U8 count)
C/C++ (Windows 95)
U16 W_9114_Set_8254 (U16 cardNo, U16 tmr_ch, U8 count)
Visual Basic (Windows 95)
W_9114_Set_8254 (ByVal cardNo As Integer, ByVal tmr_ch As Integer, ByVal count As Byte) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
tmr_ch: Port of 8254 Timer, the value is within 0 to 2.
count: The counter value.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.22 \_9114\_Get\_8254

# @ Description

This function is used to read the PCI-9114(A)'s 8254 Programmable Timer. The read value is stored to the counter.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_Get_8254 (U16 cardNo, U16 tmr_ch, U8 *count)
```

```txt
C/C++ (Windows 95)
U16 W_9114_Get_8254 (U16 cardNo, U16 tmr_ch, U8 *count)
```

Visual Basic (Windows 95)
```txt
W_9114_Get_8254 (ByVal cardNo As Integer, ByVal tmr_ch As Integer, count As Byte) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
tmr_ch: Port of 8254 Timer, the value is within 0 to 2.
count: value read from 8254 programmable timer, only 8 LSBs are effective
```

# @ Return Code

```txt
ERR_NoError
```

# 5.23 \_9114\_AD\_Timer

# @ Description

This function is used to set timers #1 and #2. These timers are used as frequency dividers for generating constant A/D sampling rates. It is possible to stop the pacer trigger by setting any one of the dividers as 0. Since the AD conversion rate is limited due to the conversion time of the AD converter, the highest sampling rate of the PCI-9114(A) can not be exceeded 100 KHz. Thus the multiplication of the dividers must be larger than 20.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Timer (U16 cardNo, U16 c1, U16 c2)
C/C++ (Windows 95)
U16 W_9114_AD_Timer (U16 cardNo, U16 c1, U16 c2)
Visual Basic (Windows 95)
W_9114_AD_Timer (ByVal cardNo As Integer, ByVal c1 As Integer, ByVal c2 As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
c1: frequency divider of timer #1
c2: frequency divider of timer #2
```

# @ Return Code

```txt
ERR_NoError
```

# 5.24 \_9114\_Counter\_Start

Only supported by the PCI-9114A or PCI-9114 Rev.C2 and later)

# @ Description

Counter #0 of the PCI-9114(A) Timer/Counter chip is freely available for programming. This function is used to program counter #0. This counter can be used as a frequency generator if an internal clock is used. It can also be used as an event counter if an external clock is used. All 8254 modes (six operating modes) are available.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114 Counter Start (U16 cardNo, U16 mode, U16 c0)
C/C++ (Windows 95)
U16 W_9114 Counter Start (U16 cardNo, U16 mode, U16 c0)
Visual Basic (Windows 95)
W_9114 Counter Start (ByVal cardNo As Integer, ByVal mode As Integer, ByVal c0 As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
mode: the 8254 timer mode, the possible values are :
TIMER_MODE0, TIMER_MODE1,
TIMER_MODE2, TIMER_MODE3,
TIMER_MODE4, TIMER_MODE5.
Please refer to Counter/Timer 8254's reference manual for more detailed information of timer mode.
c0: counter value of counter#0
```

# @ Return Code

```txt
ERR_NoError
```

# 5.25 \_9114\_Counter\_Read

Only supported by the PCI-9114A or PCI-9114 Rev.C2 and later

@ Description

This function is used to read the counter value from Counter#0.

@ Syntax

```csv
C/C++ (DOS)
U16 _9114 Counter_Read (U16 cardNo, U16 *c0)
C/C++ (Windows 95)
U16 W_9114 Counter_Read (U16 cardNo, U16 *c0)
Visual Basic (Windows 95)
W_9114 Counter_Read (ByVal cardNo As Integer, c0 As Integer)
As Integer
```

@ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
c0: count value of counter#0
```

@ Return Code

```txt
ERR_NoError
```

# 5.26 \_9114\_Counter\_Stop

Only supported for the PCI-9114A and PCI-9114 Rev.C2 or later

# @ Description

This function is used to stop the timers operation. The timer is set as a “One-shot” mode with counter value '0'. That is, the clock output signal will be set as high after executing this function.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114 Counter_Stop (U16 cardNo, U16 *c0)
C/C++ (Windows 95)
U16 W_9114 Counter_Stop (U16 cardNo, U16 *c0)
Visual Basic (Windows 95)
U16 W_9114 Counter_Stop (ByVal cardNo As Integer, c0 As Integer) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
c0: the current counter value of the Counter#0
```

# @ Return Code

```txt
ERR_NoError
```

# 5.27 \_9114\_INT\_Source\_Control

# @ Description

The PCI-9114(A) has a dual-interrupt system, therefore, two interrupt sources can be generated and be checked by the software. This function is used to select and control the PCI-9114(A) interrupt sources by writing data to interrupt control register. Refer to section 5.1.4 for details of the A/D data transfer modes.

# @ Syntax

```asm
C/C++ (DOS)
void _9114_INT_Source_Control (U16 cardNo, U16 int1Ctrl, U16 int2Ctrl)
```

```c
C/C++ (Windows 95)
void W_9114_INT_Source_Control (U16 cardNo, U16 int1Ctrl, U16 int2Ctrl)
```

```txt
Visual Basic (Windows 95)
W_9114_INT_Source_Control (ByVal cardNo As Integer, ByVal int1Ctrl As Integer, ByVal int2Ctrl As Integer)
```

# @ Argument

```yaml
cardNo: the card number of PCI-9114(A) card initialized.
int1Ctrl: the value to control INT1, the value can be set and the corresponding definition is the following:
0 : INT1 disable
1 : INT1 AD end of conversion (EOC) interrupt
2 : INT1 FIFO half full
int2Ctrl: the value to control INT2, the value can be set and the corresponding definition is the following:
0 : INT2 disable
1 : INT2 timer pacer interrupt
```

# @ Return Code

None

# 5.28 \_9114\_CLR\_IRQ1

# @ Description

This function is used to clear the interrupt request that is requested by PCI-9114\_INT1. If an interrupt is used to transfer any A/D converted data, this function must be used to clear the interrupt request status, otherwise the new incoming interrupt will not be generated.

@ Syntax
```txt
C/C++ (DOS)
void _9114_CLR_IRQ1 (U16 cardNo)
C/C++ (Windows 95)
void W_9114_CLR_IRQ1 (U16 cardNo)
Visual (Windows 95)
W_9114_CLR_IRQ1 (ByVal cardNo As Integer)
```

@ Argument
```txt
None
```

@ Return Code
```txt
None
```

# 5.29 \_9114\_CLR\_IRQ2

# @ Description

This function is used to clear interrupt request that is requested by PCI-9114\_INT2. If an interrupt is used to transfer any A/D converted data, this function must be used to clear the interrupt request status, otherwise the new incoming interrupt will not be generated.

@ Syntax
```txt
C/C++ (DOS)
void _9114_CLR_IRQ2 (U16 cardNo)
C/C++ (Windows 95)
void W_9114_CLR_IRQ2 (U16 cardNo)
Visual (Windows 95)
W_9114_CLR_IRQ2 (ByVal cardNo As Integer)
```

@ Argument
```txt
None
```

@ Return Code
```txt
None
```

# 5.30 \_9114\_Get\_IRQ\_Channel

# @ Description

This function is used to retrieve the IRQ level of the PCI-9114(A) card currently used.

# @ Syntax

```txt
C/C++ (DOS)
void _9114_Get_IRQ_Channel (U16 cardNo, U16 *irq_no)
C/C++ (Windows 95)
void W_9114_Get_IRQ_Channel (U16 cardNo, U16 *irq_no)
Visual Basic (Windows 95)
W_9114_Get_IRQ_Channel (ByVal cardNo As Integer, irq_no As Integer)
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
Irq_no: The IRQ level used to transfer A/D data for this card
```

# @ Return Code

None

# 5.31 \_9114\_Get\_IRQ\_Status

# @ Description

This function is used to retrieve the status of the two IRQs (INT1 and INT2) in the PCI-9114(A) card.

# @ Syntax

```c
C/C++ (DOS)
void _9114_Get_IRQ_Status (U16 cardNo, U16 *ch1, U16 *ch2)
C/C++ (Windows 95)
void W_9114_Get_IRQ_Status (U16 cardNo, U16 *ch1, U16 *ch2)
Visual Basic (Windows 95)
W_9114_Get_IRQ_Status (ByVal cardNo As Integer, ch1 As Integer, ch2 As Integer)
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
ch1: the IRQ status of INT1
ch2: the IRQ status of INT2
```

# @ Return Code

None

# 5.32 \_9114\_AD\_FFHF\_Polling

# @ Description

This function is used to perform an AD data transfer by applying the half-full polling mode. This method checks the FIFO half-full signal each time this function is called. Refer to section 5.1.4 for details of the half-full polling mode.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_AD_FFHF_Polling (U16 cardNo, I16 far *ad_buf)
C/C++ (Windows 95)
U16 W_9114_AD_FFHF_Polling (U16 cardNo, I16 *ad_buf)
```

# Visual Basic (Windows 95)

```txt
W_9114_AD_FFHF_Polling (ByVal cardNo As Integer, ad_buf As Integer) As Integer
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
ad_buf: the buffer stores the A/D converted value. The size of ad_buf can not be smaller than 512 words. The data format can be referred to section 5.1.5 for the details.
```

# @ Return Code

```txt
ERR_NoError
ERR_FIFO_Half_NotReady
```

# 5.33 \_9114\_AD\_FFHF\_Polling\_MUX

# @ Description

This function is used to perform an AD data transfer by applying the half-full polling mode. This method checks the FIFO half full signal each time this function is called. If the FIFO is not half-full, the software will not read the data. The difference between this function and 9114\_AD\_FFHF\_Polling is that the former reads data from a 16-bit register and this function reads data from a 32-bit data register. Refer to section 5.1.4 for the details of half-full polling mode.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_AD_FFFH_Polling_MUX (U16 cardNo, U32 far *ad_buf)
C/C++ (Windows 95)
U16 W_9114_AD_FFFH_Polling_MUX (U16 cardNo, U32 *ad_buf)
Visual Basic (Windows 95)
U16 W_9114_AD_FFFH_Polling_MUX (ByVal cardNo As Integer, ad_buf As Long) As Integer
```

# @ Argument

```txt
cardNo: The card number of PCI-9114(A) card initialized.
ad_buf: The 32bits A/D converted value. The data format can be referred to section 5.1.5 for details.
```

# @ Return Code

```txt
ERR_NoError
ERR_FIFO_Half_NotReady
```

# 5.34 \_9114\_AD\_Aquire

# @ Description

This function is used to poll the A/D converted data using a software trigger. It reads the A/D data when the data is ready.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_Aquire (U16 cardNo, I16 far *ad_data)
C/C++ (Windows 95)
U16 W_9114_AD_Aquire (U16 cardNo, I16 *ad_data)
Visual Basic (Windows 95)
W_9114_AD_Aquire (ByVal cardNo As Integer, ad_data As Integer) As Integer
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
ad_data: the 16bits A/D converted value. The bit 0 of ADData is the LSB of A/D converted data and the bit 15 of ADData is the MSB of A/D converted data. Please refer to section 5.1.5 for the relationship between the voltage and the value.
```

# @ Return Code

```txt
ERR_NoError
ERR_AD_AquireTimeOut
```

# 5.35 \_9114\_AD\_Aquire\_MUX

# @ Description

This function is used to poll the A/D converted data. It reads the A/D data when the data is ready.

# @ Syntax

```csv
C/C++ (DOS)
U16 _9114_AD_Aquire_MUX ( U16 cardNo, U32 far *ad_data )
C/C++ (Windows 95)
U16 W_9114_AD_Aquire_MUX ( U16 cardNo, U32 far *ad_data )
Visual Basic (Windows 95)
W_9114_AD_Aquire_MUX (ByVal cardNo As Integer, ad_data As Long) As Integer
```

# @ Argument

```yaml
cardNo: the card number of PCI-9114(A) card initialized.
ad_data: the 32bits A/D converted value. The resolution of A/D conversion data is 16-bit. The unsigned integer data format of ADData is as follows:
bit 0...15: A/D converted data
bit 16...20: converted channel no.
```

# @ Return Code

```txt
ERR_NoError
ERR_FIFO_Half_NotReady
```

# 5.36 \_9114\_AD\_INT\_Start

# @ Description

This function is used to initiate and start up the AD EOC (end-of-conversion) interrupt. This function can perform an A/D conversion N times using interrupt data transfer and pacer trigger. It takes place in the background and will not stop until the N-th conversion has been completed or your program executes the \_9114\_AD\_INT\_Stop() function to stop the process.

After executing this function, it is necessary to check the status of the operation by using the function \_9114\_AD\_INT\_Status(). This function can perform on a single A/D channel (autoscan is disabled) or multiple A/D channels (autoscan is enabled) with a fixed analog input range.

Note: The interrupt mode provided in this function is from an internal timer source; therefore you must specify c1 & c2 as calling this function. In addition, this function in the DOS library supports just one PCI-9114(A) card and provides only one ISR (interrupt service routine) for processing the interrupt events.

@ Syntax
```csv
C/C++ (DOS)
U16_9114_AD_INT_Start (U16 cardNo, U16 auto_scan, U16 ad_ch_no, U16 ad_gain, U16 count, U32 *ad_buffer, U16 c1, U16 c2)

C/C++ (Windows 95)
U16 W_9114_AD_INT_Start (U16 cardNo, U16 auto_scan, U16 ad_ch_no, U16 ad_gain, U16 count, U32 *ad_buffer, U16 c1, U16 c2)

Visual Basic (Windows 95)
W_9114_AD_INT_Start (ByVal cardNo As Integer, ByVal auto_scan As Integer, ByVal ad_ch_no As Integer, ByVal ad_gain As Integer, ByVal count As Integer, ad_buffer As Long, ByVal c1 As Integer, ByVal c2 As Integer) As Integer
```

@ Argument
```txt
cardNo: the card number of PCI-9114(A) card initialized.
auto_scan:0: autoscan is disabled.
    1: autoscan is enabled.
ad_ch_no: A/D channel number.
    If the auto_scan is set as enabled, the selection sequence of A/D channel is: 0, 1, 2, 3, ..., [ad_ch_no], 0, 1, 2, 3, [ad_ch_no], ...
    If the auto_scan is set as disabled, only the data input from [ad_ch_no] is converted.
ad_gain: A/D analog input range, the possible values are:
    AD_B_10_V, AD_B_1_V, AD_B_0_1_V, AD_B_0_01_V,
    AD_B_5_V, AD_B_2_5_V, AD_B_1_25_V
count: the number of A/D conversion
ad_buffer: the start address of the memory buffer to store
```

```txt
the AD data. The buffer size must large than the number of AD conversion. The unsigned integer data format in ad_buffer is as follows:
bit 0...15: A/D converted data
bit 16...20: converted channel no.
c1: the frequency divider of Timer#1.
c2: the frequency divider of Timer#2.
```

# @ Return Code

```txt
ERR_InvalidADChannel
ERR_AD_InvalidGain
ERR_InvalidTimerValue
ERR_NoError
```

# 5.37 \_9114\_AD\_FFHF\_INT\_Start

# @ Description

This function is used to initiate and start up the AD EOC (end-of-conversion) interrupt by using AD FIFO Half-Full Interrupt Transfer Mode. This function can perform an A/D conversion N times using interrupt data transfer and pacer trigger. It takes place in the background and will not stop until the N-th conversion has been completed or the program executes the \_9114\_AD\_INT\_Stop() function to stop the process.

After executing this function, it is necessary to check the status of the operation using the function \_9114\_AD\_FFHF\_INT\_Status(). The function can be performed on a single A/D channel (autoscan is disabled) or multiple A/D channels (autoscan is enabled) with fixed analog input range.

Note: The interrupt mode provided in this function is from an internal timer source; therefore you must specify c1 & c2 as calling this function. In addition, this function in the DOS library supports just one PCI-9114(A) card and provides only one ISR (interrupt service routine) for processing the interrupt events.

# @ Syntax

C/C++ (DOS)

U16\_9114\_AD\_FFHF\_INT\_Start (U16 cardNo, U16 auto\_scan, U16 ad\_ch\_no, U16 ad\_gain, U16 blockNo, U32 \*ad\_buffer, U16 c1, U16 c2)

C/C++ (Windows 95)

U16 W\_9114\_AD\_FFHF\_INT\_Start (U16 cardNo, U16 auto\_scan, U16 ad\_ch\_no, U16 ad\_gain, U16 blockNo, U32 \*ad\_buffer, U16 c1, U16 c2)

Visual Basic (Windows 95)

W\_9114\_AD\_FFHF\_INT\_Start (ByVal cardNo As Integer, ByVal auto\_scan As Integer, ByVal ad\_ch\_no As Integer, ByVal ad\_gain As Integer, ByVal blockNo As Integer, ad\_buffer As Long, ByVal c1 As Integer, ByVal c2 As Integer) As Integer

# @ Argument

cardNo: the card number of PCI-9114(A) card initialized.

auto\_scan:0: autoscan is disabled.
1: autoscan is enabled.

ad ch no: A/D channel number.

If the auto\_scan is set as enable, the selection sequence of A/D channel is: 0, 1, 2, 3, ..., [ad\_ch\_no], 0, 1, 2, 3, [ad\_ch\_no], ...
If the auto\_scan is set as disable, only the data input from [ad\_ch\_no] is converted.

ad\_gain: A/D analog input range, the possible values are:
AD\_B\_10\_V, AD\_B\_1\_V, AD\_B\_0\_1\_V, AD\_B\_0\_01\_V,
AD\_B\_5\_V, AD\_B\_2\_5\_V, AD\_B\_1\_25\_V.

blockNo: the number of blocks for performing A/D conversion, one block of A/D conversion is 512 words.

ad\_buffer: the start address of the memory buffer to store the AD data. The buffer size must large than the number of AD conversion. The unsigned integer data format in ad\_buffer is as follows:

bit 0...15: A/D converted data
bit 16...20: converted channel no.

c1: the frequency divider of Timer#1.
c2: the frequency divider of Timer#2.

# @ Return Code

```txt
ERR_InvalidADChannel
ERR_AD_InvalidGain
ERR_InvalidTimerValue
ERR_NoError
```

# 5.38 \_9114\_AD\_INT\_Status

# @ Description

This function is used to check the status of the interrupt operation. The \_9114\_AD\_INT\_Start() function is executed in the background.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_AD_INT_Status (U16 cardNo, U16 *status, U16 *count)
C/C++ (Windows 95)
U16 W_9114_AD_INT_Status (U16 cardNo, U16 *status, U16 *count)
```

# Visual Basic (Windows 95)

```txt
W_9114_AD_INT_Status (ByVal cardNo As Integer, status As Integer, count As Integer) As Integer
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
status: the status of the INT data transfer, the possible values are:
AD_INT_RUN, AD_INT_STOP
count: the A/D conversion count number performed currently
```

# @ Return Code

```txt
ERR_NoError
```

# 5.39 \_9114\_AD\_FFHF\_INT\_Status

# @ Description

This function is used to check the status of the interrupt operation. The \_9114\_AD\_FFHF\_INT\_Start() is executed in the background.

# @ Syntax

```c
C/C++ (DOS)
U16_9114_AD_FFHF_INT_Status (U16 cardNo, U16 *status, U16 *blockNo)

C/C++ (Windows 95)
U16 W_9114_AD_FFHF_INT_Status (U16 cardNo, U16 *status, U16 *blockNo)

Visual Basic (Windows 95)
W_9114_AD_FFHF_INT_Status (ByVal cardNo As Integer, status As Integer, blockNo As Integer) As Integer
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
status: the status of the INT data transfer, the possible values are:
AD_FFHF_INT_RUN, AD_FFHF_BLOCK_FULL
blockNo: the A/D conversion block number performed currently.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.40 \_9114\_AD\_FFHF\_INT\_Restart

# @ Description

After calling the \_9114\_AD\_FFHF\_INT\_Start() function, the AD conversion and transfer will not stop until the Nth block of the AD data is acquired, calling this function can restart the FIFO half full interrupt transfer without re-initiating all its relative registers. However, if the interrupt operation was stopped by calling the \_9114\_AD\_FFHF\_INT\_Stop() function, the program should use \_9114\_AD\_FFHF\_INT\_Start() to restart the interrupt transfer function.

# @ Syntax

```c
C/C++ (DOS)
U16 _9114_AD_FFHF_INT_Restart (U16 cardNo)
C/C++ (Windows 95)
U16 W_9114_AD_FFHF_INT_Restart (U16 cardNo)
Visual Basic (Windows 95)
W_9114_AD_FFHF_INT_Restart (ByVal cardNo As Integer) As Integer
```

# @ Argument

```txt
cardNo: the card number of PCI-9114(A) card initialized.
```

# @ Return Code

```txt
ERR_NoError
```

# 5.41 \_9114\_AD\_INT\_Stop

# @ Description

This function is used to stop the interrupt data transfer function. After executing this function, the internal AD trigger is disabled and the AD timer is stopped. This function returns the number of data that has been transferred.

# @ Syntax

```txt
C/C++ (DOS)
U16 _9114_AD_INT_Stop (U16 cardNo, U16 *count)
C/C++ (Windows 95)
U16 W_9114_AD_INT_Stop (U16 cardNo, U16 *count)
Visual Basic (Windows 95)
W_9114_AD_INT_Stop (ByVal cardNo As Integer, count As Integer) As Integer
```

# @ Argument

```txt
CardNo: the card number of PCI-9114(A) card initialized.
count: the number of A/D data which has been transferred.
```

# @ Return Code

```c
ERR_AD_INTNotSet
ERR_NoError
```

# Calibration & Utilities

In data acquisition processes, how to calibrate your measurement devices to maintain its accuracy is very important. Users can calibrate the analog input and output channels under the users' operating environment to maximize its accuracy. This chapter will guide you though how to calibrate the PCI-9114(A).

The software CD provides two utility programs, the 9114util.exe and I-eeprom. The 9114util.exe utility provides three basic functions for System Configuration, Calibration, and Functional Testing, while the I\_eeprom utility is used to enable or disable the interrupts of the PCI-9114(A) board. The utility programs are described in the following sections.

# 6.1 Calibration

# 6.1.1 What do you need?

Before calibrating your PCI-9114 card, you need to prepare the following equipment's and materials for the calibration process:

- Calibration program: Once the program is executed, it will guide you to do the calibration. This program is included in the delivered package.
• A 5 1/2-digit multi-meter (a 6 1/2 is recommended)
- An adjustable voltage calibrator or a very stable and noise free DC voltage generator

# 6.1.2 VR Assignment

There are five variable resistors (VR) on the PCI-9114(A) board that allow you to make adjustments on the A/D channels. The function of each VR is specified in Table 3.

<table><tr><td>VR1</td><td>A/D offset adjustment</td></tr><tr><td>VR2</td><td>A/D full scale adjustment</td></tr><tr><td>VR3</td><td>Programmable Gain Amplifier input offset adjustment</td></tr><tr><td>VR4</td><td>Cold junction sensor offset adjustment</td></tr><tr><td>VR5</td><td>Programmable Gain Amplifier output offset adjustment(Only available in PCI-9114A and PCI-9114 Rev. C2 or later)</td></tr></table>

Table 3: Function of the VRs

# 6.1.3 A/D Adjustment

# Analog input offset calibration (For PCI-9114 Rev. B2 Only)

1. Set AD input signal type to single-ended (default) input.
2. Short AD Channel 0 (CN1 pin 19) to ground (CN1 pin 11 or 29).
3. Trim VR1 (post-gain offset) until the reading approaches to zero.
4. Trim VR3 (pre-gain offset) until the reading approaches to zero.
5. Repeat steps 3 and 4 until both post-gain offset and pre-gain offset are steady at zero.
6. Connect +5V to AD channel 1 (pin 18).
7. Adjust VR2 to obtain a reading between 16383\~16384.

# PGA offset calibration (For PCI-9114A and PCI-9114 Rev. C2 or later)

1. Set AD input signal type to single-ended (default) input.
2. Adjust JP2 to set AD channel #16 to ground (D.I. mode, Refer to section 2.7.2.) and program the card to use AD ch#16.
3. Use the multi-meter to measure the voltage between TP1 and TP2.
4. Set the gain register to maximum gain (gain = 8 for PCI-9114(A) DG; gain = 1000 for PCI-9114(A) HG).
5. Adjust VR3 until the multi-meter value approaches to zero.
6. Set gain register to minimum gain (gain = 1).
7. Adjust VR5 until the multi-meter value approaches to zero.

8. Repeat steps 4\~7 until the multi-meter value reads zero even after a gain changed.

# A/D offset calibration (For PCI-9114A and PCI-9114 Rev. C2 or later)

1. Set the AD input signal type to single-ended (default) input.
2. Adjust JP2 to set AD channel #16 to ground (D.I. mode, Refer to section 2.7.2.) and program the card to use AD ch#16.
3. Set gain register to minimum gain (gain = 1).
4. Adjust VR1 to obtain reading between -1\~+1.

# A/D full range calibration

1. Set the AD input signal type to single-ended (default) input.
2. Use the multi-meter to calibrate the reference voltage of an external power supply unit to +10V.
3. Connect the reference voltage to AD channel #0, and program the card to use AD ch#0.
4. Set gain register to minimum gain (gain = 1).
5. Adjust VR2 to obtain a reading between 32766\~32767.

# Cold junction sensor calibration

1. Set the C.J. sensor for operation under S.E. input mode. (Refer to section 2.7.2), and program the card to use AD ch#0.
2. Set gain register to minimum gain (gain = 1).
3. Measure the current temperature.
4. Adjust VR4 until the read-out value equals the temperature value.
5. The relationship between temperature and the read-out value is as followed:

$$
V (m V) = T (^ {\circ} K) \times 1 0 (m V / ^ {\circ} K)
$$

$$
T \left(^ {\circ} K\right) = V (m V) / 1 0 (m V / ^ {\circ} K)
$$

$$
T \left(^ {\circ} C\right) = T \left(^ {\circ} K\right) - 2 7 3 \left(^ {\circ} K\right)
$$

For example:

If the temperature is $25^{\circ}$ C, user should calibrate the C.J. voltage to $(25+273)\times10=2980\ mV=2.98\ V$

# 6.1.4 Software A/D Offset Calibration

For more accurate calibration of the input offset signal, using a software utility to calibrate the offset of the analog input signal is a good approach. Benefits in using this method are that it is online and it eliminates any temperature drift.

For example, user's can adjust JP2 to set AD channel #16 to ground (D.I. mode, Refer to section 2.7.2.). Measuring the digital value of channel #16 can retrieve the offset voltage of the AD channel. If the digital offset value is $V_{\text{off}}$ , user can modify any AD data by subtracting $V_{\text{off}}$ from the AD data to obtain the offset calibrated value. Note that the $V_{\text{off}}$ may be different for each gain level. Users should calibrate the offset value for each gain value.

# 6.2 Utility

# 6.2.1 9114util (For PCI-9114 Rev. B2 Only)

There are 3 functions provided by the 9114util.exe. It is used for system configuration, calibration, and functional testing. This software utility is designed with a menu-driven based Windows environment. It provides text messages and graphical indicators for operating guidance.

# Running 9114util.exe

After finishing the DOS installation, you can execute the utility by typing in the following commands:

C> cd \ADLINK\9114\DOS\Util

C> 9114UTIL

The following displayed will appear on your screen. The message at the bottom of each window guides you through the selected item; follow the on screen instructions to change/set a value.

\*\*\*\*\* PCI-9114 Utility Rev. 2.1 \*\*\*\*\*

Copyright © 2000-2004, ADLINK Technology Inc. All rights reserved.

```txt
&lt;F1&gt; : Configuration.
&lt;F2&gt; : Calibration.
&lt;F3&gt; : Function testing.
&lt;Esc&gt;: Quit.
```

>>> Select function key F1, F2, F3, or press &lt;Esc&gt; to quit. &lt;&lt;&lt;

# System Configuration

This function guides you through configuration of the PCI-9114 card to set the correct hardware parameters. The configuration window shows the setting items that you have to set before using the PCI-9114 card.

The following diagram will be displayed on the screen as you choose the Configuration function from main menu.

\*\*\*\*\* Configuration of PCI-9114 \*\*\*\*\*

```txt
&lt;1&gt; Card Type PCI9114HG
&lt;2&gt; AD Polarity setting Bipolar
&lt;3&gt; AD Input Range Gain=1 Bipolar(-10V~10V)
```

>>> &lt;Up/Down&gt;: Select Item, &lt;PgUp/PgDn&gt;: Change Setting &lt;&lt;&lt;

# Calibration

This function is used to guide you through on how to calibrate the PCI-9114. The calibration program serves as a useful test for the PCI-9114's A/D and D/A functions and can aid in troubleshooting if problems arise.

Note: For an environment with frequently large changes in temperature and vibration, a 3 months re-calibration interval is recommended. For laboratory conditions, 6 months to 1 year is acceptable.

When you choose the calibration function from the main menu list, a calibration sub-menu is displayed on the screen. After you select one of the calibration items from the calibration sub-menu, a calibration window appears. The upper window outlines procedures to be followed when calibrating the board. The instructions guide you through the calibration process step by step.

```txt
***** PCI-9114 Calibration *****
```

```txt
&lt;1&gt; PGA Offset adjustment
&lt;2&gt; A/D Bipolar adjustment
&lt;3&gt; Cold junction sensor calibration
&lt;Esc&gt; Quit
```

Select 1 to 3 or &lt;Esc&gt; to quit calibration.

# Functional Testing

This function is used to test the functions of the PCI-9114. It includes the Digital I/O testing, D/A testing, A/D polling testing, A/D Interrupt Testing, and A/D FIFO Half-Full Interrupt testing.

When you choose one of the testing functions from the function menu, the screen below is displayed.

```txt
***** PCI-9114 Function Testing *****
```

```txt
&lt;1&gt; : A/D with Polling Test
&lt;2&gt; : A/D with Interrupt Test
&lt;3&gt; : A/D with FIFO Half-Full Interrupt
&lt;4&gt; : DI/DO Test
&lt;Esc&gt;: Quit
```

Select 1 to 4 or (Esc) to quit function testing

# 6.2.2 9114AUtl

# (For PCI-9114A or PCI-9114 Rev. C2 and later)

There are three basic functions provided by the 9114Autl utility. They are System Configuration, Calibration, and Functional Testing. This software utility is designed as a menu-driven based windows environment. It provides text messages and graphical indicators for operating guidance.

# Running 9114util.exe

After finishing the DOS installation, you can execute the utility by typing in the following command.

```txt
C> cd \ADLINK\9114\DOS\Util
C> 9114AUTL
```

The following displayed will appear on your screen. The message at the bottom of each window guides you through the selected item; follow the on screen instructions to change/set a value.

```txt
****** PCI-9114(A) Utility Rev. 2.0 *****
Copyright © 2001-2003, ADLink Technology Inc. All rights reserved.
```

```txt
&lt;F1&gt; : Configuration.
&lt;F2&gt; : Calibration.
&lt;F3&gt; : Function testing.
&lt;Esc&gt;: Quit.
```

>>> Select function key F1, F2, F3, or press &lt;Esc&gt; to quit. &lt;&lt;&lt;

# System Configuration

This function guides you through configuration of the PCI-9114(A) card to set the correct hardware parameters. The configuration window shows the setting items that you have to set before using the PCI-9114(A) card.

The following diagram will be displayed on the screen as you choose the Configuration function from main menu

```txt
***** Configuration of PCI-9114 (A) *****
```

```txt
&lt;1&gt; Card Type PCI9114(A) HG
&lt;2&gt; AD Polarity setting Bipolar
&lt;3&gt; AD Input Range Gain=1 Bipolar(-10V~10V)
```

```txt
>>> &lt;Up/Down&gt;: Select Item, &lt;PgUp/PgDn&gt;: Change Setting &lt;&lt;&lt;
```

# Calibration

This function is used to guide you through on how to calibrate the PCI-9114(A). The calibration program serves as a useful test for the PCI-9114(A)'s A/D and D/A functions and can aid in troubleshooting if problems arise.

Note: For an environment with frequently large changes in temperature and vibration, a 3 months re-calibration interval is recommended. For laboratory conditions, 6 months to 1 year is acceptable.

When you choose the calibration function from the main menu list, a calibration sub-menu is displayed on the screen. After you select one of the calibration items from the calibration sub-menu, a calibration window appears. The upper window outlines procedures to be followed when calibrating the board. The instructions guide you through the calibration process step by step.

```txt
***** PCI-9114(A) Calibration *****
```

```txt
&lt;1&gt; PGA Offset adjustment
&lt;2&gt; A/D Bipolar adjustment
&lt;3&gt; Cold junction sensor calibration
&lt;Esc&gt; Quit
```

Select 1 to 3 or &lt;Esc&gt; to quit calibration.

# Functional Testing

This function is used to test the functions of the PCI-9114(A). It includes the Digital I/O testing, D/A testing, A/D polling testing, A/D Interrupt Testing, and A/D FIFO Half-Full Interrupt testing.

When you choose one of the testing functions from the function menu, the screen below is displayed.

```txt
***** PCI-9114 (A) Function Testing *****
```

```txt
&lt;1&gt; : A/D with Polling Test
&lt;2&gt; : A/D with Interrupt Test
&lt;3&gt; : A/D with FIFO Half-Full Interrupt
&lt;4&gt; : DI/DO Test
&lt;Esc&gt;: Quit
```

Select 1 to 4 or (Esc) to quit function testing

# 6.2.3 I\_EEPROM

This file is used to enable or disable the interrupts of the PCI-9114(A) board. This software is a text-driven program. By default, the interrupts on the PCI-9114(A) board is “on”; users wishing not to use the interrupt function can use this utility to turn off the interrupts of the PCI-9114(A) board.

After finishing the DOS installation, you can execute the utility by typing in the following command:

C> cd \ADLINK\DOS\9111\UTIL

C> I\_EEPROM

The program will prompt for an input of the card type – enter 9114(A). After specifying the card type, the program displays a set of instructions to guide you through to enable or disable the interrupts of the PCI-9114(A) board.

# Appendix A. 8254

# Programmable Interval Timer

# A.1 The 8254 Timer / Counter Chip

The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words. The most common uses for the 8254 in microprocessor-based systems are:

- Event counter
• Binary rate multiplier
• Real-time clock
- Digital one-shot
- Motor control

• Programmable baud rate generator

# A.2 The Control Byte

The 8254 occupy 4 I/O address locations in the PCI-9114(A) I/O map. As shown in the following table:

<table><tr><td>Base + 20</td><td>LSB OR MSB OF COUNTER 0</td></tr><tr><td>Base + 22</td><td>LSB OR MSB OF COUNTER 1</td></tr><tr><td>Base + 24</td><td>LSB OR MSB OF COUNTER 2</td></tr><tr><td>Base + 26</td><td>CONTROL BYTE</td></tr></table>

Before loading or reading any of these individual counters, the control byte (Base +26) must be loaded first. The format of the control byte is:

Control Byte:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td></td><td>SC1</td><td>SC0</td><td>RL1</td><td>RL0</td><td>M2</td><td>M1</td><td>M0</td><td>BCD</td></tr></table>

• SC1 & SC1 - Select Counter (Bit7 & Bit 6)

<table><tr><td>SC1</td><td>SC0</td><td>COUNTER</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>2</td></tr><tr><td>1</td><td>1</td><td>ILLEGAL</td></tr></table>

\- RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4)

<table><tr><td>RL1</td><td>RL0</td><td>OPERATION</td></tr><tr><td>0</td><td>0</td><td>COUNTER LATCH</td></tr><tr><td>0</td><td>1</td><td>READ/LOAD LSB</td></tr><tr><td>1</td><td>0</td><td>READ/LOAD MSB</td></tr><tr><td>1</td><td>1</td><td>READ/LOAD LSB FIRST, THEN MSB</td></tr></table>

• M2, M1 & M0 - Select Operating Mode (Bit 3, Bit 2, & Bit 1)

<table><tr><td>M2</td><td>M1</td><td>M0</td><td>MODE</td></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>0</td><td>1</td><td>1</td></tr><tr><td>x</td><td>1</td><td>0</td><td>2</td></tr><tr><td>x</td><td>1</td><td>1</td><td>3</td></tr><tr><td>1</td><td>0</td><td>0</td><td>4</td></tr><tr><td>1</td><td>0</td><td>1</td><td>5</td></tr></table>

• BCD - Select Binary/BCD Counting (Bit 0)

<table><tr><td>0</td><td>16-BITS BINARY COUNTER</td></tr><tr><td>1</td><td>BINARY CODED DECIMAL (BCD) COUNTER (4 DIGITAL)</td></tr><tr><td>Note</td><td>The count of the binary counter is from 0 up to 65,535 and the count of the BCD counter is from 0 up to 9,999</td></tr></table>

# Mode Definitions

The 8254 support six operating modes that can be selected from. They are:

Mode 0: Interrupt on Terminal Count

Mode 1: Programmable One-Shot.

Mode 2: Rate Generator.

Mode 3: Square Wave Rate Generator.

Mode 4: Software Triggered Strobe.

Mode 5: Hardware Triggered Strobe.

Details of these modes can be found in Intel's data sheet available at the following website:

(http://support.intel.com/support/controllers/peripheral/231164.htm).

# Appendix B. Signal Wiring Diagrams

Analog Input
![This block diagram illustrates an analog input signal conditioning circuit leading to an Analog-to-Digital Converter (ADC).\n\n**Labeled Blocks and Elements:**\n*   **Input Stage:**\n    *   **Single-Ended Input**: Labeled at the top left.\n    *   **Differential Input**: Labeled below a dotted circle containing a '+' sign.\n    *   **AI0~15**: Label for the top input node.\n    *   **AI16~31**: Label for the middle input node.\n    *   **A.G.N.D**: Label for the ground node at the bottom.\n    *   **A**: A triangle pointing downwards below the A.G.N.D node.\n*   **Processing Stage:**\n    *   **Multiplexer**: Appears twice (top and bottom).\n    *   **S.E or D.I (By JP1)**: Label near a switch mechanism.\n    *   **ADC**: A rectangular block on the far right.\n*   **Amplifier**: A triangular op-amp symbol with '+' and '-' terminals.\n\n**Connections:**\n1.  **Inputs**: An input source (circle with '+') connects to the **Single-Ended Input** path leading to the **AI0~15** node. A dotted line indicates a **Differential Input** connection leading to the **AI16~31** node. The bottom wire is labeled **A.G.N.D**.\n2.  **Multiplexers**:\n    *   The top **Multiplexer** receives input from **AI0~15**. Its output connects to the **'** (positive) terminal of the amplifier.\n    *   The bottom **Multiplexer** receives input from **AI16~31**. Its output connects to one side of a switch.\n3.  **Switch & Amplifier**:\n    *   A switch labeled **S.E or D.I (By JP1)** toggles between the output of the bottom **Multiplexer** and the **A.G.N.D** line.\n    *   The common output of this switch connects to the **'** (negative) terminal of the amplifier.\n4.  **Output**: The output of the amplifier connects directly to the **ADC** block.](.pci-9114series-manual-4/e4190c2d083797c03ea85e4d611346d8fea0812daf4ba4d13c2ce032a02e5d65.jpg)

(Channel 0 for CJC)
![**Labeled Blocks:**\n*   **\$A1_0\$**\n*   **\$A1_6\$**\n*   **JP2** (with pins labeled 1, 2, 3, 4, 5, 6)\n*   **CJC**\n*   **A** (Inverter symbol)\n*   **Multiplexer** (Top)\n*   **Multiplexer** (Bottom)\n\n**Connections:**\n*   **\$A1_0\$** connects to **JP2** pins **1**, **3**, and **2**. It also connects to the top input of the top **Multiplexer**.\n*   **\$A1_6\$** connects to **JP2** pins **5** and **4**. It also connects to **CJC**.\n*   **JP2** pin **2** connects to the bottom input of the top **Multiplexer**.\n*   **JP2** pin **4** connects to the bottom input of the bottom **Multiplexer**.\n*   **JP2** pin **6** connects to the top input of the bottom **Multiplexer** and the input of inverter **A**.\n*   The output of inverter **A** connects to **JP2** pin **5**.](.pci-9114series-manual-4/f7a6daefd0ba0a98d0935472ec4235e67527f5dc933f016078d04e17e2e13689.jpg)

Digital Input
![DC (Up to 24V)\nIDI_n\n2.4KΩ\nEIGND\nPC 3H4\nVCC\n4.7KΩ\nTL\nDC (Up to 24V)\nIDI_n\n2.4KΩ\nEIGND\nPC 3H4\nVCC\n4.7KΩ\nTL](.pci-9114series-manual-4/49d2ea66db40875e6a84946c32a1fde8bb2325c8fea039f33587481588166d4d.jpg)

Digital Output
![The image displays two electronic circuit diagrams, arranged vertically. Both diagrams depict a driver circuit connected to a load and a DC power source.\n\n**Top Circuit:**\n*   **Left Side:** A DC voltage source labeled 'DC (5-35V)' is connected in parallel with a box labeled 'Resistive Load'.\n    *   The top wire connects the positive terminal to the top of the load and continues to a node labeled **V_power**.\n    *   The bottom wire connects the negative terminal to the bottom of the load and continues to a node labeled **IDO_n**.\n*   **Center:** A dotted box labeled **'Darlington Source Driver'** contains a composite transistor configuration (a Sziklai pair).\n    *   The top component is a PNP transistor with its collector connected to **V_power**.\n    *   The bottom component is an NPN transistor.\n    *   The base of the PNP transistor is connected to the collector of the NPN transistor.\n    *   The base of the NPN transistor is connected to the node **IDO_n**.\n    *   The emitter of the NPN transistor is connected to a node labeled **EOG_n**.\n    *   A diode is connected across the collector-emitter path of the NPN transistor (from the PNP emitter/NPN collector junction to the **EOG_n** node).\n*   **Right Side:** A box labeled **'PC 3H7'** (an optocoupler) is connected.\n    *   The LED side is connected to a node labeled **V5V** and an inverter buffer.\n    *   The phototransistor side (with a parallel diode) connects to the junction of the PNP base and NPN collector.\n\n**Bottom Circuit:**\n*   **Left Side:** A DC voltage source labeled 'DC (5-35V)' is connected to a box labeled **'Inductance Load'**.\n    *   The top wire connects the positive terminal to the top of the load and continues to the node **V_power**.\n    *   The bottom wire connects the negative terminal to the bottom of the load. From this connection point, a wire goes to a node labeled **EOG_n**, and another wire goes up to a node labeled **IDO_n**. (Visually, **IDO_n**, **EOG_n**, and the bottom of the load appear to be connected).\n*   **Center:** The same **'Darlington Source Driver'** configuration is shown.\n    *   The PNP collector connects to **V_power**.\n    *   The NPN base connects to **IDO_n**.\n    *   The NPN emitter connects to **EOG_n**.\n*   **Right Side:** The **'PC 3H7'** optocoupler and inverter setup is identical to the top diagram, driving the base of the PNP transistor.](.pci-9114series-manual-4/7633229701a93cbd098dab6ada306510539219c3b34efa39da2f57e0be8b35cc.jpg)

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/.
2. All ADLINK products come with a limited two-year warranty, one year for products bought in China.

- The warranty period starts on the day the product is shipped from ADLINK's factory.
- Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
- For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for any loss of data.
- Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.
- For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's guarantee in the following situations:

- Damage caused by not following instructions in the User's Manual.
- Damage caused by carelessness on the user's part during product transportation.
- Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
- Damage caused by inappropriate storage environments such as with high temperatures, high humidity, or volatile chemicals.
- Damage caused by leakage of battery fluid during or after change of batteries by customer/user.

- Damage from improper repair by unauthorized ADLINK technicians.
- Products with altered and/or damaged serial numbers are not entitled to our service.
• This warranty is not transferable or extendible.
• Other categories not protected under our warranty.

4. Customers are responsible for all fees necessary to transport damaged products to ADLINK.

For further questions, please e-mail our FAE staff: service@adlinktech.com
[🔗 Link to the original document](.pci-9114series-manual-4/pci-9114series-manual-4.pdf)