# NuDAQ® PCI-9221

16-bit High-Resolution and

Multi-function DAQ Card

User's Manual

Manual Rev. 2.00

Revision Date: February 15, 2007

Part No: 50-11145-1000

![The image displays a black circle containing the white universal recycling symbol, known as the Mobius loop. It consists of three chasing arrows arranged in a triangular formation. The arrows feature horizontal stripes on their inner sections to create a sense of depth.](.pci-9221-manual-5/40a1b8c7804380ca6082f6ac556461a143014a94ba7fddcde7fa7e40d9571932.jpg)
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Copyright 2007 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Trademarks

NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK TECHNOLOGY INC.

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting service

Customer satisfaction is our top priority. Contact us should you require any service or assistance.

# ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com

Sales & Service service@adlinktech.com

Telephone No. +886-2-8226-5877

Fax No. +886-2-8226-5717

Mailing Address 9F No. 166 Jian Yi Road, Chungho City,

Taipei Hsien 235, Taiwan, ROC

# ADLINK TECHNOLOGY AMERICA, INC.

Sales & Service info@adlinktech.com

Toll-Free +1-866-4-ADLINK (235465)

Fax No. +1-949-727-2099

Mailing Address 8900 Research Drive, Irvine,

CA 92618, USA

# ADLINK TECHNOLOGY EUROPEAN SALES OFFICE

Sales & Service emea@adlinktech.com

Toll-Free +49-211-4955552

Fax No. +49-211-4955557

Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany

# ADLINK TECHNOLOGY SINGAPORE PTE LTD

Sales & Service singapore@adlinktech.com

Telephone No. +65-6844-2261

Fax No. +65-6844-2263

Mailing Address 84 Genting Lane #07-02A,

Cityneon Design Center, Singapore 349584

# ADLINK TECHNOLOGY INDIA LIAISON OFFICE

Sales & Service india@adlinktech.com

Telephone No. +91-80-57605817

Fax No. +91-80-26671806

Mailing Address No. 1357, Ground Floor, "Anupama",

Aurobindo Marg JP Nagar (Ph-1)

Bangalore - 560078

# ADLINK TECHNOLOGY BEIJING

Sales & Service market@adlinkchina.com.cn

Telephone No. +82-2-20570565

Fax No. +82-2-20570563

Mailing Address 4F, Kostech Building, 262-2,

Yangjae-Dong, Seocho-Gu,

Seoul, 137-130, South Korea

# ADLINK TECHNOLOGY BEIJING

Sales & Service market@adlinkchina.com.cn

Telephone No. +86-10-5885-8666

Fax No. +86-10-5885-8625

Mailing Address Room 801, Building E, Yingchuangdongli

Plaza, No.1 Shangdidonglu,

Haidian District, Beijing, China

# ADLINK TECHNOLOGY SHANGHAI

Sales & Service market@adlinkchina.com.cn

Telephone No. +86-21-6495-5210

Fax No. +86-21-5450-0414

Mailing Address Floor 4, Bldg. 39, Caoheting Science and

Technology Park, No.333 Qinjiang Road,

Shanghai, China

# ADLINK TECHNOLOGY SHENZHEN

Sales & Service market@adlinkchina.com.cn

Telephone No. +86-755-2643-4858

Fax No. +86-755-2664-6353

Mailing Address C Block, 2nd Floor, Building A1,

Cyber-tech Zone, Gaoxin Ave. 7.S,

High-tech Industrial Park S.,

Nanshan District, Shenzhen,

Guangdong Province, China

# Using this manual

# 1.1 Audience and scope

This manual guides you when using ADLINK NuDAQ® multi-function PCI card. The card's hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming.

# 1.2 How this manual is organized

This manual is organized as follows:

Chapter 1 Introduction: This chapter introduces the NuDAQ® PCI-9221 card including its features, specifications, software support information, and package contents.

Chapter 2 Hardware Information: This chapter presents the card's layout and connector pin definition.

Chapter 3 Installation: This part describes the PCI-9221 installation, configuration, and options for signal connections.

Chapter 4 Operation Theory: The operation theory of the PCI-9221 functions including A/D conversion, D/A conversion, and programmable function I/O are discussed in this chapter.

Chapter 5 Calibration: The chapter offers information on how to calibrate the PCI-9221 for accurate data acquisition and output.

Appendix: The Appendix contains information on ADLINK components that are recommended for use with the PCI-9221.

Warranty Policy: This presents the ADLINK Warranty Policy terms and coverages.

# 1.3 Conventions

Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly.

NOTE Additional information, aids, and tips that help you perform particular tasks.

IMPORTANT Critical information and instructions that you MUST perform to complete a task.

WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.

# Table of Contents

# List of Tables...... iii

# List of Figures ...... iv

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 3
1.4 Unpacking Checklist 6
1.5 Software Support 7
Software Support 7
Programming Library 7

# 2 Hardware Information 9

2.1 Card Layout 9
2.2 Connector Pin Assignment 10

# 3 Installation 11

3.1 Before You Proceed 11
3.2 Installing the Card.... 11
3.3 Configuring the Card.... 12
Configuration 12
Troubleshooting 12

3.4 Signal Connections.... 13
Signal Descriptions 13
Analog Input Signal Connection 14
Input Configurations 15

# 4 Operation Theory 19

4.1 A/D Conversion.... 19
AI Data Format 20
Programmable Scan Acquisition Mode 21

4.2 D/A Conversion.... 27

4.3 Programmable Function I/O 28

TTL DI/DO 28

General Purpose Timer/Counter 29

Encoder mode 36

4.4 Trigger Sources 40

Software-Trigger 40

External Digital Trigger 40

# 5 Calibration 41

5.1 Loading Calibration Constants.... 41

5.2 Auto-calibration 41

5.3 Saving Calibration Constants.... 42

# Appendix: ADLINK TB-9221 43

# Warranty Policy 45

# List of Tables

Table 2-1: Connector Pin Assignment 10

Table 3-1: I/O Signal Description 13

Table 4-1: Bipolar Analog Input Range and Output Digital Code 20

Table 4-2: Bipolar Output Code Table 27

Table 4-3: Pin definition of TTL DIO mode 28

Table 4-4: Pin Definition of Timer/Counter Mode 29

Table 4-5: Pin Definition for Encoder Mode 36

# List of Figures

Figure 2-1: PCI-9221 Layout.... 9

Figure 3-1: Floating Source and RSE Input Connections ..... 15

Figure 3-2: Ground-referenced Sources and NRSE Input Connections.... 16

Figure 3-3: Ground-referenced Source and Differential Input.... 16

Figure 3-4: Floating Source and Differential Input 17

Figure 4-1: Scan Timing.... 22

Figure 4-2: Post Trigger 24

Figure 4-3: Scatter-gather DMA for Data Transfer.... 26

Figure 4-4: Mode 1 Operation.... 31

Figure 4-5: Mode 2 Operation.... 31

Figure 4-6: Mode 3 Operation.... 32

Figure 4-7: Mode 4 Operation.... 32

Figure 4-8: Mode 5 Operation.... 33

Figure 4-9: Mode 6 Operation.... 33

Figure 4-10: Mode 7 Operation.... 34

Figure 4-11: Mode 8 Operation.... 34

Figure 4-12: Mode 9 Operation.... 35

Figure 4-13: Mode 10 Operation.... 35

Figure 4-14: Differential to Single-ended Conversion 36

Figure 4-15: CW/CCW Encoder Timing 37

Figure 4-16: X1 Encoder Mode 37

Figure 4-17: X2 Encoder Mode 38

Figure 4-18: X4 Encoder Mode 38

Figure 4-19: Phase Z 39

Figure 4-20: External Digital Trigger 40

# 1 Introduction

The ADLINK PCI-9221 is a 16-bit high-resolution and low-cost multifunction DAQ card capable of up to 250 kS/s sampling rate in 16-CH single-ended or 8-CH differential input configurations. In addition, the PCI-9221 comes with a 2-CH 16-bit static analog output and programmable function I/O. The software-programmable function I/O supports a variety of applications, including TTL digital I/O, general purpose timer/counter, encoder input, and PWM output. The flexible function I/O makes the PCI-9221 the best single-board solution for combined data acquisition and simple motion control functionalists. Ideal for manufacturing, laboratory research, and factory automation, the PCI-9221 comes with all the functions you need at an affordable price.

# 1.1 Features

The PCI-9221 comes with the following advanced features:

▶ Supports a 32-bit 3.3 V or 5 V PCI bus
▶ 16-CH single-ended or 8-CH differential analog input
▶ Up to 250 kS/s sampling rate
▶ Programmable gains: x1, x5, x10, x25
▶ 2-CH 16-bit static analog output
▶ 12-CH programmable I/O $^{*}$ , supporting
▷ 8-CH DI and 4-CH DO
▷ 2-CH 32-bit 40 MHz general purpose timer/counters
▷ 2-CH 4 MHz encoder input, supporting AB phase and CW/CCW
▷ 2-CH PWM outputs

▶ Auto-calibration feature

\* The card may only run on one programmable I/O mode.

# 1.2 Applications

The PCI-9221 is suitable for these applications:

▶ Automotive testing
▶ Transient signal measurement
▶ ATE
▶ Laboratory automation
▶ Biotech measurement

# 1.3 Specifications

<table><tr><td colspan="2">Analog Input (AI)</td></tr><tr><td>Channels (programmable)</td><td>16 single-ended (SE) or 8 differential input (DI)</td></tr><tr><td>A/D converter</td><td>AD7685 or equivalent</td></tr><tr><td>Maximum sampling rate</td><td>250K samples/s (single channel)100K samples/s (scanning)</td></tr><tr><td>Resolution</td><td>16 bits</td></tr><tr><td>Input coupling</td><td>DC</td></tr><tr><td>Bipolar input range and gain</td><td>±5 V = 1±1 V = 5±0.5 V = 10±0.2 V = 25</td></tr><tr><td>Operational common mode voltage range</td><td>±5.5 V</td></tr><tr><td>Overfatigue protection</td><td>Power on (continuous) ±10 VPower off (continuous) ±10 V</td></tr><tr><td>FIFO buffer size</td><td>1024 samples (512 x 32 bits)</td></tr><tr><td>Data transfers</td><td>Programmed I/OBus-mastering DMA with scatter/gather</td></tr><tr><td>Channel gain queue configuration size</td><td>16 words</td></tr><tr><td>-3dB small signal bandwidth1</td><td>±5 V = 1800 kHz±1 V = 1800 kHz±0.5 V = 1600 kHz±0.2 V = 1400 kHz</td></tr><tr><td>System noise2</td><td>±5 V = 0.54 LSBrms±1 V = 0.74 LSBrms±0.5 V = 1.0 LSBrms±0.2 V = 2.3 LSBrms</td></tr><tr><td>Input impedance</td><td>Normal power on: 1000G/150 pFPower off: 1 KΩOverload: 1 KΩ</td></tr><tr><td>CMMR3</td><td>±5 V = 71 dB±1 V = 80 dB±0.5 V = 86 dB±0.1 V = 91 dB</td></tr><tr><td>Settling time to full-scale step4</td><td>Multiple channels: 4 μs to 0.6% errorMultiple ranges: 5 μs to 0.1% error</td></tr><tr><td>Time-base source</td><td>Internal 40 MHzExternal clock input (fmax: 20 MHz, fmin: 50% duty cycle)</td></tr><tr><td>Trigger mode</td><td>Post-trigger</td></tr><tr><td>Offset error</td><td>Before calibration: ±2.6 mV typicalAfter calibration: ±0.5 mV typical</td></tr><tr><td>Gain error</td><td>Before calibration: ±0.2% typicalAfter calibration: ±0.015% typical</td></tr><tr><td colspan="2">Analog Output (AO)</td></tr><tr><td>Number of channels</td><td>2 analog voltage outputs</td></tr><tr><td>D/A converter</td><td>Onboard converter</td></tr><tr><td>Maximum update range</td><td>1.25 k sample/s (static)</td></tr><tr><td>Resolution</td><td>16 bits</td></tr><tr><td>Data transfers</td><td>Programmed I/O</td></tr><tr><td>Output range</td><td>±5 V</td></tr><tr><td>Settling time</td><td>1396μs (0.1% of full scale)</td></tr><tr><td>Slew rage</td><td>0.014/uS</td></tr><tr><td>Output coupling</td><td>DC</td></tr><tr><td>Protection</td><td>No</td></tr><tr><td>Output impedance</td><td>330 Ω max</td></tr><tr><td>Output driving</td><td>±5 mA max</td></tr><tr><td>Stability</td><td>Any passive load, up to 1500 pF</td></tr><tr><td>Power-on state</td><td>Around 0 V steady-state</td></tr><tr><td>Power-on glitch</td><td>6.25 mV/ms</td></tr><tr><td>Offset error</td><td>Before calibration: ±35 mV typicalAfter calibration: ±1 mV typical</td></tr><tr><td>Gain error</td><td>Before calibration: ±1% of output maxAfter calibration: ±0.02% of output max</td></tr><tr><td colspan="2">Programmable Function I/O</td></tr><tr><td>Number of channels</td><td>8 DI, 4 DO</td></tr><tr><td>Compatibility</td><td>TTL (single-ended)</td></tr><tr><td>Input voltage</td><td>Logic low: VIL = 0.8 V max; IIL = 0.2 mA maxLogic high: VIH = 2.0 V min; IIH = 0.2 mA max</td></tr><tr><td>Output voltage</td><td>Logic low:  $VIL = 0.5$  V max;  $IIL = 10$  mA maxLogic high:  $VIH = 2.6$  V min;  $IIH = 10$  mA max</td></tr><tr><td rowspan="4">Supported modes $^{5}$ </td><td>8-CH TTL DI and 4-CH TTL DO</td></tr><tr><td>2-CH, 32-bit general-purpose timer/countersClock source: Internal or externalMaximum source frequency: Internal, 40 MHz; External, 10 MHz</td></tr><tr><td>2-CH encoder inputsMaximum input frequency: 4 MHzEncoder modes:CW/CCWX1 AB phase encoderX2 AB phase encoderX4 AB phase encoder</td></tr><tr><td>2-CH PWM outputsDuty cycle: 1% to 99%Modulation frequency: 20 MHz to 0.005 Hz</td></tr></table>

<table><tr><td colspan="2">Physical, Power, and Operating Environment</td></tr><tr><td>Dimension</td><td>120 mm x 87 mm</td></tr><tr><td>I/O connector</td><td>37-pin D-sub connector</td></tr><tr><td>Power Requirement</td><td>+5 VDC; 1A for PCI-9221</td></tr><tr><td>Operating environment</td><td>• Ambient temperature: 0°C to 45°C• Relative humidity: 10% to 90% non-condensing</td></tr><tr><td>Storage environment</td><td>• Ambient temperature: -20°C to 80°C• Relative humidity: 5% to 95% non-condensing</td></tr></table>

$^{1}$ Typical 25°C.

$^{2}$ LSBrms, including quantization. Typical $25^{\circ}$ C.

$^{3}$ Typical DC to 60 Hz

$^{4}$ All input range, typical $25^{\circ}$ C

$^{5}$ The card may only function in one of these modes. These modes may not work simultaneously. Refer to section 4.3: Programmable Function I/O.

Specifications are subject to change without notice.

# 1.4 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK.

Check if the following items are included in the package.

▶ PCI-9221 multi-function DAQ card
▶ ADLINK All-in-One CD
▶ User's manual

If any of the items is damaged or missing, contact your dealer immediately.

# CAUTION

The card must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the card. Wear a grounded wrist strap when servicing.

# 1.5 Software Support

# Software Support

ADLINK provides versatile software drivers and packages to suit various user approach to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environment such as LabVIEW $^{®}$ .

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes only up to two hours. Contact your ADLINK dealers if you want to purchase the software license.

# Programming Library

For customers who want to write their own programs, ADLINK provides the PCIS-DASK function library that is compatible with various operating systems.

# PCIS-DASK

The PCIS-DASK includes device drivers and DLL for Windows 98/NT/2000/XP. DLL is binary compatible across Windows 98/NT/2000/XP. This means all applications developed with PCIS-DASK are compatible with these Windows operating systems. The developing environment may be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The PCIS-DASK user's and function reference manuals are in the ADLINK All-in-One CD. (\Manual\Software Package\PCIS-DASK).

# 2 Hardware Information

This chapter provides information on the PCI-9221 layout, connectors, and pin assignments.

# 2.1 Card Layout

Figure 2-1 shows the PCI-9221 board and bracket layout and dimensions.

![17.5\n63.65](.pci-9221-manual-5/af6069e5773b6b76d0e4afe34b77695f1c08ad452e2650074ca68d6fa96dd99c.jpg)

![119.9\n100.33\n86.7\n44.43\n93.2\n94.54\n106.46](.pci-9221-manual-5/927d08439d6a86b7d884ba7f26017a7a1f765f6a580949cab05efe5b0683ce00.jpg)

Figure 2-1: PCI-9221 Layout

# 2.2 Connector Pin Assignment

The PCI-9221 is equipped with a 37-pin D-Sub connector. This connector is used for analog input/output, digital input/output, and timer/counter signaling, among others. The pin assignment for the connectors is listed below.

<table><tr><td>Definition</td><td colspan="2">Pin #</td><td>Definition</td></tr><tr><td>GPO2</td><td>1</td><td>20</td><td>GPO3</td></tr><tr><td>DGND</td><td>2</td><td>21</td><td>GPO1/GPTC_OUT1</td></tr><tr><td>GPO0/GPTC_OUT0</td><td>3</td><td>22</td><td>GPI7/ORG1/GPTC_AUX1</td></tr><tr><td>GPI6/EZ1/GPTC_GATE1</td><td>4</td><td>23</td><td>DGND</td></tr><tr><td>GPI5/EB1/GPTC_UD1</td><td>5</td><td>24</td><td>GPI4/EA1/GPTC_CLK1</td></tr><tr><td>GPI3/ORG0/GPTC_AUX0</td><td>6</td><td>25</td><td>GPI2/EZ0/GPTC_GATE0</td></tr><tr><td>DGND</td><td>7</td><td>26</td><td>GPI1/ EB0/GPTC_UD0</td></tr><tr><td>GPI0/EA0/GPTC_CLK0</td><td>8</td><td>27</td><td>AO1</td></tr><tr><td>AOGND</td><td>9</td><td>28</td><td>AO0</td></tr><tr><td>AIGND</td><td>10</td><td>29</td><td>AI15(AIL7)</td></tr><tr><td>AI7(AIH7)</td><td>11</td><td>30</td><td>AI14(AIL6)</td></tr><tr><td>AI6(AIH6)</td><td>12</td><td>31</td><td>AI13(AIL5)</td></tr><tr><td>AI5(AIH5)</td><td>13</td><td>32</td><td>AI12(AIL4)</td></tr><tr><td>AI4(AIH4)</td><td>14</td><td>33</td><td>AISENSE</td></tr><tr><td>AIGND</td><td>15</td><td>34</td><td>AI11(AIL3)</td></tr><tr><td>AI3(AIH3)</td><td>16</td><td>35</td><td>AI10(AIL2)</td></tr><tr><td>AI2(AIH2)</td><td>17</td><td>36</td><td>AI9(AIL1)</td></tr><tr><td>AI1(AIH1)</td><td>18</td><td>37</td><td>AI8(AIL0)</td></tr><tr><td>AI0(AIH0)</td><td>19</td><td></td><td></td></tr></table>

Table 2-1: Connector Pin Assignment

# 3 Installation

# 3.1 Before You Proceed

The PCI-9221 card has electro-static sensitive components that can be easily damaged by static electricity. The card must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for damages. Shipping and handling could cause damage to the module. Make sure that the card has no damage before installing.

After opening the card packaging, get the module and place it on a grounded anti-static surface with component side up, then carefully inspect the module for any damage. Press down all socketed IC's to make sure that they are properly seated. Do this only with the module placed on a firm flat surface.

WARNING Do not apply power to the card if it is damaged.

# 3.2 Installing the Card

# To install the card:

1. Turn off the system/chassis and disconnect the power plug from the power source.
2. Remove the system/chassis cover.
3. Select the PCI slot that you intend to use, then remove the bracket opposite the slot, if any.
4. Align the card connectors (golden fingers) with the slot, then press the card firmly until the card is completely seated on the slot.
5. Secure the card to the chassis with a screw.
6. Replace the system/chassis cover.
7. Connect the power plug to a power source, then turn on the system/chassis.

# 3.3 Configuring the Card

As a plug and play component, the card requests an interrupt number through its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load detected by the system.

# Configuration

The board configuration is done on a board-by-board basis for all PCI boards on your system. Because configuration is controlled by the system and the software, there is no jumper setting required for base address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the system as new boards are added or removed.

# Troubleshooting

If your system fails to boot or if you experience erratic operation with your PCI board in place, this is likely caused by an interrupt conflict (i.e. the BIOS Setup is incorrectly configured). Refer to the BIOS documentation that came with the system for details.

# 3.4 Signal Connections

The following sections discuss the PCI-9221 signal descriptions and analog input connections.

Signal Descriptions

<table><tr><td>Signal Name</td><td>Reference</td><td>Direction</td><td>Description</td></tr><tr><td>AIGND</td><td>—</td><td>—</td><td>Analog ground for AI.</td></tr><tr><td>AI&lt;0..15&gt;</td><td>AIGND</td><td>Input</td><td>Analog Input Channels 0~15. Each channel pair, AI&lt;i, i+8&gt;(I=0..7) can be configured either two single-ended inputs or one differential input pair (marked as AIH&lt;0..7&gt; and AIL&lt;0..7&gt;).</td></tr><tr><td>AISENSE</td><td>AIGND</td><td>Input</td><td>Analog Input Sense. This pin is the reference for any channels AI&lt;0..63&gt; in NRSE input configuration.</td></tr><tr><td>AO&lt;0, 1&gt;</td><td>AOGND</td><td>Output</td><td>AO channel &lt;0, 1&gt;</td></tr><tr><td>AOGND</td><td>—</td><td>—</td><td>Analog ground for AO.</td></tr><tr><td>GPI&lt;0..7&gt;</td><td>DGND</td><td>Input</td><td>Function Input &lt;0..7&gt; (Refer to section 4.3.)</td></tr><tr><td>GPO&lt;0..3&gt;</td><td>DGND</td><td>Output</td><td>Function Output &lt;0..3&gt; (Refer to section 4.3.)</td></tr><tr><td>EA&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Encoder A Phase</td></tr><tr><td>EB&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Encoder B Phase</td></tr><tr><td>EZ&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Encoder Z Phase</td></tr><tr><td>ORG&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Original Signal</td></tr><tr><td>GPTC_CLK&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Clock source of GPTC&lt;0, 1&gt;.</td></tr><tr><td>GPTC_GATE&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Gate of GPTC&lt;0, 1&gt;.</td></tr><tr><td>GPTC_OUT&lt;0, 1&gt;</td><td>DGND</td><td>Output</td><td>Output of GPTC&lt;0, 1&gt;.</td></tr><tr><td>GPTC_UD&lt;0, 1&gt;</td><td>DGND</td><td>Input</td><td>Up/Down of GPTC&lt;0, 1&gt;.</td></tr><tr><td>DGND</td><td>—</td><td>—</td><td>Digital ground for GPI/GPO.</td></tr></table>

Table 3-1: I/O Signal Description

# Analog Input Signal Connection

The PCI-9221 provides up to 16 single-ended or 8 differential analog input channels. You can fill the Channel Gain Queue to get the desired input signal type combination. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and obtain a more accurate measurement from the A/D conversion, it is important to understand the signal source type and how to choose the analog input modes: Referenced Single-Ended (RSE), Non-Referenced Single-Ended (NRSE), and Differential Input (DIFF) mode.

# Types of Signal Sources

# Floating Signal Sources

A floating signal source means it is not connected in any way to the buildings ground system. A device with an isolated output is a floating signal source, such as optical isolator outputs, transformer outputs, and thermocouples.

# Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way to the building's system. That is, the signal source is already connected to a common ground point with respect to the PCI-9221, assuming that the computer is plugged into the same power system. Non-isolated outputs of instruments and devices that plug into the building's power systems are ground-referenced signal sources.

# Input Configurations

# Single-ended Connections

A single-ended connection is used when the analog input signal is referenced to a ground that can be shared with other analog input signals. There are two types of single-ended connections: RSE and NRSE configuration. In RSE configuration, the PCI-9221 card provides the grounding point for the external analog input signals and is suitable for floating signal sources. In NRSE configuration, the card does not provide the grounding point, the external analog input signal provides its own reference grounding point and is suitable for ground-referenced signals.

# Referenced Single-ended (RSE) Mode

In referenced single-ended mode, all the input signals are connected to the ground provided by the PCI-9221. It is suitable for connections with floating signal sources. Figure 3-1 shows an illustration. Note that when more than two floating sources are connected, these sources will be referenced to the same common ground.

![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n*   **Floating Signal Source**: A group on the left containing two AC voltage sources labeled **V1** and **V2**. Below this section is the text **n = 0, ..., 63**.\n*   **CN1 Input Muxplexer**: A central block consisting of a vertical bar with terminals on the left and a rectangular box in the middle. The vertical bar is labeled **AIn** (near the top) and **AIGND** (near the bottom).\n*   **Instrumentation Amplifier**: A triangle symbol located to the right of the Muxplexer.\n*   **To A/D Converter**: Text label on the far right indicating the output destination.\n\n**Connections:**\n*   **V1** and **V2** (from the Floating Signal Source) connect to the **CN1 Input Muxplexer**. The top of source **V1** connects to the top terminal of the vertical bar, and the top of source **V2** connects to the second terminal down.\n*   The vertical bar (**AIn** / **AIGND**) connects to the central rectangular part of the Muxplexer via multiple horizontal lines.\n*   The output from the **CN1 Input Muxplexer** connects to the non-inverting (+) input of the **Instrumentation Amplifier**.\n*   The inverting (-) input of the amplifier is connected to the common ground line at the bottom.\n*   The output of the amplifier connects to the line labeled **To A/D Converter**. This output line features **+** and **-** indicators.\n*   A common ground line runs along the bottom, connecting the negative terminals of **V1** and **V2**, the **AIGND** terminal, and the negative input of the amplifier.](.pci-9221-manual-5/ddb59744b7024a57ce9f38c94395a1bb2552b77bd2d58781988cbf35acffabab.jpg)

Figure 3-1: Floating Source and RSE Input Connections

# Non-Referenced Single-ended (NRSE) Mode

To measure ground-referenced signal sources, which are connected to the same ground point, you can connect the signals in NRSE mode. Figure 3-2 illustrates the connection. The signals local ground reference is connected to the negative input of the instrumentation Amplifier (AISENSE pin on CN1 connector), and the common-mode ground potential between signal ground and the ground on board will be rejected by the instrumentation amplifier.

![The flowchart depicts a signal acquisition system with the following labeled blocks and connections:\n\n**Labeled Blocks and Components:**\n*   **Ground-Referenced Signal Source**: A label on the left.\n*   **V1** and **V2**: Two circles containing sine waves, representing signal sources.\n*   **Common-mode noise & Ground potential**: A label below the signal sources.\n*   **Vcm**: A circle containing a DC voltage source symbol.\n*   **Input Multiplexer**: A label above the central rectangular block.\n*   **AIn**: A label above the top input pin of the multiplexer.\n*   **AISENSE**: A label next to the bottom input pin of the multiplexer.\n*   **Instrumentation Amplifier**: A label above the triangular amplifier symbol.\n*   **To A/D Converter**: Text on the far right indicating the output destination.\n*   Text **n = 0, ..., 63** appears near the connection to the common-mode noise source.\n\n**Connections:**\n*   **V1** connects to the top input pin of the **Input Multiplexer** (labeled **AIn**).\n*   **V2** connects to the second input pin of the **Input Multiplexer**.\n*   The bottom terminals of **V1** and **V2**, along with the top terminal of **Vcm**, are connected to a common line labeled **AISENSE**. This line connects to the bottom input pin of the **Input Multiplexer**.\n*   The output of the **Input Multiplexer** connects to the **'+'** input of the **Instrumentation Amplifier**.\n*   The **AISENSE** line connects to the **'-'** input of the **Instrumentation Amplifier**.\n*   The output of the **Instrumentation Amplifier** connects to the text **To A/D Converter**.](.pci-9221-manual-5/beb5900abfd784d672155d9bd0a1a6c650dd4e5c492e7ff8ef413e68ea71891b.jpg)

Figure 3-2: Ground-referenced Sources and NRSE Input Connections

# Differential input mode

The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 3-3 shows the connection of ground-referenced signal sources under differential input mode.

![Based on the provided block diagram, here is the accurate and concise description:\n\n**Blocks and Labels:**\n*   **Signal Source Section:** A circle with a sine wave labeled 'Ground Referenced Signal Source'. Below it is a circle labeled 'Vcm' with text 'Common-mode noise & Ground potential'.\n*   **Multiplexer Section:** A vertical bus bar labeled 'Input Multiplexer'. Above it is the text 'x = 0, ..., 31'. To the right of the bus bar are two rectangular blocks representing the multiplexer switches.\n*   **Amplifier Section:** A triangle symbol labeled 'Instrumentation Amplifier'.\n*   **Output:** Text 'To A/D Converter'.\n\n**Connections:**\n*   **Inputs:**\n    *   The 'Ground Referenced Signal Source' connects via a line labeled **AIxH** to the upper inputs of the Input Multiplexer bus bar.\n    *   The 'Common-mode noise & Ground potential' (Vcm) connects via a line labeled **AIxL** to the middle inputs of the Input Multiplexer bus bar.\n    *   The bottom of the bus bar is labeled **AIGND** and connects to a ground symbol.\n*   **Multiplexer to Amplifier:**\n    *   The upper rectangular block inside the Input Multiplexer connects to the non-inverting input (**+**) of the Instrumentation Amplifier.\n    *   The lower rectangular block inside the Input Multiplexer connects to the inverting input (**-**) of the Instrumentation Amplifier.\n    *   The reference pin of the Instrumentation Amplifier is connected to ground.\n*   **Amplifier to Output:**\n    *   The output of the Instrumentation Amplifier connects to the positive (**+**) terminal labeled 'To A/D Converter'.\n    *   The negative (**-**) terminal labeled 'To A/D Converter' is connected to ground.](.pci-9221-manual-5/80556a3b5e9786cfa24abd880638d2443426efcbf1fcf2452e36526e62d59279.jpg)

Figure 3-3: Ground-referenced Source and Differential Input

Figure 3-4 shows how to connect a floating signal source to the PCI-9221 in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. If the source impedance is less than 100ohms, you can simply connect the negative side of the signal to AIGND as well as the negative input of the Instrumentation Amplifier without any resistors. In differential input mode, less noise couples into the signal connections than in single-ended mode.

![Ground\nReferenced\nSignal\nSource\nx = 0, ..., 31\nInput Multiplexer\nInstrumentation\nAmplifier\nTo A/D\nConverter\nAIXH\nAIXL\nAIGND](.pci-9221-manual-5/1123ff98f16e33bc32a3884edb5505422d7e41b37865012e6f24b157d6ffb964.jpg)

Figure 3-4: Floating Source and Differential Input

# 4 Operation Theory

The operation theory of the PCI-9221 functions is described in this chapter. The functions include A/D conversion, D/A conversion, and programmable function I/O. The operation theory helps you understand the PCI-9221 configuration and programming.

# 4.1 A/D Conversion

When using an A/D converter, you must know about the properties of the signal to be measured. You may decide which channel to use and how to connect the signals to the card. Refer to section 3.4. In addition, users should define and control the A/D signal configurations, including channels, gains, and polarities (unipolar/bipolar).

The A/D acquisition is initiated by a trigger source and you must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched.

After the end of an A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data can now be transferred into the system memory for further processing.

The Software Polling and Scan Acquisition modes are discussed below as well as timing, trigger modes, trigger sources, and transfer methods.

# AI Data Format

The data format of the acquired 16-bit A/D data is 2's Complement coding. Table 4-1 shows the valid input ranges and the ideal transfer characteristics.

<table><tr><td>Description</td><td colspan="4">Bipolar Analog Input Range</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>±5V</td><td>±1V</td><td>±0.5V</td><td>±0.2V</td><td></td></tr><tr><td>Least significant bit</td><td>152.6uV</td><td>30.5uV</td><td>15.3uV</td><td>6.1uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>4.999847V</td><td>0.99997V</td><td>0.499985V</td><td>0.199939V</td><td>7FFF</td></tr><tr><td>Midscale +1LSB</td><td>152.6uV</td><td>30.5uV</td><td>15.3uV</td><td>6.1uV</td><td>0001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0000</td></tr><tr><td>Midscale -1LSB</td><td>-152.6uV</td><td>-30.5uV</td><td>-15.3uV</td><td>-6.1uV</td><td>FFFF</td></tr><tr><td>-FSR</td><td>-5V</td><td>-1V</td><td>-0.5V</td><td>-0.2V</td><td>8000</td></tr></table>

Table 4-1: Bipolar Analog Input Range and Output Digital Code

# Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. The software then polls the conversion status and read the A/D data back when it is available.

This method is suitable for applications that need to process A/D data in real time. In this mode, the timing of the A/D conversion is fully controlled by the software. The A/D conversion rate is decided by the software timer and may not be totally precise.

In Software Polling, the channel, gain, and input configuration (RSE, NRSE, or DIFF) may be specified for each single-point measurement.

Example:

Ch2 with $\pm$ 5V input range and single-ended NRSE connection

# Programmable Scan Acquisition Mode

# Scan Timing and Procedure

It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least four counters that have to be specified:

▶ SI\_counter (32-bit): Specify the Scan Interval = SI\_counter / Timebase
▶ SI2\_counter (24-bit): Specify the data Sampling Interval = SI2\_counter/Timebase
▶ PSC\_counter (31-bit): Specify the Post Scan Counts after a trigger event
▶ NumChan\_counter (8-bit): Specify the Number of samples per scan

The acquisition timing and the meaning of the four counters are illustrated in Figure 4-1.

# Timebase Clock Source

In scan acquisition mode, all A/D conversions start on the output of counters which use Timebase as the clock source. Through the software, you may specify the Timebase to be either an internal clock source (onboard 40 MHz) or an external clock input (EXTTIMEBASE) on the programmable function I/O. The external clock is useful when you want to acquire data at rates not available with the internal A/D sample clock. The external clock source should generate TTL-compatible continuous clocks with maximum 20 MHz and minimum 1 MHz frequencies.

![3 Scans, 4 Samples per scan\n(NumChan_Counter=4)\nScan_start\nAD_conversion\nAcquisition_in_progress\nSampling Interval t=\nSI2_COUNTER/TimeBase\nChannel sequences are specified in Channel Gain Queue\nCh2 Ch3 Ch1 Ch0\nCh2 Ch3 Ch1 Ch0\nCh2 Ch3 Ch1 Ch0\nScan start\nAcquisition_in_progress\nScan Interval T=\nSI2_COUNTER/TimeBase\nScan Interval T=](.pci-9221-manual-5/1f7969964ea0936b291b070f8e0f684e9ea134a751b2cb1f10220aae6e8aea5b.jpg)

Figure 4-1: Scan Timing

Two trigger sources are available to start the scan acquisition. Refer to section 4.4 for the details. For the data transfer mode, refer to the Bus-mastering DMA Data Transfer section.

# NOTES

- The maximum A/D sampling rate is 250 kHz. The minimum setting for SI2\_counter is 160 while using the internal Timebase.
- The SI\_counter is 32-bit while the SI2\_counter is 24-bit. The maximum scan interval using the internal Timebase = $2^{32} / 40$ Ms = 107.374 s, and the maximum sampling interval between two channels using the internal Timebase = $2^{24} / 40$ Ms = 0.419 ms.
- The scan interval must not be smaller than the product of the data sampling interval and the NumChan\_counter value. The relationship can be represented as: SI\_counter>=SI2\_counter \* NumChan\_counter.

# Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue

The channel, gain, and input configurations can be specified in the Channel Gain Queue under the scan acquisition mode. Refer to section section. Note that in scan acquisition mode the number of entries in the Channel Gain Queue is normally equivalent to the value of NumChan\_counter (the number of samples per scan).

# Example:

# Set

▶ SI2\_counter = 160
▶ SI\_counter = 640
▶ PSC\_counter = 3
▶ NumChan\_counter = 4
▶ Timebase = Internal clock source
▶ Channel entries in the Channel Gain Queue: ch1, ch2, ch0, ch2

# Then

▶ Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2
▶ Sampling Interval = 160/40M s = 4 us
▶ Scan Interval = 640/40M s = 16 us
▶ Equivalent sampling rate of ch0, ch1: 62.5kHz
▶ Equivalent sampling rate of ch2: 125kHz

# Trigger Modes

The PCI-9221 supports two trigger sources: internal software and external digital trigger sources. You must select one as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source. For example, a rising edge on the external digital trigger input.

The card supports post-trigger mode working with software or external digital trigger sources to initiate different scan data acquisition timing when a trigger event occurs.

# Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in the PSC\_counter, illustrated in Figure 4-2. The total acquired data length = NumChan\_counter \*PSC\_counter.

![(NumChan_Counter=4, PSC_Counter=3)\nTrigger\nScan_start\nAD_conversion\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(3 scans)](.pci-9221-manual-5/394e1acbb8fb4cc8191685a16429d499482b1116d1ab99f0e4d4269b608d944a.jpg)

Figure 4-2: Post Trigger

# Bus-mastering DMA Data Transfer

In programmable scan acquisition mode, the PCI-9221 supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on PCI-bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a user-defined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA.

The DMA transfer mode is a very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a high-level programming library for high speed DMA data acquisition, you simply need to assign the sampling period and the number of conversion through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA.

The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list.

In a multi-user or multitasking OS, like Windows, Linux, etc, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the non-continuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-3 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual-address support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs. The software driver provides simple settings of the scatter-gather function, and some sample programs are also provided in the ADLINK All-in-one CD.

![Based on the provided image, here is the accurate description of the flowchart:\n\n**Labeled Blocks:**\n\n*   **Bottom Block:** Local Memory (FIFO)\n*   **Middle Block:** PCI Bus\n*   **Top Row (Left Block):**\n    *   First PCI Address\n    *   First Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n*   **Top Row (Middle Block):**\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n*   **Top Row (Right Block):**\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n\n**Connections:**\n\n*   An arrow points upward from **Local Memory (FIFO)** to **PCI Bus**.\n*   An arrow points upward from **PCI Bus** to the **Top Row (Middle Block)**.\n*   An arrow connects the **Top Row (Left Block)** to the **Top Row (Middle Block)**.\n*   An arrow connects the **Top Row (Middle Block)** to the **Top Row (Right Block)**.](.pci-9221-manual-5/c8cbe1beb3f5378be6ae807741ac6eb0be232d6f1043d27451f0b995acdfb915.jpg)

Figure 4-3: Scatter-gather DMA for Data Transfer

In non-chaining mode, the maximum DMA data transfer size is 2 M double words (8 MB). However, by using chaining mode-scatter/gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multi-buffered mode DMA.

# 4.2 D/A Conversion

There are two single-ended channels of 16-bit static D/A output available in the PCI-9221. These D/A channels support software polling to update output status. The D/A update rate is fully controlled by software timing. Mostly, this is used for applications requiring a constant DC output.

The PCI-9221 supports maximum $\pm5$ V voltage output. Table 4-2 illustrates the relationship of 2's Complement coding between digital code and output voltages

<table><tr><td>Digital Code</td><td>Analog Output</td></tr><tr><td>0x7FFF</td><td>5V * (65535/65536)</td></tr><tr><td>0x0001</td><td>5V * (1/65536)</td></tr><tr><td>0x0000</td><td>0V</td></tr><tr><td>0xFFFF</td><td>5V</td></tr><tr><td>0x8000</td><td>-5V</td></tr></table>

Table 4-2: Bipolar Output Code Table

# 4.3 Programmable Function I/O

The PCI-9221 supports a powerful programmable function I/O provided by an FPGA chip. These function I/O can be configured as TTL DI/DO or 32-bit timer/counters. In addition, the timer/counter supports a variety of modes, including general purpose timer/counter, PWM output, or encoder input for simple motion control. These signals are single-ended and 5 V TTL-compliant.

# TTL DI/DO

Programmable function I/O can be used as static TTL-compliant 8-CH digital inputs and 4-CH digital outputs. You can read/write these I/O line by software polling. Its sample and update rate is fully controlled by software timing.

<table><tr><td>Pin No.</td><td>Name</td><td>Function</td></tr><tr><td>8</td><td>GPI0</td><td>Digital Input CH0</td></tr><tr><td>26</td><td>GPI1</td><td>Digital Input CH1</td></tr><tr><td>25</td><td>GPI2</td><td>Digital Input CH2</td></tr><tr><td>6</td><td>GPI3</td><td>Digital Input CH3</td></tr><tr><td>24</td><td>GPI4</td><td>Digital Input CH4</td></tr><tr><td>5</td><td>GPI5</td><td>Digital Input CH5</td></tr><tr><td>4</td><td>GPI6</td><td>Digital Input CH6</td></tr><tr><td>22</td><td>GPI7</td><td>Digital Input CH7</td></tr><tr><td>3</td><td>GPO0</td><td>Digital Output CH0</td></tr><tr><td>21</td><td>GPO1</td><td>Digital Output CH1</td></tr><tr><td>1</td><td>GPO2</td><td>Digital Output CH2</td></tr><tr><td>20</td><td>GPO3</td><td>Digital Output CH3</td></tr></table>

Table 4-3: Pin definition of TTL DIO mode

# General Purpose Timer/Counter

The programmable function I/O can be configured as two independent 32-bit general purpose timer/counters. They have the following features:

▶ Count up/down controlled by hardware or software
▶ Programmable counter clock source (internal clock up to 40 MHz, external clock up to 10 MHz)
▶ Programmable gate selection (hardware or software control)
▶ Programmable input and output signal polarities (high active or low active)
▶ Initial Count can be loaded from software
▶ Current count value can be read-back by software without affecting circuit operation

<table><tr><td>Pin No.</td><td>Name</td><td>Function</td></tr><tr><td>25</td><td>GPTC_GATE0</td><td>GPTC_0 Enable Gate</td></tr><tr><td>26</td><td>GPTC_UD0</td><td>GPTC_0 Counting Direction</td></tr><tr><td>6</td><td>GPTC_AUX0</td><td>GPTC_0 Auxiliary Signal</td></tr><tr><td>8</td><td>GPTC_CLK0</td><td>External clock source of GPTC_0</td></tr><tr><td>3</td><td>GPTC_OUT0</td><td>GPTC_0 Output</td></tr><tr><td>4</td><td>GPTC_GATE1</td><td>GPTC_1 Enable Gate</td></tr><tr><td>5</td><td>GPTC_UD1</td><td>GPTC_1 Counting Direction</td></tr><tr><td>22</td><td>GPTC_AUX1</td><td>GPTC_1 Auxiliary Signal</td></tr><tr><td>24</td><td>GPTC_CLK1</td><td>External clock source of GPTC_1</td></tr><tr><td>21</td><td>GPTC_OUT1</td><td>GPTC_1 Output</td></tr></table>

Table 4-4: Pin Definition of Timer/Counter Mode

# Basic Timer/Counter Functions

Each timer/counter has three inputs that can be controlled via hardware or software. They are clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UD). The GPTC\_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UD input controls the counter to count up or down. The GPTC\_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications.

All the polarities of input/output signals can be programmed by software. In this chapter, all GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT are assumed to be active high or rising-edge triggered.

# General Purpose Timer/Counter Modes

Ten programmable timer/counter modes are available. All modes start to operate following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and reloads the initial value to the counter. The operation remains halted until the software-start is re-executed. The operating theories in each mode are described below.

# Mode 1: Simple Gated-Event Counting

The counter counts the number of pulses on the GPTC\_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software at anytime without affecting the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-4 illustrates the operation with initial count = 5, count-down mode.

![| Signal | Value |\n|--------|-------|\n| Gate   | 1     |\n| CLK    | 1     |](.pci-9221-manual-5/68eb4b4781d08108060abcdc3ecae3cde4253948b92c71eec931ddee1e797b48.jpg)

Figure 4-4: Mode 1 Operation

# Mode 2: Single Period Measurement

The counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from the software. After the software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by software. Figure 4-5 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.pci-9221-manual-5/fafb01f47fc243efca3d2a3864b79300d08a4872fa3d56ec0d94b31152bac792.jpg)

Figure 4-5: Mode 2 Operation

# Mode 3: Single Pulse-width Measurement

The counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by software. Figure 4-6 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.pci-9221-manual-5/d7680de6cc35a887f0311260019423db2a6b8bcb77147dc77fa161f7563aee00.jpg)

Figure 4-6: Mode 3 Operation

# Mode 4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters can be specified in terms of periods of the GPTC\_CLK input by software. GPTC\_GATE is use to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-7 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | High  |\n| CLK        | Low   |\n| Count value| 2     |\n| OUT        | 0     |](.pci-9221-manual-5/d9fd99548d0c63c1a96f50fef7dd1a3e362ef35dddbd0e212d6788e0ffc892e7.jpg)

Figure 4-7: Mode 4 Operation

# Mode 5: Single Triggered Pulse Generation

This function generates a single pulse with programmable delay and programmable pulse-width following an active GPTC\_GATE edge. You may specify these programmable parameters in terms of periods of the GPTC\_CLK input. When the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until the software-start is executed again. Figure 4-8 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![The image is a timing diagram displaying four signal rows labeled on the left: 'Gate', 'CLK', 'Count value', and 'OUT'. Centered at the top is the text 'Software start'.\n\n*   **Gate:** The signal line is low, briefly pulses high shortly after the vertical 'Software start' dashed line, and returns low.\n*   **CLK:** A continuous square wave signal that begins immediately.\n*   **Count value:** The text 'Count value' appears on the left. To its right, below the CLK signal, is a sequence of numbers aligned with the clock cycles: **2 2 1 0 3 2 1 0**.\n*   **OUT:** The signal line is low, then goes high coinciding with the first '0' in the count sequence, and returns low coinciding with the final '0'.](.pci-9221-manual-5/569153aa6fe073bdb963a9742c342310370db2a602ac2f4e63a232777b10dd9d.jpg)
Figure 4-8: Mode 5 Operation

# Mode 6: Re-triggered Single Pulse Generation

This mode is similar to Mode 5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After the software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE triggers that occur when the prior pulse is not completed is ignored. Figure 4-9 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four.

![| Signal | Value |\n|--------|-------|\n| Gate   | 0     |\n| CLK    | 0     |\n| Count value | 2 |\n| OUT    | 0     |](.pci-9221-manual-5/cff27e32ede804eeedc4f2cdf45e00d3f5d15c0a99bb80983f34c4a1ce4b316d.jpg)

Figure 4-9: Mode 6 Operation

# Mode 7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. When the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until the software-start is executed again. Figure 4-10 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![Software start\nGate\nCLK\nCount value\nOUT](.pci-9221-manual-5/6813c7458e8e60b5e5e7b8e1095f9eddbf44706f0044635dd02bedbba43498a7.jpg)

Figure 4-10: Mode 7 Operation

# Mode 8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC\_GATE is use to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-11 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![Software start\nGate\nCLK\nCount value 4 1 1 1 1 0 3 1 0 1 1 1 0 2 1 1 0 1\nOUT](.pci-9221-manual-5/ca0ff3bf4dfed90731cbc8781ea48114b2026a0e479aaff1ffaa76045b65f83f.jpg)

Figure 4-11: Mode 8 Operation

# Mode 9: Edge Separation Measurement

Measures the time differentiation between two different pulse signals. The first pulse signal is connected to GPTC\_GATE and the second signal is connected to GPTC\_AUX. It counts how many clocks passed by between the rising edge signal of two different pulses through the 40 MHz internal clock or external clock. You can calculate the time period via the known clock frequency. The maximum counting width is 32-bit. Figure 4-12 illustrates how the counter value decreases in Edge Separation Measurement mode.

![| Signal | Value |\n|--------|-------|\n| Gate   | 11    |\n| Gate   | 12    |\n| Gate   | 13    |\n| Gate   | 14    |\n| Gate   | 15    |\n| Gate   | 16    |\n| Gate   | 17    |\n| Gate   | 18    |\n| Gate   | 19    |\n| Gate   | 20    |\n| AUX    | 11    |\n| AUX    | 12    |\n| AUX    | 13    |\n| AUX    | 14    |\n| AUX    | 15    |\n| AUX    | 16    |\n| AUX    | 17    |\n| AUX    | 18    |\n| AUX    | 19    |\n| AUX    | 20    |\n| CLK    | 11    |\n| CLK    | 12    |\n| CLK    | 13    |\n| CLK    | 14    |\n| CLK    | 15    |\n| CLK    | 16    |\n| CLK    | 17    |\n| CLK    | 18    |\n| CLK    | 19    |\n| CLK    | 20    |\n| Count value | 11   |\n| Count value | 12   |\n| Count value | 13   |\n| Count value | 14   |\n| Count value | 15   |\n| Count value | 16   |\n| Count value | 17   |\n| Count value | 18   |\n| Count value | 19   |\n| Count value | 20   |](.pci-9221-manual-5/cb43f1118d81dceaff14c055d8e110f3f14dd5dc46528bff6ab8bedf4df72d38.jpg)

Figure 4-12: Mode 9 Operation

# Mode 10: PWM output

The card's powerful timer/counter can simulate a PWM (Pulse Width Modulation) output. By setting varying number of Pulse\_initial\_cnt and Pulse\_length\_cnt, you can get varying pulse frequency (Fpwm) and duty cycle (Dutypwm). Figure 4-13 illustrates the PWM output and the equation showing how to calculate the PWM frequency and duty cycle.

![PWMOUT\nTIMEBASE\nPulse_Initial_cnt =0x7\nPulse_length_cnt =0xB](.pci-9221-manual-5/0af813c246bcb55993427f390be04751d817ad4148e2744791bd571a10620d6c.jpg)

Figure 4-13: Mode 10 Operation

$$
\begin{array}{l} F _ {P W M} = \frac {F _ {T i m e b a s e}}{P u l s e \_ i n i t i a l \_ c n t + P u l s e \_ l e n g t h \_ c n t} \\ D u t y _ {P W M} = \frac {\text { Pulse\_length\_cnt }}{\text { Pulse\_initial\_cnt } + \text { Pulse\_length\_cnt }} \\ \end{array}
$$

# Encoder mode

The PCI-9221 programmable function I/O supports encoder input that provides an alternative for stepper or servo motor's position feedback, thus providing a way to combine data acquisition and simple motion control. The PCI-9221 only supports single-ended mode for these signal connections. If your encoder signals are in differential mode, you need to convert to single-ended mode, then connect to PCI-9221. You may also use the ADLINK TB-9221 termination board to convert differential signals to single-ended mode. Refer to the appendix for details.

The following table illustrates the card's pin assignments for encoder mode.

Pin Assignment

<table><tr><td>Pin No.</td><td>Name</td><td>Function</td></tr><tr><td>8</td><td>EA0</td><td>Encoder_0 A Phase</td></tr><tr><td>26</td><td>EB0</td><td>Encoder_0 B Phase</td></tr><tr><td>25</td><td>EZ0</td><td>Encoder_0 Z Phase</td></tr><tr><td>6</td><td>ORG0</td><td>Encoder_0 Original Signal</td></tr><tr><td>24</td><td>EA1</td><td>Encoder_1 A Phase</td></tr><tr><td>5</td><td>EB1</td><td>Encoder_1 B Phase</td></tr><tr><td>4</td><td>EZ1</td><td>Encoder_1 Z Phase</td></tr><tr><td>22</td><td>ORG1</td><td>Encoder_1 Original Signal</td></tr></table>

Table 4-5: Pin Definition for Encoder Mode

Differential Signal to Single-end Signal in TB-9221 Terminal Board

![EAx+, EBx+, EZx+\nEAX-, EBx-, EZx-\nVCC\nEAx, EBx, EZx\nGND](.pci-9221-manual-5/d3d42213f202c3473a3783515e9d00205389d7b78fbdb1da48fcce4107788672.jpg)

Figure 4-14: Differential to Single-ended Conversion

# CW/CCW Encoder Mode

When GPTC is set to CW/CCW encoder mode and if the input EAx is connected to CW source signal and EBx is connected to CCW source signal, then pulses from EAx will cause the counter to counter up and spin the motor clockwise. Otherwise, pulses from EBx will cause the counter to counter down and spin the motor counterclockwise. Figure 4-15 shows the increase/decrease of counter value in CW or CCW encoder mode.

![CW\nCCW\nEA0/EA1\nEB0/EB1\nCount Value 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2](.pci-9221-manual-5/37fff816836404586848fc16b699fc40bcc2fd3b0d36c087290cdd43a9b4d703.jpg)

Figure 4-15: CW/CCW Encoder Timing

# x1 Encoder Mode

In X1 encoder mode, if phase A (EA0/EA1) is advanced of phase B (EB0/EB1) in a quadrature cycle, the increment of counter value will be 1. Otherwise, if phase B is advanced of phase A in a quadrature cycle, the decrement of counter value will also be 1.

Figure 4-16 shows a quadrature cycle and the increment and decrement of counter value in X1 encoder mode. When phase A leads phase B, the counter value increases on the first rising edge of CLK after phase A goes high. When phase B leads phase A, the counter value decreases on the first rising edge of CLK after phase A goes low.

![Phase A\nPhase B\nCLK\nCount Value 0 1 1 2 2 3 3 2 2 1](.pci-9221-manual-5/9e8bd3ec54843a1cd59bb28be591b800445b69ab09c771edc9014364470dafa8.jpg)

Figure 4-16: X1 Encoder Mode

# X2 Encoder Mode

This mode is similar to X1 Encoder Mode, except that the amount of counter value increases or decreases by two. Refer to Figure 4-17.

![Phase A\nPhase B\nCLK\nCount Value 0 1 2 3 4 5 5 4 3 2 1](.pci-9221-manual-5/1c142ffefdf853eaf25ad78e70ac20695d194f8bac2e64bd3b7392fd175b832d.jpg)

Figure 4-17: X2 Encoder Mode

# X4 Encoder Mode

This mode is similar to X1 Encoder Mode, except that the amount of counter value increases or decreases by four. Refer to Figure 4-18.

![| Time | Phase A | Phase B | CLK |\n|------|---------|---------|-----|\n| 0    | High    | Low     | Low |\n| 1    | High    | Low     | Low |\n| 2    | High    | Low     | Low |\n| 3    | High    | Low     | Low |\n| 4    | High    | Low     | Low |\n| 5    | High    | Low     | Low |\n| 6    | High    | Low     | Low |\n| 7    | High    | Low     | Low |\n| 8    | High    | Low     | Low |\n| 9    | High    | Low     | Low |\n| 8    | Medium  | Medium  | Medium |\n| 7    | Medium  | Medium  | Medium |\n| 6    | Medium  | Medium  | Medium |\n| 5    | Medium  | Medium  | Medium |\n| 4    | Medium  | Medium  | Medium |\n| 3    | Medium  | Medium  | Medium |\n| 2    | Medium  | Medium  | Medium |\n| 1    | Medium  | Medium  | Medium |\n| 0    | Medium  | Medium  | Medium |](.pci-9221-manual-5/6b321a8f986c78983fe081cc12e70fad3c50cc76f379d8033a1b30f45e1aacf0.jpg)

Figure 4-18: X4 Encoder Mode

# Phase Z

Each encoder mode may use a third phase, phase Z, that is also frequently used for the index phase. You may decide if the counter needs to be reloaded a specified value when phase Z is at a logic high level with phase A and B at a specific logic condition.

You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z. Otherwise, the counter does not reload.

In Figure 4-19, the reload phase is when the logic level of phase A is high, phase B is low, and phase Z is high in X1 Encoder Mode. In addition, reloading takes higher priority than increment or decrement of counter value. The reload occurs within one maximum CLK period after the reload phase becomes true. After the counter value is reloaded, the counter continues to count as before.

![| Phase   | Value |\n|---------|-------|\n| Phase A | 0     |\n| Phase B | 1     |\n| Phase Z | 2     |\n| CLK     | 3     |](.pci-9221-manual-5/e09c7d14f0f55230259f66781f919a964473d70a38add7e0d715cb59463111d5.jpg)

Figure 4-19: Phase Z

# Original Signal (ORGx)

Original Signal (ORG0/ORG1) is used with phase Z. With ORG enabled, a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle. When you use ORG signal if it is at a low level and phase Z is at a high level, then counter reload is ignored.

# 4.4 Trigger Sources

The PCI-9221 supports two trigger sources for analog input: software trigger and external digital trigger.

# Software-Trigger

This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function calls to begin data acquisition.

# External Digital Trigger

An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the PCI-9221's function I/O. You can set any DI line as external trigger pin. You may also easily program the trigger polarity via the ADLINK software drivers. Take note that the signal level of the external digital trigger signals should be TTL-compatible with a minimum 25 ns pulse.

![Based on the provided image, here is the description:\n\n**Labeled Blocks/Elements:**\n*   **Left Diagram:** A square pulse waveform. An arrow points upward along the rising edge of the signal. The text reads: 'Positive-edge trigger event occurs'.\n*   **Right Diagram:** A square pulse waveform. An arrow points downward along the falling edge of the signal. The text reads: 'Negative-edge trigger event occurs'.\n\n**Connections:**\n*   There are no connecting lines between the two diagrams; they are displayed separately side-by-side to illustrate the two distinct trigger types.](.pci-9221-manual-5/7afca3504c0ae2873b4ce54ee0c96861395c7485805234d7535597f1776febb6.jpg)

Figure 4-20: External Digital Trigger

# 5 Calibration

This chapter introduces the card calibration process to minimize AD measurement errors and DA output errors.

# 5.1 Loading Calibration Constants

The PCI-9221 is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware are written to the onboard EEPROM. TrimDACs firmware is the algorithm in the FPGA. Loading calibration constants is the process of loading the values of TrimDACs firmware stored in the onboard EEPROM. ADKLINK provides a software utility that automatically reads the calibration constants, if necessary.

There is a dedicated space for storing calibration constants in the EEPROM. In addition to the default bank of factory calibration constants, there is one user-utilization bank. This bank allows you to load the TrimDACs firmware values either from the original factory calibration or from a subsequently-performed calibration.

Because of the fact that measurements and outputs errors may vary depending on time and temperature, it is recommended that you calibrate the card when it is integrated in your computing environment. The auto-calibration function is presented in the following sections.

# 5.2 Auto-calibration

Through the PCI-9221 auto-calibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices.

The PCI-9221 comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software. The calibration constant is memorized after this measurement. We do not recommend adjustment of the onboard calibration reference except when an ultra-precision calibrator is available.

# 5.3 Saving Calibration Constants

Factory-calibrated constants are permanently stored in a bank of the onboard EEPROM and may not be modified. When you re-calibrate the device, the software stores the new constants in a user-configurable section of the EEPROM. To return a device to its initial factory calibration settings, the software can copy the factory calibrated constants to the user-configurable section of the EEPROM. When auto-calibration is completed, you can save the new calibration constants to the user-configurable banks in the EEPROM. The date and the temperature when you ran auto-calibration is saved with the calibration constants. You can store three sets of calibration constants according to three different environments and re-load the calibration constants later.

# NOTES

- Warm the card up for at least 15 minutes before initiating auto-calibration.
- Remove the cable before auto-calibrating the card since the DA outputs are changed during the process.

# Appendix: ADLINK TB-9221

The ADLINK TB-9221 is a termination board specially designed for the PCI-9221.

TB-9221 Layout
![106.8\n101.8\n85.15\n21.65\n5\n0\n16.25\n192\n89.2\n38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20\n19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1\nCON2\nU4\nCON1\nS1 2 3 4 5 6 7 8 9 10\nC25\nJP2 GP14-7 MODE SELECT\n1-2 GP1\n2-3 ENCODER\nJP1 GP10-3 MODE SELECT\n1-2 GP1\n2-3 ENCODER\n11 12 13 14 15 16 17 18 19 20\n10\n5\nR2(4x)\n150\n155](.pci-9221-manual-5/227a377f0b1374c6d7afa59022bc22b6574fed477e74ff1e52e3e3391fcd82e8.jpg)

CON1 Encoder Pin Assignments

<table><tr><td>Definition</td><td colspan="2">Pin #</td><td>Definition</td></tr><tr><td>Ext. 24V</td><td>1</td><td>11</td><td>NC</td></tr><tr><td>Ext. GND</td><td>2</td><td>12</td><td>NC</td></tr><tr><td>IEA0+</td><td>3</td><td>13</td><td>IEA1+</td></tr><tr><td>IEA0-</td><td>4</td><td>14</td><td>IEA1-</td></tr><tr><td>IEB0+</td><td>5</td><td>15</td><td>IEB1+</td></tr><tr><td>IEB0-</td><td>6</td><td>16</td><td>IEB1-</td></tr><tr><td>IEZ0+</td><td>7</td><td>17</td><td>IEZ1+</td></tr><tr><td>IEZ0-</td><td>8</td><td>18</td><td>IEZ1-</td></tr><tr><td>IORG0</td><td>9</td><td>19</td><td>IORG1</td></tr><tr><td>NC</td><td>10</td><td>20</td><td>NC</td></tr></table>

# NOTES

- CON1 connector is used for differential wiring while CON2 is used for single-ended wiring.
- An extra 24 V power (apply to pin 1 and 2 on CON1 connector) is required in differential encoder mode.
- In differential encoder input, logic high voltage must be between 4 V to 5.5 V, logic low voltage must be between 0 V to 0.8 V. Otherwise, the encoder input signal may not be recognized.
- Differential inputs support up to 2500 Vrms isolation voltage.

TB-9221 Jumper Settings

<table><tr><td rowspan="5">&lt;img src="images/4a4234e834d339bbc2c2353a8a4376643a14d3e61f3418572f3a9abcb6b4c17f.jpg"/&gt;&lt;img src="images/750c06aafefc079922fd4e38c8838b94f3b3fdea2e93d062b7def5ff47a4e3e7.jpg"/&gt;</td><td>Jumper</td><td>Description</td><td>Short Pins</td><td>Function</td></tr><tr><td rowspan="2">JP2</td><td rowspan="2">GPI4 – 7 Mode Select</td><td>1 – 2</td><td>GPI</td></tr><tr><td>2 – 3</td><td>Encoder</td></tr><tr><td rowspan="2">JP1</td><td rowspan="2">GPI0 – 3 Mode Select</td><td>1 – 2</td><td>GPI</td></tr><tr><td>2 – 3</td><td>Encoder</td></tr></table>

NOTE GPI indicates single-ended input mode. Encoder indicates differential input mode.

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/.
2. All ADLINK products come with a limited two-year warranty, one year for products bought in China:

The warranty period starts on the day the product is shipped from ADLINK's factory.
▶ Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for any loss of data.
▶ Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.
For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's guarantee in the following situations:

▶ Damage caused by not following instructions in the User's Manual.
▶ Damage caused by carelessness on the user's part during product transportation.
▶ Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
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▶ Other categories not protected under our warranty.

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5. To ensure the speed and quality of product repair, please download an RMA application form from our company website: http://rma.adlinktech.com/policy. Damaged products with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff: service@adlinktech.com.
[🔗 Link to the original document](.pci-9221-manual-5/pci-9221-manual-5.pdf)