# NuDAQ® PCI-9222 # NuDAQ® PCI-9223 16-bit High-Performance DAQ Card with Programmable Function I/O User's Manual Manual Rev. 2.00 Revision Date: April 24, 2008 Part No: 50-11237-1000 ![The image displays a black circle containing a white recycling symbol, also known as the Mobius loop. The symbol consists of three white arrows arranged in a triangular formation, chasing each other in a clockwise direction. Each arrow features three parallel lines on its tail section. There is no text visible in the image.](.pci-9222-9223-manual-10/0616806e77864fb8a7cc4b64181f68293db3a8e80207c44607968bc43f59a1df.jpg) Recycled Paper Copyright 2008 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Trademarks NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK TECHNOLOGY INC. Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Getting service Customer satisfaction is our top priority. Contact us should you require any service or assistance. # ADLINK TECHNOLOGY INC. Web Site http://www.adlinktech.com Sales & Service service@adlinktech.com Telephone No. +886-2-8226-5877 Fax No. +886-2-8226-5717 Mailing Address 9F No. 166 Jian Yi Road, Chungho City, Taipei Hsien 235, Taiwan, ROC # ADLINK TECHNOLOGY AMERICA, INC. Sales & Service info@adlinktech.com Toll-Free +1-866-4-ADLINK (235465) Fax No. +1-949-727-2099 Mailing Address 8900 Research Drive, Irvine, CA 92618, USA # ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales & Service emea@adlinktech.com Toll-Free +49-211-4955552 Fax No. +49-211-4955557 Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany # ADLINK TECHNOLOGY SINGAPORE PTE LTD Sales & Service singapore@adlinktech.com Telephone No. +65-6844-2261 Fax No. +65-6844-2263 Mailing Address 84 Genting Lane #07-02A, Cityneon Design Center, Singapore 349584 # ADLINK TECHNOLOGY INDIA LIAISON OFFICE Sales & Service india@adlinktech.com Telephone No. +91-80-57605817 Fax No. +91-80-26671806 Mailing Address No. 1357, Ground Floor, "Anupama", Aurobindo Marg JP Nagar (Ph-1) Bangalore - 560078 # ADLINK TECHNOLOGY KOREA Sales & Service korea@adlinktech.com Telephone No. +82-2-20570565 Fax No. +82-2-20570563 Mailing Address #402, Dongsung B/D, 60-12, Nonhyeon-Dong Gangnam-gu, Seoul, 135-010, South Korea # ADLINK TECHNOLOGY BEIJING Sales & Service market@adlinkchina.com.cn Telephone No. +86-10-5885-8666 Fax No. +86-10-5885-8625 Mailing Address Room 801, Building E, Yingchuangdongli Plaza, No.1 Shangdidonglu, Haidian District, Beijing, China # ADLINK TECHNOLOGY SHANGHAI Sales & Service market@adlinkchina.com.cn Telephone No. +86-21-6495-5210 Fax No. +86-21-5450-0414 Mailing Address Floor 4, Bldg. 39, Caoheting Science and Technology Park, No.333 Qinjiang Road, Shanghai, China # ADLINK TECHNOLOGY SHENZHEN Sales & Service market@adlinkchina.com.cn Telephone No. +86-755-2643-4858 Fax No. +86-755-2664-6353 Mailing Address C Block, 2nd Floor, Building A1, Cyber-tech Zone, Gaoxin Ave. 7.S, High-tech Industrial Park S., Nanshan District, Shenzhen, Guangdong Province, China # Using this manual # 1.1 Audience and scope This manual guides you when using ADLINK high-performance data acquisition PCI card. The card's hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming. # 1.2 How this manual is organized This manual is organized as follows: Chapter 1 Introduction: This chapter introduces the ADLINK NuDAQ PCI-9222 and NuDAQ PCI-9223 cards including their features, specifications, software support information, and package contents. Chapter 2 Hardware Information: This chapter presents the card's layout, connector pin assignment, signal descriptions, and analog input signal connection. Chapter 3 Installation: This part describes the PCI-9222/PCI-9223 installation and configuration. Chapter 4 Operation Theory: The operation theory of the PCI-9222/PCI-9223 card functions are discussed in this chapter. These include A/D conversion, D/A conversion, programmable function I/O, application function I/O, digital waveform acquisition, isolation encoder, and trigger sources. Chapter 5 Calibration: The chapter offers information on how to calibrate the PCI-9222/PCI-9223 for accurate data acquisition and measurement. Warranty Policy: This presents the ADLINK Warranty Policy terms and coverages. # 1.3 Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption, and others when trying to complete a particular task. # Table of Contents # List of Tables...... iii # List of Figures ...... iv # 1 Introduction ...... 1 1.1 Features.... 2 1.2 Applications 2 1.3 Specifications.... 3 1.4 Unpacking Checklist 8 1.5 Software Support 8 Driver Support for Windows 9 # 2 Hardware Information 13 2.1 Card Layout 13 2.2 Connector Pin Assignment 13 CN1 Pin Assignment 14 CN2 Pin Assignment 16 CN1/CN2 Signal Descriptions 17 SSI Connector Pin Assignment 18 SSI Connector Signal Description 19 2.3 Analog Input Signal Connection 20 Types of Signal Sources 20 Input Configurations 21 # 3 Installation 25 3.1 Before You Proceed 25 3.2 Installing the Card.... 25 3.3 Configuring the Card.... 26 Configuration 26 Troubleshooting 26 # 4 Operation Theory 27 4.1 Block Diagram 27 4.2 A/D Conversion.... 28 AI Data Format 29 Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) 29 Continuous Acquisition (Scanning) Mode .... 30 Trigger Modes 33 Bus-mastering DMA Data Transfer 35 4.3 D/A Conversion.... 38 Bipolar Output Modes 38 Software Update 38 Waveform Generation 38 4.4 Programmable Function I/O 47 TTL DI/DO 47 General Purpose Timer/Counter 48 Basic Timer/Counter Functions 48 General Purpose Timer/Counter Modes 49 Digital Waveform Acquisition and Generation 55 4.5 Isolation Encoder 57 4.6 Trigger Sources 62 Software Trigger 62 External Digital Trigger 62 5 Calibration 63 5.1 Loading Calibration Constants.... 63 5.2 Auto-calibration 63 5.3 Saving Calibration Constants.... 64 Warranty Policy 65 # List of Tables Table 2-1: CN1 Pin Assignment for PCI-9222 14 Table 2-2: CN1 Pin Assignment for PCI-9223 15 Table 2-3: CN2 Pin Assignment for PCI-9222/PCI-9223 ..... 16 Table 2-4: CN1/CN2 Signal Description 17 Table 2-5: SSI Connector Pin Assignment 18 Table 2-6: SSI Connector Signal Description 19 Table 4-1: Bipolar Analog Input Range and Output Digital Code 29 Table 4-2: Bipolar Analog Input Range and Output Digital Code 29 Table 4-3: Bipolar Output Codes 38 Table 4-4: Summary of Counters for Waveform Generation ... 40 Table 4-5: TTL DIO Pins in CN1 47 Table 4-6: Timer/Counter Mode Pins in CN1 48 Table 4-7: Encoder Pins in CN2 57 # List of Figures Figure 1-1: ADLINK Software Support Overview 9 Figure 1-2: DAQPilot Main Interface 9 Figure 1-3: DAQMaster Device Manager.... 10 Figure 1-4: Legacy Software Support Overview ...... 11 Figure 2-1: PCI-9222/PCI-9223 Layout.... 13 Figure 2-2: Floating Source and RSE Input Connections ...... 21 Figure 2-3: Ground-referenced Sources and NRSE Input Connections.... 22 Figure 2-4: Ground-referenced Source and Differential Input.... 22 Figure 2-5: Floating Source and Differential Input 23 Figure 4-1: PCI-9222/PCI-9223 Block Diagram 27 Figure 4-2: PCI-9222/PCI-9223 AI Circuitry.... 28 Figure 4-3: Continuous A/D Conversion Clock Source Block Diagram 30 Figure 4-4: Scan Timing.... 31 Figure 4-5: Post Trigger without Retrigger 33 Figure 4-6: Post Trigger with Retrigger 34 Figure 4-7: Gated Trigger with Finite Scan Acquisition.... 35 Figure 4-8: Scatter-gather DMA for Data Transfer.... 36 Figure 4-9: FIFO Data In/Out Structure.... 39 Figure 4-10: Waveform Generation for Three Channels Update. 39 Figure 4-11: Waveform Generation Clock Source Selection ..... 40 Figure 4-12: Typical D/A Timing of Waveform Generation ..... 41 Figure 4-13: Post-Trigger Generation 42 Figure 4-14: Delay-Trigger Generation 43 Figure 4-15: Post-Trigger with Retrigger Generation 44 Figure 4-16: Finite Iterative Waveform Generation with Post-trigger 45 Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger 46 Figure 4-18: Mode 1 Operation.... 49 Figure 4-19: Mode 2 Operation....50 Figure 4-20: Mode 3 Operation....51 Figure 4-21: Mode 4 Operation....51 Figure 4-22: Mode 5 Operation 52 Figure 4-23: Mode 6 Operation....52 Figure 4-24: Mode 7 Operation.... 53 Figure 4-25: Mode 8 Operation.... 53 Figure 4-26: Mode 9 Operation.... 54 Figure 4-27: Mode 10 Operation.... 54 Figure 4-28: Digital Waveform Acquisition Operation 55 Figure 4-29: Digital Waveform Generation Operation.... 56 Figure 4-30: Encoder Isolation Input Module 57 Figure 4-31: Encoder OGRx Input 58 Figure 4-32: CW/CCW Encoder Timing 58 Figure 4-33: X1 Encoder Mode.... 59 Figure 4-34: X2 Encoder Mode.... 59 Figure 4-35: X4 Encoder Mode.... 60 Figure 4-36: Phase Z 61 Figure 4-37: External Digital Trigger 62 # 1 Introduction The NuDAQ PCI-9222 (16-CH, 250 kS/s) and NuDAQ PCI-9223 (32-CH, 500 kS/s) are 16-bit high-performance DAQ cards with eight different input ranges. These cards also features a 2-CH, 16-bit analog output capable of up to 1 MS/s update rate, a 2-CH encoder input, and a programmable function I/O. The software-programmable function I/O supports a variety of applications including TTL digital I/O, high-speed DIO, general-purpose timer/counter, and PWM output. These cards' analog input, analog output, and function I/O are capable of functioning simultaneously at full speed. If you need additional channels, you can synchronize these cards using the onboard SSI (System Synchronization Interface) bus. Suitable for mixed-signal tests, laboratory research, and factory automation, the PCI-9222 and PCI-9223 provide the best single-board solution with optimum integration capability of multiple tasks at an affordable price. # 1.1 Features The PCI-9222/PCI-9223 comes with the following features: ▶ Supports a 32-bit 3.3 V or 5 V PCI bus ▶ PCI 2.3-compliant ▶ Up to 32-CH single-ended or 16-CH differential analog input ▶ Up to 500 kS/s sampling rate ▶ Programmable analog input gains of 1, 2, 4, 5, 8, 10, 20, 40 ▶ 2-CH, 16-bit simultaneous analog output supports update rate of up to 1 MS/s ▶ Programmable function I/O supports the following modes: ▷ 16-CH TTL DI and 16-CH TTL DO ▷ 2 MHz 32-CH high-speed DIO ▷ 4-CH 32-bit 80 MHz general-purpose timer/counter ▷ 4-CH PWM outputs ▶ 2-CH 4 MHz dedicated encoder inputs, supporting AB phase, and CW/CCW ▶ Four DMA channels for A/D, D/A, and high-speed DIO ▶ External digital trigger for A/D, D/A, and high-speed DIO ▶ Multiple card synchronization through SSI (System Synchronization Interface) ▶ Auto-calibration feature # 1.2 Applications The PCI-9222 and PCI-9223 are ideal for these applications: ▶ Automotive testing ▶ Cable testing ▶ Transient signal measurement ▶ Waveform generation ▶ ATE ▶ Laboratory automation ▶ Biotech measurement ▶ Motor control feedback # 1.3 Specifications Analog Input (AI)
HardwarePCI-9222PCI-9223
Number of channels (programmable)1632
A/D converterAD7685 or equivalentAD7686 or equivalent
Maximum sampling rateSingle-channel:Scanning:250 K samples/s100 K samples/s500 K samples/s200 K samples/s
Resolution16-bit
Input couplingDC
Programmable input range±10 V, ±5 V, ±2.5 V, ±2 V, ±1.25 V, ±1 V, ±500 mV, ±250 mV
Operational common mode voltage range±8 V
Overvoltage protectionPower on:Power off:Continuous ±30 VContinuous ±30 VContinuous ±30 VContinuous ±30 V
FIFO buffer size1K samples
Data transfersProgrammed I/OBus-mastering DMA with scatter/gather
Channel Gain Queue configuration size32 words
Input impedance1000G/150pF
Trigger modePost-trigger with retrigger, Gated trigger
Time-base sourceInternal, 80 Mhz
Electrical
Function23°C (±5°C)
Offset error±0.5 mV
Gain error±2 mV
-3dB small signal bandwidth11.5 Mhz
System noise20.5 mVrms
1% THD large signal bandwidth
CMRR393.5 dB
Spurious-free dynamic range (SFDR)95 dB88 dB
Signal-to-noise and distortion ratio (SINAD)86 dB84 dB
Total harmonic distortion (THD)-94 dB-90 dB
Signal-to-noise ration (SNR)87 dB86 dB
Effective number of bits (ENOB)13.913.5
Settling time to full-scale stepMultiple channelsMultiple ranges2 μs to 0.1% error4 μs to 0.01% error
Analog Output (AO) Hardware
Function23°C (±5°C)
Number of channels2
D/A converterDAC8812 or equivalent
Maximum update range1M sample/s (static)
Resolution16-bit
FIFO size512 samples, 2-CH sharing
Data transfersProgrammed I/O, DMA
Output range±10 V
Output couplingDC
Output impedance0.010 (maximum)
ProtectionNone
StabilityAny passive load, up to 1500pF
Power-on stateAround 0 V, steady-state
Electrical
Offset errorBefore calibration:After calibration:±35 mV typical±1 mV typical
Gain errorBefore calibration:After calibration:±1% of output max0.001% of output max
Slew rate20 V/μs
Rise time0.67 μs
Fall time0.7 μs
Settling time to 1% output error3 μs
DNL0.7 LSB
INL1 LSB
Output driving±5 mA (maximum)
Function I/O
Number of channels16-CH programmable function DI16-CH programmable function DO
CompatibilityTTL (single-ended)(supports 3.3 V and 5 V DI; 3.3 V DO)
Input voltageLogic low: $\text{VIL} = 0.8 \text{ V max}$ ; $\text{IIL} = 0.2 \text{ mA max}$ Logic high: $\text{VIH} = 2.0 \text{ V min}$ ; $\text{IIH} = 0.2 \text{ mA max}$
Output voltageLogic low: $\text{VOL} = 0.5 \text{ V max}$ ; $\text{IOL} = 10 \text{ mA max}$ Logic high: $\text{VOH} = 2.6 \text{ V min}$ ; $\text{IIH} = 10 \text{ mA max}$
Supported modes416-CH TTL DI and16-CH TTL DO4-CH 32-bit general-purpose timer/countersClock source: Internal or ExternalMax. source frequency: Internal 80 MHzExternal 10 MHz4-CH PWM outputsDuty cycle5:1-99%Modulation frequency: 20 MHz to 0.005 HzExternal digital trigger in and outExternal analog input convert sourceExternal analog output convert sourceDigital waveform acquisition and generation
DI acquisition FIFO size512 samples
DO acquisition FIFO size512 samples
Data transfersProgrammed I/O, DMA
Encoder Input (EI)
Number of channels2
Max. Input frequency4 MHz
Encoder count $(2^{31}-1)$ bits
Photo isolatorNEC PS9115 or equivalent
Encoder modesCW/CCWX1 AB phase encoderX2 AB phase encoderX4 AB phase encoder
Physical, Power, and Operating Environment
InterfacePCI 2.3-compliant
Dimension120 mm x 87 mm
I/O connector2 x 68-pin female VHDCI connectors
Power requirement (typical)• +5 VDC: 1.2A• +12 VDC: 760 mA• -12 VDC: 50 mA
Operating environment• Ambient temperature: 0°C to 45°C• Relative humidity: 10% to 90%, non-condensing
Storage environment• Ambient temperature: -20°C to 80°C• Relative humidity: 5% to 95%, non-condensing
Specifications are subject to change without notice. 1. -3dB small signal bandwidth: (Typical, 25°C)
Input rangeBandwidth(-3dB)
±10 V1500 kHz
±5 V1400 kHz
±2.5 V1400 kHz
±2 V1400 kHz
±1.25 V1400 kHz
±1 V1400 kHz
±500 mV1350 kHz
±250 mV1250 kHz
2. System Noise (LSBrms, including Quantization, Typical, 25°C)
Input RangeSystem Noise
±10 V0.78 LSBrms
±5 V0.80 LSBrms
±2.5 V0.98 LSBrms
±2 V0.96 LSBrms
±1.25 V0.77 LSBrms
±1 V0.81 LSBrms
±500 mV0.99 LSBrms
±250 mV0.96 LSBrms
3. CMRR (DC to 60 Hz, Typical)
Input RangeSystem Noise
±10 V93.5 dB
±5 V96.3 dB
±2.5 V103 dB
±2 V104.2 dB
±1.25 V106 dB
±1 V106.2 dB
±0.5 V110 dB
±0.25 V118 dB
4. Only one of the following modes can be selected. These modes can not work at the same time. Refer to section 4.3 and 4.4. 5. Refer to Chapter 4. # 1.4 Unpacking Checklist Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package. ▶ PCI-9222 or PCI-9223 multi-function DAQ card ▶ ADLINK All-in-One CD ▶ User's manual If any of the items is damaged or missing, contact your dealer immediately. # CAUTION The card must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the card. Wear a grounded wrist strap when servicing.Software Support # 1.5 Software Support ADLINK provides comprehensive software drivers and packages to suit various user approach to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environment such as LabVIEW $^{®}$ and MATLAB $^{®}$ . ADLINK also provides ActiveX component ware for measurement and SCADA/HMI, and breakthrough proprietary software applications. All software options are included in the ADLINK All-in-One CD. ![This diagram illustrates a software architecture for ADLINK data acquisition (DAQ) hardware, organized in horizontal layers.\n\n**Top Layer (Applications & Tools):**\n* **Left:** A blue block labeled **ADE** containing 'VB.NET/C#.NET/VC++/VB/Delphi/BCB etc.'\n* **Center:** Two green blocks labeled **LabVIEW** and **MATLAB**.\n* **Right:** A red block labeled **DAQMaster** containing the text 'DAQMaster Configuration based System Manager For ADLINK DAQ Devices'.\n\n**Middle Layer (Libraries, Drivers, & Toolboxes):**\nThis section is divided into columns.\n* **Left Column (Blue Background):**\n * **Library Row:** Contains two boxes:\n * 'DAQBench PCI5-D2K/-WD-OCX ActiveX Control'\n * 'DAQPilot ActiveX Control & .NET Assembly' (with a red ADLINK logo)\n * **Driver Row:** Contains two boxes:\n * 'D2K/-PCI5/-WD-DASK'\n * 'DAQPilot Drivers (Task-oriented)' (with a red ADLINK logo)\n * **Connections:** Two downward blue arrows connect the library boxes to their corresponding driver boxes below:\n * From 'DAQBench...' to 'D2K/-PCI5/-WD-DASK'.\n * From 'DAQPilot...' to 'DAQPilot Drivers...'.\n* **Center Column (Green Background):**\n * Located below LabVIEW: **ADLINK DAQ-VIEWPnP VI Library**.\n * Located below MATLAB: **ADLINK DAQ-MTLB DAQ Toolbox**.\n* **Right Column (Red Background):** The **DAQMaster** block continues vertically down to this layer.\n\n**Operating System Layer:**\n* **Left:** Label **Operating System** next to a box reading 'Windows 98/NT/2K/XP/Vista x86'.\n* **Right:** A box reading 'Windows XP x64/Server 2003 x64/Vista x64' (with a red ADLINK logo).\n\n**Bottom Layer (Hardware):**\n* A full-width blue block labeled **ADLINK DAQ Cards**.\n* Text inside: '(General-Purpose DAQ, Digital I/O, Analog Output, Performance DAQ, PXI, High-Speed Digital I/O, Digitizer)'.](.pci-9222-9223-manual-10/59c5998892056b2c2fb4e8213b2faee74634543f3b32d80c0facac302e21d1a0.jpg) Figure 1-1: ADLINK Software Support Overview # Driver Support for Windows # DAQPilot DAQPilot is a driver and SDK with a graphics-driven interface for various application development environments. DAQPilot comes as ADLINK's commitment to provide full support to its comprehensive line of data acquisition products and is designed for the novice to the most experienced programmer. ![DAQPilot\nANALOG INPUT\nANALOG OUTPUT\nDIGITAL INPUT\nDIGITAL OUTPUT\nTIMER/CTR\nYour pilot to\ndata acquisition world\nADLINK\nTECHNOLOGY INC.\nCopyright © 2007 ADLINK Technology Inc. All Rights Reserved.](.pci-9222-9223-manual-10/cfbd4918400d84624022fe7e4fdd9fb97c3713d380ae07c2a2fd391b6c5f1e9c.jpg) Figure 1-2: DAQPilot Main Interface As a task-oriented DAQ driver, SDK and wizard for Windows systems, DAQPilot helps you shorten the development time while accelerating your learning curve for data acquisition programming. You can download and install DAQPilot at http://www.adlinktech.com/TM/DAQPilot.html # DAQMaster The ADLINK DAQMaster is a smart device manager that opens up access to ADLINK data acquisition and test and measurement products. DAQMaster delivers all-in-one configurations and provides you with a full support matrix to properly and conveniently configure ADLINK Test and Measurement products. ![DAQMaster\nDevice Manager\nSoftware Manager\nTask Manager\nProducts\nADLINK Test & Measurement\nDevice Overview Support Matrix\n# Type Model Form Factor Driver ComponentWare\n1 Analog Output Modules PCI LPCI sPCI PCIe PS0 Windows Linux DAQ/Bench ComponentWare\n2 6208/6216 v v v PGS-DASK POS-DASK v POS-OCX\n3 6308 v v v PGS-DASK POS-DASK v POS-OCX\n4 7200 v v v PGS-DASK POS-DASK v POS-OCX\n5 7224 v v v PGS-DASK POS-DASK v POS-OCX\n6 7230 v v v PGS-DASK POS-DASK v POS-OCX\n7 7233 v v v PGS-DASK POS-DASK v POS-OCX\n8 7234 v v v PGS-DASK POS-DASK v POS-OCX\n9 7248 v v v PGS-DASK POS-DASK v POS-OCX\n10 7249 v v v PGS-DASK POS-DASK v POS-OCX\n11 7250 v v v PGS-DASK POS-DASK v POS-OCX\n12 7252 v v v PGS-DASK POS-DASK v\n13 Digital I/O Modules PGS-DASK PGS-DASK PGS-OCX\n14 Digital I/O Modules PGS-DASK PGS-DASK PGS-OCX\n15 7260 v v PGS-DASK POS-DASK v\n16 7266 v v PGS-DASK POS-DASK v POS-OCX\n17 7300 v v PGS-DASK POS-DASK v POS-OCX\n18 7432 v v PGS-DASK POS-DASK v POS-OCX\n19 7433 v v PGS-DASK POS-DASK v POS-OCX\n20 7434 v v PGS-DASK POS-DASK v\n21 7442 v PGS-DASK POS-DASK v\n22 7443 v PGS-DASK POS-DASK v\n23 7444 v PGS-DASK POS-DASK v\n24 7452 v PGS-DASK POS-DASK v\n25 7348 v PGS-DASK POS-DASK v POS-OCX\n26 7396 v PGS-DASK POS-DASK v POS-OCX\n27 Digitizer Modules POS-DASK PGS-DASK PGS-OCX\n28 9810/9812 v VHD-DASK VHD-DASK VHD-OCX\n29 Product Support Matrix Tied Party Support & Application\nDevice Manager(Installed) Drag the selected device item to subfunction button to launch\nCalibrates DAQ-2000 series modules](.pci-9222-9223-manual-10/17a80449394a7fe6b732f583b9424c7e61b6e6250d1d5344d5a24b2b4c60b821.jpg) Figure 1-3: DAQMaster Device Manager As a configuration-based device manager for ADLINK DAQ cards, DAQMaster enables you to manage ADLINK devices and interfaces, install and upgrade software applications, and manage ADLINK DAQPilot tasks. # PCIS-DASK (Legacy Drivers and Support) PCIS-DASK is composed of advanced 32-bit kernel drivers for customized DAQ application development. PCIS-DASK enables you to perform detailed operations and achieve superior performance and reliability from your data acquisition system. DASK kernel drivers now support the revolutionary Windows Vista® OS. ![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Labeled Blocks**\n\n* **Far Left Column (Programming Languages):**\n * Delphi\n * BCB\n * VC++\n * VB\n * VB.NET\n * C#\n\n* **User Mode Column:**\n * User Mode\n * PCIS-DASK (Blue oval)\n * D2K-DASK (Blue oval)\n * WD-DASK (Blue oval)\n\n* **Kernel Mode Column:**\n * Kernel Mode\n * System Service (Vertical blue bar)\n * Process Structure\n * Object Manager\n * Memory Manager\n * Configuration Manager\n * I/O Manager\n * DASK Kernel Driver (.sys) (Red text)\n * Executive Support\n * Plug and Pay\n * Power Manager\n * File System\n * Lowest-level Driver\n\n* **Hardware Layer Column:**\n * Hardware Abstraction Layer (Vertical blue bar)\n * Hardware (Vertical blue bar)\n\n**Connections**\n\n* **User Mode to Kernel Mode:** Orange arrows originate from 'PCIS-DASK', 'D2K-DASK', and 'WD-DASK' and point rightwards into the 'System Service' block.\n* **Hardware Layer to Hardware:** Two orange arrows originate from the 'Hardware Abstraction Layer' block and point rightwards into the 'Hardware' block (one aligned with the upper section, one aligned with the lower section).](.pci-9222-9223-manual-10/f8341b9ace44d3a077df9aa02a8683f8376a3c83b20bc537a9c3451e57b84078.jpg) Figure 1-4: Legacy Software Support Overview # NOTE ADLINK strongly recommends installing DAQPilot and avoid using legacy DASK drivers. For current DASK driver users or those who do not have Internet access, we offer an installation CD. Contact your ADLINK distributor for details. PCIS-DASK drivers prepare legacy Windows users for Windows Vista and 64-bit editions of Windows. PCIS-DASK comes with the following features: ▶ Supports Windows Vista 32-bit or 64-bit editions ▶ Supports AMD64 and Intel x86-64 architectures ▶ Digitally-signed for Windows Vista 64-bit edition ▶ Utilizes WOW64 subsystem to ensure that 32-bit applications run normally on 64-bit editions of Windows XP, Windows 2003 Server, and Windows Vista without modification For more information about Windows Vista support, visit http://www.adlinktech.com/TM/VistaSupport.html, or view the user's guide included in the ADLINK All-in-one CD. # 2 Hardware Information This chapter provides information on the PCI-9222/PCI-9223 layout, connectors, and pin assignments. # 2.1 Card Layout Figure 2-1 shows the PCI-9222/PCI-9223 board layout and dimensions. ![CN1\nCN2\n100.3\n42.95\n76.1\n102.46\n106.4\n70.22\n98.42\n106.68](.pci-9222-9223-manual-10/b6d68f7fdf1eda94f03a57dc43a45196783291a12a8e4d18101cab19412e903b.jpg) Figure 2-1: PCI-9222/PCI-9223 Layout # 2.2 Connector Pin Assignment The PCI-9222/PCI-9223 card is equipped with two VHDCI 68-pin connectors. CN1 is for analog input/output, while CN2 is for digital input/output and encoder functions. These cards also come with an SSI (System Synchronous Interface) connector. Attached a 20-pin ribbon connector (male) to the SSI when synchronizing the PCI-9222/PCI-9223 card with other cards. CN1 Pin Assignment
DefinitionPin #Definition
AI0(AIH0)3468AI8(AIL0)
AI1(AIH1)3367AI9(AIL1)
AI2(AIH2)3266AI10(AIL2)
AI3(AIH3)3165AI11(AIL3)
AI4(AIH4)3064AI12(AIL4)
AI5(AIH5)2963AI13(AIL5)
AI6(AIH6)2862AI14(AIL6)
AI7(AIH7)2761AI15(AIL7)
AGND2660AISENSE
NC2559NC
NC2458NC
NC2357NC
NC2256NC
NC2155NC
NC2054NC
NC1953NC
NC1852NC
AGND1751AGND
AO01650AGND
AO11549AGND
NC1448NC
NC1347NC
NC1246NC
NC1145NC
NC1044NC
NC943NC
NC842NC
NC741NC
NC640NC
NC539NC
NC438NC
NC337NC
NC236NC
NC135NC
Table 2-1: CN1 Pin Assignment for PCI-9222
DefinitionPin #Definition
AI0(AIH0)3468AI16(AIL0)
AI1(AIH1)3367AI17(AIL1)
AI2(AIH2)3266AI18(AIL2)
AI3(AIH3)3165AI19(AIL3)
AI4(AIH4)3064AI20(AIL4)
AI5(AIH5)2963AI21(AIL5)
AI6(AIH6)2862AI22(AIL6)
AI7(AIH7)2761AI23(AIL7)
AGND2660AISENSE
AI8(AIH8)2559AI24(AIL8)
AI9(AIH9)2458AI25(AIL9)
AI10(AIH10)2357AI26(AIL10)
AI11(AIH11)2256AI27(AIL11)
AI12(AIH12)2155AI28(AIL12)
AI13(AIH13)2054AI29(AIL13)
AI14(AIH14)1953AI30(AIL14)
AI15(AIH15)1852AI31(AIL15)
AGND1751AGND
AO01650AGND
AO11549AGND
NC1448NC
NC1347NC
NC1246NC
NC1145NC
NC1044NC
NC943NC
NC842NC
NC741NC
NC640NC
NC539NC
NC438NC
NC337NC
NC236NC
NC135NC
Table 2-2: CN1 Pin Assignment for PCI-9223 CN2 Pin Assignment
DefinitionPin #Definition
GPI0/GPTC_CLK03468GPI8/GPTC_CLK2
GPI1/GPTC_UD03367GPI9/GPTC_UD2
GPI2/GPTC_GATE03266GPI10/GPTC_GATE2
GPI3/GPTC_AUX03165GPI11/GPTC_AUX2
GPI4/GPTC_CLK13064GPI12/GPTC_CLK3
GPI5/GPTC_UD12963GPI13/GPTC_UD3
GPI6/GPTC_GATE12862GPI14/GPTC_GATE3
GPI7/GPTC_AUX12761GPI15/GPTC_AUX3
DGND2660DGND
GPO0/GPTC_OUT02559GPO8
GPO1/GPTC_OUT12458GPO9
GPO2/GPTC_OUT22357GPO10
GPO3/GPTC_OUT32256GPO11
GPO42155GPO12
GPO52054GPO13
GPO61953GPO14
GPO71852GPO15
DGND1751DGND
DGND1650DGND
DGND1549DGND
+5Vout1448DGND
NC1347NC
NC1246NC
NC1145NC
NC1044NC
E24V943NC
EGND842NC
IEA0+741IEA1+
IEA0-640IEA1-
IEB0+539IEB1+
IEB0-438IEB1-
IEZ0+337IEZ1+
IEZ0-236IEZ1-
IORG0135IORG1
Table 2-3: CN2 Pin Assignment for PCI-9222/PCI-9223 # CN1/CN2 Signal Descriptions Below are the signal descriptions for the CN1/CN2 connectors:
Signal NameReferenceDirectionDescription
AIGND——Analog input ground. All three ground references (AIGND, AOGND, and DGND) are connected onboard.
AI<0..15> (16-CH)AIGNDInputPCI-9222 Analog Input Channels 0~15. Each channel pair, AI(i=0..7), can be configured as either two single-ended inputs or one differential input pair (marked as AIH<0..7> and AIL<0..7>).
AI<0..31> (32-CH)AIGNDInputPCI-9223 Analog Input Channels 0~31. Each channel pair, AI(i=0..15) can be configured as either two single-ended inputs or one differential input pair (marked as AIH<0..15> and AIL<0..15>).
AISENSEAIGNDInputAnalog Input Sense. This pin serves as reference for any channels AI<0..63> in NRSE input configuration.
AO<0, 1>AOGNDOutputAnalog output channel <0, 1>
AOGND--Analog output ground
GPI<0..15>DGNDInputFunction input <0..15>. See section 4.3.
GPO<0..15>DGNDOutputFunction output <0..15>. See section 4.3.
EA<0, 1>Encoder GroundInputEncoder A Phase
EB<0, 1>Encoder GroundInputEncoder B Phase
Table 2-4: CN1/CN2 Signal Description
Signal NameReferenceDirectionDescription
EZ<0, 1>Encoder GroundInputEncoder Z Phase
ORG<0, 1>Encoder GroundInputEncoder Original Signal
Encoder +24VEncoder GroundInputEncoder voltage input pin
GPTC_CLK<0, 3>DGNDInputGPTC<0, 3> clock source
GPTC_GATE<0, 3>DGNDInputGPTC<0, 3> gate
GPTC_OUT<0, 3>DGNDOutputGPTC<0, 3> output
GPTC_UD<0, 3>DGNDInputGPTC<0, 3> up/down
NCNCNCNo connection
Table 2-4: CN1/CN2 Signal Description SSI Connector Pin Assignment
DefinitionPin#Definition
RESERVED12DGND
SSI_ADCONV34DGND
SSI_DAWR56DGND
RESERVED78DGND
RESERVED910DGND
SSI_AD_TRIG1112DGND
SSI_DA_TRIG1314DGND
RESERVED1516DGND
RESERVED1718DGND
RESERVED1920DGND
Table 2-5: SSI Connector Pin Assignment SSI Connector Signal Description
Signal NameSettingDirectionDescription
SSI_ADCONVMasterOutputSends out the ADCONV
SlaveInputAccepts the SSI_ADCONV to replace the internal ADCONV signal
SSI_AD_TRIGMasterOutputSends the internal AD_TRIG out
SlaveInputAccepts the SSI_AD_TRIG as the digital trigger signal
SSI_DAWRMasterOutputSends the DAWR out
SlaveInputAccepts the SSI_DAWR to replace the internal DAWR signal
SSI_DA_TRIGMasterOutputSends the DA_TRIG out
SlaveInputAccepts the SSI_DA_TRIG as the digital trigger signal
Table 2-6: SSI Connector Signal Description # 2.3 Analog Input Signal Connection The PCI-9222 provides up to 16 single-ended or 8 differential analog input channels, while the PCI-9223 offers up to 32 single-ended or 16 differential analog input channels. You can fill the Channel Gain Queue to get the desired input signal type combination. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and obtain a more accurate measurement from the A/D conversion, it is important to understand the type of signal source and how to choose the analog input modes: Referenced Single-Ended (RSE), Non-Referenced Single-Ended (NRSE), and Differential Input (DIFF). # Types of Signal Sources # Floating Signal Sources A floating signal source means it is not connected in any way to the building's ground system. A device with an isolated output is a floating signal source. This includes optical isolator outputs, transformer outputs, and thermocouples. # Ground-Referenced Signal Sources A ground-referenced signal means it is connected in some way to the building's ground system. That is, the signal source is already connected to a common ground point with respect to the PCI-9222/PCI-9223, assuming that the computer is plugged into the same power system. Non-isolated outputs of instruments and devices that plug into the building's power systems are ground-referenced signal sources. # Input Configurations # Single-ended Connections A single-ended connection is used when the analog input signal is referenced to a ground that can be shared with other analog input signals. There are two types of single-ended connections: RSE and NRSE configuration. In RSE configuration, the PCI-9222/PCI-9223 card provides the grounding point for external analog input signals and is suitable for floating signal sources. In NRSE configuration, the card does not provide the grounding point. The external analog input signal provides its own reference grounding point and is suitable for ground-referenced signals. # Referenced Single-ended (RSE) Mode In referenced single-ended mode, all the input signals are connected to the ground provided by the PCI-9222/PCI-9223. This mode is suitable for connections with floating signal sources. Figure 2-2 shows an illustration of this mode. Take note that when two or more floating sources are connected, these sources will be referenced to the same common ground. ![This block diagram illustrates a signal acquisition and conditioning circuit.\n\n**Labeled Blocks and Text:**\n* **Floating Signal Source**: A label on the left indicating the two AC voltage sources (circles with sine waves).\n* **V1**: Label under the left voltage source.\n* **V2**: Label under the right voltage source.\n* **n = 0, ..., 63**: Text at the bottom left indicating the channel range.\n* **CN1 Input Multiplexer**: Label above the central rectangular block.\n* **AIn**: Label next to the top input pin of the multiplexer.\n* **AIGND**: Label next to the bottom input pin of the multiplexer.\n* **Instrumentation Amplifier**: Label above the triangular component.\n* **+**: Label for the positive input of the amplifier.\n* **-**: Label for the negative input of the amplifier.\n* **To A/D**: Text to the right of the top output line.\n* **Converter**: Text to the right of the bottom output line.\n\n**Connections:**\n* **Floating Signal Source**:\n * The top terminal of source **V1** connects to the top input pin labeled **AIn**.\n * The top terminal of source **V2** connects to the second input pin of the multiplexer.\n * The bottom terminals of both **V1** and **V2** connect to a common horizontal ground rail.\n* **CN1 Input Multiplexer**:\n * To its left is a vertical column of input pins. Besides the connections from **V1** and **V2**, there are five additional input lines shown.\n * The bottom pin is labeled **AIGND** and connects to the common horizontal ground rail.\n * The output of the multiplexer (right side) connects to the positive input (**+**) of the amplifier.\n* **Instrumentation Amplifier**:\n * The positive input (**+**) receives the signal from the multiplexer.\n * The negative input (**-**) connects to the common horizontal ground rail.\n * The output of the amplifier goes to the right, forming the top output line.\n* **Output**:\n * The top output line is labeled **+** and points toward '**To A/D**'.\n * The bottom output line is the continuation of the common ground rail, labeled **-**, and points toward '**Converter**'. Together, these lines go 'To A/D Converter'.](.pci-9222-9223-manual-10/e6a7e9732eb3d62acce3816a919a9a12591bdfa960bfbe4be0ef74c33fb124f5.jpg) Figure 2-2: Floating Source and RSE Input Connections # Non-Referenced Single-Ended (NRSE) Mode To measure ground-referenced signal sources, which are connected to the same ground point, you can connect the signals in NRSE mode. Figure 2-3 illustrates the connection. The signal's local ground reference is connected to the negative input of the instrumentation amplifier (AISENSE pin on CN1 connector), and the common-mode ground potential between signal ground and the onboard ground will be rejected by the instrumentation amplifier. ![Based on the provided image, here is an accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n* **Ground-Referenced Signal Source** (Text group)\n* **V1** (AC voltage source)\n* **V2** (AC voltage source)\n* **Common-mode noise & Ground potential** (Text group)\n* **Vcm** (DC voltage source)\n* Vertical bar with terminals labeled **AIn** (top) and **AISENSE** (bottom)\n* **Input Multiplexer** (Rectangle)\n* **Instrumentation Amplifier** (Triangle)\n* **To A/D Converter** (Text)\n\n**Connections:**\n* **V1** connects to the top terminal labeled **AIn**.\n* **V2** connects to the second terminal below **AIn**.\n* The bottom terminal labeled **AISENSE** connects to the common ground node shared by **V1**, **V2**, and **Vcm**.\n* Multiple terminals on the vertical bar connect into the **Input Multiplexer**.\n* The text **n = 0, ..., 63** is located near the **Vcm** source, indicating the channel range.\n* The output of the **Input Multiplexer** connects to the non-inverting input (**+**) of the **Instrumentation Amplifier**.\n* The inverting input (**-**) of the **Instrumentation Amplifier** is connected to ground.\n* The output of the **Instrumentation Amplifier** connects to **To A/D Converter**.](.pci-9222-9223-manual-10/3c3faa257be28996602963916eb1a1cc0d416f420c5b3b441c278edaa51b1d55.jpg) Figure 2-3: Ground-referenced Sources and NRSE Input Connections # Differential input mode The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 2-4 shows the connection of ground-referenced signal sources under differential input mode. ![Based on the provided diagram, here is an accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks and Components:**\n* **Left Side:**\n * 'Ground Referenced Signal Source' (represented by a circle with a sine wave).\n * 'Common-mode noise & Ground potential' (represented by a circle labeled \$V_{cm}\$).\n* **Center:**\n * 'Input Multiplexer' (a vertical bar with four input terminals and two internal rectangular blocks).\n * Text above the multiplexer: 'x = 0, ..., 31'.\n* **Right Side:**\n * 'Instrumentation Amplifier' (represented by a triangle).\n * Text to the right: 'To A/D Converter'.\n\n**Connections:**\n* **Signal Sources:** The bottom terminal of the 'Ground Referenced Signal Source' connects to the top terminal of the '\$V_{cm}\$' source. The bottom terminal of the '\$V_{cm}\$' source connects to a ground symbol.\n* **Multiplexer Inputs:**\n * The top terminal of the signal source connects to a line labeled 'A1xH', which feeds the top input of the 'Input Multiplexer'.\n * The common node (bottom of the signal source) connects to two lines: one labeled 'A1xL' feeding the second input, and another line feeding the third input.\n * The fourth (bottom) input is labeled 'AIGND' and connects to ground.\n* **Multiplexer Internal:**\n * The top rectangular block receives inputs from the top two terminals.\n * The bottom rectangular block receives inputs from the bottom two terminals.\n* **Amplifier Connections:**\n * The output of the top rectangular block connects to the non-inverting '+' input of the 'Instrumentation Amplifier'.\n * The output of the bottom rectangular block connects to the inverting '-' input of the 'Instrumentation Amplifier'.\n * The bottom vertex of the amplifier triangle connects to ground.\n* **Output:**\n * The output of the amplifier goes to the right, labeled with a '+' sign. The text 'To A/D Converter' is placed next to this output.\n * A separate line with a '-' sign runs parallel below the main output line.](.pci-9222-9223-manual-10/05c747b1d7685cf00caa5a40bd5cccd172e83948e8b20b4b52c91ec29cc54441.jpg) Figure 2-4: Ground-referenced Source and Differential Input Figure 2-5 shows how to connect a floating signal source to the PCI-9222/PCI-9223 card in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance. If the source impedance is less than 100 ohms, you can simply connect the negative side of the signal to AIGND as well as the negative input of the instrumentation amplifier without any resistors. In differential input mode, less noise couples into the signal connections than in single-ended mode. ![Ground\nReferenced\nSignal\nSource\nx = 0, ..., 31\nInput Multiplexer\nInstrumentation\nAmplifier\nTo A/D\nConverter\nAIxH\nAIxL\nAIGND\n-](.pci-9222-9223-manual-10/26bc64dd05a87ce060e6ba35b7b2cbeac6c3a898239513bd60791f0841d3330c.jpg) Figure 2-5: Floating Source and Differential Input # 3 Installation # 3.1 Before You Proceed The PCI-9222/PCI-9223 card has electro-static sensitive components that can be easily damaged by static electricity. The card must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for damages. Shipping and handling could cause damage to the module. Make sure that the card has no damage before installing it. After opening the card package, get the module and place it on a grounded anti-static surface with component side up, then carefully inspect the module for any damage. Press down all socketed ICs to make sure that they are properly seated. Do this only with the module placed on a firm flat surface. WARNING Do not apply power to the card if it is damaged. # 3.2 Installing the Card # IMPORTANT Install the card driver before you install the card into your computer system. Refer to section 1.5 for driver support information. # To install the card: 1. Turn off the system/chassis and disconnect the power plug from the power source. 2. Remove the system/chassis cover. 3. Select the PCI slot that you intend to use, then remove the bracket opposite the slot, if any. 4. Align the card connectors (golden fingers) with the slot, then press the card firmly until the card is completely seated on the slot. 5. Secure the card to the chassis with a screw. 6. Replace the system/chassis cover. 7. Connect the power plug to a power source, then turn on the system. # 3.3 Configuring the Card As a plug and play component, the card requests an interrupt number through its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load detected by the system. # Configuration The card configuration is done on a card-by-card basis for all PCI cards on your system. Because configuration is controlled by the system and the software, there is no jumper setting required for base address, DMA, and interrupt IRQ. The configuration is subject to change with every boot of the system as new PCI cards are added or removed. # Troubleshooting If your system fails to boot or if you experience erratic operation with your PCI card in place, this is likely caused by an interrupt conflict (such as when the BIOS Setup is incorrectly configured). Refer to the BIOS documentation that came with the system for details. # 4 Operation Theory The operation theory of each function in the PCI-9222/PCI-9223 card is described in this chapter. These functions include A/D conversion, D/A conversion, encoder, programmable function I/O, and more. The operation theory can help you understand how to configure and program the PCI-9222/PCI-9223 card. # 4.1 Block Diagram There are 32/16 single-ended channels of 16-bit A/D input and 2 single-ended channels of 16-bit D/A output available in the PCI-9222/PCI-9223 card. By switching the multiple front-end multiplexers, all A/D input channels are connected to one ADC (ADI AD7685/7686 or equivalent). As for the D/A function, 2 analog output channels are generated by one DAC chip (TI DAC8812). The ADC/DAC controller and all timing control logics are implemented by the FPGA. The PCI-9222/PCI-9223 has calibration circuits to provide high-performance and low-temperature drift DC signal source. The calibration data are saved in the EEPROM. Combining FIFO control logic and simultaneous update characteristic, the PCI-9222/PCI-9223 offers a 2-channel simultaneous basic waveform generation. The general purpose function digital IO and encoders are controlled directly by the FPGA. Refer to Figure 4-1. ![The diagram illustrates a hardware architecture with input signal processing, an FPGA core, and output signal generation.\n\n**Input Chain (Left Side):**\n* **Blocks:** 'SCSI CONNECTOR X 2 INTERFACE' (Vertical blue arrow), 'MUX', 'Connect Selection', 'PGA', '16Bit ADC 250ks/s or 500ks/s'.\n* **Connections:**\n * Inputs 'AI Channel Select', 'AI Gain Select', 'AI Offset', 'AID_011', 'AIDG00E', and 'AI GND' feed into the 'MUX'.\n * The 'MUX' connects to 'Connect Selection'.\n * 'Connect Selection' connects to 'PGA'.\n * 'PGA' connects to the '16Bit ADC 250ks/s or 500ks/s'.\n * The ADC outputs a connection labeled 'DATA' to the FPGA block.\n\n**FPGA Core (Center/Right Grid):**\n* **Main Block:** 'FPGA'\n* **Internal Sub-Blocks:**\n * **Column 1:** 'AI DATA SPI Control', 'AI DATA FLOW Control', 'AO Control', 'Calibration Control'.\n * **Column 2:** 'CQ FIFO Control', 'AI/AO /PFI /PFO FIFO Control', 'PFI, PFO, Encoder'.\n * **Column 3:** 'AI Convert Timing Control', 'Calibration Data Storage', 'PCI INTERFACE', 'SSI Control'.\n* **Connections:**\n * 'AI DATA SPI Control' receives the 'DATA' input from the ADC.\n * 'EEPROM' connects via a purple arrow to 'AI Convert Timing Control'.\n * A purple arrow labeled 'DATA' connects from the FPGA area to the DAC blocks (see below).\n * 'AO Control' connects to the DAC blocks.\n * 'Calibration Control' connects to the Calibration DAC.\n * 'PCI INTERFACE' (in FPGA) connects to a vertical blue arrow labeled 'PCI INTERFACE'.\n * 'SSI Control' connects to a vertical blue arrow labeled 'SSI INTERFACE'.\n\n**Output Chain (Center/Right):**\n* **Blocks:** Yellow block containing 'CH2 16Bit DAC', 'CH3 16Bit DAC', 'CH2 LATCH', 'CH3 LATCH'. Dashed boxes labeled 'DP' (two instances).\n* **Connections:**\n * The yellow DAC/Latch block receives inputs from the FPGA (via 'DATA' and 'AO Control' connections).\n * The DACs connect to the 'DP' boxes.\n * The 'DP' boxes connect back to the 'SCSI CONNECTOR X 2 INTERFACE'.\n\n**Calibration & Digital IO:**\n* **Blocks:** 'Calibration DAC 12Bit TimeDAC', 'REF VOLTAGE', 'DIGITAL IO FUNCTION'.\n* **Connections:**\n * 'Calibration Control' (FPGA) connects to 'Calibration DAC 12Bit TimeDAC'.\n * 'Calibration DAC 12Bit TimeDAC' connects to 'REF VOLTAGE'.\n * 'REF VOLTAGE' connects back to 'Calibration Control'.\n * A large yellow arrow labeled 'DIGITAL IO FUNCTION' spans the bottom of the diagram.](.pci-9222-9223-manual-10/c4b976d627f2a7e2f5ec24117ef51314a9e63bd6329b68bc402fd2ef6aa43304.jpg) Figure 4-1: PCI-9222/PCI-9223 Block Diagram # 4.2 A/D Conversion When using an A/D converter, you must know about the properties of the signal to be measured and decide which channel to use and how to connect the signals to the card. Refer to section 2.3. In addition, you should define and control the A/D signal configurations, including channels, gains, and signal types. The A/D acquisition is initiated by a trigger source and you must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched. After the end of an A/D conversion, the A/D data is buffered in a data FIFO. The A/D data can now be transferred into the system's memory for further processing. Software Polling and Scan Acquisition modes are discussed below as well as timing, trigger modes, trigger sources, and transfer methods. PCI-9222/PCI-9223 AI Circuitry ![**CN1 SCSI CONNECTOR INTERFACE**: A vertical blue arrow on the far left acting as the input source.\n* **AI(0..31)**: Connects the interface to the **Analog Input MUX**.\n* **AI SENSE**: Connects the interface to the **Connect** block.\n* **AI GND**: Connects the interface to the **Connect** block.\n\n**Analog Input MUX**: A light yellow block receiving **AI(0..31)**.\n* **AI Channel Selection**: An arrow connecting the **Analog Input MUX** to the **Connect** block.\n\n**Connect**: A blue trapezoid block receiving inputs from **AI SENSE**, **AI GND**, **AI Channel Selection**, and an arrow labeled **Connector Type Selection**.\n* Outputs to **PGA**.\n\n**PGA**: A triangle symbol receiving input from **Connect**.\n* Outputs to **16Bit ADC 250ks/s or 500ks/s**.\n\n**16Bit ADC 250ks/s or 500ks/s**: An orange pentagon block receiving input from **PGA**.\n* Outputs a block labeled **DATA** pointing to the **FPGA**.\n\n**Calibration MUX**: A dashed blue box.\n* Connects to **REF VOLTAGE**.\n\n**FPGA**: A large green square divided into four quadrants.\n* **AI DATA SPI Control**: Top-left quadrant receiving **DATA**. It has an arrow pointing down to **Arithmetic Process** and an arrow pointing right to **CGQ FIFO**.\n* **CGQ FIFO**: Top-right quadrant.\n* **Arithmetic Process**: Bottom-left quadrant receiving input from **AI DATA SPI Control**. It has an arrow pointing right to **AI S12 FIFO**.\n* **AI S12 FIFO**: Bottom-right quadrant.](.pci-9222-9223-manual-10/684e8c734d6042e5b6c664f42bff86b26bd863ed8901c0f8aaa62b42b860d7e2.jpg) Figure 4-2: PCI-9222/PCI-9223 AI Circuitry # AI Data Format The data format of the acquired 16-bit A/D data is 2's complement coding. Table 4-1 shows the valid input ranges and the ideal transfer characteristics.
DescriptionBipolar Analog Input RangeDigital code
Full-scale Range±10V±5V±2.5V±2V
Least significant bit305.2uV152.6uV76.3uV61.03uV
FSR-1LSB9.999695V4.999847V2.499924V1.999938V7FFF
Midscale +1LSB305.2uV152.6uV76.3uV61.03uV0001
Midscale0V0V0V0V0000
Midscale -1LSB-305.2uV-152.6uV-76.3uV-61.03uVFFFF
-FSR-10V-5V-2.5V-2V8000
Table 4-1: Bipolar Analog Input Range and Output Digital Code
DescriptionBipolar Analog Input RangeDigital code
Full-scale Range±1.25V±1V±0.5V±0.25V
Least significant bit38.14uV30.51uV15.25uV7.62uV
FSR-1LSB1.249961V0.999969V0.499984V0.249992V7FFF
Midscale +1LSB38.14uV30.51uV15.25uV7.62uV0001
Midscale0V0V0V0V0000
Midscale -1LSB-38.14uV-30.51uV-15.25uV-7.62uVFFFF
-FSR-1.25V-1V-0.5V-0.25V8000
Table 4-2: Bipolar Analog Input Range and Output Digital Code # Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) Considered the most convenient way to acquire a single A/D data, the A/D converter starts one conversion whenever the dedicated software command is executed. The software then polls the conversion status and reads back the A/D data when it is available. This method is suitable for applications that need to process A/D data in real time. In this mode, the timing of the A/D conversion is fully controlled by the software. The A/D conversion rate is decided by the software timer and may not be totally precise. In Software Polling, the channel, gain, and input configuration (RSE, NRSE, or DIFF) may be specified for each single-point measurement. For example: Ch2 with ± 5V input range and single-ended NRSE connection # Continuous Acquisition (Scanning) Mode # Continuous A/D Conversion Clock Source When the onboard ADC receives a conversion clock signal, it will trigger an A/D conversion. The conversion clock of PCI-9222/PCI-9223 may come from three different clock sources: internal hardware timer, general purpose input channel (GPI 0 \~ GPI 7), or SSI (system synchronization interface). Refer to Figure 4-3. ![The diagram depicts a central trapezoidal block with inputs on the left and an output on the right.\n\n**Inputs (connected to the left side):**\n* Internal Timer\n* GPI(7..0)\n* SSI\n\n**Output (connected to the right side):**\n* AI Conversion Clock](.pci-9222-9223-manual-10/50d646249da0fca8b8d203bc67d9209d049851ab76ecf7bac7986a53164fa0dd.jpg) Figure 4-3: Continuous A/D Conversion Clock Source Block Diagram You can choose conversion clock source by setting AI source configuration. But if users want to get the precision acquisition, the internal hardware timer is recommended. # Continuous Scanning with Internal Hardware Timer It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels. There are at least four counters that have to be specified: ▶ SI\_counter (32-bit) Specify the Scan Interval = SI\_counter / Timebase ▶ SI2\_counter (24-bit) Specify the Data Sampling Interval = SI2\_counter/Timebase ▶ PSC\_counter (31-bit) Specify the Post Scan Counts after a trigger event ▶ NumChan\_counter (8-bit) Specify the number of samples per scan The acquisition timing and the meaning of the four counters are illustrated in Figure 4-4. Timebase Clock Source In scan acquisition mode, all A/D conversions start on the output of counters which use Timebase as the clock source. Through the software, you can specify the Timebase as the internal clock source (onboard 80 MHz). ![3 Scans, 4 Samples per scan\n(NumChan_Counter=4)\nScan_start\nAD_conversion\nAcquisition_in_progress\nSampling Interval t=\nSI2_COUNTER/TimeBase\nScan Interval T=\nSI_COUNTER/TimeBase\n channel sequences are specified in Channel Gain Queue)](.pci-9222-9223-manual-10/f8eea3c03574b3cdf5f7181cfb714127f6012ba4bc00880beb4296f4b500f414.jpg) Figure 4-4: Scan Timing Two trigger sources are available to start the scan acquisition. Refer to section 4.6 for details. For data transfer mode, refer to the Bus-mastering DMA Data Transfer section. # NOTES - The maximum A/D sampling rate is 250 kHz for PCI-9222 and 500 kHz for PCI-9223. The minimum setting for the SI2 counter when using the internal Timebase is 320 (PCI-9222) and 160 (PCI-9223). - The SI\_counter is 32-bit while the SI2\_counter is 24-bit. The maximum scan interval using the internal Timebase = $2^{32}/80$ Ms = 53.687s, and the maximum sampling interval between two channels using the internal Timebase = $2^{24}/40$ Ms = 0.419s. - The scan interval must not be smaller than the product of the data sampling interval and the NumChan\_counter value. The relationship can be represented as: SI\_counter>=SI2\_counter \* NumChan\_counter. # Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue The channel, gain, and input configurations can be specified in the Channel Gain Queue under the scan acquisition mode. Note that in scan acquisition mode the number of entries in the Channel Gain Queue is normally equivalent to the value of NumChan\_counter (the number of samples per scan). Example: Set ▶ SI2\_counter = 160 ▶ SI\_counter = 640 ▶ PSC\_counter = 3 ▶ NumChan\_counter = 4 ▶ Timebase = Internal clock source ▶ Channel entries in the Channel Gain Queue: ch1, ch2, ch0, ch2 Then: ▶ Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2 ▶ Sampling Interval = 160/80M s = 2 us ▶ Scan Interval = 640/80M s = 8 us ▶ Equivalent sampling rate of ch0, ch1: 125 kHz ▶ Equivalent sampling rate of ch2: 250 kHz # Trigger Modes The PCI-9222/PCI-9223 supports two trigger sources: internal software and external digital trigger. You must select one as the trigger event source. A trigger event occurs when the specified condition is detected on the selected trigger source. For example, a rising edge on the external digital trigger input. These cards support post-trigger (with retrigger) via software or an external digital trigger source to initiate various scan data acquisition timing when a trigger event occurs. # Post-Trigger Acquisition (no retrigger) Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in the PSC\_counter as illustrated in Figure 4-5. The total acquired data length = NumChan\_counter \*PSC\_counter. ![| Event | Value |\n| ---------------------- | ----- |\n| Trigger | 4 |\n| Scan_start | 3 |\n| AD_conversion | 2 |\n| Acquisition_in_progress| 1 |\n| Operation start | Start |\n| Acquired & stored data (3 scans) | 3 scans |](.pci-9222-9223-manual-10/e4cbc4f67ffd56d7967d30e80c09381a81843464cfa2f545763f8be78979ccdd.jpg) Figure 4-5: Post Trigger without Retrigger # Post-Trigger Acquisition (with retrigger) Use post-trigger acquisition with retrigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC\_counter and are programmable. Use Retrig\_no to specify the re-trigger numbers. In Figure 4-6, two scans of data are acquired after the first trigger signal, then the card waits for the retrigger signal (retrigger signals which occur before the scans are completed will be ignored). When the retrigger signal occurs, two more scans are performed. The process repeats until the specified amount of retrigger signals are detected. The total acquired data length = NumChan\_counter \*PSC\_counter \* Re-trig\_no. For infinite retrigger, the retrig\_no is set to 0. ![(NumChan Counter=4, PSC Counter=2, retrig_no=3)\nTrigger\nScan_start\nAD_conversion\nAcquisition_in_progress\nOperation start\nAcquired & stored data\n(8 scans)](.pci-9222-9223-manual-10/7dc117fcadbd34fa4da41eebd26ad422658e264b7017b184e52b7fb2e29eb096.jpg) Figure 4-6: Post Trigger with Retrigger # Gated Trigger Use the gated-trigger acquisition function in applications where you want to collect data when trigger events are set to level high/low, and hold acquisition when trigger events are set to the opposite level. The number of scans after each trigger is specified in the PSC\_counter. In Figure 4-7, after the operation starts, the first scan of data is immediately acquired when the trigger signal is disasserted and paused at the second scan when the trigger signal is asserted. The four remaining scans are not performed until the trigger signal is disasserted again. The process repeats until the specified amount of retrigger signals are detected. The total acquired data length = NumChan\_counter \*PSC\_counter. ![| Event | Value |\n| ------------------- | ----- |\n| ACQ_EN | High |\n| Trigger | High |\n| Scan_start | Low |\n| AD_convserion | Low |\n| Acquisition_in_progress | Low |\n| Acquisition Paused | Delayed |\n| Operation Start | Start |\n| Acquired & stored data (6 scans) | Start |](.pci-9222-9223-manual-10/5d21aec03d6396bd4bfba71cf33613af4b3ca874d1a8f004cc82c4e627ed1e74.jpg) Figure 4-7: Gated Trigger with Finite Scan Acquisition # Bus-mastering DMA Data Transfer In programmable scan acquisition mode, the PCI-9222/PCI-9223 supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention. Bus-mastering DMA provides the fastest data transfer rate on PCI-bus. Once the analog input operation starts, control returns to your program. The hardware temporarily stores the acquired data in the onboard AD Data FIFO, then transfers the data to a user-defined DMA buffer memory in the computer. Note that even when the acquired data length is less than the Data FIFO, the AD data is not kept in the Data FIFO but rather directly transferred to the host memory by the bus-mastering DMA. The DMA transfer mode is a very complex to program. It is recommended that you use a high-level program library provided by the ADLINK driver to configure this card. By using a high-level programming library for high speed DMA data acquisition, you simply need to assign the sampling period and the number of conversion through their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA. The PCI controller also supports the scatter/gather bus mastering DMA function that enables transfer of large amounts of data by linking all the memory blocks into a continuous linked list. In a multi-user or multitasking OS, like Windows, Linux, etc, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PCI controller provides the function of scatter-gather or chaining mode DMA to link the non-continuous memory blocks into a linked list, allowing transfers of very large amounts of data without being limited by the fragment of small size memory. You may configure the linked list for the input DMA channel or the output DMA channel. Figure 4-8 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a PCI dual-address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual-address support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs. The software driver provides simple settings of the scatter-gather function, and some sample programs are also provided in the ADLINK All-in-one CD. ![Based on the provided image, here is the description of the flowchart:\n\n**Labeled Blocks:**\n* **Local Memory (FIFO)**\n* **PCI Bus**\n* **Left Block:**\n * First PCI Address\n * First Dual Address\n * Transfer Size\n * Next Descriptor\n* **Middle Block:**\n * PCI Address\n * Dual Address\n * Transfer Size\n * Next Descriptor\n* **Right Block:**\n * PCI Address\n * Dual Address\n * Transfer Size\n * Next Descriptor\n\n**Connections:**\n* An arrow points upward from **Local Memory (FIFO)** to **PCI Bus**.\n* An arrow points upward from **PCI Bus** to the **Middle Block**.\n* An arrow connects the **Left Block** to the **Middle Block**.\n* An arrow connects the **Middle Block** to the **Right Block**.](.pci-9222-9223-manual-10/74c8dc2134126d7e046ea532110941ab7623269a1b2ea586ee1165b2edd368f1.jpg) Figure 4-8: Scatter-gather DMA for Data Transfer In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multi-buffered mode DMA. # 4.3 D/A Conversion For complex applications, the PCI-9222/PCI-9223 offers software polling to update the output, and DMA data transfer to generate waveform. This means that the D/A update rate is not only controlled by software timing, but can also be set by a precision hardware timer that you specified. The following sections discuss the PCI-9222/PCI-9223 D/A architecture and control methods. # Bipolar Output Modes The PCI-9222/PCI-9223 supports a maximum $\pm10$ V voltage output. Table 4-3 illustrates the relationship of straight binary coding between the digital codes and output voltages.
Digital CodeAnalog Output
0xFFFF20V * (65535/65536) – 10V
0xC0005V
0x800120V * (32769/65536) – 10V
0x80000V
0x4000-5V
0x0000-10V
Table 4-3: Bipolar Output Codes # Software Update This method is suitable for applications that need to generate D/A output controlled by user programs. In this mode, the D/A converter generates one output once the software command is issued. However, it is difficult to determine the software update rate under a multitask OS such as Windows. # Waveform Generation # Waveform Generation Data Structure FIFO is a hardware first-in first-out data queue that holds temporary digital codes for D/A conversion. When PCI-9222/PCI-9223 operates in waveform generation mode, the waveform patterns are stored in FIFO with 512 samples. Waveform patterns larger than 512 samples are also supported using bus-mastering DMA transfer via the PCI controller. Data format in FIFO is shown in Figure 4-9. ![The diagram depicts a block labeled **512 Samples Data FIFO**.\n\n**Inputs and Outputs:**\n* An arrow labeled **Data In** points into the right side of the block.\n* An arrow labeled **Data Out** points out of the left side of the block.\n\n**Internal Structure:**\n* Inside the main block, text reads **16 Bit Hex Data Format**.\n* Below this text is a row of green rectangles containing hex values: **FFFF**, **0000**, **0100**, **FFFE**, **0001**, **0101**, followed by ellipses **......**, and ending with **FF00**, **00FF**, **01FF**.\n\n**Connections and Destinations:**\n* Vertical arrows connect each hex data rectangle to a corresponding rectangle in a row below.\n* The row below is labeled **Destination Channel**.\n* The green rectangles in this row contain the text: **CH0**, **CH1**, **CH3**, **CH0**, **CH1**, **CH3**, followed by ellipses **......**, and ending with **CH0**, **CH1**, **CH3**.](.pci-9222-9223-manual-10/ff9410ad3477c36770ca88a309d33baae7d9e773049c2e92b1b1712b2f4185cd.jpg) Figure 4-9: FIFO Data In/Out Structure DMA transfers data according to channel order. Figure 4-10 shows DA channel 0 to channel 3 data, while channel 2 is disabled. ![DA Channel 0\n0000\nX\n0100\nDDA Channel 1\nDA Channel 2\nDA Channel 3\nFFFF\n0001\nX\n0101\nDDA Channel 0\n0002\nX\n0102\nDDA Channel 1\n0002\nX\n0102\nDDA Channel 2\nDisable\n01FF\n0F00\n00FF\nX\n01FF](.pci-9222-9223-manual-10/8f3d60cbd6be44b221417ea9b07d79338c561d084f1bf8316a1be6613bbaa4f9.jpg) Figure 4-10: Waveform Generation for Three Channels Update With hardware-based waveform generation, D/A conversions are updated automatically by the FPGA rather than by the application software. Compare with the conventional software-based waveform generation, the precise hardware timing control guarantees non-distorted waveform generation even when the host CPU is under heavy loading. # NOTE When using waveform generation mode, both DACs must be configured in a single mode. However, any individual DAC can be disabled. # Waveform Generation Clock Source When the onboard DAC receives a conversion clock signal, it will trigger a D/A update. The update clock of PCI-9222/PCI-9223 may come from three different clock sources: internal hardware timer, general purpose input channel (GPI 0 \~ GPI 7), or SSI (system synchronization interface). You can choose the update clock source by setting the AO source configuration. Refer to Figure 4-11. It is recommended that you use the internal hardware to get a more precise update rate. ![The diagram depicts a central processing block (a light green trapezoid) with inputs on the left and an output on the right.\n\n**Inputs:**\n* **Internal Timer**\n* **GPI(7..0)**\n* **SSI**\n\n**Connections:**\n* Horizontal lines connect 'Internal Timer', 'GPI(7..0)', and 'SSI' from the left to the left side of the central block.\n* A horizontal line connects the right side of the central block to the output label **AO update clock**.](.pci-9222-9223-manual-10/d2c5454cd4ca7f50492e0682e934d212cd6f74fe520c519c3557b7a3d355acee.jpg) Figure 4-11: Waveform Generation Clock Source Selection # Waveform Generation with Internal Hardware Timer Six counters interact with the waveform to generate different DAWR timing to form various waveforms. These are described in Table 4-4 and illustrated in Figure 4-12.
Counter NameWidthDescriptionNote
UI_counter32-bitUpdate Interval.Defines the update interval between each data output.Update Interval = UI_counter / Timebase*.
UC_counter32-bitUpdate Counts.Defines the number of data in a waveform.When value in UC_counter is smaller than the size of waveform patterns, the waveform is generated piece-wisely.
IC_counter32-bitIteration Counts.Defines how many times the waveform is generated.
DLY1_counter32-bitDefines the delay time for waveform generation after the trigger signal.Delay Time = (DLY1_counter / Clock Timebase)
Table 4-4: Summary of Counters for Waveform Generation
DLY2_counter32-bitDefines the delay time to separate consecutive waveform generation. This is applicable only in Iterative Waveform Generation mode.Delay Time = (DLY2_counter / Clock Timebase)
Trig_counter32-bitDefines the acceptable start trigger count when re-trigger function is enabled
Table 4-4: Summary of Counters for Waveform Generation Timebase $^{*}$ = 80M # NOTE The maximum D/A update rate is 1 MHz, and the minimum UI\_counter setting is 80. ![| Signal | Description |\n|-----------------|--------------------------------|\n| Trigger | UP/UP waveform with UC Counter = 4 |\n| DAWR | Up/Up waveform with UC Counter = 4 |\n| WF_in_Rrog | Up/Up waveform with UC Counter = 4 |\n| Wave | Wave waveform with DA_Update_Interval T = UI Counter / Timebase |\n| Delay until DLY1 | Delay until DLY1 Counter Reach 0 |\n| Delay until DLY2 | Delay until DLY2 Counter Reach 0 |\n| Delay until DLY2 | Delay until DLY2 Counter Reach 0 |](.pci-9222-9223-manual-10/6f51e3ee0484bb83055b255dcff14be01a095c5cd11f1ebebed755fdbfab7499.jpg) Figure 4-12: Typical D/A Timing of Waveform Generation # Trigger Modes # Post-Trigger Generation Use post-trigger generation when you want to generate a waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC\_counter\* IC\_counter and is illustrated in Figure 4-13. ![| Signal | Value |\n| ------------- | ----- |\n| Trigger | 12 |\n| DAWR | 12 |\n| WF_in_Rrog | 12 |\n| Wave | 12 |](.pci-9222-9223-manual-10/e67260478fa2e213b79273376036864d1d4c9220025e2c0a7e9c8909c48043c8.jpg) Figure 4-13: Post-Trigger Generation # Delay-Trigger Generation Use delay-trigger when you want to delay the waveform generation after the trigger signal. The delay time is determined by DLY1\_counter, as illustrated in Figure 4-14. The counter counts down on the rising edges of DLY1\_counter clock source after the start trigger signal. When the count reaches zero, card will start to generate the waveform. The DLY1\_counter clock source can be selected via software application using the internal 80 MHz timebase. ![| Signal | Value |\n|-----------------|-------|\n| Trigger | Delay until DLY1 Counter reaches 0 |\n| DAWR | Uc Counter = 6 |\n| WF_in_Rrog | Uc Counter = 6 |\n| Wave | Uc Counter = 6 |](.pci-9222-9223-manual-10/3b6fc39e31164d75b76dc17410d123478d6a06bce5f81db9b6205658261233ca.jpg) Figure 4-14: Delay-Trigger Generation # Post-Trigger or Delay-Trigger with Retrigger Use post-trigger or delay-trigger with retrigger when you want to generate multiple waveforms with respect to multiple incoming trigger signals. You can set Trig\_counter to specify the number of acceptable trigger signals. Refer to Figure 4-15. In this example, two waveforms are generated after the first trigger signal. The card then waits for another trigger signal. When the next trigger signal is asserted, the card generates two more waveforms. After two trigger signals, as specified in Trig\_Counter, no more triggers signals will be accepted unless trigger reset command is executed. For more information on Iterative Waveform Generation that is used in this example, refer to the next section. ![| Signal | Value |\n|-----------------|-------|\n| Trigger | 3 |\n| DAWR | 3 |\n| WF_in_Rrog | 3 |\n| Wave | 3 |](.pci-9222-9223-manual-10/172368c177a0b2bb306cec83b3fa37f0965909d3e34708c2aa0114413f112e6d.jpg) Figure 4-15: Post-Trigger with Retrigger Generation NOTE Start Trigger signals asserted during the waveform generation process will be ignored. # Iterative Waveform Generation You can set the IC\_counter to generate iterative waveforms regardless of the trigger mode used. The IC\_counter stores the iteration number. Examples are shown in Figure 4-16 and Figure 4-17. NOTE When IC\_counter is disabled, the waveform generation will not stop until a stop trigger is asserted. An onboard data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host computer's memory, the data in FIFO will be reused when a single waveform generation is completed and will not occupy the PCI bandwidth afterwards. However, if the size of a single waveform is larger than that of the FIFO, it needs to be intermittently loaded from the host computer's memory via DMA, and will occupy the PCI bandwidth. If the value specified in UC\_counter is smaller than the sample size of the waveform patterns, the waveform will be generated piece-wisely. For example, if you defined a 16-sample sine wave and set the UC\_counter to 2, the generated waveform will be a 1/8-cycle sine wave for every waveform period, and a complete sine wave will be generated for every 8-iterations. If you specified a UC\_counter value that is larger than the sample size of the waveform LUT (for example, 32), the generated waveform will be a 2-cycle sine wave for every waveform period. ![| Signal | Value |\n|-----------------|-------|\n| Trigger | 4 |\n| DAWR | 3 |\n| WF_in_Rrog | 0 |\n| Wave | 1 |](.pci-9222-9223-manual-10/db19e3e3db08adb55244b5e3d2c51f2a4fb2ca5e2f89292c72fc29d353416b80.jpg) Figure 4-16: Finite Iterative Waveform Generation with Post-trigger ![| Signal | Value |\n|-----------------|-------|\n| Trigger | 4 |\n| DAWR | 4 |\n| WF_in_Rrog | 4 |\n| Wave | 4 |](.pci-9222-9223-manual-10/fae22d787df950452d94ae266911e3f7532b1f0acb3733e783d8c78f473c2807.jpg) Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger In conjunction with different trigger modes and counter setups, you can manipulate a single waveform to generate different and more complex waveforms. DLY2\_Counter in Iterative Waveform Generation To expand the flexibility of iterative waveform generation, DLY2\_counter was implemented to separate consecutive waveform generations. The DLY2\_counter starts counting down right after a single waveform generation is completed. When it reaches zero, the next iteration of waveform generation will start as shown in Figure 4-12. If you generate the waveform piece-wisely, the next piece of waveform will be generated. The DLY2\_counter clock source can be software selected from internal 80 MHz Timebase. # 4.4 Programmable Function I/O The PCI-9222/PCI-9223 supports a powerful programmable function I/O provided by an FPGA chip. These function I/O can be configured as TTL DI/DO or 32-bit timer/counters. In addition, the timer/counter supports a variety of modes, including general purpose timer/counter, PWM output, or encoder input for simple motion control. These signals are single-ended and 5V TTL-compliant. # TTL DI/DO Programmable function I/O can be used as static TTL-compliant 8-CH digital input and 4-CH digital output. You can read/write these I/O lines by software polling. Its sample and update rate is fully controlled by software timing.
DefinitionPin #Definition
GPI03468GPI8
GPI13367GPI9
GPI23266GPI10
GPI33165GPI11
GPI43064GPI12
GPI52963GPI13
GPI62862GPI14
GPI72761GPI15
DGND2660DGND
GPO02559GPO8
GPO12458GPO9
GPO22357GPO10
GPO32256GPO11
GPO42155GPO12
GPO52054GPO13
GPO61953GPO14
GPO71852GPO15
......
135
Table 4-5: TTL DIO Pins in CN1 # General Purpose Timer/Counter The PCI-9222/PCI-9223 comes with three general purpose timer/counter sets featuring: ▶ Count up/down controlled by hardware or software ▶ Programmable counter clock source (internal clock up to 80 MHz, external clock up to 10 MHz) ▶ Programmable gate selection (hardware or software control) ▶ Programmable input and output signal polarities (high active or low active) ▶ Initial Count can be loaded from a software application ▶ Current count value can be read-back by software without affecting circuit operation.
DefinitionPin #Definition
GPTC_CLK03468GPTC_CLK2
GPTC_UD03367GPTC_UD2
GPTC_GATE03266GPTC_GATE2
GPTC_AUX03165GPTC_AUX2
GPTC_CLK13064GPTC_CLK3
GPTC_UD12963GPTC_UD3
GPTC_GATE12862GPTC_GATE3
GPTC_AUX12761GPTC_AUX3
DGND2660DGND
GPTC_OUT02559
GPTC_OUT12458
GPTC_OUT22357
GPTC_OUT32256
......
135
Table 4-6: Timer/Counter Mode Pins in CN1 # Basic Timer/Counter Functions Each timer/counter has three inputs that can be controlled via hardware or software applications. They are clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UD). The GPTC\_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UD input controls the counter to count up or down (high: count up; low: count down), while the GPTC\_GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications. The GPTC\_OUT will then generate a pulse signal based on which timer/counter mode you have set. All input/output signals polarities can be programmed by software application. For brevity, all GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT in the following illustrations are assumed to be active high or rising-edge triggered. # General Purpose Timer/Counter Modes Ten programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and reloads the initial value to the counter. The operation remains halted until the software-start is executed again. The operating theories under different modes are described in the following sections. # Mode1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC\_CLK after the software-start. Initial count can be loaded from the software application. Current count value can be read-back by software any time with no effect to the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-18 illustrates the operation with initial count = 5, count-down mode. ![| Time | Gate | CLK |\n|------|------|-----|\n| 0 | 1 | 1 |\n| 1 | 1 | 1 |\n| 2 | 1 | 1 |\n| 3 | 1 | 1 |\n| 4 | 1 | 1 |\n| 5 | 1 | 1 |\n| 6 | 1 | 1 |\n| 7 | 1 | 1 |\n| 8 | 1 | 1 |\n| 9 | 1 | 1 |\n| 10 | 1 | 1 |\n| 11 | 1 | 1 |\n| 12 | 1 | 1 |\n| 13 | 1 | 1 |\n| 14 | 1 | 1 |\n| 15 | 1 | 1 |\n| 16 | 1 | 1 |\n| 17 | 1 | 1 |\n| 18 | 1 | 1 |\n| 19 | 1 | 1 |\n| 20 | 1 | 1 |\n| 21 | 1 | 1 |\n| 22 | 1 | 1 |\n| 23 | 1 | 1 |\n| 24 | 1 | 1 |\n| 25 | 1 | 1 |\n| 26 | 1 | 1 |\n| 27 | 1 | 1 |\n| 28 | 1 | 1 |\n| 29 | 1 | 1 |\n| 30 | 1 | 1 |\n| 31 | 1 | 1 |\n| 32 | 1 | 1 |\n| 33 | 1 | 1 |\n| 34 | 1 | 1 |\n| 35 | 1 | 1 |\n| 36 | 1 | 1 |\n| 37 | 1 | 1 |\n| 38 | 1 | 1 |\n| 39 | 1 | 1 |\n| 40 | 1 | 1 |\n| 41 | 1 | 1 |\n| 42 | 1 | 1 |\n| 43 | 1 | 1 |\n| 44 | 1 | 1 |\n| 45 | 1 | 1 |\n| 46 | 1 | 1 |\n| 47 | 1 | 1 |\n| 48 | 1 | 1 |\n| 49 | 1 | 1 |\n| 50 | 1 | 1 |\n| Note: The actual values for Gate and CLK are not provided in the code. The data is presented as a sequence of 'Count value' values from '5' to '0'.](.pci-9222-9223-manual-10/126bb53706aa35b61bc1bb43c9d3e71e4ae9824e2c760885511deac9cc882a6c.jpg) Figure 4-18: Mode 1 Operation # Mode 2: Single Period Measurement The counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from the software application. After the software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by the software application. Figure 4-19 illustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value\n0 0 1 2 3 4 5 5 5](.pci-9222-9223-manual-10/ad0e4ed3db009a34fa1aca00d0a3dad708a6254a273c3210513639857835da1f.jpg) Figure 4-19: Mode 2 Operation # Mode 3: Single Pulse-width Measurement The counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. Initial count can be loaded from the software application. After the software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT outputs high and then current count value can be read-back by the software application. Figure 4-20 illustrates the operation where initial count = 0, count-up mode. ![Software start\nGate\nCLK\nCount value 0 0 1 2 3 4 5 5 5](.pci-9222-9223-manual-10/2ab54b95c9acdb72c914191f6396daff710c20b814a1fb282eaf6c479e724a66.jpg) Figure 4-20: Mode 3 Operation # Mode 4: Single Gated Pulse Generation This generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters can be specified in terms of periods of the GPTC\_CLK input by the software application. GPTC\_GATE is use to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-21 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|------------|-------|\n| Gate | 2 |\n| CLK | 2 |\n| Count value| 0 |\n| OUT | 1 |](.pci-9222-9223-manual-10/c24522fc06e54817a88c07ea531b5d6b18bd98e4a487447f9e2e0a5efed3ddd0.jpg) Figure 4-21: Mode 4 Operation # Mode 5: Single Triggered Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following an active GPTC\_GATE edge. You may specify these programmable parameters in terms of periods of the GPTC\_CLK input. When the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE makes no effect until the software-start is executed again. Figure 4-22 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. ![The image is a timing diagram featuring four signal rows labeled on the left: 'Gate', 'CLK', 'Count value', and 'OUT'. Centered at the top is the text 'Software start', from which a vertical dashed line extends downward.\n\nThe waveforms and data are arranged as follows:\n* **Gate:** Shows a low signal that briefly pulses high before returning low.\n* **CLK:** Displays a continuous square wave clock signal.\n* **Count value:** Below the CLK signal, a sequence of numbers is listed: '2 2 1 0 3 2 1 0'.\n* **OUT:** Shows a signal that remains low, goes high for a duration covering several clock cycles, and then goes low again.](.pci-9222-9223-manual-10/d0b3fd7e0e7031827fc3626dd63eaad10547a5aea159d2b8f31cc9f83072a720.jpg) Figure 4-22: Mode 5 Operation # Mode 6: Re-triggered Single Pulse Generation This mode is similar to Mode 5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After the software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC\_GATE triggers that occur when the prior pulse is not completed is ignored. Figure 4-23 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four. ![| Signal | Value |\n|--------|-------|\n| Gate | 0 |\n| CLK | 0 |\n| Count value | 2 |\n| OUT | 0 |](.pci-9222-9223-manual-10/4b435a9c00bb391dae19d9946fdb8f40fa535cd517cd7d127e82ff46c308b40c.jpg) Figure 4-23: Mode 6 Operation # Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. When the first GPTC\_GATE edge triggers the counter, GPTC\_GATE makes no effect until the software-start is executed again. Figure 4-24 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value\nOUT](.pci-9222-9223-manual-10/9ff907463134185a62e093886dc54126976aed70c5764e2a7526767ca991fcc8.jpg) Figure 4-24: Mode 7 Operation # Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC\_GATE is use to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 4-25 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. ![Software start\nGate\nCLK\nCount value 4 1 1 1 1 0 3 1 0 1 1 1 0 3 1 1 0 1\nOUT](.pci-9222-9223-manual-10/ab108f271822d76e7bfd24e27c8b83445c493cf95daf68f73e3832e01a6d0f9f.jpg) Figure 4-25: Mode 8 Operation # Mode 9: Edge Separation Measurement Measures the time differentiation between two different pulse signals. The first pulse signal is connected to GPTC\_GATE and the second signal is connected to GPTC\_AUX. It counts the clocks that pass by between the rising edge signal of two different pulses through the 40MHz internal clock or external clock. You can calculate the time period via the known clock frequency. The maximum counting width is 32-bit. Figure 4-26 illustrates how the counter value decreases in Edge Separation Measurement mode. ![| Signal | Value |\n|--------|-------|\n| Gate | 11 |\n| AUX | 11 |\n| CLK | 12 |\n| Count | 10 |](.pci-9222-9223-manual-10/bea12240a9983b17831dea00b94c3ed6c0c89374fcdc2564832d14525d4a4db7.jpg) Figure 4-26: Mode 9 Operation # Mode 10: PWM Output These cards' powerful timer/counter can also simulate a PWM (Pulse Width Modulation) output. By setting varying number of Pulse\_initial\_cnt and Pulse\_length\_cnt, you can get varying pulse frequency (Fpwm) and duty cycle (Dutypwm). Figure 4-27 illustrates the PWM output and the formula showing how to calculate the PWM frequency and duty cycle. ![PWMOUT\nTIMEBASE\nPulse_Initial_cnt =0x7\nPulse_length_cnt =0x8](.pci-9222-9223-manual-10/f20be2035fb6bb0bfca1dc442244c40869553089977c3cd5e357b705e458813b.jpg) Figure 4-27: Mode 10 Operation $$ \begin{array}{l} F _ {P W M} = \frac {F _ {\text { Timebase }}}{\text { Pulse } \_ i n i t i a l \_ c n t + \text { Pulse } \_ l e n g t h \_ c n t} \\ D u t y _ {P W M} = \frac {\text {Pulse\_length\_cnt}}{\text {Pulse\_initial\_cnt} + \text {Pulse\_length\_cnt}} \\ \end{array} $$ # Digital Waveform Acquisition and Generation The PCI-9222/PCI-9223 GPI and GPO support digital waveform generation and digital waveform acquisition. You can sample GPI or update GPO based on the precision hardware timer. # Digital Waveform Acquisition The digital data on GPI channels can be acquired by using the digital waveform acquisition mode. This function is similar with AI scan acquisition mode. With periodic sampling clock, you can acquire data based on the precision hardware time interval. The PCI-9222/PCI-9223 comes with a dedicated FIFO that stores the sampled digital data and transfers it to the system memory via DMA. The GPI is a 16-bit data and the sample clock source can be configured from an internal timer pacer, internal analog conversion clock, or external clock. When using an internal timer pacer as clock source, the GPI supports data transfer rates of up to 2MHz. The internal analog conversion clock source can come from AI conversion clock or AO update clock. The external signal clock source can be set from any of the GPI [0..7] pins. When the sample clock is from the GPI, the actual GPI data width is only 15-bit since the external sample clock signal occupies one bit. Figure 4-28 illustrates the GPI sample clock routing. ![**Blocks:**\n* **GPI Sample clock select**: A vertical rectangular block.\n* **GPI Waveform FIFO**: A rectangular block with a dashed border.\n* **CN2 SCSI CONNECTOR GPI(15..0)**: A large vertical double-headed arrow.\n\n**Connections and Inputs:**\n* Four inputs enter the **GPI Sample clock select** block from the left:\n * 'Internal Divided Down Timer'\n * 'GPI(7..0)'\n * 'AI Conversion Clock'\n * 'AO Update Clock'\n* An output exits the **GPI Sample clock select** block to the right, labeled 'GPI Sample Clock', and enters the **GPI Waveform FIFO** block.\n* A line exits the right side of the **GPI Waveform FIFO** block and connects to the vertical arrow labeled **CN2 SCSI CONNECTOR GPI(15..0)**.\n* From this connecting line, a branch extends downward and leftward with an arrow pointing to the text 'Static GPI'.](.pci-9222-9223-manual-10/fe2a5e6de81cda7a6e73d632e675baaf893b872112dbe161f49e8cb6f30f1808.jpg) Figure 4-28: Digital Waveform Acquisition Operation # Digital Waveform Generation The digital output on GPO [15..0] channels can be updated by using digital waveform generation mode. This works similar to AO waveform generation. With periodic update clock, you can generate a sequence of digital output patterns based on precision hardware time interval. The PCI-9222 and PCI-9223 come with a dedicated FIFO that stores these waveform patterns. The update patterns are transferred from the system memory to the FIFO via DMA after the digital waveform generation starts. The GPO update clock source can be configured from the onboard timer pacer, internal analog conversion clock, or external clock. When using the internal timer pacer as update clock source, the GPO supports data update rates of up to 2MHz. The internal analog conversion clock source can come from AI conversion clock or AO update clock, while the external signal clock source can be set from any of the GPI [0..7] pins. When the update clock is from the GPI and the GPI funtions at the same time, the actual GPI data width is only 15-bit. Figure 4-29 illustrates the routing of GPO update clock. ![This block diagram illustrates the signal routing for a General Purpose Output (GPO) interface.\n\n**Labeled Blocks and Inputs:**\n* **Input Sources:** Four signals feed into a vertical block labeled (vertically) **'GPO Sample clock select'**:\n * 'Internal Divided Down Timer'\n * 'GPI(7..0)'\n * 'AI Conversion Clock'\n * 'AO Update Clock'\n* **Label:** The text **'GPO'** appears to the left of the sample clock select block.\n* **FIFO:** A dashed box labeled **'GPO Waveform FIFO'**.\n* **Output Interface:** A large vertical blue arrow labeled **'CN2 SCS1 CONNECTOR GPO(15..0)'**.\n\n**Connections:**\n1. The four input sources listed above connect into the **'GPO Sample clock select'** block.\n2. This block outputs a line labeled **'GPO Sample Clock'**, which connects into the top of the **'GPO Waveform FIFO'**.\n3. Three signals feed into a rightmost vertical block (acting as a multiplexer):\n * The output from the **'GPO Waveform FIFO'**.\n * A signal labeled **'Static GPO'**.\n * A signal labeled **'GPTC Output'**.\n4. The output of this rightmost block connects to the **'CN2 SCS1 CONNECTOR GPO(15..0)'**.](.pci-9222-9223-manual-10/872cdf219fdc31fe7b300b153f81734349046f511f58d8b6e6cdbe768795c073.jpg) Figure 4-29: Digital Waveform Generation Operation # 4.5 Isolation Encoder The PCI-9222/PCI-9223 features a combination of data acquisition and simple motion control with support for two channel encoder input sets which provide an alternative for step motor or servo motor's position feedback. The encoder sets are assigned in CN2.
DefinitionPin #Definition
3468
......
E24V943NC
EGND842NC
IEA0+741IEA1+
IEA0-640IEA1-
IEB0+539IEB1+
IEB0-438IEB1-
IEZ0+337IEZ1+
IEZ0-236IEZ1-
IORG0135IORG1
Table 4-7: Encoder Pins in CN2 # Encoder Isolation Input Module Figure 4-30 illustrates the encoder isolation phase A, phase B and phase Z inputs module with 2500 Vrms protection. ![The flowchart depicts an interface circuit with inputs on the left and an output on the right.\n\n**Labeled Blocks and Inputs:**\n* **Top Input:** 'Encoder phase A+, phase B+, phase Z+ Input' points to a light blue rectangular block labeled '470 ohm Resistor'.\n* **Bottom Input:** 'Encoder phase A-, phase B-, phase Z- Input' points to a wire entering the bottom of a large central rectangular block.\n* **Central Block:** A large rectangle containing two internal components:\n * A **phototransistor symbol** (a triangle pointing down with inward-pointing arrows) on the left.\n * A **buffer/inverter symbol** (a triangle pointing right with a small circle at the output) on the right.\n * Two arrows point from the phototransistor symbol towards the buffer/inverter symbol.\n\n**Connections:**\n* **Top Path:** The output of the '470 ohm Resistor' connects to the top input of the central block. Inside the block, this wire splits to connect to:\n * The collector of the phototransistor symbol.\n * The input of the buffer/inverter symbol.\n * A terminal labeled 'Internal logic Power' (connected to a circle).\n* **Bottom Path:** The 'Encoder phase A-, phase B-, phase Z- Input' wire enters the bottom of the central block and connects to:\n * The emitter of the phototransistor symbol.\n * A terminal labeled 'Internal Ground' (connected to a ground symbol).\n* **Output:** The output of the buffer/inverter symbol connects to the text 'Internal Signal to FPGA'.](.pci-9222-9223-manual-10/f6535af8d6f047957e5d561ad894722f363b45f090501a239dd8f0d644c276ce.jpg) Figure 4-30: Encoder Isolation Input Module The Encoder OGRx input is different from the encoder phase input since you need to add an external +24V power to drive the photo-couple. Figure 4-31 shows the OGRx input. ![Based on the provided flowchart/block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n* **4.7K Resistor**: A vertical rectangular block.\n* **Central Box**: A large rectangular enclosure containing a phototransistor symbol (transistor with arrows pointing towards the base) and an inverter (triangle with a bubble).\n* **External +24V power**: A terminal point.\n* **Internal logic Power**: A terminal point.\n* **Encoder ORGx**: An input arrow.\n* **Internal Signal to FPGA**: An output arrow.\n* **Internal Ground**: A ground symbol terminal.\n\n**Connections:**\n* **External +24V power** connects to the top of the **4.7K Resistor**.\n* The bottom of the **4.7K Resistor** connects to the top-left side of the **Central Box**.\n* **Encoder ORGx** connects to the bottom-left side of the **Central Box**.\n* **Internal logic Power** connects to the top-right side of the **Central Box**.\n* **Internal Ground** connects to the bottom-right side of the **Central Box**.\n* **Internal Signal to FPGA** is the output originating from the right side of the **Central Box** (specifically from the inverter inside).](.pci-9222-9223-manual-10/058be09163f59cafbf78777fff2af49098cbbfeafc843a316261344ee978cc93.jpg) Figure 4-31: Encoder OGRx Input # CW/CCW Encoder Mode When GPTC is set to CW/CCW encoder mode and when the input EAx is connected to CW source signal and EBx is connected to CCW source signal, pulses from EAx will cause the counter to counter up and spin the motor clockwise. Otherwise, pulses from EBx will cause the counter to counter down and spin the motor counterclockwise. Figure 4-32 shows the increase/decrease of counter value in CW or CCW encoder mode. ![CW\nCCW\nEA0/EA1\nEB0/EB1\nCount Value 0 1 2 3 4 5 6 7 8 9 7 6 5 4 3 2](.pci-9222-9223-manual-10/9dcbd4685bdfbab8f78795fbd61f5a19729719ad1a5323967fccdca05e524aa5.jpg) Figure 4-32: CW/CCW Encoder Timing # X1 Encoder Mode In X1 encoder mode, if phase A (EA0/EA1) is advanced of phase B (EB0/EB1) in a quadrature cycle, the increment of counter value will be 1. Otherwise, if phase B is advanced of phase A in a quadrature cycle, the decrement of counter value will also be 1. Figure 4-33 shows a quadrature cycle and the increment and decrement of counter value in X1 encoder mode. When phase A leads phase B, the counter value increases on the first rising edge of CLK after phase A goes high. When phase B leads phase A, the counter value decreases on the first rising edge of CLK after phase A goes low. ![Phase A\nPhase B\nCLK\nCount Value 0 1 1 2 2 3 3 2 2 1](.pci-9222-9223-manual-10/0db3dc22e05fdf242d5a6c1bdb662691e1cacd986f0d0c9bba61c7f939e5732a.jpg) Figure 4-33: X1 Encoder Mode # X2 Encoder Mode This mode is similar to X1 Encoder Mode, except that the amount of counter value increases or decreases by two. Refer to Figure 4-34. ![Phase A\nPhase B\nCLK\nCount Value 0 1 2 3 4 5 5 4 3 2 1](.pci-9222-9223-manual-10/b072801c23b4196260a45d4322458b84db333b1afd4a172bfac4da3a8c254fd7.jpg) Figure 4-34: X2 Encoder Mode # X4 Encoder Mode This mode is similar to X1 Encoder Mode, except that the amount of counter value increases or decreases by four. Refer to Figure 4-35. ![| Time | Phase A | Phase B | CLK |\n|------|---------|---------|-----|\n| 0 | Yes | No | Yes |\n| 1 | Yes | No | Yes |\n| 2 | Yes | No | Yes |\n| 3 | Yes | No | Yes |\n| 4 | Yes | No | Yes |\n| 5 | Yes | No | Yes |\n| 6 | Yes | No | Yes |\n| 7 | Yes | No | Yes |\n| 8 | Yes | No | Yes |\n| 9 | Yes | No | Yes |\n| 8 | Yes | Yes | Yes |\n| 7 | Yes | Yes | Yes |\n| 6 | Yes | Yes | Yes |\n| 5 | Yes | Yes | Yes |\n| 4 | Yes | Yes | Yes |\n| 3 | Yes | Yes | Yes |\n| 2 | Yes | Yes | Yes |\n| 1 | Yes | Yes | Yes |\n| 0 | Yes | Yes | Yes |](.pci-9222-9223-manual-10/67f01a3573e952cf90654b23e58ce501c091f7bc0c5085c0a767bbd39251974f.jpg) Figure 4-35: X4 Encoder Mode # Phase Z Each encoder mode may use a third phase, phase Z, that is also frequently used for the index phase. You may decide if the counter needs to be reloaded a specified value when phase Z is at a logic high level with phase A and B at a specific logic condition. You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z. Otherwise, the counter does not reload. In Figure 4-36, the reload phase is when the logic level of phase A is high, phase B is low, and phase Z is high in X1 Encoder Mode. In addition, reloading takes higher priority than increment or decrement of counter value. The reload occurs within one maximum CLK period after the reload phase becomes true. After the counter value is reloaded, the counter continues to count as before. ![| Phase | Count Value |\n|-------|-------------|\n| Phase A | 0 |\n| Phase B | 1 |\n| Phase Z | 2 |\n| CLK | 3 |](.pci-9222-9223-manual-10/fdf9bfbbf8f797d1984bd7ab5c4b4cbb79077c1eb16fa332ad2815b4e970e69b.jpg) Figure 4-36: Phase Z # Original Signal (ORGx) Original Signal (ORG0/ORG2/ORG1) is used with phase Z. With ORG enabled, a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle. When you use ORG signal if it is at a low level and phase Z is at a high level, then counter reload is ignored. # 4.6 Trigger Sources The PCI-9222/PCI-9223 supports two trigger sources for analog input, analog output, and digital waveform acquisition/generation: software trigger and external digital trigger. # Software Trigger This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function calls to begin data acquisition. # External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the PCI-9222/PCI-9223 function I/O. You can set any DI line as external trigger pin. You may also easily program the trigger polarity via the ADLINK software drivers. Take note that the signal level of the external digital trigger signals should be TTL-compatible with a minimum 25 ns pulse. # NOTE Digital waveform acquisition/generation only supports rising-edge trigger. You can not set the polarity using the software driver. ![Positive-edge trigger event occurs\nNegative-edge trigger event occurs](.pci-9222-9223-manual-10/4356303d51e8bbbb5b774585a3dcc04b3a781c4affb1941fe52838234540d888.jpg) Figure 4-37: External Digital Trigger # 5 Calibration This chapter introduces the card calibration process to minimize AD measurement errors and DA output errors. # 5.1 Loading Calibration Constants The PCI-9222/PCI-9223 is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware are written to the onboard EEPROM. TrimDACs firmware is the algorithm in the FPGA. Loading calibration constants is the process of loading the values of TrimDACs firmware stored in the onboard EEPROM. ADKLINK provides a software utility that automatically reads the calibration constants, if necessary. There is a dedicated space for storing calibration constants in the EEPROM. In addition to the default bank of factory calibration constants, there is one user-utilization bank. This bank allows you to load the TrimDACs firmware values either from the original factory calibration or from a subsequently-performed calibration. Because of the fact that measurements and outputs errors may vary depending on time and temperature, it is recommended that you calibrate the card when it is integrated in your computing environment. The auto-calibration function is presented in the following sections. # 5.2 Auto-calibration Through the PCI-9222/PCI-9223 auto-calibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices. The PCI-9222/PCI-9223 comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software. The calibration constant is memorized after this measurement. We do not recommend adjustment of the onboard calibration reference except when an ultra-precision calibrator is available. # 5.3 Saving Calibration Constants Factory-calibrated constants are permanently stored in a bank of the onboard EEPROM and may not be modified. When you re-calibrate the device, the software stores the new constants in a user-configurable section of the EEPROM. To return a device to its initial factory calibration settings, the software can copy the factory calibrated constants to the user-configurable section of the EEPROM. When auto-calibration is completed, you can save the new calibration constants to the user-configurable banks in the EEPROM. The date and the temperature when you ran auto-calibration is saved with the calibration constants. You can store three sets of calibration constants according to three different environments and re-load the calibration constants later. # NOTES - Warm the card up for at least 15 minutes before initiating auto-calibration. - Remove the cable before auto-calibrating the card since the DA outputs are changed during the process. # Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully. 1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/. 2. All ADLINK products come with a limited two-year warranty, one year for products bought in China: The warranty period starts on the day the product is shipped from ADLINK's factory. ▶ Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty. For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for any loss of data. ▶ Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user. For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form. 3. Our repair service is not covered by ADLINK's guarantee in the following situations: ▶ Damage caused by not following instructions in the User's Manual. ▶ Damage caused by carelessness on the user's part during product transportation. ▶ Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. ▶ Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals). ▶ Damage caused by leakage of battery fluid during or after change of batteries by customer/user. ▶ Damage from improper repair by unauthorized ADLINK technicians. ▶ Products with altered and/or damaged serial numbers are not entitled to our service. ▶ This warranty is not transferable or extendible. ▶ Other categories not protected under our warranty. 4. Customers are responsible for shipping costs to transport damaged products to our company or sales office. 5. To ensure the speed and quality of product repair, please download an RMA application form from our company website: http://rma.adlinktech.com/policy. Damaged products with attached RMA forms receive priority. If you have any further questions, please email our FAE staff: service@adlinktech.com. [🔗 Link to the original document](.pci-9222-9223-manual-10/pci-9222-9223-manual-10.pdf)