# PCI-9527

24-Bit High Resolution Dynamic Signal

Acquisition and Generation

User’s Manual

Manual Revision: 2.00

Revision Date: November 26, 2010

Part No: 50-11241-1000

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# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2010/11/26</td><td>Document CreatedInitial Release</td></tr></table>

# Preface

# Copyright 2010 ADLINK TECHNOLOGY INC.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

PC, PS/2, and VGA are registered trademarks of International Business Machines Corp. Borland®, Borland® C, C++ Builder®, and Delphi® are registered trademarks of the Borland Software Corporation. LabVIEW™ is a trademark of National Instruments Corporation. Microsoft®, Visual Basic®, Visual C++®, Windows®

98, Windows® NT, Windows® 2000, Windows® XP, and Windows® Vista® are registered trademarks of Microsoft® Corporation. PCI™, is a registered trademark of the Peripheral Component Interconnect Special Interest Group (PCI-SIG).

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

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NOTE:

Additional information, aids, and tips that help users perform tasks.

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CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

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WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan ؀קᗼխࡉؑ৬ԫሁ 166 ᇆ 9 ᑔ

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

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Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: Ϟ⍋Ꮦ⌺ϰᮄऎᓴ∳催⾥ᡔುऎ㢇᯹䏃 300 ো(201203) 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China

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# ADLINK Technology Beijing

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Email: market@adlinktech.com

# ADLINK Technology Shenzhen

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Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

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Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

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Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

	

Address: 151-0072 1-1-2 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan

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Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 昢殾柢 昢爎割 昢爎壟 1506-25 穢壊 B/D 2 猻 2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu, Seoul 137-070, Korea

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Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

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Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India

Tel: +91-80-65605817

Fax: +91-80-22443548

Email: india@adlinktech.com

# Table of Contents

# 1 Introduction .........

1.1 Features...... 2
1.2 Applications .... 2
1.3 Specifications.... 3

1.3.1 Analog Input ... 3
1.3.2 Analog Output..
1.3.3 Triggers, Timebase.... 9
1.3.4 General Specifications.. .. 10

1.4 Software Support .. . 11

1.4.1 Software Support.. .. 11
1.4.2 Programming Library .. .. 11
1.4.3 DSA-DASK ... .... 11

# 2 Getting Started ........ 1 3

2.1 Installation Environment . 1 3
2.2 Package Contents .... 15
2.3 Device Layout and IO Connectors... 1 6
2.4 Installing the Module... 17
2.5 Signal Connection.... 18

2.5.1 BNC Connector Polarity . .. 18
2.5.2 Analog Input Connection .. .. 18
2.5.3 Analog Output Connection . .. 19

# 3 Operation Theory ............ .... 21

3.1 Functional Block Diagram.. 21
3.2 Analog Input Channel . 22

3.2.1 Analog Input Front-End Configuration ..... . 22
3.2.2 Input Range and Data Format ... .. 24
3.2.3 ADC and Analog Input Filter.... .. 25
3.2.4 FIFO and DMA Transfer For Analog Input ............... 26

# 3.3 Analog Output Channel.. 28

3.3.1 Analog Output Front-End Configuration ........ .. 28
3.3.2 Output Range and Data Format .. .. 29
3.3.3 DAC and Analog Output Filter .... .. 29
3.3.4 FIFO and DMA Transfer For Analog Output............. 30

# 3.4 Trigger Source and Trigger Mode... . 31

3.4.1 Trigger Sources .... .. 31
3.4.2 Trigger Mode .. .. 33

# 3.5 ADC and DAC Timing Control . 3 5

3.5.1 Timebase Architecture... .. 35
3.5.2 DDS Timing VS ADC/DAC Relationship.......... .. 35
3.5.3 Timing Constraint When AI and AO Enabled Simultaneously. . 36
3.5.4 Filter Delay in ADC and DAC. . 37

# 4 Calibration ......... .. 39

4.1 Calibration Constant . 39
4.2 Auto-Calibration ..... 40
4.3 Offset Error Compensation During AI Sampling Rate Change .... 40

# List of Figures

Figure 1-1: PCI-9527 Product Image .
Figure 1-2: Analog Input Channel Bandwidth, ±10 V Input Range .... 5
Figure 1-3: Magnitude Response of AC Couple of Input Channel..... 6
Figure 3-1: Linked List of PCI Address DMA Descriptors ................ 27
Figure 3-2: Trigger Architecture of the PCI-9527.. .. 31
Figure 3-3: Analog Trigger Conditions . . 32
Figure 3-4: Post-trigger Acquisition / Waveform Generation............ 33
Figure 3-5: Delay Trigger Mode Acquisition / Waveform Generation.. . 34
Figure 3-6: PCI-9527 Timebase Architecture... . 35

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# List of Tables

Table 1-1: Channel Characteristics.. 3

Table 1-2: Crosstalk.. 4

Table 1-3: Transfer Characteristics.. 4

Table 1-4: Analog Input Channel Bandwidth 4

Table 1-5: AC Coupling... . 5

Table 1-6: Integrated Electronic Piezoelectric (IEPE). . 6

Table 1-7: Channel Characteristics.. 7

Table 1-8: AO DC Accuracy... 7

Table 1-9: Output Impedance ... 8

Table 1-10: AO Dynamic Characteristics... 8

Table 1-11: Triggers.. . 9

Table 1-12: Analog Trigger . . 9

Table 1-13: Digital Trigger . . 9

Table 1-14: Timebase.. 9

Table 1-15: Bus and Physical Specifications.. . 10

Table 1-16: Environment Requirements . 10

Table 1-17: Calibration.. . 10

Table 1-18: Power Consumption . .. 10

Table 2-1: Analog Input Connection . . 18

Table 2-2: Analog Output Connection... . 19

Table 3-1: Input Configurations... . 22

Table 3-2: Input Range and Data Format .. . 24

Table 3-3: ADC Sample Rates VS DSS Outpu Clock.... ... 25

Table 3-4: Output Configuration.. .. 28

Table 3-5: Digital Input Code and Analog Output Range.. ... 29

Table 3-6: DAC (Digital-to-Analog Converter) . . 29

Table 3-7: Timing Relationship of the ADC, DAC and DDS Clock . 35

Table 3-8: ADC Filter Delay.. . 37

Table 3-9: DAC Filter Delay.. .. 37

Table 4-1: Offset Compensation Time Required for Different Sampling Rates... . 40

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# 1 Introduction

The PCI-9527 is a high-performance, 2-CH analog input and 2-CH analog output dynamic signal acquisition board. This board is specifically designed for use in audio testing, acoustic measurement, and vibration analysis applications.

The PCI-9527 features two 24-bit simultaneous sampling analog input channels. The 24-bit sigma-delta ADC provides a sampling rate up to 432 KS/s at high resolutions, making it idea for higher bandwidth dynamic signal measurements. The sampling rate can be adjusted by setting the onboard DDS clock source to an appropriate frequency. All channels are sampled simultaneously and accept an input range from ±40 V to ±0.316 V. The PCI-9527 analog input supports software selectable AC or DC coupling and 4 mA bias current for integrated electronic piezoelectric (IEPE) sensors.

The PCI-9527 also has two channels of 24-bit resolution, high fidelity analog output. The outputs occur simultaneously at software programmable rates up to 216 KS/s. A software programmable output range of 0.1 V, 1 V, and 10 V is available on the output channels.

![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.pci-9527-manual-50-11241-1000-004/eb39e17af5e66d257750d068f3de683eea66912991543e352d42da5474e83af1.jpg)

Figure 1-1: PCI-9527 Product Image

# 1.1 Features

 24-Bit Sigma-Delta ADC and DAC
 2-CH simultaneous sampling analog inputs
 2-CH simultaneous updated analog outputs
 432 KS/s maximum ADC sampling rate with software programmable rate
 216 KS/s maximum DAC sampling rate with software programmable rate
 Programmable input range: $\pm 4 0 \vee , \pm 1 0 \vee , \pm 3 . 1 6 \vee , \pm 1 \vee ,$ ±0.316 V
 Programmable output range: $\pm 0 . 1 \lor , \pm 1 \lor , \pm 1 0 \lor$
 AC or DC input coupling, software selectable
 A trigger I/O connector for external digital trigger signal
 Support IEPE output on each analog input, software-configurable

# 1.2 Applications

 Audio signal testing
 Acoustic measurements
 Environment noise testing
 Vibration test
 Machine conditioning monitoring

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td colspan="2">Channel Characteristics</td></tr><tr><td>Number of channels</td><td>2</td></tr><tr><td>Input configurations</td><td>Differential or pseudodifferential</td></tr><tr><td>Input coupling</td><td>AC or DC, software selectable</td></tr><tr><td>ADC resolution</td><td>24-bits</td></tr><tr><td>ADC type</td><td>Delta-sigma</td></tr><tr><td>Sample rates (fs)</td><td>432KS/s maximum, 2KS/s to 432KS/s in 454.7uS/s increments, maximum</td></tr><tr><td>FIFO buffer size</td><td>Total 4096 samples shared for AI channels</td></tr><tr><td>Data transfers</td><td>Direct memory access (DMA)</td></tr><tr><td>Input signal range</td><td>±40V±10V±3.16V±1V±0.316V</td></tr><tr><td>Input Common Mode Range</td><td>±10V for both Differential and Pseudodifferential Configuration</td></tr><tr><td>Overvoltage protection</td><td>Differential input: ±40 VpkPseudo-Differential► Positive terminal: ±40 Vpk► Negative terminal: ±10 Vpk</td></tr><tr><td>Input impedance</td><td>Differential ConfigurationBetween (+) and GND: 1MΩBetween (-) and GND: 1MΩPseudodifferential ConfigurationBetween (+) and GND: 1MΩBetween (-) and GND: 50Ω</td></tr></table>

Table 1-1: Channel Characteristics

<table><tr><td colspan="2">Crosstalk</td></tr><tr><td></td><td>Crosstalk</td></tr><tr><td>Adjacent channel</td><td>&lt; -110 dB</td></tr><tr><td colspan="2">Measured with +/-10V inputInput signal is 18 Vpp @ 1KHz sine wave</td></tr></table>

Table 1-2: Crosstalk

<table><tr><td colspan="3">Transfer Characteristics</td></tr><tr><td rowspan="6">AI Offset Error</td><td>Input Range</td><td>Offset (±mV) @ Tcal ± 5°C</td></tr><tr><td>±40 V</td><td>120</td></tr><tr><td>±10 V</td><td>3</td></tr><tr><td>±3.16 V</td><td>1.4</td></tr><tr><td>±1 V</td><td>0.6</td></tr><tr><td>±0.316 V</td><td>0.5</td></tr><tr><td>AI Gain Error</td><td>±10 V</td><td>±0.5% max</td></tr></table>

Table 1-3: Transfer Characteristics

<table><tr><td colspan="2">Analog Input Channel Bandwidth</td></tr><tr><td>Input Range</td><td>Bandwidth (-3dB)</td></tr><tr><td>±40 V</td><td>30 KHz</td></tr><tr><td>±10 V, ±3.16 V, ±1 V, ±0.316 V</td><td>130 KHz</td></tr></table>

Table 1-4: Analog Input Channel Bandwidth

![| Frequency (Hz) | Magnitude (dB) |\n| -------------- | -------------- |\n| 1K             | 0              |\n| 10K            | 0              |\n| 100K           | -2             |\n| 100K+          | -8             |](.pci-9527-manual-50-11241-1000-004/b906847372868b8b42885a6f2cf1506f4e5880fc300219bd5b3c0b205cce8d31.jpg)

Figure 1-2: Analog Input Channel Bandwidth, ±10 V Input Range

<table><tr><td colspan="2">AC Coupling</td></tr><tr><td>-3 dB cutoff frequency</td><td>6.5 Hz</td></tr><tr><td>-0.1 dB cutoff frequency</td><td>40 Hz</td></tr></table>

Table 1-5: AC Coupling

![| Input Frequency (Hz) | dB refer to 100Hz |\n| -------------------- | ----------------- |\n| 1                    | -16               |\n| 2                    | -10               |\n| 3                    | -7                |\n| 4                    | -5                |\n| 5                    | -4                |\n| 6                    | -3                |\n| 7                    | -2                |\n| 8                    | -1.5              |\n| 9                    | -1                |\n| 10                   | -0.5              |\n| 20                   | -0.2              |\n| 30                   | -0.1              |\n| 40                   | -0.05             |\n| 50                   | -0.02             |\n| 60                   | -0.01             |\n| 70                   | -0.005            |\n| 80                   | -0.002            |\n| 90                   | -0.001            |\n| 100                  | 0                 |](.pci-9527-manual-50-11241-1000-004/826c0d8e32a395759caec4c40d20322df98a99f29eff74197b4e4fbf5e8afb4e.jpg)

Figure 1-3: Magnitude Response of AC Couple of Input Channel

<table><tr><td colspan="2">Integrated Electronic Piezoelectric (IEPE)</td></tr><tr><td>Current</td><td>4 mA, each channel independently software selectable</td></tr><tr><td>Compliance</td><td>24 V</td></tr></table>

Table 1-6: Integrated Electronic Piezoelectric (IEPE)

# 1.3.2 Analog Output

<table><tr><td colspan="2">Channel Characteristics</td></tr><tr><td>Number of channels</td><td>2</td></tr><tr><td>Output configurations</td><td>Differential or Pseudodifferential (50 to chassis ground), balance output, each channel independently software selectable</td></tr><tr><td>Output coupling</td><td>DC</td></tr><tr><td>DAC resolution</td><td>24-bits</td></tr><tr><td>DAC type</td><td>Delta-sigma</td></tr><tr><td>Update rates (fs)</td><td>1KS/s to 216 KS/s in 227.3 uS/s increments, maximum</td></tr><tr><td>Minimum working load</td><td>600 Ω</td></tr><tr><td>Short circuit protection</td><td>Indefinite protection between positive and negative</td></tr><tr><td>Onboard FIFO buffer size</td><td>2048 samples for each AO channel</td></tr><tr><td>Data transfers</td><td>Direct memory access (DMA)</td></tr><tr><td>Output signal range</td><td>±10 V±1 V±0.1 V</td></tr></table>

Table 1-7: Channel Characteristics

<table><tr><td colspan="3">AO DC Accuracy</td></tr><tr><td>Output Range</td><td>AO Offset Error, ±mV</td><td>AO Gain Error, ±%</td></tr><tr><td>±0.1 V</td><td>1</td><td>0.5</td></tr><tr><td>±1 V</td><td>1</td><td>0.4</td></tr><tr><td>±10 V</td><td>1</td><td>0.4</td></tr></table>

Table 1-8: AO DC Accuracy

<table><tr><td colspan="3">Output Impedance</td></tr><tr><td></td><td>Differential Configuration</td><td>Pseudodifferential Configuration</td></tr><tr><td>Between positive output and chassis ground</td><td>10 KΩ</td><td>10 KΩ</td></tr><tr><td>Between negative output and chassis ground</td><td>10 KΩ</td><td>50 Ω</td></tr><tr><td>Between positive and negative outputs</td><td>100 KΩ</td><td>100 KΩ</td></tr></table>

Table 1-9: Output Impedance

<table><tr><td colspan="2">AO Dynamic Characteristics</td></tr><tr><td>-3dB bandwidth, analog</td><td>110 KHz</td></tr><tr><td>AO THD + N</td><td>100 Hz - 20 KHz, 200 KS/s</td></tr><tr><td>±0.1V</td><td>-89 dB</td></tr><tr><td>±1 V</td><td>-101 dB</td></tr><tr><td>±10V</td><td>-101 dB</td></tr></table>

Table 1-10: AO Dynamic Characteristics

# 1.3.3 Triggers, Timebase

<table><tr><td colspan="2">Triggers</td></tr><tr><td>Trigger source</td><td>Software command, analog input, external digital trigger</td></tr><tr><td>Trigger mode</td><td>Post trigger, delay trigger</td></tr><tr><td>Trigger function</td><td>Start trigger</td></tr></table>

Table 1-11: Triggers

<table><tr><td colspan="2">Analog Trigger</td></tr><tr><td>Source</td><td>AI0 - AI1</td></tr><tr><td>Level</td><td>± Full-scale, programmable</td></tr><tr><td>Trigger conditions</td><td>Positive or negative</td></tr><tr><td>Trigger resolution</td><td>24-bit</td></tr></table>

Table 1-12: Analog Trigger

<table><tr><td colspan="2">Digital Trigger</td></tr><tr><td>Sources</td><td>Front panel SMB connector</td></tr><tr><td>Compatibility</td><td>5V TTL</td></tr><tr><td>Trigger polarity</td><td>Rising or falling edge</td></tr><tr><td>Pulse width</td><td>25 ns minimum</td></tr></table>

Table 1-13: Digital Trigger

<table><tr><td colspan="2">Timebase</td></tr><tr><td>Frequency</td><td>80 MHz</td></tr><tr><td>Internal Timebase Accuracy</td><td>±20 ppm, over operating temperature range</td></tr></table>

Table 1-14: Timebase

# 1.3.4 General Specifications

<table><tr><td colspan="2">Bus and Physical</td></tr><tr><td>Bus interface</td><td>32-bit / 33MHz PCI bus, support 3.3V and 5V PCI signaling</td></tr><tr><td>Physical dimension</td><td>PCI: Half-size PCI card106.6 mm (H) X 174.6 mm (W)</td></tr></table>

Table 1-15: Bus and Physical Specifications

<table><tr><td colspan="2">Environment Requirements</td></tr><tr><td>Operating environment</td><td>Temperature:0°C - 50°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td>Storage Environment</td><td>Temperature: -20°C - +80°CRelative humidity: 5% - 95%, non-condensing</td></tr></table>

Table 1-16: Environment Requirements

<table><tr><td colspan="2">Calibration</td></tr><tr><td>Onboard reference</td><td>+5V</td></tr><tr><td>Temperature coefficient</td><td> $\le \pm 5$  ppm/ $^{\circ}C$ </td></tr><tr><td>Self-Calibration</td><td>On software command, the PCI-9527 corrects offset and gain error relative to internal high stability, high precision reference</td></tr><tr><td>External Calibration Interval</td><td>1 year</td></tr><tr><td>Warm-up time</td><td>15 minutes</td></tr></table>

Table 1-17: Calibration

<table><tr><td colspan="3">Power Consumption</td></tr><tr><td>Power Rail</td><td>Standby Current (mA)</td><td>Full Load (mA)</td></tr><tr><td>+5V</td><td>720</td><td>1490</td></tr><tr><td>+12V</td><td>290</td><td>340</td></tr></table>

Table 1-18: Power Consumption

# 1.4 Software Support

# 1.4.1 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from program-ming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environment such as LabVIEW®.

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes only up to two hours. Contact your ADLINK dealers if you want to purchase the software license.

# 1.4.2 Programming Library

For customers who want to write their own programs, ADLINK provides the DSA-DASK function library that is compatible with various operating systems.

# 1.4.3 DSA-DASK

The DSA-DASK includes device drivers and DLL for Windows 98/ NT/2000/XP/Vista/Win7. DLL is binary compatible across Windows 98/ NT/2000/XP/Vista/Win. This means all applications developed with DSA-DASK are compatible with these Windows operating systems. The developing environment may be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The DSA-DASK user's and function reference manuals are in the ADLINK All-in-One CD. (\\Manual\Software Package\DSA-DASK).

 Supported Operating System

 Windows 7/ Vista/XP

 Linux

 Recommended Application Environments

 VB.NET/VC.NET/VB/VC++/BCB/Delphi

 Driver Support

 DAQPilot for Windows

 DAQPilot for LabVIEW

 DASK for Windows

 DASK/X for Linux

 Toolbox adapter for MATLAB

 Application Software

 Dynamic Signal Assistant

ADLINK’s Dynamic Signal Assistant is a ready-to-run software utility designed for dynamic signal acquisition modules, such as the PCI-9527. This software provides a windows-based configuration interface for setting parameters, in addition to a real-time visualized data display on the screen. An instrument-like user interface is also provided for basic waveform generation. The Dynamic Signal Assistant can also log data acquired from hardware modules. With the Dynamic Signal Assistant, signal acquisition and generation can be performed in just a few minutes without any programming effort.

![DIA - Analog Input\nFile Device Data Help\nDevice Input Output History\nCard Type: Virtual Card Sample Rate: 50000 AI Channel: 4 AO Channel: 2 Mode: Operate AI / AO Separately\nChannel configuration\nD1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80\nSample Rate\n50000 Hz\nView Unit\nB1Hz Sample\nAcquire Stop\nActive Log\nDynamic Setting\nGd dH dJ\nNAN db NAN db\nSNAO NAN db NAN db\nTHD 28.44 db 14.75 db\nENGB NAN ba NAN ba\nSFDR 31.11 db 19.07 db\nF1 31.37 db 16.79 db\nF2 NAN NAN\nF3 NAN NAN\nCalculate\nTime Domain\nVH\n-10.000\n0 1000 2000 4000 6000 8000\nSamples\nFreq Domain\n-50\n-100\n0.0 5.0 10.0 15.0 20.0 25.0\nKHz](.pci-9527-manual-50-11241-1000-004/24924a43d7412165ca0a798c3f07812bb6caaea22749dfd521fcbe79ee6dc311.jpg)

# 2 Getting Started

This chapter further describes the proper installation environment, installation procedures, its package contents and basic information users should be aware of.

![The image displays a graphic icon representing a document. It features a white sheet of paper with a folded top-left corner and faint horizontal lines running across the lower portion. A large, thick red checkmark is superimposed diagonally over the center of the paper.](.pci-9527-manual-50-11241-1000-004/28afaae97b7a0a6350d5df8c4e68c6458b475a331cdbf3b39629de3e6f1180a1.jpg)
NOTE:

Diagrams and images of equipment illustrated are used for reference only. Actual system configuration and specs may very.

# 2.1 Installation Environment

Whenever unpacking and preparing to install any equipment described in this manual, please refer to the Important Safety Instructions chapter of this manual.

Only install equipment in well lit areas on flat, sturdy surfaces with access to basic tools such as flat and cross head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

 Phillips (cross-head) screwdriver
 Flat-head screwdriver
 Anti-static Wrist Strap
 Anti-static mat

ADLINK PCI-9527 DAQ cards are electro-static sensitive equipment that can be easily damaged by static electricity. The equipment must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installing.

![A yellow triangular warning sign containing a black exclamation point. Below the triangle, the text 'CAUTION:' appears in black capital letters.](.pci-9527-manual-50-11241-1000-004/f1d8a5f9723b2d7f78c14abde07e410cd8a8c16b53d581a99968d4dc43cd9db1.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the antistatic bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

# 2.2 Package Contents

Before continuing, check the package contents for any damage and check if the following items are included in the packaging:

 PCI-9524 Multi-function Data Acquisition Card
 ADLINK All-in-one Compact Disc
 Software Installation Guide
 PCI-9524 User’s Manual

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

![The image shows a triangular warning sign. It features a dark red triangle with a white border containing a white exclamation point in the center. Below the triangle is the text 'WARNING:' printed in black capital letters.](.pci-9527-manual-50-11241-1000-004/720443444570badb84f8611d2317f5d8499a21633f013ee3ed136d561516f7e1.jpg)

WARNING: DO NOT install or apply power to equipment that is dam-aged or if there is missing/incomplete equipment. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance. Obtain authorization from your dealer before returning any product to ADLINK.

# 2.3 Device Layout and IO Connectors

![100.33\n58.05\n176.42\n106.68](.pci-9527-manual-50-11241-1000-004/f28a24cb5e3930d179e8fcb146382549cc8ae78c5bee76411ff7f397078ca8b9.jpg)

![AI0\nAI1\nAO0\nAO1\nExt.TRG](.pci-9527-manual-50-11241-1000-004/779331c75efe4aef47ab896cf9ed859e1aafd2f4e557cc44032b2a50570ac765.jpg)

# 2.4 Installing the Module

# To install the card:

1. Turn off the system/chassis and disconnect the power plug from the power source.
2. Remove the system/chassis cover.
3. Select the PCI slot that you intend to use, then remove the bracket opposite the slot, if any.
4. Align the card connectors (golden fingers) with the slot, then press the card firmly until the card is completely seated on the slot.
5. Secure the card to the chassis with a screw.
6. Replace the system/chassis cover.
7. Connect the power plug to a power source, then turn on the system/chassis.

# 2.5 Signal Connection

# 2.5.1 BNC Connector Polarity

The following figure shows the polarity of the BNC connector:

![Positive (+)\nNegative (-)](.pci-9527-manual-50-11241-1000-004/8d697318dbad76e89d98a16b39cb00f1e022cff2e11422f33453ad524c31fcc7.jpg)

# 2.5.2 Analog Input Connection

The PCI-9527 input channels can be configured as pseudo-differential or differential. For ground-reference signal source, user should configure analog input as differential. For floating signal sources, the analog input should be configured as a pseudo-differential input in order to provide a reference. In pseudodifferential configuration, the (-) port of AI is connected to ground through a 50 Ω resistor.

<table><tr><td>Signal Source Type</td><td>AI Channel Configuration</td></tr><tr><td>Floating</td><td>Pseudo Differential</td></tr><tr><td>Ground-Reference</td><td>Differential</td></tr></table>

Table 2-1: Analog Input Connection

# 2.5.3 Analog Output Connection

If the DUT inputs are ground-referenced, the differential output mode can be used for the elimination of measuring errors which caused by ground loops.

If the DUT inputs are in a floating system (ex. a floating earphone), setting to pseudo-differential output mode will provide a reference ground connected to the positive output of the BNC through a 50 Ω resistor.

<table><tr><td>DUT Input Reference Type</td><td>AO Channel Configuration</td></tr><tr><td>Floating</td><td>Pseudo Differential</td></tr><tr><td>Ground-Reference</td><td>Differential</td></tr></table>

Table 2-2: Analog Output Connection

# 3 Operation Theory

This chapter contains information about the PCI-9527 operating concepts, including analog input, analog output, triggering and timing.

3.1 Functional Block Diagram
![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   AI Channel 0 Front End Circuit\n*   AI Channel 1 Front End Circuit\n*   Calibration Mux and Reference Src\n*   AO Channel 0 Front End Circuit\n*   AO Channel 1 Front End Circuit\n*   ADC Interface\n*   Offset/Gain Correction\n*   FP FIFO\n*   PCI Interface\n*   Timing Control and Trigger In\n*   PF FIFO\n*   Offset/Gain Correction\n*   Local FIFO\n*   DAC Interface\n*   DDS\n*   PCI Bus\n\n**Connections:**\n*   **AI Input Chain:**\n    *   AI Channel 0 Front End Circuit connects to AI Channel 1 Front End Circuit.\n    *   AI Channel 1 Front End Circuit connects to Calibration Mux and Reference Src.\n    *   Calibration Mux and Reference Src connects to AO Channel 0 Front End Circuit.\n    *   AO Channel 0 Front End Circuit connects to AO Channel 1 Front End Circuit.\n*   **ADC Interface Inputs:**\n    *   AI Channel 0 Front End Circuit connects to ADC Interface.\n    *   AI Channel 1 Front End Circuit connects to ADC Interface.\n*   **DAC Interface Inputs:**\n    *   AO Channel 0 Front End Circuit connects to DAC Interface.\n    *   AO Channel 1 Front End Circuit connects to DAC Interface.\n*   **Top Data Path (ADC to PCI):**\n    *   ADC Interface connects to Offset/Gain Correction.\n    *   Offset/Gain Correction connects to FP FIFO.\n    *   FP FIFO connects to PCI Interface.\n*   **Bottom Data Path (PCI to DAC):**\n    *   PCI Interface connects to Timing Control and Trigger In.\n    *   Timing Control and Trigger In connects to PCI Interface.\n    *   Timing Control and Trigger In connects to PF FIFO.\n    *   PF FIFO connects to Offset/Gain Correction.\n    *   Offset/Gain Correction connects to Local FIFO.\n    *   Local FIFO connects to DAC Interface.\n*   **Control and Trigger Connections:**\n    *   Timing Control and Trigger In connects to ADC Interface.\n    *   Timing Control and Trigger In connects to DAC Interface.\n    *   Timing Control and Trigger In connects to Local FIFO.\n    *   DDS connects to Timing Control and Trigger In.\n    *   A clock/trigger source symbol connects to Timing Control and Trigger In.\n    *   PCI Bus connects to PCI Interface.](.pci-9527-manual-50-11241-1000-004/ae97f3033c26000288c3c426edba51499d2b17087d5c4b6c8779d4718ba42522.jpg)

# 3.2 Analog Input Channel

# 3.2.1 Analog Input Front-End Configuration

![10-24V @ 4mA (adjustable)\nIEPE\nx1 or x1/4\nx1\nx3.16\nx10\nx31.6\nAI+\nAI-\nCalibration\nSource\nADC\n+2.5V](.pci-9527-manual-50-11241-1000-004/dc52d597441e32a35fee67d22db76b8f08149bab9010ea28b266652d542a2339.jpg)

# Input Configuration, Differential or Pseudo Differential

The differential input mode provides the anode and cathode inputs of the BNC connector that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential input mode can be used for the common-mode noise rejection.

If the signal source is a floating signal, setting to pseudo-differential input mode will provide a reference ground connected to the cathode input of the BNC through a 50ohm resistor. This will prevent the floating source from drifting over the input common-mode range.

The recommended configurations for the signal sources are as followes.

<table><tr><td>Signal Source Type</td><td>Card Configuration</td></tr><tr><td>Floating</td><td>Pseudo Differential</td></tr><tr><td>Ground-Reference</td><td>Differential</td></tr></table>

Table 3-1: Input Configurations

# Input Coupling, DC Coupling or AC Coupling

The input coupling can be AC or DC. When you select DC coupling, the DC offset present in the input signal is pass to ADC. Use the DC coupling configuration if the signal source has a small amount of offset voltage or if the DC content of the signal is important.

When you select AC coupling, the DC offset present in the input signal is removed. Use the AC coupling configuration if the DC content of the input signals that you want to reject.

AC coupling enable a high pass R-C filter through the input signal path. The corner frequency (-3dB) is about 3Hz.

# Input for IEPE

For applications that require sensors such as accelerometer or microphone, PCI-9527 provides an excitation current source.

The common excitation current is usually between 4mA for these IEPE sensors. A DC voltage offset is generated because of the excitation current and sensor impedance. When enable the IEPE current sources, the PCI-9527 will set input configuration to AC coupling automatically.

# 3.2.2 Input Range and Data Format

When using an A/D converter, users should first know about the properties of the signal to be measured. Users can decide which channel to use and how to connect the signals to the card. Please refer to section 2.5 for signal connections.

The A/D acquisition is initiated by a trigger source; users must decide how to trigger the A/D conversion. The data acquisition will start once a trigger condition is matched. After the end of an A/D conversion, the A/D data is buffered in a Data FIFO. The A/D data can now be transferred into the PC's memory for further processing.

The following table illustrates the idea transfer characteristics of various input ranges of the PCI-9527. The data format of the PCI-9527 is 2’s complement.

<table><tr><td>Description</td><td colspan="5">Bipolar Analog Input Range</td><td>Digital Code</td></tr><tr><td>Full-scale Range</td><td>±40V</td><td>±10V</td><td>±3.1622776V</td><td>±1V</td><td>±0.316227V</td><td></td></tr><tr><td>Least significant bit</td><td>4.76uV</td><td>1.19uV</td><td>0.37uV</td><td>0.119uV</td><td>0.037uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>39.99999952V</td><td>9.99999881V</td><td>3.1622773V</td><td>0.999999881V</td><td>0.31622773V</td><td>7FFFFFF</td></tr><tr><td>Midscale +1LSB</td><td>4.76uV</td><td>1.19uV</td><td>0.37uV</td><td>0.119uV</td><td>0.037uV</td><td>000001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>000000</td></tr><tr><td>Midscale -1LSB</td><td>-4.76uV</td><td>-1.19uV</td><td>-0.37uV</td><td>-0.119uV</td><td>-0.037uV</td><td>FFFFFF</td></tr><tr><td>-FSR</td><td>-40V</td><td>-10V</td><td>-3.1622776V</td><td>-1V</td><td>-0.31622776V</td><td>800000</td></tr></table>

Table 3-2: Input Range and Data Format

# 3.2.3 ADC and Analog Input Filter

# ADC (Analog-to-Digital Converter)

The ADCs on PCI-9527 are sigma-delta ADC which is very suitable for vibration, audio and acoustic measurement. The analog side of sigma-delta ADC is a 1-bit ADC. On digital side, it performs oversampling, noise shaping and digital filtering. For example, if desired sampling rate is 108KS/s, each ADC samples input signal at 6.912MS/s, 64 times the sampling rate. The 1-bit 6.912MS/s data streams from 1-bit ADC to its internal digital filter circuit to produce 24-bit data at 108KS/s. The noise shaping removes quantization noise from low frequency to high frequency. With the digital filter at the last stage, the digital filter improves the ADC resolution and removes high frequency quantization noise.

The relationship between ADC sample rate and DDS output clock is as followed

<table><tr><td>Sampling Rate</td><td>2 K - 54 KHz</td><td>54 K - 108 KHz</td><td>108 K-216 KHz</td><td>216 K - 432 KHz</td></tr><tr><td>DDS CLK</td><td>512 K - 13.824 MHz</td><td>6.912 M-13.824 MHz</td><td>6.912 M-13.824 MHz</td><td>13.824 M - 27.648 MHz</td></tr></table>

Table 3-3: ADC Sample Rates VS DSS Outpu Clock

# Filter

Each channel has a two-pole low pass filters. The filters limit the bandwidth of the signal path and is useful for rejecting out of band noise.

# 3.2.4 FIFO and DMA Transfer For Analog Input

# FIFO

There is only one FIFO implemented on PCI-9527 for analog input data storage. The FIFO depth is 4096 samples. The 4096 samples are shared for both AI channels. When user enables only one AI channel, the 4096-sample-FIFO is used for one channel data storage. When user enables two AI channels, the 4096-sample-FIFO shares for both channel.

# Bus-mastering DMA Data Transfer

PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI bus bandwidth, and also to improve bus efficiency. The bus-mastering controller controls the PCI bus when it becomes the master of which, and the host CPU is free of burden since data are directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

By using a high-level programming library for high speed DMA data acquisition, users simply need to assign the sampling period and the number of conversions into their specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, and so on, it is difficult to allocate a large continuous memory block. Therefore, the PCI controller provides DMA transfer with scatter-gather function to link non-continuous memory blocks into a linked list so users can transfer large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of your system. Users can also link descriptor nodes circularly to achieve a multibuffered DMA. Figure 4-6 illustrates a linked list that is comprised of three DMA descriptors. Each descriptor contains a PCI address,

PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space.

![The diagram illustrates a data flow with five main blocks:\n\n**Bottom Section:**\n*   A block labeled **'Local Memory (FIFO)'** has an arrow pointing upward to a block labeled **'PCI Bus'**.\n\n**Top Section:**\n*   The **'PCI Bus'** block has an arrow pointing upward to a central block containing the text:\n    *   **'PCI Address'**\n    *   **'Dual Address'**\n    *   **'Transfer Size'**\n    *   **'Next Descriptor'**\n*   To the left of this central block is a block containing:\n    *   **'First PCI Address'**\n    *   **'First Dual Address'**\n    *   **'Transfer Size'**\n    *   **'Next Descriptor'**\n    *   An arrow points from this left block to the central block.\n*   To the right of the central block is a third block containing the same list as the central block:\n    *   **'PCI Address'**\n    *   **'Dual Address'**\n    *   **'Transfer Size'**\n    *   **'Next Descriptor'**\n    *   An arrow points from the central block to this right block.](.pci-9527-manual-50-11241-1000-004/05f3ca74913d4d0efa319ff8f7ec3b8a632691762f4ecea4d5fb02a8b80b0d1c.jpg)

Figure 3-1: Linked List of PCI Address DMA Descriptors

# 3.3 Analog Output Channel

![Based on the provided block diagram, here is the accurate and concise description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   DAC CH0\n*   IV Converter\n*   Attenuator x1 x0.1 x0.01\n*   Differential Driver\n*   XLR Switch\n*   DAC CH1\n*   AO CH0+\n*   AO CH0- / AOGND\n*   AO CH0 GND\n*   AO CH1+/ AO CH0-\n*   AO CH1- / AOGND\n*   AO CH1 GND\n*   CHASSIS GND\n\n**Connections and Flow:**\nThe diagram depicts two parallel signal paths (top and bottom) flowing from left to right:\n\n1.  **Input Stage:**\n    *   **DAC CH0** connects to an **IV Converter** (two triangular symbols).\n    *   **DAC CH1** connects to an identical **IV Converter**.\n    *   Both IV Converters connect to blocks labeled **Attenuator x1 x0.1 x0.01**, which contain resistor networks and switches.\n\n2.  **Drive Stage:**\n    *   From each **Attenuator** block, signals pass through two buffer amplifiers (small triangles) and then into a large triangular amplifier labeled **Differential Driver**.\n\n3.  **Switching and Output Stage:**\n    *   The output of each **Differential Driver** connects to a vertical block labeled **XLR Switch**.\n    *   From the **XLR Switch**, connections go to a switch matrix block.\n    *   **Top Path Outputs:** The switch matrix connects to lines labeled **AO CH0+** and **AO CH0- / AOGND**.\n    *   **Bottom Path Outputs:** The switch matrix connects to lines labeled **AO CH1+/ AO CH0-** and **AO CH1- / AOGND**.\n\n4.  **Ground Connections:**\n    *   **AO CH0 GND** connects to ground via a resistor.\n    *   **AO CH1 GND** connects to ground via a resistor.\n    *   **CHASSIS GND** is shown connected to the bottom right of the circuit.](.pci-9527-manual-50-11241-1000-004/cc9ee81af97146e0ae9308f474e50b132cd1f7e0604d8c83baf1e22ceda412ff.jpg)

# 3.3.1 Analog Output Front-End Configuration

# Output Configuration - Differential, Pseudo Differential

The differential output mode provides the anode and cathode outputs of the BNC connector that respond to the DAC outputs voltage difference between them. If the DUT inputs are groundreferenced, the differential output mode can be used for the elimination of measuring errors which caused by ground loops.

If the DUT inputs are in a floating system (ex. a floating earphone), setting to pseudo-differential output mode will provide a reference ground connected to the cathode output of the BNC through a 50ohm resistor. This will prevent the floating system from drifting over its input common-mode range.

The recommended configurations respect to the input reference types of DUT are as followed.

<table><tr><td>DUT Input Reference Type</td><td>Card Configuration</td></tr><tr><td>Floating</td><td>Pseudo Differential</td></tr><tr><td>Ground-Reference</td><td>Differential</td></tr></table>

Table 3-4: Output Configuration

# 3.3.2 Output Range and Data Format

The following table illustrates the PCI-9527 idea transfer characteristics of various input codes versus output voltages. The data format of the PCI-9527 is two’s-complement.

<table><tr><td>Description</td><td>Digital Input Code</td><td colspan="3">Bipolar Analog Output</td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Full-scale Range</td><td></td><td>±10V</td><td>±1V</td><td>±0.1V</td></tr><tr><td>Least significant bit</td><td></td><td>1.19uV</td><td>0.119uV</td><td>0.012uV</td></tr><tr><td>FSR-1LSB</td><td>7FFFFFF</td><td>9.99999881V</td><td>0.999999881V</td><td>0.099999988V</td></tr><tr><td>Midscale +1LSB</td><td>000001</td><td>1.19uV</td><td>0.119uV</td><td>0.012uV</td></tr><tr><td>Midscale</td><td>000000</td><td>0V</td><td>0V</td><td>0V</td></tr><tr><td>Midscale -1LSB</td><td>FFFFFF</td><td>-1.19uV</td><td>-0.119uV</td><td>-0.012uV</td></tr><tr><td>-FSR</td><td>800000</td><td>-10V</td><td>-1V</td><td>-0.1V</td></tr></table>

Table 3-5: Digital Input Code and Analog Output Range

# 3.3.3 DAC and Analog Output Filter

# DAC (Digital-to-Analog Converter)

The DACs on PCI-9527 are two 24-bit delta-sigma DACs. It separates the sample rates into four regions between 1KS/s to 216KSps (table 3.3.1). Each region has different bandwidth of internal digital filter, this will optimize the DA dynamic performance over all sample rate region. For example, when setting at lower sample rate, the digital filter bandwidth is lower too. It improves SNR of output current and release the need for external analog low pass filter.

The relationship between DAC sample rate and DDS output clock is as followed

<table><tr><td>Update Rate</td><td>1K-27KHz</td><td>27K-54KHz</td><td>54K-108KHz</td><td>108K-216KHz</td></tr><tr><td>DDS CLK</td><td>512K-13.824MHz</td><td>6.912M-13.824MHz</td><td>6.912M-13.824MHz</td><td>13.824M-27.648MHz</td></tr></table>

Table 3-6: DAC (Digital-to-Analog Converter)

# Analog Front-End Filter

Each channel has a 3-pole low pass filter. The cutoff frequency is set at 110 KHz to limit the bandwidth of the signal path. This will mostly reject out of band images and noise.

# 3.3.4 FIFO and DMA Transfer For Analog Output

# FIFO

There are two FIFOs implemented on PCI-9527 for the analog output function. Each FIFO depth is 2048 samples.

# Bus-mastering DMA Data Transfer

For analog output operation, the data will be transferred from host PC memory to onboard FIFO by DMA transfer. Please refer to section 3.2.4 for detail description.

# 3.4 Trigger Source and Trigger Mode

This section describes information about triggering theory of operation. In PCI-9527, the operation of AI and AO share the same trigger source. Therefore, when user enables AI and AO operation simultaneously, the trigger signal is valid only when AI and AO are ready to receive trigger signal. For more detail in programming the PCI-9527, please refer to software operation manual.

# 3.4.1 Trigger Sources

![This flowchart depicts a signal routing and decision process, flowing from left to right:\n\n**Labeled Blocks/Sources:**\n*   **TRG Input SMB Connector** (shown with a ground symbol)\n*   **Trigger Source Mux** (a tall, vertical trapezoid)\n*   **Trigger Decision** (a square box)\n\n**Connections and Labels:**\n*   An arrow labeled **Software Trigger** points into the **Trigger Source Mux**.\n*   An arrow labeled **Digital Trigger Input** originates from the **TRG Input SMB Connector** and points into the **Trigger Source Mux**.\n*   An arrow labeled **AI CH0 Analog Trigger** points into the **Trigger Source Mux**.\n*   An arrow labeled **AI CH1 Analog Trigger** points into the **Trigger Source Mux**.\n*   A single arrow connects the **Trigger Source Mux** to the **Trigger Decision** block.\n*   An arrow exits the **Trigger Decision** block to the right, labeled **To Internal FPGA Circuit**.](.pci-9527-manual-50-11241-1000-004/6c8c92bc5bcc867975fcda1b7654bbbf4bdc1cdc9926f1503db40813ee597a1b.jpg)

Figure 3-2: Trigger Architecture of the PCI-9527

Within the PCI-9527, a trigger is a signal that starts the acquisition of data. When configuring the triggers, you have to decide where the trigger comes from. PCI-9527 supports internal software trigger, external digital trigger, as well as analog trigger.

# Software Trigger

The software trigger is generated by software command. The trigger asserts right after executing specified function calls to begin the operation.

# External Digital Trigger

An external digital trigger occurs when a TTL rising edge or a falling edge is detected at the SMB connector on the front panel. As illustrated in Figure x-x, the trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width is 25 ns.

# Analog Trigger

User can configure the PCI-9527 analog trigger circuitry to monitor one of analog input channels from which you acquire data. Selecting an analog input channel as the analog trigger channel does not influence the input channel acquisition operation. The analog trigger circuit generates an internal digital trigger signal based on the condition between analog signal and the trigger level you defined.

The trigger conditions for analog triggers is described as follows:

 Positive-slope trigger: The trigger event occurs when the analog input signal changes from a voltage that is lower than the specified trigger level to a voltage that is higher than the specified trigger level.
Negative-slope trigger: The trigger event occurs when the analog input signal changes from a voltage that is higher than the specified trigger level to a voltage that is lower than the specified trigger level.

![| Trigger Level | Event Occurrence |\n| ------------- | ---------------- |\n| Low           | Analog Signal    |\n| High          | Positive-Slope Trigger Event Occurs |\n| Low           | Negative-Slope Trigger Event Occurs |](.pci-9527-manual-50-11241-1000-004/45059747f735493c0941678ba5e1feff98c0f90eea95641199d32419d599b12a.jpg)

Figure 3-3: Analog Trigger Conditions

# 3.4.2 Trigger Mode

There are two trigger modes working with trigger sources to initiate different data acquisition timing when a trigger event occurs. The following trigger mode descriptions are applied to analog input and analog output functions.

 Post trigger mode acquisition/generation
 Delay trigger mode acquisition/generation

# Post Trigger Mode

If user configures the trigger mode as post trigger, following action begins right after the trigger conditions are met:

 The analog input channel acquires a programmed number of samples at a specified sampling rate.
The analog output channel output pre-defined voltage at a specified output rate.

![The diagram displays a timeline and three corresponding signal traces:\n\n**Timeline Section:**\n*   A horizontal line with an arrow at the right end labeled **'Time'**.\n*   Three vertical arrows point down to the timeline, labeled from left to right:\n    1.  **'Operation start'**\n    2.  **'Trigger Event Occurs Acquisition or waveform generation start'**\n    3.  **'Acquisition or waveform generation stop'**\n\n**Signal Section:**\nBelow the timeline, three signal lines are shown:\n*   **'Trigger'**: A horizontal line with a single rectangular pulse aligned with the 'Trigger Event Occurs' arrow.\n*   **'Analog Input'**: A horizontal line featuring a long, hexagonal-shaped block labeled **'N sampled data'**. This block spans the duration between the trigger event and the stop event.\n*   **'Analog Output'**: A horizontal line featuring a waveform (resembling two sine wave humps) that aligns vertically with the duration of the 'N sampled data' block.](.pci-9527-manual-50-11241-1000-004/0530a6a1ef892570ef629d5e85f11cb1185e43ebb42f73cb8ee21fce8b190110.jpg)

Figure 3-4: Post-trigger Acquisition / Waveform Generation

# Delay Trigger Mode

If user configures the trigger mode as delay trigger, user can specify a delay time from when the trigger event asserts to the beginning of the acquisition and waveform generation. The operation is illustrated below. The delay time is specified by a 32-bit counter value and the counter is clocking based on the PCI clock. So the maximum delay time is the period of PCI\_CLK X (232 - 1) while the minimum delay is the period of PCI\_CLK.

![This diagram is a timing chart illustrating the relationship between time markers and signal waveforms.\n\n**Top Timeline Section:**\nA horizontal arrow pointing right is labeled **'Time'**. Four downward arrows mark specific events on the timeline:\n1.  **'Operation start'**\n2.  **'Trigger Event Occurs'**\n3.  **'Acquisition or waveform generation start'**\n4.  **'Acquisition or waveform generation stop'**\n\nA horizontal arrow labeled **'Delay Time'** spans between the 'Trigger Event Occurs' point and the 'Acquisition or waveform generation start' point.\n\n**Signal Rows:**\nThree rows of waveforms are displayed below the timeline, labeled on the left:\n*   **Trigger:** Shows a square pulse aligned vertically with the 'Trigger Event Occurs' arrow.\n*   **Analog Input:** Shows a rectangular block labeled **'N sampled data'** that begins at the 'Acquisition or waveform generation start' mark.\n*   **Analog Output:** Shows a waveform curve that begins at the 'Acquisition or waveform generation start' mark and ends at the 'Acquisition or waveform generation stop' mark.](.pci-9527-manual-50-11241-1000-004/4ee7caccd2b29b907076453c5d7e01c881540ec7b93b16095341cff410018a15.jpg)

Figure 3-5: Delay Trigger Mode Acquisition / Waveform Generation

# 3.5 ADC and DAC Timing Control

# 3.5.1 Timebase Architecture

![The flowchart depicts a signal processing chain starting from the left and moving to the right:\n\n1.  **Onboard 125MHz Oscillator**: An oval block on the far left. An arrow points from it to a square block labeled **DDS**.\n2.  Below the **DDS** block, text reads: 'Resolution equal to 125MHz/2^32 = 0.029Hz'.\n3.  An arrow points from the **DDS** block to a triangle pointing right, labeled vertically as **1-to-4 Clock Buffer**.\n4.  The output of the buffer splits into four parallel lines:\n    *   The top line connects to a square labeled **1/2 Divider**, which then connects via an arrow to **DAC CH0**.\n    *   The second line connects to a square labeled **1/2 Divider**, which then connects via an arrow to **DAC CH1**.\n    *   The third line bypasses a divider and connects directly via an arrow to **ADC CH0**.\n    *   The bottom line bypasses a divider and connects directly via an arrow to **ADC CH1**.](.pci-9527-manual-50-11241-1000-004/d9ee8ff699bb7cb96f77561783c4610ce82c4dd522c7be609d4bc2182db2cd19.jpg)

Figure 3-6: PCI-9527 Timebase Architecture

To drive the sigma-delta ADC and DAC, an onboard timebase clock is applied. The timebase clock frequency is much higher than the sample rate and is produced from a DDS chip. The output frequency of DDS chip is programmable with excellent resolution.

# 3.5.2 DDS Timing VS ADC/DAC Relationship

<table><tr><td>Sampling Rate</td><td>2 K - 54 KHz</td><td>54 K - 108 KHz</td><td>108 K - 216 KHz</td><td>216 K - 432 KHz</td></tr><tr><td>Update Rate</td><td>1K-27KHz</td><td>27K-54KHz</td><td>54K-108KHz</td><td>108K-216KHz</td></tr><tr><td>DDS CLK</td><td>512K-13.824MHz</td><td>6.912M-13.824MHz</td><td>6.912M-13.824MHz</td><td>13.824M-27.648MHz</td></tr></table>

Table 3-7: Timing Relationship of the ADC, DAC and DDS Clock

# 3.5.3 Timing Constraint When AI and AO Enabled Simultaneously

As users can see in the section 3.5.1, the ADC and DAC shares the same Timebase source, i.e. the output of DDS clock. When users enable the operation of ADC and DAC at the same time, there are constraints that should be kept in mind:

1. The sampling rate of ADC and the update rate of DAC are related. When you set the sampling rate of ADC to certain value before configure DAC, the update rate of DAC will be limited and fixed corresponding to the sample rate of ADC. When you set the update rate of DAC to certain value before configure ADC, the sampling rate of DAC will be limited and fixed corresponding to the update rate of DAC. Please refer to following table for detail.
2. Because the ADC and DAC share the same trigger source, users have to configure both AI and AO operation before trigger event occurs. On the other words, trigger event cannot occur before AI & AO configuration complete.

# 3.5.4 Filter Delay in ADC and DAC

The filter delay indicates the time required fro data to propagate through a converter. Both AI and AO channels have filter delay due to the filter circuitry and the architecture of the converter. Following tables show the filter delay in ADC and DAC.

ADC Filter Delay

<table><tr><td>Update Rate (kS/s)</td><td>Filter Delay (Samples)</td></tr><tr><td>2K - 54KSps</td><td>12</td></tr><tr><td>54K-108KSps</td><td>7</td></tr><tr><td>108K-216KSps</td><td>5</td></tr><tr><td>216K-432KSps</td><td>5</td></tr></table>

Table 3-8: ADC Filter Delay

DAC Filter Delay

<table><tr><td>Update Rate (kS/s)</td><td>Filter Delay (Samples)</td></tr><tr><td>2K - 54KSps</td><td>43.4</td></tr><tr><td>54K-108KSps</td><td>87.5</td></tr><tr><td>108K-216KSps</td><td>176.8</td></tr></table>

Table 3-9: DAC Filter Delay

# 4 Calibration

This chapter introduces the calibration process to minimize analog input measurement errors and analog output errors.

# 4.1 Calibration Constant

The PCI-9527 is factory calibrated before shipment by writing the associated calibration constants to the onboard EEPROM. Every time the system boot up, the PCI-9527 driver will load these calibration constants that minimize the error in analog input path and analog output circuit. ADLINK provides a software API for calibrating the PCI-9527 whenever users want to calibrate the module.

The onboard EEPROM provides three banks for calibration constant storage in PCI-9527. The bank 0, which is the default bank, records the factory calibrated constants. Bank 0 is written protection that prevents any abnormal auto-calibration process occurred in user’s environment. The banks 1 and 2, which are user-defined space, provided for user’s self-calibration constants. When user execute the auto-calibration process, the calibration constants will be recorded to bank 1 or 2 based on user assignment.

When PCI-9527 boot up, the driver will access the calibration constants and set to hardware automatically. Without user’s assignment, the driver will load constants stored in bank 0. If user wants to load constants from bank 1 or 2, user can assign the bank 1 or 2 as the boot up bank through software. Once user re-assign the bank, driver will load the constants when user re-boot the system. This setting will be recorded to EEPROM and maintains no change until user modify it.

# 4.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, it is recommended to re-calibration when the card is installed in the user’s environment. The auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PCI-9527 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before begining the auto-calibration procedure, it is recommended to warm up the PCI-9527 for at least 20 minutes. Please remove cables before an auto-calibration procedure is initiated.

# 4.3 Offset Error Compensation During AI Sampling Rate Change

To provide better measurement results, PCI-9527 has an internal offset error compensation mechanism whenever user changes the AI sampling rate. Following table shows the compensation time required when setting different sampling rate. For example, when changing the sampling rate from 432 KS/s to 2 KS/s, 6.2 sec is required for offset compensation. Next time when the sampling rate is set between 2 KS/s and 53.999 KS/s, it is not necessary to have 6.2 sec for the offset compensation. Only the sampling rate set to different ranges will cause a compensation time.

Note that it is not necessary to add delay in you application. The PCI-9527 driver will automatically add the compensation time.

<table><tr><td>Sampling Rate</td><td>2 KS/s - 53.999 KS/s</td><td>54 KS/s - 107.999 KS/s</td><td>108 K/s - 215.999 KS/s</td><td>216 KS/s - 432 KS/s</td></tr><tr><td>Offset Compensation Time</td><td>6.2 sec</td><td>2.6 sec</td><td>1.3 sec</td><td>0.65 sec</td></tr></table>

Table 4-1: Offset Compensation Time Required for Different Sampling Rates

# 5 Calibration

This chapter introduces the calibration process to minimize AD measurement errors and DA output errors.

# 5.1 Loading Calibration Constants

The PCI-9524 is factory calibrated before shipment by writing the associated calibration constants of TrimDACs firmware to the onboard EEPROM. TrimDACs firmware is the algorithm in the FPGA. Loading calibration constants is the process of loading the values of TrimDACs firmware stored in the on-board EEPROM. ADKLINK provides a software utility for reading the calibration constants automatically if necessary.

There is a dedicated space for storing calibration constants in the EEPROM. In addition to the default bank of factory calibration constants, there are three more user-utilization banks. That means users can load TrimDAC firmware values either from the original factory calibration or from a calibration that is subsequently performed.

Because errors in measurements and outputs will vary with time and temperature, it is recommended to re-calibrate when the card is installed in the user's environment. The auto-calibration function used to minimize errors will be introduced in the next sub-section.

# 5.2 Auto-calibration

By using the auto-calibration feature of PCI-9524, the calibration software can measure and minimize measurement errors without external signal connections, reference voltages, or measurement devices.

PCI-9524 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line through a digital potentiometer and compensated in the software. The calibration constant is memorized after this measurement.

# 5.3 Saving Calibration Constants

Factory calibrated constants are permanently stored in a onboard EEPROM data bank and cannot be modified. When you re-calibrate the device, software stores new constants in a user-modifiable section of the EEPROM. To return a device to its initial factory calibration settings, software copies the factory calibrated constants to the user-modifiable section of the EEPROM. After an auto-calibration is completed, users can save the new calibration constants into the user-modifiable banks in the EEPROM. The date, temperature and calibration constants of the auto-calibration will be saved. Therefore users can store three sets of calibration constants according to three different environments and re-load the calibration constants later.

![The image displays an icon of a white sheet of paper with a folded upper-left corner. Faint horizontal lines run across the paper, resembling a document or list. A large, bold red checkmark is superimposed over the center of the document, indicating approval or completion.](.pci-9527-manual-50-11241-1000-004/05d223435edc4cfe03a7861c639558402cd8994e18dec39cf4def633b50b2fde.jpg)
NOTE:

1) Before auto-calibration starts, it is recommended to warm up the card for at least 25 minutes.
2) Please remove cables before an auto-calibration procedure is initiated because the DA outputs will change in the calibration process.

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this user’s manual for future reference.
? Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 When installing/mounting or uninstalling/removing equipment:

 Turn off power and unplug any power cords/cables.

 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);

 Make sure to use recommended voltage and power source settings;

 Always install and operate equipment near an easily accessible electrical socket-outlet;

 Secure the power cord (do not place any object on/over the power cord);

 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
 A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.pci-9527-manual-50-11241-1000-004/96516f89ddeb409c0b862e97916dd773218cb9da18a03eb8c89a240fd117059a.jpg)

# RISK OF EXPLOSION IF BATTERY IS REPLACED BY AN INCORECT TYPE. DISPOSE OF USED BATTERIES ACCORDING TO THEIR INSTRUCTIONS.

 Equipment must be serviced by authorized technicians when:

 The power cord or plug is damaged;
 Liquid has penetrated the equipment;
 It has been exposed to high humidity/moisture;
 It is not functioning or does not function according to the user’s manual;
 It has been dropped and/or damaged; and/or,
 It has an obvious sign of breakage.
[🔗 Link to the original document](.pci-9527-manual-50-11241-1000-004/pci-9527-manual-50-11241-1000-004.pdf)