# PCIe-7442

# 64CH Isolated DI/64CH Isolated DO PCIe Card User's Manual

![Green printed circuit board with ADLINK Technology Inc. branding and various electronic components (no readable text or symbols beyond branding)](.pcie-7442-50-11264-1000-200-en/c874f9b5e176030ef7e03706c5b9aa8b47d6208ed20c4d1cc3836e89cee1c532.jpg)

Manual Rev.: 2.00

Revision Date: Dec. 30, 2016

Part No: 50-11264-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>Dec. 30, 2016</td><td>Initial release</td></tr></table>

# Preface

# Copyright ©2016 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a white document icon with a folded top-left corner. Faint gray horizontal lines run across the paper, and a large, bold red checkmark is superimposed over the center.](.pcie-7442-50-11264-1000-200-en/cad83fd7c9fbac5edcc0ed5c7157ad0328977d114bd70a98750c01b241543098.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border featuring a black exclamation point in the center.](.pcie-7442-50-11264-1000-200-en/fc6816fd268d0d57661b6bf414ca8898b7cf44cca3558a93e2b3eedf71664415.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning symbol: a red equilateral triangle pointing upwards containing a large, white exclamation point (!) in its center. The background is white.](.pcie-7442-50-11264-1000-200-en/eaaced529f769714e2d883f1aafc1e443f944e16ee3abc86c2aac06f1d7efe24.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface.... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2
1.4 Software Support.... 3
PCIS-DASK .... 3
1.5 PCB Layout.... 4
1.6 Connectors 5
1.7 DI/O Connections 11
1.8 Digital Channels.... 12
1.9 Change of State (COS) Interrupt 14
1.10 Programmable Power Up DO Status.... 15
1.11 Watchdog Timer (WDT).... 15
1.12 Programmable TTL I/O 15

# 2 Getting Started 17

2.1 Unpacking Checklist 17
2.2 Installing the Card.... 17
2.3 Setting Board ID 18

# 3 I/O Registers 21

3.1 About PCIe Controller Registers.... 21
3.2 Isolated Digital Input Register 21

3.3 COS Interrupt Control Registers 21
3.4 COS Setup/Latch Registers.... 23
3.5 TTL I/O Setup, Status, DO, and DI Registers 24
3.6 Isolated Digital Output and Read Back Registers...... 25
3.7 Power-up DO Setup/Read Register 26
3.8 Watchdog Timer Load, Safety DO Setup/Read Back Registers 27
3.9 WDT INT Control, Hot-Reset, and Hold Control Register.. 28

# Important Safety Instructions.... 31

# Getting Service 35

# List of Figures

Figure 1-1: PCIe-7442 Board Layout 4
Figure 1-2: CN1/CN2 Connector....5
Figure 1-3: CN1A Connector ID....6
Figure 1-4: CN1B Connector ID 7
Figure 1-5: CN2A Connector ID 9
Figure 1-6: CN2B Connector ID....10
Figure 1-7: I/O Connector 11
Figure 1-8: Isolated Input Connection....13
Figure 1-9: Common Ground Connection....14

This page intentionally left blank.

# List of Tables

Table 1-1: PCIe-7442 Board Layout Legend .... 4
Table 1-2: CN1 Connector Pin Assignment....8
Table 1-3: CN2 Connector Pin Assignment....11
Table 1-4: JP3 I/O Connector Pin Assignment 12
Table 1-5: JP4 I/O Connector Pin Assignment 12
Table 2-1: Board ID Setting Conditions ...... 19

This page intentionally left blank.

# 1 Introduction

ADLINK'S PCIe-7442 is a basic digital I/O card for PCIe bus computers in industrial applications.

All digital input channels are identical non-polar and opto-isolated, suitable for collecting digital input in noisy environments. COS (Change of state) interrupt is supported, whereby when any digital input changes state, an interrupt is generated to allow management of the event. The input common junction can be common ground or common power, dependent on the user environment. Accordingly, the digital input can be a current source or current sink. When isolated digital output is ON, sink current is conducted through the transistors, and when OFF, none is.

![The image displays a white document icon featuring a folded top corner and faint horizontal lines. Superimposed over the document is a large, bold red checkmark.](.pcie-7442-50-11264-1000-200-en/63ff235b4b23d84558fb8113bf0211056b99eaf949bca7592b2937e959c5fcb2.jpg)
NOTE:

When multiple PCIe-7442 cards are installed, board ID provides convenient identification of each via switch jumper for quick troubleshooting and easy maintenance.

# 1.1 Features

▶ PCI Express x1, Plug and Play
▶ Isolated digital input channels
▶ Isolated digital output channels
▶ Change-of-state (COS) detection
▶ Channels with 28 V voltage protection
▶ Channels with 250 mA sink current
▶ Channels with digital output status read back
▶ DO value retained after hot system reset
▶ Programmable power-up DO status
▶ Programmable safety DO status function after WDT interrupt
▶ Watchdog timer
▶ TTL I/O channels
▶ 1250 VRMS isolation
▶ Board ID capability

# 1.2 Applications

▶ Industrial ON/OFF control
▶ External high power relay driving, signal switching
▶ Laboratory automation
▶ Industrial automation
▶ Switch contact status detection and limit switch monitoring & control systems

# 1.3 Specifications

<table><tr><td colspan="2">Digital Input</td></tr><tr><td>Input channels</td><td>64</td></tr><tr><td>Photocoupler</td><td>PC3H4</td></tr><tr><td>Input current</td><td>10 mA rated50 mA max. for isolated input</td></tr><tr><td>Input voltage</td><td>Up to 28V, non-polarityLogic Low: 0 to 1.5VLogic High: 5 to 28V</td></tr><tr><td>Input impedance</td><td>4.7kΩ@0.5W</td></tr><tr><td>Interrupt sources</td><td>Change of State (COS)</td></tr><tr><td>Isolated voltage</td><td>1,250 Vrms channel-to-system</td></tr><tr><td colspan="2">Digital Output</td></tr><tr><td>Output channels</td><td>64</td></tr><tr><td>Output type</td><td>Open drain power MOSFET driver</td></tr><tr><td>Output voltage</td><td>5V DC min, 40V DC maximum</td></tr><tr><td>Throughput</td><td>1kHz (CPU: DualCore Intel Pentium D 925,3.00GHz)</td></tr><tr><td>Isolated voltage</td><td>1,250 Vrms channel-to-system</td></tr><tr><td colspan="2">Isolated +5V Power Supply</td></tr><tr><td>Output voltage</td><td>+5V</td></tr><tr><td>Output current</td><td>100mA max. (@ 40°C)</td></tr><tr><td colspan="2">Physical</td></tr><tr><td>Dimensions</td><td>175 mm x 107 mm, standard PCIe half size</td></tr><tr><td>Operating temperature</td><td>0 to 60°C</td></tr><tr><td>Storage temperature</td><td>-20 to 80 °C</td></tr><tr><td>Humidity</td><td>5 to 95% non-condensing</td></tr><tr><td>Bus</td><td>1x PCI Express</td></tr><tr><td>Power consumption</td><td>+12V@170mA (typical) 300mA (Max.) +3.3V@ 1mA (typical) 1.5mA (Max.) (when all relays are activated simultaneously)</td></tr></table>

# 1.4 Software Support

ADLINK provides comprehensive software solutions for all system building requirements. In addition to programming libraries such as DLLs for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW®.

Ensure the driver and utility are installed before using the PCIe-7442.

# PCIS-DASK

PCIS-DASK consists of advanced 32/64-bit kernel drivers and SDK for customized DAQ application development, enabling detailed operations, superior performance, and reliability from data acquisition systems.

PCIS-DASK kernel drivers currently support Windows 7/8.1 OS.

# 1.5 PCB Layout

![The image displays an icon of a white document with a folded top-left corner and faint horizontal lines, overlaid with a large, bold red checkmark.](.pcie-7442-50-11264-1000-200-en/9a3f9dc7e3c5ac6712d60e07be4cf1b18926cc4c68586687fdef92e5db4e63d9.jpg)
NOTE:

All dimensions shown are in mm

![A\nB\nS1\nC\nD\nE](.pcie-7442-50-11264-1000-200-en/5e33e00ffbd64f794a80f73a8d45a2d8f856a29ba8e240ef98a5252ff56e1f6e.jpg)

Figure 1-1: PCIe-7442 Board Layout

<table><tr><td>A</td><td>JP4</td><td>16CH (TTL15 to 31) TTL I/O connector</td></tr><tr><td>B</td><td>JP3</td><td>16CH (TTL 0 to 15) TTL I/O connector</td></tr><tr><td>C</td><td>S1</td><td>Board ID DIP switch</td></tr><tr><td>D</td><td>CN2</td><td>64CH isolated digital output connector</td></tr><tr><td>E</td><td>CN1</td><td>64CH isolated digital input connector</td></tr></table>

Table 1-1: PCIe-7442 Board Layout Legend

# 1.6 Connectors

The PCIe-7442 is equipped with a 68-pin Dual port VHDCI connector, via CN1A, CN1B, CN2A, and CN2B.

![CN2B\nCN2A\nCN1B\nCN1A](.pcie-7442-50-11264-1000-200-en/c94dc239754f2328b34729af2c7dfa77d6775b6e01d7d5586da33a7355f4e16e.jpg)

Figure 1-2: CN1/CN2 Connector

<table><tr><td>IDI_0</td><td>A01</td><td>A35</td><td>IDI_8</td></tr><tr><td>IDI_1</td><td>A02</td><td>A36</td><td>IDI_9</td></tr><tr><td>IDI_2</td><td>A03</td><td>A37</td><td>IDI_10</td></tr><tr><td>IDI_3</td><td>A04</td><td>A38</td><td>IDI_11</td></tr></table>

<table><tr><td>IDI_4</td><td>A05</td><td>A39</td><td>IDI_12</td></tr><tr><td>IDI_5</td><td>A06</td><td>A40</td><td>IDI_13</td></tr><tr><td>IDI_6</td><td>A07</td><td>A41</td><td>IDI_14</td></tr><tr><td>IDI_7</td><td>A08</td><td>A42</td><td>IDI_15</td></tr><tr><td>COM1</td><td>A09</td><td>A43</td><td>COM2</td></tr><tr><td>COM1</td><td>A10</td><td>A44</td><td>COM2</td></tr><tr><td>COM1</td><td>A11</td><td>A45</td><td>COM2</td></tr><tr><td>COM1</td><td>A12</td><td>A46</td><td>COM2</td></tr><tr><td>COM1</td><td>A13</td><td>A47</td><td>COM2</td></tr><tr><td>COM1</td><td>A14</td><td>A48</td><td>COM2</td></tr><tr><td>COM1</td><td>A15</td><td>A49</td><td>COM2</td></tr><tr><td>COM1</td><td>A16</td><td>A50</td><td>COM2</td></tr><tr><td>N/C</td><td>A17</td><td>A51</td><td>N/C</td></tr><tr><td>IDI_16</td><td>A18</td><td>A52</td><td>IDI_24</td></tr><tr><td>IDI_17</td><td>A19</td><td>A53</td><td>IDI_25</td></tr><tr><td>IDI_18</td><td>A20</td><td>A54</td><td>IDI_26</td></tr><tr><td>IDI_19</td><td>A21</td><td>A55</td><td>IDI_27</td></tr><tr><td>IDI_20</td><td>A22</td><td>A56</td><td>IDI_28</td></tr><tr><td>IDI_21</td><td>A23</td><td>A57</td><td>IDI_29</td></tr><tr><td>IDI_22</td><td>A24</td><td>A58</td><td>IDI_30</td></tr><tr><td>IDI_23</td><td>A25</td><td>A59</td><td>IDI_31</td></tr><tr><td>COM3</td><td>A26</td><td>A60</td><td>COM4</td></tr><tr><td>COM3</td><td>A27</td><td>A61</td><td>COM4</td></tr><tr><td>COM3</td><td>A28</td><td>A62</td><td>COM4</td></tr><tr><td>COM3</td><td>A29</td><td>A63</td><td>COM4</td></tr><tr><td>COM3</td><td>A30</td><td>A64</td><td>COM4</td></tr><tr><td>COM3</td><td>A31</td><td>A65</td><td>COM4</td></tr><tr><td>COM3</td><td>A32</td><td>A66</td><td>COM4</td></tr><tr><td>COM3</td><td>A33</td><td>A67</td><td>COM4</td></tr><tr><td>N/C</td><td>A34</td><td>A68</td><td>N/C</td></tr></table>

Figure 1-3: CN1A Connector ID

<table><tr><td>N/C</td><td>B68</td><td>B34</td><td>N/C</td></tr><tr><td>COM8</td><td>B67</td><td>B33</td><td>COM7</td></tr></table>

<table><tr><td>COM8</td><td>B66</td><td>B32</td><td>COM7</td></tr><tr><td>COM8</td><td>B65</td><td>B31</td><td>COM7</td></tr><tr><td>COM8</td><td>B64</td><td>B30</td><td>COM7</td></tr><tr><td>COM8</td><td>B63</td><td>B29</td><td>COM7</td></tr><tr><td>COM8</td><td>B62</td><td>B28</td><td>COM7</td></tr><tr><td>COM8</td><td>B61</td><td>B27</td><td>COM7</td></tr><tr><td>COM8</td><td>B60</td><td>B26</td><td>COM7</td></tr><tr><td>IDI_63</td><td>B59</td><td>B25</td><td>IDI_55</td></tr><tr><td>IDI_62</td><td>B58</td><td>B24</td><td>IDI_54</td></tr><tr><td>IDI_61</td><td>B57</td><td>B23</td><td>IDI_53</td></tr><tr><td>IDI_60</td><td>B56</td><td>B22</td><td>IDI_52</td></tr><tr><td>IDI_59</td><td>B55</td><td>B21</td><td>IDI_51</td></tr><tr><td>IDI_58</td><td>B54</td><td>B20</td><td>IDI_50</td></tr><tr><td>IDI_57</td><td>B53</td><td>B19</td><td>IDI_49</td></tr><tr><td>IDI_56</td><td>B52</td><td>B18</td><td>IDI_48</td></tr><tr><td>N/C</td><td>B51</td><td>B17</td><td>N/C</td></tr><tr><td>COM6</td><td>B50</td><td>B16</td><td>COM5</td></tr><tr><td>COM6</td><td>B49</td><td>B15</td><td>COM5</td></tr><tr><td>COM6</td><td>B48</td><td>B14</td><td>COM5</td></tr><tr><td>COM6</td><td>B47</td><td>B13</td><td>COM5</td></tr><tr><td>COM6</td><td>B46</td><td>B12</td><td>COM5</td></tr><tr><td>COM6</td><td>B45</td><td>B11</td><td>COM5</td></tr><tr><td>COM6</td><td>B44</td><td>B10</td><td>COM5</td></tr><tr><td>COM6</td><td>B43</td><td>B09</td><td>COM5</td></tr><tr><td>IDI_47</td><td>B42</td><td>B08</td><td>IDI_39</td></tr><tr><td>IDI_46</td><td>B41</td><td>B07</td><td>IDI_38</td></tr><tr><td>IDI_45</td><td>B40</td><td>B06</td><td>IDI_37</td></tr><tr><td>IDI_44</td><td>B39</td><td>B05</td><td>IDI_36</td></tr><tr><td>IDI_43</td><td>B38</td><td>B04</td><td>IDI_35</td></tr><tr><td>IDI_42</td><td>B37</td><td>B03</td><td>IDI_34</td></tr><tr><td>IDI_41</td><td>B36</td><td>B02</td><td>IDI_33</td></tr><tr><td>IDI_40</td><td>B35</td><td>B01</td><td>IDI_32</td></tr></table>

Figure 1-4: CN1B Connector ID

<table><tr><td>Pin</td><td>Definition</td></tr><tr><td>IDI_n</td><td>Isolated digital input channel n</td></tr><tr><td>COM1</td><td>Common VDD junction for input channels 0-7</td></tr><tr><td>COM2</td><td>Common VDD junction for input channels 8-15</td></tr><tr><td>COM3</td><td>Common VDD junction for input channels 16-23</td></tr><tr><td>COM4</td><td>Common VDD junction for input channels 24-31</td></tr><tr><td>COM5</td><td>Common VDD junction for input channels 32-39</td></tr><tr><td>COM6</td><td>Common VDD junction for input channels 40-47</td></tr><tr><td>COM7</td><td>Common VDD junction for input channels 48-55</td></tr><tr><td>COM8</td><td>Common VDD junction for input channels 56-63</td></tr><tr><td>N/C</td><td>No connection</td></tr></table>

Table 1-2: CN1 Connector Pin Assignment

<table><tr><td>IDO_0</td><td>A01</td><td>A35</td><td>IDO_8</td></tr><tr><td>IDO_1</td><td>A02</td><td>A36</td><td>IDO_9</td></tr><tr><td>IDO_2</td><td>A03</td><td>A37</td><td>IDO_10</td></tr><tr><td>IDO_3</td><td>A04</td><td>A38</td><td>IDO_11</td></tr><tr><td>IDO_4</td><td>A05</td><td>A39</td><td>IDO_12</td></tr><tr><td>IDO_5</td><td>A06</td><td>A40</td><td>IDO_13</td></tr><tr><td>IDO_6</td><td>A07</td><td>A41</td><td>IDO_14</td></tr><tr><td>IDO_7</td><td>A08</td><td>A42</td><td>IDO_15</td></tr><tr><td>VDD1</td><td>A09</td><td>A43</td><td>VDD2</td></tr><tr><td>IGND</td><td>A10</td><td>A44</td><td>IGND</td></tr><tr><td>IGND</td><td>A11</td><td>A45</td><td>IGND</td></tr><tr><td>IGND</td><td>A12</td><td>A46</td><td>IGND</td></tr><tr><td>IGND</td><td>A13</td><td>A47</td><td>IGND</td></tr><tr><td>IGND</td><td>A14</td><td>A48</td><td>IGND</td></tr><tr><td>IGND</td><td>A15</td><td>A49</td><td>IGND</td></tr><tr><td>IGND</td><td>A16</td><td>A50</td><td>IGND</td></tr><tr><td>N/C</td><td>A17</td><td>A51</td><td>N/C</td></tr><tr><td>IDO_16</td><td>A18</td><td>A52</td><td>IDO_24</td></tr></table>

<table><tr><td>IDO_17</td><td>A19</td><td>A53</td><td>IDO_25</td></tr><tr><td>IDO_18</td><td>A20</td><td>A54</td><td>IDO_26</td></tr><tr><td>IDO_19</td><td>A21</td><td>A55</td><td>IDO_27</td></tr><tr><td>IDO_20</td><td>A22</td><td>A56</td><td>IDO_28</td></tr><tr><td>IDO_21</td><td>A23</td><td>A57</td><td>IDO_29</td></tr><tr><td>IDO_22</td><td>A24</td><td>A58</td><td>IDO_30</td></tr><tr><td>IDO_23</td><td>A25</td><td>A59</td><td>IDO_31</td></tr><tr><td>VDD3</td><td>A26</td><td>A60</td><td>VDD4</td></tr><tr><td>IGND</td><td>A27</td><td>A61</td><td>IGND</td></tr><tr><td>IGND</td><td>A28</td><td>A62</td><td>IGND</td></tr><tr><td>IGND</td><td>A29</td><td>A63</td><td>IGND</td></tr><tr><td>IGND</td><td>A30</td><td>A64</td><td>IGND</td></tr><tr><td>IGND</td><td>A31</td><td>A65</td><td>IGND</td></tr><tr><td>IGND</td><td>A32</td><td>A66</td><td>IGND</td></tr><tr><td>IGND</td><td>A33</td><td>A67</td><td>IGND</td></tr><tr><td>N/C</td><td>A34</td><td>A68</td><td>N/C</td></tr></table>

Figure 1-5: CN2A Connector ID

<table><tr><td>V5V</td><td>B68</td><td>B34</td><td>V5V</td></tr><tr><td>IGND</td><td>B67</td><td>B33</td><td>IGND</td></tr><tr><td>IGND</td><td>B66</td><td>B32</td><td>IGND</td></tr><tr><td>IGND</td><td>B65</td><td>B31</td><td>IGND</td></tr><tr><td>IGND</td><td>B64</td><td>B30</td><td>IGND</td></tr><tr><td>IGND</td><td>B63</td><td>B29</td><td>IGND</td></tr><tr><td>IGND</td><td>B62</td><td>B28</td><td>IGND</td></tr><tr><td>IGND</td><td>B61</td><td>B27</td><td>IGND</td></tr><tr><td>VDD8</td><td>B60</td><td>B26</td><td>VDD7</td></tr><tr><td>IDO_63</td><td>B59</td><td>B25</td><td>IDO_55</td></tr><tr><td>IDO_62</td><td>B58</td><td>B24</td><td>IDO_54</td></tr><tr><td>IDO_61</td><td>B57</td><td>B23</td><td>IDO_53</td></tr><tr><td>IDO_60</td><td>B56</td><td>B22</td><td>IDO_52</td></tr><tr><td>IDO_59</td><td>B55</td><td>B21</td><td>IDO_51</td></tr><tr><td>IDO_58</td><td>B54</td><td>B20</td><td>IDO_50</td></tr></table>

<table><tr><td>IDO_57</td><td>B53</td><td>B19</td><td>IDO_49</td></tr><tr><td>IDO_56</td><td>B52</td><td>B18</td><td>IDO_48</td></tr><tr><td>N/C</td><td>B51</td><td>B17</td><td>N/C</td></tr><tr><td>IGND</td><td>B50</td><td>B16</td><td>IGND</td></tr><tr><td>IGND</td><td>B49</td><td>B15</td><td>IGND</td></tr><tr><td>IGND</td><td>B48</td><td>B14</td><td>IGND</td></tr><tr><td>IGND</td><td>B47</td><td>B13</td><td>IGND</td></tr><tr><td>IGND</td><td>B46</td><td>B12</td><td>IGND</td></tr><tr><td>IGND</td><td>B45</td><td>B11</td><td>IGND</td></tr><tr><td>IGND</td><td>B44</td><td>B10</td><td>IGND</td></tr><tr><td>VDD6</td><td>B43</td><td>B09</td><td>VDD5</td></tr><tr><td>IDO_47</td><td>B42</td><td>B08</td><td>IDO_39</td></tr><tr><td>IDO_46</td><td>B41</td><td>B07</td><td>IDO_38</td></tr><tr><td>IDO_45</td><td>B40</td><td>B06</td><td>IDO_37</td></tr><tr><td>IDO_44</td><td>B39</td><td>B05</td><td>IDO_36</td></tr><tr><td>IDO_43</td><td>B38</td><td>B04</td><td>IDO_35</td></tr><tr><td>IDO_42</td><td>B37</td><td>B03</td><td>IDO_34</td></tr><tr><td>IDO_41</td><td>B36</td><td>B02</td><td>IDO_33</td></tr><tr><td>IDO_40</td><td>B35</td><td>B01</td><td>IDO_32</td></tr></table>

Figure 1-6: CN2B Connector ID

<table><tr><td>Pin</td><td>Definition</td></tr><tr><td>IDO_n</td><td>Isolated digital output channel n</td></tr><tr><td>VDD1</td><td>Common VDD junction for output channels 0-7</td></tr><tr><td>VDD2</td><td>Common VDD junction for output channels 8-15</td></tr><tr><td>VDD3</td><td>Common VDD junction for output channels 16-23</td></tr><tr><td>VDD4</td><td>Common VDD junction for output channels 24-31</td></tr><tr><td>VDD5</td><td>Common VDD junction for output channels 32-39</td></tr><tr><td>VDD6</td><td>Common VDD junction for output channels 40-47</td></tr><tr><td>VDD7</td><td>Common VDD junction for output channels 48-55</td></tr><tr><td>VDD8</td><td>Common VDD junction for output channels 56-63</td></tr><tr><td>IGND</td><td>Ground return path for isolated output channels</td></tr></table>

<table><tr><td>Pin</td><td>Definition</td></tr><tr><td>V5V</td><td>Onboard unregulated 5V power supply output</td></tr><tr><td>N/C</td><td>No connection</td></tr></table>

Table 1-3: CN2 Connector Pin Assignment

# 1.7 DI/O Connections

![1\n2\n19\n20](.pcie-7442-50-11264-1000-200-en/110d90c81f17c5ce6936721f9bc96c5a104bca66dcd24e766873851b8975a105.jpg)

Figure 1-7: I/O Connector

<table><tr><td>TTLIO_n</td><td>TTL I/O channel n</td></tr><tr><td>SGND</td><td>System ground for PCIe-7442 card</td></tr></table>

<table><tr><td>Pin</td><td>Function</td><td>Pin</td><td>Function</td></tr><tr><td>1</td><td>TTLIO_0</td><td>2</td><td>TTLIO_8</td></tr><tr><td>3</td><td>TTLIO_1</td><td>4</td><td>TTLIO_9</td></tr></table>

<table><tr><td>Pin</td><td>Function</td><td>Pin</td><td>Function</td></tr><tr><td>5</td><td>TTLIO_2</td><td>6</td><td>TTLIO_10</td></tr><tr><td>7</td><td>TTLIO_3</td><td>8</td><td>TTLIO_11</td></tr><tr><td>9</td><td>SGND</td><td>10</td><td>SGND</td></tr><tr><td>11</td><td>TTLIO_4</td><td>12</td><td>TTLIO_12</td></tr><tr><td>13</td><td>TTLIO_5</td><td>14</td><td>TTLIO_13</td></tr><tr><td>15</td><td>TTLIO_6</td><td>16</td><td>TTLIO_14</td></tr><tr><td>17</td><td>TTLIO_7</td><td>18</td><td>TTLIO_15</td></tr><tr><td>19</td><td>SGND</td><td>20</td><td>SGND</td></tr></table>

Table 1-4: JP3 I/O Connector Pin Assignment

<table><tr><td>Pin</td><td>Function</td><td>Pin</td><td>Function</td></tr><tr><td>1</td><td>TTLIO_16</td><td>2</td><td>TTLIO_24</td></tr><tr><td>3</td><td>TTLIO_17</td><td>4</td><td>TTLIO_25</td></tr><tr><td>5</td><td>TTLIO_18</td><td>6</td><td>TTLIO_26</td></tr><tr><td>7</td><td>TTLIO_19</td><td>8</td><td>TTLIO_27</td></tr><tr><td>9</td><td>SGND</td><td>10</td><td>SGND</td></tr><tr><td>11</td><td>TTLIO_20</td><td>12</td><td>TTLIO_28</td></tr><tr><td>13</td><td>TTLIO_21</td><td>14</td><td>TTLIO_29</td></tr><tr><td>15</td><td>TTLIO_22</td><td>16</td><td>TTLIO_30</td></tr><tr><td>17</td><td>TTLIO_23</td><td>18</td><td>TTLIO_31</td></tr><tr><td>19</td><td>SGND</td><td>20</td><td>SGND</td></tr></table>

Table 1-5: JP4 I/O Connector Pin Assignment

# 1.8 Digital Channels

# 1.8.1 Isolated Digital Input Channels

The isolated digital input, with open collector transistor structure, supports voltage range of 0 to 28V with input resistance 4.7K. Connection between external signals and the PCIe-7442 is as shown. Since the input common junction can be common ground with the existing environment, digital input can be current source or current sink.

![Isolated Input\nIDI_n (source)\n4.7kΩ\nCurrent Flow\nDICOM\n(GND)](.pcie-7442-50-11264-1000-200-en/2e82d8d38f6ea1a913c872f52d045f5c602201f5a9472bca08a53da4d808947b.jpg)

![Isolated Input\nIDI_n (sink)\n4.7kΩ\nCurrent Flow\nDICOM\n(+VDD)](.pcie-7442-50-11264-1000-200-en/ce77fb7fb3fe4a82b273f6cae2fef3cd6b72afe4d9f1506d66ac0d407124a08e.jpg)

Figure 1-8: Isolated Input Connection

# 1.8.2 Isolated Digital Output Channels

In the common ground connection of isolated digital output, as shown, when isolated digital output goes ON, sink current passes through the transistors until output is OFF. When the load is of an inductance nature, such as a relay, coil, or motor, the VDD pin must be connected to an external power source, allowing the flywheel diode to form a current-release closed loop, whereby transistors are protected from high reverse voltage from inductance loading when the output is switched to OFF.

![DC-DC\nConverter\nV5V\nVDD_n\nLoad\nIDO_x\nIGND\nVm\n5 to 40V\nIGND](.pcie-7442-50-11264-1000-200-en/25f06b9a3dae7f2b586f88710d92cd66df2331ba4b1d19995c35192f0b8a7652.jpg)

Figure 1-9: Common Ground Connection

# 1.9 Change of State (COS) Interrupt

The COS designation refers to either the input state (logic level) changing from low to high, or vice versa, with the COS detection circuit ascertaining the edge of the level change. In the PCIe-7442, COS detection is applied to all input channels, wherein when any channel changes logic level, an interrupt request is issued to the PCI controller.

# 1.9.1 COS Detection

All enabled DI channel signal level changes are detected to generate the interrupt request, during which time corresponding DI data is further latched into the COS latch register. DI data are here sampled by a 33 MHz clock, such that pulse width of the digital input must exceed 31ns, or input data cannot be latched accurately. The COS latch register is erased after the interrupt request is cleared.

# 1.9.2 COS Detection Architecture

The COS interrupt system generates an interrupt request signal which is serviced request with ISR. The PCIe-7442 has bank 0 from DI0 to DI31 and bank 1 from DI32 to 63, cascaded together toward the same IRQ line via CPLD. Notification can be configured to show which bank or DI line carries the COS when it occurs, and to enable/disable the COS function of specific DI lines. COS function for each is disabled as default.

# 1.10 Programmable Power Up DO Status

The PCIe-7442 provides programmable configuration of all 64CH DO initial status when powering up. As well, the system can be configured to hold DO status and avoid power-up initial configuration after a hot system reset.

# 1.11 Watchdog Timer (WDT)

In safety-critical applications, enabling watchdog timer (WDT) function automatically generates an interrupt signal for when the OS or card crashes. To enable, the watchdog timer overflow counter must be configured by Windows API. Generally, trigger source is acquired from the onboard 32-bit watchdog timer.

The WDT overflow interval can be programmed via API, and WDT counter value must be reloaded before enabling the WDT, and periodical reload of the timer value enabled by configuration. If the timer is not reloaded within the specified interval, the WDT module generates an overflow interruption signal. When the SafetyOut\_Enable bit is enabled, 64CH DO safety statuses are automatically configured. This WDT function is disabled by default.

# 1.12 Programmable TTL I/O

32CH programmable TTL input/output is provided, with the channels divided between JP3 and JP4 connectors. The direction of each TTL channel can be reconfigured at any time. I/O voltage level is compatible with 5V TTL level and 3.3V TTL level, with driving strength of each channel 4mA. Current consumption of the TTL channel should be regularly monitored.

This page intentionally left blank.

# 2 Getting Started

# 2.1 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

▶ PCIe-7442 high-speed DI/O card
▶ Quick Start Guide

If any of the items is damaged or missing, contact your dealer immediately.

![The image displays a standard safety warning sign. It features a yellow triangle with a black border containing a large black exclamation point in the center. Below the triangle is a white rectangular strip with the word 'CAUTION:' printed in black capital letters.](.pcie-7442-50-11264-1000-200-en/5d722a03f3256759a2c1db1911c692d1016a5d2b71e6842a427f6ada9cc6ea24.jpg)

The card must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the card. Wear a grounded wrist strap when servicing.

# 2.2 Installing the Card

Install the card driver before you install the card into your computer system. See “Software Support” on page 3. for driver support information.

To install the card:

1. Turn off the system/chassis and disconnect the power plug from the power source.
2. Remove the system/chassis cover.
3. Select the PCIE Express slot that you intend to use, then remove the bracket opposite the slot, if any.
4. Align the card connectors (golden fingers) with the slot, then press the card firmly until the card is completely seated on the slot.
5. Secure the card to the chassis with a screw.

6. Replace the system/chassis cover.
7. Connect the power plug to a power source, then turn on the system.

# Configuration

All PCI/PCIE Express cards on your system are configured individually. Because configuration is controlled by the system and the software, no jumper setting is required for base address, DMA, and interrupt IRQ. Configuration is subject to change with every boot of the system as new PCI/PCIE Express $^{®}$ cards are added or removed.

# Troubleshooting

If your system fails to boot or if you experience erratic operation with your PCI/PCIE Express card in place, an interrupt conflict may have been generated (such as when the BIOS Setup is incorrectly configured). Refer to the system's BIOS documentation for details.

# 2.3 Setting Board ID

When more than one data acquisition card is installed in the system, identification of specific cards can be a problem. The PCIe-7442 provides Board ID function, in which, according to settings of a DIP switch located in S1, ID is directly assigned to specific cards, providing error-free access to the card. Switch setting conditions are as shown, wherein 1= ON and 0 = OFF.

![| Category | Bottom Segment | Top Segment |\n|---|---|---|\n| 1 | 2 | 8 |\n| 2 | 2 | 7 |\n| 3 | 2 | 8 |\n| 4 | 2 | 6 |](.pcie-7442-50-11264-1000-200-en/f8461871d29b71b252819c0dbf5a892778e11cb3fd73389235ab1730b833ab76.jpg)

<table><tr><td rowspan="2">Board ID</td><td colspan="4">Switch</td></tr><tr><td>1</td><td>2</td><td>3</td><td>4</td></tr><tr><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr><tr><td>2</td><td>1</td><td>0</td><td>1</td><td>1</td></tr><tr><td>3</td><td>0</td><td>0</td><td>1</td><td>1</td></tr><tr><td>4</td><td>1</td><td>1</td><td>0</td><td>1</td></tr><tr><td>5</td><td>0</td><td>1</td><td>0</td><td>1</td></tr><tr><td>6</td><td>1</td><td>0</td><td>0</td><td>1</td></tr><tr><td>7</td><td>0</td><td>0</td><td>0</td><td>1</td></tr><tr><td>8</td><td>1</td><td>1</td><td>1</td><td>0</td></tr><tr><td>9</td><td>0</td><td>1</td><td>1</td><td>0</td></tr><tr><td>10</td><td>1</td><td>0</td><td>1</td><td>0</td></tr><tr><td>11</td><td>0</td><td>0</td><td>1</td><td>0</td></tr><tr><td>12</td><td>1</td><td>1</td><td>0</td><td>0</td></tr><tr><td>13</td><td>0</td><td>1</td><td>0</td><td>0</td></tr><tr><td>14</td><td>1</td><td>0</td><td>0</td><td>0</td></tr><tr><td>15</td><td>0</td><td>0</td><td>0</td><td>0</td></tr></table>

Table 2-1: Board ID Setting Conditions

This page intentionally left blank.

# 3 I/O Registers

# 3.1 About PCIe Controller Registers

The PCIe-7442 function library provides simple and easy-to-use functions to mange interrupt procedures. The functions eliminate the need to manipulate the interrupt register in the PCIe controller. It is recommended to use these functions to avoid the effort in developing all-new interrupt functions.

# 3.2 Isolated Digital Input Register

Status of the 64 isolated inputs is supplied by the four isolated input registers, with each bit corresponding to a channel. Bit value 1 indicates the input is ON and 0 OFF.

<table><tr><td>Address/W</td><td>R</td><td>Value Mapping[MSB (bit15)----LSB (bit0)]</td></tr><tr><td>BASE+0x02h</td><td>R</td><td>IDI [15...0]</td></tr><tr><td>BASE+0x04h</td><td>R</td><td>IDI [31...16]</td></tr><tr><td>BASE+0x42h</td><td>R</td><td>IDI [47...32]</td></tr><tr><td>BASE+0x44h</td><td>R</td><td>IDI [63...48]</td></tr></table>

# 3.3 COS Interrupt Control Registers

The two supported interrupt modes, disabled by default, enable interrupt when registers as listed are written. In the first mode, COS (Change of State) interrupt function monitors the status of enabled input channels and status changes from 0 to 1 or 1 to 0. In the second mode, the Watchdog Timer (WDT) counter is enabled. The interrupt asserts when the WDT Counter reaches zero. After processing the interrupt request event, interrupt request must be cleared to handle subsequent requests. Since an interval is required in which to clear the interrupt, COS or WDT interrupts preceding the previous interrupt that have not cleared will be ignored. To clear the interrupt request, write 1 to the corresponding bit (CLRn). The WDT INT control registers are as shown.

The COS interrupt is enabled by two registers. Because the 64 digital inputs are divided into two 32-bit onboard buses, every 32 inputs are connected to a CPLD. When COS interrupt EA0 (BASE+0x06h) is enabled, the first CPLD (CPLD0) generates an interrupt signal when the first 32 inputs IDI [31..0] experience state change. When COS interrupt EA1 (BASE+0x46h) is enabled, the second CPLD (CPLD1) generates an interrupt signal when the second 32 inputs IDI[63..32] experience state change.

For COS interrupt EA1 (BASE+0x46h), Bits 15–9 and Bits 7–1 are unused, Bit0 CLR0: COS 0 interrupt clear is 1: Clear and 0: No effect, and Bit8 EA0: COS 0 interrupt enable/disable is 1: Enabled and 0: Disabled.

<table><tr><td colspan="8">Address: BASE+0x06hReset Value: 0x0000hRead/Write: W</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>CLR0</td></tr><tr><td>Bit7</td><td>Bit6</td><td>Bit5</td><td>Bit4</td><td>Bit3</td><td>Bit2</td><td>Bit1</td><td>Bit0</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>EA0</td></tr><tr><td>Bit15</td><td>Bit14</td><td>Bit13</td><td>Bit12</td><td>Bit11</td><td>Bit10</td><td>Bit9</td><td>Bit8</td></tr></table>

For COS interrupt EA1 (BASE+0x46h), Bits 15–9 and Bits 7–1 are unused, Bit0 CLR0: COS 0 interrupt clear is 1: Clear; 0: No effect, and Bit8 EA0: COS 0 interrupt enable/disable is 1: Enabled; 0: Disabled.

<table><tr><td colspan="8">Address: BASE+0x46hReset Value: 0x0000hRead/Write: W</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>CLR1</td></tr><tr><td>Bit7</td><td>Bit6</td><td>Bit5</td><td>Bit4</td><td>Bit3</td><td>Bit2</td><td>Bit1</td><td>Bit0</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>EA1</td></tr><tr><td>Bit15</td><td>Bit14</td><td>Bit13</td><td>Bit12</td><td>Bit11</td><td>Bit10</td><td>Bit9</td><td>Bit8</td></tr></table>

# 3.4 COS Setup/Latch Registers

Change of State (COS) interrupt is provided on any digital input channel, allowing status of digital input channels to be monitored by setting registers as follows.

Enabling COS Setup registers generates an interrupt when the corresponding channel changes its state.

For IDI\_COS\_EN [n]: Change-of-State function enable of IDI on channel n, n = 0 - 63, bit value 0 disables COS function and 1 enables.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x08h</td><td>W</td><td>IDI_COS_EN[15...0]</td></tr><tr><td>BASE+0x0Ah</td><td>W</td><td>IDI_COS_EN[31...16]</td></tr><tr><td>BASE+0x48h</td><td>W</td><td>IDI_COS_EN[47...32]</td></tr><tr><td>BASE+0x4Ah</td><td>W</td><td>IDI_COS_EN[63...48]</td></tr></table>

When COS occurs, the COS latch registers also latch the IDI[31..0], IDI[63..32] data, respectively. Once the interrupt request is cleared, the COS latch register automatically clears. Since these registers can be checked for post=interrupt status, the CPU is freed from the workload presented by constant polling of all inputs, enabling it to handle other tasks. With bit value 1, input is ON, and with 0, OFF (initial value).

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x08h</td><td>R</td><td>IDI_COS_LATCH_DATA[15...0]</td></tr><tr><td>BASE+0x0Ah</td><td>R</td><td>IDI_COS_LATCH_DATA[31...16]</td></tr><tr><td>BASE+0x48h</td><td>R</td><td>IDI_COS_LATCH_DATA[47...32]</td></tr><tr><td>BASE+0x4Ah</td><td>R</td><td>IDI_COS_LATCH_DATA[63...48]</td></tr></table>

<table><tr><td colspan="8">Address: BASE+0x06hReset Value: 0x0000hRead/Write: W</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>CLR0</td></tr><tr><td>Bit7</td><td>Bit6</td><td>Bit5</td><td>Bit4</td><td>Bit3</td><td>Bit2</td><td>Bit1</td><td>Bit0</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>EA0</td></tr><tr><td>Bit15</td><td>Bit14</td><td>Bit13</td><td>Bit12</td><td>Bit11</td><td>Bit10</td><td>Bit9</td><td>Bit8</td></tr></table>

# 3.5 TTL I/O Setup, Status, DO, and DI Registers

An extra 32CH TTL I/O function is provided for optional applications. Divided between two 16-bit banks and between JP3 and JP4 connectors, they accommodate selection of direction for each TTL channel at any time via the two-bank TTL I/O setup register.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x0Ch</td><td>W</td><td>TTL_IO_SETUP[15...0]</td></tr><tr><td>BASE+0x4Ch</td><td>W</td><td>TTL_IO_SETUP[31..16]</td></tr></table>

When TTL I/O channel direction is set, status can be read back through TTL I/O Status Read Back Register to determine whether correct.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x0Ch</td><td>R</td><td>TTL_IO_STATUS[15...0]</td></tr><tr><td>BASE+0x4Ch</td><td>R</td><td>TTL_IO_STATUS[31...16]</td></tr></table>

When the I/O direction setting is output, data can be transmitted via TTL I/O output channel, with bit value 0 setting output low (default), and 1 high.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x0Eh</td><td>W</td><td>TTL_IO_DO[15...0]</td></tr><tr><td>BASE+0x4Eh</td><td>W</td><td>TTL_IO_DO[31...16]</td></tr></table>

When the I/O direction setting is input, data can be read through the TTL I/O input channel, with bit value 0 setting input low and 1 high (initial value).

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x0Eh</td><td>R</td><td>TTL_IO_DI[15...0]</td></tr><tr><td>BASE+0x4Eh</td><td>R</td><td>TTL_IO_DI[31...16]</td></tr></table>

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x08h</td><td>W</td><td>IDI_COS_EN[15...0]</td></tr><tr><td>BASE+0x0Ah</td><td>W</td><td>IDI_COS_EN[31...16]</td></tr><tr><td>BASE+0x48h</td><td>W</td><td>IDI_COS_EN[47...32]</td></tr><tr><td>BASE+0x4Ah</td><td>W</td><td>IDI_COS_EN[63...48]</td></tr></table>

# 3.6 Isolated Digital Output and Read Back Registers

The 64 isolated digital outputs are divided between output connectors CN2A and CN2B, controlled by four 16-bit registers in bank2. Each digital output line is controlled by each bit of the four control registers. To complete the process, corresponding DO output data must be issued, followed by the start command to bank2. 64-bit DO data is transmitted at the same time. Output device type is Open Drain Power MOSFET driver. DO Send Out Start requires no register value, ony the transmission of the address (BASE + 0x88h) in Write mode after setup of all 64-bit channel output data. When back2 receives the Start command, 64-bit DO data is sent at the same time, and progress can be checked via nDO\_SendReady flag status. Bit value 0 sets output Power MOSFET OFF (Initial value), and 1 ON.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x80h</td><td>R</td><td>DO Read Back Start</td></tr><tr><td>BASE+0x82h</td><td>R</td><td>IDO[15...0]</td></tr><tr><td>BASE+0x84h</td><td>R</td><td>IDO[31...16]</td></tr><tr><td>BASE+0x86h</td><td>R</td><td>IDO[47...32]</td></tr><tr><td>BASE+0x88h</td><td>R</td><td>IDO[63...48]</td></tr></table>

# 3.7 Power-up DO Setup/Read Register

When the system powers up, the PCIe-7442 can initiate transmission of default initial value to 64CH digital outputs. The power-up default DO values can be configured and stored in flash memory, such that DO assumes a specified status at power up. Default 64CH power-up default DO values can be programmed via the Power-up DO Setup Register in turn. After access to the previous Power-up DO Setup Register (BASE+0x92h), it can take up to 0.5s to finish writing the procedure to the flash memory. It can be determined whether the procedure is complete via the nAction\_Ready flag. Bit value: 0 sets Output Power MOSFET to OFF (Initial value), and 1 to ON.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x8Ch</td><td>W</td><td>IDO[15...0]</td></tr><tr><td>BASE+0x8Eh</td><td>W</td><td>IDO[31...16]</td></tr><tr><td>BASE+0x90h</td><td>W</td><td>IDO[47...32]</td></tr><tr><td>BASE+0x92h</td><td>W</td><td>IDO[63...48]</td></tr></table>

Configured initial power-up DO values stored in the flash memory can be reviewed by sending out the Read Start command (BASE+0x8Ch), after which read procedure starts in 50 ms. When the Read Back procedure is ready (nAction\_Ready flag), the 64-bit Power-up DO Read Back Register can be read back in turn. Bit value: 0 sets Output Power MOSFET to OFF (Initial value), and 1 to ON.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x8Ch</td><td>R</td><td>Read Back Start</td></tr><tr><td>BASE+0x8Eh</td><td>R</td><td>IDO[15...0]</td></tr><tr><td>BASE+0x90h</td><td>R</td><td>IDO[31...16]</td></tr><tr><td>BASE+0x92h</td><td>R</td><td>IDO[47...32]</td></tr><tr><td>BASE+0x94h</td><td>R</td><td>IDO[63...48]</td></tr></table>

# 3.8 Watchdog Timer Load, Safety DO Setup/Read Back Registers

In the 32-bit watch dog timer (WDT) with 10 MHz clock, the WDT counter loads the 32-bit value of two 16-bit WDT\_LOAD\_CONFIG registers in turn, where the corresponding user-defined hexadecimal value determines the overflow time of the WDT counter. Overflow time is calculated by the set value multiplied by 100 ns. Timer interval is from 0 to 429.496 seconds.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x94h</td><td>W</td><td>WDT_LOAD_CONFIG[15...0]</td></tr><tr><td>BASE+0x96h</td><td>W</td><td>WDT_LOAD_CONFIG[31...16]</td></tr></table>

When the WDT interrupt asserts, the system can be set to send out the Safety DO value via the SafetyOut\_Enable bit. When WDT INT asserts, the system process may halt or be offline, in the event of which this function prevents untoward damage. Default 64CH safety DO values are stored in the flash memory. When WDT interrupt asserts and the SafetyOut\_Enable bit is enabled, the PCIe-7442 enters the safety DO procedure which sends out the default safety value to 64CH digital outputs.

64CH safety default DO values can be programmed by accessing the previous WDTSafety DO Setup register in turn. After accessing the previous WDTSafety DO Setup register (BASE+0x9Eh), it takes 500 ms to finish writing the procedure to the flash memory. It can be determined whether the procedure is complete via nAction\_Ready flag. Bit value: 0 sets Output Power MOSFET to OFF(Initial value), and 1 to ON.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x98h</td><td>W</td><td>IDO[15...0]</td></tr><tr><td>BASE+0x9Ah</td><td>W</td><td>IDO[31...16]</td></tr><tr><td>BASE+0x9Ch</td><td>W</td><td>IDO[47...32]</td></tr><tr><td>BASE+0x9Eh</td><td>W</td><td>IDO[63...56]</td></tr></table>

Configured Safety DO values stored in flash memory can be reviewed by sending out the WDTSafety DO ReadBack command (BASE+0x96h). The flash memory read procedure starts in 50 ms. The finished flag can be checked by nAction\_Ready flag. After Read Back, the 64-bit WDTSafety DO Read Back registers can be reviewed in turn. Bit value: 0 sets Output Power MOSFET to OFF(Initial value) and 1 to ON.

<table><tr><td>Address</td><td>R/W</td><td>Value Mapping (MSB----LSB)</td></tr><tr><td>BASE+0x96h</td><td>R</td><td>Read Back Start</td></tr><tr><td>BASE+0x98h</td><td>R</td><td>IDO[15...0]</td></tr><tr><td>BASE+0x9Ah</td><td>R</td><td>IDO[31...16]</td></tr><tr><td>BASE+0x9Ch</td><td>R</td><td>IDO[47...32]</td></tr><tr><td>BASE+0x9Ch</td><td>R</td><td>IDO[63...56]</td></tr></table>

# 3.9 WDT INT Control, Hot-Reset, and Hold Control Register

The PCIe-7442 supports COS INT and watch dog timer (WDT) interrupt modes. When enabled, the WDT counts down as a mode of interrupt, and is asserted when the counter reaches zero. WDT enable and clear WDT INT can be operated by setting two bits (WDTE and WIC) in Bank2 WDT INT Control/Hot-Reset Hold Control Register.

The PCIe-7442 also enhances industrial safety by, when the WDT interrupt asserts, issuing the Safety DO value to set the SOE bit and prevent possible system damage. According to user settings, when the system experiences unexpected or normal hot system reset without proper power down, the board can retain the original pre-rest DO values, or enter the power-up initial procedure to issue the previously configured default initial DO values. Setting the HRHE bit enables Hot\_Reset\_Hold function anytime, especially useful in unstable environments.

Bit functionality is as shown.

<table><tr><td colspan="8">Address: BASE+0x8AhReset Value: 0x0000hRead/Write: W</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>WSOE</td><td>WIC</td><td>WDTE</td><td>HRHE</td></tr><tr><td>Bit7</td><td>Bit6</td><td>Bit5</td><td>Bit4</td><td>Bit3</td><td>Bit2</td><td>Bit1</td><td>Bit0</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td></tr><tr><td>Bit15</td><td>Bit14</td><td>Bit13</td><td>Bit12</td><td>Bit11</td><td>Bit10</td><td>Bit9</td><td>Bit8</td></tr></table>

<table><tr><td>Bit</td><td>Function</td><td>1</td><td>0</td></tr><tr><td>0</td><td>HRHE: Hot Reset Hold Enable, enables hot-system-reset DO hold</td><td>Enabled</td><td>Disabled</td></tr><tr><td>1</td><td>WDTE: WDT interrupt enable/disable</td><td>Enabled</td><td>Disabled</td></tr><tr><td>2</td><td>WIC: WDT interrupt clear</td><td>Clear WDT interrupt</td><td>No effect</td></tr><tr><td>3</td><td>WSOE: WDT Safety DO Send Out enable</td><td>Enabled</td><td>Disabled</td></tr><tr><td>4 to 15</td><td>Not Used</td><td>N/A</td><td>N/A</td></tr></table>

<table><tr><td colspan="8">Address: BASE+0x8AhReset Value: 0x0000hRead/Write: R</td></tr><tr><td>--</td><td>ARDYS</td><td>SRDYS</td><td>RBRDYS</td><td>SOES</td><td>WIS</td><td>WDTES</td><td>HRHES</td></tr><tr><td>Bit7</td><td>Bit6</td><td>Bit5</td><td>Bit4</td><td>Bit3</td><td>Bit2</td><td>Bit1</td><td>Bit0</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td><td>--</td></tr><tr><td>Bit15</td><td>Bit14</td><td>Bit13</td><td>Bit12</td><td>Bit11</td><td>Bit10</td><td>Bit9</td><td>Bit8</td></tr></table>

<table><tr><td>Bit</td><td>Function</td><td>1</td><td>0</td></tr><tr><td>0</td><td>HRHES: Hot Reset Hold Enable Status</td><td>Enabled</td><td>Disabled</td></tr><tr><td>1</td><td>WDTES: WDT Interrupt Enable Status</td><td>Enabled</td><td>Disabled</td></tr><tr><td>2</td><td>WIS: WDT Interrupt Status</td><td>WDT interrupt does not assert</td><td>WDT interrupt asserts</td></tr><tr><td>3</td><td>SOES: Safety Out Enable Status</td><td>Enabled</td><td>Disabled</td></tr><tr><td>4</td><td>RBRDYS: DO Read Back Data Ready Status</td><td>Not ready</td><td>Ready</td></tr><tr><td>5</td><td>SRDYS: DO Data Sending Finished Status</td><td>Not finished</td><td>Finished</td></tr><tr><td>6</td><td>ARDYS: Flash Data Read/Write Finished Status</td><td>Not finished</td><td>Finished</td></tr><tr><td>7 to 15</td><td>Not Used</td><td>N/A</td><td>N/A</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing (See “Getting Started” on page 17.):

▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power

▶ To avoid electrical shock and/or damage to device:

▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▷ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
▶ A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![A vertical yellow triangle with a black border containing a black exclamation point in the center.](.pcie-7442-50-11264-1000-200-en/3372d588387bc7b46e7f7354f564ec1d81487d1b4faa79d8c121dded1463001e.jpg)
CAUTION:

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d'explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up

It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required

▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

![Yellow triangular warning sign with black smoke symbol indicating heat or hazard](.pcie-7442-50-11264-1000-200-en/b49939964f6e65d97626470e2b312171284b02e86cd2cd0ebdfb4ace35d1a2ca.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

This page intentionally left blank.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110
San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park
Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
Rm. 801, Power Creative E, No. 1 Shang Di East Rd.
Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8626

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园
A1 栋 2 楼 C 区 (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7
High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11
D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

# PENTA ADLINK Technology GmbH

Ulrichsbergerstrasse 17
94469 Deggendorf, Germany

Tel: +49 (0) 991 290 94 - 10

Fax: +49 (0) 991 290 94 - 29

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 6 allée de Londres, Immeuble Ceylan

91940 Les Ulis, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

神田 374 ビル 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 경기도 성남시 분당구 수내로 46 번길 4 경동빌딩 2 층

(수내동 4-4 번지)(우)463-825

2F, Kyungdong B/D, 4 Sunae-ro 46 beon-gil

Bundang-gu, Seongnam-si, Gyeonggi-do, Korea, 463-825

Toll Free +82-80-800-0585

Tel +82-31-786-0585

Fax +82-31-786-0583

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre

Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: #50-56, First Floor, Spearhead Towers

Margosa Main Road (between 16th/17th Cross)

Malleswaram, Bangalore - 560 055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 27 Maskit St., Corex Building

PO Box 12777

Herzliya 4673300, Israel

Tel: +972-54-632-5251

Fax: +972-77-208-0230

Email: israel@adlinktech.com

# ADLINK Technology, Inc. (UK Liaison Office)

Tel: +44 774 010 59 65

Email: UK@adlinktech.com
[🔗 Link to the original document](.pcie-7442-50-11264-1000-200-en/pcie-7442-50-11264-1000-200-en.pdf)