# NuDAQ® PCIe-9100 Series

# Multiplexer/Simultaneous Multifunction Data Acquisition Card

User’s Manual
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Manual Revision: 1.3

Revision Date: December 24, 2024

Part No: 50M-18094-1030

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2023-02-21</td><td>Initial release</td></tr><tr><td>1.1</td><td>2023-06-01</td><td>Update product name to PCIe-9100 Series.Add PCIe-9103.</td></tr><tr><td>1.2</td><td>2024-05-05</td><td>Add PCIe-9146 and PCIe-9147.</td></tr><tr><td>1.3</td><td>2024-12-24</td><td>Add PCIe-9161, PCIe-9163, and PCIe-9164</td></tr></table>

# Preface

Copyright © 2024 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental Protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

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NOTE:

Additional information, aids, and tips that help users perform tasks.

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CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image shows a red equilateral triangle pointing upwards containing a white exclamation mark in its center. Thin black horizontal lines run across the top and bottom edges of the image, framing the triangle against a white background.](.pcie-9100-50m-18094-1030-17/4f4027e6c7ece628a115fe9f6b489f71d907db270146cd0aaed83cdbfebdcd5e.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History.......... ii

# Preface ............ iii

# 1 Introduction ........

1.1 Functions ..... 1
1.2 Features... 1
1.3 Applications ...... 3
1.4 Specifications..... 4
1.5 Software Support .. 13

# 2 Getting Started ........ 1 7

2.1 Package Contents .... . 18
2.2 Device Layout and I/O Connectors... 1 9
2.3 Switch and Jumper Settings ...... 26
2.4 Connector Pin Assignments ..... 3 1
2.5 Hardware Installation Outline.... 47
2.6 Device Installation for Windows Systems ..... 48

# 3 Operation Theory .......... 4 9

3.1 A/D Conversion.. 49
3.2 Analog Input Signal Connection .. 5 0
3.3 D/A Conversion.. 68
3.4 Digital Input and Output .. 79
3.5 General Purpose Timer/Counter.. 8 8
3.6 Encoder ... 99
3.7 Pattern Match .. . 106
3.8 Programmable Function I/O.... . 108

# Important Safety Instructions ........ 109

# Getting Service......... . 113

This page intentionally left blank.

# 1 Introduction

The PCIe-9100 Series of products are PCI Express multifunction data acquisition cards for industrial applications. The plug and play feature of the PCI Express bus architecture makes it easy for users to quickly install PCIe-9100 Series products on their systems.

# 1.1 Functions

The PCIe-9100 Series provides the following functions for most measurement and control uses:

 14/16-bit A/D conversion
 16-bit D/A conversion
 Digital Input/Output lines
 Timer Counter with PWM function
 Encoder

# 1.2 Features

The PCIe-9100 Series provides the following advanced features:

 A/D conversion

 Differential (SE) or Differential (SE) input channels

 14/16-bit analog input resolution

 Up to 4M sampling rate

 Up to onboard 8K samples A/D FIFO memory

 Programmable Gain Control (x1, x2, x4, x8, x16, x32)

 Auto-scanning channel selection

 A/D Data transfer: software polling & bus-mastering DMA with Scatter/Gather functionality

 6 trigger mode support, Post trigger, Pre-trigger, Delay trigger, Middle trigger, Post trigger with re-trigger, delay trigger with re-trigger

#  D/A conversion

 Up to 4 channels D/A output with waveform generation capability
 Up to 2MHz D/A sampling rates
 1K samples output data FIFO for DA channels
 D/A Data transfer: software update and bus-mastering DMA with Scatter/Gather functionality
 2 trigger modes: Post trigger, Post trigger with re-trigger

#  Digital I/O Lines

 16 TTL compatible digital output channels
 16 TTL compatible digital input channels
 8mA high current driving capability per channel
 16 isolated digital output channels (PCIe-9103 only)
 16 isolated digital input channels (PCIe-9103 only)

#  Timer counter

 Up to 4 independent programmable 32-bit timer counters
 Provides one pulse output, PWM output, event counting, and the measurement of frequency and pulse width

#  Board ID switch

 Built-in DIP switch that helps define each card’s ID when multiple PCIe-9100 Series cards have been installed on the same PC

#  Encoder

 2-ch 4 MHz dedicated encoder inputs
 Supports AB phase and CW/CCW

#  PM (Pattern Match) function

 Reflective actions by comparing patterns of digital input or encoder without involving software

# 1.3 Applications

 ATE
 Cable Testing
 Laboratory Automation
 Industrial process control and monitoring
 Vibration and transient analysis
 Power monitoring
 Biotech measurement
 Medical instrumentation
 Energy

# 1.4 Specifications

# 1.4.1 General Specifications

<table><tr><td colspan="2">Model</td><td>PCIe-9101/9121/9141</td><td>PCIe-9103</td><td>PCIe-9161/9163/9164</td><td>PCIe-9146/9147</td></tr><tr><td colspan="6">Analog Input</td></tr><tr><td colspan="2">Simultaneous/Scanning</td><td colspan="3">Scanning</td><td>Simultaneous</td></tr><tr><td colspan="2">Number of Channels</td><td>16 single-ended (SE) or 8 differential input (DI)</td><td>32 single-ended (SE) or 16 differential input (DI)</td><td>PCIe-9161: 16-chPCIe-9163: 32-chPCIe-9164: 64-chsingle-ended (SE) orPCIe-9161: 8-chPCIe-9163: 16-chPCIe-9164: 32-chdifferential input (DI)</td><td>PCIe-9146: 4-chPCIe-9147: 8-chdifferential input (DI)</td></tr><tr><td rowspan="2">Max. Sampling Rate</td><td>Single-channel</td><td>PCIe-9101: 250 kS/sPCIe-9121: 800 kS/sPCIe-9141: 1 MS/s</td><td rowspan="2">500 kS/s</td><td>4 MS/s</td><td rowspan="2">1 MS/s</td></tr><tr><td>Scanning</td><td>PCIe-9101: 100 kS/sPCIe-9121: 400 kS/sPCIe-9141: 500 kS/s</td><td>1 MS/s*1</td></tr><tr><td colspan="6">*1: The PCIe-9161/9163 is a 16/32-ch multiplexer DAQ with a 1MSps sampling rate. It can also function as a 2-ch simultaneous DAQ with a 4MSps sampling rate.The PCIe-9164 is a 64-ch multiplexer DAQ with a 1MSps sampling rate. It can also function as a 4-ch simultaneous DAQ with a 4MSps sampling rate.</td></tr><tr><td colspan="2">Resolution</td><td>PCIe-9101/9141: 16-bitPCIe-9121: 14-bit</td><td colspan="3">16-bit</td></tr><tr><td colspan="2">Input Range</td><td colspan="4">±10V, ±5V, ±2.5V, ±1.25V, ±0.625V, ±0.3125V</td></tr><tr><td colspan="2">FIFO Buffer Size</td><td colspan="2">Onboard 4K samples</td><td>Onboard 8K samples</td><td>Onboard 4K samples</td></tr><tr><td colspan="2">Input Coupling</td><td colspan="4">DC</td></tr><tr><td colspan="2">Input Impedance</td><td colspan="3">10MΩ</td><td>1GΩ</td></tr><tr><td colspan="2">Overvoltage Protection</td><td>Continuous ±20V</td><td colspan="2">Continuous ±15V</td><td>Continuous ±30V</td></tr><tr><td colspan="2">Channel Gain Queue Configuration Size</td><td>PCIe-9101/9121: 512 samplesPCIe-9141: 1024 samples</td><td>512 samples</td><td>1024 samples</td><td>N/A</td></tr><tr><td colspan="2">Time Base</td><td>Internal: 64 MHzExternal: 8 MHz (CN3 Pin 37)</td><td>Internal: 64 MHzExternal: N/A</td><td>Internal: 80 MHzExternal: 8 MHz (CN1 Pin 32)</td><td>Internal: 64 MHzExternal: 8 MHz (CN1 Pin 16)</td></tr><tr><td colspan="2">Trigger Source</td><td>Software Trigger, Analog Trigger, External Digital Trigger (CN3 Pin 17)</td><td>Software Trigger, External Trigger (CN4 pin 8)</td><td>Software Trigger, Analog Trigger, External Digital Trigger (CN1 Pin 67)</td><td>Software Trigger, Analog Trigger, External Digital Trigger (CN1 Pin 53)</td></tr><tr><td colspan="2">Trigger Modes</td><td colspan="4">Pre-trigger, Post trigger, Delay trigger, Middle trigger, Post trigger with re-trigger, Delay trigger with re-trigger</td></tr><tr><td colspan="2">Data Transfers</td><td colspan="4">Programmed I/O, bus-mastering DMA with scatter/ gather</td></tr><tr><td colspan="2">Signal-to-Noise Ratio (SNR)</td><td>PCIe-9101/9141: 90 dBPCIe-9121: 84 dB</td><td>90 dB</td><td>84 dB</td><td>80 dB</td></tr><tr><td colspan="2">ENOB</td><td>PCIe-9101/9141: 14.5 bitPCIe-9121: 13.5 bit</td><td>14.5 bits</td><td>14 bits</td><td>13.5 bits</td></tr><tr><td colspan="2">Offset Error (mV)</td><td>PCIe-9101/9141: 0.1PCIe-9121: 0.3</td><td>0.1</td><td>0.3</td><td>0.1</td></tr></table>

Table 1-1: General Specifications

<table><tr><td>Model</td><td>PCIe-9101/9121/9141</td><td>PCIe-9103</td><td>PCIe-9161-9163-9164</td><td>PCIe-9146/9147</td></tr><tr><td>Gain Error (% of FSR)</td><td colspan="4">0.1</td></tr><tr><td>Integral Nonlinearity (INL)</td><td colspan="4">&lt;1 LSB</td></tr><tr><td>Differential Nonlinearity (DNL)</td><td colspan="4">&lt;1 LSB</td></tr><tr><td>CMRR @ 60 Hz</td><td colspan="4">85 dB</td></tr><tr><td colspan="5">Analog Output (AO)</td></tr><tr><td>Number of Channels</td><td>2</td><td>N/A</td><td>PCIe-9161: 2PCIe-9163: 4PCIe-9164: 4</td><td>2</td></tr><tr><td>Max. Updating Rate</td><td>1MS/s</td><td>N/A</td><td>2MS/s</td><td>1MS/s</td></tr><tr><td>Resolution</td><td>16-bit</td><td>N/A</td><td colspan="2">16-bit</td></tr><tr><td>Output Range</td><td>±10 V</td><td>N/A</td><td colspan="2">±10 V</td></tr><tr><td>FIFO Size</td><td>1K samples(2-ch sharing)</td><td>N/A</td><td>2K samples (2/4-CH sharing)</td><td>1K samples(2-ch sharing)</td></tr><tr><td>Output Driving Capacity</td><td>±20 mA max</td><td>N/A</td><td colspan="2">±20 mA max</td></tr><tr><td>Slew Rate</td><td>10 V/μs</td><td>N/A</td><td colspan="2">10 V/μs</td></tr><tr><td>Output Coupling</td><td>DC</td><td>N/A</td><td colspan="2">DC</td></tr><tr><td>Settling Time (0.1% of full scale)</td><td>2 μs</td><td>N/A</td><td colspan="2">2 μs</td></tr><tr><td>Output Impedance</td><td>&lt;0.1 ohms</td><td>N/A</td><td colspan="2">&lt;0.1 ohms</td></tr><tr><td>SNR</td><td>&gt;100 dB</td><td>N/A</td><td colspan="2">&gt;100 dB</td></tr><tr><td>THD</td><td>&gt;75 dB</td><td>N/A</td><td colspan="2">&gt;75 dB</td></tr><tr><td>Offset Error</td><td>±0.1 mV</td><td>N/A</td><td colspan="2">±0.1 mV</td></tr><tr><td>Gain Error</td><td>±0.05% of FSR</td><td>N/A</td><td colspan="2">±0.05% of FSR</td></tr><tr><td>INL (Relative Accuracy)</td><td>±2 LSB max</td><td>N/A</td><td colspan="2">±2 LSB max</td></tr><tr><td>DNL</td><td>±1 LSB</td><td>N/A</td><td colspan="2">±1 LSB</td></tr><tr><td>Default On/Off</td><td>AO Off (relay)if AO relay turned on, default AO is 0V (+0.1V to -0.1V)</td><td>N/A</td><td colspan="2">AO Off (relay)if AO relay turned on, default AO is 0V (+0.1V to -0.1V)</td></tr><tr><td>Power On/Off Glitch</td><td>&lt;1mV/μs</td><td>N/A</td><td colspan="2">&lt;1mV/μs</td></tr><tr><td>Timebase Source</td><td>Internal Timebase fixed64MHzExternal Timebase fixed8MHz (CN3.37)</td><td>N/A</td><td>Internal Timebase fixed80MHzExternal Timebase fixed8MHz (CN1.32)</td><td>Internal Timebase fixed64MHzExternal Timebasefixed 8MHz (CN1.16)</td></tr><tr><td>Trigger Source</td><td>Software triggerExternal digital trigger(CN3.17)</td><td>N/A</td><td>Software triggerExternal digital trigger (CN1Pin 33)</td><td>Software triggerExternal digital trigger(CN1 Pin 54)</td></tr><tr><td>Trigger Modes</td><td>Post triggerPost trigger with re-trigger</td><td>N/A</td><td colspan="2">Post triggerPost trigger with re-trigger</td></tr><tr><td>Data Transfers</td><td>Programmed I/Obus-mastering DMA with scatter/ gather</td><td>N/A</td><td colspan="2">Programmed I/Obus-mastering DMA with scatter/ gather</td></tr><tr><td colspan="5">General Purpose Digital IO (DIO)</td></tr><tr><td>Number of Channels</td><td colspan="4">Digital Input: 16 channelsDigital Output: 16 channels</td></tr></table>

Table 1-1: General Specifications

<table><tr><td>Model</td><td>PCIe-9101/9121/9141</td><td>PCIe-9103</td><td>PCIe-9161-9163-9164</td><td>PCIe-9146/9147</td></tr><tr><td>Digital Type</td><td>TTL</td><td>Isolation 2500Vrms</td><td colspan="2">TTL</td></tr><tr><td>Power-on Status</td><td>Digital Input: Low Digital Output: Low</td><td>Digital Input: Low Digital Output: Open</td><td colspan="2">Digital Input: Low Digital Output: Low</td></tr><tr><td>FIFO Buffer Size</td><td>512 samples for all DI channels 512 samples for all DO channels</td><td>N/A</td><td>1024 samples for all DI channels 1024 samples for all DO channels</td><td>512 samples for all DI channels 512 samples for all DO channels</td></tr><tr><td>DI Input Logic Level</td><td>Logic Low: VIL =0V - 0.8V (max.); IIL = -0.2 mA max. Logic High: VIH = 2.0V (min.) - 5V; IIH = 20 uA max.</td><td>Logic low: VIL =0V - 1.5V(max); IIL = -0.2 mA max. Logic high: VIH = 5V(min) - 24V; IIH = 10 mA max.</td><td colspan="2">Logic Low: VIL =0V - 0.8V (max.); IIL = -0.2 mA max. Logic High: VIH = 2.0V (min.) - 5V; IIH = 20 uA max.</td></tr><tr><td>DI Input Frequency Range</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DI_SYNC_IN (CN1 Pin 20) up to 1MHz Down to 0.01Hz</td><td>N/A</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DI_SYNC_IN (CN8 Pin 20) up to 1MHz Down to 0.01Hz</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DI_SYNC_IN (CN1 Pin 59) up to 1MHz Down to 0.01Hz</td></tr><tr><td>DI Input Impedance</td><td>pull-low 100kohm</td><td>2.4kohm/0.5W</td><td colspan="2">pull-low 100kohm</td></tr><tr><td>DI DMA Sync IN source</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN3.37) 3. Up to 1MHz from DI SYNC IN (CN1 Pin 20)</td><td>N/A</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN1 Pin 32) 3. Up to 1MHz from DI (CN8 Pin 20)</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN1 Pin 16) 3. Up to 1MHz from DI SYNC IN (CN1 Pin 59)</td></tr><tr><td>DO Output Logic Level</td><td>Logic low: VIL = 0V - 0.5V (max.); OIL = 8mA max. Logic high: VIH = 2.4V (min.); OIH = 0.4mA max.</td><td>Logic low: VIL = Open; Sink current = 800mA max per CH &amp; total = 1.6A max for 16-ch Logic high: VIH = 5V (min) - 35V from Iso VDD</td><td colspan="2">Logic low: VIL = 0V - 0.5V (max.); OIL = 8mA max. Logic high: VIH = 2.4V (min.); OIH = 0.4mA max.</td></tr><tr><td>DO Output Speed</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DO_SYNC_OUT (CN2 Pin 20) up to 1MHz Down to 0.01Hz</td><td>N/A</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DO_SYNC_OUT (CN7 Pin 20) up to 1MHz Down to 0.01Hz</td><td>Up to 500ns pulse for 1MHz Duty 50% sync by DO_SYNC_OUT (CN1 Pin 68) up to 1MHz Down to 0.01Hz</td></tr><tr><td>DO Pull-low</td><td>Pull-low 100kohm</td><td>No, default Open</td><td colspan="2">Pull-low 100kohm</td></tr><tr><td>DO Default Level</td><td colspan="4">Low</td></tr><tr><td>DO DMA Sync OUT source</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN3.37)</td><td>N/A</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN1 Pin 32)</td><td>1. Up to 1MHz from Internal Timebase 2. Up to 1MHz from External Timebase fixed 8MHz (CN1 Pin 16)</td></tr><tr><td>DIO Setup Time</td><td>250 ns</td><td>N/A</td><td colspan="2">250 ns</td></tr><tr><td>DIO Hold Time</td><td>250 ns</td><td>N/A</td><td colspan="2">250 ns</td></tr></table>

Table 1-1: General Specifications

<table><tr><td>Model</td><td>PCIe-9101/9121/9141</td><td>PCIe-9103</td><td>PCIe-9161-9163-9164</td><td>PCIe-9146/9147</td></tr><tr><td>Trigger Source</td><td>Software trigger, External digital trigger (CN3.17)</td><td>Software trigger, External digital trigger (CN4.8)</td><td>Software trigger, External digital trigger (CN7 Pin 19 for DI, CN7 Pin 17 for DO)</td><td>Software trigger, External digital trigger (CN1 Pin 53 for DI, CN1 Pin 54 for DO)</td></tr><tr><td>Trigger Modes</td><td colspan="4">Post triggerPost trigger with re-trigger</td></tr><tr><td>Data Transfers</td><td>Programmed I/O, Bus-mastering DMA with scatter/ gather</td><td>Programmed I/O</td><td colspan="2">Programmed I/O, Bus-mastering DMA with scatter/ gather</td></tr><tr><td colspan="5">General Purpose Timer/Counter (GPTC)</td></tr><tr><td>Number of Channels</td><td>2 on CN3</td><td>1 on CN4</td><td>4 on CN7/CN8</td><td>2 on CN1</td></tr><tr><td>Resolution</td><td colspan="4">32-bit</td></tr><tr><td>Clock Source</td><td>1. Internal Timebase [fixed 33MHz]2. External Timebase 0.01Hz-8MHz (CN3.37)</td><td>1. Internal Timebase [fixed 33MHz]2. External Timebase fixed 2MHz (CN4.1)</td><td>1. Internal Timebase [fixed 33MHz]2. External Timebase 0.01Hz-8MHz (CN8 Pin 5,6,7,8)</td><td>1. Internal Timebase [fixed 33MHz]2. External Timebase 0.01Hz-8MHz (CN1 Pin 16)</td></tr><tr><td>Clock &amp; Gate Input Level</td><td colspan="4">Logic low: VIL = 0V to 0.8V (max).Logic high: VIH = 2.0V (min.)</td></tr><tr><td>Counter Output Level</td><td colspan="4">Logic low: VIL = 0.8V (max.) @ 2.5mALogic high: VIH = 2.0V (min.) @ -2.5mA</td></tr><tr><td>Overvoltage Protection</td><td colspan="4">0V to 5.5V</td></tr><tr><td>Counter Mode</td><td colspan="4">Mode 1: Simple Gated-Event CountingMode 2: Single Period MeasurementMode 3: Single Pulse-Width MeasurementMode 4: Single-Gated Pulse GenerationMode 5: Single Triggered Pulse GenerationMode 6: Re-Triggered Single Pulse GenerationMode 7: Single-Triggered Continuous Pulse GenerationMode 8: Continuous Gated Pulse Generation</td></tr><tr><td>PWM</td><td colspan="4">Supported and can change on the fly</td></tr><tr><td colspan="5">Encoder</td></tr><tr><td>Encoder Input Channels</td><td>N/A</td><td>N/A</td><td colspan="2">2</td></tr><tr><td>Pinouts</td><td>N/A</td><td>N/A</td><td>CN8.1-12 in Mode 2 (See &quot;Programmable Function I/O&quot; on page 108.)</td><td>CN1.17-24 &amp; CN1.51-58 In Mode 2 (See &quot;Programmable Function I/O&quot; on page 108.)</td></tr><tr><td>Max. Input Frequency</td><td>N/A</td><td>N/A</td><td colspan="2">4MHz</td></tr><tr><td>Encoder Count</td><td>N/A</td><td>N/A</td><td colspan="2">(231-1) bits</td></tr><tr><td>Encoder Mode</td><td>N/A</td><td>N/A</td><td colspan="2">1. CW/CCW Encoder Mode2. X1 Encoder Mode3. X2 Encoder Mode4. X4 Encoder Mode</td></tr><tr><td>Data Transfer</td><td>N/A</td><td>N/A</td><td colspan="2">Polling &amp; DMA DMA: combined AI &amp; non-combined AI</td></tr><tr><td colspan="5">Mechanical &amp; Environmental</td></tr><tr><td>Bus Type</td><td colspan="4">PCI Express 1.0</td></tr><tr><td>Bus Width</td><td colspan="4">x1 Lane</td></tr><tr><td>Connector</td><td colspan="2">37-pin D-type connector</td><td colspan="2">68-pin VHDCI female</td></tr></table>

Table 1-1: General Specifications

<table><tr><td>Model</td><td>PCIe-9101/9121/9141</td><td>PCIe-9103</td><td>PCIe-9161-9163-9164</td><td>PCIe-9146/9147</td></tr><tr><td>Dimensions (mm)</td><td colspan="2">169.55 (L) X 16.15 (W) X 98.4 (H)</td><td>181.05 (L) x 21.1 (W) x 126.29 (H)</td><td>181.05 (L) x 19.4 (W) x 126.72 (H)</td></tr><tr><td>Weight</td><td colspan="2">118.8 g</td><td>115 g</td><td>100 g</td></tr><tr><td>Operating Temperature</td><td colspan="4">0°C to 60°C</td></tr><tr><td>Storage Temperature</td><td colspan="4">-40 to 85 °C</td></tr><tr><td>Humidity</td><td colspan="4">10% to 90%,non-condensing</td></tr><tr><td>ESD</td><td colspan="4">Contact ± 4 kV, Air ± 8 kV</td></tr><tr><td>EMI/EMC</td><td colspan="4">CE &amp; FCC Class B (EN61000-6-4/EN61000-6-2)</td></tr></table>

Table 1-1: General Specifications

# 1.4.2 Performance Specifications

# 1.4.2.1 Large Signal Bandwidth

<table><tr><td colspan="7">Large Signal Bandwidth (-3db with 0.9 of FSR of Input)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td>330kHz</td><td>400kHz</td><td>470kHz</td><td>470kHz</td><td>460kHz</td><td>470kHz</td></tr><tr><td>PCIe-9103</td><td>420kHz</td><td>720kHz</td><td>730kHz</td><td>720kHz</td><td>730kHz</td><td>730kHz</td></tr><tr><td>PCIe-9121</td><td>380kHz</td><td>560kHz</td><td>760kHz</td><td>750kHz</td><td>760kHz</td><td>760kHz</td></tr><tr><td>PCIe-9141</td><td>410kHz</td><td>570kHz</td><td>700kHz</td><td>760kHz</td><td>770kHz</td><td>770kHz</td></tr><tr><td>PCIe-9161</td><td rowspan="3">1.26Mhz</td><td rowspan="3">1.69MHz</td><td rowspan="3">2.11MHz</td><td rowspan="3">2.23MHz</td><td rowspan="3">2.66MHz</td><td rowspan="3">2.93MHz</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td><td rowspan="2" colspan="6">220kHz or 25kHz software selectable</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-2: Large Signal Bandwidth

# 1.4.2.2 Small Signal Bandwidth

<table><tr><td colspan="7">Small Signal Bandwidth (-3db with 0.1 of FSR of Input)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td>480kHz</td><td>480kHz</td><td>500kHz</td><td>500kHz</td><td>515kHz</td><td>560kHz</td></tr><tr><td>PCIe-9103</td><td>1.9MHz</td><td>2.75MHz</td><td>3.5MHz</td><td>3.5MHz</td><td>2.3MHz</td><td>1.55MHz</td></tr><tr><td>PCIe-9121</td><td>1.9MHz</td><td>2.65MHz</td><td>3.5MHz</td><td>3.45MHz</td><td>2.3MHz</td><td>1.69MHz</td></tr><tr><td>PCIe-9141</td><td>1.9MHz</td><td>2.65MHz</td><td>3.5MHz</td><td>3.45MHz</td><td>2.3MHz</td><td>1.69MHz</td></tr><tr><td>PCIe-9161</td><td rowspan="3">2.4MHz</td><td rowspan="3">3MHz</td><td rowspan="3">2.5MHz</td><td rowspan="3">4.5MHz</td><td rowspan="3">4.7MHz</td><td rowspan="3">4.95MHz</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td><td rowspan="2" colspan="6">220kHz or 25kHz software selectable</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-3: Small Signal Bandwidth

# 1.4.2.3 System Noise

<table><tr><td colspan="7">System noise (LSBrms)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td>1</td><td>1</td><td>1</td><td>1.5</td><td>2</td><td>3</td></tr><tr><td>PCIe-9103</td><td>1</td><td>1.5</td><td>1.5</td><td>2.5</td><td>3.5</td><td>5</td></tr><tr><td>PCIe-9121</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1.5</td></tr><tr><td>PCIe-9141</td><td>1</td><td>1.5</td><td>1.5</td><td>2.5</td><td>3.5</td><td>5</td></tr><tr><td>PCIe-9161</td><td rowspan="3">1.3</td><td rowspan="3">1.3</td><td rowspan="3">1.3</td><td rowspan="3">1.6</td><td rowspan="3">2.6</td><td rowspan="3">4</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td><td rowspan="2" colspan="5">1.2</td><td rowspan="2">1.7</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-4: System Noise

# 1.4.2.4 CrossTalk

<table><tr><td colspan="7">CrossTalk (dB)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td rowspan="4" colspan="6">-80</td></tr><tr><td>PCIe-9103</td></tr><tr><td>PCIe-9121</td></tr><tr><td>PCIe-9141</td></tr><tr><td>PCIe-9161</td><td rowspan="3" colspan="6">-90</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td><td rowspan="2" colspan="6">-100</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-5: CrossTalk

# 1.4.2.5 Drift – Offset

<table><tr><td colspan="7">Drift – Offset (LSB per C)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td>3</td><td>1</td><td>2</td><td>3</td><td>3</td><td>3</td></tr><tr><td>PCIe-9103</td><td>2</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr><tr><td>PCIe-9121</td><td>2</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr><tr><td>PCIe-9141</td><td>3</td><td>3</td><td>1</td><td>2</td><td>1</td><td>2</td></tr><tr><td>PCIe-9161</td><td rowspan="3" colspan="6">0.5</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td><td rowspan="2" colspan="6">1</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-6: Drift – Offset

# 1.4.2.6 Drift – Gain

<table><tr><td colspan="7">Drift – Gain (LSB per C)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr><tr><td>PCIe-9103</td><td>4</td><td>4</td><td>4</td><td>4</td><td>4</td><td>4</td></tr><tr><td>PCIe-9121</td><td>4</td><td>4</td><td>4</td><td>4</td><td>4</td><td>4</td></tr><tr><td>PCIe-9141</td><td>7</td><td>7</td><td>7</td><td>7</td><td>7</td><td>6</td></tr><tr><td>PCIe-9161</td><td rowspan="5" colspan="6">1</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr><tr><td>PCIe-9146</td></tr><tr><td>PCIe-9147</td></tr></table>

Table 1-7: Drift – Gain

# 1.4.2.7 Settling Time to Full-scale Step for ±2 LSB

<table><tr><td colspan="7">Settling time to full-scale step for ±2 LSB (μs)</td></tr><tr><td>Input Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td></tr><tr><td>PCIe-9101</td><td colspan="6">10</td></tr><tr><td>PCIe-9103</td><td colspan="6">2</td></tr><tr><td>PCIe-9121</td><td colspan="6">2</td></tr><tr><td>PCIe-9141</td><td colspan="6">2</td></tr><tr><td>PCIe-9161</td><td rowspan="3" colspan="2">1</td><td rowspan="3">1.11</td><td rowspan="3" colspan="2">1.25</td><td rowspan="3">&gt;2</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr></table>

Table 1-8: Settling Time to Full-scale Step for ±2 LSB

# 1.4.2.8 Settling Time Error at Maximum Sampling Rate, LSB

<table><tr><td colspan="8">Settling time error at maximum sampling rate, LSB (μs)</td></tr><tr><td>Model</td><td>Input Range</td><td rowspan="2">±10V</td><td rowspan="2">±5V</td><td rowspan="2">±2.5V</td><td rowspan="2">±1.25V</td><td rowspan="2">±0.625V</td><td rowspan="2">±0.3125V</td></tr><tr><td></td><td>Sampling Rate</td></tr><tr><td>PCIe-9101</td><td>100k</td><td colspan="6">±2</td></tr><tr><td>PCIe-9103</td><td rowspan="3">500k</td><td colspan="6">±2</td></tr><tr><td>PCIe-9121</td><td colspan="6">±2</td></tr><tr><td>PCIe-9141</td><td colspan="6">±2</td></tr><tr><td>PCIe-9161</td><td rowspan="3">1M</td><td rowspan="3">&lt;=±1</td><td rowspan="3" colspan="2">&lt;=±2</td><td rowspan="3" colspan="3">&lt;=±3</td></tr><tr><td>PCIe-9163</td></tr><tr><td>PCIe-9164</td></tr></table>

Table 1-9: Settling Time Error at Maximum Sampling Rate, LSB

# 1.5 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platforms.

By leveraging low-level kernel management and a user friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![This diagram depicts a layered software and hardware architecture stack.\n\n**Top Layer (Software/Management):**\nThis section is divided into a left column and three vertical columns on the right.\n\n*   **Left Column (Red Background):** Titled **'MAPS Core Device Management'**. It contains four grey sub-blocks labeled:\n    *   'Device Manager (ACE)'\n    *   'PXI Platform Resource Mgmt. Utility'\n    *   'PXI Platform ChassisWatch Utility'\n    *   'DAQ/IO Module Function Test Utility'\n\n*   **Right Columns (Development Environments):**\n    *   **Column 1:** A white top block labeled **'User APPs in C/C++'** sits above an orange block labeled **'MAPS/C'** and **'C/C++ SDK for DAQ/IO module'**.\n    *   **Column 2:** A white top block labeled **'User APPs in LabVIEW'** sits above a green block labeled **'MAPS/LV'** and **'LabVIEW SDK for DAQ/IO module'**.\n    *   **Column 3:** A white top block labeled **'User APPs in C#'** sits above a purple block labeled **'MAPS/C#'**, **'C# SDK for DAQ/IO module'**, and **'Coming soon'**.\n\n**Middle Layer (Runtime):**\nA red horizontal bar spans the width.\n*   On the left: **'MAPS Core -Device Runtime'**\n*   On the right (stacked text):\n    *   'PXI Platform Service'\n    *   'DAQ/IO Module Device Driver'\n    *   'DAQ/IO Module Runtime Library'\n\n**Bottom Layer (Hardware):**\nA blue horizontal bar displaying images of hardware devices with labels underneath:\n*   'Digitizers'\n*   'DAQ'\n*   'Edge Platform'\n*   'PXle Controllers'\n*   'PXIe/PXI Chassis'](.pcie-9100-50m-18094-1030-17/d74c1dd6ee7168abe29f1d39087ff42539e6a064bec36c0c91bcf5ad404a5129.jpg)

# 1.5.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCIe9141 Device 'PCIe'\n0: PCIe9101 Device 'PCIe'\nUSB\nNETWORK\nGeneral\nSettings\nAlias Name	PCIe-9141-0\nVendor	ADLINK Technology Inc.\nModel	PCIe9141 Device\nPCI Bus	2\nPCI Device	0\nPCI Function	0\nDMA Buffer\nAI	1024 KB\nAO	1024 KB\nDI	1024 KB\nDO	1024 KB\nUtility\nSoftFrontPanel	Launch\nPlease reboot your system to activate driver registry](.pcie-9100-50m-18094-1030-17/d42a3818f430c4ef23287268d0151645d16e40cd6fb052f82e996a5a5ed526d5.jpg)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control DAQ cards through the UI and display the acquired waveform/data on the screen.

# 1.5.2 MAPS/LV, LabVIEW Support

Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual:

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_LV

# 1.5.3 MAPS/C, C & C++ Support

Customers who develop their own programs in C or C++ environments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

https://www.adlinktech.com/Products/Data\_Acquisition/ DAQSoftware\_Utility/MAPS\_C

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# 2 Getting Started

This chapter describes the proper installation environment, installation procedures, package contents and basic information users should be aware of.

![A white document icon with black horizontal lines and a folded top-left corner, overlaid with a large red checkmark.](.pcie-9100-50m-18094-1030-17/b422639ed80f44d0054fdb3b0095ae1e6fdf335f50f9b3ecb44eb16160bc81ad.jpg)
NOTE:

Diagrams and images of equipment illustrated are for reference only. Actual system configuration and specifications may vary.

# 2.1 Package Contents

Before continuing, check the package contents for any damage and check if the following items are included in the packaging:

 PCIe-9100 Series Multi-Function Data Acquisition Card
 Product Warranty Card

The card contains electro-static sensitive components that can easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the modules carton before continuing.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface with component side up.

Inspect the module for any damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

![The image displays a warning sign featuring a red triangle with a white border and a white exclamation point in the center. Below the triangle, the word 'WARNING' appears in black capital letters.](.pcie-9100-50m-18094-1030-17/ec1efbd6845410404346a79fd2733e66d355da1a402964d2ce68147d897dac93.jpg)

WARNING: DO NOT install or apply power to equipment that is damaged or if there are missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Device Layout and I/O Connectors

# 2.2.1 PCIe-9101 PCB Layout

![181.15mm\n125.39mm\nCN3\nDNREF2\nDNREF4\nINREF*\nINA\nVREF\nADC\nFPGA\nMUX\nPCIe\nBridge\nOSC\nDI Buffer\nCN1\nDO Buffer\nCN2](.pcie-9100-50m-18094-1030-17/8c5eda11a88953483fc842ea36a49aa6d231911c16f69ecc7973c60459131d38.jpg)

Figure 2-1: PCIe-9101 PCB Front Layout

![181.15mm\nSW1\n125.39mm](.pcie-9100-50m-18094-1030-17/c5794198240f5a7184318707cbe0fda2141ce03281a0932774ac168474e8a2ee.jpg)

Figure 2-2: PCIe-9101 PCB Rear Layout

2.2.2 PCIe-9103 PCB Layout
![181.15 mm\n125.39 mm\nCN4\nDN1\nDI Photocoupler\nFPGA\nPCIe Bridge\nSW1\nDO Photocoupler\nCN2\nMUX\nINA\nADC\nCN2](.pcie-9100-50m-18094-1030-17/1961e976bb7d9a8e9138cdcdb48c737f475d2c74b133dee9738ceefd5d0afa06.jpg)

Figure 2-3: PCIe-9103 PCB Layout

2.2.3 PCIe-9121/9141 PCB Layout
![181.15 mm\n125.39 mm\nCN3\nDAC\nINA\nADC\nFPGA\nSW1\nPCIe\nBridge\nDO\nBuffer\nCN1\nBuffer\nCN2](.pcie-9100-50m-18094-1030-17/4e577330ef164af82fc091484ea1e5eb7df4236cfbad8aa5c1b8c939a9dcf85b.jpg)

Figure 2-4: PCIe-9121/9141 PCB Layout

2.2.4 PCIe-9146/9147 PCB Layout
![181.05mm\n126.287mm\nCN1\nDO Buffer\nLine Driver\nCN8\nDI Buffer\nDAC\nFPGA\nMUX\nPGA\nADC\nPCIe Bridge\nSW1](.pcie-9100-50m-18094-1030-17/31cb1c365bc1f46d614c6f6d512cf2a98a14177b49d091d0e75d42bd042220ac.jpg)

Figure 2-5: PCIe-9146/9147 PCB Layout

2.2.5 PCIe-9161/9163 PCB Layout
![181.05mm\n126.29mm\nCN1\nMUX\nDAC\nCN9\nPGA\nADC\nFPGA\nPCIe Bridge\nDO Buffer\nSW1\nDI Buffer\nCN8\nCN7](.pcie-9100-50m-18094-1030-17/b3529cf4c6bc2c8173383e8c918eef8c2dd662f97c5821be6d38b73f33a37a37.jpg)

Figure 2-6: PCIe-9161/9163 PCB Front Layout

![Line Receiver](.pcie-9100-50m-18094-1030-17/bfe20ebaaca8cde344fc5c935e566aa27f9c5dbd3f654f713d68cec44b26f6f4.jpg)

Figure 2-7: PCIe-9161/9163 PCB Rear Layout

2.2.6 PCIe-9164 PCB Layout
![181.05mm\n126.29mm\nCN1 MUX PGA ADC PAC\nCN6 PN1 DN2 DN3 DN4 DN5 DN6 DN7 DN8 DN9 DN10 DN11 DN12 DN13 DN14 DN15 DN16 DN17 DN18 DN19 DN20 DN21 DN22 DN23 DN24 DN25 DN26 DN27 DN28 DN29 DN30 DN31 DN32 DN33 DN34 DN35 DN36 DN37 DN38 DN39 DN40 DN41 DN42 DN43 DN44 DN45 DN46 DN47 DN48 DN49 DN50 DN51 DN52 DN53 DN54 DN55 DN56 DN57 DN58 DN59 DN60 DN61 DN62 DN63 DN64 DN65 DN66 DN67 DN68 DN69 DN70 DN71 DN72 DN73 DN74 DN75 DN76 DN77 DN78 DN79 DN80\nDAC CN9 DI Buffer CN8\nPCIe Bridge DO Buffer CN7](.pcie-9100-50m-18094-1030-17/368724f31ab417f7e8adcb9b8a64ce62b91440f71daaa30659068b4055bb0e00.jpg)

Figure 2-8: PCIe-9164 PCB Front Layout

![Line Receiver](.pcie-9100-50m-18094-1030-17/6727ab08a7f76059d81af909632bb1c9495b2d31c850fce4165aae84367d1dad.jpg)

Figure 2-9: PCIe-9164 PCB Rear Layout

# 2.3 Switch and Jumper Settings

The following item can be configured with jumpers:

 analog output range on PCIe-9101
 5V or 12V output setting on CN1 Pins 15, 49 on PCIe-9146/ 9147
 5V or 12V output setting on CN1 Pins 34 on PCIe-9161/ 9163/9164

The card's jumpers and switches are preset at the factory. You can change the jumper settings for your own applications.

<table><tr><td>Configuration</td><td>Attributes</td><td>Jumper</td></tr><tr><td>D/A Reference Source</td><td>Internal Reference or External Reference</td><td>JP4</td></tr><tr><td>5V or 12V output</td><td>Output 5V or 12V on CN1 Pins 15, 49</td><td>CN8</td></tr><tr><td>5V or 12V output</td><td>Output 5V or 12V on CN1 Pins 15, 49</td><td>CN9</td></tr></table>

Table 2-1: Jumper Settings

# 2.3.1 D/A Reference Voltage Settings

The D/A converter's reference voltage source can be supplied both internally and externally. The external reference voltage comes from connector CN3, Pin 31 (ExtRef1) and Pin12 (ExtRef2). The reference source of the D/A channel 1 and channel 2 are selected by JP4.

<table><tr><td>D/A CH1 is InternalD/A CH2 is Internal(Default setting)</td><td colspan="2">ExtRef2JP4 &lt;img src="images/4c2e432bbd730d418090ff4462a4f67c85c75fa18a21e8445f09c189fa0a753e.jpg"/&gt;INTREF INTREF</td><td>ExtRef1INTREF</td></tr><tr><td>D/A CH1 is ExternalD/A CH2 is Internal</td><td colspan="2">ExtRef2JP4 &lt;img src="images/4630aa8ccaae4374e446f9d5b23997de28fe4bda1da8f4da5696c2ef4b5b0d05.jpg"/&gt;INTREF INTREF</td><td>ExtRef1INTREF</td></tr><tr><td>D/A CH1 is InternalD/A CH2 is External</td><td colspan="2">ExtRef2JP4 &lt;img src="images/344f95b9a58faada152ed12e71b91ee180134c9961c54607bc06c851efe36d2d.jpg"/&gt;INTREF INTREF</td><td>ExtRef1INTREF</td></tr><tr><td>D/A CH1 is ExternalD/A CH2 is External</td><td colspan="2">ExtRef2JP4 &lt;img src="images/d022cf52cff5a341ee9e9487c0e10d7f98b928030d1c967919067de37db14507.jpg"/&gt;INTREF INTREF</td><td>ExtRef1INTREF</td></tr></table>

Table 2-2: D/A Reference Voltage Settings

<table><tr><td>No output on CN1 Pin 15, 49.</td><td>+5V +12V</td></tr><tr><td>5V output on CN1 Pin 15, 49.</td><td>+5V +12V</td></tr><tr><td>12V output on CN1 Pin 15, 49.</td><td>+5V +12V</td></tr></table>

Figure 2-10: PCIe-9146/9147 CN8 Settings

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>14</td><td>48</td><td></td></tr><tr><td>+12V or 5V</td><td>15</td><td>49</td><td>+12V or 5V</td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>34</td><td>68</td><td></td></tr></table>

Table 2-3: PCIe-9146/9147 5V/12V Output Pin on CN1 Pin Assignments

<table><tr><td>No output on CN1 Pin 34.</td><td>+5V +12V</td></tr><tr><td>5V output on CN1 Pin 34.</td><td>+5V +12V</td></tr><tr><td>12V output on CN1 Pin 34.</td><td>+5V +12V</td></tr></table>

Figure 2-11: PCIe-9161/9163/9164 CN9 Settings

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>14</td><td>48</td><td></td></tr><tr><td></td><td>15</td><td>49</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>+12V or 5V</td><td>34</td><td>68</td><td>DGND</td></tr></table>

Table 2-4: PCIe-9161/9163/9164 5V/12V Output Pin on CN1 Pin Assignments

# 2.3.2 Board ID (SW1)

The PCIe-9100 Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for identifying each card’s device number. After setting each PCIe-9100 Series card, you can identify each card in the system with different device numbers. The default value of the Board ID is 0 and if you need to adjust it to another value, set the SW1 switch as shown in the table below.

![ON\nDIP\n1 2 3 4](.pcie-9100-50m-18094-1030-17/b693d5e99520e561907f7b800b99fd22486dcd4e0bc555ce9fe7f362ce4158e9.jpg)

Figure 2-12: Board ID SW1 DIP Switch

<table><tr><td>SW1</td><td>Pin 1</td><td>Pin 2</td><td>Pin 3</td><td>Pin 4</td></tr><tr><td>Board ID</td><td>ID0</td><td>ID1</td><td>ID2</td><td>ID3</td></tr><tr><td>0</td><td>Off</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>1</td><td>On</td><td>Off</td><td>Off</td><td>Off</td></tr><tr><td>2</td><td>Off</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>3</td><td>On</td><td>On</td><td>Off</td><td>Off</td></tr><tr><td>4</td><td>Off</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>5</td><td>On</td><td>Off</td><td>On</td><td>Off</td></tr><tr><td>6</td><td>Off</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>7</td><td>On</td><td>On</td><td>On</td><td>Off</td></tr><tr><td>8</td><td>Off</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>9</td><td>On</td><td>Off</td><td>Off</td><td>On</td></tr><tr><td>10</td><td>Off</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>11</td><td>On</td><td>On</td><td>Off</td><td>On</td></tr><tr><td>12</td><td>Off</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>13</td><td>On</td><td>Off</td><td>On</td><td>On</td></tr><tr><td>14</td><td>Off</td><td>On</td><td>On</td><td>On</td></tr><tr><td>15</td><td>On</td><td>On</td><td>On</td><td>On</td></tr></table>

Table 2-5: Board ID by SW1 Switch

# 2.4 Connector Pin Assignments

# 2.4.1 PCIe-9101/9121/9141/9103

The PCIe-9101/9121/9141/9103 comes equipped with two 20-pin insulation displacement connectors (CN1 and CN2) and one 37- pin D-type connector (CN3). CN1 and CN2 are located on the board and CN3 is located on the faceplate.

CN1 is for digital signal input, CN2 is for digital signal output, and CN3 is for analog input/output and timer/counter signals.

# 2.4.1.1 CN3: Analog Input/Output & Counter/Timer

CN3 is a 37-pin D-type connector with the following pin assignments.

![(For single-ended connection)\n| Label | Pin 1 | Pin 2 | Pin 3 | Pin 4 | Pin 5 | Pin 6 | Pin 7 | Pin 8 |\n|---|---|---|---|---|---|---|---|---|\n| CN3 | 1 | 20 | 21 | 22 | 23 | 24 | 25 | 26 |\n| AI8 | - | - | - | - | - | - | - | - |\n| AI9 | - | - | - | - | - | - | - | - |\n| AI10 | - | - | - | - | - | - | - | - |\n| AI11 | - | - | - | - | - | - | - | - |\n| AI12 | - | - | - | - | - | - | - | - |\n| AI13 | - | - | - | - | - | - | - | - |\n| AI14 | - | - | - | - | - | - | - | - |\n| AI15 | - | - | - | - | - | - | - | - |\n| A.GND | 10 | 28 | 29 | 30 | 31 | 32 | 33 | GATE0 |\n| A.GND | 11 | 29 | 30 | 31 | 32 | 33 | 34 | GATE1 |\n| A.GND | 12 | 30 | 31 | 32 | 33 | 34 | 35 | COUT1 |\n| AO1 | - | - | - | - | - | - | - | N/C |\n| ExtRef1 | +12V | 13 | 14 | 15 | 16 | 17 | 18 | N/C |\n| AO2 | +5V | 19 | 20 | 21 | 22 | 23 | 24 | ExtCLK |\n| ExtTrg | +5V | 19 | 20 | 21 | 22 | 23 | 24 | N/C |\n| COUT0 | +5V | 19 | 20 | 21 | 22 | 23 | 24 | N/C |\n| COUT1 | +5V | 19 | 20 | 21 | 22 | 23 | 24 | N/C |\n| N/C | +5V | 19 | 20 | 21 | 22 | 23 | 24 | N/C |\n| ExtCLK (not labeled) only) is not included in the image. The values are estimated based on the number of pins (e.g., “CN3” or “CN3”, “GATE0”, “COUT1”, etc.). The chart contains a legend for the data series: “AI0”, “AI1”, “AI2”, “AI3”, “AI4”, “AI5”, “AI6”, “AI7”, “A.GND”, “A.GND”, “AO1”, “AO2”, “GATE0”, “GATE1”, and “N/C”.](.pcie-9100-50m-18094-1030-17/3c0737eeeb792a91cc1c87ad3088dddf26329ca187235c9da9a73e3966d7a8f2.jpg)

![| Label   | Value |\n|---------|-------|\n| AIH0    | 1     |\n| AIH1    | 2     |\n| AIH2    | 3     |\n| AIH3    | 4     |\n| AIH4    | 5     |\n| AIH5    | 6     |\n| AIH6    | 7     |\n| AIH7    | 8     |\n| A.GND   | 9     |\n| A.GND   | 10    |\n| V.REF   | 11    |\n| ExtRef2 | 12    |\n| +12V    | 13    |\n| D.GND   | 14    |\n| D.GND   | 15    |\n| COUT0   | 16    |\n| ExtTrg  | 17    |\n| N/C     | 18    |\n| +5V     | 19    |\n| 20      |       |\n| 21      |       |\n| 22      |       |\n| 23      |       |\n| 24      |       |\n| 25      |       |\n| 26      |       |\n| 27      |       |\n| 28      |       |\n| 29      |       |\n| 30      |       |\n| 31      |       |\n| 32      |       |\n| 33      |       |\n| 34      |       |\n| 35      |       |\n| 36      |       |\n| 37      |       |\n| AIL0    |       |\n| AIL1    |       |\n| AIL2    |       |\n| AIL3    |       |\n| AIL4    |       |\n| AIL5    |       |\n| AIL6    |       |\n| AIL7    |       |\n| A.GND   |       |\n| A.GND   |       |\n| AO1     |       |\n| ExtRef1 |       |\n| AO2     |       |\n| GATE0   |       |\n| GATE1   |       |\n| COUT1   |       |\n| N/C     |       |\n| ExtCLK  |       |](.pcie-9100-50m-18094-1030-17/d6d0e3631ea5ee6fc3b80a6a1d8a288aa2c5ae4ece75ad83402201842a3e4513.jpg)

Figure 2-13: PCIe-9101 CN3 Pin Assignments

(For single-ended connection)
![| Label | Value |\n|-------|-------|\n| AI0   | 1     |\n| AI1   | 2     |\n| AI2   | 3     |\n| AI3   | 4     |\n| AI4   | 5     |\n| AI5   | 6     |\n| AI6   | 7     |\n| AI7   | 8     |\n| A.GND | 9     |\n| AI8   | 10    |\n| AI9   | 11    |\n| AI10  | 12    |\n| AI11  | 13    |\n| AI12  | 14    |\n| AI13  | 15    |\n| AI14  | 16    |\n| AI15  | 17    |\n| N/C   | 18    |\n| +12V  | 19    |](.pcie-9100-50m-18094-1030-17/e17e621936f2889f0a5c46645053f05e0851eb51239ec4545cb29aa2810720ab.jpg)

(For differential connection)
![| Label | Value |\n|-------|-------|\n| AIH0  | 1     |\n| AIH1  | 2     |\n| AIH2  | 3     |\n| AIH3  | 4     |\n| AIH4  | 5     |\n| AIH5  | 6     |\n| AIH6  | 7     |\n| AIH7  | 8     |\n| A.GND | 9     |\n| AIH8  | 10    |\n| AIH9  | 11    |\n| AIH10 | 12    |\n| AIH11 | 13    |\n| AIH12 | 14    |\n| AIH13 | 15    |\n| AIH14 | 16    |\n| AIH15 | 17    |\n| N/C   | 18    |\n| +12V  | 19    |\n| 20    |       |\n| 21    |       |\n| 22    |       |\n| 23    |       |\n| 24    |       |\n| 25    |       |\n| 26    |       |\n| 27    |       |\n| 28    |       |\n| 29    |       |\n| 30    |       |\n| 31    |       |\n| 32    |       |\n| 33    |       |\n| 34    |       |\n| 35    |       |\n| 36    |       |\n| 37    |       |\nA.GND|\nAIL0|\nAIL1|\nAIL2|\nAIL3|\nAIL4|\nAIL5|\nAIL6|\nAIL7|\nA.GND|\nAIL8|\nAIL9|\nAIL10|\nAIL11|\nAIL12|\nAIL13|\nAIL14|\nAIL15|\nA.GND|](.pcie-9100-50m-18094-1030-17/edee1192ea4e732e1fe2b5e4cce3fd39e89e506fc249e524b5132bf74c4bc060.jpg)

Figure 2-14: PCIe-9103 CN3 Pin Assignments

(For single-ended connection)
![| Label | Value |\n|-------|-------|\n| AI0   | 1     |\n| AI1   | 2     |\n| AI2   | 3     |\n| AI3   | 4     |\n| AI4   | 5     |\n| AI5   | 6     |\n| AI6   | 7     |\n| AI7   | 8     |\n| A.GND | 9     |\n| A.GND | 10    |\n| N/C   | 11    |\n| N/C   | 12    |\n| +12V  | 13    |\n| D.GND | 14    |\n| D.GND | 15    |\n| COUNT0| 16    |\n| ExtTrg| 17    |\n| N/C   | 18    |\n| +5V   | 19    |\n| AI8   | 20    |\n| AI9   | 21    |\n| AI10  | 22    |\n| AI11  | 23    |\n| AI12  | 24    |\n| AI13  | 25    |\n| AI14  | 26    |\n| AI15  | 27    |\n| A.GND | 28    |\n| A.GND | 29    |\n| AO1   | 30    |\n| AO2   | 31    |\n| GATE0 | 32    |\n| GATE1 | 33    |\n| COUNT1| 34    |\n| N/C   | 35    |\n| ExtCLK| 36    |](.pcie-9100-50m-18094-1030-17/962ac5ed32bb74d6a358d683c1ab17d0d4268f68ac96d6ee5c06d7ed3d01c3db.jpg)

(For differential connection)
![| Label     | Value |\n| --------- | ----- |\n| AIH0      | 1     |\n| AIH1      | 2     |\n| AIH2      | 3     |\n| AIH3      | 4     |\n| AIH4      | 5     |\n| AIH5      | 6     |\n| AIH6      | 7     |\n| AIH7      | 8     |\n| A.GND     | 9     |\n| A.GND     | 10    |\n| N/C       | 11    |\n| N/C       | 12    |\n| +12V      | 13    |\n| D.GND     | 14    |\n| D.GND     | 15    |\n| COUNT0    | 16    |\n| ExtTrg    | 17    |\n| N/C       | 18    |\n| +5V       | 19    |\n| 20        |       |\n| 21        |       |\n| 22        |       |\n| 23        |       |\n| 24        |       |\n| 25        |       |\n| 26        |       |\n| 27        |       |\n| 28        |       |\n| 29        |       |\n| 30        |       |\n| 31        |       |\n| 32        |       |\n| 33        |       |\n| 34        |       |\n| 35        |       |\n| 36        |       |\n| 37        |       |\n| AIL0      |       |\n| AIL1      |       |\n| AIL2      |       |\n| AIL3      |       |\n| AIL4      |       |\n| AIL5      |       |\n| AIL6      |       |\n| AIL7      |       |\n| A.GND     |       |\n| A.GND     |       |\n| AO1       |       |\n| AO2       |       |\n| GATE0     |       |\n| GATE1     |       |\n| COUNT1    |       |\n| N/C       |       |\n| ExtCLK    |       |](.pcie-9100-50m-18094-1030-17/ac4226690c006c820ce8f781d7319d5eea6460b92bbb796fb3d7b18a57652b69.jpg)

Figure 2-15: PCIe-9121/9141 CN3 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>AI &lt;0...31&gt;</td><td>I</td><td>Signal-ended Analog Input Channels 0-31</td></tr><tr><td>AIH &lt;0...15&gt;</td><td>I</td><td>Differential Analog High Input Channels 0-15</td></tr><tr><td>AIL &lt;0...15&gt;</td><td>I</td><td>Differential Analog Low Input Channels 0-15</td></tr><tr><td>ExtRef &lt;1,2&gt;</td><td>I</td><td>External Reference Voltage for D/A CH &lt;1,2&gt;</td></tr><tr><td>AO &lt;0,1&gt;</td><td>O</td><td>Analog Output Channels &lt;0,1&gt;</td></tr><tr><td>ExtCLK</td><td>I</td><td>External Clock</td></tr><tr><td>ExtTrig</td><td>I</td><td>External Trigger Signal</td></tr><tr><td>GATE &lt;0,1&gt;</td><td>I</td><td>Gate Input &lt;0,1&gt;</td></tr><tr><td>COUT&lt;0,1&gt;</td><td>O</td><td>Signal Output of Counter Channels &lt;0,1&gt;</td></tr><tr><td>V.REF</td><td>O</td><td>Voltage Reference</td></tr><tr><td>A.GND</td><td></td><td>Analog Ground</td></tr><tr><td>D.GND</td><td></td><td>Digital Ground</td></tr><tr><td>+12V</td><td>O</td><td>12V power output @ 0.2A</td></tr><tr><td>+5V</td><td>O</td><td>5V power output @ 0.2A</td></tr><tr><td>NC</td><td></td><td>No connect</td></tr></table>

Table 2-6: CN3 Pin Assignment Legend

# 2.4.1.2 CN1/CN2: Digital Signal Input/Output

CN1 and CN2 are 20-pin insulation displacement connectors for digital signal input/output with the following pin assignments.

![DI 0 —— 1 2 —— DI 1\nDI 2 —— 3 4 —— DI 3\nDI 4 —— 5 6 —— DI 5\nDI 6 —— 7 8 —— DI 7\nDI 8 —— 9 10 —— DI 9\nDI 10 —— 11 12 —— DI 11\nDI 12 —— 13 14 —— DI 13\nDI 14 —— 15 16 —— DI 15\nGND —— 17 18 —— GND\n+5V —— 19 20 —— DI_SYNC_IN](.pcie-9100-50m-18094-1030-17/a11f7e5b38fad4834405b86fec19b1fcba00a263af58c613ea87dffa0d7c37b3.jpg)

Figure 2-16: PCIe-9101/21/41 CN1 Pin Assignments

![DO 0 —— 1 2 —— DO 1\nDO 2 —— 3 4 —— DO 3\nDO 4 —— 5 6 —— DO 5\nDO 6 —— 7 8 —— DO 7\nDO 8 —— 9 10 —— DO 9\nDO 10 —— 11 12 —— DO 11\nDO 12 —— 13 14 —— DO 13\nDO 14 —— 15 16 —— DO 15\nGND —— 17 18 —— GND\n+5V —— 19 20 —— DO_SYNC_OUT](.pcie-9100-50m-18094-1030-17/bdd8f31681045855a1c3142c56c11786c4c1db9f6ac7c6c6b9a3497c1c98d4b6.jpg)

Figure 2-17: PCIe-9101/21/41 CN2 Pin Assignments

![DI0 —— 1 2 —— DI1\nDI2 —— 3 4 —— DI3\nDI4 —— 5 6 —— DI5\nDI6 —— 7 8 —— DI7\nDI8 —— 9 10 —— DI9\nDI10 —— 11 12 —— DI11\nDI12 —— 13 14 —— DI13\nDI14 —— 15 16 —— DI15\nEICOM1 —— 17 18 —— EICOM3\nEICOM2 —— 19 20 —— EICOM4](.pcie-9100-50m-18094-1030-17/b9b1cbab346a859fc918407be1aaf5e1253c411bb898ec6d273d6441e68250ea.jpg)

Figure 2-18: PCIe-9103 CN1 Pin Assignments

![DO0 —— 1 2 —— DO1\nDO2 —— 3 4 —— DO3\nDO4 —— 5 6 —— DO5\nDO6 —— 7 8 —— DO7\nDO8 —— 9 10 —— DO9\nDO10 —— 11 12 —— DO11\nDO12 —— 13 14 —— DO13\nDO14 —— 15 16 —— DO15\nEOGND —— 17 18 —— EOGND\nVpower —— 19 20 —— Vpower](.pcie-9100-50m-18094-1030-17/68b2b24d43d1c5a5bfdfc28d1e0c0573fd0c420b835bfbb5002d6eeffb7d9393.jpg)

Figure 2-19: PCIe-9103 CN2 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>DI &lt;0...15&gt;</td><td>I</td><td>Digital Input signal channels 0-15</td></tr><tr><td>DO &lt;0...15&gt;</td><td>O</td><td>Digital Output signal channels 0-15</td></tr><tr><td>DI_SYNC_IN</td><td>I</td><td>Digital Input synchronization clock source in</td></tr><tr><td>DO_SYNC_OUT</td><td>O</td><td>Digital Output synchronization clock source out</td></tr><tr><td>GND</td><td></td><td>Digital Ground</td></tr><tr><td>+12V</td><td>O</td><td>12V power output @ 0.2A</td></tr><tr><td>+5V</td><td>O</td><td>5V power output @ 0.2A</td></tr><tr><td>EICOM&lt;1...4&gt;</td><td>I</td><td>Common plane for Isolated Input group.</td></tr><tr><td>EOGND</td><td></td><td>Isolated Output Signal Ground.</td></tr><tr><td>Vpower</td><td>I</td><td>Isolated Output driver&#x27;s power supply.Supports 5 to 35V.</td></tr></table>

Table 2-7: CN1/CN2 Pin Assignment Legend

# 2.4.1.3 CN4: External Signal Connector (PCIe-9103 only)

CN4 is a 10-pin connector used for external signal connections with the following pin assignments.

![ExtCLK In —— 1 —— NC/GND\nCOUT0 —— 3 —— NC\nGATE0 IN —— 5 —— +5V\nGND —— 7 —— ExtTrg In\nNC —— 9 —— NC/GND](.pcie-9100-50m-18094-1030-17/83145e85839f5cd49d33099bb312578dc028cb2701a6d181b3fa570183522d9a.jpg)

Figure 2-20: CN4 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>ExtCLK In/CONVS.</td><td>I</td><td>External Clock or Conversion clock signal input</td></tr><tr><td>NC</td><td></td><td>No Connection</td></tr><tr><td>GATE</td><td>I</td><td>External Gate Control Signal</td></tr></table>

Table 2-8: CN4 Pin Assignment Legend

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>COUT</td><td>O</td><td>Output of Counter</td></tr><tr><td>ExtTrg In</td><td>I</td><td>External A/D Trigger Signal</td></tr><tr><td>+5V</td><td>O</td><td>+5V output</td></tr><tr><td>GND</td><td></td><td>Ground</td></tr></table>

Table 2-8: CN4 Pin Assignment Legend

# 2.4.2 PCIe-9146/9147

The PCIe-9146/9147 comes equipped with one 68-pin SCSI-type female connector (CN1). CN1 is located on the faceplate which is used for analog input/output, digital signal input/output, timer/ counter signals and encoder signals.

# 2.4.2.1 PCIe-9146/9147 CN1 Connector

CN1 is a 68-pin SCSI-type connector with the following pin assignments.

<table><tr><td>NC</td><td>1</td><td>35</td><td>NC</td></tr><tr><td>AI_AO_Cal+</td><td>2</td><td>36</td><td>AI_AO_Cal-</td></tr><tr><td>NC</td><td>3</td><td>37</td><td>NC</td></tr><tr><td>NC</td><td>4</td><td>38</td><td>NC</td></tr><tr><td>AGND</td><td>5</td><td>39</td><td>AGND</td></tr><tr><td>NC</td><td>6</td><td>40</td><td>NC</td></tr><tr><td>AIH3</td><td>7</td><td>41</td><td>AIL3</td></tr><tr><td>AGND</td><td>8</td><td>42</td><td>AGND</td></tr><tr><td>AIH2</td><td>9</td><td>43</td><td>AIL2</td></tr><tr><td>AIH1</td><td>10</td><td>44</td><td>AIL1</td></tr><tr><td>AGND</td><td>11</td><td>45</td><td>AGND</td></tr><tr><td>AIH0</td><td>12</td><td>46</td><td>AIL0</td></tr><tr><td>AO1</td><td>13</td><td>47</td><td>AGND</td></tr><tr><td>AO0</td><td>14</td><td>48</td><td>AGND</td></tr><tr><td>+12V or 5V</td><td>15</td><td>49</td><td>+12V or 5V</td></tr><tr><td>Ext. Time Base or GPTC CLK0</td><td>16</td><td>50</td><td>Ext. CONVSN. or GPTC CLK1</td></tr><tr><td>DI0 / DI0 / EA0+</td><td>17</td><td>51</td><td>DI8 / GPTC GATE0 / EA0-</td></tr><tr><td>DI1 / DI1 / EB0+</td><td>18</td><td>52</td><td>DI9 / GPTC GATE1 / EB0-</td></tr><tr><td>DI2 / DI2 / EZ0+</td><td>19</td><td>53</td><td>DI10 / AI Trigger In/ EZ0-</td></tr><tr><td>DI3 /DI3 / EORG0+</td><td>20</td><td>54</td><td>DI11 / AO Trigger In / NA</td></tr><tr><td>DI4 / DI4 / NA</td><td>21</td><td>55</td><td>DI12 / NA / EORG1</td></tr><tr><td>DI5 / DI5 / EA1+</td><td>22</td><td>56</td><td>DI13 / NA / EA1-</td></tr><tr><td>DI6 / DI6 / EB1+</td><td>23</td><td>57</td><td>DI14 / NA / EB1-</td></tr><tr><td>DI7 / DI7 / EZ1+</td><td>24</td><td>58</td><td>DI15 / NA / EZ1-</td></tr><tr><td>DGND</td><td>25</td><td>59</td><td>DI Sync In</td></tr><tr><td>DO0</td><td>26</td><td>60</td><td>DO8 / GPTC COUT0 / DO8</td></tr><tr><td>DO1</td><td>27</td><td>61</td><td>DO9 / GPTC COUT1 / DO9</td></tr><tr><td>DO2</td><td>28</td><td>62</td><td>DO10 / NA / DO10</td></tr><tr><td>DO3</td><td>29</td><td>63</td><td>DO11 / NA / DO11</td></tr><tr><td>DO4</td><td>30</td><td>64</td><td>DO12 / NA / DO12</td></tr><tr><td>DO5</td><td>31</td><td>65</td><td>DO13 / NA / DO13</td></tr><tr><td>DO6</td><td>32</td><td>66</td><td>DO14 / NA / DO14</td></tr><tr><td>DO7</td><td>33</td><td>67</td><td>DO15 / NA / DO15</td></tr><tr><td>DGND</td><td>34</td><td>68</td><td>DO Sync Out</td></tr></table>

Figure 2-21: PCIe-9146 CN1 Pin Assignments

<table><tr><td>AIH7</td><td>1</td><td>35</td><td>AIL7</td></tr><tr><td>AI_AO_Cal+</td><td>2</td><td>36</td><td>AI_AO_Cal-</td></tr><tr><td>AIH6</td><td>3</td><td>37</td><td>AIL6</td></tr><tr><td>AIH5</td><td>4</td><td>38</td><td>AIL5</td></tr><tr><td>AGND</td><td>5</td><td>39</td><td>AGND</td></tr><tr><td>AIH4</td><td>6</td><td>40</td><td>AIL4</td></tr><tr><td>AIH3</td><td>7</td><td>41</td><td>AIL3</td></tr><tr><td>AGND</td><td>8</td><td>42</td><td>AGND</td></tr><tr><td>AIH2</td><td>9</td><td>43</td><td>AIL2</td></tr><tr><td>AIH1</td><td>10</td><td>44</td><td>AIL1</td></tr><tr><td>AGND</td><td>11</td><td>45</td><td>AGND</td></tr><tr><td>AIH0</td><td>12</td><td>46</td><td>AIL0</td></tr><tr><td>AO1</td><td>13</td><td>47</td><td>AGND</td></tr><tr><td>AO0</td><td>14</td><td>48</td><td>AGND</td></tr><tr><td>+12V or 5V</td><td>15</td><td>49</td><td>+12V or 5V</td></tr><tr><td>Ext. Time Base or GPTC CLK0</td><td>16</td><td>50</td><td>Ext. CONVSN. or GPTC CLK1</td></tr><tr><td>DI0 / DI0 / EA0+</td><td>17</td><td>51</td><td>DI8 / GPTC GATE0 / EA0-</td></tr><tr><td>DI1 / DI1 / EB0+</td><td>18</td><td>52</td><td>DI9 / GPTC GATE1 / EB0-</td></tr><tr><td>DI2 / DI2 / EZ0+</td><td>19</td><td>53</td><td>DI10 / AI Trigger In / EZ0-</td></tr><tr><td>DI3 /DI3 / EORG0+</td><td>20</td><td>54</td><td>DI11 / AO Trigger In / NA</td></tr><tr><td>DI4 / DI4 / NA</td><td>21</td><td>55</td><td>DI12 / NA / EORG1</td></tr><tr><td>DI5 / DI5 / EA1+</td><td>22</td><td>56</td><td>DI13 / NA / EA1-</td></tr><tr><td>DI6 / DI6 / EB1+</td><td>23</td><td>57</td><td>DI14 / NA / EB1-</td></tr><tr><td>DI7 / DI7 / EZ1+</td><td>24</td><td>58</td><td>DI15 / NA / EZ1-</td></tr><tr><td>DGND</td><td>25</td><td>59</td><td>DI Sync In</td></tr><tr><td>DO0</td><td>26</td><td>60</td><td>DO8 / GPTC COUT0 / DO8</td></tr><tr><td>DO1</td><td>27</td><td>61</td><td>DO9 / GPTC COUT1 / DO9</td></tr><tr><td>DO2</td><td>28</td><td>62</td><td>DO10 / NA / DO10</td></tr><tr><td>DO3</td><td>29</td><td>63</td><td>DO11 / NA / DO11</td></tr><tr><td>DO4</td><td>30</td><td>64</td><td>DO12 / NA / DO12</td></tr><tr><td>DO5</td><td>31</td><td>65</td><td>DO13 / NA / DO13</td></tr><tr><td>DO6</td><td>32</td><td>66</td><td>DO14 / NA / DO14</td></tr><tr><td>DO7</td><td>33</td><td>67</td><td>DO15 / NA / DO15</td></tr><tr><td>DGND</td><td>34</td><td>68</td><td>DO Sync Out</td></tr></table>

Figure 2-22: PCIe-9147 CN1 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>AIH &lt;0...7&gt;</td><td>I</td><td>Differential Analog High Input Channels 0-7</td></tr><tr><td>AIL &lt;0...7&gt;</td><td>I</td><td>Differential Analog Low Input Channels 0-7</td></tr><tr><td>AO &lt;0,1&gt;</td><td>O</td><td>Analog Output Channels &lt;0,1&gt;</td></tr><tr><td>AGND</td><td></td><td>Analog Ground</td></tr><tr><td>Ext. Time Base</td><td>I</td><td>External Time Base Clock Signal Input</td></tr><tr><td>Ext. CONVSN</td><td>I</td><td>External Conversion Clock Signal Input</td></tr><tr><td>AI Trigger In</td><td>I</td><td>External Analog Input Trigger Signal Input</td></tr><tr><td>AO Trigger In</td><td>I</td><td>External Analog Output Trigger Signal Input</td></tr><tr><td>DI &lt;0...15&gt;</td><td>I</td><td>Digital Input Channels 0-15</td></tr><tr><td>DI Sync In</td><td>I</td><td>Digital Input synchronization clock source</td></tr><tr><td>DO &lt;0...15&gt;</td><td>O</td><td>Digital Output Channels 0-15</td></tr><tr><td>DO Sync Out</td><td>O</td><td>Digital Output synchronization clock source out</td></tr><tr><td>GPTC CLK &lt;0,1&gt;</td><td>I</td><td>Source clock input of GPTC&lt;0,1&gt;</td></tr><tr><td>GPTC GATE &lt;0,1&gt;</td><td>I</td><td>Gate Input of GPTC&lt;0,1&gt;</td></tr><tr><td>GPTC COUT &lt;0,1&gt;</td><td>O</td><td>Output of GPTC&lt;0,1&gt;</td></tr><tr><td>EA &lt;0,1&gt;</td><td>I</td><td>Encoder A Phase</td></tr><tr><td>EB &lt;0,1&gt;</td><td>I</td><td>Encoder B Phase</td></tr><tr><td>EZ &lt;0,1&gt;</td><td>I</td><td>Encoder Z Phase</td></tr><tr><td>EORG &lt;0,1&gt;</td><td>I</td><td>Encoder Original Signal</td></tr><tr><td>DGND</td><td></td><td>Digital Ground</td></tr><tr><td>+12V</td><td>O</td><td>12V power output @ 0.2A</td></tr><tr><td>5V</td><td>O</td><td>5V power output @ 0.2A</td></tr><tr><td>NC</td><td></td><td>No connect</td></tr><tr><td>NA</td><td></td><td>No function</td></tr><tr><td>AI_AO_Cal</td><td>I</td><td>Calibration Voltage Input, only factory used.</td></tr></table>

Table 2-9: PCIe-9146/9147 CN1 Pin Assignment Legend

# 2.4.3 PCIe-9161/9163/9164

The PCIe-9161/9163/9164 comes equipped with one/two 68-pin SCSI - type female connector (CN1/CN6) and two 20-pin insulation dis- placement connectors (CN7/CN8). CN1/CN6 are located on the faceplate and CN7/CN8 are located on the board. CN1/CN6 are used for analog input/output, and CN7/CN8 are used for digital signal input/output.

# 2.4.3.1 PCIe-9161/9163/9164 CN1/CN6 Connector

CN1/CN6 are 68-pin SCSI-type female connectors with the following pin assignments.

<table><tr><td>NC</td><td>1</td><td>35</td><td>NC</td></tr><tr><td>NC</td><td>2</td><td>36</td><td>NC</td></tr><tr><td>NC</td><td>3</td><td>37</td><td>NC</td></tr><tr><td>NC</td><td>4</td><td>38</td><td>NC</td></tr><tr><td>AGND</td><td>5</td><td>39</td><td>AGND</td></tr><tr><td>AGND</td><td>6</td><td>40</td><td>AGND</td></tr><tr><td>AI15</td><td>7</td><td>41</td><td>NC</td></tr><tr><td>AI14</td><td>8</td><td>42</td><td>NC</td></tr><tr><td>AI13</td><td>9</td><td>43</td><td>NC</td></tr><tr><td>AI12</td><td>10</td><td>44</td><td>NC</td></tr><tr><td>AI11</td><td>11</td><td>45</td><td>NC</td></tr><tr><td>AI10</td><td>12</td><td>46</td><td>NC</td></tr><tr><td>AI9</td><td>13</td><td>47</td><td>NC</td></tr><tr><td>AI8</td><td>14</td><td>48</td><td>NC</td></tr><tr><td>AI7 / AI7+</td><td>15</td><td>49</td><td>AI7-</td></tr><tr><td>AI6 / AI6+</td><td>16</td><td>50</td><td>AI6-</td></tr><tr><td>AI5 / AI5+</td><td>17</td><td>51</td><td>AI5-</td></tr><tr><td>AI4 / AI4+</td><td>18</td><td>52</td><td>AI4-</td></tr><tr><td>AI3 / AI3+</td><td>19</td><td>53</td><td>AI3-</td></tr><tr><td>AI2 / AI2+</td><td>20</td><td>54</td><td>AI2-</td></tr><tr><td>AI1 / AI1+</td><td>21</td><td>55</td><td>AI1-</td></tr><tr><td>AI0 / AI0+</td><td>22</td><td>56</td><td>AI0-</td></tr><tr><td>AGND</td><td>23</td><td>57</td><td>AGND</td></tr><tr><td>NC</td><td>24</td><td>58</td><td>AGND</td></tr><tr><td>NC</td><td>25</td><td>59</td><td>AGND</td></tr><tr><td>AO1</td><td>26</td><td>60</td><td>AGND</td></tr><tr><td>AO0</td><td>27</td><td>61</td><td>AGND</td></tr><tr><td>AI_AO_Cal+</td><td>28</td><td>62</td><td>AI_AO_Cal-</td></tr><tr><td>AGND</td><td>29</td><td>63</td><td>AGND</td></tr><tr><td>NC</td><td>30</td><td>64</td><td>NC</td></tr><tr><td>DGND</td><td>31</td><td>65</td><td>DGND</td></tr><tr><td>Ext. Time Base</td><td>32</td><td>66</td><td>Ext. CONVT</td></tr><tr><td>AO_Trig +12V or 5V</td><td>33 34</td><td>67 68</td><td>AI_Trig DGND</td></tr></table>

Figure 2-23: PCIe-9161 CN1 Pin Assignments

<table><tr><td>NC</td><td>1</td><td>35</td><td>NC</td></tr><tr><td>NC</td><td>2</td><td>36</td><td>NC</td></tr><tr><td>NC</td><td>3</td><td>37</td><td>NC</td></tr><tr><td>NC</td><td>4</td><td>38</td><td>NC</td></tr><tr><td>AGND</td><td>5</td><td>39</td><td>AGND</td></tr><tr><td>AGND</td><td>6</td><td>40</td><td>AGND</td></tr><tr><td>AI15 / AI15+</td><td>7</td><td>41</td><td>AI16 / AI15-</td></tr><tr><td>AI14 / AI14+</td><td>8</td><td>42</td><td>AI17 / AI14-</td></tr><tr><td>AI13 / AI13+</td><td>9</td><td>43</td><td>AI18 / AI13-</td></tr><tr><td>AI12 / AI12+</td><td>10</td><td>44</td><td>AI19 / AI12-</td></tr><tr><td>AI11 / AI11+</td><td>11</td><td>45</td><td>AI20 / AI11-</td></tr><tr><td>AI10 / AI10+</td><td>12</td><td>46</td><td>AI21 / AI10-</td></tr><tr><td>AI9 / AI9+</td><td>13</td><td>47</td><td>AI22 / AI9-</td></tr><tr><td>AI8 / AI8+</td><td>14</td><td>48</td><td>AI23 / AI8-</td></tr><tr><td>AI7 / AI7+</td><td>15</td><td>49</td><td>AI24 / AI7-</td></tr><tr><td>AI6 / AI6+</td><td>16</td><td>50</td><td>AI25 / AI6-</td></tr><tr><td>AI5 / AI5+</td><td>17</td><td>51</td><td>AI26 / AI5-</td></tr><tr><td>AI4 / AI4+</td><td>18</td><td>52</td><td>AI27 / AI4-</td></tr><tr><td>AI3 / AI3+</td><td>19</td><td>53</td><td>AI28 / AI3-</td></tr><tr><td>AI2 / AI2+</td><td>20</td><td>54</td><td>AI29 / AI2-</td></tr><tr><td>AI1 / AI1+</td><td>21</td><td>55</td><td>AI30 / AI1-</td></tr><tr><td>AI0 / AI0+</td><td>22</td><td>56</td><td>AI31 / AI0-</td></tr><tr><td>AGND</td><td>23</td><td>57</td><td>AGND</td></tr><tr><td>AO3</td><td>24</td><td>58</td><td>AGND</td></tr><tr><td>AO2</td><td>25</td><td>59</td><td>AGND</td></tr><tr><td>AO1</td><td>26</td><td>60</td><td>AGND</td></tr><tr><td>AOO</td><td>27</td><td>61</td><td>AGND</td></tr><tr><td>AI_AO_Cal+</td><td>28</td><td>62</td><td>AI_AO_Cal-</td></tr><tr><td>AGND</td><td>29</td><td>63</td><td>AGND</td></tr><tr><td>NC</td><td>30</td><td>64</td><td>NC</td></tr><tr><td>DGND</td><td>31</td><td>65</td><td>DGND</td></tr><tr><td>Ext. Time Base</td><td>32</td><td>66</td><td>Ext. CONVT</td></tr><tr><td>AO_Trig +12V or 5V</td><td>33 34</td><td>67 68</td><td>AI_Trig DGND</td></tr></table>

Figure 2-24: PCIe-9163/9164 CN1 Pin Assignments

<table><tr><td>NC</td><td>1</td><td>35</td><td>NC</td></tr><tr><td>NC</td><td>2</td><td>36</td><td>NC</td></tr><tr><td>NC</td><td>3</td><td>37</td><td>NC</td></tr><tr><td>NC</td><td>4</td><td>38</td><td>NC</td></tr><tr><td>NC</td><td>5</td><td>39</td><td>NC</td></tr><tr><td>NC</td><td>6</td><td>40</td><td>NC</td></tr><tr><td>NC</td><td>7</td><td>41</td><td>NC</td></tr><tr><td>NC</td><td>8</td><td>42</td><td>NC</td></tr><tr><td>AGND</td><td>9</td><td>43</td><td>AGND</td></tr><tr><td>AGND</td><td>10</td><td>44</td><td>AGND</td></tr><tr><td>AI47 / AI31+</td><td>11</td><td>45</td><td>AI48 / AI31-</td></tr><tr><td>AI46 / AI30+</td><td>12</td><td>46</td><td>AI49 / AI30-</td></tr><tr><td>AI45 / AI29+</td><td>13</td><td>47</td><td>AI50 / AI29-</td></tr><tr><td>AI44 / AI28+</td><td>14</td><td>48</td><td>AI51 / AI28-</td></tr><tr><td>AI43 / AI27+</td><td>15</td><td>49</td><td>AI52 / AI27-</td></tr><tr><td>AI42 / AI26+</td><td>16</td><td>50</td><td>AI53 / AI26-</td></tr><tr><td>AI41 / AI25+</td><td>17</td><td>51</td><td>AI54 / AI25-</td></tr><tr><td>AI40 / AI24+</td><td>18</td><td>52</td><td>AI55 / AI24-</td></tr><tr><td>AI39 / AI23+</td><td>19</td><td>53</td><td>AI56 / AI23-</td></tr><tr><td>AI38 / AI22+</td><td>20</td><td>54</td><td>AI57 / AI22-</td></tr><tr><td>AI37 / AI21+</td><td>21</td><td>55</td><td>AI58 / AI21-</td></tr><tr><td>AI36 / AI20+</td><td>22</td><td>56</td><td>AI59 / AI20-</td></tr><tr><td>AI35 / AI19+</td><td>23</td><td>57</td><td>AI60 / AI19-</td></tr><tr><td>AI34 / AI18+</td><td>24</td><td>58</td><td>AI61 / AI18-</td></tr><tr><td>AI33 / AI17+</td><td>25</td><td>59</td><td>AI62 / AI17-</td></tr><tr><td>AI32 / AI16+</td><td>26</td><td>60</td><td>AI63 / AI16-</td></tr><tr><td>AGND</td><td>27</td><td>61</td><td>AGND</td></tr><tr><td>AGND</td><td>28</td><td>62</td><td>AGND</td></tr><tr><td>NC</td><td>29</td><td>63</td><td>NC</td></tr><tr><td>NC</td><td>30</td><td>64</td><td>NC</td></tr><tr><td>NC</td><td>31</td><td>65</td><td>NC</td></tr><tr><td>NC</td><td>32</td><td>66</td><td>NC</td></tr><tr><td>NC</td><td>33</td><td>67</td><td>NC</td></tr><tr><td>NC</td><td>34</td><td>68</td><td>NC</td></tr></table>

Figure 2-25: PCIe-9164 CN6 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>AI+ &lt;0...31&gt;</td><td>I</td><td>Differential Analog High Input Channels 0-31</td></tr><tr><td>AI- &lt;0...31&gt;</td><td>I</td><td>Differential Analog Low Input Channels 0-31</td></tr><tr><td>AO &lt;0,3&gt;</td><td>O</td><td>Analog Output Channels &lt;0,3&gt;</td></tr><tr><td>AGND</td><td></td><td>Analog Ground</td></tr><tr><td>Ext. Time Base</td><td>I</td><td>External Time Base Clock Signal Input</td></tr><tr><td>Ext. CONVSN</td><td>I</td><td>External Conversion Clock Signal Input</td></tr><tr><td>AI Trigger In</td><td>I</td><td>External Analog Input Trigger Signal Input</td></tr><tr><td>AO Trigger In</td><td>I</td><td>External Analog Output Trigger Signal Input</td></tr><tr><td>DGND</td><td></td><td>Digital Ground</td></tr><tr><td>+12V</td><td>O</td><td>12V power output @ 0.2A</td></tr><tr><td>5V</td><td>O</td><td>5V power output @ 0.2A</td></tr><tr><td>NC</td><td></td><td>No connect</td></tr><tr><td>NA</td><td></td><td>No function</td></tr><tr><td>AI_AO_Cal</td><td>I</td><td>Calibration Voltage Input, only factory used.</td></tr></table>

Table 2-10: PCIe-9161/9163/9164 CN1/CN6 Pin Assignment Legend

# 2.4.3.2 PCIe-9161/9163/9164 CN7/CN8 Connector

CN7/CN8 are 20-pin insulation displacement connectors with the following pin assignments.

![DO0 / GPTC COUT0 1 2\nDO2 / GPTC COUT2 3 4\nDO4 5 6\nDO6 7 8\nDO8 9 10\nDO10 11 12\nDO12 13 14\nDO14 15 16\nDO_Trig 17 18\nDI_Trig 19 20\nDO1 / GPTC COUT1\nDO3 / GPTC COUT3\nDO5\nDO7\nDO9\nDO11\nDO13\nDO15\nDGND\nDO_SYNC_OUT](.pcie-9100-50m-18094-1030-17/42214b545a24cffadcdc526df782c1b6af5a6d14e29d178830a0c220d095a32a.jpg)

Figure 2-26: PCIe-9161/9163/9164 CN7 Pin Assignments

![DI0 / GPTC GATE0 / EA0+ 1 2\nDI2 / GPTC GATE2 / EB1+ 3 4\nDI4 / GPTC CLK0 / EZ0+ 5 6\nDI6 / GPTC CLK2 / EA1+ 7 8\nDI8 / EB1+ 9 10\nDI10 / EZ1+ 11 12\nDI12 13 14\nDI14 15 16\nGND 17 18\n+5V 19 20\nDI1 / GPTC GATE1 / EA0-\nDI3 / GPTC GATE3 / EB1-\nDI5 / GPTC CLK1 / EZ0-\nDI7 / GPTC CLK3 / EA1-\nDI9 / EB1-\nDI11 / EZ1-\nDI13\nDI15\nDGND\nDI_SYNC_IN](.pcie-9100-50m-18094-1030-17/4aaeafc15f5f1aa77480ce79cdc1f20f0bfac36ec2fc61ef413fd71c55e7a751.jpg)

Figure 2-27: PCIe-9161/9163/9164 CN8 Pin Assignments

<table><tr><td>Signal Name</td><td>I/O</td><td>Description</td></tr><tr><td>AGND</td><td></td><td>Analog Ground</td></tr><tr><td>DI &lt;0...15&gt;</td><td>I</td><td>Digital Input Channels 0-15</td></tr><tr><td>DI Sync In</td><td>I</td><td>Digital Input Synchronization Clock Source In</td></tr><tr><td>DO &lt;0...15&gt;</td><td>O</td><td>Digital Output Channels 0-15</td></tr><tr><td>DO Sync Out</td><td></td><td>Digital Output Synchronization Clock Source Out</td></tr><tr><td>GPTC CLK &lt;0,3&gt;</td><td></td><td>Source Clock Input of GPTC &lt;0,3&gt;</td></tr><tr><td>GPTC Gate &lt;0,3&gt;</td><td></td><td>Gate Input of GPTC &lt;0,3&gt;</td></tr><tr><td>GPTC COUT &lt;0,3&gt;</td><td></td><td>Output of GPTC &lt;0,3&gt;</td></tr><tr><td>EA &lt;0,1&gt;</td><td></td><td>Encoder A Phase</td></tr><tr><td>EB &lt;0,1&gt;</td><td></td><td>Encoder B Phase</td></tr><tr><td>EZ &lt;0,1&gt;</td><td></td><td>Encoder Z Phase</td></tr><tr><td>DGND</td><td></td><td>Digital Ground</td></tr><tr><td>5V</td><td>O</td><td>5V power output @ 0.2A</td></tr><tr><td>NC</td><td></td><td>No connect</td></tr><tr><td>NA</td><td></td><td>No function</td></tr></table>

Table 2-11: PCIe-9161/9163/9164 CN7/CN8 Pin Assignment Legend

# 2.5 Hardware Installation Outline

# 2.5.1 PCI Express Configuration

PCI Express cards are equipped with a plug and play PCI Express controller that can request base addresses and interrupts according to the PCI Express standard. The system BIOS will configure resources based on the PCI Express cards’ configuration registers and system parameters (set in the BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI Express cards can be assigned by the system BIOS only. These system resource assignments are done on a board-by-board basis. It is not suggested to assign the system resource by any other method.

# 2.5.2 PCI Express Slot Selection

A PCIe-9100 Series card can be inserted into any PCI Express slot without the need to configure system resources.

# 2.5.3 Installation Procedures

1. Turn off your computer.
2. Turn off all peripherals connected to your computer (printer, monitor, etc.).
3. Remove the cover from your computer.
4. Setup jumpers and switchs on the PCIe-9100 Series card.
5. Before handling PCI Express cards, discharge any static buildup on your body by touching the metal case of the computer. Hold the edge and do not touch the components.
6. Position the board into the PCI Express slot you have selected.
7. Secure the card in place at the rear panel of the system.

# 2.6 Device Installation for Windows Systems

Once Windows 7/10/11 or later has started, the Plug and Play function of Windows system will find the new NuDAQ cards. If this is the first time the NuDAQ cards are running on your Windows system, you will be prompted to input the device information source. Please refer to the Software Installation Guide for stepby-step installation procedures.

# 3 Operation Theory

This chapter describes the operation theory of the PCIe-9100 Series card functions. The functions include A/D conversion, D/A conversion, Digital I/O and counter/timer usage. The operation theory can help you to understand how to configure or to program the PCIe-9100 Series cards.

# 3.1 A/D Conversion

Before programming the PCIe-9100 Series card to perform any A/ D conversions, you should have an understanding of the following:

 A/D front-end signal input connection
 A/D conversion procedure
 A/D trigger mode
 A/D data transfer mode
 Signal Connection
 AI data format

# 3.2 Analog Input Signal Connection

The PCIe-9100 Series provides single-ended or differential analog input channels. The analog signals can be converted to digital values by the A/D converter. To avoid ground loops and to obtain more accurate measurements, it is important to understand the signal source type and how to choose the analog input modes, either signal-ended or differential. The mode can be selected by software settings.

# Single-ended Mode

The single-ended mode has only one input relative to ground and is suitable for connecting with a floating signal source. A floating source is one that does not have any connection to ground. Figure 3-1 shows the single-ended connection. Note that when more than two floating sources are available, the sources must have a common ground.

![Based on the provided image, here is the description of the flowchart/block diagram:\n\n**Labeled Blocks and Text:**\n*   **Floating Signal Source**: Located on the far left.\n*   **Aln**: Label at the top of a vertical bar with dots.\n*   **AGND**: Label at the bottom of the vertical bar.\n*   **n = 0, ..., 15**: Text located below the vertical bar.\n*   **Input Multiplexer**: Label inside a rectangular block (split as 'Input' and 'Multiplexer').\n*   **Operational Amplifier**: Label above a triangle symbol.\n*   **To A/D Converter**: Text at the far right end of the output arrow.\n\n**Connections:**\n1.  Two AC source symbols (circles with sine waves) are connected to the label 'Floating Signal Source'.\n2.  Lines from these sources connect to a vertical bar containing a column of dots. The top dot is labeled 'Aln' and the bottom dot is labeled 'AGND'.\n3.  This vertical input structure connects to the left side of the 'Input Multiplexer' block.\n4.  A line exits the right side of the 'Input Multiplexer' and connects to the base of the triangle labeled 'Operational Amplifier'.\n5.  An arrow exits the point of the triangle, pointing to the right towards the text 'To A/D Converter'.](.pcie-9100-50m-18094-1030-17/c684dd971a3c5da11a7583924c5327bf78f9af0394445a2bfbf68f59bfbf8c94.jpg)

Figure 3-1: Floating source and single-ended

# Differential Input Mode

The differential input mode provides two inputs that respond to differences in signals. If the signal source has one side connected to local ground, the differential mode can be used to reduce the effect of ground loops. Figure 3-2 shows the connection for differential input mode. However, if the signal source is locally grounded, the single-ended mode can be used when the Vcm (Common Mode Voltage) is very small and the effect of ground loops is minimal.

![n = 0, ..., 7\nGround\nSignal\nSource\nAlHn\nAlLn\nGND\nTo A/D\nConverter\nVcm = VG1 - VG2\nVG1\nVG2](.pcie-9100-50m-18094-1030-17/96ad5c44ef4ba779fd5976068fd31487970f2f845343d5b8cc740ef129b162dc.jpg)

Figure 3-2: Ground source and differential input

A differential mode must be used when the signal source is differential. A differential source means that the ends of the signal are not grounded. To avoid the danger of high voltages between the local ground of the signal and the ground of the PC system, a shorted ground path must be connected. Figure 3-3 shows the connection for a differential source.

![n = 0, ..., 7\nDifferential\nSignal\nSource\nAIHn\nAlLn\nTo A/D\nConverter\nGND\nVcm = VG1 - VG2\nVG1\nVG2](.pcie-9100-50m-18094-1030-17/1cc969ca71f6b231a004fde31e3d1a95946d954ef6611bb41ce9e54b1c720814.jpg)

Figure 3-3: Differential source and differential input

If the signal source are both floating, you should use the differential mode, and the floating signal source should be connected as in Figure 3-4.

![Based on the provided image, here is an accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n*   **Floating Signal Source:** Represented by a circle containing a sine wave symbol.\n*   **Vertical Connection Bar:** A vertical rectangular bar with three connection points.\n*   **Amplifier:** Represented by a triangle symbol.\n*   **Ground:** Represented by a standard ground symbol.\n\n**Text Labels:**\n*   'n = 0, ..., 7' (located at the top)\n*   'Floating Signal Source' (to the left of the source)\n*   'AIHn' (to the left of the top connection point)\n*   'High' (to the right of the top connection point)\n*   'AILn' (to the left of the middle connection point)\n*   'Low' (to the right of the middle connection point)\n*   'GND' (to the right of the bottom connection point)\n*   'To A/D Converter' (to the right of the amplifier output)\n\n**Connections:**\n1.  **Source to Vertical Bar:**\n    *   The top wire from the **Floating Signal Source** connects to the top connection point on the vertical bar (labeled 'AIHn' and 'High').\n    *   The bottom wire from the **Floating Signal Source** connects to a junction that splits: one path goes right to the middle connection point (labeled 'AILn' and 'Low'), and another path goes down to the bottom connection point (labeled 'GND').\n2.  **Vertical Bar to Ground:**\n    *   The bottom connection point labeled 'GND' is connected to the ground symbol.\n3.  **Vertical Bar to Amplifier:**\n    *   The connection point labeled 'High' connects to the top input of the triangle (amplifier).\n    *   The connection point labeled 'Low' connects to the bottom input of the triangle.\n4.  **Amplifier Output:**\n    *   The output of the triangle connects to the text 'To A/D Converter'.](.pcie-9100-50m-18094-1030-17/ceefe046ad21a2ab56051266d1b12828932bfbb1291a08acfb90459b833babec.jpg)

Figure 3-4: Floating source and differential input

# 3.2.1 A/D Conversion Procedure

A/D conversion starts when a trigger is set by the trigger source. The PCIe-9100 Series provides three trigger modes. See section 3.2.2.

The A/D data should now be transferred into the PC's memory for further processing. The PCIe-9100 Series provides three data transfer modes that allow users to optimize the DAQ system. See section for data transfer modes.

# 3.2.2 A/D Trigger Sources

A/D conversion can be triggered by an Internal or External trigger source. Whenever an external source is set, the internal sources are disabled.

Totally there are three trigger sources available to the PCIe-9100 Series. The different trigger conditions are specified below.

# Software Trigger

This trigger source is software controllable. That is, the A/D conversion starts when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversions. Under this mode, the timing of the A/D conversion is fully controlled by the software. However, it is difficult to control a fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger.

# External Digital Trigger

Through Pin ExtTrig, an external digital trigger is generated when a TTL rising edge or falling edge is detected. The trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 50 ns.

# Analog Trigger

From any channel selected as an analog trigger source for A/D conversion, FPGA could generate a trigger signal when the analog trigger condition is satisfied. The PCIe-9100 Series uses two threshold voltages, Low\_Threshold and High\_Threshold, to build five different trigger conditions that are software configurable.

# Below-Low analog trigger condition

Figure 3-5 shows the below-low analog trigger condition. The trigger signal is generated when the input analog signal is less than the Low\_Threshold voltage. The High\_Threshold setting is not used in this trigger condition.

![Low Threshold\nTrigger](.pcie-9100-50m-18094-1030-17/68363bfc92ced4d57e664a659364e590b57ec9e44343a14349410ad62426c7b3.jpg)

Figure 3-5: Below-Low analog trigger condition

# Above-High analog trigger condition

Figure 3-6 shows the above-high analog trigger condition. The trigger signal is generated when the input analog signal is higher than the High\_Threshold voltage. The Low\_Threshold setting is not used in this trigger condition.

![High_Threshold\nTrigger](.pcie-9100-50m-18094-1030-17/0c07a1d0f21fa0c6b58c375fe0e6deb783747bde1844277e00a5629194052356.jpg)

Figure 3-6: Above-High analog trigger condition

# Inside-Region analog trigger condition

Figure 3-7 shows the inside-region analog trigger condition. The trigger signal is generated when the input analog signal level falls in the range between the High\_Threshold and the Low\_Threshold voltages.

![The image displays a white document icon with horizontal lines representing text, overlaid with a large red checkmark.](.pcie-9100-50m-18094-1030-17/29d6f5dc5a4d8489ec9d8e0428c2fa218eead7a04a328af6d1d6587ac34f79bc.jpg)
NOTE:

The High\_Threshold setting should be always higher than the Low\_Threshold voltage setting.

![High_Threshold\nLow_Threshold\nTrigger](.pcie-9100-50m-18094-1030-17/565d21f001d3f419cb5c77ad9e62cf02f9ff6f9a043e5fa8d59c9253f2946191.jpg)

Figure 3-7: Inside-Region analog trigger condition

# High-Hysteresis analog trigger condition

Figure 3-8 shows the high-hysteresis analog trigger condition. The input analog signal level should be greater than the Low\_Threshold voltage at first, and then the trigger signal will be generated when the input analog signal level is greater than High\_Threshold voltage to determine the hysteresis duration.

![The image displays a simple icon of a white piece of paper with faint horizontal grey lines and a folded top-right corner. A large, bold red checkmark is superimposed over the center of the document.](.pcie-9100-50m-18094-1030-17/1a37d0f31ebf837c5684f4d1d6721877cbe98d3d5eca8ec73026712ec5078776.jpg)
NOTE:

The High\_Threshold setting should be always higher than the Low\_Threshold voltage setting.

![| Trigger | Low_Threshold | High_Threshold |\n| ------- | ------------ | -------------- |\n| 0       | Low          | Low            |\n| Peak    | High         | High           |\n| Trigger | Low          | High           |](.pcie-9100-50m-18094-1030-17/b56fdd486914b8feb0c6c6606e5a06697c524dfc0dc56d65c4bc9fe8fd6bff10.jpg)

Figure 3-8: High-Hysteresis analog trigger condition

# Low-Hysteresis analog trigger condition

Figure 3-9 shows the low-hysteresis analog trigger condition. The input analog signal level should be lower than the High\_Threshold voltage at first, and then the trigger signal will be generated when the input analog signal level is lower than Low\_Threshold voltage to determine the hysteresis duration.

![The image displays a white document icon with a folded top-right corner and horizontal lines, featuring a large red checkmark superimposed on it.](.pcie-9100-50m-18094-1030-17/2ff7e09c2634be9c45cac8f3f224542592e403e84fba0efbe79533c471c1d142.jpg)
NOTE:

The High\_Threshold setting should be always higher than the Low\_Threshold voltage setting.

![| Trigger | High_Threshold | Low_Threshold |\n| ------- | ------------- | ------------ |\n| Start   | Low           | High         |\n| End     | High          | Low          |](.pcie-9100-50m-18094-1030-17/336893a833b23e4a1bf9d1c257cfcf315b02bbf7c4c898acfaae5d8ba016b204.jpg)

Figure 3-9: Low-Hysteresis analog trigger condition

# 3.2.3 A/D Trigger Modes

There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger, delay-trigger, post-trigger with re-trigger and delay-trigger with re-trigger) working with the 3 trigger sources to initiate different scan data acquisition timing when a trigger event occurs.

# Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to collect data before a trigger event. The A/D starts to sample when you execute the specified function calls to begin the pretrigger operation, and stops when the trigger event occurs. Users must program the value M in M\_counter to specify the amount of the stored scans before the trigger event. If an external trigger occurs, the program only stores the last M scans of data converted before the trigger event, as illustrated in Figure 3-10, where M\_counter = M =3, PSC\_counter = 0. The post scan count is 0 because there is no sampling after the trigger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels \* M\_counter.

$$
(M \_ c o u n t e r = M = 3, \text { NumChan\_counter } = 4, \text { PSC\_counter } = 0)
$$

![Trigger\nScan_start\nAD_conversion\nAcquisition_in_progress\nAquired data\nAcquired & stored data\n(M scans)](.pcie-9100-50m-18094-1030-17/547e22adada14eca668082da8caa4ea467ae393e2c6f89e7a50ad021743af62c.jpg)

Figure 3-10: Pre-trigger (trigger occurs after at least M scans acquired)

If a trigger event occurs when a scan is in progress, the data acquisition will not stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan\_counter), no matter when a trigger signal occurs, as illustrated in Figure 3-11, where

M\_counter = M = 3, NumChan\_counter = 4, PSC\_counter = 0.

![(M_counter = M = 3, NumChan_counter =4, PSC_counter=0)\nTrigger\nScan_start\nAcquisition_in_progress\nTrigger occurs\nAquired data\nAcquired & stored data\n(M scans)](.pcie-9100-50m-18094-1030-17/f86edbbe0a76ad2789e5dc48b17c54335dc6921a003fef7ac379e69dda7b3def.jpg)

Figure 3-11: Pre-trigger (Trigger with scan in progress)

When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the originally specified amount in M\_counter, as illustrated in Figure 3-12. This situation can be avoided by setting M\_enable. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 3-13. However, if M\_enable is set to 0, the trigger signal will be accepted any time, as shown in Figure 3- 12. Note that the total amount of stored data will always be equal to the number in the M\_counter because data acquisition does not stop until a scan is completed.

(M\_Counter = M = 3, NumChan\_Counter=4, PSC\_Counter=0)

![This timing diagram displays four signal lines labeled on the left:\n\n1.  **Trigger**\n2.  **Scan_start**\n3.  **AD_conversion**\n4.  **Acquisition_in_progress**\n\nThe diagram illustrates the following temporal relationships:\n*   The **Scan_start** signal has two pulses. The first pulse aligns with the rising edge of the **Acquisition_in_progress** signal.\n*   The **AD_conversion** signal displays two bursts of pulses, occurring during the high state of **Acquisition_in_progress**.\n*   The **Acquisition_in_progress** signal goes high and remains high until the second burst of **AD_conversion** completes.\n\nAt the bottom, a double-headed arrow spans the duration of the **Acquisition_in_progress** signal. The text below reads:\n**Acquired & stored data (2 scans)**](.pcie-9100-50m-18094-1030-17/1edd9e572d1af58aa465c21e4faaf3770fd2daed3b96305a59cca81043e49b51.jpg)

Figure 3-12: Pre-trigger with M\_enable=0 (Trigger occurs before M scans)

(M\_counter = M = 3, NumChan\_counter=4, PSC\_counter=0)

![This diagram is a timing chart illustrating signal relationships. The labeled blocks (signal tracks) on the left are:\n\n*   **Trigger**\n*   **Scan_start**\n*   **AD_conversion**\n*   **Acquisition_in_progress**\n\nThe connections and annotations between these signals are:\n\n*   A bracket at the top labeled **The first M scans**.\n*   Text pointing to a hatched region on the Trigger line: **Trigger signals which occur in the shadow region(the first M scans) will be ignored**.\n*   A bracket at the bottom labeled **Aquired data**.\n*   A bracket at the bottom labeled **Acquired & stored data (M scans)**.](.pcie-9100-50m-18094-1030-17/1c3864014b2c4f05a290279efb47a794e5d4d0994ae18adb9f5b6472150d6058.jpg)

[Max. value of M\_counter is 65536]

Figure 3-13: Pre-trigger with M\_enable=1

# Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M\_counter, while the number of scans (N) after the trigger is specified in PSC\_counter. Like pre-trigger mode, the number of stored data could be less than the specified amount of data (M+N), if an external trigger occurs before M scans of data are converted. The M\_enable bit in middle-trigger mode takes the same effect as in pre-trigger mode. If M\_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user with (M+N) scans of data under middle-trigger mode. However, if M\_enable is set to 0, the trigger signal will be accepted at any time. Figure 3-14 shows the acquisition timing with M\_enable=1.

![Based on the provided image, here is an accurate and concise description of the timing diagram:\n\n**Header:**\n*   `(M_Counter=M=3, PSC_Counter=N=1)`\n\n**Signal Labels (Left Axis):**\n*   `Trigger`\n*   `Scan_start`\n*   `ADCONV`\n*   `Acquisition_in_progress`\n*   `Post Scan Count`\n\n**Annotations and Connections:**\n*   **Top Annotation:** An arrow labeled 'The first M scans' points to a hatched shaded region on the `Trigger` line. A separate text annotation points to this region stating: 'Trigger signals which occur in the shadow region (the first M scans) will be ignored'.\n*   **Bottom Timeline Annotations:**\n    *   `Operation start` marks the beginning.\n    *   `Acquired data` spans the entire active duration.\n    *   `M scans before trigger` spans the period from the start to the trigger event.\n    *   `N scans after trigger` spans the period immediately following the trigger event.\n    *   `Acquired & stored data (M+N scans)` spans the total duration combining the previous two sections.\n*   **Values:** The label `Post Scan Count` shows the value `1` at the start and `0` at the end of the sequence.\n*   **Vertical Alignment:** Vertical dashed lines connect events across the signals, marking the start of `Acquisition_in_progress`, the trigger pulse alignment on `Scan_start`/`ADCONV`/`Trigger`, and the end of the sequence where `Acquisition_in_progress` drops and `Post Scan Count` becomes `0`.](.pcie-9100-50m-18094-1030-17/c233eaf2e1c3d2941c68fa7a4f02cc0e9e875509a4116ff8b74fed5ca1918c8b.jpg)

Figure 3-14: Middle trigger with M\_enable = 1

If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 3-15.

![(M Counter=M=2, PSC Counter=N=2)\nTrigger occurs when a scan is in progress\nTrigger\nScan_s tari\nAD CO N V\nAcquisition_In_progress\nPost Scan Count 2\n1 0\nAcquired data\nM scans before\ntrigger\nN scans at and\nafter trigger\nOperation start\nAcquired & stored data\n(M+N scans)](.pcie-9100-50m-18094-1030-17/2026908bac10fe56e3b4b414a94b789916ad89a3dcbcb83456c74a5af5bbe7b3.jpg)

Figure 3-15: Middle trigger (trigger occurs when a scan is in progress)

![The image displays a white document icon with a folded top-right corner and faint horizontal lines. A large, red checkmark is superimposed over the document.](.pcie-9100-50m-18094-1030-17/4a387b37bda2c67597d5a91e80c5061ffde1feec9c775718b8458699f9168d96.jpg)
NOTE:

M\_counter defined in Middle-Trigger is different from that of Pre-Trigger. In Middle-trigger, M\_Counter ends counting before the trigger event while in Pre-Trigger, M\_Counter ends counting right at or before a trigger event. Refer to Figure 3-14 and Figure 3-15.

# Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC\_counter, as illustrated in Figure 3- 16. The total acquired data length = number of enable-channel \* PSC\_counter.

![(PSC_Counter=3)\nTrigger\nScan_start\nADCO NV\nAcquisitb_in_progress\nPost Scan Corr1 3\nOperation start\n2 | 1 0\nAcquired & stored data\n(8 scans)](.pcie-9100-50m-18094-1030-17/eb2dd6088239fd4769492489be5eb3931fdd2f6b9aedc08b1c47d0c21c3c4c9d.jpg)

Figure 3-16: Post trigger

# Delay-Trigger Acquisition

Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time/samples are controlled by the value, which is pre-loaded in the Delay\_counter (16-bit). The counter counts down on the rising edge of the Delay\_counter clock source after the trigger condition is met. The clock source can be software programmed either by the TIMEBASE clock (64MHz) or A/D sampling clock (TIMEBASE / SI\_counter). When the count reaches 0, the counter stops and the card starts to acquire data. The total acquired data length = number of enable-channel \* PSC\_counter.

![(PSC_Counter=3\nTrigger\nScan_start\nADCO NV\nAcquisition_in_progress\nPost Scan Count 3\n2 1 0\nDelay until\nDelay_ Counter\nreaches 0 Acquired & stored data\n(3 scans)\nOperation start](.pcie-9100-50m-18094-1030-17/95fc03c63789bfc042a998c3c50caba961f78f4d171f491e2141246e21e52195.jpg)

Figure 3-17: Delay trigger

![The image displays a white document icon with a folded top-left corner and faint horizontal grey lines. A large, bold red checkmark is superimposed over the center of the document. The entire icon is framed by a thin black border.](.pcie-9100-50m-18094-1030-17/64c949e29f8c56be71c1c7e2cf875b1ac970d31eedc53a9e51455cd3cb13f018.jpg)
NOTE:

When the Delay\_counter clock source is set to TIMEBASE, the maximum delay time = 2^32/64M s = 67Sec, and when the source is set to A/D sampling clock, the maximum delay time can be as high as (2^32 \* SI\_counter / 64M ).

# Post-Trigger or Delay-Trigger Acquisition with Re-trigger

Use post-trigger or delay-trigger acquisition with the re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC\_counter, and users can program Retrig\_no to specify the number of re-triggers. Figure 3-18 illustrates 2 scans of data acquired after the first trigger signal, then the card waits for the re-trigger signal. Re-trigger signals which occur before the first 2 scans are completed will be ignored. When the re-trigger signal occurs, 2 more scan are performed. The process repeats until the specified amount of re-trigger signals are detected. The total acquired data length = number of enable-channel \* PSC\_counter \* Retrig\_no.

![(PSC_Counter=2, retrig_no=3)\nTrigger\nScan_start\nADCONV\nAcquisition_in_progress\nPost Scan Count 2 1 0 2 1 0 2 1 0 .\nOperation start\nAcquired & stored data\n(5 scans)](.pcie-9100-50m-18094-1030-17/63518e2de2c6cb8e7d82bfa436d09946aba8b2bc2c3a80633a221eaf0509e888.jpg)

Figure 3-18: Post trigger with re-trigger

# 3.2.4 A/D Data Transfer Modes

Any of the two A/D data transfer modes can be used when a conversion is completed. The Data Transfer Mode is controlled by the A/D mode control bits of the A/D control register. The different transfer modes are specified below.

# Software Data Transfer

Usually, this mode is used with software A/D trigger mode. The conversion starts when it receives a software trigger, the software then polls the DRDY bit on the A/D Status register until it becomes high. When it is low, the A/D data is read, and the DRDY bit will be cleared to indicate the data transfer is completed.

It is possible to read A/D converted data without polling. The A/ D conversion time takes no more then 1μs on the PCIe-9100 Series card. Hence, after a software trigger, the software can wait for at least 1μs then read the A/D register without polling.

# DMA Transfer

The DMA (Direct Memory Access) bus master allows data to be transferred directly between the PCIe-9100 Series and the PC’s memory at the fastest possible rate, without using up any CPU time. The A/D data is queued in the local FIFO on the PCIe-9100 Series itself and it is automatically transferred to PC's memory.

The DMA transfer mode is very complex to program. It is recommended to use high-level programming libraries to operate this card. If you wish to program software to handle the DMA bus master data transfer, refer to the PCI Express controller manual for more details.

# 3.2.5 AI Data Format

The data format of the acquired 16- and 14-bit A/D data is 2’s complement coding. Table 3-1 and Table 3-2 show the valid input ranges and the ideal transfer characteristics.

<table><tr><td>Description</td><td colspan="6">Bipolar Analog Input Range</td><td>Digital Code (16-bit)</td></tr><tr><td>Full-scale Range</td><td>±10V</td><td>±5V</td><td>±2.5V</td><td>±1.25V</td><td>±0.625V</td><td>±0.3125V</td><td></td></tr><tr><td>Least significant bit</td><td>305.2uV</td><td>152.6uV</td><td>76.3uV</td><td>38.14uV</td><td>19.07uV</td><td>9.54uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>9.999695V</td><td>4.999847V</td><td>2.499924V</td><td>1.249961V</td><td>0.624981V</td><td>0.31249V</td><td>7FFF</td></tr><tr><td>Midscale +1LSB</td><td>305.2uV</td><td>152.6uV</td><td>76.3uV</td><td>38.14uV</td><td>19.07uV</td><td>9.54uV</td><td>0001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0000</td></tr><tr><td>Midscale - 1LSB</td><td>-305.2uV</td><td>-152.6uV</td><td>-76.3uV</td><td>-38.14uV</td><td>-19.07uV</td><td>-9.54uV</td><td>FFFF</td></tr><tr><td>-FSR</td><td>-10V</td><td>-5V</td><td>-2.5V</td><td>-1.25V</td><td>-0.625V</td><td>-0.3125V</td><td>8000</td></tr></table>

Table 3-1: Bipolar Analog Input Range and Output Digital Code (16-bit)

<table><tr><td>Description</td><td colspan="6">Bipolar Analog Input Range</td><td>Digital Code (14-bit)</td></tr><tr><td>Full-scale Range</td><td>±10</td><td>±5</td><td>±2.5</td><td>±1.25</td><td>±0.625</td><td>±0.3125</td><td></td></tr><tr><td>Least significant bit</td><td>1220.7uV</td><td>610.4uV</td><td>305.2uV</td><td>152.6uV</td><td>76.3uV</td><td>38.1uV</td><td></td></tr><tr><td>FSR-1LSB</td><td>9.9987793V</td><td>4.9993896V</td><td>2.4996948V</td><td>1.2498474V</td><td>0.6249237V</td><td>0.3124619V</td><td>1FFF</td></tr><tr><td>MID+1LSB</td><td>1220.7uV</td><td>610.4uV</td><td>305.2uV</td><td>152.6uV</td><td>76.3uV</td><td>38.1uV</td><td>0001</td></tr><tr><td>MID</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0V</td><td>0000</td></tr><tr><td>MID-1LSB</td><td>-1220.7uV</td><td>-610.4uV</td><td>-305.2uV</td><td>-152.6uV</td><td>-76.3uV</td><td>-38.1uV</td><td>3FFF</td></tr><tr><td>-FSR</td><td>-10V</td><td>-5V</td><td>-2.5V</td><td>-1.25V</td><td>-0.625V</td><td>-0.3125V</td><td>2000</td></tr></table>

Table 3-2: Bipolar Analog Input Range and Output Digital Code (14-bit)

# 3.3 D/A Conversion

For complex applications, the PCIe-9100 Series offer software polling to update the output, and DMA data transfer to generate waveforms. This means that the D/A update rate is not only controlled by software timing, but can also be set by a precision hardware timer that is user specified. The following sections discuss the PCIe-9100 Series D/A architecture and control methods.

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>20</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>9</td><td>27</td><td></td></tr><tr><td></td><td>10</td><td>28</td><td></td></tr><tr><td>AGND</td><td>11</td><td>29</td><td>AGND</td></tr><tr><td></td><td>12</td><td>30</td><td>AO1</td></tr><tr><td></td><td>13</td><td>31</td><td></td></tr><tr><td></td><td>14</td><td>32</td><td>AO2</td></tr><tr><td>DGND</td><td>15</td><td>33</td><td></td></tr><tr><td></td><td>16</td><td>34</td><td></td></tr><tr><td>Ext Trg</td><td>17</td><td>35</td><td></td></tr><tr><td></td><td>18</td><td>36</td><td></td></tr><tr><td></td><td>19</td><td>37</td><td>Ext CLK</td></tr></table>

Table 3-3: PCIe-9101/9121/9141 Analog Output Mode on CN3 Pin Assignments

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>12</td><td>46</td><td></td></tr><tr><td>AO1</td><td>13</td><td>47</td><td>AGND</td></tr><tr><td>AO0</td><td>14</td><td>48</td><td>AGND</td></tr><tr><td></td><td>15</td><td>49</td><td></td></tr><tr><td>Ext. Time Base</td><td>16</td><td>50</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>19</td><td>53</td><td></td></tr><tr><td></td><td>20</td><td>54</td><td>AO Trigger In</td></tr><tr><td></td><td>21</td><td>55</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>DGND</td><td>34</td><td>68</td><td></td></tr></table>

Table 3-4: PCIe-9146/9147 Analog Output Mode on CN1 Pin Assignments

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>22</td><td>56</td><td></td></tr><tr><td>AGND</td><td>23</td><td>57</td><td>AGND</td></tr><tr><td></td><td>24</td><td>58</td><td></td></tr><tr><td></td><td>25</td><td>59</td><td></td></tr><tr><td>AO1</td><td>26</td><td>60</td><td></td></tr><tr><td>AO0</td><td>27</td><td>61</td><td></td></tr><tr><td></td><td>28</td><td>62</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>DGND</td><td>31</td><td>65</td><td>DGND</td></tr><tr><td></td><td>32</td><td>66</td><td></td></tr><tr><td>AO Trigger</td><td>33</td><td>67</td><td></td></tr><tr><td></td><td>34</td><td>68</td><td></td></tr></table>

Table 3-5: PCIe-9161 Analog Output Mode on CN1 Pin Assignments

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>22</td><td>56</td><td></td></tr><tr><td>AGND</td><td>23</td><td>57</td><td>AGND</td></tr><tr><td>AO3</td><td>24</td><td>58</td><td></td></tr><tr><td>AO2</td><td>25</td><td>59</td><td></td></tr><tr><td>AO1</td><td>26</td><td>60</td><td></td></tr><tr><td>AO0</td><td>27</td><td>61</td><td></td></tr><tr><td></td><td>28</td><td>62</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>DGND</td><td>31</td><td>65</td><td>DGND</td></tr><tr><td></td><td>32</td><td>66</td><td></td></tr><tr><td>AO Trigger</td><td>33</td><td>67</td><td></td></tr><tr><td></td><td>34</td><td>68</td><td></td></tr></table>

Table 3-6: PCIe-9163/9164 Analog Output Mode on CN1 Pin Assignments

# 3.3.1 Bipolar Output Modes

The PCIe-9100 Series series supports a maximum ±10 V voltage output. Table 3-7 illustrates the relationship of straight binary coding between the digital codes and output voltages.

<table><tr><td>Digital Code</td><td>Analog Output</td></tr><tr><td>0x7FFF</td><td>9.9997V</td></tr><tr><td>0x4000</td><td>5V</td></tr><tr><td>0x0000</td><td>0V</td></tr><tr><td>0xC000</td><td>-5V</td></tr><tr><td>0x8000</td><td>-10V</td></tr></table>

Table 3-7: Bipolar Output Codes

# 3.3.2 Software Update

This method is suitable for applications that need to generate D/A output controlled by user programs. In this mode, the D/A converter generates one output once the software command is issued. However, it is difficult to determine the software update rate under a multitasking OS such as Windows.

# 3.3.3 Waveform Generation

# Waveform Generation Data Structure

FIFO is a hardware first-in first-out data queue that holds temporary digital codes for D/A conversion. When a PCIe-9100 Series operates in waveform generation mode, the waveform patterns are stored in FIFO with 1024 samples (shared).

Waveform patterns larger than 1024 samples are also supported using bus-mastering DMA transfer via the PCIe controller. Data format in FIFO is shown in Figure 3-19.

![This flowchart depicts a 'Samples Data FIFO' block, which functions as a buffer.\n\n**Top Section:**\n*   A large rectangular container labeled **'Samples Data FIFO'**.\n*   An arrow on the right side points inward labeled **'Data In'**.\n*   An arrow on the left side points outward labeled **'Data Out'**.\n*   Inside the container, text reads **'16 Bit Hex Data Format'**.\n*   Below this text is a row of green data blocks containing hex values: **'FFFF'**, **'0000'**, **'0100'**, **'FFFE'**, **'0001'**, **'0101'**, **'......'**, **'FF00'**, **'00FF'**, **'01FF'**.\n\n**Bottom Section:**\n*   Below the FIFO block is a row of green blocks labeled on the left as **'Destination Channel'**.\n*   These blocks contain channel identifiers: **'CH0'**, **'CH1'**, **'CH3'**, **'CH0'**, **'CH1'**, **'CH3'**, **'......'**, **'CH0'**, **'CH1'**, **'CH3'**.\n\n**Connections:**\n*   Vertical arrows point downward from each data block in the top row to the corresponding channel block directly below it in the bottom row.\n*   Specifically, the arrows map the data sequence to the channels in a repeating pattern:\n    *   **'FFFF'** points to **'CH0'**\n    *   **'0000'** points to **'CH1'**\n    *   **'0100'** points to **'CH3'**\n    *   **'FFFE'** points to **'CH0'**\n    *   **'0001'** points to **'CH1'**\n    *   **'0101'** points to **'CH3'**\n    *   (The ellipsis indicates this pattern continues)\n    *   **'FF00'** points to **'CH0'**\n    *   **'00FF'** points to **'CH1'**\n    *   **'01FF'** points to **'CH3'**](.pcie-9100-50m-18094-1030-17/221f6aae8cec63582e605d258460c543f38e5a5f6e568531ff29072cd489c05b.jpg)

Figure 3-19: FIFO Data In/Out Structure

With hardware-based waveform generation, D/A conversions are updated automatically by the FPGA rather than by the application software. Compared with conventional software based waveform generation, the precise hardware timing control guarantees non-distorted waveform generation even when the host CPU is under heavy loading.

# Waveform Generation Clock Source

When the onboard DAC receives a conversion clock signal, it will trigger a D/A update. The update clock of PCIe-9100 Series may come from two different clock sources: internal hardware timer, or external timebase clock source (CN3 pin 37). You can choose the update clock source by setting the AO source configuration

# Waveform Generation with Internal Hardware Timer

Six counters interact with the waveform to generate different DAWR timings to form various waveforms. These are described in Table 3-8 and illustrated in Figure 3-20.

<table><tr><td>Counter Name</td><td>Width</td><td>Description</td><td>Note</td></tr><tr><td>UI_counter</td><td>32-bit</td><td>Update Interval.Defines the update interval between each data output.</td><td>Update Interval = Timebase* / UI_counter</td></tr><tr><td>UC_counter</td><td>32-bit</td><td>Update Counts.Defines the number of data in a waveform.</td><td>When value in UC_counter is smaller than the size of waveform patterns, the waveform is generated piece-wisely.</td></tr><tr><td>IC_counter</td><td>32-bit</td><td>Iteration Counts.Defines how many times the waveform is generated.</td><td></td></tr><tr><td>Trig_counter</td><td>32-bit</td><td>Defines the acceptable start trigger count when re-trigger function is enabled</td><td></td></tr></table>

Table 3-8: Summary of Counters for Waveform Generation

![The image shows an icon of a white document page with horizontal black lines representing text. A large red checkmark is superimposed on the left side of the document.](.pcie-9100-50m-18094-1030-17/b2d246424bb8c418817d7ead8e8aac7cf026712281fec5b26dbad28f62ef1a8a.jpg)
NOTE:

 Timebase = 64M Hz
 The maximum D/A update rate is 1 MHz, and the minimum UI\_counter setting is 64.

![| Signal          | Event Description                     |\n|-----------------|----------------------------------------|\n| Trigger         | UC_Counter = 4 (Initial)             |\n| DAWR            | Delay until DLY1_Counter Reach 0     |\n| WF_in_Rrog      | Delay until DLY2_Counter Reach 0     |\n| Wave            | DA_Update_Interval T = UI_Counter / Timebase |\n| Transition      | UC_Counter = 4 (Initial)             |\n| Transition      | Delay until DLY1_Counter Reach 0     |\n| Transition      | Delay until DLY2_Counter Reach 0     |\n| Transition      | DA_Update_Interval T = UI_Counter / Timebase |](.pcie-9100-50m-18094-1030-17/8ddfc5e5b295ebb973295ae3c87b8e5a8cfffe4d5828bda372fc4567484a8893.jpg)

Figure 3-20: Typical D/A Timing of Waveform Generation

# 3.3.4 Trigger Modes

# Post-Trigger Generation

Use post-trigger generation when you want to generate a waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC\_counter\* IC\_counter, illustrated in Figure 3-21.

![| Signal          | Value |\n| --------------- | ----- |\n| Trigger         | 12    |\n| DAWR            | 12    |\n| WF_in_Rrog      | 12    |\n| Wave            | 12    |](.pcie-9100-50m-18094-1030-17/7c4f0b021a1a3eb251d3fc62fce1f19572358c26f6412ba359583883c59dcef9.jpg)

Figure 3-21: Post-Trigger Generation

# Post-Trigger with Retrigger

Use post-trigger with retrigger to generate multiple waveforms with respect to multiple incoming trigger signals. Set Trig\_counter to specify the number of acceptable trigger signals. Figure 3-22 Iillustrates two waveforms generated after the first trigger signal. The card then waits for another trigger signal. When the next trigger signal is asserted, the card generates two more waveforms. After two trigger signals, as specified in Trig\_Counter, no more triggers signals will be accepted unless the trigger reset command is executed. For more information on Iterative Waveform Generation used in this example, refer to the next section.

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 3     |\n| DAWR            | 3     |\n| WF_in_Rrog      | 3     |\n| Wave            | 3     |](.pcie-9100-50m-18094-1030-17/66767cefa4d9df9a53a759d6d6774a5bf7c9b2c49f2a3b6a48826f585b6aefcb.jpg)

Figure 3-22: Post-Trigger with Retrigger Generation

![A document icon featuring a white page with a folded top-right corner and faint horizontal lines at the bottom, overlaid with a large red checkmark.](.pcie-9100-50m-18094-1030-17/60089cbdb64db7fc231f76e32d43c30fa37c7527776667d55c0a005ba158f6fe.jpg)
NOTE:

Start Trigger signals asserted during the waveform generation process will be ignored.

# Iterative Waveform Generation

You can set the IC\_counter to generate iterative waveforms regardless of the trigger mode used. The IC\_counter stores the iteration number. Examples are shown in Figure 3-23 and Figure 3-24.

![The image shows a digital icon featuring a white document sheet with a folded top-right corner. Faint grey horizontal lines run across the page, resembling a list or text. A large, thick red checkmark is superimposed over the document.](.pcie-9100-50m-18094-1030-17/d97f5bfc3e4927e960212d65696edadf32852ca093369b3fd093aa10b5c4217b.jpg)
NOTE:

When IC\_counter is disabled, the waveform generation will not stop until a stop trigger is asserted.

An onboard data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host computer’s memory, the data in FIFO will be reused when a single waveform generation is completed and will not occupy the PCI Express bandwidth afterwards. However, if the size of a single waveform is larger than that of the FIFO, it needs to be intermittently loaded from the host computer’s memory via DMA, and will occupy the PCI Express bandwidth.

If the value specified in UC\_counter is smaller than the sample size of the waveform patterns, the waveform will be generated in a series of iterations. For example, if you defined a 16-sample sine wave and set the UC\_counter to 2, the generated waveform will be a 1/8-cycle sine wave for every waveform period, and a complete sine wave will be generated for every 8- iterations. If you specified a UC\_counter value that is larger than the sample size of the waveform LUT (for example, 32), the generated waveform will be a 2-cycle sine wave for every waveform period.

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WF_in_Rrog      | 4     |\n| Wave            | 4     |](.pcie-9100-50m-18094-1030-17/ad03f076b62257a5523730efcc16d288fb6fbe2cb4826e8c1bea482e8ffad079.jpg)

Figure 3-23: Finite Iterative Waveform Generation with Post-trigger

![| Signal          | Value |\n|-----------------|-------|\n| Trigger         | 4     |\n| DAWR            | 4     |\n| WF_in_Rrog      | 4     |\n| Wave            | 4     |\n| A single waveform | 4     |](.pcie-9100-50m-18094-1030-17/e60c5627ff8696847b9fb1473e7bc7d848f845cb748a7c0d0db9f4dca3c30e85.jpg)

Figure 3-24: Infinite Iterative Waveform Generation with Post-trigger

# 3.4 Digital Input and Output

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DI0</td><td>1</td><td>2</td><td>DI1</td></tr><tr><td>DI2</td><td>3</td><td>4</td><td>DI3</td></tr><tr><td>DI4</td><td>5</td><td>6</td><td>DI5</td></tr><tr><td>DI6</td><td>7</td><td>8</td><td>DI7</td></tr><tr><td>DI8</td><td>9</td><td>10</td><td>DI9</td></tr><tr><td>DI10</td><td>11</td><td>12</td><td>DI11</td></tr><tr><td>DI12</td><td>13</td><td>14</td><td>DI13</td></tr><tr><td>DI14</td><td>15</td><td>16</td><td>DI15</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>+5V</td><td>19</td><td>20</td><td>DI_SYNC_IN</td></tr></table>

Table 3-9: PCIe-9101/9121/9141 DIO Mode Pin Assignments on CN1

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DO0</td><td>1</td><td>2</td><td>DO1</td></tr><tr><td>DO2</td><td>3</td><td>4</td><td>DO3</td></tr><tr><td>DO4</td><td>5</td><td>6</td><td>DO5</td></tr><tr><td>DO6</td><td>7</td><td>8</td><td>DO7</td></tr><tr><td>DO8</td><td>9</td><td>10</td><td>DO9</td></tr><tr><td>DO10</td><td>11</td><td>12</td><td>DO11</td></tr><tr><td>DO12</td><td>13</td><td>14</td><td>DO13</td></tr><tr><td>DO14</td><td>15</td><td>16</td><td>DO15</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>+5V</td><td>19</td><td>20</td><td>DI_SYNC_OUT</td></tr></table>

Table 3-10: PCIe-9101/9121/9141 DIO Mode Pin Assignments on CN2

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>DI0</td><td>17</td><td>51</td><td>DI8</td></tr><tr><td>DI1</td><td>18</td><td>52</td><td>DI9</td></tr><tr><td>DI2</td><td>19</td><td>53</td><td>DI10</td></tr><tr><td>DI3</td><td>20</td><td>54</td><td>DI11</td></tr><tr><td>DI4</td><td>21</td><td>55</td><td>DI12</td></tr><tr><td>DI5</td><td>22</td><td>56</td><td>DI13</td></tr><tr><td>DI6</td><td>23</td><td>57</td><td>DI14</td></tr><tr><td>DI7</td><td>24</td><td>58</td><td>DI15</td></tr><tr><td>DGND</td><td>25</td><td>59</td><td></td></tr><tr><td>DO0</td><td>26</td><td>60</td><td>DO8</td></tr><tr><td>DO1</td><td>27</td><td>61</td><td>DO9</td></tr><tr><td>DO2</td><td>28</td><td>62</td><td>DO10</td></tr><tr><td>DO3</td><td>29</td><td>63</td><td>DO11</td></tr><tr><td>DO4</td><td>30</td><td>64</td><td>DO12</td></tr><tr><td>DO5</td><td>31</td><td>65</td><td>DO13</td></tr><tr><td>DO6</td><td>32</td><td>66</td><td>DO14</td></tr><tr><td>DO7</td><td>33</td><td>67</td><td>DO15</td></tr><tr><td>DGND</td><td>34</td><td>68</td><td></td></tr></table>

Table 3-11: PCIe-9146/9147 DIO Mode Pin Assignments on CN1

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DO0</td><td>1</td><td>2</td><td>DO1</td></tr><tr><td>DO2</td><td>3</td><td>4</td><td>DO3</td></tr><tr><td>DO4</td><td>5</td><td>6</td><td>DO5</td></tr><tr><td>DO6</td><td>7</td><td>8</td><td>DO7</td></tr><tr><td>DO8</td><td>9</td><td>10</td><td>DO9</td></tr><tr><td>DO10</td><td>11</td><td>12</td><td>DO11</td></tr><tr><td>DO12</td><td>13</td><td>14</td><td>DO13</td></tr><tr><td>DO14</td><td>15</td><td>16</td><td>DO15</td></tr><tr><td>DO_Trig</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>DI_Trig</td><td>19</td><td>20</td><td>DI_SYNC_OUT</td></tr></table>

Table 3-12: PCIe-9161/9163/9164 DIO Mode Pin Assignments on CN7

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DI0</td><td>1</td><td>2</td><td>DI1</td></tr><tr><td>DI2</td><td>3</td><td>4</td><td>DI3</td></tr><tr><td>DI4</td><td>5</td><td>6</td><td>DI5</td></tr><tr><td>DI6</td><td>7</td><td>8</td><td>DI7</td></tr><tr><td>DI8</td><td>9</td><td>10</td><td>DI9</td></tr><tr><td>DI10</td><td>11</td><td>12</td><td>DI11</td></tr><tr><td>DI12</td><td>13</td><td>14</td><td>DI13</td></tr><tr><td>DI14</td><td>15</td><td>16</td><td>DI15</td></tr><tr><td>DI16</td><td>17</td><td>18</td><td>DGND</td></tr><tr><td>+5V</td><td>19</td><td>20</td><td>DI_SYNC_IN</td></tr></table>

Table 3-13: PCIe-9161/9163/9164 DIO Mode Pin Assignments on CN8

# 3.4.1 TTL Compatible

The PCIe-9100 Series provides 16 digital input and 16 digital output channels through the connectors CN1 and CN2 onboard. The digital I/O signal is fully TTL/DTL compatible. The digital I/O signals are illustrated in Figure 3-25.

To program the digital I/O operation is fairly straightforward. The digital input operation is used to read data from corresponding registers, and the digital output operation is to write data to the corresponding registers. Note that the DIO data channel can only be read or written to in groups of 16 bits. It is impossible to access individual bits.

![This block diagram illustrates the interface between a **PCI-9100 Series** device (left) and an **Outside Device** (right), separated by a vertical bus line with three connection nodes.\n\n**Labeled Blocks and Connections:**\n\n*   **Digital Input (DI):**\n    *   **Label:** 'Digital Input (DI)'\n    *   **Right Connection:** An arrow pointing left towards the bus, labeled 'From TTL Signal'.\n    *   **Left Connection:** A triangle symbol pointing left (towards the PCI-9100 side).\n*   **Digital Output (DO):**\n    *   **Label:** 'Digital Output (DO)'\n    *   **Right Connection:** An arrow pointing right away from the bus, labeled 'To TTL Devices'.\n    *   **Left Connection:** A triangle symbol pointing right (towards the bus).\n*   **Digital GND (DGND):**\n    *   **Label:** 'Digital GND (DGND)'\n    *   **Connection:** A ground line connecting a ground symbol (inverted triangle) on the PCI-9100 side to a ground symbol on the Outside Device side.\n\n**Additional Connections:**\n*   On the far left, a vertical line connects the left terminals of the top and middle triangle symbols to the ground rail.](.pcie-9100-50m-18094-1030-17/dc79d1ae596c327032aef1bf528515be6af5768296a0615d206cca271032b578.jpg)

Figure 3-25: Digital I/O Connection

The PCIe-9100 Series also provides a DMA high speed data transfer mode up to 1M Hz with DI\_SYNC\_IN and DO\_SYNC\_OUT pins to synchronize DI and DO clock during data transmission.

# 3.4.2 Isolation (PCIe-9103 only)

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DI0</td><td>1</td><td>2</td><td>DI1</td></tr><tr><td>DI2</td><td>3</td><td>4</td><td>DI3</td></tr><tr><td>DI4</td><td>5</td><td>6</td><td>DI5</td></tr><tr><td>DI6</td><td>7</td><td>8</td><td>DI7</td></tr><tr><td>DI8</td><td>9</td><td>10</td><td>DI9</td></tr><tr><td>DI10</td><td>11</td><td>12</td><td>DI11</td></tr><tr><td>DI12</td><td>13</td><td>14</td><td>DI13</td></tr><tr><td>DI14</td><td>15</td><td>16</td><td>DI15</td></tr><tr><td>EICOM1</td><td>17</td><td>18</td><td>EICOM2</td></tr><tr><td>EICOM3</td><td>19</td><td>20</td><td>EICOM4</td></tr></table>

Table 3-14: PCIe-9103 DIO Mode Pin Assignments on CN1

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>DO0</td><td>1</td><td>2</td><td>DO1</td></tr><tr><td>DO2</td><td>3</td><td>4</td><td>DO3</td></tr><tr><td>DO4</td><td>5</td><td>6</td><td>DO5</td></tr><tr><td>DO6</td><td>7</td><td>8</td><td>DO7</td></tr><tr><td>DO8</td><td>9</td><td>10</td><td>DO9</td></tr><tr><td>DO10</td><td>11</td><td>12</td><td>DO11</td></tr><tr><td>DO12</td><td>13</td><td>14</td><td>DO13</td></tr><tr><td>DO14</td><td>15</td><td>16</td><td>DO15</td></tr><tr><td>EOGND</td><td>17</td><td>18</td><td>EOGND</td></tr><tr><td>Vpower</td><td>19</td><td>20</td><td>Vpower</td></tr></table>

Table 3-15: PCIe-9103 DIO Mode Pin Assignments on CN2

# 3.4.2.1 Isolated Digital Input

There are 16 Isolated Digital input signals. Each digital input signal is connect to a photo isolator such that the signal is isolated from the ground or the power plane of the host PC. The figure below illustrates a single digital input circuit.

![DI_n R=2.4K Ohm\nPhoto Isolator\nto digital circuits](.pcie-9100-50m-18094-1030-17/cd9d9767c1e699cb9d7173e59a959c10463aa7983c410b170c661a6dcc409f15.jpg)

Figure 3-26: Isolated Input Circuits

The Isolated Digital input could be an AC input. The isolation voltage is 2.5KVrms. The input resistance is 2.4K ohms.

Note that the 16 DI signals are partitioned into 4 groups. Each group is based on a common plane. Every group is mutually isolated. Refer to Figure 3-27 and Table 3-16 for the four groups.

<table><tr><td>Signal Names</td><td>Common Signal</td></tr><tr><td>ID_0 to ID_3</td><td>EICOM1</td></tr><tr><td>ID_4 to ID_7</td><td>EICOM2</td></tr><tr><td>ID_8 to ID_11</td><td>EICOM3</td></tr><tr><td>ID_12 to ID_15</td><td>EICOM4</td></tr></table>

Table 3-16: Digital input signals and ground plane

The common plane could be either common power or common ground. The following diagram shows the EICOM as common ground. An external device or circuit will provide the power source or current source.

![Isolated Input\n2.4K Ohm\nEICOM](.pcie-9100-50m-18094-1030-17/38c27db5b153f0f3e5d6248345b921403c5f9e947da2e53ada47583806704ada.jpg)

Figure 3-27: Common Ground

The following diagram shows the EICOM as common power. An external device or circuit will provide the power source and current sink. Most open collector output devices can be connected to the PCIe-9103 using this configuration.

![Isolated Input\nEICOM\n2.4K Ohm](.pcie-9100-50m-18094-1030-17/20507c69c492acb5fde78b7a9328180c02bac84893bdc8e94c83bbc618cfc975.jpg)

Figure 3-28: Common Power

# 3.4.2.2 Isolated Digital Output

There are 16 Isolated Digital output signals. Darlington transistors drive the digital output signals. Figure 3-29 shows the output circuits.

Note that the 16 DO signals uses a common ground and common external power source.

![From digital circuits\nVpower\nDO_n\nEOGND](.pcie-9100-50m-18094-1030-17/1bd7fa44d54febb487eb946982084ae972fa8632f456d9e228d32b4d6b06fcce.jpg)

Figure 3-29: Digital Output Circuits

The EOGND pin is used via a (fly-wheel) diode. This will protect the driver if an inductive load from a relay, motor or solenoid is present. If the loading is resistive such as from resistors or LEDs, the connection to the fly-wheel diode is not necessary.

The first step in connecting the output to an external device is to distinguish the type of load. For example, if the load is a LED or a resistor, connection diagram below can be used.

![From digital circuits\nVpower\nPower Supply\nDO_n\nLoad\nEOGND](.pcie-9100-50m-18094-1030-17/4c44a486bbcc1d27555d9602de882673ff6bf4ffa21c7da558787f1f31f26984.jpg)

Figure 3-30: Opto-isolated output circuit for resistive loads

If the load is inductive such as from a relay, the diagram below can be used. The power supply must be from an external source in order to form a fly-wheel current loop.

![From digital circuits\nVpower\nPower Supply\nDO_n\nLoad\nEOGND](.pcie-9100-50m-18094-1030-17/2c07783dc7f23965ebd04df73ede62f54357580330c5df4f3e6884892ad9c391.jpg)

Figure 3-31: Opto-isolated output circuit for inductive loads

# 3.5 General Purpose Timer/Counter

The PCIe-9100 Series comes with up to four general purpose timer/counter sets featuring:

 Count up/down controlled by hardware or software
 Programmable counter clock source (internal clock up to 33 MHz, external clock up to 8 MHz)
 Programmable gate selection (hardware or software control)
 Programmable input and output signal polarities (high active or low active)
 Initial count can be loaded from a software application
 Current count value can be read back by software without affecting circuit operation
 PWM with COF (change on the fly) support

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td></td><td>1</td><td>20</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>14</td><td>32</td><td></td></tr><tr><td>DGND</td><td>15</td><td>33</td><td>GPYC GATE0</td></tr><tr><td>GTPC COUT0</td><td>16</td><td>34</td><td>GPYC GATE1</td></tr><tr><td></td><td>17</td><td>35</td><td>GTPC COUT1</td></tr><tr><td></td><td>18</td><td>36</td><td></td></tr><tr><td></td><td>19</td><td>37</td><td>GPTC CLK</td></tr></table>

Table 3-17: PCIe-9101/9121/9141 GPTC Mode Pin Assignments on CN3

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>GPTC CLK</td><td>1</td><td>2</td><td></td></tr><tr><td>GPTC COUT</td><td>3</td><td>4</td><td></td></tr><tr><td>GPTC GATE</td><td>5</td><td>6</td><td></td></tr><tr><td>GND</td><td>7</td><td>8</td><td></td></tr><tr><td></td><td>9</td><td>10</td><td></td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>GPTC CLK0</td><td>17</td><td>51</td><td>GPTC CLK1</td></tr><tr><td></td><td>18</td><td>52</td><td>GPTC GATE0</td></tr><tr><td></td><td>19</td><td>53</td><td>GPTC GATE1</td></tr><tr><td></td><td>20</td><td>54</td><td></td></tr><tr><td></td><td>21</td><td>55</td><td></td></tr><tr><td></td><td>22</td><td>56</td><td></td></tr><tr><td></td><td>23</td><td>57</td><td></td></tr><tr><td></td><td>24</td><td>58</td><td></td></tr><tr><td></td><td>25</td><td>59</td><td></td></tr><tr><td></td><td>26</td><td>60</td><td>GPTC COUT0</td></tr><tr><td></td><td>27</td><td>61</td><td>GPTC COUT1</td></tr><tr><td></td><td>28</td><td>62</td><td></td></tr><tr><td></td><td>29</td><td>63</td><td></td></tr><tr><td></td><td>30</td><td>64</td><td></td></tr><tr><td></td><td>31</td><td>65</td><td></td></tr><tr><td></td><td>32</td><td>66</td><td></td></tr><tr><td></td><td>33</td><td>67</td><td></td></tr><tr><td>DGND</td><td>34</td><td>68</td><td></td></tr></table>

Table 3-18: PCIe-9103 GPTC Mode Pin Assignments on CN4

Table 3-19: PCIe-9146/9147 GPTC Mode Pin Assignments on CN1

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>GPTC_COUT0</td><td>1</td><td>2</td><td>GPTC_COUT1</td></tr><tr><td>GPTC_COUT2</td><td>3</td><td>4</td><td>GPTC_COUT3</td></tr><tr><td></td><td>5</td><td>6</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>15</td><td>16</td><td></td></tr><tr><td></td><td>17</td><td>18</td><td>DGND</td></tr><tr><td></td><td>19</td><td>20</td><td></td></tr></table>

Table 3-20: PCIe-9161/9163/9164 GPTC Mode Pin Assignments on CN7

<table><tr><td>Definition</td><td colspan="2">Pin No,</td><td>Definition</td></tr><tr><td>GPTC_GATE0</td><td>1</td><td>2</td><td>GPTC_GATE1</td></tr><tr><td>GPTC_GATE2</td><td>3</td><td>4</td><td>GPTC_GATE3</td></tr><tr><td>GPTC_CLK0</td><td>5</td><td>6</td><td>GPTC_CLK1</td></tr><tr><td>GPTC_CLK2</td><td>7</td><td>8</td><td>GPTC_CLK3</td></tr><tr><td></td><td>9</td><td>10</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>17</td><td>18</td><td>DGND</td></tr><tr><td></td><td>19</td><td>20</td><td></td></tr></table>

Table 3-21: PCIe-9161/9163/9164 GPTC Mode Pin Assignments on CN8

# 3.5.1 Basic Timer/Counter Functions

Each timer/counter has three inputs that can be controlled via hardware or software applications: clock input (GPTC\_CLK), gate input (GPTC\_GATE), and up/down control input (GPTC\_UD). The GPTC\_CLK input provides a clock source input to the timer/counter controlled by software which can switch the clock source internally or externally. Active edges on the GPTC\_CLK input make the counter increment or decrement. The GPTC\_UD input controls the counter up or down (high: count up; low: count down), while the GPTC\_GATE input is a control signal which acts as a counter enabling or a counter trigger signal under different applications. GPTC\_OUT will then generate a pulse signal based on which timer/counter mode you have set. All input/output signal polarities can be programmed by software. For brevity, all GPTC\_CLK, GPTC\_GATE, and GPTC\_OUT in the following illustrations are assumed to be active high or rising-edge triggered.

# 3.5.2 General Purpose Timer/Counter Modes

Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by software. The GPTC software reset initializes the status of the counter and reloads the initial value to the counter. The operation remains halted until software-start is executed again. The operating theories under different modes are described in the following sections.

# Mode 1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the GPTC\_CLK after software-start. Initial count can be loaded from software. The current count value can be read back by software any time with no effect on the counting. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 3-32 illustrates the operation with initial count = 5, count-down mode.

![| Time | Gate | CLK |\n|------|------|-----|\n| 5    | 1    | 1   |\n| 3    | 1    | 1   |\n| 2    | 1    | 1   |\n| 1    | 1    | 1   |\n| 0    | 1    | 1   |\n| tfff | 1    | 1   |](.pcie-9100-50m-18094-1030-17/c9d078b1e3c0b05cca501028c87ef37d16c8a1016278ec9437e5d32baec63169.jpg)

Figure 3-32: Simple Gated-Event Counting

# Mode 2: Single Period Measurement

The counter counts the period of the signal on GPTC\_GATE in terms of GPTC\_CLK. The initial count can be loaded from software. After software-start, the counter counts the number of active edges on GPTC\_CLK between two active edges of GPTC\_GATE. After the completion of the period interval on GPTC\_GATE, GPTC\_OUT outputs high and then the current count value can be read back by software. Figure 3-33 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value 0 0 1 2 3 4 5 5 5](.pcie-9100-50m-18094-1030-17/c664bc886a8b4c611855536c66b353d83ef7e1630da8674f78fba2612b97b8b5.jpg)

Figure 3-33: Simple Period Measurement

# Mode 3: Single Pulse-width Measurement

The counter counts the pulse-width of the signal on GPTC\_GATE in terms of GPTC\_CLK. The initial count can be loaded from software. After software-start, the counter counts the number of active edges on GPTC\_CLK when GPTC\_GATE is in its active state. After the completion of the pulse-width interval on GPTC\_GATE, GPTC\_OUT outputs high and then the current count value can be read back by software. Figure 3- 34 illustrates the operation where initial count = 0, count-up mode.

![Software start\nGate\nCLK\nCount value 0 0 1 2 3 4 5 5 5](.pcie-9100-50m-18094-1030-17/d59e657343ea25e1d6c8be29e7b7a971e98bf938325c072bc1acc50ca04e3bf2.jpg)

Figure 3-34: Simple Pulse-width Measurement

# Mode 4: Single Gated Pulse Generation

This generates a single pulse with programmable delay and programmable pulse-width following software-start. The two programmable parameters can be specified in terms of periods of the GPTC\_CLK input by software. GPTC\_GATE is used to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 3-35 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 2     |\n| CLK        | 2     |\n| Count value| 2     |\n| OUT        | 2     |](.pcie-9100-50m-18094-1030-17/ae8b4f4a046644e7bebd4ed03153a6498c34d680bc54d52a30bb05fcfccd5f46.jpg)

Figure 3-35: Simple Gated Pulse Generation

# Mode 5: Single Triggered Pulse Generation

This mode generates a single pulse with programmable delay and programmable pulse-width following an active GPTC\_GATE edge. You may specify these programmable parameters in terms of periods of the GPTC\_CLK input. When the first GPTC\_GATE edge triggers the single pulse, GPTC\_GATE takes no effect until software-start is executed again. Figure 3-36 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 2     |\n| CLK        | 2     |\n| Count value| 2     |\n| OUT        | 0     |](.pcie-9100-50m-18094-1030-17/b65d457ae362032df3e0d95bb158c9dfa132219ea4b8a86f6dd64a1b7b00f7be.jpg)

Figure 3-36: Simple Triggered Pulse Generation

# Mode 6: Re-triggered Single Pulse Generation

This mode is similar to Mode 5 except that the counter generates a pulse following every active edge of GPTC\_GATE. After software-start, every active GPTC\_GATE edge triggers a single pulse with programmable delay and pulsewidth. Any GPTC\_GATE triggers that occur when the prior pulse is not completed is ignored. Figure 3-37 illustrates the generation of two pulses with a pulse delay of two and a pulse width of four.

![| Signal     | Value |\n|------------|-------|\n| Gate       | 0     |\n| CLK        | 0     |\n| Count value| 2     |\n| OUT        | 0     |](.pcie-9100-50m-18094-1030-17/0d4843672f6db532826d78b3b1a144b44bb15e6caf909b4b05360c489776f29b.jpg)

Figure 3-37: Re-triggered Single Pulse Generation

# Mode 7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode 5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC\_GATE. When the first GPTC\_GATE edge triggers the counter, GPTC\_GATE takes no effect until software-start is executed again. Figure 3-38 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![Software start\nGate\nCLK\nCount value 4 4 1 1 1 0 2 1 0 1 1 0 2 1 0 1 1\nOUT](.pcie-9100-50m-18094-1030-17/f14b93f118a595c1e662374797d253908fff79cb33bc4d9796c86a1fb4931ba3.jpg)

Figure 3-38: Re-triggered Single Pulse Generation

# Mode 8: Continuous Gated Pulse Generation

This mode generates periodic pulses with a programmable pulse interval and pulse-width following software-start. GPTC\_GATE is use to enable/disable counting. When GPTC\_GATE is inactive, the counter halts the current count value. Figure 3-39 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

![Software start\nGate\nCLK\nCount value\nOUT](.pcie-9100-50m-18094-1030-17/1e2d8836c0075e4080b8ff8f9990bce5c233b933228fce917b61a0e616512076.jpg)

Figure 3-39: Continuous Gated Pulse Generation

# 3.5.3 PWM Modes

The PCIe-9100 Series powerful timer/counter can also simulate a PWM (Pulse Width Modulation) output. By setting varying number of Pulse\_initial\_cnt and Pulse\_length\_cnt, you can get a varying pulse frequency (Fpwm) and duty cycle (Dutypwm). This parameters can change immediately when PWM mode is operating COF (Change on the Fly). Figure 3-40 illustrates the PWM output and the formula showing how to calculate the PWM frequency and duty cycle.

![PWMOUT\nTIMEBASE\nPulse_Initial_cnt =0x7\nPulse_length_cnt =0xB](.pcie-9100-50m-18094-1030-17/bb6a8b95d3d7284ed212c32ddc7001df54dc3df67df9f5193dcbb79ee991a49a.jpg)

Figure 3-40: PWM Mode

$$
F _ {P W M} = \frac {F _ {\text { Timebase }}}{\text { Pulse } \_ i n i t i a l \_ c n t + \text { Pulse } \_ l e n g t h \_ c n t}
$$

$$
D u t y _ {P W M} = \frac {\text { Pulse\_length\_cnt }}{\text { Pulse\_initial\_cnt } + \text { Pulse\_length\_cnt }}
$$

# 3.6 Encoder

The PCIe-9100 Series features a simple motion control with support for two channel encoder input sets which provide an alternative for a step motor or servo motor's position feedback. The encoder sets are assigned in CN1 or CN8 depending on the model.

<table><tr><td>Definition</td><td colspan="2">Pin No.</td><td>Definition</td></tr><tr><td></td><td>1</td><td>35</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td>EA0+</td><td>17</td><td>51</td><td>EA0-</td></tr><tr><td>EB0+</td><td>18</td><td>52</td><td>EB0-</td></tr><tr><td>EZ0+</td><td>19</td><td>53</td><td>EZ0-</td></tr><tr><td>EORG0+</td><td>20</td><td>54</td><td></td></tr><tr><td></td><td>21</td><td>55</td><td>EORG1</td></tr><tr><td>EA1+</td><td>22</td><td>56</td><td>EA1-</td></tr><tr><td>EB1+</td><td>23</td><td>57</td><td>EB1-</td></tr><tr><td>EZ1+</td><td>24</td><td>58</td><td>EZ1-</td></tr><tr><td>DGND</td><td>25</td><td>59</td><td></td></tr><tr><td></td><td>26</td><td>60</td><td></td></tr><tr><td></td><td>27</td><td>61</td><td></td></tr><tr><td></td><td>28</td><td>62</td><td></td></tr><tr><td></td><td>29</td><td>63</td><td></td></tr><tr><td></td><td>30</td><td>64</td><td></td></tr><tr><td></td><td>31</td><td>65</td><td></td></tr><tr><td></td><td>32</td><td>66</td><td></td></tr><tr><td></td><td>33</td><td>67</td><td></td></tr><tr><td>DGND</td><td>34</td><td>68</td><td></td></tr></table>

Table 3-22: PCIe 9146/9147 CN1 Encoder Mode Pin Assignments

<table><tr><td>Definition</td><td colspan="2">Pin No.</td><td>Definition</td></tr><tr><td>EA0+</td><td>1</td><td>2</td><td>EA0-</td></tr><tr><td>EB0+</td><td>3</td><td>4</td><td>EB0-</td></tr><tr><td>EZ0+</td><td>5</td><td>6</td><td>EZ0-</td></tr><tr><td>EA1+</td><td>7</td><td>8</td><td>EA1-</td></tr><tr><td>EB1+</td><td>9</td><td>10</td><td>EB1-</td></tr><tr><td>EZ0+</td><td>11</td><td>12</td><td>EZ1-</td></tr><tr><td></td><td>13</td><td>14</td><td></td></tr><tr><td></td><td>...</td><td>...</td><td></td></tr><tr><td></td><td>17</td><td>18</td><td>DGND</td></tr><tr><td></td><td>19</td><td>20</td><td></td></tr></table>

Table 3-23: PCIe 9161/9163/9164 CN8 Encoder Mode Pin Assignments

# Encoder Input Module

Figure 3-41 illustrates the encoder isolation phase A, phase B and phase Z inputs module.
![The diagram depicts a signal processing chain consisting of two main blocks: a **Line Receiver** and a **Buffer**, followed by an output label.\n\n**Labeled Blocks:**\n*   **Line Receiver**\n*   **Buffer**\n\n**Inputs (Left Side):**\n*   **Encoder phase A+** / **Encoder phase A-**: Points to the top section.\n*   **Encoder phase B+** / **Encoder phase B-**: Points to the middle section.\n*   **Encoder phase Z+** / **Encoder phase Z-**: Points to the bottom section.\n\n**Line Receiver Block Contents & Connections:**\n*   Contains six buffers (triangles with small squares next to their outputs), arranged in three pairs.\n*   **Top Pair:** Labeled **1A** (with number **2**) and **1B** (with number **1**). Their outputs are connected together by a vertical line.\n*   **Middle Pair:** Labeled **2A** (with number **6**) and **2B** (with number **7**). Their outputs are connected together by a vertical line.\n*   **Bottom Pair:** Labeled **3A** (with number **10**) and **3B** (with number **9**). Their outputs are connected together by a vertical line.\n*   **Outputs:** Three distinct lines emerge from the right side of this block.\n\n**Buffer Block Contents & Connections:**\n*   Contains three buffers (triangles).\n*   **Inputs:** The three lines from the Line Receiver connect to the inputs of these three buffers.\n*   **Internal Connection:** The output terminals of these three buffers are connected together by a vertical line.\n*   **Outputs:** Three distinct arrows emerge from the right side of the block.\n\n**Final Output:**\n*   The three output arrows are labeled **Internal signal to FPGA**.](.pcie-9100-50m-18094-1030-17/9d50006e70e2fac38e9bf88bc1bc2f9447cb24b4dbd9dbc629a892ccada7f94d.jpg)

Figure 3-41: Encoder Input Module

The Encoder OGRx input is different from the encoder phase input since you need to add external +24V power to drive the photocouple. Figure 3-42 shows the OGRx input.

![The image displays a simple block diagram with a left-to-right signal flow:\n\n1.  **Input:** The text **'ORG (5V)'** is on the far left.\n2.  **Central Component:** An arrow points from 'ORG (5V)' to a rectangular box. Inside the box is a logic symbol resembling a buffer (a triangle pointing to the right) with a feedback loop connecting the output (right side of the triangle) back to the input (left side of the triangle).\n3.  **Output:** An arrow points from the right side of the box to the text **'Internal signal to FPGA'**.](.pcie-9100-50m-18094-1030-17/c5ba5f8204e740f669e90325fa571a58f72ab4ae0e60a07c6d7cadb42ec39f88.jpg)

Figure 3-42: Encoder OGRx Input

# CW/CCW Encoder Mode

When the Encoder is set to CW/CCW mode and when the input EAx is connected to a CW source signal and EBx is connected to a CCW source signal, pulses from EAx will cause the counter to count up and spin the motor clockwise.

Otherwise, pulses from EBx will cause the counter to count down and spin the motor counterclockwise. Figure 3-43 shows the increase/decrease of the counter value in CW or CCW encoder mode.

![CW\nCCW\nEA0/EA1\nEB0/EB1\nCount Value 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2](.pcie-9100-50m-18094-1030-17/8a1ee12abe387c97671fb605f8ad476b5f2af54e0aa9733a67a0b5027e1f5154.jpg)

Figure 3-43: CW/CCW Encoder Timing

# X1 Encoder Mode

In X1 encoder mode, if phase A (EA0/EA1) is ahead of phase B (EB0/EB1) in a quadrature cycle, the counter value will increase by 1. Otherwise, if phase B is ahead of phase A in a quadrature cycle, the counter value will decrease by1.

Figure 3-44 shows a quadrature cycle and the increase and decrease of counter value in X1 encoder mode. When phase A leads phase B, the counter value increases on the first rising edge of CLK after phase A goes high. When phase B leads phase A, the counter value decreases on the first rising edge of CLK after phase A goes low.

![Phase A\nPhase B\nCLK\nCount Value 0 1 1 2 2 3 3 2 2 1](.pcie-9100-50m-18094-1030-17/8f9e22b99d7f4cb9a7900e4ea64554e12f16b6b895a2577092ec21683beca1f2.jpg)

Figure 3-44: X1 Encoder Mode

# X2 Encoder Mode

This mode is similar to X1 Encoder Mode, except that the amount of the counter value increases or decreases by two. Refer to Figure 3-45.

![Phase A\nPhase B\nCLK\nCount Value 0 1 2 3 4 5 5 4 3 2 1](.pcie-9100-50m-18094-1030-17/684dc7614efec0547e90a53bbe364ecdb320cb8c9ce5370d7d4a4d5c0a1531c1.jpg)

Figure 3-45: X2 Encoder Mode

# X4 Encoder Mode

This mode is similar to X1 Encoder Mode, except that the amount of the counter value increases or decreases by four. Refer to Figure 3-46.

![| Time | Phase A | Phase B | CLK |\n|------|---------|---------|-----|\n| 0    | High    | Low     | Low |\n| 1    | High    | Low     | Low |\n| 2    | High    | Low     | Low |\n| 3    | High    | Low     | Low |\n| 4    | High    | Low     | Low |\n| 5    | High    | Low     | Low |\n| 6    | High    | Low     | Low |\n| 7    | High    | Low     | Low |\n| 8    | High    | Low     | Low |\n| 9    | High    | Low     | Low |\n| 0    | ...     | ...     | ... |\n| 1    | ...     | ...     | ... |\n| 2    | ...     | ...     | ... |\n| 3    | ...     | ...     | ... |\n| 4    | ...     | ...     | ... |\n| 5    | ...     | ...     | ... |\n| 6    | ...     | ...     | ... |\n| 7    | ...     | ...     | ... |\n| 8    | ...     | ...     | ... |\n| 9    | ...     | ...     | ... |\n| 0    | ...     | ...     | ... |\n| 1    | ...     | ...     | ... |\n| 2    | ...     | ...     | ... |\n| 3    | ...     | ...     | ... |\n| 4    | ...     | ...     | ... |\n| 5    | ...     | ...     | ... |\n| 6    | ...     | ...     | ... |\n| 7    | ...     }(fcel)...     | ...     | ... |\n| 8    | ...     | ...     | ... |\n| 9    | ...     | ...     | ... |\n| 0    | ...     | ...     | ... |\n| 1    | ...     | ...     | ... |\n| 2    | ...     | ...     | ... |\n| 3    | ...     | ...     | ... |\n| 4    | ...     | ...     | ... |\n| ...  | ...     | ...     | ... |\n| 9    | ...     | ...     | ... |\n| 8    | ...     | ...     | ... |\n| 7    | ...     | ...     | ... |\n| 6    | ...     | ...     | ... |\n| 5    | ...     | ...     | ... |\n| 4    | ...     | ...     | ... |\n| 3    | ...     | ...     | ... |\n| 2    | ...     | ...     | ... |\n| 1    | ...     | ...     | ... |\n| 0    | ...     | ...     | ... |\nCount Value: 0, 1, 2, ..., 3, 4, ..., 5, ..., 6, ..., 7, ..., 8, ..., 9](.pcie-9100-50m-18094-1030-17/338e863453b1dc9019abbc6b64c3842e726012594d35a6b6d921a3a32d82e539.jpg)

Figure 3-46: X4 Encoder Mode

# Phase Z

Each encoder mode can use a third phase, phase Z, that is also frequently used for the index phase. You can decide if the counter needs to reload a specified value when phase Z is at a logic high level with phase A and B at a specific logic condition.

You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z; otherwise, the counter does not reload.

In Figure 3-47, the reload phase is when the logic level of phase A is high, phase B is low, and phase Z is high in X1 Encoder Mode. In addition, reloading takes higher priority than inceasing or decreasing of the counter value. The reload occurs within one maximum CLK period after the reload phase becomes true. After the counter value is reloaded, the counter continues to count as before.

![| Phase   | Value |\n|---------|-------|\n| Phase A | 0     |\n| Phase B | 1     |\n| Phase Z | 2     |\n| CLK     | 3     |](.pcie-9100-50m-18094-1030-17/554b15b5fc6069a44f71acb7012455d8db8a03fe6eae722ca73a0bbd7e5076b9.jpg)

Figure 3-47: Phase Z

# Original Signal (ORGx)

Original Signal (ORG0/ORG2/ORG1) is used with phase Z.

With ORG enabled, a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle. When you use the ORG signal if it is at a low level and phase Z is at a high level, then the counter reload is ignored.

![The image displays a graphic icon of a white document with a folded top-right corner. Faint grey horizontal lines run across the document, suggesting text. A large, bold red checkmark is superimposed over the document, angled diagonally from the bottom left to the top right.](.pcie-9100-50m-18094-1030-17/b16afed0fe376e937120acbc9fa8f4061ef032f2be1dd1dd93fb127a31e9df7e.jpg)
NOTE:

ORGx signal pin of PCIe-9146/9147 only support 5V TTL compatible signal.

# 3.7 Pattern Match

The PCIe-9161/9163/9164 cards feature a pattern matching function, which automatically performs preassigned actions upon encountering predefined patterns without involving any software. With this pattern match function, users can achieve real-time process control for any aspect application.

The patterns predefined could be programmable DI codes on DI port or position values from the encoder interface. Up to 1024 sets of DI can be defined for each of encoder#0 and encoder#1.

Once set, whenever specific patterns are met, the PCIe-9161/ 9163/9164 will perform the preassigned actions on its AO port or DO port, with/without asserting corresponding interrupt event to the user’s application.

The process flow of the pattern match function is outlined below..

![**Labeled Blocks:**\n*   DI pattern\n*   Encoder pattern\n*   AO (top left)\n*   DO (top left)\n*   Setup pattern\n*   Setup action\n*   Interrupt (bottom left input)\n*   Match pattern?\n*   Action\n*   AO (top right output)\n*   DO (middle right output)\n*   Interrupt (bottom right output)\n\n**Connections:**\n*   Dotted arrows connect 'DI pattern' and 'Encoder pattern' to 'Setup pattern'.\n*   A solid arrow connects 'Setup pattern' to 'Setup action'.\n*   Dotted arrows connect the top-left 'AO', 'DO', and the bottom-left 'Interrupt' to 'Setup action'.\n*   A solid arrow connects 'Setup action' to the 'Match pattern?' decision diamond.\n*   A loop labeled 'No' connects 'Match pattern?' back to 'Setup action'.\n*   A solid arrow labeled 'Yes' connects 'Match pattern?' to the 'Action' block.\n*   Arrows connect 'Action' to the right-side 'AO', 'DO', and 'Interrupt' blocks.](.pcie-9100-50m-18094-1030-17/136facad3c626caef54c13961903169f2fa5aecd8120b2edd78ec4eaac48ad23.jpg)

The following is a list of the operational mode combinations that the pattern match function can perform.

 Interrupt-event
 Output DO status in static polling mode or DO pattern in continuous mode
 Output AO level in static polling mode or AO waveform in continuous mode
 Output DO status in static polling mode or DO pattern in continuous mode with applied interrupt-event
 Output AO level in static polling mode or AO waveform in continuous mode with applied interrupt-event

![The image displays a digital icon featuring a white document with a folded upper-right corner and faint grey horizontal lines. A large, bold red checkmark is superimposed over the center of the document.](.pcie-9100-50m-18094-1030-17/a8bbd69fe589633d4453054c58985e57520b4e37ed8c6ee100307fd04a00dc95.jpg)
NOTE:

For detailed usage of the pattern match function, please refer to the example codes of PCIe-9161/9163/9164.

# 3.8 Programmable Function I/O

The PCIe-9146/9147/9161/9163/9164 supports a powerful programmable function I/O provided by an FPGA chip. These functional I/Os can be configured to three modes by software.

Mode 0: TTL compatible Digital Input/Output (See “Digital Input and Output” on page 79.)
 Mode 1: 32-bit timer/counters (See “General Purpose Timer/Counter” on page 88.)
 Mode 2: Encoder input (See “Encoder” on page 99.)

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

 Read these safety instructions carefully
 Keep the User’s Manual for future reference
 Read the Specifications section of this manual for detailed information on the recommended operating environment
? The device can be operated at an ambient temperature of 50ºC
? When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing:
 Turn off power and unplug any power cords/cables
 Reinstall all chassis covers before restoring power

 To avoid electrical shock and/or damage to device:

 Keep device away from water or liquid sources
 Keep device away from high heat or humidity
 Keep device properly ventilated (do not block or cover ventilation openings)
 Always use recommended voltage and power source settings
 Always install and operate device near an easily accessible electrical outlet
 Secure the power cord (do not place any object on/over the power cord)
 Only install/attach and operate device on stable surfaces and/or recommended mountings

 If the device will not be used for long periods of time, turn off and unplug from its power source

 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the triangle, a white rectangle contains the text 'CAUTION:' in black capital letters.](.pcie-9100-50m-18094-1030-17/3ee8edfc7bc273fb84efabcd87041cfd9b8ec1f0d4c4aeda57673506bc583e94.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged
 Liquid has entered the device interior
 The device has been exposed to high humidity and/or moisture
 The device is not functioning or does not function according to the User’s Manual
 The device has been dropped and/or damaged and/or shows obvious signs of breakage

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up
 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required

 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

If PoE (Power over Ethernet) is enabled for the device, the system can ONLY be deployed indoors. Unless otherwise noted, the PoE system is NOT designed to withstand the rigors of outdoor use.

![Yellow triangular warning sign with black smoke symbol indicating thermal hazard](.pcie-9100-50m-18094-1030-17/b33c2a7055a13d0a6cc6321f1d306c9974abe05fc20b10c84c7093658bd46894.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

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