# PCIe-9814

# 4-CH 12-Bit 80MS/s Digitizer

# PCIe-9814/PCIe-9814P

# User's Manual

![Close-up of a green printed circuit board (PCB) with gold connectors and various electronic components, no visible text or symbols.](.pcie-9814-50-11256-1000-200-en/4a0f491932f1e42f02df642c7c2842818e9d6c6c06b7025c548c6a7b0cd1fedd.jpg)

Manual Rev.: 2.00

Revision Date: Feb. 13, 2015

Part No: 50-11256-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2015/02/13</td><td>Initial Release</td></tr></table>

# Preface

# Copyright 2015 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a graphic of a white piece of paper with a folded top-left corner and faint horizontal lines running across it. A large, bold red checkmark is superimposed over the center of the document.](.pcie-9814-50-11256-1000-200-en/8fe56cc7ddfe99d30a5338a9c5c7c12d3d286adb4327a9a5a439663f6db25646.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.pcie-9814-50-11256-1000-200-en/b6c0fa28ff84d04f7fe4daf9d04c362743d33531576332a05af8ba6b57da0957.jpg)

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a warning sign featuring a red, upward-pointing triangle with a white border. Inside the triangle is a white exclamation point. Below the triangle, the word 'WARNING' is written in black capital letters.](.pcie-9814-50-11256-1000-200-en/10d37ff056f6640429c859ff74877cda19ea069a094f8315506034ea0c90d61d.jpg)

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface .... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2

1.3.1 Analog Input 2
1.3.2 Timebase 4
1.3.3 Triggers 5
1.3.4 General Specifications....6

1.4 Software Support 6

1.4.1 WD-DASK....7
1.4.2 LabVIEW Support....7

1.5 Device Layout and I/O Array 8

# 2 Getting Started 11

2.1 Installation Environment 11
2.2 Installing the Module.... 12

# 3 Operations 13

3.1 Functional Block Diagram.... 13
3.2 Analog Input Channel 13

3.2.1 Analog Input Front-End Configuration 13
3.2.2 Input Range and Data Format 14
3.2.3 DMA Data Transfer....15
3.2.4 Synchronous Digital Input....16

3.3 Trigger Source and Trigger Modes.... 17

3.3.1 Software Trigger 18
3.3.2 External Digital Trigger 18
3.3.3 Analog Trigger 18

# 3.4 Trigger Modes.... 19

3.4.1 Post Trigger Mode 19
3.4.2 Delayed Trigger Mode 19
3.4.3 Pre-Trigger Mode....20
3.4.4 Middle Trigger Mode....20
3.4.5 Acquisition with Re-Triggering 21

# 3.5 Timebase 22

3.5.1 Internal Sampling Clock....22
3.5.2 External Reference Clock (PCIe-9814P only) ...... 22
3.5.3 External Sampling Clock....22

# 3.6 ADC Timing Control 23

3.6.1 Timebase Architecture....23
3.6.2 Basic Acquisition Timing....23

# 3.7 Synchronizing Multiple Modules 25

3.7.2 SSI\_TRIG 28

3.8 SDI 28
3.9 Multi-boot 29

# A Appendix: Calibration.... 31

A.1 Calibration Constant 31
A.2 Auto-Calibration 31

# Important Safety Instructions.... 33

# Getting Service 35

# List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp......4

Figure 1-2: PCIe-9814 Schematic....8

Figure 1-3: PCIe-9814 I/O Array 9

Figure 3-1: Analog Input Architecture 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ..... 16

Figure 3-3: Synchronous Digital Input Operations ..... 17

Figure 3-4: Trigger Architecture 17

Figure 3-5: External Digital Trigger 18

Figure 3-6: Post-Trigger Acquisition .... 19

Figure 3-7: Delayed Trigger Mode Acquisition....20

Figure 3-8: Pre-Trigger Mode Acquisition 20

Figure 3-9: Middle Trigger Mode Acquisition ....21

Figure 3-10: Re-Trigger Mode Acquisition 21

Figure 3-11: PCIe-9814 Clock Architecture 22

Figure 3-12: PCIe-9814 Timebase Architecture ...... 23

Figure 3-13: Basic Digitizer Acquisition Timing....24

Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval Counter....24

Figure 3-15: Card Number Configuration Switch 27

Figure 3-16: Flash Memory Configuration Switch....29

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# List of Tables

Table 1-1: Channel Characteristics....3
Table 1-2: PCIe-9814 I/O Array Legend 10
Table 3-1: Input Range and Data Format 14
Table 3-2: Input Range FSR and -FSR Values....14
Table 3-3: Input Range Midscale Values....15
Table 3-4: Counter Parameters and Description 25
Table 3-5: SSI Signal Location and Pin Definition 26
Table 3-6: Card Number Configuration Settings....28
Table 3-7: SDI Input vs. Data....28

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# 1 Introduction

The ADLINK PCIe-9814 is a 4-channel, 12-bit, 80MS/s PCI Express digitizer providing speedy, high quality data acquisition. Each of the four input channels supports up to 80MS/s sampling, with 12-bit resolution A/D converter. 40MHz bandwidth analog input with 50Ω impedance receives ±0.5V, ±1V, ±5V, and ±10V high speed signals, and a simplified front end and highly stable onboard reference provide both highly accurate measurement results and high dynamic performance.

The PCIe-9814, based on x4 lane slot PCI Express technology, can be used in any standard PCI Express slot, x4, x8, or x16. With a PCI Express bus interface and extremely large onboard memory (up to 1GB), the PCIe-9814 easily manages simultaneous 4-CH data streaming even at the highest sampling rates.

The PCIe-9814 is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following auto-calibration, the calibration constant is stored in EEPROM, such that these values can be loaded and used as needed by the board. There is no requirement to calibrate the module manually.

# 1.1 Features

▶ Up to 80MS/s sampling
▶ 4 simultaneous analog inputs
▶ High resolution 12-bit ADC
▶ Up to 40 MHz bandwidth for analog input
▶ 1GB onboard storage
▶ Programmable input voltage of ±0.5V, ±1V, ±5V, or ±10V
▶ Scatter/gather DMA data transfer for high speed streaming
▶ 10 or 20MHz digital onboard filter (FPGA)
PLL module provides precise synch (PCIe-9814P only)
▶ Supports:
▶ One external digital trigger input
▶ One external clock input
▶ Three SDI inputs
▶ Full auto-calibration

# 1.2 Applications

▶ Testing/monitoring for Energy Management applications, including:

▷ Partial discharge
▶ Power line/device monitoring

▶ Non-destructive testing
▶ Radar acquisition
LiDAR

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td>Item</td><td>Detail</td><td>Comments</td></tr><tr><td>Channels</td><td>4 single-ended</td><td></td></tr><tr><td>Connector type</td><td>SMB</td><td></td></tr><tr><td>input coupling</td><td>DC</td><td></td></tr><tr><td>ADC resolution</td><td>12-Bit</td><td></td></tr><tr><td>input signal range</td><td>±0.5 V, ±1 V, ± 5V, or ± 10V</td><td></td></tr><tr><td>Bandwidth(-3dB)</td><td>40MHz</td><td></td></tr><tr><td rowspan="3">Overvoltage</td><td>±10V sine wave / 7 Vrms</td><td>50Ω, all ranges</td></tr><tr><td>±10V</td><td>1M Ω, ±0.5V or ±1V</td></tr><tr><td>±30V</td><td>1M Ω, ±5V or ±10V</td></tr><tr><td>input impedance</td><td>50 Ω or 1M Ω, software selectable</td><td></td></tr><tr><td rowspan="3">Offset error</td><td>±0.5 mV</td><td>±0.5V, ±1V</td></tr><tr><td>±4 mV</td><td>±5V</td></tr><tr><td>±10 mV</td><td>±10V</td></tr><tr><td rowspan="5">Gain error</td><td colspan="2">50Ω</td></tr><tr><td>±1%</td><td>for all ranges</td></tr><tr><td colspan="2">1MΩ</td></tr><tr><td>±0.5%</td><td>for other ranges</td></tr><tr><td>±1%</td><td>±10V</td></tr></table>

<table><tr><td>Item</td><td>Detail</td><td>Comments</td></tr><tr><td rowspan="4">System Noise (RMS)</td><td>150 μV</td><td>±0.5V</td></tr><tr><td>300 μV</td><td>±1.0V</td></tr><tr><td>1.5 mV</td><td>±5V</td></tr><tr><td>2.5 mV</td><td>±10V</td></tr><tr><td colspan="3">AC Dynamic Performance (10MHz, -1dBFS input signal)</td></tr><tr><td colspan="3">50Ω with filter OFF</td></tr><tr><td>SNR</td><td>64dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>THD</td><td>-74dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>SFDR</td><td>76dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td colspan="3">1MΩ with filter OFF</td></tr><tr><td>SNR</td><td>64dB</td><td>±0.5V, ±1V, ±5V, ±10V</td></tr><tr><td rowspan="3">THD</td><td>-71dB</td><td>±10V</td></tr><tr><td>-73dB</td><td>±5V</td></tr><tr><td>-75dB</td><td>±0.5V, ±1V</td></tr><tr><td rowspan="3">SFDR</td><td>72dB</td><td>±10V</td></tr><tr><td>74dB</td><td>±5V</td></tr><tr><td>76dB</td><td>±0.5V, ±1V</td></tr><tr><td colspan="3">50Ω with filter ON</td></tr><tr><td>SNR</td><td>65dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>THD</td><td>-93dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>SFDR</td><td>78dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td colspan="3">1MΩ with filter ON</td></tr><tr><td>SNR</td><td>65dB</td><td>±0.5V, ±1V, ±5V, ±10V</td></tr><tr><td rowspan="3">THD</td><td rowspan="3">-93dB</td><td>±10V</td></tr><tr><td>±5V</td></tr><tr><td>±0.5V, ±1V</td></tr><tr><td rowspan="3">SFDR</td><td rowspan="3">78dB</td><td>±10V</td></tr><tr><td>±5V</td></tr><tr><td>±0.5V, ±1V</td></tr><tr><td rowspan="2">Crosstalk</td><td>-80dB</td><td>±0.5V</td></tr><tr><td>-90dB</td><td>±1V, ±5V, ±10V</td></tr></table>

Table 1-1: Channel Characteristics

CH0 Bandwidth 50Ω
![| Hz       | ±5V   | ±1V   | ±0.5V |\n| -------- | ----- | ----- | ----- |\n| 10^3     | 0.0   | 0.0   | 0.0   |\n| 10^4     | 0.0   | 0.0   | 0.0   |\n| 10^5     | 0.0   | 0.0   | 0.0   |\n| 10^6     | 0.0   | 0.0   | 0.0   |\n| 10^7     | -1.0  | -1.2  | -1.5  |\n| 10^8     | -6.5  | -5.0  | -6.0  |](.pcie-9814-50-11256-1000-200-en/d7f1b62c640a810e5de8d87bd236fda4b81f31973e9824eaed7626c27622d0ee.jpg)

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

1.3.2 Timebase

<table><tr><td>Sample Clock</td><td>Detail</td><td>Comment</td></tr><tr><td rowspan="2">Timebase options</td><td>Internal : onboard crystal oscillator</td><td></td></tr><tr><td>External : CLK IN (front panel)</td><td></td></tr><tr><td rowspan="2">Sampling clock frequency</td><td>Internal : 80MHz</td><td>1.22kS/s to 80MS/s</td></tr><tr><td>External : 20MHz to 80MHz (CLK IN)</td><td></td></tr><tr><td>Timebase accuracy</td><td>&lt; ± 25ppm</td><td></td></tr><tr><td>External reference clock source</td><td>SDI0 (supported by PCI-9814P only)</td><td></td></tr><tr><td>External reference clock</td><td>10MHz</td><td></td></tr><tr><td>External reference clock input range</td><td>3.3V to 5V TTL</td><td>DC compliant</td></tr><tr><td>External sampling clock input range</td><td>1Vpp to 5Vpp</td><td>AC / DC compliant</td></tr></table>

# 1.3.3 Triggers

<table><tr><td colspan="2">Trigger Source &amp; Mode</td></tr><tr><td>Trigger source</td><td>Software, external digital trigger, analog trigger, and SSI (system synchronized interface)</td></tr><tr><td>Trigger mode</td><td>Post trigger, delay trigger, pre-trigger, or middle trigger, re-trigger for post trigger and delay trigger modes</td></tr></table>

<table><tr><td colspan="2">Digital Trigger Input</td></tr><tr><td>Sources</td><td>Front panel SMB connector</td></tr><tr><td>Compatibility</td><td>3.3 V TTL, 5 V tolerant</td></tr><tr><td>Input high threshold</td><td>2.0 V</td></tr><tr><td>Input low threshold (VIL)</td><td>0.8 V</td></tr><tr><td>Maximum input overload</td><td>-0.5 V to +5.5 V</td></tr><tr><td>Trigger polarity</td><td>Rising or falling edge</td></tr><tr><td>Pulse width</td><td>20 ns minimum</td></tr></table>

# 1.3.4 General Specifications

<table><tr><td colspan="2">Specifications</td></tr><tr><td>Dimensions</td><td>167.64 W x 106.68 H mm (6.53 x 4.16 in)</td></tr><tr><td>Bus interface</td><td>PCI Express Gen 1 x 4</td></tr><tr><td>Operating</td><td>Temperature: 0°C - 50°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td>Storage</td><td>Temperature: -20°C - +80°CRelative humidity: 5% - 95%, non-condensing</td></tr></table>

<table><tr><td colspan="2">Calibration</td></tr><tr><td>Onboard reference</td><td>+1.8V, +0.9V, and +0.45V</td></tr><tr><td>Temperature coefficient</td><td>1.0 ppm/°C</td></tr><tr><td>Warm-up time</td><td>15 minutes</td></tr></table>

<table><tr><td colspan="5">Power Consumption</td></tr><tr><td></td><td colspan="2">PCIe-9814</td><td colspan="2">PCIe-9814P</td></tr><tr><td>Power Rail</td><td>Standby current (mA)</td><td>Full load (mA)</td><td>Standby current (mA)</td><td>Full load (mA)</td></tr><tr><td>3.3V</td><td>20</td><td>20</td><td>20</td><td>20</td></tr><tr><td>12V</td><td>425</td><td>505</td><td>655</td><td>715</td></tr><tr><td>Total RMS Power (W)</td><td>5.116</td><td>6.126</td><td>7.926</td><td>8.646</td></tr></table>

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW $^{®}$ .

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license.

# 1.4.1 WD-DASK

WD-DASK includes device drivers and DLL for Windows XP/7/8. DLL is binary compatible across Windows XP/7/8. This means all applications developed with WD-DASK are compatible with these Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The WD-DASK user and function reference manuals are on the ADLINK All-in-One CD.

# 1.4.2 LabVIEW Support

For customers who want to write their own programs in LabVIEW, a LabVIEW library toolkit, DAQPilot, is provided, with a newly architected DAQLite package to support PCIe-9814 card use.

# 1.5 Device Layout and I/O Array

![The image displays a graphic icon of a piece of paper with a folded top-right corner and faint horizontal lines running across it. A large, bold red checkmark is superimposed over the center of the document.](.pcie-9814-50-11256-1000-200-en/29190825903ff22e7787d3e953d7b4e2fbc1d3f9c70de367bcd5904c7e7aacd5.jpg)
NOTE:

All dimensions are in mm

![ADLINK\n100.36\n59.05\n169.55\n98.4](.pcie-9814-50-11256-1000-200-en/3703a09eea51af58843fd5f3fbf6361ceb53596bc35466cd2c9fe27110fc0c54.jpg)

Figure 1-2: PCIe-9814 Schematic

The PCIe-9814 I/O array is labeled to indicate connectivity, as shown.

![CH0\nCH1\nCH2\nCH3\nCLK\nTRG\nSD10\nSD11\nSD12](.pcie-9814-50-11256-1000-200-en/3d27abfd8e5d89ff3f28f48e4234ad401c66dac8fa5e5b864f23de7d24a2385e.jpg)

Figure 1-3: PCIe-9814 I/O Array

All I/O connectors are SMB Snap-on type.

<table><tr><td>Input</td><td>Faceplate Label</td><td>Remark</td></tr><tr><td>Analog</td><td>CH0</td><td rowspan="4">Analog Input Channel</td></tr><tr><td>Analog</td><td>CH1</td></tr><tr><td>Analog</td><td>CH2</td></tr><tr><td>Analog</td><td>CH3</td></tr><tr><td>Ext. Clock</td><td>CLK</td><td>Input for external sample clock to digitizer</td></tr><tr><td>Ext. Digital Trigger</td><td>TRG</td><td>External digital trigger input, receiving trigger signal from external instrument and initiating acquisition</td></tr><tr><td>Synced Digital</td><td>SDI0</td><td rowspan="3">3 SDI bits (bit 0:2) and ADC data are combined into one register and transferred to host PC by DMA.Refer to Chapter 3 for detailed data format.Optional: For PCIe-9814P (with PLL module), SDI0 can be used to receive an external reference 10MHz to generate ADC timebase.Please see Section 3.5.2 External Reference Clock (PCIe-9814P only) for more information.</td></tr><tr><td>Synced Digital</td><td>SDI1</td></tr><tr><td>Synced Digital</td><td>SDI2</td></tr></table>

Table 1-2: PCIe-9814 I/O Array Legend

# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PCIe-9814.

![An icon depicting a white piece of paper with horizontal lines and a large red checkmark overlaid on it.](.pcie-9814-50-11256-1000-200-en/036a34ba73c0c75be2b5d7e3a5e44cc71bc3ae2e716992f7bc3605bad2289513.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

▶ Phillips (cross-head) screwdriver
▶ Flat-head screwdriver
Anti-static wrist strap
▶ Antistatic mat

ADLINK PCIe-9814 DAQ modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation.

![A vertical sign features a yellow triangle with a black border containing a large black exclamation point in the center. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.pcie-9814-50-11256-1000-200-en/bcfbf7051674fec8774828c28a718d674b1ee3ae968cf70ff0a5871c865f2c3e.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

▶ Package Contents
▶ PCIe-9814 digitizer
▶ ADLINK All-in-one compact disc
▶ PCIe-9814 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

![The image displays a triangular warning sign with a red border. Inside the triangle is a large exclamation point on a dark red background. Below the triangle, the word 'WARNING' appears in black capital letters.](.pcie-9814-50-11256-1000-200-en/a77ea932414e8fe83fd84d58ea22be2d3f132885b6f32ed7eeffa30cf4d2bfc5.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Installing the Module

1. Turn off the computer.
2. Remove the top cover.
3. Select an available PCI express x4 slot and remove the bracket-retaining screw and the bracket cover.
4. Line up the PCI express digitizer with the PCI express slot on the back panel. Slowly push down on the top of the PCI express digitizer until its card-edge connector is resting on the slot receptacle.
5. Install the bracket-retaining screw to secure the PCI express digitizer to the back panel rail.
6. Replace the computer cover.

# 3 Operations

This chapter contains information regarding analog input, triggering and timing for the PCIe-9814.

3.1 Functional Block Diagram
![Based on the provided block diagram, here is the accurate and concise description of the blocks and their connections:\n\n**Blocks:**\n*   **Inputs:** CH0, CH1, CH2, CH3, CLK IN, TRG IN, SDI0, SDI1, SDI2.\n*   **Processing/Interface Blocks:** Analog Front-End, Calibration, 12 Bit ADC, Clock Distribution, Buffer, FPGA, SSI.\n*   **External Interface:** PCIe Interface.\n\n**Connections:**\n*   **Analog Path:** Inputs **CH0**, **CH1**, **CH2**, and **CH3** connect to the **Analog Front-End**. The **Analog Front-End** outputs to the **12 Bit ADC** and connects to a **Calibration** block below it.\n*   **Clock Path:** **CLK IN** connects to the **Clock Distribution** block. A small circle with a sine wave symbol also connects to the **Clock Distribution** block. The **Clock Distribution** block outputs to the **12 Bit ADC**.\n*   **Digital Input Path:** Inputs **TRG IN**, **SDI0**, **SDI1**, and **SDI2** connect to the **Buffer**. The **Buffer** outputs a connection labeled with a slash and '4' to the **FPGA**.\n*   **FPGA Connections:** The **FPGA** receives inputs from the **12 Bit ADC** and the **Buffer**. It connects bidirectionally to the **SSI** block above it and the **PCIe Interface** arrow to its right.](.pcie-9814-50-11256-1000-200-en/675db625822bb9f263af6d4e49e28d3c9689121bb1e262c5c67672e6e6e1f5f8.jpg)

# 3.2 Analog Input Channel

3.2.1 Analog Input Front-End Configuration
![Based on the provided block diagram, here is the accurate description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **Calibration Source**: A label at the top left pointing to an input connector.\n*   **50Ω/ Hi-Z**: A block containing a resistor symbol. The text is split across two lines: '50Ω/' and 'Hi-Z'.\n*   **Attenuator**: A block containing a resistor symbol.\n*   **High Impe dance Buffe r**: A triangular block (amplifier symbol). The text is split across two lines: 'High Impe dance' and 'Buffe r'.\n*   **ADC D river**: A triangular block (amplifier symbol). The text is split across two lines: 'ADC D river'.\n*   **Anti-aliasing Filter**: A rectangular block.\n*   **12-bit ADC**: A rectangular block at the end of the chain. The text is at the top. Inside the block, there are small triangles and the number '0'.\n*   **12**: A label on the output line (bus) to the right of the ADC.\n\n**Connections:**\n1.  **Calibration Source** connects to a gray switch block (which also receives an input from the far left).\n2.  The switch block connects to the **50Ω/ Hi-Z** block.\n3.  **50Ω/ Hi-Z** connects to the **Attenuator** block.\n4.  **Attenuator** connects to the **High Impe dance Buffe r** block.\n5.  **High Impe dance Buffe r** connects to the **ADC D river** block.\n6.  **ADC D river** connects to the **Anti-aliasing Filter** block.\n7.  **Anti-aliasing Filter** connects to the **12-bit ADC** block.\n8.  The **12-bit ADC** block outputs a signal to the bus labeled **12**.](.pcie-9814-50-11256-1000-200-en/df29d5e9c377f97eeb3c2b0cb9dc684d0d6c771d8f6099bdf29fdc2d3ffc5c6c.jpg)

Figure 3-1: Analog Input Architecture

# Input Configuration

The input channel terminates with equivalent 50Ω or 1MΩ input impedance (selected by software). The 12-bit ADC provides not only accurate DC performance but also high signal-to-noise ratio, and high spurious-free dynamic range in AC performance. The ADC transfers data to system memory via the high speed PCI Express Gen 1 X 4 interface.

For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI.

# 3.2.2 Input Range and Data Format

Data format of the PCIe-9814 is 2's complement. The ADC data of PCIe-9814 is on the 12 MSB of the 16-bit A/D data. D2 to D0 is SDI2 to SDI0, with D3 disregarded. A/D data structure is as follows.

<table><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>....</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td colspan="9">D15 to D4 bits represent the data from ADC (2&#x27;s complement)D2 is SDI2, D1 SDI1, D0 SDI0, and D3 is disregarded</td></tr></table>

Table 3-1: Input Range and Data Format

<table><tr><td>Description</td><td>Full scale range</td><td>Least significant bit</td><td>FSR-1LSB</td><td>-FSR</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>±10V</td><td>4.88mV</td><td>9.9512V</td><td>-10V</td></tr><tr><td>±5V</td><td>2.44mV</td><td>4.99756V</td><td>-5V</td></tr><tr><td>±1V</td><td>0.488mV</td><td>0.99512V</td><td>-1V</td></tr><tr><td>±0.5V</td><td>0.244mV</td><td>0.499756V</td><td>-0.5V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FF0</td><td>8000</td></tr><tr><td>Comment</td><td colspan="4">SDI bit is assumed to be 0</td></tr></table>

Table 3-2: Input Range FSR and -FSR Values

<table><tr><td>Description</td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale -1LSB</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>4.88mV</td><td>0V</td><td>-4.88mV</td></tr><tr><td>2.44mV</td><td>0V</td><td>-2.44mV</td></tr><tr><td>0.488mV</td><td>0V</td><td>-0.488mV</td></tr><tr><td>0.244mV</td><td>0V</td><td>-0.244mV</td></tr><tr><td>Digital Code</td><td>0001</td><td>0000</td><td>FFF0</td></tr><tr><td>Comment</td><td colspan="3">SDI bit is assumed to be 0</td></tr></table>

Table 3-3: Input Range Midscale Values

# 3.2.3 DMA Data Transfer

The PCIe-9814, a PCIe Gen 1 X 4 device, is equipped with a 200MS/s high sampling rate ADC, generating a 640 MByte/second rate.

To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list so users can transfer large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. Figure 3-2 illustrates a linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space, but the subsequent descriptor address must be less than 4GB.

![The diagram illustrates a data flow involving five blocks arranged vertically and horizontally.\n\n**Labeled Blocks:**\n\n*   **Bottom Block:** 'Local Memory ( FIFO)'\n*   **Middle Block:** 'PCI Express Bus'\n*   **Top Left Block:** Contains four rows labeled:\n    *   'First PCI Address'\n    *   'First Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n*   **Top Middle Block:** Contains four rows labeled:\n    *   'PCI Address'\n    *   'Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n*   **Top Right Block:** Contains four rows labeled:\n    *   'PCI Address'\n    *   'Dual Address'\n    *   'Transfer Size'\n    *   'Next Descriptor'\n\n**Connections:**\n\n1.  An upward arrow connects 'Local Memory ( FIFO)' to 'PCI Express Bus'.\n2.  An upward arrow connects 'PCI Express Bus' to the bottom of the Top Middle Block (specifically pointing towards the 'Next Descriptor' row).\n3.  A rightward arrow connects the Top Left Block to the Top Middle Block.\n4.  A rightward arrow connects the Top Middle Block to the Top Right Block.](.pcie-9814-50-11256-1000-200-en/db2012a7c6865a8f6173a869b040ba12cfd0d565d9201df7c96ecd486d522956.jpg)

Figure 3-2: Linked List of PCI Address DMA Descriptors

# 3.2.4 Synchronous Digital Input

The PCIe-9814 has three synchronous digital input channels, SDI0, SDI1 and SDI1. These three digital input lines can be sampled synchronously with the Timebase clock for mixed signal applications. Thus the data transfer can reach 80 Mbit/s when using internal 80 MS/s Timebase clock. These three digital input lines are combined with ADC data and located in 3 LSB when SDI function is enabled, as shown.

![The diagram illustrates a digital data acquisition and synchronization circuit.\n\n**Input and Latching Stage (Top Left):**\n*   Three inputs labeled **SDI0**, **SDI1**, and **SDI2** (each accompanied by a square/triangle wave icon) connect to triangular buffers.\n*   The outputs of these buffers connect to the **D** inputs of three vertically stacked **D Flip Flop** blocks. Each block is labeled 'D Flip Flop' and has **D** and **CLK** terminals.\n*   The **CLK** terminals of all three **D Flip Flop** blocks are connected to a common vertical clock line.\n\n**Analog-to-Digital Conversion Stage (Bottom Left):**\n*   An **Analog Input** (sine wave icon) connects to a buffer labeled **AFE**.\n*   The output of the **AFE** connects to the input of an **ADC** (Analog-to-Digital Converter) block.\n*   The **ADC** block has a **CLK** input and a **Data** output.\n*   The common clock line from the flip flops connects to the **CLK** input of the **ADC**. A square wave icon labeled **Timebase** is shown near this connection.\n\n**Output Data Block (Right):**\n*   A rectangular block represents the output data structure, divided into sections:\n    *   The **Data** output from the **ADC** connects to the leftmost section labeled **ADC Data** (under **Bit 15**).\n    *   The next section is labeled **X** (under **Bit 3**).\n    *   The output line from the bottom **D Flip Flop** (associated with **SDI2**) connects to the section labeled **SDI2** (under **Bit 2**).\n    *   The output line from the middle **D Flip Flop** (associated with **SDI1**) connects to the section labeled **SDI1** (under **Bit 1**).\n    *   The output line from the top **D Flip Flop** (associated with **SDI0**) connects to the rightmost section labeled **SDI0** (under **Bit 0**).](.pcie-9814-50-11256-1000-200-en/9d8692d51dcdad7f6d47f38e58a833cc1fdab329bcd6a6f800e0fbe1c92c8868.jpg)

Figure 3-3: Synchronous Digital Input Operations

# 3.3 Trigger Source and Trigger Modes

This section details PCIe-9814 triggering operations.

![Based on the provided image, here is the description of the flowchart:\n\n**Labeled Blocks and Inputs:**\n*   **Software Trigger**: An input arrow pointing to the top of a trapezoidal block.\n*   **Digital Trigger Input**: An input arrow (originating from a connector icon) pointing to the middle of the trapezoidal block.\n*   **SSI Trigger**: A label for the bottom input of the trapezoidal block.\n*   **Trigger Decision**: A square block receiving the output from the trapezoidal block.\n*   **ISS**: A vertical, bidirectional arrow (double-headed) on the right side.\n\n**Connections and Flow:**\n1.  **Inputs to Trapezoid**: 'Software Trigger', 'Digital Trigger Input', and the 'SSI Trigger' input all feed into the left side of a trapezoidal block (likely a multiplexer or selector).\n2.  **Trapezoid to Trigger Decision**: The output of the trapezoidal block points to the right, entering the 'Trigger Decision' block.\n3.  **Trigger Decision Outputs**:\n    *   One arrow points to the right labeled **'To Internal FPGA'**.\n    *   Another arrow points downward from 'Trigger Decision' and splits.\n4.  **ISS Connection**:\n    *   One branch of the downward path goes right, labeled **'(Master =) Slave)'**, and points into the 'ISS' block.\n    *   A feedback line originates from the 'ISS' block, labeled **'(Master (= Slave)'**. This line travels to the left and connects to the bottom input of the trapezoidal block (labeled 'SSI Trigger').](.pcie-9814-50-11256-1000-200-en/d873a1651d112e16824b7d8325f55775ba88b4f68db7e508d9865e74839fe851.jpg)

Figure 3-4: Trigger Architecture

The PCIe-9814 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-9814 supports internal software trigger, external digital trigger, and analog trigger.

# 3.3.1 Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

# 3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL rising edge or falling edge is detected at the SMB connector TRG IN on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 20 ns.

![The image displays two side-by-side diagrams illustrating signal pulses and trigger events.\n\n**Left Side:**\n*   **Top Text:** 'Pulse Width ) 20ns'\n*   **Graphic:** A horizontal line with arrows pointing left and right indicating duration. Below this is a square wave pulse with an arrow pointing upward on the rising edge.\n*   **Bottom Text:** 'Rising Edge Trigger Event'\n\n**Right Side:**\n*   **Top Text:** 'Pulse Width ) 20ns'\n*   **Graphic:** A horizontal line with arrows pointing left and right indicating duration. Below this is a square wave pulse with an arrow pointing downward on the falling edge.\n*   **Bottom Text:** 'Falling Edge Trigger Event'](.pcie-9814-50-11256-1000-200-en/6e9787217b3e247dbd16f45bd6327174d50894190f8fd1afff0de3398ac1693c.jpg)
Figure 3-5: External Digital Trigger

# 3.3.3 Analog Trigger

An analog trigger is generated when AI input signal level is detected at the SMB connectors CH0 to CH3 (selected by software). The trigger level is also selected by software.

# 3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input function.

# 3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PCIe-9814 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. The acquisition stops once the total data amount reaches a predefined value.

![This diagram illustrates a timing sequence for data acquisition. It consists of three horizontal signal lines aligned against a vertical timeline:\n\n1.  **Timeline:** A horizontal arrow pointing to the right is labeled '**Time**'. Three downward arrows point to specific moments on this line:\n    *   '**Operation start**'\n    *   '**Trigger Event Occurs**' / '**Acquisition start**' (stacked text)\n    *   '**Acquisition stop**'\n\n2.  **Trigger Signal:** A line labeled '**Trigger**' displays a single square pulse that aligns vertically with the 'Trigger Event Occurs' marker on the timeline.\n\n3.  **Data Signal:** A line labeled '**Data**' contains a long rectangular block labeled '**N samples**' which begins following the trigger pulse and extends to the right, representing the duration of data collection.](.pcie-9814-50-11256-1000-200-en/2a03badafb6ffd0230c14870ba6ee2c9a93028ff76c2b5823f3131db4de047cf.jpg)

Figure 3-6: Post-Trigger Acquisition

# 3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When PCIe-9814 receives a trigger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X ( $2^{16}$ ), and the minimum is the Timebase period.

![The diagram illustrates a timing sequence with a horizontal axis labeled 'Time'. Above this axis, vertical arrows mark four chronological points: 'Operation start', 'Trigger Event Occurs', 'Acquisition start', and 'Acquisition stop'. A horizontal arrow labeled 'Delay Time' connects the vertical markers for 'Trigger Event Occurs' and 'Acquisition start'.\n\nBelow the timeline, two signal traces are depicted:\n*   A waveform labeled 'Trigger' shows a single square pulse aligned with 'Trigger Event Occurs'.\n*   A waveform labeled 'Data' shows a rectangular segment labeled 'N samples' that spans the time between 'Acquisition start' and 'Acquisition stop'.](.pcie-9814-50-11256-1000-200-en/68b8d7c23d459cc75503d95b348b99ef182c4d03a9fed2ff817007cfbac26787.jpg)

Figure 3-7: Delayed Trigger Mode Acquisition

# 3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.

![This image is a timing diagram illustrating a data acquisition process with pre-trigger buffering. It is organized into three horizontal tracks aligned by time (left to right).\n\n**Top Track (Timeline & Events):**\n*   A horizontal axis labeled **'Time'** points to the right.\n*   Three downward arrows indicate specific events:\n    1.  **Left:** Points to the start of the timeline. Text above:\n        *   'Operation start'\n        *   'Acquisition start'\n    2.  **Middle (dotted arrow):** Points to the timeline. Text above:\n        *   'Trigger signals occuring before the specified amount of data has been acquired are ignored'\n    3.  **Right:** Points further down the timeline. Text above:\n        *   'Trigger Event Occurs'\n        *   'Acquisition stop'\n        *   'Data transfer to system begins'\n\n**Middle Track (Trigger Signal):**\n*   Labeled **'Trigger'** on the left.\n*   Displays a signal waveform with two square-wave pulses.\n    *   The **first pulse** aligns vertically with the 'Trigger signals occuring...' text.\n    *   The **second pulse** aligns vertically with the 'Trigger Event Occurs...' text.\n\n**Bottom Track (Data Buffer):**\n*   Labeled **'Data'** on the left.\n*   Shows a long bar starting at the 'Operation start' mark, divided into two sections:\n    1.  **Left Section:** A rectangle filled with diagonal hatching.\n    2.  **Right Section:** A white rectangle adjacent to the hatched section, containing the text **'N samples'**.\n*   Below the bar, there is a dimension line spanning the hatched section.\n*   Text below the dimension line reads: **'X samples have been acquired before trigger occurs, where X(N'**\n\n**Connections & Logic:**\n*   The **'Operation start'** aligns with the beginning of the **Data** bar.\n*   The hatched section of the Data bar represents the pre-trigger buffer. The first **Trigger** pulse occurs within this section, corresponding to the text stating those signals are ignored.\n*   The second **Trigger** pulse ('Trigger Event Occurs') aligns with the end of the hatched section.\n*   The bottom text clarifies that the hatched section contains **'X samples'** and that this amount is less than the total buffer size **'N'** (implied by the label 'N samples' and the condition X(N).](.pcie-9814-50-11256-1000-200-en/370f063e0c79b5913b72c4f6d96fca770b70e1292beea3d5c4aa7943fd89aa25.jpg)

Figure 3-8: Pre-Trigger Mode Acquisition

# 3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to be collected set individually (M and N samples), as follows

![The image displays a timeline diagram consisting of three parallel tracks illustrating the relationship between time, triggers, and data acquisition.\n\n**Top Track (Timeline):**\nA horizontal line labeled 'Time' at the far right with an arrow pointing to the right. Three vertical arrows point downward to specific points on this line:\n*   **Left Arrow:** Labeled 'Operation start' and 'Acquisition start'.\n*   **Middle Arrow:** Labeled 'Trigger event occurs'.\n*   **Right Arrow:** Labeled 'Acquisition stop' and 'Data transfer to system begins'.\n\n**Middle Track (Trigger):**\nA horizontal line labeled 'Trigger' on the left. It features a rectangular pulse that aligns vertically with the 'Trigger event occurs' arrow above it.\n\n**Bottom Track (Data):**\nA horizontal line labeled 'Data' on the left. It features a long rectangular block divided into three distinct sections:\n*   **Left Section:** A block filled with diagonal hatching. It spans the time interval between 'Operation start' and the trigger event.\n*   **Middle Section:** A block labeled 'M samples'. It aligns vertically with the trigger pulse.\n*   **Right Section:** A block labeled 'N samples'. It spans the time interval following the trigger event up to the 'Acquisition stop'.](.pcie-9814-50-11256-1000-200-en/fbb4b3fa5a7d04720e4d0d5d63bc4d971453d28b533fb7d647f52dc4c4d488c3.jpg)

Figure 3-9: Middle Trigger Mode Acquisition

# 3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single acquisition. Re-Trigger mode can also be set to automatically acquire R traces, containing N\*R samples/channel of data, without additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed-Trigger modes, with different limitations on the spacing between trigger events in each mode. Trigger events arriving too close to the previous instance will be ignored by the digitizer.

In Post-Trigger mode, the minimum spacing between trigger events is N+1
▶ In Delayed-Trigger mode, the minimum spacing between trigger events is $(N+D)+1$ , where D is the number of the delayed setting

![This diagram is a timing chart showing the synchronization between time, trigger signals, and data collection.\n\n**Labeled Blocks and Annotations:**\n*   **Top Axis:** A horizontal line with an arrow pointing right, labeled **'Time'** at the end. Above this line are three vertical arrows pointing to specific moments, labeled:\n    *   **'Operation start'**\n    *   **'1st Trigger Event Occurs'**\n    *   **'2nd Trigger Event Occurs'**\n*   **Middle Track:** Labeled **'Trigger'** on the left. It displays a signal line with two square pulses.\n*   **Bottom Track:** Labeled **'Data'** on the left. It features two rectangular blocks connected by a line. Both blocks are labeled **'N samples'**.\n\n**Connections and Alignment:**\n*   The first pulse on the **'Trigger'** line aligns vertically with the **'1st Trigger Event Occurs'** annotation and corresponds to the start of the first **'N samples'** block.\n*   The second pulse on the **'Trigger'** line aligns vertically with the **'2nd Trigger Event Occurs'** annotation and corresponds to the start of the second **'N samples'** block.\n*   The **'Operation start'** annotation aligns with the beginning of the timeline, preceding the first trigger event.](.pcie-9814-50-11256-1000-200-en/694a19cc9d031722335a47b0cdc66b2b40bbb1a996f186dfe59590fec3623738.jpg)

Figure 3-10: Re-Trigger Mode Acquisition

# 3.5 Timebase

![This diagram illustrates a signal selection path leading to an Analog-to-Digital Converter (ADC).\n\n**Labeled Blocks and Components:**\n*   **CLK IN**: Represented by a cylindrical component symbol at the top left.\n*   **80M Xtal**: Represented by a circular component symbol with a sine wave inside, located below 'CLK IN'.\n*   **SDI0**: Represented by a cylindrical component symbol at the bottom left.\n*   **Synthesizer Board**: A rectangular block located to the right of 'SDI0'.\n*   **Switch Box**: An unlabeled rectangular box containing a switch symbol (a single pole with a toggle arm) on the right side.\n*   **To ADC**: Text label with an arrow pointing to the right, indicating the final output.\n\n**Connections:**\n*   A line connects **CLK IN** to the top input terminal of the **Switch Box**.\n*   A line connects **80M Xtal** to the middle input terminal of the **Switch Box**.\n*   A line connects **SDI0** to the left side of the **Synthesizer Board**.\n*   A line connects the right side of the **Synthesizer Board** to the bottom input terminal of the **Switch Box**.\n*   Inside the **Switch Box**, a switch symbol indicates signal selection (currently pointing toward the top input).\n*   A single output line exits the right side of the **Switch Box** and is labeled **To ADC**.](.pcie-9814-50-11256-1000-200-en/456f8272852f272121e939016a32af774b89819569efa30c74744306435ee2b2.jpg)

Figure 3-11: PCIe-9814 Clock Architecture

# 3.5.1 Internal Sampling Clock

The PCIe-9814 internal 80MHz crystal oscillator acts as a sampling clock for ADC.

# 3.5.2 External Reference Clock (PCIe-9814P only)

The PCIe-9814P's onboard PLL module allows SDI0 to act as an external reference clock. Synthesizer input switches to the clock source at SMB connector SDI0, generating precisely 80MHz clock for ADC.

# 3.5.3 External Sampling Clock

The PCIe-9814 can further choose an external clock source as ADC sampling clock. When an external sampling clock is selected, the ADC sampling frequency switches to the clock source at SMB Connector CLK IN, and clock source frequency is available from 20MHz to 80MHz. Be advised that if the frequency of the external sample clock is changed, the LVDS timebase requires recalibration.

To do so, call WD-DASK function: WD\_AI\_Config().

For more information, refer to the WD-DASK Function Library Reference.

# 3.6 ADC Timing Control

# 3.6.1 Timebase Architecture

![Based on the provided diagram, here is the accurate and concise description:\n\n**Labeled Blocks:**\n*   ADC\n*   X6 Multiplier PLL\n*   FPGA (indicated by the dashed box and label below)\n\n**Connections:**\n*   An arrow originates from 'Onboard 80MHz Oscillator' and points to the 'ADC' block.\n*   An arrow exits the 'ADC' block, labeled 'ADC Output 80MHz'.\n*   This line enters the 'FPGA' area and splits into two paths:\n    *   **Top Path:** Enters the 'X6 Multiplier PLL' block. The output from this block is labeled '480MHz' and points to the text 'For ADC Data Bus'.\n    *   **Bottom Path:** Bypasses the multiplier block. The output is labeled '80MHz' and points to the text 'For ADC State machine'.](.pcie-9814-50-11256-1000-200-en/2f5e776959a1742c75f2b510b24c97b75eb41ba8f9c82fdcad9b529b6ac5fdfa.jpg)

Figure 3-12: PCIe-9814 Timebase Architecture

# 3.6.2 Basic Acquisition Timing

The PCIe-9814 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger. The Timebase is a clock provided to the ADC and acquisition engine for essential timing. The Timebase is from an onboard synthesizer. To achieve different sampling rates, a scan interval counter is used.

Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC, and stores the sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately through the DMA engine. The sampled data is generated continuously at the rising edge of Timebase according to the scan interval counter setting. When sampled data reaches a specified value, in this example 256, acquisition ends.

![The diagram displays five horizontal timing tracks labeled on the left: **Analog signal**, **TIMEBASE**, **Trigger**, **Acquisition In Progress**, and **DATA**.\n\nThe **DATA** track features a sequence of rectangular blocks labeled **D1**, **D2**, **D3**, **D4**, followed by a gap represented by circles, and ending with blocks labeled **D253**, **D254**, **D255**, **D256**.\n\nAn arrow connects the text '**Acquisition initiates following this clock edge**' to the rising edge of the **TIMEBASE** signal.\n\nThe footer text reads: '**Trigger mode = post-trigger, DataCnt = 256, ScanInterv = 1**'.](.pcie-9814-50-11256-1000-200-en/2e07fe9d658be1625f9a44e53fad40c1b5149d7ad40c31437d98b2390048e33c.jpg)

Figure 3-13: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 80MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 80MS/s / 2 = 40MS/s. If as 3, the equivalent sampling rate is 80MS/s / 3 = 26.66MS/s, and vice versa. The scan interval counter is 16 bits in width, therefore the lowest sampling rate is 1.221kS/s (80MS/s / 65535).

![This diagram illustrates timing relationships between a trigger signal, a clock, and data acquisition intervals.\n\n**Labels and Blocks:**\n*   **Trigger:** A waveform signal at the top.\n*   **TIMEBASE:** A continuous square wave clock signal.\n*   **DATA:** A label grouping three rows of data sequences.\n    *   **ScanIntrv = 1:** A sequence of contiguous blocks labeled **D1**, **D2**, **D3**, **D4**, **D5**, **D6**, **D7**, **D8**, **D9**, **D10**.\n    *   **ScanIntrv = 2:** A sequence of spaced blocks labeled **D1**, **D2**, **D3**, **D4**, **D5**, **D6**.\n    *   **ScanIntrv = 3:** A sequence of widely spaced blocks labeled **D1**, **D2**, **D3**, **D4**.\n*   **Acquisition In Progress:** A signal line at the bottom.\n*   **Annotation Text:** 'Acquisition is initiated following this clock edge'.\n\n**Connections and Layout:**\n*   The **TIMEBASE** clock pulses align vertically with the data blocks.\n*   In the **ScanIntrv = 1** row, the blocks D1-D10 are connected in a continuous chain, appearing to correspond to every clock edge.\n*   In the **ScanIntrv = 2** row, the blocks are spaced out, skipping one clock cycle between them (e.g., D1 is at the first edge, D2 is at the third).\n*   In the **ScanIntrv = 3** row, the blocks are spaced even further apart, skipping two clock cycles between them.\n*   An arrow from the text 'Acquisition is initiated following this clock edge' points to the rising edge of the first pulse on the **TIMEBASE** line, which aligns with the start of the 'Acquisition In Progress' signal.](.pcie-9814-50-11256-1000-200-en/0ef67502618d2630d90a1dadd4b91d9d2a6cc672ed0e055fe1d057086f4f307f.jpg)

Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval Counter

<table><tr><td>Counter Name</td><td>Length</td><td>Valid Value</td><td>Description</td></tr><tr><td>ScanIntrv</td><td>16-bit</td><td>1-65535</td><td>Timebase divider to achieve equivalent sampling rate of the digitizer, where Sampling rate = Timebase / ScanIntrv</td></tr><tr><td>DataCnt</td><td>31-bit</td><td>1-2147483647</td><td>Specifies the amount of data to be acquired:1 - 2147483648 for pre-trig or mid-trig mode operation</td></tr><tr><td>trigDelayTicks</td><td>16-bit</td><td>1 -65535</td><td>Indicates time between a trigger event and commencement of acquisition. The unit of a delay count is the period of the Timebase.</td></tr><tr><td>ReTrgCnt</td><td>31-bit</td><td>1-2147483647</td><td>Enables re-trigger to accept multiple triggers.1 - 2147483647 for normal operationSee Section 3.4.5: Acquisition with Re-Triggering</td></tr></table>

Table 3-4: Counter Parameters and Description

# 3.7 Synchronizing Multiple Modules

The PCIe-9814 provides a dedicated connector as system synchronization interface, enabling multiple module synchronization. As shown, bi-directional SSI I/Os provides a flexible connection between modules, allowing one SSI master PCIe-9814 to output SSI signals to other slave modules. For more accurate synchronization between modules, external sampling clock or external reference clock should be applied.

The table summarizes SSI functionalities.

![The image displays an icon of a white document or piece of paper with a folded top-left corner. Horizontal grey lines run across the lower portion, simulating text. A large red checkmark is superimposed over the center of the document. There is no other text present.](.pcie-9814-50-11256-1000-200-en/d3d46d12a92783246dbe08554ef52d05cde82144fe500fb30f390b922027e0e4.jpg)
NOTE:

Different signals cannot be routed onto the same trigger bus line.

<table><tr><td>SSI Timing Signal</td><td>Function</td></tr><tr><td>SSI Trig</td><td>Input/output trigger signal through SSI</td></tr></table>

All SSI signals are routed to the 16-pin connector from FPGA, enabling multi-module synchronization. ACL-eSSI-2/ACLeSSI-3/ACL-eSSI-4 cables can be used to synchronize 2, 3, or 4 modules.

<table><tr><td>15 13 11 9 7 5 3 1</td></tr><tr><td>16 14 12 10 8 6 4 2</td></tr><tr><td>PCB</td></tr></table>

<table><tr><td>Signal</td><td>Direction</td><td>Descr.</td><td>Pin</td></tr><tr><td>SSI Trig</td><td>Input/Output</td><td>Trigger signal through SSI</td><td>1, 9, 11, 13, 15</td></tr><tr><td>GND</td><td></td><td>Ground</td><td>2, 4, 6, 8, 10, 12, 14, 16</td></tr><tr><td>Reserved</td><td>Input/Output</td><td>Reserved for future use</td><td>3, 5,7</td></tr></table>

Table 3-5: SSI Signal Location and Pin Definition

# 3.7.1 Card Number Configuration

When multiple cards are used in a single chassis, card number configuration via switch, as shown.

![Floor plan diagram of an electronic circuit board layout with a highlighted component (no text or labels)](.pcie-9814-50-11256-1000-200-en/38ace17e5d0a16c36b230ffe8d2657d383769fb60c4ef1ef1d7b93cdb3a709d2.jpg)

Figure 3-15: Card Number Configuration Switch

When all sliders are in ON position, card number is 15, when all are OFF, card number is 0, as shown.

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>0</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td><td>1</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td><td>2</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td><td>3</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>OFF</td><td>4</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td><td>5</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td><td>6</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>ON</td><td>7</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>OFF</td><td>8</td></tr></table>

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td><td>9</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td><td>10</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>ON</td><td>11</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td><td>12</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>ON</td><td>13</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>OFF</td><td>14</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>ON</td><td>15</td></tr></table>

Table 3-6: Card Number Configuration Settings

Default card number is 15.

# 3.7.2 SSI\_TRIG

As an output, the SSI\_TRIG signal reflects the trigger event signal in an acquisition sequence. As an input, the PCIe-9814 accepts the SSI\_TRIG signal to be the trigger event source. The signal is configured in the rising edge-detection mode.

# 3.8 SDI

In some applications, marks may need to be added to some data. The PCIe-9814 uses SDI to accomplish this. The lowest 3 LSBs correspond to the logic level of SDI2 to SDI0.

<table><tr><td>SDI2</td><td>SDI1</td><td>SDI0</td><td>Data at midscale</td></tr><tr><td>Low</td><td>Low</td><td>Low</td><td>0000</td></tr><tr><td>Low</td><td>Low</td><td>High</td><td>0001</td></tr><tr><td>Low</td><td>High</td><td>Low</td><td>0002</td></tr><tr><td>Low</td><td>High</td><td>High</td><td>0003</td></tr><tr><td>High</td><td>Low</td><td>Low</td><td>0004</td></tr><tr><td>High</td><td>Low</td><td>High</td><td>0005</td></tr><tr><td>High</td><td>High</td><td>Low</td><td>0006</td></tr><tr><td>High</td><td>High</td><td>High</td><td>0007</td></tr></table>

Table 3-7: SDI Input vs. Data

# 3.9 Multi-boot

The PCIe-9814 supports software-based firmware updates. If firmware updates fail, the system may be unable to recognize the module, in which case the following steps may solve the problem.

1. Config SW2 to "on"
2. Install the module and restart the system
3. If the module is recognized, update firmware again (ensure the firmware you updated is workable)
4. Turn off the system, config SW2 to "off" and restart the system.

The default state of SW2 is "off".

If the problem remains, please contact FAE.

![Top-down schematic of a circuit board layout with component layouts and a highlighted storage unit (no text or symbols)](.pcie-9814-50-11256-1000-200-en/c5dacc61d1fe052ba29dd37dcbd9e68bcc9a3b86a83f0d9dbc8901aac85928a9.jpg)

Figure 3-16: Flash Memory Configuration Switch

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# Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

# A.1 Calibration Constant

The PCIe-9814 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-9814 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PCIe-9814.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PCIe-9814 boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

# A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PCIe-9814 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PCIe-9814 for at least 20 minutes and remove connected cables.

![The image displays a white document icon featuring horizontal lines and a folded top-left corner, overlaid with a large, bold red checkmark.](.pcie-9814-50-11256-1000-200-en/74209417e0d023af50b220c97404a33fd00b0a5ab4dd016eff38770d126c8877.jpg)
NOTE:

It is not necessary to manually factor delay into applications, as the PCIe-9814 driver automatically adds the compensation time.

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
- When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
▶ A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard warning sign. It features a red triangle with a black border pointing upwards. Inside the triangle is a large white exclamation point. Below the triangle, the word 'WARNING' is written in black capital letters.](.pcie-9814-50-11256-1000-200-en/6cba554f98932ed1cdaae4deda617fa70a48171289400bb1e31e41d723a30e40.jpg)

Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110
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Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

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Tel: +86-21-5132-8988

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Email: market@adlinktech.com

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Tel: +86-10-5885-8666

Fax: +86-10-5885-8626

Email: market@adlinktech.com

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Address: 深圳市南山区科技园南区高新南七道 数字技术园
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High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 6 allée de Londres, Immeuble Ceylan
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Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町3-7-4
神田374ビル4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
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Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 137-881 서울시 서초구 서초대로 326, 802 (서초동, 모인터빌딩)
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Tel: +82-2-2057-0565

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# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre Singapore 349584

Tel: +65-6844-2261

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Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: #50-56, First Floor, Spearhead Towers Margosa Main Road (between 16th/17th Cross) Malleswaram, Bangalore - 560 055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 27 Maskit St., Corex Building
PO Box 12777
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Email: israel@adlinktech.com

# ADLINK Technology, Inc. (UK Liaison Office)

Tel: +44 774 010 59 65

Email: UK@adlinktech.com
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