# PCIe-9834

# 4CH 16-bit 80MS/s Digitizer

# PCIe-9834/PCIe-9834P

# User's Manual

![Green ADLINK PCI card with gold connectors and circuit board (no readable text or symbols beyond branding)](.pcie-9834-50-11263-1000-200/21a87807ffd273ab66c3a40d410c34d0b382d738311562746c0b3f32a7c7f536.jpg)

Manual Rev.: 2.00

Revision Date: June 3, 2016

Part No: 50-11263-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>June 3. 2016</td><td>Initial Release</td></tr></table>

# Preface

# Copyright 2016 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a white document icon with faint horizontal lines and a folded top-left corner, overlaid with a large red checkmark.](.pcie-9834-50-11263-1000-200/2e866189f58d87961a3e5cf8171204e6561759d834896fd28efb384eac1b2d54.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border containing a large black exclamation point in the center, with the text 'CAUTION:' printed in black capital letters on a white background directly below the triangle.](.pcie-9834-50-11263-1000-200/5478003c4c1deec8c1c891354407609dc43c39d0d8c301d6938a8c65bc2db7a9.jpg)

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning sign featuring a red triangle with a white border containing a white exclamation point (!) in the center. Below the triangle is the text 'WARNING' in black capital letters.](.pcie-9834-50-11263-1000-200/48dfa05affb20fdca21a9d817f726bdcd814742834c6cd77206655677764ea38.jpg)

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface...... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2

1.3.1 Analog Input 2
1.3.2 Timebase 4
1.3.3 Triggers 4
1.3.4 General Specifications....5

1.4 Software Support 5

1.4.1 WD-DASK....6
1.4.2 LabVIEW Support....6

1.5 Device Layout and I/O Array 7

# 2 Getting Started 11

2.1 Installation Environment 11
2.2 Installing the Module.... 12

# 3 Operations 13

3.1 Functional Block Diagram.... 13
3.2 Analog Input Channel 13

3.2.1 Analog Input Front-End Configuration 13
3.2.2 Input Range and Data Format 14
3.2.3 DMA Data Transfer....15

3.3 Trigger Source and Trigger Modes.... 17

3.3.1 Software Trigger 17

3.3.2 External Digital Trigger 17
3.3.3 Analog Trigger 18

# 3.4 Trigger Modes.... 18

3.4.1 Post Trigger Mode 18
3.4.2 Delayed Trigger Mode 19
3.4.3 Pre-Trigger Mode....19
3.4.4 Middle Trigger Mode....20
3.4.5 Acquisition with Re-Triggering 20

# 3.5 Timebase 21

3.5.1 Internal Sampling Clock....22
3.5.2 External Reference Clock (PCIe-9834P only) ...... 22
3.5.3 External Sampling Clock....22

# 3.6 ADC Timing Control 23

3.6.1 Timebase Architecture....23
3.6.2 Basic Acquisition Timing....23

# 3.7 Synchronizing Multiple Modules 25

3.7.2 SSI\_TRIG 28

3.8 Multi-boot 28
3.9 Measurement Function API 29

# A Appendix: Calibration.... 35

A.1 Calibration Constant 35
A.2 Auto-Calibration 35

# Important Safety Instructions.... 39

# Getting Service 41

# List of Figures

Figure 1-1: Analog Input Channel Bandwidth .... 3

Figure 1-2: PCIe-9834 Schematic....7

Figure 1-3: PCIe-9834 I/O Array 8

Figure 3-1: Analog Input Architecture 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ..... 16

Figure 3-3: Trigger Architecture 17

Figure 3-4: External Digital Trigger 18

Figure 3-5: Post-Trigger Acquisition .... 19

Figure 3-6: Delayed Trigger Mode Acquisition....19

Figure 3-7: Pre-Trigger Mode Acquisition 20

Figure 3-8: Middle Trigger Mode Acquisition ....20

Figure 3-9: Re-Trigger Mode Acquisition 21

Figure 3-10: PCIe-9834 Clock Architecture 21

Figure 3-11: Timebase Architecture....23

Figure 3-12: Basic Digitizer Acquisition Timing....24

Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter 24

Figure 3-14: Card Number Configuration Switch 27

Figure 3-15: Flash Memory Configuration Switch....29

Figure 3-16: Waveform Transition 30

Figure A-1: Auto-Calibration Block Diagram 36

Figure A-2: Auto-Calibration Flow 37

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# List of Tables

Table 1-1: Channel Characteristics....3
Table 1-2: PCIe-9834 I/O Array Legend 9
Table 3-1: Input Range and Data Format 14
Table 3-2: Input Range FSR and -FSR Values....14
Table 3-3: Input Range Midscale Values....15
Table 3-4: Counter Parameters and Description ..... 25
Table 3-5: SSI Signal Location and Pin Definition 26
Table 3-6: Card Number Configuration Settings....28
Table 3-7: Measurement Parameters ...... 33

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# 1 Introduction

The ADLINK PCIe-9834 is a 4-channel, 16-bit, 80MS/s PCI Express digitizer providing speedy, high quality data acquisition. Each of the four input channels supports up to 80MS/s sampling, with 16-bit resolution A/D converter. 40MHz bandwidth analog input with 50Ω impedance receives ±0.5V, ±1V, ±5V, and ±10V high speed signals, and a simplified front end and highly stable onboard reference provide both highly accurate measurement results and high dynamic performance.

The PCIe-9834, based on x4 lane slot PCI Express technology, can be used in any standard PCI Express slot, x4, x8, or x16. With a PCI Express bus interface and extremely large onboard memory (up to 1GB), the PCIe-9834 easily manages simultaneous 4-CH data streaming even at the highest sampling rates.

The PCIe-9834 is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following auto-calibration, the calibration constant is stored in EEPROM, such that these values can be loaded and used as needed by the board. There is no requirement to calibrate the module manually.

# 1.1 Features

▶ Up to 80MS/s sampling
▶ 4 simultaneous analog inputs
▶ High resolution 16-bit ADC
▶ Up to 40 MHz bandwidth for analog input
▶ 1GB onboard storage
▶ Programmable input voltage of ±0.5V, ±1V, ±5V, or ±10V
▶ Scatter/gather DMA data transfer for high speed streaming
▶ 10 or 20MHz digital onboard filter (FPGA)
PLL module provides precise synch (PCIe-9834P only)
▶ Supports:
▶ One external digital trigger input
▶ One external clock input
▶ Full auto-calibration

# 1.2 Applications

▶ Testing/monitoring for Energy Management applications, including:

▷ Partial discharge
▶ Power line/device monitoring

▶ Non-destructive testing
▶ Radar acquisition
LiDAR

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td>Item</td><td>Spec</td><td>Notes</td></tr><tr><td>Channels</td><td>4 single-ended</td><td></td></tr><tr><td>Connector type</td><td>SMB</td><td></td></tr><tr><td>Input coupling</td><td>DC</td><td></td></tr><tr><td>ADC resolution</td><td>16-Bit</td><td></td></tr><tr><td>Input range</td><td>±0.5 V, ±1 V, ± 5V, or ± 10V</td><td>± 10V only supported Input impedance 1MΩ</td></tr><tr><td>Bandwidth (-3dB)</td><td>40MHz</td><td></td></tr><tr><td rowspan="3">Overvoltage</td><td>±10V sine wave/7Vrms</td><td>50Ω, ±0.5V or ±1V or ± 5V</td></tr><tr><td>±10V</td><td>1MΩ, ±0.5V or ±1V</td></tr><tr><td>±30V</td><td>1MΩ, ±5V or ±10V</td></tr><tr><td>Input impedance</td><td>50Ω or 1MΩ, software selectable</td><td></td></tr><tr><td>Digital filter</td><td>10MHz or 20MHz, software selectable</td><td></td></tr><tr><td rowspan="3">Offset Error</td><td>±0.1mV</td><td>±0.5V</td></tr><tr><td>±0.2mV</td><td>±1V</td></tr><tr><td>±0.5mV</td><td>±5V, or ±10V</td></tr></table>

<table><tr><td>Item</td><td>Spec</td><td>Notes</td></tr><tr><td>Gain Error</td><td>±0.15%</td><td></td></tr><tr><td rowspan="4">System Noise (RMS)</td><td>0.1mV</td><td>±0.5V</td></tr><tr><td>0.15mV</td><td>±1V</td></tr><tr><td>1mV</td><td>±5V</td></tr><tr><td>1.5 mV</td><td>±10 V</td></tr><tr><td rowspan="2">Crosstalk</td><td>-80 dB</td><td>±0.5 V</td></tr><tr><td>-90 dB</td><td>±1 V or ± 5V or ± 10V</td></tr><tr><td>SNR</td><td>67 dB</td><td></td></tr><tr><td>THD</td><td>-78 dB</td><td></td></tr><tr><td>SFDR</td><td>78 dB</td><td></td></tr></table>

Table 1-1: Channel Characteristics

![| Frequency (Hz) | 5V    | 1V    | 0.5V  |\n| -------------- | ----- | ----- | ----- |\n| 1.00E+05       | 0.0   | 0.0   | 0.0   |\n| 1.00E+06       | 0.0   | 0.0   | 0.0   |\n| 1.00E+07       | -0.5  | -0.5  | -0.5  |\n| 1.00E+08       | -6.0  | -4.5  | -7.0  |](.pcie-9834-50-11263-1000-200/73e91358f907651b166b9307d7967c3653d2e725c787dde1ba11e1b0e220e066.jpg)

Figure 1-1: Analog Input Channel Bandwidth

# 1.3.2 Timebase

<table><tr><td>Sample Clock</td><td>Detail</td><td>Comment</td></tr><tr><td rowspan="2">Timebase options</td><td>Internal : onboard crystal oscillator</td><td></td></tr><tr><td>External : CLK IN (front panel)</td><td></td></tr><tr><td rowspan="2">Sampling clock frequency</td><td>Internal : 80MHz</td><td>1.22kS/s to 80MS/s</td></tr><tr><td>External : 20MHz to 80MHz (CLK IN)</td><td></td></tr><tr><td>Timebase accuracy</td><td>&lt; ± 25ppm</td><td></td></tr><tr><td>External reference clock source</td><td>REF_CLK (supported by PCI-9834P only)</td><td></td></tr><tr><td>External reference clock</td><td>10MHz</td><td></td></tr><tr><td>External reference clock input range</td><td>3.3V to 5V TTL</td><td>DC compliant</td></tr><tr><td>External sampling clock input range</td><td>1Vpp to 5Vpp</td><td>AC / DC compliant</td></tr></table>

# 1.3.3 Triggers

<table><tr><td colspan="2">Trigger Source &amp; Mode</td></tr><tr><td>Trigger source</td><td>Software, external digital trigger, analog trigger, and SSI (system synchronized interface)</td></tr><tr><td>Trigger mode</td><td>Post trigger, delay trigger, pre-trigger, or middle trigger, re-trigger for post trigger and delay trigger modes</td></tr></table>

<table><tr><td colspan="2">Digital Trigger Input</td></tr><tr><td>Sources</td><td>Front panel SMB connector</td></tr><tr><td>Compatibility</td><td>3.3 V TTL, 5 V tolerant</td></tr><tr><td>Input high threshold</td><td>2.0 V</td></tr><tr><td>Input low threshold (VIL)</td><td>0.8 V</td></tr><tr><td>Maximum input overload</td><td>-0.5 V to +5.5 V</td></tr><tr><td>Trigger polarity</td><td>Rising or falling edge</td></tr><tr><td>Pulse width</td><td>20 ns minimum</td></tr></table>

# 1.3.4 General Specifications

<table><tr><td colspan="2">Specifications</td></tr><tr><td>Dimensions</td><td>167.64 W x 106.68 H mm (6.53 x 4.16 in)</td></tr><tr><td>Bus interface</td><td>PCI Express Gen 1 x 4</td></tr><tr><td>Operating</td><td>Temperature: 0°C - 50°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td>Storage</td><td>Temperature: -20°C - +80°CRelative humidity: 5% - 95%, non-condensing</td></tr></table>

<table><tr><td colspan="2">Calibration</td></tr><tr><td>Onboard reference</td><td>+1.8V, +0.9V, and +0.45V</td></tr><tr><td>Temperature coefficient</td><td>1.0 ppm/°C</td></tr><tr><td>Warm-up time</td><td>15 minutes</td></tr></table>

<table><tr><td></td><td colspan="2">PCIe-9834</td><td colspan="2">PCIe-9834P</td></tr><tr><td>Power Rail</td><td>Standby Current (mA)</td><td>Full Load (mA)</td><td>Standby Current (mA)</td><td>Full Load (mA)</td></tr><tr><td>3.3V</td><td>18</td><td>18</td><td>18.7</td><td>21.4</td></tr><tr><td>12V</td><td>450</td><td>470</td><td>675</td><td>697</td></tr><tr><td>Total RMS Power (W)</td><td>5.459</td><td>5.699</td><td>8.162</td><td>8.435</td></tr></table>

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW $^{®}$ .

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license.

# 1.4.1 WD-DASK

WD-DASK includes device drivers and DLL for Windows XP/7/8/10. DLL is binary compatible across Windows XP/7/8/10. This means all applications developed with WD-DASK are compatible with these Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The WD-DASK user and function reference manuals are on the ADLINK All-in-One CD.

# 1.4.2 LabVIEW Support

For customers who want to write their own programs in LabVIEW, a LabVIEW library toolkit, DAQ-LabVIEW Plus, is provided to support PCIe-9834 card use.

# 1.5 Device Layout and I/O Array

![The image displays a white document icon featuring a folded top-right corner and faint horizontal lines running across it. A large, bold red checkmark is superimposed diagonally across the center of the document.](.pcie-9834-50-11263-1000-200/74465a1b356ed7091bc5d8342dac608e8937d7c0986ff4d708323878e290137c.jpg)
NOTE:

All dimensions are in mm

![ADLINK\n100.36\n59.05\n169.55\n98.4](.pcie-9834-50-11263-1000-200/a6ab1d1f39946a66bd748458998db851de5938e1f80e123ba8a14457dcf2e9cc.jpg)

Figure 1-2: PCIe-9834 Schematic

The PCIe-9834 I/O array is labeled to indicate connectivity, as shown.

![CH0\nCH1\nCH2\nCH3\nCLK\nTRG\nREF_CLK](.pcie-9834-50-11263-1000-200/8a1f2f42ce099acecf907f34820a4a4c78c6b80fb502f83b1aa3a03df6316166.jpg)

Figure 1-3: PCIe-9834 I/O Array

All I/O connectors are SMB snap-on.

<table><tr><td>Input</td><td>Faceplate Label</td><td>Remark</td></tr><tr><td>Analog</td><td>CH0</td><td rowspan="4">Analog Input Channel</td></tr><tr><td>Analog</td><td>CH1</td></tr><tr><td>Analog</td><td>CH2</td></tr><tr><td>Analog</td><td>CH3</td></tr><tr><td>Ext. Clock</td><td>CLK</td><td>Input for external sample clock to digitizer</td></tr><tr><td>Ext. Digital Trigger</td><td>TRG</td><td>External digital trigger input, receiving trigger signal from external instrument and initiating acquisition</td></tr><tr><td>Ext. Reference Clock Input</td><td>REF_CLK</td><td>(PCIe-9834P with PLL module only)REF_CLK can be used to receive an external reference 10MHz clock to generate ADC timebase. See Section 3.5.2 External Reference Clock (PCIe-9834P only)</td></tr></table>

Table 1-2: PCIe-9834 I/O Array Legend

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# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PCIe-9834.

![The image displays a simple digital icon of a white sheet of paper featuring faint, horizontal grey lines. The top right corner of the paper is folded down. A large, bold red checkmark is superimposed diagonally across the center of the document.](.pcie-9834-50-11263-1000-200/cfe5282f438a3c7dca6dbe1ed3d2ed24f062388deebad11d63662aca0d505b67.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

▶ Phillips (cross-head) screwdriver
▶ Flat-head screwdriver
Anti-static wrist strap
▶ Antistatic mat

The ADLINK PCIe-9834 is electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black, uppercase letters.](.pcie-9834-50-11263-1000-200/2670a3f481efb346cea8d5d8faf4cc5b92b9403f18652197c6a2501db6d07e7a.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

▶ Package Contents
▶ PCIe-9834 digitizer
▶ ADLINK All-in-one compact disc
▶ PCIe-9834 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

![The image displays a red triangular warning sign containing a white exclamation point in the center. Below the triangle, the word 'WARNING' is written in black capital letters.](.pcie-9834-50-11263-1000-200/d076a13f68ca5e19bd9174cadbc9e336b185a47a11c1f41fff118bdb95fe0568.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Installing the Module

1. Turn off the computer.
2. Remove the top cover.
3. Select an available PCI express x4 slot and remove the bracket-retaining screw and the bracket cover.
4. Line up the PCI express digitizer with the PCI express slot on the back panel. Slowly push down on the top of the PCI express digitizer until its card-edge connector is resting on the slot receptacle.
5. Install the bracket-retaining screw to secure the PCI express digitizer to the back panel rail.
6. Replace the computer cover.

# 3 Operations

This chapter contains information regarding analog input, triggering and timing for the PCIe-9834.

# 3.1 Functional Block Diagram

![This block diagram depicts a signal processing and data acquisition system.\n\n**Labeled Blocks and Inputs:**\n*   **Inputs:** On the left side, there are input channels labeled **CH0**, **CH1**, **CH2**, and **CH3**. Below these are timing inputs labeled **CLK IN**, **REF_CLK**, and **TRIG IN**.\n*   **Internal Blocks:** Inside the light blue box are blocks labeled **Analog Front-End**, **Calibration**, **16 Bit ADC**, **Clock Distribution**, and **FPGA**.\n*   **External Interfaces:** Outside the main box are blocks labeled **SSI** and a large vertical arrow labeled **PCIe Interface**.\n\n**Connections:**\n*   **CH0**, **CH1**, **CH2**, and **CH3** connect to the left side of the **Analog Front-End**.\n*   The **Analog Front-End** is connected to the **Calibration** block below it.\n*   Four lines connect the right side of the **Analog Front-End** to the left side of the **16 Bit ADC**.\n*   The **16 Bit ADC** connects to the left side of the **FPGA**.\n*   The **Clock Distribution** block sends a signal up to the bottom of the **16 Bit ADC**.\n*   **CLK IN** connects to the left side of the **Clock Distribution**.\n*   **REF_CLK** connects to a small oscillator symbol, which then connects to the left side of the **Clock Distribution**.\n*   **TRIG IN** connects directly to the bottom of the **FPGA**.\n*   The **FPGA** has a bidirectional connection (double-headed arrow) to the **SSI** block above it.\n*   The **FPGA** has a bidirectional connection (double-headed arrow) to the large vertical arrow labeled **PCIe Interface**.](.pcie-9834-50-11263-1000-200/3b19c44af301add04078d0a4cb14a542793bffd274ab4b4b8d134a820cbcfbbf.jpg)

# 3.2 Analog Input Channel

# 3.2.1 Analog Input Front-End Configuration

![The diagram illustrates a signal chain flowing from left to right. The labeled blocks and connections are as follows:\n\n1.  **Inputs:** On the far left, a box labeled 'Calibration Source' connects to a switch mechanism. An unlabeled input box also connects to the same switch.\n2.  **Signal Path:**\n    *   The switch connects to a block containing a resistor symbol, labeled below as '50Ω/Hi-Z'.\n    *   This connects to a block containing a resistor symbol, labeled above as 'Attenuator'.\n    *   This connects to a triangle symbol labeled below as 'High Impedance Buffer'.\n    *   This connects to a second triangle symbol labeled above as 'ADC Driver'.\n    *   The output from the 'ADC Driver' connects to a block labeled 'Anti-aliasing Filter'.\n    *   This block connects to a block labeled '16-bit ADC'. Inside this block, there is a triangle pointing right. On the left and right sides of the block, there are small circles labeled with the text '0'.\n3.  **Output:** A line extends from the '16-bit ADC' to the right, labeled below with the text '16'.](.pcie-9834-50-11263-1000-200/201b84667a9461b939b00f99ef3ba2804bb067545a406fa353b48271e63594c6.jpg)

Figure 3-1: Analog Input Architecture

# Input Configuration

The input channel terminates with equivalent 50Ω or 1MΩ input impedance (selected by software). The 16-bit ADC provides not only accurate DC performance but also high signal-to-noise ratio, and high spurious-free dynamic range in AC performance. The ADC transfers data to system memory via the high speed PCI Express Gen 1 X 4 interface.

For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI.

# 3.2.2 Input Range and Data Format

Data format of the PCIe-9834 is 2's complement.

<table><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>....</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td colspan="9">D15 to D0 bits represent the 16-bit data from ADC (2&#x27;s complement)</td></tr></table>

Table 3-1: Input Range and Data Format

<table><tr><td></td><td>Full Scale Range</td><td>Least Significant Bit</td><td>FSR-1LSB</td><td>-FSR</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>± 10.0V</td><td>0.305 mV</td><td>9.999694824</td><td>-10V</td></tr><tr><td>± 5.0V</td><td>0.153 mV</td><td>4.999847412</td><td>-5V</td></tr><tr><td>± 1.0V</td><td>0.031 mV</td><td>0.999969482</td><td>-1V</td></tr><tr><td>± 0.5V</td><td>0.015 mV</td><td>0.499984741</td><td>-0.5V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FFF</td><td>8000</td></tr></table>

Table 3-2: Input Range FSR and -FSR Values

<table><tr><td></td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale -1LSB</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>0.305 mV</td><td>0 V</td><td>-0.305 mV</td></tr><tr><td>0.153 mV</td><td>0 V</td><td>-0.153 mV</td></tr><tr><td>0.031 mV</td><td>0 V</td><td>-0.031 mV</td></tr><tr><td>0.015 mV</td><td>0 V</td><td>-0.015 mV</td></tr><tr><td>Digital Code</td><td>0001</td><td>0000</td><td>FFFF</td></tr></table>

Table 3-3: Input Range Midscale Values

# 3.2.3 DMA Data Transfer

The PCIe-9834, a PCIe Gen 1 X 4 device, is equipped with a 80MS/s high sampling rate ADC, generating a 640 MByte/second rate.

To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list so users can transfer large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. Figure 3-2 illustrates a linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space, but the subsequent descriptor address must be less than 4GB.

![The diagram illustrates a data flow structure involving memory, a bus, and descriptor blocks.\n\n**Labeled Blocks:**\n\n*   **Bottom:** A rectangle labeled 'Local Memory (FIFO)'.\n*   **Middle:** A wide rectangle labeled 'PCI Express Bus'.\n*   **Top Row (Left to Right):**\n    *   **Left Block:** A rectangle divided into four rows containing the text: 'First PCI Address', 'First Dual Address', 'Transfer Size', 'Next Descriptor'.\n    *   **Center Block:** A rectangle divided into four rows containing the text: 'PCI Address', 'Dual Address', 'Transfer Size', 'Next Descriptor'.\n    *   **Right Block:** A rectangle divided into four rows containing the text: 'PCI Address', 'Dual Address', 'Transfer Size', 'Next Descriptor'.\n\n**Connections:**\n\n*   An arrow points upward from 'Local Memory (FIFO)' to 'PCI Express Bus'.\n*   An arrow points upward from 'PCI Express Bus' to the 'Center Block'.\n*   An arrow points rightward from the 'Left Block' to the 'Center Block'.\n*   An arrow points rightward from the 'Center Block' to the 'Right Block'.](.pcie-9834-50-11263-1000-200/c2bf2b9e04beb2abbf57cc9c8abd12f19d82ef2a321618914391ab3859a138e2.jpg)

Figure 3-2: Linked List of PCI Address DMA Descriptors

# 3.3 Trigger Source and Trigger Modes

This section details PCIe-9834 triggering operations.

![Based on the provided image, here is the accurate description of the flowchart:\n\n**Blocks and Labels:**\n*   **Input Sources:** 'Software Trigger', 'Digital Trigger Input' (associated with a cylinder connector icon), and 'SSI Trigger'.\n*   **Processing Blocks:** A trapezoidal shape (acting as a multiplexer), a square block labeled 'Trigger Decision', and a vertical double-headed arrow block labeled 'ISS'.\n*   **Outputs/Paths:** 'To Internal FPGA', '(Master =) Slave)', and '(Master (= Slave)'.\n\n**Connections and Flow:**\n1.  **Inputs:** Three lines feed into the left side of the trapezoidal block:\n    *   The top input is 'Software Trigger'.\n    *   The middle input is 'Digital Trigger Input'.\n    *   The bottom input is labeled 'SSI Trigger'.\n2.  **Main Processing:** The trapezoidal block outputs a single line that enters the 'Trigger Decision' block.\n3.  **Outputs from 'Trigger Decision':**\n    *   One line exits to the right and is labeled 'To Internal FPGA'.\n    *   Another line exits downwards and splits into two parallel paths connecting to the 'ISS' block:\n        *   The upper path is labeled '(Master =) Slave)' and an arrow points right into the 'ISS' block.\n        *   The lower path originates from the 'ISS' block, is labeled '(Master (= Slave)', and the arrow points left. This line loops back around the bottom and connects to the 'SSI Trigger' input of the trapezoidal block.](.pcie-9834-50-11263-1000-200/3e47d0b14e8194be739ce810c1f133c34ec999ef6d3b8d712629c7f8d20331fa.jpg)

Figure 3-3: Trigger Architecture

The PCIe-9834 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-9834 supports internal software trigger, external digital trigger, and analog trigger.

# 3.3.1 Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

# 3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL rising edge or falling edge is detected at the SMB connector TRG IN on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 20 ns.

![Pulse Width ) 20ns](.pcie-9834-50-11263-1000-200/63dda9f22487512fe06658e42e9e7f30c0da2e4fe791137696201b2662127be2.jpg)

Rising Edge Trigger Event

![Pulse Width ) 20ns](.pcie-9834-50-11263-1000-200/1c31c08f5b2229e7deb61f318136e4af24392e07b2e22b6ae96e880bf1b2d319.jpg)

Falling Edge Trigger Event
Figure 3-4: External Digital Trigger

# 3.3.3 Analog Trigger

An analog trigger is generated when AI input signal level is detected at the SMB connectors CH0 to CH3 (selected by software). The trigger level is also selected by software.

# 3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input function.

# 3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PCIe-9834 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. The acquisition stops once the total data amount reaches a predefined value.

![The image is a timing diagram illustrating the relationship between time, a trigger signal, and data acquisition.\n\n**Labeled Blocks and Axes:**\n*   **Time Axis:** A horizontal line running across the top with an arrow pointing right, labeled **'Time'**.\n*   **Trigger Signal:** A horizontal line labeled **'Trigger'** below the time axis.\n*   **Data Signal:** A horizontal line labeled **'Data'** at the bottom.\n\n**Events and Connections:**\nThree downward arrows on the 'Time' axis mark specific events:\n1.  **'Operation start'** (leftmost arrow).\n2.  **'Trigger Event Occurs Acquisition start'** (middle arrow).\n3.  **'Acquisition stop'** (rightmost arrow).\n\n**Signal Relationships:**\n*   **Trigger:** The 'Trigger' line shows a brief rectangular pulse (high state) that aligns perfectly with the **'Trigger Event Occurs Acquisition start'** arrow.\n*   **Data:** The 'Data' line shows a long rectangular block labeled **'N samples'**. This block begins at the same vertical alignment as the rising edge of the 'Trigger' pulse and ends at the vertical alignment of the **'Acquisition stop'** arrow.](.pcie-9834-50-11263-1000-200/7bf60da80714eb976af09a12c35ab870ac24d50bc5f2d0e54ec34ec8e89cbd98.jpg)

Figure 3-5: Post-Trigger Acquisition

# 3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When the PCIe-9834 receives a trigger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X ( $2^{16}$ ), and the minimum is the Timebase period.

![This diagram illustrates a timing sequence involving triggers and data acquisition. It consists of a main timeline and two signal traces below it:\n\n**Timeline and Event Markers:**\nA horizontal arrow labeled **'Time'** extends to the right. Above this line, vertical arrows indicate specific moments:\n*   **'Operation start'**\n*   **'Trigger Event Occurs'**\n*   **'Acquisition start'**\n*   **'Acquisition stop'**\n\nBetween 'Trigger Event Occurs' and 'Acquisition start,' a horizontal bracket labeled **'Delay Time'** connects the two points.\n\n**Signal Traces:**\n*   **'Trigger'**: A line showing a single positive pulse that aligns vertically with the 'Trigger Event Occurs' marker.\n*   **'Data'**: A line featuring a rectangular block labeled **'N samples'** that aligns vertically with the period between 'Acquisition start' and 'Acquisition stop.'](.pcie-9834-50-11263-1000-200/741755c90bc3a72c095597242d7eb22b0c27457a8cf90f31e10d08e7ba463da5.jpg)

Figure 3-6: Delayed Trigger Mode Acquisition

# 3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.

![This diagram illustrates a data acquisition timeline and triggering mechanism.\n\n**Text Labels:**\n*   **Top Row:**\n    *   'Operation start Acquisition start'\n    *   'Trigger signals occuring before the specified amount of data has been acquired are ignored'\n    *   'Trigger Event Occurs Acquisition stop Data transfer to system begins'\n    *   'Time' (at the far right end of the axis)\n*   **Middle Row:** 'Trigger'\n*   **Bottom Row:** 'Data', 'N samples', 'X samples have been acquired before trigger occurs, where X(N'\n\n**Structure and Connections:**\n*   **Timeline:** A horizontal black line with an arrowhead pointing right serves as the time axis at the top. Three downward-pointing arrows originate from the text blocks above, pointing to specific moments on this timeline.\n*   **Trigger Signal:** Below the timeline is a row labeled 'Trigger.' It shows a signal line with two square pulses.\n*   **Data Buffer:** Below the trigger row is a row labeled 'Data.' It features a long rectangular bar divided into two sections:\n    *   A left section with diagonal hatching.\n    *   A right section (white rectangle) labeled 'N samples.'\n*   **Alignment:**\n    *   The first downward arrow (for 'Trigger signals occuring...') aligns vertically with the first pulse on the 'Trigger' line.\n    *   The second downward arrow (for 'Trigger Event Occurs...') aligns vertically with the second pulse on the 'Trigger' line. This pulse aligns with the boundary between the hatched section and the 'N samples' section of the data bar.\n    *   A double-headed dimension line below the hatched section indicates its width, corresponding to the text 'X samples have been acquired before trigger occurs, where X(N'.](.pcie-9834-50-11263-1000-200/33e92b99732aae72a290ff8dea828ef4b326261518a6ab673def64a4414ecf16.jpg)

Figure 3-7: Pre-Trigger Mode Acquisition

# 3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to be collected set individually (M and N samples), as follows

![The image is a timing diagram illustrating a data acquisition process. It features a horizontal axis labeled 'Time' pointing to the right, along which three vertical arrows mark specific events:\n\n1.  **Left Arrow:** Points to the beginning of the timeline and is labeled 'Operation start' and 'Acquisition start'.\n2.  **Middle Arrow:** Points to a specific moment and is labeled 'Trigger event occurs'.\n3.  **Right Arrow:** Points to the end of the timeline and is labeled 'Acquisition stop' and 'Data transfer to system begins'.\n\nBelow the timeline are two signal tracks:\n\n*   **Trigger:** Labeled on the left, this track shows a flat line that briefly pulses high (a square wave) vertically aligned with the 'Trigger event occurs' arrow.\n*   **Data:** Labeled on the left, this track displays a sequence of blocks:\n    *   A rectangular block filled with diagonal hatching (stripes) that begins at the 'Operation start' point.\n    *   A rectangular block labeled 'M samples' that begins at the 'Trigger event occurs' point.\n    *   A rectangular block labeled 'N samples' that follows the 'M samples' block and ends at the 'Acquisition stop' point.](.pcie-9834-50-11263-1000-200/46a0585c95570a19ecf408bca19661e66f92882d667d4562d3100cbb1b67dce6.jpg)

Figure 3-8: Middle Trigger Mode Acquisition

# 3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single acquisition. Re-Trigger mode can also be set to automatically acquire R traces, containing N\*R samples/channel of data, without additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed-Trigger modes, with different limitations on the spacing between trigger events in each mode. Trigger events arriving too close to the previous instance will be ignored by the digitizer.

▶ In Post-Trigger mode, the minimum spacing between trigger events is N+1
▶ In Delayed-Trigger mode, the minimum spacing between trigger events is $(N+D)+1$ , where D is the number of the delayed setting

![This diagram illustrates a timeline sequence involving triggers and data acquisition.\n\n**Top Section (Timeline & Events):**\n*   A horizontal arrow pointing right is labeled **'Time'**.\n*   Three downward-pointing arrows indicate specific moments on the timeline:\n    *   **'Operation start'** (at the far left).\n    *   **'1st Trigger Event Occurs'**.\n    *   **'2nd Trigger Event Occurs'**.\n\n**Middle Section (Trigger Signal):**\n*   A horizontal line labeled **'Trigger'** runs below the timeline.\n*   It shows two rectangular pulses:\n    *   The first pulse aligns vertically with the **'1st Trigger Event Occurs'** arrow.\n    *   The second pulse aligns vertically with the **'2nd Trigger Event Occurs'** arrow.\n\n**Bottom Section (Data Signal):**\n*   A horizontal line labeled **'Data'** runs below the trigger line.\n*   It contains two elongated hexagonal blocks, both labeled **'N samples'**.\n    *   The first **'N samples'** block begins immediately after the first **'Trigger'** pulse.\n    *   The second **'N samples'** block begins immediately after the second **'Trigger'** pulse.](.pcie-9834-50-11263-1000-200/b96d4b3061c8bb72e77e51bacb468ace9632a3f73c0894a2f9146f8a68d84371.jpg)

Figure 3-9: Re-Trigger Mode Acquisition

# 3.5 Timebase

![The diagram illustrates a clock signal selection system with the following components and connections:\n\n*   **Inputs (Left Side):**\n    *   Top: A coaxial connector symbol labeled **CLK IN**. A line connects it to the top input of a central rectangular box.\n    *   Middle: A circle containing a sine wave symbol labeled **80M Xtal**. A line connects it to the middle input of the central rectangular box.\n    *   Bottom: A coaxial connector symbol labeled **REF_CLK**. A line connects it to a separate rectangular block.\n\n*   **Processing Block:**\n    *   A rectangular block labeled **Synthesizer PLL Board** receives the **REF_CLK** signal. A line exits this block and connects to the bottom input of the central rectangular box.\n\n*   **Switching Block (Center Right):**\n    *   A rectangular box receives three inputs (from **CLK IN**, **80M Xtal**, and the **Synthesizer PLL Board**). Inside, a switch symbol is drawn with an arrow pointing toward the top input and a curved line indicating the switch mechanism.\n\n*   **Output:**\n    *   A single line exits the right side of the switch box, leading to an arrowhead labeled **To ADC**.](.pcie-9834-50-11263-1000-200/76166f7ebe1625d64599dea86fa5e366fff328302b341e54c304915f33fca0fa.jpg)

Figure 3-10: PCIe-9834 Clock Architecture

# 3.5.1 Internal Sampling Clock

The PCIe-9834 internal 80MHz crystal oscillator acts as a sampling clock for ADC.

# 3.5.2 External Reference Clock (PCIe-9834P only)

The onboard PLL module allows REF\_CLK to act as an external reference clock input, such that when multi-card synchronization for more than two modules is needed, a 10MHz clock source can be provided to REF\_CLK and API function utilized to switch synthesizer input to the clock source at SMB connector REF\_CLK, and generate a precise 80MHz clock for ADC. as the synthesizer's reference clock is the same for all modules, the generated 80MHz clock is synchronous.

# 3.5.3 External Sampling Clock

The PCIe-9834 can further choose an external clock source as ADC sampling clock. When an external sampling clock is selected, the ADC sampling frequency switches to the clock source at SMB Connector CLK IN, and clock source frequency is available from 20MHz to 80MHz. Be advised that if the frequency of the external sample clock is changed, the LVDS timebase requires recalibration.

To do so, call WD-DASK function: WD\_AI\_Config().

For more information, refer to the WD-DASK Function Library Reference.

# 3.6 ADC Timing Control

# 3.6.1 Timebase Architecture

![The diagram shows a signal flow starting from an external source and entering a system labeled **FPGA**.\n\n**Labeled Blocks and Text:**\n*   **Onboard 80MHz Oscillator**\n*   **ADC**\n*   **ADC Output 80MHz**\n*   **X6 Multiplier PLL**\n*   **480MHz**\n*   **For ADC Data Bus**\n*   **80MHz**\n*   **For ADC State machine**\n*   **FPGA** (enclosing the right-hand section in a dashed box)\n\n**Connections:**\n1.  An arrow connects **Onboard 80MHz Oscillator** to the **ADC** block.\n2.  An arrow connects the **ADC** block to the label **ADC Output 80MHz**.\n3.  The signal **ADC Output 80MHz** enters the **FPGA** box and splits into two paths:\n    *   **Top Path:** An arrow points into the **X6 Multiplier PLL** block. An arrow exiting this block points to **For ADC Data Bus**, labeled with **480MHz**.\n    *   **Bottom Path:** An arrow bypasses the multiplier block and points to **For ADC State machine**, labeled with **80MHz**.](.pcie-9834-50-11263-1000-200/d4d73ea6677f8462ea6c0cd001720f0bc63e7aa8f78342fd316244a2e67df2b9.jpg)

Figure 3-11: Timebase Architecture

# 3.6.2 Basic Acquisition Timing

The PCIe-9834 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger. The Timebase is a clock provided to the ADC and acquisition engine for essential timing. The Timebase is from an onboard synthesizer. To achieve different sampling rates, a scan interval counter is used.

Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC, and stores the sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately through the DMA engine. The sampled data is generated continuously at the rising edge of Timebase according to the scan interval counter setting. When sampled data reaches a specified value, in this example 256, acquisition ends.

![The flowchart depicts a signal processing path starting with an **Onboard 80MHz Oscillator** connected to an **ADC** block.\n\nThe **ADC** block outputs an **ADC Output 80MHz** signal, which enters a dashed box labeled **FPGA**. Inside the FPGA, the signal splits into two paths:\n1.  The top path feeds into an **X6 Multiplier PLL** block, which outputs a **480MHz** signal directed to **For ADC Data Bus**.\n2.  The bottom path carries the original signal, labeled **80MHz**, directed to **For ADC State machine**.](.pcie-9834-50-11263-1000-200/fbe8141abf30e8c9b8e96e6c24f258a97253b9c4919bc01dfc62ec26791e7972.jpg)

Figure 3-12: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 80MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 80MS/s / 2 = 40MS/s. If as 3, the equivalent sampling rate is 80MS/s / 3 = 26.66MS/s, and vice versa. The scan interval counter is 16 bits in width, therefore the lowest sampling rate is 1.221kS/s (80MS/s / 65535).

![The diagram is a timing chart illustrating the relationship between trigger signals, a clock, and data acquisition intervals.\n\n**Top Section:**\n*   **Trigger**: A square wave signal that goes high and stays high for the duration of the diagram.\n*   **TIMEBASE**: A clock signal represented by a square wave with upward-pointing arrows on the rising edges.\n\n**Middle Section (DATA):**\n*   A brace labeled **DATA** groups three horizontal rows representing different scan intervals:\n    *   **ScanIntrv = 1**: A continuous chain of hexagonal blocks labeled sequentially: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**, **D7**, **D8**, **D9**, **D10**.\n    *   **ScanIntrv = 2**: A chain of hexagonal blocks labeled sequentially: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**. These blocks are spaced further apart than in the row above.\n    *   **ScanIntrv = 3**: A chain of hexagonal blocks labeled sequentially: **D1**, **D2**, **D3**, **D4**. These blocks are spaced furthest apart.\n\n**Bottom Section:**\n*   **Acquisition In Progress**: Text at the bottom left.\n*   An arrow points from the text **Acquisition is initiated following this clock edge** to a specific rising edge of the **TIMEBASE** signal, indicating the start of the data collection.](.pcie-9834-50-11263-1000-200/8f43667e2b4f34f0dbecc0728ee28fb3609221aee9c92db79df5114f95a93bb3.jpg)

Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter

<table><tr><td>Counter Name</td><td>Length</td><td>Valid Value</td><td>Description</td></tr><tr><td>ScanIntrv</td><td>16-bit</td><td>1-65535</td><td>Timebase divider to achieve equivalent sampling rate of the digitizer, where Sampling rate = Timebase / ScanIntrv</td></tr><tr><td>DataCnt</td><td>31-bit</td><td>1-2147483647</td><td>Specifies the amount of data to be acquired: 1 - 2147483648 for pre-trig or mid-trig mode operation</td></tr><tr><td>trigDelayTicks</td><td>16-bit</td><td>1 -65535</td><td>Indicates time between a trigger event and commencement of acquisition. The unit of a delay count is the period of the Timebase.</td></tr><tr><td>ReTrgCnt</td><td>31-bit</td><td>1-2147483647</td><td>Enables re-trigger to accept multiple triggers. 1 - 2147483647 for normal operation See Section 3.4.5: Acquisition with Re-Triggering</td></tr></table>

Table 3-4: Counter Parameters and Description

# 3.7 Synchronizing Multiple Modules

The PCIe-9834 provides a dedicated connector as system synchronization interface, enabling multiple module synchronization. As shown, bi-directional SSI I/Os provides a flexible connection between modules, allowing one SSI master PCIe-9834 to output SSI trigger signals to other slave modules. For more accurate synchronization between modules, external sampling clock or external reference clock should be applied.

The table summarizes SSI functionalities.

![The image displays an icon of a white document with a folded top-left corner. Faint gray horizontal lines run across the page, and a large, bold red checkmark is drawn diagonally across the center.](.pcie-9834-50-11263-1000-200/e402c0ef663f2a3bc6dfedcf4f2424c201e7d3587cb05d4715c22c223ad3b81d.jpg)
NOTE:

Different signals cannot be routed onto the same trigger bus line.

<table><tr><td>SSI Timing Signal</td><td>Function</td></tr><tr><td>SSI Trig</td><td>Input/output trigger signal through SSI</td></tr></table>

All SSI signals are routed to the 16-pin connector from FPGA, enabling multi-module synchronization. ACL-eSSI-2/ACLeSSI-3/ ACL-eSSI-4 cables can be used to synchronize 2, 3, or 4 modules.

<table><tr><td>15</td><td>13</td><td>11</td><td>9</td><td>7</td><td>5</td><td>3</td><td>1</td></tr><tr><td>16</td><td>14</td><td>12</td><td>10</td><td>8</td><td>6</td><td>4</td><td>2</td></tr></table>

PCB

<table><tr><td>Signal</td><td>Direction</td><td>Descr.</td><td>Pin</td></tr><tr><td>SSI Trig</td><td>Input/Output</td><td>Trigger signal through SSI</td><td>1, 9, 11, 13, 15</td></tr><tr><td>GND</td><td></td><td>Ground</td><td>2, 4, 6, 8, 10, 12, 14, 16</td></tr><tr><td>Reserved</td><td>Input/Output</td><td>Reserved for future use</td><td>3, 5,7</td></tr></table>

Table 3-5: SSI Signal Location and Pin Definition

# 3.7.1 Card Number Configuration

When multiple cards are used in a single chassis, card number configuration via switch, as shown.

![Floor plan diagram of an electronic circuit board with a highlighted component marked in red.](.pcie-9834-50-11263-1000-200/19e2d1d4e70128185345ff7850eff83677280d77ca91a82458caa6416be96052.jpg)

Figure 3-14: Card Number Configuration Switch

When all sliders are in ON position, card number is 15, when all are OFF, card number is 0, as shown.

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>0</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td><td>1</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td><td>2</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td><td>3</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>OFF</td><td>4</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td><td>5</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td><td>6</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>ON</td><td>7</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>OFF</td><td>8</td></tr></table>

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td><td>9</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td><td>10</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>ON</td><td>11</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td><td>12</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>ON</td><td>13</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>OFF</td><td>14</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>ON</td><td>15</td></tr></table>

Table 3-6: Card Number Configuration Settings

Default card number is 15.

# 3.7.2 SSI\_TRIG

As an output, the SSI\_TRIG signal reflects the trigger event signal in an acquisition sequence. As an input, the PCIe-9834 accepts the SSI\_TRIG signal to be the trigger event source. The signal is configured in the rising edge-detection mode.

# 3.8 Multi-boot

The PCIe-9834 supports software-based firmware updates. If firmware updates fail, the system may be unable to recognize the module, in which case the following steps may solve the problem.

1. Config SW2 to "on"
2. Install the module and restart the system
3. If the module is recognized, update firmware again (ensure the firmware you updated is workable)
4. Turn off the system, config SW2 to "off" and restart the system.

The default state of SW2 is "off".

If the problem remains, please contact FAE.

![Top-down schematic of a circuit board layout with component layouts and a highlighted storage unit (no text or symbols)](.pcie-9834-50-11263-1000-200/ce18a791252cd269365710e0e4c78f8e84d3ba786fdf8cbc7aa56b07fc772a9d.jpg)

Figure 3-15: Flash Memory Configuration Switch

# 3.9 Measurement Function API

The PCIe-9834 supports measurement function APIs for easily conversion of basic voltage/time measurement results, with no extra programming required for development of scoping application software.

![| Level               | Value |\n| ------------------- | ----- |\n| Max                 | 100   |\n| Overshoot           | 100   |\n| High Reference Level| 100   |\n| Transition Time     | 50    |\n| Preshoot            | 25    |\n| Low Reference Level| 25    |\n| Min                 | 0     |](.pcie-9834-50-11263-1000-200/9ad7f88f5c8c2b11acf9e1c64ca397679d4d1eff14e65e458b2bcd5cfbe71d00.jpg)

Figure 3-16: Waveform Transition

<table><tr><td>Parameter</td><td>Descr.</td><td>Comments</td><td>Type</td><td>Unit</td></tr><tr><td>max</td><td>Highest waveform value</td><td>Refer to Figure 3-16, “Waveform Transition”</td><td>Double</td><td>V</td></tr><tr><td>min</td><td>Lowest waveform value</td><td>Refer to Figure 3-16, “Waveform Transition”</td><td>Double</td><td>V</td></tr><tr><td>mean</td><td>Arithmetic average value of the waveform</td><td> $(\sum \text{Waveform [i]}/n$ </td><td>Double</td><td>V</td></tr><tr><td>p2p</td><td>Peak to peak</td><td>max - min</td><td>Double</td><td>V</td></tr><tr><td>std</td><td>Standard deviation</td><td> $\sqrt{(\sum \text{Waveform [i]-M}^{2}) / (n-1)}$ </td><td>Double</td><td></td></tr><tr><td>rms</td><td>Root/mean/square</td><td> $\sqrt{\sum \text{Waveform [i]}^{2}/n}$ </td><td>Double</td><td></td></tr><tr><td>period</td><td>Duration of one complete waveform cycle, calculated in WD-DASK via the interval between first and third mid reference level crossings</td><td></td><td>Double</td><td>Sec</td></tr><tr><td>freq</td><td>Reciprocal of period</td><td>1 / period</td><td>Double</td><td>Hz</td></tr><tr><td>negwidth</td><td>Negative pulse width, the duration between two consecutive mid reference level points of a negative waveform pulse</td><td></td><td>Double</td><td>Sec</td></tr><tr><td>poswidth</td><td>Positive pulse width, the duration between two consecutive mid reference level points of a positive waveform pulse</td><td></td><td>Double</td><td>Sec</td></tr><tr><td>negdutycycle</td><td>Negative pulse width/waveform period ratio</td><td>(negwidth/period) *100%</td><td>Double</td><td></td></tr><tr><td>posdutycycle</td><td>Positive pulse width/waveform period ratio</td><td>(poswidth/period) *100%</td><td>Double</td><td></td></tr><tr><td>risetime</td><td>Duration of signal rising from low to high reference level</td><td>Refer to Figure 3-16, “Waveform Transition”</td><td>Double</td><td>Sec</td></tr><tr><td>falltime</td><td>Duration of signal falling from high to low reference level</td><td>Refer to Figure 3-16, “Waveform Transition”</td><td>Double</td><td>Sec</td></tr><tr><td>high</td><td>Voltage high, calculated via histogram, using the voltage of the histogram bin with the maximum number of hits above 60% of the peak-to-peak value of the waveform</td><td>high-&gt;value</td><td>wd_hist_bin</td><td>V</td></tr><tr><td>low</td><td>Voltage low, calculated via histogram, using the voltage of the histogram bin with the maximum number of hits below 40% of the peak-to-peak value of the waveform</td><td>low-&gt;value</td><td>wd_hist_bin</td><td>V</td></tr><tr><td>ampl</td><td>Amplitude, difference between voltage high and voltage low</td><td>vol_high – vol_low Refer to</td><td>Double</td><td>V</td></tr><tr><td>pospreshoot</td><td>Peak distortion preceding a valid positive transition</td><td>((voltage low – local min)/ amplitude)*100%</td><td>Double</td><td></td></tr></table>

<table><tr><td>Parameter</td><td>Descr.</td><td>Comments</td><td>Type</td><td>Unit</td></tr><tr><td>posovershoot</td><td>Peak distortion following a valid positive transition</td><td>((local max – voltage high)/amplitude)*100%</td><td>Double</td><td></td></tr><tr><td>negpreshoot</td><td>Peak distortion preceding a valid negative transition</td><td>((local max – voltage high)/amplitude)*100%</td><td>Double</td><td></td></tr><tr><td>negovershoot</td><td>Peak distortion following a valid negative transition</td><td>((voltage low – local min)/amplitude)*100%</td><td>Double</td><td></td></tr><tr><td>cyclemean</td><td>Arithmetic average of integral number of points in one period</td><td>(ΣWaveform [i]/(points/period)</td><td>Double</td><td>V</td></tr><tr><td>cyclerms</td><td>Rms of integral number of points in one period</td><td> $\sqrt{\sum\text{Waveform [i] }^{2}/(\text{points/period})}$ </td><td>Double</td><td></td></tr><tr><td>fft_ampl</td><td>FFT amplitude</td><td></td><td>Double</td><td>V/rms</td></tr><tr><td>fft_freq</td><td>FFT frequency</td><td></td><td>Double</td><td>Hz</td></tr></table>

Table 3-7: Measurement Parameters

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# Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

# A.1 Calibration Constant

The PCIe-9834 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-9834 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PCIe-9834.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PCIe-9834 boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

# A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PCIe-9834 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PCIe-9834 for at least 20 minutes and remove connected cables.

![The image displays a white sheet of paper icon featuring a folded corner at the top left and horizontal lines near the bottom. A large, bold red checkmark is superimposed over the center of the paper.](.pcie-9834-50-11263-1000-200/fe3dbc9a944c7e8c39c3e862c263aa9932368b4b652f5a7be5c19533e8596f59.jpg)
NOTE:

It is not necessary to manually factor delay into applications, as the PCIe-9834 driver automatically adds the compensation time.

![The diagram is titled **PCIe-9834** in the top right corner. It depicts a signal processing architecture with the following labeled blocks and connections:\n\n*   **Inputs:** On the far left, there are cylindrical symbols representing signal channels, connected to ground. Vertical dotted lines below them indicate additional channels.\n*   **Calibration Source:** At the top, a circle labeled **Onboard Calibration Source** (with + and - terminals) connects via a line to a vertical bus.\n*   **Switches:** Two rectangular boxes are positioned in the center. They are labeled **Switch** and **Signal Path / Internal Calibration Source**.\n    *   The vertical bus from the calibration source connects to the top input terminal of both switches.\n    *   The cylindrical inputs connect to the bottom input terminal of their respective switches.\n    *   The upper switch is depicted connecting the top terminal (calibration source) to the output.\n    *   The lower switch is depicted connecting the bottom terminal (signal path) to the output.\n*   **Amplifiers:** The outputs of the switches connect to two triangular amplifier symbols labeled **Analog Front End**.\n*   **ADC:** The outputs from the **Analog Front End** amplifiers connect to a block labeled **ADC**.](.pcie-9834-50-11263-1000-200/4c0ef5dc686318b769c7ab2df96eb6019d79881ceaee169db973faa6974d468a.jpg)

Figure A-1: Auto-Calibration Block Diagram

![**Labeled Blocks:**\n\n*   Auto-calibration start\n*   Set analog front end input to onboard calibration source\n*   Set calibration source to ground\n*   Capture data and calculate offset compensation parameters\n*   Are all channels and all ranges complete?\n*   Set calibration source to calibration voltage\n*   Capture data and calculate gain compensation parameters\n*   Are all channels and all ranges complete?\n*   Set analog front end input to SMB connector\n*   Auto-calibration complete\n\n**Connections:**\n\n*   **Auto-calibration start** connects to **Set analog front end input to onboard calibration source**.\n*   **Set analog front end input to onboard calibration source** connects to **Set calibration source to ground**.\n*   **Set calibration source to ground** connects to **Capture data and calculate offset compensation parameters**.\n*   **Capture data and calculate offset compensation parameters** connects to **Are all channels and all ranges complete?**\n*   From **Are all channels and all ranges complete?**, a 'No' path loops back to **Capture data and calculate offset compensation parameters**.\n*   From **Are all channels and all ranges complete?**, a 'Yes' path extends downward and upward to connect to **Set calibration source to calibration voltage**.\n*   **Set calibration source to calibration voltage** connects to **Capture data and calculate gain compensation parameters**.\n*   **Capture data and calculate gain compensation parameters** connects to **Are all channels and all ranges complete?**\n*   From the second **Are all channels and all ranges complete?**, a 'No' path loops back to **Capture data and calculate gain compensation parameters**.\n*   From the second **Are all channels and all ranges complete?**, a 'Yes' path connects to **Set analog front end input to SMB connector**.\n*   **Set analog front end input to SMB connector** connects to **Auto-calibration complete**.](.pcie-9834-50-11263-1000-200/73efb6520833a284181dfaa015377faaa287c529f87dfa6c2b91d0fe75845cce.jpg)

Figure A-2: Auto-Calibration Flow

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# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
▶ A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a warning sign featuring a red triangle pointing upwards with a white exclamation point in its center. Below the triangle is a white rectangular box containing the word 'WARNING' in black, uppercase letters.](.pcie-9834-50-11263-1000-200/d3d86c41d5ff6def1d5bd42e97a62cb7b04cb328644676840e5e04d85bebbc71.jpg)

Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110
San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
Rm. 801, Power Creative E, No. 1 Shang Di East Rd.
Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8626

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园
A1 栋 2 楼 C 区 (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7
High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11
D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

# PENTA ADLINK Technology GmbH

Ulrichsbergerstrasse 17
94469 Deggendorf, Germany

Tel: +49 (0) 991 290 94 - 10

Fax: +49 (0) 991 290 94 - 29

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 6 allée de Londres, Immeuble Ceylan
91940 Les Ulis, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町3-7-4
神田374ビル4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 경기도 성남시 분당구 수내로 46 번길 4 경동빌딩 2 층 (수내동 4-4 번지) (우) 463-825
2F, Kyungdong B/D, 4 Sunae-ro 46 beon-gil
Bundang-gu, Seongnam-si, Gyeonggi-do, Korea, 463-825

Toll Free +82-80-800-0585

Tel +82-31-786-0585

Fax +82-31-786-0583

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: #50-56, First Floor, Spearhead Towers Margosa Main Road (between 16th/17th Cross) Malleswaram, Bangalore - 560 055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 27 Maskit St., Corex Building
PO Box 12777
Herzliya 4673300, Israel

Tel: +972-54-632-5251

Fax: +972-77-208-0230

Email: israel@adlinktech.com

# ADLINK Technology, Inc. (UK Liaison Office)

Tel: +44 774 010 59 65

Email: UK@adlinktech.com
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