# PCIe-9852

# 2-CH 14-Bit 200 MS/s digitizer

# User's Manual

![Green printed circuit board (PCB) with gold connectors and various electronic components, no visible text or symbols on the board itself.](.pcie-9852-50-11041-1000-200-en/a61363c61a876b7ea973f09fd43247605295118dacde8d8b67d918664ba48dd4.jpg)

Manual Rev.: 2.00

Revision Date: May 20, 2013

Part No: 50-11041-1000

![Circular black-and-white recycling symbol with three white arrows forming a triangle (no text or symbols)](.pcie-9852-50-11041-1000-200-en/f5da099005b9e8c7e909a8deb7aab511eabe07302bc9164059548f98af0d5a87.jpg)

Recycled Paper

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2013/05/20</td><td>Initial Release</td></tr></table>

# Preface

# Copyright 2013 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a white document icon with the top-right corner folded over. Faint gray horizontal lines appear near the bottom of the page. A large, red checkmark is superimposed over the left and center of the document.](.pcie-9852-50-11041-1000-200-en/8fe56cc7ddfe99d30a5338a9c5c7c12d3d286adb4327a9a5a439663f6db25646.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text reads 'CAUTION:'.](.pcie-9852-50-11041-1000-200-en/1c85f623fa5fa1b45e3dd42853bad8d4fdea9363d881ee458aa1f440e3ee489d.jpg)

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning sign. It features a red triangle with a thin black border containing a large white exclamation point. Below the triangle, on a white background, is the word 'WARNING' in black, uppercase letters.](.pcie-9852-50-11041-1000-200-en/10d37ff056f6640429c859ff74877cda19ea069a094f8315506034ea0c90d61d.jpg)

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface...... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2

1.3.1 Analog Input 2
1.3.2 Timebase 4
1.3.3 Triggers 5
1.3.4 General Specifications....6

1.4 Software Support 6

1.4.1 SDK 7
1.4.2 WD-DASK....7

1.5 Device Layout and I/O Array 8

# 2 Getting Started 11

2.1 Installation Environment 11
2.2 Installing the Module 12

# 3 Operations 13

3.1 Functional Block Diagram.... 13
3.2 Analog Input Channel 13

3.2.1 Analog Input Front-End Configuration 13
3.2.2 Input Range and Data Format 14
3.2.3 DMA Data Transfer....14

3.3 Trigger Source and Trigger Modes.... 16

3.3.1 Software Trigger 17

3.3.2 External Digital Trigger 17
3.3.3 Analog Trigger 18
3.3.4 Trigger Export 18

# 3.4 Trigger Modes.... 18

3.4.1 Post Trigger Mode 18
3.4.2 Delayed Trigger Mode 18
3.4.3 Pre-Trigger Mode....19
3.4.4 Middle Trigger Mode....20
3.4.5 Acquisition with Re-Triggering 20
3.4.6 Data Average Mode
(Post-Trigger and Delayed-Trigger only)....21

# 3.5 Timebase 21

3.5.1 Internal Reference Clock 21
3.5.2 External Reference Clock....22
3.5.3 External Sampling Clock....22

# 3.6 ADC Timing Control 22

3.6.1 Timebase Architecture....22
3.6.2 Basic Acquisition Timing....22

# 3.7 Synchronizing Multiple Modules 25

3.7.2 SSI Timebase 28
3.7.3 SSI\_TRIG 28
3.7.4 SSI\_pre\_data\_rdy....28

# A Appendix: Calibration.... 29

A.1 Calibration Constant 29
A.2 Auto-Calibration 29

# Important Safety Instructions.... 31

# Getting Service 33

# List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp....3

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp......4

Figure 1-3: PCIe-9852 Schematic....8

Figure 1-4: PCIe-9852 I/O Array 9

Figure 3-1: Analog Input Architecture of the PCIe-9852 ...... 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ..... 16

Figure 3-3: Trigger Architecture of the PCIe-9852....16

Figure 3-4: External Digital Trigger 17

Figure 3-5: Post-Trigger Acquisition .... 18

Figure 3-6: Delayed Trigger Mode Acquisition....19

Figure 3-7: Pre-Trigger Mode Acquisition 19

Figure 3-8: Middle Trigger Mode Acquisition ....20

Figure 3-9: Re-Trigger Mode Acquisition 21

Figure 3-10: PCIe-9852 Clock Architecture 21

Figure 3-11: PCIe-9852 Timebase Architecture 22

Figure 3-12: Basic Digitizer Acquisition Timing....23

Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter ..... 24

Figure 3-14: Card Number Configuration Switch 27

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# List of Tables

Table 1-1: Channel Characteristics....3
Table 1-2: Timebase 5
Table 1-3: Trigger Source & Mode......5
Table 1-4: Digital Trigger Input 5
Table 1-5: Digital Trigger Output....6
Table 1-6: PCIe-9852 I/O Array Legend 10
Table 3-1: Input Range and Data Format 14
Table 3-2: Input Range FSR and -FSR Values....14
Table 3-3: Input Range Midscale Values....14
Table 3-4: Counter Parameters and Description ...... 25
Table 3-5: SSI Signal Location and Pin Definition 26
Table 3-6: Card Number Configuration Settings....28

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# 1 Introduction

The PCIe-9852 is a high-speed 2-CH 14-Bit 200 MS/s digitizer, specifically designed for applications such as LIDAR testing, optical fiber testing and radar signal acquisition. Analog input with 90 MHz bandwidth receives $\pm10V$ high speed signals with 50 $\Omega$ impedance, and a simplified front-end design and highly stable onboard reference provide both highly accurate measurement results and high dynamic performance.

Ideal for environments requiring real-time acquisition and transfer of data, the PCIe-9852 is based on the PCI Express Gen 2 x4 bus as interface. When signals are converted from analog to digital, continual data transfer to host system memory is enabled by PCI Express high bandwidth capability.

The PCIe-9852 is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following auto-calibration, the calibration constant is stored in EEPROM, such that these values can be loaded and used as needed by the board. There is no requirement to calibrate the module manually.

# 1.1 Features

▶ PCI Express specification Rev. 2.0 compliant
▶ Up to 200 MS/s sampling rate
▶ 2 simultaneous analog inputs
▶ High resolution 14-Bit ADC
▶ Up to 90 MHz bandwidth for analog input
▶ One GB onboard storage memory
▶ Scatter-Gather DMA data transfer for high-speed data streaming
▶ Supports signal averaging
▶ Support for:

▶ one external digital trigger input
▶ one digital trigger output to external instrument
▷ one external clock input
▷ auto-calibration

# 1.2 Applications

▶ Distributed Temperature Sensing (DTS)
▶ Video IC testing
▶ Physics laboratory and research environments
▶ Cable fault location and partial discharge monitoring for power applications

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td colspan="2">Channel Characteristics</td><td>Comment</td></tr><tr><td>Channels</td><td>2 single-ended</td><td></td></tr><tr><td>Connector type</td><td>SMA</td><td></td></tr><tr><td>Input coupling</td><td>AC or DC, software selectable</td><td></td></tr><tr><td>AC coupling cutoff frequency</td><td>11Hz</td><td></td></tr><tr><td>ADC resolution</td><td>14-Bit</td><td></td></tr><tr><td>Inout signal range</td><td>±0.2 V, ±2 V, or ±10 V</td><td></td></tr><tr><td>Bandwidth (-3dB)</td><td>90MHz</td><td></td></tr><tr><td rowspan="2">Overvoltage</td><td>±10V</td><td>1MΩ</td></tr><tr><td>±10V sine wave / 7Vrms for</td><td>50Ω</td></tr><tr><td>Input impedance</td><td>50 Ω or 1MΩ, software selectable</td><td></td></tr><tr><td>Offset error</td><td>±1 mV</td><td></td></tr><tr><td>Gain error</td><td>±0.65%</td><td></td></tr><tr><td rowspan="4">SNR</td><td>56dB</td><td>1MΩ, ±0.2 V</td></tr><tr><td>62dB</td><td>1MΩ, ±2 V</td></tr><tr><td>60dB</td><td>50Ω, ±0.2 V</td></tr><tr><td>62dB</td><td>50Ω, ±2 V</td></tr></table>

<table><tr><td colspan="2">Channel Characteristics</td><td>Comment</td></tr><tr><td rowspan="4">THD</td><td>-73dBc</td><td>1MΩ, ±0.2 V</td></tr><tr><td>-69dBc</td><td>1MΩ, ±2 V</td></tr><tr><td>-73dBc</td><td>50Ω, ±0.2 V</td></tr><tr><td>-69dBc</td><td>50Ω, ±2 V</td></tr><tr><td>SFDR</td><td>-72dBc</td><td>1MΩ, ±0.2 V</td></tr><tr><td></td><td>-72dBc</td><td>1MΩ, ±2 V</td></tr><tr><td></td><td>-68dBc</td><td>50Ω, ±0.2 V</td></tr><tr><td></td><td>-68dBc</td><td>50Ω, ±2 V</td></tr><tr><td>Crosstalk</td><td>-80dBc</td><td>±0.2 V, ±2 V</td></tr></table>

Table 1-1: Channel Characteristics

![| Frequency (Hz) | Magnitude (dB) |\n| -------------- | -------------- |\n| 0.1M           | 0.0            |\n| 0.3M           | 0.0            |\n| 1M             | 0.0            |\n| 3M             | 0.0            |\n| 10M            | 0.0            |\n| 30M            | -1.0           |\n| 100M           | -4.0           |\n| 300M           | -9.0           |](.pcie-9852-50-11041-1000-200-en/4d806edc325d786f1edf8d6701e899eabc377a272d84ae6efd059acf97a245de.jpg)

Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp

![| Frequency (Hz) | Magnitude (dB) |\n| -------------- | -------------- |\n| 0.1M           | 0              |\n| 0.3M           | 0              |\n| 1M             | 0              |\n| 3M             | 0              |\n| 10M            | 0              |\n| 30M            | -1             |\n| 100M           | -4             |\n| 300M           | -9             |](.pcie-9852-50-11041-1000-200-en/d0ffb158ed67376f5f2c4d4c39f0af69f3f92b5e8a96a6bcab36957145cc46b6.jpg)

Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp

# 1.3.2 Timebase

<table><tr><td colspan="2">Sample Clock</td><td>Comment</td></tr><tr><td rowspan="2">Timebase options</td><td>Internal : on board synthesizer</td><td></td></tr><tr><td>External : CLK IN (front panel), SSI</td><td></td></tr><tr><td rowspan="2">Sampling clock frequency</td><td>Internal : 200MHz</td><td>3.052kS/s to 200MS/s</td></tr><tr><td>External : 40MHz ~ 200MHz (CLK IN)</td><td></td></tr><tr><td>Timebase accuracy</td><td>&lt; ± 25ppm</td><td></td></tr><tr><td>External reference clock source</td><td>Front panel, SSI</td><td></td></tr></table>

<table><tr><td colspan="2">Sample Clock</td><td>Comment</td></tr><tr><td>External reference clock</td><td>10MHz</td><td></td></tr><tr><td>External reference clock input range</td><td>500mVpp ~ 5Vpp</td><td>AC / DC compliant</td></tr><tr><td>External sampling clock input range</td><td>1Vpp ~ 5Vpp</td><td>AC / DC compliant</td></tr></table>

Table 1-2: Timebase

# 1.3.3 Triggers

<table><tr><td colspan="2">Trigger Source &amp; Mode</td></tr><tr><td>Trigger source</td><td>Software, external digital trigger, analog trigger, and SSI (system synchronized interface)</td></tr><tr><td>Trigger mode</td><td>Post trigger, delay trigger, pre-trigger, or middle trigger, re-trigger for post trigger and delay trigger modes</td></tr></table>

Table 1-3: Trigger Source & Mode

<table><tr><td colspan="2">Digital Trigger Input</td></tr><tr><td>Sources</td><td>Front panel SMA connector</td></tr><tr><td>Compatibility</td><td>3.3 V TTL, 5 V tolerant</td></tr><tr><td>Input high threshold</td><td>2.0 V</td></tr><tr><td>Input low threshold (VIL)</td><td>0.8 V</td></tr><tr><td>Maximum input overload</td><td>-0.5 V ~ +5.5 V</td></tr><tr><td>Trigger polarity</td><td>Rising or falling edge</td></tr><tr><td>Pulse width</td><td>20 ns minimum</td></tr></table>

Table 1-4: Digital Trigger Input

<table><tr><td colspan="2">Digital Trigger Output</td></tr><tr><td>Compatibility</td><td>5 V TTL</td></tr><tr><td>Output high threshold (VOH)</td><td>2.4 V</td></tr><tr><td>Output low threshold (VOL)</td><td>0.2 V</td></tr></table>

<table><tr><td colspan="2">Digital Trigger Output</td></tr><tr><td>Trigger polarity</td><td>Positive or negative</td></tr><tr><td>Pulse width</td><td>50 ns, 100 ns, 150 ns, 200 ns, 500 ns, 1 μs, 2 μs, 7.5 μs, and 10 μs</td></tr><tr><td>Trigger output driving capacity</td><td>Capable of driving 50Ω load</td></tr></table>

Table 1-5: Digital Trigger Output

# 1.3.4 General Specifications

<table><tr><td colspan="2">Specifications</td></tr><tr><td>Physical dimensions</td><td>167.64 W x 106.68 H mm (6.53 x 4.16 in)</td></tr><tr><td>Bus</td><td></td></tr><tr><td>Bus interface</td><td>PCI Express Gen 2 x 4</td></tr><tr><td colspan="2">Environmental tolerance</td></tr><tr><td>Operating</td><td>Temperature: 0°C - 50°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td>Storage</td><td>Temperature: -20°C - +80°CRelative humidity: 5% - 95%, non-condensing</td></tr></table>

<table><tr><td colspan="2">Calibration</td></tr><tr><td>Onboard reference</td><td>+5 V and +2.5 V</td></tr><tr><td>Temperature coefficient</td><td>3.0 ppm/°C</td></tr><tr><td>Warm-up time</td><td>15 minutes</td></tr></table>

<table><tr><td colspan="3">Power Consumption</td></tr><tr><td>Power Rail</td><td>Standby Current (mA)</td><td>Full Load (mA)</td></tr><tr><td>+3.3 V</td><td>102</td><td>102.2</td></tr><tr><td>+12 V</td><td>20</td><td>20</td></tr><tr><td>+5V</td><td>1920</td><td>2010</td></tr></table>

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW $^{®}$ .

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license.

# 1.4.1 SDK

For customers who want to write their own programs, ADLINK provides the following software development kits.

▶ DAQPilot for Windows, compatible with various application environments, such as VB.NET, VC.NET, VB/VC++, BCB, and Delphi
▶ DAQPilot for LabVIEW
▶ Toolbox adapter for MATLAB

# 1.4.2 WD-DASK

WD-DASK includes device drivers and DLL for Windows XP/7/8. DLL is binary compatible across Windows XP/7/8. This means all applications developed with WD-DASK are compatible with these Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The WD-DASK user and function reference manuals are on the ADLINK All-in-One CD.

# 1.5 Device Layout and I/O Array

![The image displays a simple icon representing a document or checklist. It features a white piece of paper with a folded top-right corner and faint horizontal lines running across the surface. A large, bold red checkmark is superimposed over the paper, slanting upwards from the bottom left to the top right.](.pcie-9852-50-11041-1000-200-en/e0efd3909122be0d4f736d15e0d1843b343bef1d2b537b5f85d7e8f85b719c20.jpg)
NOTE:

All dimensions are in mm

![174.52\n100.36\n59.05\n176.42\n111.15](.pcie-9852-50-11041-1000-200-en/c7ca99c544469ffb8017d69f50285cb8aa6cdd80bbefeaa148bf4f5f9eb920d9.jpg)

Figure 1-3: PCIe-9852 Schematic

The PCIe-9852 I/O array is labeled to indicate connectivity, as shown.

![CH0\nCH1\nCLK IN\nTRG IN\nTRG OUT\nCH0\nCH1](.pcie-9852-50-11041-1000-200-en/f387018c6d80860f47800c12dd4fd1c5745df0c946262ddd0e6ae784fc722ff3.jpg)

Figure 1-4: PCIe-9852 I/O Array

<table><tr><td>Name</td><td>Faceplate Legend</td><td>Type</td><td>Remark</td></tr><tr><td>CH0</td><td>N/A</td><td>Blue</td><td>On indicates CH0 acquisition ongoingOff indicates CH0 acquisition stopped</td></tr><tr><td>CH1</td><td>N/A</td><td>Blue</td><td>On indicates CH1 acquisition ongoingOff indicates CH1 acquisition stopped</td></tr></table>

<table><tr><td>Name</td><td>Faceplate Legend</td><td>Type</td><td>Remark</td></tr><tr><td>Ext. Clock Input</td><td>CLK IN</td><td rowspan="5">SMA Screw</td><td>Input for external reference clock or sample clock to digitizer</td></tr><tr><td>Ext. Digital Trigger Input</td><td>TRG IN</td><td>External digital trigger input, receiving trigger signal from external instrument and initiating acquisition</td></tr><tr><td>Trigger Output</td><td>TRG OUT</td><td>Trigger output, in which every time acquisition begins, a pulse synchronized with Timebase clock asserts and is output through this connector, at pulse width programmable from 50ns to 10μs via software</td></tr><tr><td>Analog Input</td><td>CH0</td><td>Analog input channel</td></tr><tr><td>Analog Input</td><td>CH1</td><td>Analog input channel</td></tr></table>

Table 1-6: PCIe-9852 I/O Array Legend

# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PCIe-9852.

![The image features a white document icon with a folded upper right corner. Faint horizontal lines suggest text on the page. A large red checkmark is superimposed over the document, running diagonally from the bottom left to the top right.](.pcie-9852-50-11041-1000-200-en/ab81f6f6e59a59c533c05e6d5d2f6196d8d06449d2a083639ed36c9db31001e5.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

▶ Phillips (cross-head) screwdriver
▶ Flat-head screwdriver
Anti-static wrist strap
▶ Antistatic mat

ADLINK PCIe-9852 DAQ modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the sign, the text 'CAUTION:' is printed in black capital letters.](.pcie-9852-50-11041-1000-200-en/bfd8b4e7b414a6e90bb074e9ed504214d64b136bf642a70f6c1775d9ed5cc030.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

▶ Package Contents
▶ PCIe-9852 high-speed digitizer
▶ ADLINK All-in-one compact disc
▶ PCIe-9852 Quick Start Guide

If any of these items are missing or damaged, contact the dealer

![The image displays a triangular warning sign with a black border. The interior of the triangle features a gradient background that transitions from white at the top to red at the bottom. Centered within the triangle is a large black exclamation point. Below the triangle, the word 'WARNING' is printed in bold, black, uppercase letters.](.pcie-9852-50-11041-1000-200-en/a18baee15df202179508f2d8bc1df9b0e3f48630fb4f057b91ffa4910603af64.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Installing the Module

1. Turn off the computer.
2. Remove the top cover.
3. Select an available PCI express x4 slot and remove the bracket-retaining screw and the bracket cover.
4. Line up the PCI express digitizer with the PCI express slot on the back panel. Slowly push down on the top of the PCI express digitizer until its card-edge connector is resting on the slot receptacle.
5. Install the bracket-retaining screw to secure the PCI express digitizer to the back panel rail.
6. Replace the computer cover.

# 3 Operations

This chapter contains information regarding analog input, triggering and timing for the PCIe-9852.

# 3.1 Functional Block Diagram

![This flowchart depicts a signal processing system divided into two main sections: a 'Daughter Board' (blue background) and a 'Carrier Board' (light blue background).\n\n**Labeled Blocks:**\n*   **Daughter Board:** CH0, CH1, CLK IN, TRG IN, buffer, TRG OUT, Analog Front End, Calibration CKT, 14 bit ADC, Synthesizer, B to B High Speed Interface.\n*   **Carrier Board:** Carrier Board (label), Daughter Board (label), AUX DIO Port, FPGA (label), ADC Interface, FIFO, Trigger Interface, Local Bus Interface, PCI Express Controller, PCI Express BUS (label).\n\n**Connections:**\n*   **CH0** and **CH1** connect to **Analog Front End**.\n*   **Analog Front End** connects to **14 bit ADC**.\n*   **Calibration CKT** connects to both **Analog Front End** and **14 bit ADC**.\n*   **Synthesizer** connects to **14 bit ADC**.\n*   **CLK IN** connects to **Synthesizer**.\n*   **TRG IN** connects to a **buffer**, which connects to **B to B High Speed Interface**.\n*   **B to B High Speed Interface** connects to a **buffer**, which connects to **TRG OUT**.\n*   **B to B High Speed Interface** sends signals to the FPGA area, connecting to **ADC Interface** and **Trigger Interface**.\n*   Inside the **FPGA** (dashed box):\n    *   **Local Bus Interface** connects to **PCI Express Controller**.\n    *   **PCI Express Controller** connects bidirectionally to **PCI Express BUS**.\n*   **AUX DIO Port** is an isolated block at the top right.](.pcie-9852-50-11041-1000-200-en/34ffe581006ae0178a310b95bf1238d1b0c46852e4914b38682c135bf96e6383.jpg)

# 3.2 Analog Input Channel

# 3.2.1 Analog Input Front-End Configuration

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   Calibration Source\n*   Protectionckt\n*   AC/DC Couple\n*   50Ω / Hi-Z\n*   High Impedance Buffer\n*   1x / 10x amplifier\n*   ADC Driver\n*   100MHz LPF\n*   14-bit ADC\n\n**Connections:**\n*   An input connector connects to the **Protectionckt**.\n*   The **Protectionckt** connects to a switch.\n*   The **Calibration Source** also connects to this switch.\n*   The switch connects to the **AC/DC Couple**.\n*   The **AC/DC Couple** connects to the **50Ω / Hi-Z**.\n*   The **50Ω / Hi-Z** connects to the **High Impedance Buffer**.\n*   The **High Impedance Buffer** connects to the **1x / 10x amplifier**.\n*   The **1x / 10x amplifier** connects to the **ADC Driver**.\n*   The **ADC Driver** connects to the **100MHz LPF**.\n*   The **100MHz LPF** connects to the **14-bit ADC**.\n*   The **14-bit ADC** outputs a line labeled **14**.](.pcie-9852-50-11041-1000-200-en/4a1a60b468349fafe2d34f441531352d3b075b65540118fc86ea69ad88b37142.jpg)

Figure 3-1: Analog Input Architecture of the PCIe-9852

# Input Configuration

The input channel terminates with equivalent 50Ω or 1 MΩ input impedance (selected by software). The 14-bit ADC provides not only accurate DC performance but also high signal-to-noise ratio, and high spurious-free dynamic range in AC performance. The ADC transfers data to system memory via the high speed PCI Express Gen2 X 4 interface.

For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI.

# 3.2.2 Input Range and Data Format

Data format of the PCIe-9852 is 2's complement. The ADC data of PCIe-9852 is on the 14 MSB of the 16-bit A/D data. The 2 LSB of the 16-bit A/D data should be truncated by software. A/D data structure is as follows.

<table><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>....</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td colspan="9">D15 ~ D2 bits represent the data from ADC (2&#x27;s complement)D1, D0 bits are always 0.</td></tr></table>

Table 3-1: Input Range and Data Format

<table><tr><td>Description</td><td>Full scale range</td><td>Least significant bit</td><td>FSR-1LSB</td><td>-FSR</td></tr><tr><td rowspan="3">Bipolar Analog Input</td><td>±10V</td><td>1.22mV</td><td>9.99878V</td><td>-10.000V</td></tr><tr><td>±2V</td><td>0.244mV</td><td>1.99976V</td><td>-2V</td></tr><tr><td>±0.2V</td><td>24.4uV</td><td>0.199976V</td><td>-0.2V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FFC</td><td>8000</td></tr></table>

Table 3-2: Input Range FSR and -FSR Values

<table><tr><td>Description</td><td></td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale -1LSB</td></tr><tr><td rowspan="3">Bipolar Analog Input</td><td>±10V</td><td>1.22mV</td><td>0V</td><td>-1.22mV</td></tr><tr><td>±2V</td><td>0.244mV</td><td>0V</td><td>-0.244mV</td></tr><tr><td>±0.2V</td><td>24.4V</td><td>0V</td><td>-24.4μV</td></tr><tr><td>Digital Code</td><td></td><td>0001</td><td>0000</td><td>FFFC</td></tr></table>

Table 3-3: Input Range Midscale Values

# 3.2.3 DMA Data Transfer

The PCIe-9852, a PCIe Gen 2 X 4 device, is equipped with a 200MS/s high sampling rate ADC, generating a 800 MByte/second rate.

To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list so users can transfer large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. Figure 3-2 illustrates a linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space.

![The diagram illustrates a data flow involving memory and address descriptors across a bus.\n\n**Bottom to Top Connections:**\n*   A block labeled **'Local Memory (FIFO)'** connects via an upward-pointing arrow to a wider block labeled **'PCI Express Bus'**.\n*   The **'PCI Express Bus'** connects via an upward-pointing arrow to the central block in the top row.\n\n**Top Row Sequence (Left to Right):**\n*   **Left Block:** Contains the text:\n    *   First PCI Address\n    *   First Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n    *   An arrow points from this block to the central block.\n*   **Central Block:** Contains the text:\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n    *   An arrow points from this block to the rightmost block.\n*   **Right Block:** Contains the text:\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor](.pcie-9852-50-11041-1000-200-en/587631fe54cbd7e02f8c79384c753f0a68e87d441b2e8792e11b0a720b22dbda.jpg)

Figure 3-2: Linked List of PCI Address DMA Descriptors

# 3.3 Trigger Source and Trigger Modes

This section details PCIe-9852 triggering operations.

![This block diagram illustrates a signal processing flow involving trigger inputs and outputs.\n\n**Labeled Blocks:**\n*   A large vertical trapezoidal block on the left.\n*   A rectangular block labeled **Trigger Decision**.\n*   A trapezoidal block labeled **Trigger Output MUX**.\n\n**Input Labels:**\n*   **Software trigger**\n*   **Digital trigger input**\n\n**Connections and Flow:**\n1.  **Inputs:** The lines labeled **Software trigger** and **Digital trigger input** point into the left vertical trapezoidal block.\n2.  **Trigger Decision:** An arrow exits the left trapezoidal block and points to the **Trigger Decision** block.\n3.  **Split:** From the **Trigger Decision** block, the path splits:\n    *   One arrow points right, labeled **To Internal FPGA circuits**.\n    *   Another arrow points down and enters the top-left side of the **Trigger Output MUX** block.\n4.  **Outputs:** From the **Trigger Output MUX** block:\n    *   One arrow exits the top right and points to a connector symbol.\n    *   One thick arrow exits the bottom right and points to the label **ISS**.](.pcie-9852-50-11041-1000-200-en/fdab262face39340ee4894291bbdf467103f458777e5b86e7005d1c83914a403.jpg)

Figure 3-3: Trigger Architecture of the PCIe-9852

The PCIe-9852 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-9852 supports internal software trigger, external digital trigger, and analog trigger.

# 3.3.1 Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

# 3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL rising edge or falling edge is detected at the SMA connector TRG IN on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 20 ns.

![The image displays two side-by-side diagrams illustrating digital signal concepts.\n\n**Left Diagram:**\n*   **Top Text:** 'Pulse Width ) 20ns'\n*   **Graphic:** A horizontal line with arrows pointing in opposite directions, indicating a duration. Below this is a square wave pulse showing a sharp rise and fall. An arrow points upwards at the leading edge of the pulse.\n*   **Bottom Text:** 'Rising Edge Trigger Event'\n\n**Right Diagram:**\n*   **Top Text:** 'Pulse Width ) 20ns'\n*   **Graphic:** A horizontal line with arrows pointing in opposite directions, indicating a duration. Below this is a square wave pulse showing a sharp rise and fall. An arrow points downwards at the trailing edge of the pulse.\n*   **Bottom Text:** 'Falling Edge Trigger Event'](.pcie-9852-50-11041-1000-200-en/4bc62e1d97fd4c89409f7d459c18fbd2412d79c8b81e4af2f78d3c1d4d852e5a.jpg)
Figure 3-4: External Digital Trigger

# 3.3.3 Analog Trigger

An analog trigger is generated when AI input signal level is detected at the SMA connector CH0, CH1 (selected by software). The trigger level is also selected by software.

# 3.3.4 Trigger Export

When acquisition is initiated, a pulse synchronized with the Time-base clock asserts and is output through trigger output, at a pulse width programmable from 50ns to 10 $\mu$ s via software.

# 3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input function.

# 3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PCIe-9852 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. The acquisition stops once the total data amount reaches a predefined value.

![This image is a timing diagram illustrating a data acquisition sequence. It consists of three horizontal levels aligned along a timeline:\n\n1.  **Top Timeline:** A horizontal arrow pointing right is labeled **'Time'**. Three downward-pointing arrows mark specific events:\n    *   **'Operation start'**\n    *   **'Trigger Event Occurs Acquisitions start'** (The text is stacked on two lines).\n    *   **'Acquisition stop'**\n\n2.  **Trigger Signal:** Labeled **'Trigger'** on the left, this line remains low until it forms a rectangular pulse that aligns vertically with the 'Trigger Event Occurs' marker.\n\n3.  **Data Signal:** Labeled **'Data'** on the left, this line features a rectangular box labeled **'N samples'**. The left edge of this box aligns with the rising edge of the Trigger pulse, and the right edge aligns with the 'Acquisition stop' marker.](.pcie-9852-50-11041-1000-200-en/4997b0e8e0a18711dae9d1f0331c75d9c91bdb6efb65cca2215cfdedc7333647.jpg)

Figure 3-5: Post-Trigger Acquisition

# 3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When PCIe-9852 receives a trigger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X ( $2^{16}$ ), and the minimum is the Timebase period.

![The diagram illustrates a timing sequence across three distinct sections:\n\n**Top Section (Timeline):**\n*   A horizontal line with an arrow pointing right is labeled **Time**.\n*   Four downward-pointing arrows mark specific points on the timeline. From left to right, the text above these arrows reads: **Operation start**, **Trigger Event Occurs**, **Acquisition start**, and **Acquisition stop**.\n*   Between the **Trigger Event Occurs** and **Acquisition start** markers, a horizontal line segment is labeled **Delay Time**.\n\n**Middle Section:**\n*   A signal line labeled **Trigger** shows a single rectangular pulse. The rising edge of this pulse aligns vertically with the **Trigger Event Occurs** marker.\n\n**Bottom Section:**\n*   A signal line labeled **Data** contains a rectangular block labeled **N samples**.\n*   The left edge of the **N samples** block aligns with **Acquisition start**.\n*   The right edge of the **N samples** block aligns with **Acquisition stop**.](.pcie-9852-50-11041-1000-200-en/9fc94e9288e6d3e1561b3af70f69e59edec9d20081eb8c65eab10a2943dd74b0.jpg)

Figure 3-6: Delayed Trigger Mode Acquisition

# 3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.

![This image is a timing diagram illustrating a data acquisition process. It consists of three parallel tracks aligned along a horizontal axis labeled **Time**.\n\n**Top Track (Timeline & Annotations):**\n*   A horizontal arrow pointing right represents the flow of time.\n*   **First Annotation:** An arrow points to the start of the timeline. The text reads:\n    'Operation start\n    Acquisition start'\n*   **Second Annotation:** An arrow points to a location further along the timeline, accompanied by vertical dotted lines. The text reads:\n    'Trigger signals occurring before the specified amount of data has been acquired are ignored'\n*   **Third Annotation:** An arrow points to the end of the timeline. The text reads:\n    'Trigger Event Occurs\n    Acquisition stop\n    Data transfer to system begins'\n\n**Middle Track (Signal):**\n*   Labeled **Trigger**.\n*   It displays a square wave signal. A pulse aligns vertically with the 'Trigger signals occurring before...' annotation. A second pulse aligns vertically with the 'Trigger Event Occurs...' annotation.\n\n**Bottom Track (Data Buffer):**\n*   Labeled **Data**.\n*   It displays a long rectangular bar representing the data buffer.\n*   The left portion of the bar is hatched with diagonal lines. Below it, a double-headed arrow indicates the span, with text reading: 'X samples have been acquired before trigger occurs, where X(N'.\n*   The remainder of the bar (extending to the end of the timeline) is empty and labeled: 'N samples'.](.pcie-9852-50-11041-1000-200-en/2e8b1f1691c2413a674cf92557482f4429f02392caec3230f473ac61dbfe1fbe.jpg)

Figure 3-7: Pre-Trigger Mode Acquisition

# 3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to be collected set individually (M and N samples), as follows

![This diagram illustrates a timeline of events related to data acquisition and triggering. It consists of three aligned horizontal sections:\n\n**1. Top Timeline:**\nA horizontal arrow labeled **'Time'** indicates the passage of time. Three downward arrows mark specific events:\n*   The first arrow is labeled **'Operation start'** and **'Acquisition start'**.\n*   The second arrow is labeled **'Trigger event occurs'**.\n*   The third arrow is labeled **'Acquisition stop'** and **'Data transfer to system begins'**.\n\n**2. Middle Section (Trigger Signal):**\nA line labeled **'Trigger'** shows a signal. A square pulse rises and falls. The rising edge of this pulse aligns vertically with the **'Trigger event occurs'** marker.\n\n**3. Bottom Section (Data):**\nA sequence of blocks labeled **'Data'** represents the data buffer. From left to right, there are three adjacent blocks:\n*   A rectangle filled with diagonal hatching.\n*   A rectangle labeled **'M samples'**.\n*   A rectangle labeled **'N samples'**.\n\n**Connections and Alignments:**\n*   The **'Operation start'** marker aligns with the beginning of the hatched data block.\n*   The **'Trigger event occurs'** marker aligns with the rising edge of the trigger pulse and the start of the **'M samples'** block.\n*   The **'Acquisition stop'** marker aligns with the end of the **'N samples'** block.](.pcie-9852-50-11041-1000-200-en/0431528b9673f37c6bb607db7cca7171892b749812616958225357ce2762ec69.jpg)

Figure 3-8: Middle Trigger Mode Acquisition

# 3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single acquisition. Re-Trigger mode can also be set to automatically acquire R traces, containing N\*R samples/channel of data, without additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed-Trigger modes, with different limitations on the spacing between trigger events in each mode. Trigger events arriving too close to the previous instance will be ignored by the digitizer.

▶ In Post-Trigger mode, the minimum spacing between trigger events is N+1
▶ In Delayed-Trigger mode, the minimum spacing between trigger events is $(N+D)+1$ , where D is the number of the delayed setting

![This diagram illustrates a timing sequence across three horizontal rows:\n\n**1. Top Row (Time Axis):**\nA horizontal line with an arrow pointing right, labeled **'Time'** at the far right. Three vertical arrows point downward to this line, labeled from left to right:\n*   **'Operation start'**\n*   **'1st Trigger Event Occurs'**\n*   **'2nd Trigger Event Occurs'**\n\n**2. Middle Row (Trigger Signal):**\nLabeled **'Trigger'** on the left. It displays a signal line with two square pulses.\n*   The first pulse aligns vertically with the **'1st Trigger Event Occurs'** marker.\n*   The second pulse aligns vertically with the **'2nd Trigger Event Occurs'** marker.\n\n**3. Bottom Row (Data):**\nLabeled **'Data'** on the left. It displays two rectangular blocks containing the text **'N samples'**.\n*   The first block aligns vertically with the first trigger pulse.\n*   The second block aligns vertically with the second trigger pulse.](.pcie-9852-50-11041-1000-200-en/a4045e137f724b888cf6455ad3ad7d8c598025687148224f7755c92978389964.jpg)

Figure 3-9: Re-Trigger Mode Acquisition

# 3.4.6 Data Average Mode (Post-Trigger and Delayed-Trigger only)

In normal post-trigger mode acquisition, N samples/channel data are generated for a single trigger event. In Re-trigger mode (See "Acquisition with Re-Triggering" on page 20.), a total of N \* R samples/channel data is generated for R trigger events, that is, R traces (A trace contains N samples/channel). In Data Average Mode, only N samples/channel data are generated for R trigger events. The single trace data (N samples/channel) is the average of the R traces sample by sample.

# 3.5 Timebase

![The flowchart depicts a clock signal routing system with the following labeled blocks and connections:\n\n**Blocks:**\n*   **CLK IN** (Source)\n*   **10MHz Xtal** (Source)\n*   **Synthesizer**\n*   **Clock buffer**\n*   **To ADC** (Output)\n\n**Connections:**\n*   **CLK IN** connects to a switch.\n*   **10MHz Xtal** connects to the same switch mechanism.\n*   The switch routes **CLK IN** to the **Clock buffer**.\n*   The switch routes **10MHz Xtal** to the **Synthesizer**.\n*   The **Synthesizer** connects to the **Clock buffer**.\n*   The **Clock buffer** connects to **To ADC**.](.pcie-9852-50-11041-1000-200-en/9c22bea878aa39332339b3d005b9ff539172217144c7707805f9069d919422ab.jpg)

Figure 3-10: PCIe-9852 Clock Architecture

# 3.5.1 Internal Reference Clock

The PCIe-9852 internal 10MHz Crystal oscillator acts as reference clock, generating, after synthesis, precisely 200MHz clock for ADC.

# 3.5.2 External Reference Clock

The PCIe-9852 can choose an external clock source for use as a reference clock. When an external clock reference is selected, the synthesizer input will switch to the clock source at SMA connector CLK IN, and generate precisely 200MHz clock for ADC. The frequency of clock source is restricted to 10MHz.

# 3.5.3 External Sampling Clock

The PCIe-9852 can further choose an external clock source as ADC sampling clock. When an external sampling clock is selected, the ADC sampling frequency switches to the clock source at SMA Connector CLK IN, and clock source frequency is available from 40MHz to 200MHz.

# 3.6 ADC Timing Control

# 3.6.1 Timebase Architecture

![The diagram shows a signal flow starting from the left:\n\n1.  **Onboard 200 MHz Oscillator** points to a block labeled **ADC**.\n2.  An arrow exits the **ADC** block labeled **ADC Output 200 MHz**.\n3.  This line enters a dashed box labeled **FPGA** at the bottom.\n4.  Inside the **FPGA**, the line splits into two paths:\n    *   The top path enters a block labeled **X2 Multiplier PLL**. An arrow exits this block labeled **400 MHz** pointing to text reading **For ADC Data Bus**.\n    *   The bottom path is labeled **200 MHz** and points directly to text reading **For ADC state machine**.](.pcie-9852-50-11041-1000-200-en/124591ae59aba02038b71f677455dc0b2ad7123502827c7a7dc4c032d4f2d154.jpg)

Figure 3-11: PCIe-9852 Timebase Architecture

# 3.6.2 Basic Acquisition Timing

The PCIe-9852 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger, or the PXI Trigger Bus. The Timebase is a clock provided to the ADC and acquisition engine for essential timing. The Timebase is from an onboard synthesizer. To achieve different sampling rates, a scan interval counter is used.

Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC, and stores the sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately through the DMA engine. The sampled data is generated continuously at the rising edge of Timebase according to the scan interval counter setting. When sampled data reaches a specified value, in this example 256, acquisition ends.

![The image is a timing diagram illustrating an acquisition process. It contains the following labeled rows and components:\n\n**Labels (Left Side):**\n*   Analog signal\n*   TIMEBASE\n*   Trigger\n*   Acquisition In Progress\n*   DATA\n\n**Bottom Text:**\n*   Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1\n\n**Diagram Rows and Connections:**\n*   **Analog signal:** A sine wave. Black dots are placed on the peaks and troughs of the wave.\n*   **TIMEBASE:** A square wave signal.\n    *   **Connection:** The black dots on the 'Analog signal' align vertically with the edges of the 'TIMEBASE' signal. Specifically, the peaks align with the rising edges, and the troughs align with the falling edges.\n*   **Trigger:** A digital signal that goes high at the start of the diagram and drops low at the end of the fourth TIMEBASE pulse.\n*   **Acquisition In Progress:** A digital signal that goes high exactly at the rising edge of the first TIMEBASE pulse and remains high.\n    *   **Connection:** An arrow points from the text 'Acquisition initiates following this clock edge' to the rising edge of the first TIMEBASE pulse, indicating the start of the acquisition.\n*   **DATA:** A sequence of rectangular blocks aligned with the TIMEBASE pulses. The blocks are labeled 'D1', 'D2', 'D3', 'D4', followed by circles (indicating omission), and then 'D253', 'D254', 'D255', 'D256'.\n    *   **Connection:** The data blocks align vertically with the TIMEBASE pulses. 'D1' aligns with the first pulse, 'D2' with the second, and so on, corresponding to the 256 pulses implied by 'DataCnt = 256'.](.pcie-9852-50-11041-1000-200-en/58968121e6eb579e4490428565a51871867451814d209371d824e8db6e539954.jpg)

Figure 3-12: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 200MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 200MS/s / 2 = 100MS/s. If as 3, the equivalent sampling rate is 200MS/s / 3 = 66.66MS/s, and vice versa. The scan interval counter is 16 bits in width, therefore the lowest sampling rate is 3.051KS/s (200MS/s / 65535).

![This diagram illustrates a timing relationship between a trigger signal, a timebase clock, and data acquisition intervals.\n\n**Labeled Blocks and Signals:**\n*   **Trigger:** A waveform at the top showing a single rising edge.\n*   **TIMEBASE:** A square wave signal below the trigger, featuring upward-pointing arrows on its rising edges.\n*   **DATA:** A bracket grouping three horizontal rows.\n    *   **Row 1:** Labeled **ScanIntrv = 1**. It contains a continuous sequence of hexagonal blocks labeled **D1**, **D2**, **D3**, **D4**, **D5**, **D6**, **D7**, **D8**, **D9**, **D10**.\n    *   **Row 2:** Labeled **ScanIntrv = 2**. It contains hexagonal blocks labeled **D1**, **D2**, **D3**, **D4**, **D5**, **D6** separated by gaps.\n    *   **Row 3:** Labeled **ScanIntrv = 3**. It contains hexagonal blocks labeled **D1**, **D2**, **D3**, **D4** separated by larger gaps.\n*   **Acquisition In Progress:** Text at the bottom left.\n*   **Acquisition is initiated following this clock edge:** Text annotation near the bottom.\n\n**Connections:**\n*   The **TIMEBASE** signal acts as a clock. Upward arrows indicate clock edges that align vertically with the start of the data blocks (e.g., **D1** in each row aligns with the first clock edge after the **Trigger**).\n*   In the **ScanIntrv = 1** row, the data blocks are connected in a tight chain.\n*   In the **ScanIntrv = 2** and **ScanIntrv = 3** rows, horizontal lines connect the data blocks, indicating spacing or intervals between acquisitions.\n*   An arrow originates from the **Acquisition In Progress** area and points upward to the first rising edge of the **TIMEBASE** waveform. The text **Acquisition is initiated following this clock edge** explains that the process begins on that specific signal transition.](.pcie-9852-50-11041-1000-200-en/40e820cad71ed69a5b36c1695cc1ceaa380093fa6009c5e9129b543279f283cc.jpg)

Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter

<table><tr><td>Counter Name</td><td>Length</td><td>Valid Value</td><td>Description</td></tr><tr><td>ScanIntrv</td><td>16-bit</td><td>1-65535</td><td>Timebase divider to achieve equivalent sampling rate of the digitizer, where Sampling rate = Timebase / ScanIntrv</td></tr><tr><td>DataCnt</td><td>28-bit</td><td>1-268435452</td><td>Specifies the amount of data to be acquired:► 1 - 268435452 for pre-trig or mid-trig mode operation► 1 - 268435452 for Data Average mode for 1 channel► 1 - 134217724 for Data Average mode for 2 channel</td></tr><tr><td>trigDelayTicks</td><td>16-bit</td><td>1 -65535</td><td>Indicates time between a trigger event and commencement of acquisition. The unit of a delay count is the period of the Timebase.</td></tr></table>

<table><tr><td>Counter Name</td><td>Length</td><td>Valid Value</td><td>Description</td></tr><tr><td>ReTrgCnt</td><td>31-bit</td><td>1-2147483647</td><td>Enables re-trigger to accept multiple triggers.► 1 - 2147483647 for normal operation► 1 - 65535 for Data Average modeSee Acquisition with Re-Triggering</td></tr></table>

Table 3-4: Counter Parameters and Description

# 3.7 Synchronizing Multiple Modules

The PCIe-9852 provides a dedicated connector as system synchronization interface, enabling multiple module synchronization. As shown, bi-directional SSI I/Os provides a flexible connection between modules, allowing one SSI master PCIe-9852 to output SSI signals to other slave modules. The table summarizes SSI timing signals and functionalities.

![The image displays a white document icon with a folded top-left corner. Faint horizontal gray lines run across the lower portion of the paper. A large, bold red checkmark is superimposed over the center and right side of the document.](.pcie-9852-50-11041-1000-200-en/6c52472aadacc4b859fe4730f8cd4378d262ff689848d60caa8d20d1596e23ef.jpg)
NOTE:

Different signals cannot be routed onto the same trigger bus line.

<table><tr><td>SSI Timing Signal</td><td>Function</td></tr><tr><td>SSI Clock (10MHz)</td><td>Input/output timebase signal through SSI</td></tr><tr><td>SSI Trig</td><td>Input/output trigger signal through SSI</td></tr><tr><td>SSI_pre_data_rdy</td><td>Input/output trigger signal through SSI</td></tr></table>

All SSI signals are routed to the 16-pin connector from FPGA, enabling multi-module synchronization. ACL-eSSI-2/

ACLeSSI-3/ACL-eSSI-4 cables can be used to synchronize 2, 3, or 4 modules.

<table><tr><td>15 13 11 9 7 5 3 1</td></tr><tr><td>16 14 12 10 8 6 4 2</td></tr><tr><td>PCB</td></tr></table>

<table><tr><td>Signal</td><td>Direction</td><td>Descr.</td><td>Pin</td></tr><tr><td>SSI Clock</td><td>Input/Output</td><td>Timebase signal through SSI</td><td>1</td></tr><tr><td>SSI Trig</td><td>Input/Output</td><td>Trigger signal through SSI</td><td>11</td></tr><tr><td>SSI_pre_data_rdy</td><td>Input/Output</td><td>Trigger signal through SSI</td><td>3, 5, 13, 15,</td></tr><tr><td>NC</td><td></td><td>No Connection</td><td>7</td></tr><tr><td>GND</td><td></td><td>Ground</td><td>2, 4, 6, 8, 10, 12, 14, 16</td></tr><tr><td>Reserved</td><td>Input/Output</td><td>Reserved for future use</td><td>9</td></tr></table>

Table 3-5: SSI Signal Location and Pin Definition

# 3.7.1 Card Number Configuration

When multiple cards are used in a single chassis, card number configuration via switch, as shown.

![SW1\n72\n12\n3\n4\nNO DIP](.pcie-9852-50-11041-1000-200-en/c7c130ad46183a476584dbc76c3688803a9e0b307b6fa9b14ad0edb74cecbb94.jpg)

Figure 3-14: Card Number Configuration Switch

When all sliders are in ON position, card number is 0, when all are OFF, card number is 15, as shown.

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>ON</td><td>0</td></tr><tr><td>ON</td><td>ON</td><td>ON</td><td>OFF</td><td>1</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>ON</td><td>2</td></tr><tr><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td><td>3</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>ON</td><td>4</td></tr><tr><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td><td>5</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td><td>6</td></tr><tr><td>ON</td><td>OFF</td><td>OFF</td><td>OFF</td><td>7</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>ON</td><td>8</td></tr><tr><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td><td>9</td></tr></table>

<table><tr><td>Slider 1</td><td>Slider 2</td><td>Slider 3</td><td>Slider 4</td><td>Card #</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td><td>10</td></tr><tr><td>OFF</td><td>ON</td><td>OFF</td><td>OFF</td><td>11</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td><td>12</td></tr><tr><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td><td>13</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td><td>14</td></tr><tr><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>15</td></tr></table>

Table 3-6: Card Number Configuration Settings

Default card number is 0.

# 3.7.2 SSI Timebase

As an output, the SSI\_TIMEBASE signal outputs the onboard 10MHz through ACL-eSSI-2/ACLeSSI-3/ACL-eSSI-4 cables. As an input, the PCIe-9852 accepts the SSI\_TIMEBASE signal to be the source of timebase.

# 3.7.3 SSI\_TRIG

As an output, the SSI\_TRIG signal reflects the trigger event signal in an acquisition sequence. As an input, the PCIe-9852 accepts the SSI\_TRIG signal to be the trigger event source. The signal is configured in the rising edge-detection mode.

# 3.7.4 SSI\_pre\_data\_rdy

If one SSI slave is set to mid-trig or pre-trig mode, the SSI master should also be in mid-trig or pre-trig mode. SSI slaves in mid-trig or pre-trig mode should send pre\_data\_rdy to SSI master through SSI[0], SSI[1], SSI[5] or SSI[6].

A SSI master sends SSI\_trig to other SSI slaves. If set to pre-trig or mid-trig mode, SI\_pre\_data\_rdy is received from other SSI slaves. SSI slaves should be set to mid-trig or pre-trig mode to send SSI\_pre\_data\_rdy signal to the SSI master. Different SSI slaves should not use the same SSI pins.

# Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

# A.1 Calibration Constant

The PCIe-9852 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-9852 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PCIe-9852.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PCIe-9852 boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

# A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PCIe-9852 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PCIe-9852 for at least 20 minutes and remove connected cables.

![A white document icon with a folded top-left corner and horizontal lines representing text, overlaid with a large red checkmark.](.pcie-9852-50-11041-1000-200-en/0ce069bf2669da43b30fc44380127bd3b3ace98b11ceaa82538c2d97fd67660e.jpg)
NOTE:

It is not necessary to manually factor delay into applications, as the PCIe-9852 driver automatically adds the compensation time.

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
▶ A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![This image displays a standard safety warning sign. It features a red triangle with a darker red gradient background and a black border. Inside the triangle is a large white exclamation point. Below the triangle, the word 'WARNING' is printed in bold, black capital letters.](.pcie-9852-50-11041-1000-200-en/35f196271e43c1ebe017a663f3125516de0744b274a32dc88602c7bb6719f612.jpg)

Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
Rm. 801, Power Creative E, No. 1,
Shang Di East Rd., Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8626

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园

A1 栋 2 楼 C 区 (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4
神田 374 ビル 4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 서울시 서초구 서초동 1675-12 모인터빌딩 8 층 8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu, Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza, Margosa Main Road, Malleswaram, Bangalore-560055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 6 Hasadna St., Kfar Saba 44424, Israel

Tel: +972-9-7446541

Fax: +972-9-7446542

Email: israel@adlinktech.com
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