# PXI-3800

3U PXI Pentium M

System Controller

User's Manual

Manual Rev. 2.01

Revision Date: December 21, 2003

Part No: 50-17014-101

![The image displays the standard recycling symbol. It features a solid black circle containing three white arrows arranged in a triangular formation. The arrows are chasing each other in a clockwise direction, representing the cycle of recycling. There is no text present in the image.](.pxi-3800-manual-4/4b42ef38d7ca4da93ecdc6b0105207808fb8e79facde8633455a8cc821ace71c.jpg)
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Copyright 2004 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

PXI is registered trademarks of PXI Systems Alliance. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance.

# ADLINK TECHNOLOGY INC.

Web Site: http://www.adlinktech.com

Sales & Service: Service@adlinktech.com

TEL: +886-2-82265877

FAX: +886-2-82265717

Address: 9F, No. 166, Jian Yi Road, Chungho City,

Taipei, 235 Taiwan

Please email or FAX this completed service form for prompt and satisfactory service.

<table><tr><td colspan="2">Company Information</td></tr><tr><td>Company/Organization</td><td></td></tr><tr><td>Contact Person</td><td></td></tr><tr><td>E-mail Address</td><td></td></tr><tr><td>Address</td><td></td></tr><tr><td>Country</td><td></td></tr><tr><td>TEL</td><td>FAX:</td></tr><tr><td>Web Site</td><td></td></tr><tr><td colspan="2">Product Information</td></tr><tr><td>Product Model</td><td></td></tr><tr><td>Environment</td><td>OS:M/B: CPU:Chipset: BIOS:</td></tr></table>

Please give a detailed description of the problem(s):

# Table of Contents

# List of Tables......v

# List of Figures ...... vi

# 1 Introduction ...... 1

1.1 Features.... 2

PXI-3800 Features 2

1.2 Functional Block Diagram.... 3

PXI Bus Interface 3

CPU Support 4

Memory Support 5

Ethernet Interfaces 6

Display Interfaces 6

IDE Interfaces 7

Universal Serial Bus (USB) 7

Hot-swappable CF Interface 8

Serial I/O 8

Floppy Disk Drive 8

IEEE-1284 Parallel Port/Printer Interface 8

PXI Trigger I/O Port 9

AC '97 Multimedia Audio Output 10

Hardware Monitor Function 10

Watchdog Timer 10

LED Setting 11

1.3 Specifications.... 12

PXI/CompactPCI Compliancy 12

Form Factor 12

CPU/Cache 12

Chipset 12

Host Memory 12

BIOS 12

CompactPCI Bus Controller 13

Graphics 13

Gigabit Ethernet 13

Onboard Peripherals 14

Front Panel LED Indicators and Reset Button 14

Real-Time Clock and Nonvolatile Memory 15

Environment 15

Safety Certificate and Test 15

Power Requirements 15

1.4 Unpacking Checklist 16

# 2 I/O Connectors and Pin Assignment.... 17

2.1 Peripheral Connectivity 17

2.2 PXI-3800 I/O Connectors.... 18

PXI-3800 Front Panel I/O Connectors 18

PXI-3800 Onboard I/O connectors 19

PXI-3800DB Daughter Board I/O Connectors ...... 20

2.3 PXI-3800 Connector Pin Assignments.... 20

PXI Trigger Connector 20

VGA Connector 21

USB port 1, 2 Connector ....21

Ethernet (RJ-45) Connector 22

COM1, 2 Serial Port Connector DB-9 ...... 23

44-Pin IDE Connector 24

LPT Printer Port Connector DB-25 25

General Purpose LED definitions 25

Compact Flash Type I/II Connector 26

Slim Type FDD connector 27

PS/2 Keyboard/Mouse Combo Connector (Mini DIN-6) 28

J1 Connector Pin Assignment 29

J2 Connector Pin Assignment 30

2.4 PXI-3800 Jumper Settings 31

Clear CMOS (PXI-3800, JP7) 32

CompactFlash Master/Slave Selection

(PXI-3800, JP2) 33

COM port Operation Mode Selection

(PXI-3800, JP3\~JP5) 33

USB-to-CF/USB-to-IDE Selection (PXI-3800DB, JP4) . 34

# 3 Getting Started 37

3.1 Installing the PXI-3800 37

How to Remove the Controller from the PXI Chassis ... 38

3.2 Memory Module Installation 39

Installing the first memory module 39

Installing the second memory module 40

3.3 HDD and CF Installation 41

HDD Installation 42

CompactFlash Card Installation 42

3.4 BIOS Configuration Overview 43

3.5 Operating System Installation 44

3.6 Boot PXI-3800 via USB ports or CompactFlash sockets... 45

Boot from USB-CDROM Drive 45

Boot from USB Floppy Drive 45

Boot from the front panel CompactFlash Drive 46

Boot from the onboard CompactFlash Drive 46

# 4 Driver Installation 47

4.1 Chipset Driver Installation 48

Installing Hardware Configuration File 48

4.2 VGA Driver Installation 50

4.3 LAN Driver Installation 51

4.4 Audio Codec Driver Installation 51

4.5 PXI Trigger Driver Installation 52

# 5 Utilities 53

5.1 Watchdog Timer Overview 53

Intel® 6300ESB ICH Watchdog Timer 53

Configuration Registers 54

GPIO Control Registers 56

WDT Programming Procedure 57

W83627HF (Super IO) Watchdog Timer 58

5.2 Intel Preboot Execution Environment (PXE).... 59

5.3 PICMG 2.1 Hot Swap Support.... 60

# Appendix A PXI Trigger Function Description.... 61

Data Types 61

Function Reference 62

P3800\_Close 62

P3800\_GetGPIOBase 63

P3800\_Init 64

P3800\_SetSoftTrg 65

P3800\_Trigger\_Clear 65

# Warranty Policy.... 69

# List of Tables

Table 1-1: W83627HF Hardware Monitor Inputs ...... 10
Table 1-2: Power Requirements 15
Table 2-1: Peripheral Connectivity Table 17
Table 2-2: PXI Trigger Connector Pin Assignment 20
Table 2-3: VGA Connector Pin Assignment 21
Table 2-4: USB Connector Pin Assignment 21
Table 2-5: Ethernet Connector Pin Assignment 22
Table 2-6: Ethernet LED Status Definitions 22
Table 2-7: COM Connector Pin Assignment 23
Table 2-8: IDE 44-pin Connector Pin Assignment 24
Table 2-9: LPT Connector Pin Assignment 25
Table 2-10: General Purpose LED Definitions 25
Table 2-11: Compact Flash Connector Pin Assignment ..... 26
Table 2-12: Slim Type Floppy Connector Pin Assignment ..... 27
Table 2-13: PS/2 Connector Pin Assignment 28
Table 2-14: J1 Connector Pin Assignment 29
Table 2-15: J2 Connector Pin Assignment 30
Table 2-16: Jumpers Definition on the PXI-3800 31
Table 2-17: Clear CMOS Jumper Setting 32
Table 2-18: CompactFlash Master/Slave Jumper Setting ...... 33
Table 2-19: COM port Operation Mode Jumper Setting ...... 34
Table 2-20: USB-to-CF/USB-to-IDE Selection Jumper Setting . 35

# List of Figures

Figure 1-1: PCI-3800 Functional Block Diagram .... 3

Figure 1-2: PXI Trigger I/O Block diagram....9

Figure 2-1: PXI-3800 Front Panel I/O Connectors.... 18

Figure 2-2: PXI-3800 Onboard I/O Connectors 19

Figure 2-3: PXI-3800DB Daughter Board I/O Connectors ..... 20

Figure 2-4: PXI-3800 Carrier Board Jumper Locations.... 32

Figure 3-1: PXI-3800 System Controller being installed in a PXI Chassis.... 38

Figure 3-2: First Memory Module Installation (preinstalled by ADLINK) 40

Figure 3-3: Second Memory Module Installation .... 41

Figure 5-1: Intel® 6300ESB Watchdog Timer Architecture ..... 54

Figure 5-2: W83267HF Watchdog Timer Architecture.... 59

# 1 Introduction

The PXI-3800 System Controller is ADLINK's first Intel® Pentium® M solution in the PXI form factor. This product is designed to meet the highest performance requirements for embedded computing. It is based on the Intel® Pentium® M processor, 855GME and 6300ESB chipset that provides both long life and excellent driver support to meet the majority of industrial applications. The PXI-3800 System Controller complies with PXI specification Rev. 2.2 and features many practical interfaces, such as hot swappable CompactFlash card, USB 2.0 ports, and Gigabit Ethernet. The PXI-3800 can support a CPU frequency of up to 1.8GHz and a memory size up to 2GB RAM via two 200-pin DDR SO-DIMM sockets. With an embedded PXI trigger pin, the PXI-3800 provides synchronous trigger ability to meet the high-performance requirements of instrumentation. In addition, the PXI-3800's compact and rugged mechanism makes it ideal for test & measurement applications in harsh environments.

This chapter gives an overview of the PXI-3800 System Controller, and covers the following topics:

▶ Features
▶ Functional block diagram and overview
▶ Specifications
▶ Unpacking checklist

# 1.1 Features

# PXI-3800 Features

▶ Standard 3U PXI form factor
▶ PICMG 2.0 CompactPCI Specification R3.0 compliant
▶ PICMG 2.8 PXI Specification Rev. 2.2 compliant
▶ PICMG 2.1 R1.0 CompactPCI Hot Swap Specification compliant
▶ Design for Pentium® M processor, FSB 400MHz, CPU frequency up to 1.8GHz
▶ Two 200-pin DDR SO-DIMM sockets supporting up to 2GB RAM
▶ One 44-pin EIDE (primary IDE) with built-in 2.5" low profile HDD (40 GB, standard)
▶ Two CompactFlash interfaces for HDD and FDD replacement; CF Type II supports hot-swappable CF card functionality
▶ Two USB 2.0 ports, two serial ports (RS-232) and one parallel port provided on the front panel
▶ One AC '97 stereo audio output
▶ One TRIG I/O on the front panel for advanced PXI trigger function
▶ VGA output on the front panel supporting up to 2048 x 1536 resolution at 75Hz
Intel® 82545EM controller providing one 10/100/1000 Mb Ethernet port
▶ Supports 7 bus-master PCI devices on PXI/CompactPCI bus
▶ Programmable watchdog timer

# 1.2 Functional Block Diagram

The following sections give an overview the PXI-3800 System Controller's main features as outlined in the functional block diagram below:

![Based on the provided image, here is the accurate and concise description of the flowchart.\n\n**Title:** PXI-3800 Block Diagram\n\n**Labeled Blocks:**\n*   **Front Panel (3 Slot)** (Grouping label for the left column)\n*   **Front Panel Components:** PXI TRIG, VGA, Reset/LEDs, USB 2.0 x2, Compact Flash, GigaLAN 1000/100/10, Audio Jack, COM1, COM2, PS2 KB/MS, PRN\n*   **System Logic & Core:** Clock Generator, PWM, HW monitor, Pentium M, Intel 855GME GMCH, Intel 6300ESB ICH, Winbond W83627HF\n*   **Controllers & Memory:** DDR SO-DIMM, ASIC, Reset Logic, USB-to-CF controller, 82545EM, AC'97 Codec, FWH BIOS\n*   **Storage & Expansion:** CF socket, IDE (44pin), Floppy (optional), Compact PCI 12, Compact PCI 1\n\n**Connections:**\n*   **Pentium M** \$\leftrightarrow\$ **Intel 855GME GMCH** (Label: **400 MHz**)\n*   **Intel 855GME GMCH** \$\leftrightarrow\$ **DDR SO-DIMM** (Labels: **DDR 200/266**, **DDR333 (GME)**)\n*   **Intel 855GME GMCH** \$\rightarrow\$ **Intel 6300ESB ICH** (Label: **Hub I/F 1.5**)\n*   **PXI TRIG** \$\rightarrow\$ **ASIC**\n*   **VGA** \$\rightarrow\$ **ASIC** (Label: **CRT**)\n*   **Reset/LEDs** \$\rightarrow\$ **Reset Logic**\n*   **USB 2.0 x2** \$\rightarrow\$ **Intel 6300ESB ICH** (Label: **USB2.0 x2**)\n*   **Compact Flash** \$\rightarrow\$ **USB-to-CF controller** \$\rightarrow\$ **Intel 6300ESB ICH** (Label: **USB2.0**)\n*   **GigaLAN 1000/100/10** \$\rightarrow\$ **82545EM** \$\rightarrow\$ **Intel 6300ESB ICH** (Labels: **LA**, **PCI-X 64bit/66MHz**)\n*   **Audio Jack** \$\rightarrow\$ **AC'97 Codec** (Label: **Speaker out**)\n*   **AC'97 Codec** \$\rightarrow\$ **Intel 6300ESB ICH**\n*   **FWH BIOS** \$\rightarrow\$ **Intel 6300ESB ICH** (Label: **LPC**)\n*   **COM1** \$\rightarrow\$ **Winbond W83627HF**\n*   **COM2** \$\rightarrow\$ **Winbond W83627HF**\n*   **PS2 KB/MS** \$\rightarrow\$ **Winbond W83627HF**\n*   **PRN** \$\rightarrow\$ **Winbond W83627HF** (Label: **LPT**)\n*   **Intel 6300ESB ICH** \$\rightarrow\$ **CF socket** (Label: **IDE1**)\n*   **CF socket** \$\rightarrow\$ **IDE (44pin)** \$\rightarrow\$ **Floppy (optional)**\n*   **Intel 6300ESB ICH** \$\rightarrow\$ **Compact PCI 12** (Label: **PCI 32bit/33MHz**)\n*   **Compact PCI 12** \$\rightarrow\$ **Compact PCI 1**](.pxi-3800-manual-4/dbd5a09b66fb9cb0d19510855a465ca034f61cd0afe5ef98af7282ac808c099c.jpg)

Figure 1-1: PCI-3800 Functional Block Diagram

# PXI Bus Interface

The PXI-3800 System Controller is built on the PICMG 2.8 Instrumentation Extensions to CompactPCI Specification. PXI specifications dedicate the leftmost slot of the PXI chassis to the System Controller. PXI is electrically compatible with the PCI local bus standard, and provides enhanced instrumentation signals for synchronization or communication between peripherals. Based on the mechanical design of CompactPCI systems, PXI systems provide the high levels of environmental performance required by the vibration, shock, temperature, and humidity extremes of industrial environments.

The PXI-3800 utilizes a 32-bit/33MHz PCI bus and can be used in the ADLINK PXI chassis listed below:

▶ PXIS-2506, 6-slot 3U PXI Instrument chassis
▶ PXIS-2556/T, 6-slot 3U Instrument chassis
▶ PXIS-2630, 8-slot 3U PXI Instrument chassis
▶ PXIS-2650/T, 8-slot 3U Instrument chassis
▶ PXIS-2700, 18-slot 3U PXI Instrument chassis
▶ PXIS-2680P, 8-slot 3U Integrated Portable Instrument chassis

When used in a Hot Swap compliant backplane and in accordance to the CompactPCI Hot Swap Specification, PICMG 2.1 R1.0, the PXI-3800 System Controller supports hot swappable peripherals in a powered system.

# CPU Support

The PXI-3800 supports a single Intel® Pentium® M Processor with 1MB L2 cache in 478-pin Micro-FCPGA or 479-ball Micro-FCBGA package. The standard PXI-3800 comes with a CPU socket which can be installed with a Micro-FC-PGA package CPU, including Pentium M 1.1GHz, 1.6GHz and 1.8GHz. The Pentium® M processor runs at a core speed up to 1.8GHz, with a Front Side Bus (FSB) speed of 400MHz. Micro-FCBGA package support is reserved for OEM programs only. ADLINK's factory can pre-mount the CPU for customers. Please contact an ADLINK sales representative for available CPU configurations.

The Intel® Pentium® M processor is a high performance, low power mobile processor with several micro-architectural enhancements over existing Intel mobile processors. The key features of the processor are listed as follows:

▶ Support Intel® Architecture with Dynamic Execution
▶ On-die, primary 32-KB instruction cache and 32-KB write-back data cache
▶ On-die, 1-MB second level cache with Advanced Transfer Cache Architecture
▶ Advanced Branch Prediction and Data Prefetch Logic
▶ Streaming SIMD Extensions 2 (SSE2)
▶ 400-MHz, Source-Synchronous processor system bus
▶ Advanced Power Management features including Enhanced Intel® SpeedStep® technology

The Pentium® M processor runs at a core speed up to 1.8GHz, with a Front Side Bus (FSB) speed of 400MHz.

# Memory Support

The PXI-3800 is based on Intel® 855GME chipset, which consists of 855GME Graphics Memory Controller Hub (GMCH) and the 6300ESB I/O Controller Hub (ICH). The GMCH system memory interface supports the following features:

▶ Single channel of x72, unbuffered, ECC DDR SDRAM (SO-DIMM)
▶ 200, 266MHz and 333MHz DDR device
▶ 64-bit data interface(72-bit with ECC)
▶ Up to two double-sided SO-DIMMs (four rows populated) with unbuffered PC2100/PC2700 DDR-SDRAM (with or without ECC)
▶ Up to 16 simultaneous open pages
▶ 64MB, 128MB, 256MB, and 512MB technologies for x8 and x16 width devices
▶ System memory supports up to 2GB
▶ SDRAM speed, type and size can be determined by the BIOS reading the SO-DIMM presence detect bits on the System Management Bus (SMBus)
▶ SDRAM timing register, which provides the DRAM speed control for the entire array, is programmed to use the timings of the slowest DRAMs installed.

# Ethernet Interfaces

The PXI-3800 supports an Intel® 82545EM Gigabit Ethernet controller. It integrates MAC and PHY functions into a single chip to provide a standard IEEE 802.3 Ethernet interface for 10/100/1000BASE-T applications. The controller provides a 64-bit wide interface compliant with PCI 2.3 and PCI-X 1.0a specifications. The Ethernet interface is routed to an RJ45 port with activity/speed LEDs. The controller supports Intel® Pre-Boot Execution Environment (PXE) for remote boot of Windows NT/2000. The board's Ethernet addresses are displayed on the label attached to the connector.

# Display Interfaces

The Intel® 855GME GMCH chip has dual independent display pipes which can support concurrent or simultaneous display on each display device. The 350MHz integrated 24bit RAMDAC supports analog display pixel resolution up to 1600x1200 at 85Hz and

2048x1536 at 75Hz. One DVO port supports digital video output with 165MHz output clock on 12 bit interface with pixel resolution up to 1600x1200 at 85Hz. Tri-view is supported through the LFP interface, DVO and CRT. Up to 64MB of dynamic video memory allocation and is DDC2B compliant.

# IDE Interfaces

PXI-3800 supports one 44-pin EIDE connector and two Compact-Flash Type I/II sockets. The 44-pin EIDE connector supports a 2.5" HDD with Ultra ATA 66/100 support. CompactFlash support listed as below:

▶ One Compact Flash Type II interface through IDE interface
▶ One Compact Flash Type II drive using USB to CF adaptor

# Internal 44-pin IDE Interfaces

The 44-pin IDE connector is on the top-side of the PXI-3800. A 2.5-inch low profile 40GB HDD is mounted on the PXI-3800 as standard configuration. Contact an ADLINK sales representative for available 2.5-inch drive options. For some customers, a CompactFlash Disk may be used for harsh environment applications.

# Internal CompactFlash Socket

An internal CompactFlash socket is available on the PXI-3800. It is connected to the IDE interface, which is also bootable. With a solid state CF card, PXI-3800 can work in high-vibration environments.

# Universal Serial Bus (USB)

The PXI-3800 supports three USB 2.0 serial ports. Ports 1 and 2 are on front panel, port 3 is used as a USB-to-CF or USB-to-IDE adaptor to support a Compact Flash Type II socket on the front panel or a 2.5" IDE HDD. Additional ports can be added through the use of an external USB hub. USB allows for the easy addition of peripherals such as mouse, keyboard, speakers, etc. Transfer rates of up to 480Mb/s are supported. High-speed connections require shielded cables. The PXI-3800 provides each USB port 0.5A at 5V to power peripherals and each USB port is protected by a power distribution switch (0.5A rating allows for inrush currents).

# Hot-swappable CF Interface

An external CompactFlash socket is available on the PXI-3800 front panel. The external CompactFlash interface provides Plug and Play features and is also hot swappable. Therefore, a CompactFlash card can be used as a replacement for floppy disks and can also provide very large storage capability (up to 1GB). It is also possible to set this CF interface as a boot device by selecting boot from USB in the BIOS menu. Note that drivers are needed for the external CompactFlash interface. Refer to Chapter 3 for installation detail.

# Serial I/O

The PXI-3800 provides support for two 16C550 UART compatible COM ports. COM1 and COM2 are accessible from the front face-plate through DB-9 connectors. COM1 is jumper-selectable to support a RS-422/485 interface. The RS-485 mode supports auto direction control which can automatically sense the direction of data flow and switch the transmission direction accordingly. This feature will make half duplex RS-485 control under a multitasking OS (e.g. Windows) equivalent to full duplex RS-232.

# Floppy Disk Drive

The PXI-3800 does NOT come equipped with a Floppy Disk Drive in standard configuration. For most applications, the hot-swappable CF card can replace the functionality of a FDD. However, ADLINK will provide an FDD option on request, which will occupy 4 slots (16HP). Please contact an ADLINK sales representative for the Floppy Disk Drive option.

# IEEE-1284 Parallel Port/Printer Interface

The parallel I/O interface signals are routed to the DB-25 connector on the front faceplate. This port supports the full IEEE-1284 specification and provides a basic printer interface. The BIOS will initialize the parallel port as LPT1 with an ISA I/O base address of 378h. This default configuration also assigns the parallel port to IRQ7. The printer interface mode (Normal, Extended, EPP, or ECP) is selectable through the BIOS menu.

# PXI Trigger I/O Port

The PXI-3800 System Controller provides one PXI trigger I/O port on the front panel for advanced PXI trigger functionality. The TRIG I/O is the software-controlled trigger connection for routing PXI triggers to or from the backplane trigger bus. All trigger lines are compatibility with TTL voltage levels and are edge sensitive. Please refer to Figure 2 for the detailed block diagram of PXI Trigger I/O.

![Based on the provided block diagram, here is the accurate and concise description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   3-state output\n*   8-to-1 Mux\n*   3-to-1 Mux\n*   1-to-8 Mux with 3-state output\n\n**Connections and Signal Flow:**\n*   **SMB_OE** connects to the **3-state output**.\n*   **TRGBUSIN_SEL(2..0)** connects to the **8-to-1 Mux**.\n*   **TRGBUS (7..0)** acts as a bidirectional bus, connecting to the **8-to-1 Mux** (as an input) and the **1-to-8 Mux with 3-state output** (as an output).\n*   The **3-state output** receives input from the **8-to-1 Mux** and outputs **SMBTRIGGER**. A connection from this output line also feeds into the **3-to-1 Mux**.\n*   **WDTTIMER** and **SOFTWARE_TRG** connect to the **3-to-1 Mux**.\n*   **INT_TRG_SW(1..0)** connects to the **3-to-1 Mux**.\n*   The **3-to-1 Mux** connects to the **1-to-8 Mux with 3-state output**.\n*   **TRGBUSOUT_SEL(2..0)** and **TRGBUS_OE** connect to the **1-to-8 Mux with 3-state output**.](.pxi-3800-manual-4/d083b59c326e831bb934e9c768ea9966a7589e0d3de65820fff0671ca3716abb.jpg)

Figure 1-2: PXI Trigger I/O Block diagram

# AC '97 Multimedia Audio Output

The PXI-3800 System Controller supports an AC '97 2.2 compliant audio stereo output with amplifier. Supports multiple sample rates up to 48 kHz.

# Hardware Monitor Function

Two devices provide all the hardware monitor functions of a PXI-3800 system. The ADM1032 provides a CPU temperature monitor with programmable over/under temperature limits and over temperature alarm. The Winbond W83627HF provides system temperature and DC voltage monitoring.

<table><tr><td>83627HF Pin Name</td><td>Voltage/ Temperature</td><td>Function/Comments</td></tr><tr><td>-12VIN</td><td>-12V</td><td>+/- 5%</td></tr><tr><td>+12VIN</td><td>+12V</td><td>+/- 5%</td></tr><tr><td>+3.3VIN</td><td>+3.3V</td><td>+/- 5%</td></tr><tr><td>VSB</td><td>+5VSB</td><td>+/- 5%</td></tr><tr><td>VCOREB</td><td>+1.05V</td><td>+/- 5%</td></tr><tr><td>VCOREA</td><td>CPU_VCORE</td><td>Processor core voltage</td></tr><tr><td>VTIN1</td><td></td><td>System Temperature</td></tr><tr><td>VTIN2</td><td></td><td>External Temperature Sensor Input</td></tr><tr><td>OVT#</td><td></td><td>CPU over temperature shutdown output</td></tr><tr><td>BEEP</td><td></td><td>Beep function for hardware monitor</td></tr></table>

Table 1-1: W83627HF Hardware Monitor Inputs

# Watchdog Timer

The PXI-3800 system implements two watchdog timers. The Intel® 6300ESB provides one 2-stage programmable watchdog timer (WDT) and the W83627HF provides one 1-stage programmable watchdog timer.

# 6300ESB Watchdog Timer

▶ Supports selectable prescaler – approximately 1MHz (1us to 1s) and approximately 1KHz (1ms to 10min).
The 2-stage WDT mode operates as follows: When the first programmed time expires before the counter is reloaded, the WDT generates an IRQ, SMI, or SCI interrupt and loads the second programmed value. If the host still fails to reload the WDT before the second timeout, the WDT drives WDT\_TOUT# low and resets PXI-3800 system.

# W83627HF Watchdog Timer

▶ Watchdog timer is programmable from 1 to 255 seconds.
▶ Time out will generate interrupt to NMI or RESET, BIOS selectable.

# LED Setting

The PXI-3800 System Controller provides four LEDs on the front panel to display the following information:

▶ System Active LED: This Green LED will turn on after POST; turn off when system is powered off.
▶ IDE LED: This amber LED flashes when the IDE port is accessed.
▶ WDT LED: This Red LED should be off in normal situations. The LED flashes after the WDT is enabled by software. The LED turns on steady when the WDT times out.
▶ General Purpose LED: This Blue LED is a general purpose LED. Customers can define this LED through software.

# 1.3 Specifications

# PXI/CompactPCI Compliancy

▶ PXI Specification Rev 2.2
▶ PICMG 2.0 CompactPCI Rev. 3.0
▶ PICMG 2.1 CompactPCI Hot-Swap Specification Rev. 1.0

# Form Factor

▶ Standard PXI 3U form factor (board size: 100mm x 160mm)
▶ 3-slot (12 HP) width

# CPU/Cache

▶ Supports Intel® Pentium® M processor, CPU frequency up to 1.8GHz
▶ Front Side Bus (FSB) frequency: 400MHz
▶ Cache size: 1MB on-die cache

# Chipset

Intel® 855GME Graphic Memory Controller Hub (GMCH)
Intel® 6300ESB I/O Controller Hub

# Host Memory

▶ Two 200-pin SO-DIMM sockets for DDR SDRAM, up to 2GB with or w/o ECC

# BIOS

▶ Award PnP BIOS with 4Mb LPC compatible Flash ROM
▶ BIOS write protection provides anti-virus capability
▶ DMI BIOS Support: Desktop Management Interface (DMI) allows users to download system hardware-level information such as CPU type, CPU speed, internal/external frequencies, and memory size
▶ Supports Intel® Pre-Boot Execution Environment (PXE) for remote boot
▶ Optional OEM BIOS features on request

▶ Customized power-on screen
Remote-console

# CompactPCI Bus Controller

PLXtech PCI-6540 Universal PCI-X to PCI-X bridge, supports transparent and non-transparent mode
▶ PCI-X Rev 1.0 compliant
▶ Supports 64-bit/66MHz, 64-bit/33MHz, 32-bit/33MHz

# Graphics

▶ Integrated into 855GME GMCH
▶ 350MHz integrated 24bit RAMDAC supports analog display pixel resolution up to 1600x1200 at 85Hz and 2048x1536 at 75Hz
▶ Up to 64MB of dynamic video memory allocation
▶ Dual independent display pipes support concurrent or simultaneous display on each display device
▶ Front panel analog VGA DB-15 connector is available
▶ One DVO port supports digital video output with 165MHz output clock on 12 bit interface with pixel resolution up to 1600x1200 at 85Hz

# Gigabit Ethernet

Intel® 82545EM Gigabit Ethernet controller provides one 10/100/1000 Mbps Gigabit Ethernet port via a RJ-45 connector on the front panel.
▶ Standard IEEE 802.3 Ethernet interface
▶ 64-bit wide interface compliant with PCI 2.3 and PCI-X 1.0a Specifications
▶ Supports Intel® Pre-Boot Execution Environment (PXE) for remote boot in Windows NT/2000.

# Onboard Peripherals

▶ Integrated into Intel® 6300ESB southbridge
▶ One EIDE connector supports a 2.5" HDD with Ultra ATA 66/100 support
▶ Four USB 2.0 ports

▶ USB 1 and 2 are on the front panel
▶ USB 3 is used for USB-to-CF or USB-to-IDE adaptor to support Compact Flash Type II socket on front panel or a 2.5" IDE HDD

▶ Two CompactFlash Type I/II sockets

▶ Supports one CompactFlash Type II interface through IDE interface
▶ Supports one CompactFlash Type II drive using USB to CF adaptor

▶ Supports up to three 16C550 UART compatible COM ports
▷ COM1 and COM2 are on front faceplate, COM1 supports RS-232/422/485 (with RS-485+ Auto-Direction control)

▶ One PXI trigger input/output on front panel

▶ One AC '97 2.2 compliant audio stereo output with amplifier on the front panel. Supports multiple sample rates up to 48KHz.

▶ One high-speed bi-directional SPP/EPP/ECP parallel port

▶ One slim type FDD connector

▶ PS2 keyboard/mouse combo port on front panel

# Front Panel LED Indicators and Reset Button

▶ Four LEDs on the front panel including System Active LED (Green), IDE LED (Amber), Watchdog timer LED (Red), and General Purpose LED (Blue).

▶ Flush tact switch for system reset

# Real-Time Clock and Nonvolatile Memory

The PXI-3800 system provides a century calendar as well as a time of day function. In addition, 256 bytes of battery backed-up RAM are available for use by the BIOS. A separate 3V coin cell battery provides battery backup.

# Environment

▶ Operating temperature: 0 to 55°C
▶ Storage temperature: -20 to 80°C
▶ Humidity: 5% to 95% non-condensed
▶ Shock: 15G peak-to-peak, 11ms duration, non-operation
▶ Vibration:

▷ Non-operation: 1.88Grms, 5-500Hz, each axis
Operation: 0.5Grms, 5-500Hz, each axis, with 2.5" HDD

# Safety Certificate and Test

▶ CE; FCC Class A
▶ All plastic material, PCB and Battery used are all UL-94V0 certified

Power Requirements

<table><tr><td>Full loading Configurations</td><td>+5V</td><td>+3.3V</td><td>Total power</td></tr><tr><td>Pentium M 1.6G CPU 512MB RAM, 40GB HDD</td><td>3.976A</td><td>2.474A</td><td>28.25W</td></tr><tr><td>Pentium M 1.1G CPU 512MB RAM, 40GB HDD</td><td>2.468A</td><td>2.215A</td><td>19.65W</td></tr></table>

Table 1-2: Power Requirements

# Note:

The above power requirement values are measured on the PXI-3800 with a CPU, 512MB RAM, one mouse, and one internal 40GB slim-type HDD. The CPU is running under 100% loading. Power consumption will be decreased by 500mA for +5V and 300mA for +12V, if the external HDD is removed. Power consumption for all the other peripheral devices such as add-on cards is not included.

# 1.4 Unpacking Checklist

Check the shipping carton for any visible damage. If the shipping carton and contents are damaged, notify the dealer for a replacement. Retain the shipping carton and packing materials for inspection by the dealer. Remember to obtain authorization before returning any products to ADLINK.

Check for the following in the package. If there are any missing items, contact your dealer:

▶ PXI-3800 Controller (equipped with CPU, RAM and HDD)
▶ Y-Cable for PS/2 Keyboard and Mouse
This User's Guide
▶ ADLINK All-In-One CD

# CAUTION:

This board must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the board. Wear a grounded wrist strap when servicing components.

![The image features a triangular warning sign with a yellow background and a thick black border. Inside the triangle is a red exclamation point.](.pxi-3800-manual-4/122d943dd21b11164f2ae75ff1b599c51dd1817ca3c2872a78cb67b678abd2a7.jpg)

# 2 I/O Connectors and Pin Assignment

This chapter provides information about the board outline, connector definitions, and jumper settings to allow users to become familiar with the PXI-3800 before getting use. Included are the following topics:

▶ PXI-3800 Peripheral Connectivity
▶ PXI-3800 I/O Connectors
▶ PXI-3800 Connector Pin Assignments
▶ PXI-3800 Jumper Settings

# 2.1 Peripheral Connectivity

Table 2-1 lists the peripherals and their corresponding PXI-3800 connectors.

<table><tr><td>Peripheral</td><td>External Connector</td><td>Onboard Connector</td></tr><tr><td>Video</td><td>VGA (DB-15)</td><td>---</td></tr><tr><td>Serial Port</td><td>COM1 (DB-9)</td><td>---</td></tr><tr><td>Serial Port</td><td>COM2 (DB-9)</td><td>---</td></tr><tr><td>Parallel Port</td><td>PRN (DB-25)</td><td>---</td></tr><tr><td>PXI trigger</td><td>TRIG (SMB)</td><td>---</td></tr><tr><td>Keyboard/Mouse</td><td>PS/2 (Mini DIN-6)</td><td>---</td></tr><tr><td>IDE</td><td>---</td><td>IDE1 (44-pin)</td></tr><tr><td>IDE</td><td></td><td>IDE2 (44-pin)</td></tr><tr><td>Supported by USB-to-IDE adapter</td><td></td><td></td></tr><tr><td>Floppy (optional)</td><td>---</td><td>Slim type 26-pin</td></tr><tr><td>CompactFlash</td><td>---</td><td>CF1 Socket</td></tr><tr><td>CompactFlash</td><td>CF2 Socket (Supported by USB-to-CF adaptor)</td><td>---</td></tr><tr><td>USB 2.0 Port</td><td>USB 1,2 (USB 4-pin series)</td><td>---</td></tr><tr><td>USB 3</td><td>---</td><td>Supports USB-to-CF or USB-to-IDE adaptation</td></tr><tr><td>Gigabit Ethernet</td><td>LAN (RJ-45)</td><td>---</td></tr><tr><td>Audio speaker output</td><td>Y</td><td>---</td></tr></table>

Table 2-1: Peripheral Connectivity Table

<table><tr><td>Peripheral</td><td>External Connector</td><td>Onboard Connector</td></tr><tr><td>LEDs</td><td>Y</td><td>---</td></tr><tr><td>Reset button</td><td>Y</td><td>---</td></tr></table>

Table 2-1: Peripheral Connectivity Table

# 2.2 PXI-3800 I/O Connectors

# PXI-3800 Front Panel I/O Connectors

![COM2\nCOM1\nHot Swappable CompactFlash\nPRN\nAudio output\nPS/2 KB/MS\nTRIG I/O\nVGA\nLED & Reset\nUSB 2.0°2\n10/100Gb Ethernet](.pxi-3800-manual-4/9fb43673f6f56b0ff7c6c4ce6f86772279a403ee2318c0d78d843be660354c26.jpg)

Figure 2-1: PXI-3800 Front Panel I/O Connectors

# PXI-3800 Onboard I/O connectors

![CompactFlash\nsocket\nSO-DIMM\nsocket (on\ncore module)\nPXI J2\nconnector\nPXI J1\nconnector\n44-pin IDE\nconnector\nHard Disk\nDrive\nHDD Bracket](.pxi-3800-manual-4/13d3fb2a8bcce578ddf1e92845feb79091cec205f7cbe3e698b21162e762ae5b.jpg)

Figure 2-2: PXI-3800 Onboard I/O Connectors

# PXI-3800DB Daughter Board I/O Connectors

![COM2\n44-pin IDE connector\nCompactFlash Socket\nAudio output\nPS/2 KB/MS\nPN1](.pxi-3800-manual-4/e016ad1dfc14c950d4618a0d7c0155e0520cc1d01157823f4510083d9191f1ee.jpg)

Figure 2-3: PXI-3800DB Daughter Board I/O Connectors

# 2.3 PXI-3800 Connector Pin Assignments

# PXI Trigger Connector

![Technical line drawing of a mechanical component with a circular top and threaded end (no text or symbols)](.pxi-3800-manual-4/c2a56cf485ff3dd708dc030e3f11c8e9a960c25da07863e1f2a882d75b9d1d86.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr><tr><td>5</td><td>PXI_TRG</td><td>PXI trigger signal</td></tr></table>

Table 2-2: PXI Trigger Connector Pin Assignment

# VGA Connector

![15\n11\n5\n1\n+](.pxi-3800-manual-4/ac2c52753d22b555ef2540cd8d74e007827efae1428892b80aa644f7e52040a9.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>RED</td><td>Analog RED</td></tr><tr><td>2</td><td>GREEN</td><td>Analog GREEN</td></tr><tr><td>3</td><td>BLUE</td><td>Analog BLUE</td></tr><tr><td>4</td><td>NC</td><td>No Connect</td></tr><tr><td>5</td><td>GND</td><td>Ground</td></tr><tr><td>6</td><td>GND</td><td>Ground</td></tr><tr><td>7</td><td>GND</td><td>Ground</td></tr><tr><td>8</td><td>GND</td><td>Ground</td></tr><tr><td>9</td><td>+5V</td><td>Power In</td></tr><tr><td>10</td><td>GND</td><td>Ground</td></tr><tr><td>11</td><td>NC</td><td>No Connect</td></tr><tr><td>12</td><td>DDCDAT</td><td>DDC Data for CRT</td></tr><tr><td>13</td><td>HSYNC</td><td>Horizontal sync for Monitor</td></tr><tr><td>14</td><td>VSYNC</td><td>Vertical sync for Monitor</td></tr><tr><td>15</td><td>DDCCLK</td><td>DDC CLK for CRT</td></tr></table>

Table 2-3: VGA Connector Pin Assignment

# USB port 1, 2 Connector

![Pure technical line drawing of a mechanical component without any text, numbers, or symbols](.pxi-3800-manual-4/bfae12eb6042f97358649c6e90696df639150f1dfaebda2ab699a8a08ccf597b.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>USBVCC</td><td>Power</td></tr><tr><td>2</td><td>USB-</td><td>Data (-)</td></tr><tr><td>3</td><td>USB+</td><td>Data (+)</td></tr><tr><td>4</td><td>USBGND</td><td>Ground</td></tr></table>

Table 2-4: USB Connector Pin Assignment

# Ethernet (RJ-45) Connector

![Pin 1\nYellow LED\nGreen LED](.pxi-3800-manual-4/02f93b9aac525eab53ea8baa4ba958a245b5e44836bebd75bdff4b7b96da01b8.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>TDP</td><td>Transmit Data (+)</td></tr><tr><td>2</td><td>TDN</td><td>Transmit Data (-)</td></tr><tr><td>3</td><td>RDP</td><td>Receive Data (+)</td></tr><tr><td>4</td><td>LANCT1</td><td>Termination</td></tr><tr><td>5</td><td>LANCT2</td><td>Termination</td></tr><tr><td>6</td><td>RDN</td><td>Receive Data (-)</td></tr><tr><td>7</td><td>NC</td><td>No Connect</td></tr><tr><td>8</td><td>GND</td><td>Ground</td></tr><tr><td>9</td><td>TDP</td><td>Transmit Data (+)</td></tr></table>

Table 2-5: Ethernet Connector Pin Assignment

<table><tr><td colspan="2">Status</td><td>Yellow LED</td><td>Green LED</td></tr><tr><td colspan="2">Network link is not established</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps(10 BaseT)</td><td>Link</td><td>ON</td><td>OFF</td></tr><tr><td>Active</td><td>Flash</td><td>OFF</td></tr><tr><td rowspan="2">100 Mbps (100 BaseT)</td><td>Link</td><td>ON</td><td>OFF</td></tr><tr><td>Active</td><td>Flash</td><td>OFF</td></tr><tr><td rowspan="2">1000 Mbps (1000 BaseT)</td><td>Link</td><td>ON</td><td>ON</td></tr><tr><td>Active</td><td>Flash</td><td>ON</td></tr></table>

Table 2-6: Ethernet LED Status Definitions

# COM1, 2 Serial Port Connector DB-9

![Pin 1\nPin 9](.pxi-3800-manual-4/4bc390a229ffc1005a2cbb5cf95b5be2d7ddf6f2cf5bb229005b91c11587e00a.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>DCD#</td><td>Data Carrier Detect</td></tr><tr><td>2</td><td>RXD</td><td>Receive Data</td></tr><tr><td>3</td><td>TXD</td><td>Transmit Data</td></tr><tr><td>4</td><td>DTR#</td><td>Data Terminal Ready</td></tr><tr><td>5</td><td>GND</td><td>Ground</td></tr><tr><td>6</td><td>DSR#</td><td>Data Set Ready</td></tr><tr><td>7</td><td>RTS#</td><td>Request to Send</td></tr><tr><td>8</td><td>CTS#</td><td>Clear to Send</td></tr><tr><td>9</td><td>RI#</td><td>Ring Indicate</td></tr></table>

Table 2-7: COM Connector Pin Assignment

44-Pin IDE Connector

<table><tr><td>Pin</td><td>Signal</td><td>Function</td><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>BRSTDRVJ</td><td>Reset</td><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>DD7</td><td>Data 7</td><td>4</td><td>DD8</td><td>Data 8</td></tr><tr><td>5</td><td>DD6</td><td>Data 6</td><td>6</td><td>DD9</td><td>Data 9</td></tr><tr><td>7</td><td>DD5</td><td>Data 5</td><td>8</td><td>DD10</td><td>Data 10</td></tr><tr><td>9</td><td>DD4</td><td>Data 4</td><td>10</td><td>DD11</td><td>Data 11</td></tr><tr><td>11</td><td>DD3</td><td>Data 3</td><td>12</td><td>DD12</td><td>Data 12</td></tr><tr><td>13</td><td>DD2</td><td>Data 2</td><td>14</td><td>DD13</td><td>Data 13</td></tr><tr><td>15</td><td>DD1</td><td>Data 1</td><td>16</td><td>DD14</td><td>Data 14</td></tr><tr><td>17</td><td>DD0</td><td>Data 0</td><td>18</td><td>DD15</td><td>Data 15</td></tr><tr><td>19</td><td>GND</td><td>Ground</td><td>20</td><td>KEY</td><td>-</td></tr><tr><td>21</td><td>DDREQ</td><td>Request</td><td>22</td><td>GND</td><td>Ground</td></tr><tr><td>23</td><td>DIOWJ</td><td>I/O Write</td><td>24</td><td>GND</td><td>Ground</td></tr><tr><td>25</td><td>DIORJ</td><td>I/O Read</td><td>26</td><td>GND</td><td>Ground</td></tr><tr><td>27</td><td>IORDY</td><td>I/O Ready</td><td>28</td><td>CSEL</td><td>Cable Select</td></tr><tr><td>29</td><td>DDACKJ</td><td>DMA Acknowledge</td><td>30</td><td>GND</td><td>Ground</td></tr><tr><td>31</td><td>IRQ14</td><td>Interrupt Request</td><td>32</td><td>NC</td><td>No Connect</td></tr><tr><td>33</td><td>DA1</td><td>Device Address 1</td><td>34</td><td>66DECT</td><td>ATA 66/100 detect</td></tr><tr><td>35</td><td>DA0</td><td>Device Address 0</td><td>36</td><td>DA2</td><td>Device Address 2</td></tr><tr><td>37</td><td>CS1PJ</td><td>Chip Select 1</td><td>38</td><td>CS3PJ</td><td>Chip Select 3</td></tr><tr><td>39</td><td>IDEACTPJ</td><td>Device Active</td><td>40</td><td>GND</td><td>Ground</td></tr><tr><td>41</td><td>+5V</td><td>+5V</td><td>42</td><td>+5V</td><td>+5V</td></tr><tr><td>43</td><td>GND</td><td>Ground</td><td>44</td><td>NC</td><td>No Connect</td></tr></table>

Table 2-8: IDE 44-pin Connector Pin Assignment

# LPT Printer Port Connector DB-25

![25\n13\n14\n1](.pxi-3800-manual-4/85c67c5d70692f38bfa84177abc43461a5438fcc8248331582a767741becebbd.jpg)

<table><tr><td>Signal Name</td><td>Pin</td><td>Pin</td><td>Signal Name</td></tr><tr><td>Line printer strobe</td><td>1</td><td>14</td><td>AutoFeed</td></tr><tr><td>PD0, parallel data 0</td><td>2</td><td>15</td><td>Error</td></tr><tr><td>PD1, parallel data 1</td><td>3</td><td>16</td><td>Initialize</td></tr><tr><td>PD2, parallel data 2</td><td>4</td><td>17</td><td>Select In</td></tr><tr><td>PD3, parallel data 3</td><td>5</td><td>18</td><td>Ground</td></tr><tr><td>PD4, parallel data 4</td><td>6</td><td>19</td><td>Ground</td></tr><tr><td>PD5, parallel data 5</td><td>7</td><td>20</td><td>Ground</td></tr><tr><td>PD6, parallel data 6</td><td>8</td><td>21</td><td>Ground</td></tr><tr><td>PD7, parallel data 7</td><td>9</td><td>22</td><td>Ground</td></tr><tr><td>ACK, acknowledge</td><td>10</td><td>23</td><td>Ground</td></tr><tr><td>Busy</td><td>11</td><td>24</td><td>Ground</td></tr><tr><td>Paper empty</td><td>12</td><td>25</td><td>Ground</td></tr><tr><td>Select</td><td>13</td><td></td><td></td></tr></table>

Table 2-9: LPT Connector Pin Assignment

# General Purpose LED definitions

<table><tr><td>LED</td><td>Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="2">System Active (PW)</td><td rowspan="2">Green</td><td>OFF</td><td>System power not on or power failure</td></tr><tr><td>ON</td><td>Power ON</td></tr><tr><td rowspan="2">IDE (HD)</td><td rowspan="2">Yellow</td><td>OFF</td><td>IDE idle</td></tr><tr><td>Flash</td><td>IDE access</td></tr><tr><td rowspan="3">WDT (WD)</td><td rowspan="3">Red</td><td>OFF</td><td>WDT not enabled</td></tr><tr><td>Flash</td><td>WDT enabled</td></tr><tr><td>ON</td><td>WDT timeout occur</td></tr><tr><td rowspan="2">General Purpose (GP)</td><td rowspan="2">Blue</td><td>OFF</td><td>Board inserted and power on</td></tr><tr><td>ON</td><td>Board inserted but not powered on</td></tr></table>

Table 2-10: General Purpose LED Definitions

# Compact Flash Type I/II Connector

![1\n50](.pxi-3800-manual-4/3955bff1bd1fdecdf47ade87ee328f69f86a23d1015b01b9b1aa39dc28e154a2.jpg)

<table><tr><td>Signal Name</td><td>Pin</td><td>Pin</td><td>Signal Name</td></tr><tr><td>GND</td><td>1</td><td>26</td><td>GND</td></tr><tr><td>SDD3</td><td>2</td><td>27</td><td>SDD11</td></tr><tr><td>SDD4</td><td>3</td><td>28</td><td>SDD12</td></tr><tr><td>SDD5</td><td>4</td><td>29</td><td>SDD13</td></tr><tr><td>SDD6</td><td>5</td><td>30</td><td>SDD14</td></tr><tr><td>SDD7</td><td>6</td><td>31</td><td>SDD15</td></tr><tr><td>SDCS#1</td><td>7</td><td>32</td><td>SDCS#3</td></tr><tr><td>GND</td><td>8</td><td>33</td><td>GND</td></tr><tr><td>GND</td><td>9</td><td>34</td><td>SDIOR#</td></tr><tr><td>GND</td><td>10</td><td>35</td><td>SDIOW#</td></tr><tr><td>GND</td><td>11</td><td>36</td><td>+5V</td></tr><tr><td>GND</td><td>12</td><td>37</td><td>IDEIRQ14</td></tr><tr><td>+5V</td><td>13</td><td>38</td><td>+5V</td></tr><tr><td>GND</td><td>14</td><td>39</td><td>PCSEL</td></tr><tr><td>GND</td><td>15</td><td>40</td><td>NC</td></tr><tr><td>GND</td><td>16</td><td>41</td><td>SIDERST#</td></tr><tr><td>GND</td><td>17</td><td>42</td><td>SIORDY</td></tr><tr><td>SDA2</td><td>18</td><td>43</td><td>NC</td></tr><tr><td>SDA1</td><td>19</td><td>44</td><td>SDDACK#</td></tr><tr><td>SDA0</td><td>20</td><td>45</td><td>IDEACT#</td></tr><tr><td>SDD0</td><td>21</td><td>46</td><td>S66DECT</td></tr><tr><td>SDD1</td><td>22</td><td>47</td><td>SDD8</td></tr><tr><td>SDD2</td><td>23</td><td>48</td><td>SDD9</td></tr><tr><td>IOIS16#</td><td>24</td><td>49</td><td>SDD10</td></tr><tr><td>GND</td><td>25</td><td>50</td><td>GND</td></tr></table>

Table 2-11: Compact Flash Connector Pin Assignment

# Slim Type FDD connector

![1\n26\n26\n1](.pxi-3800-manual-4/117d70b9648b7ad366b88219115337d67c57c5495262cc7b2b8b32ff5aa08998.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>VCC</td><td>Power</td></tr><tr><td>2</td><td>INDEX#</td><td>Index</td></tr><tr><td>3</td><td>VCC</td><td>Power</td></tr><tr><td>4</td><td>DS0#</td><td>Drive 0 Select</td></tr><tr><td>5</td><td>VCC</td><td>Power</td></tr><tr><td>6</td><td>DSKCHG#</td><td>Disk Change</td></tr><tr><td>7</td><td>NC</td><td></td></tr><tr><td>8</td><td>DRATE0</td><td>Data Rate</td></tr><tr><td>9</td><td>RPM</td><td>Drive Density Select 0</td></tr><tr><td>10</td><td>MTR0#</td><td>Motor A On</td></tr><tr><td>11</td><td>NC</td><td></td></tr><tr><td>12</td><td>FDIR#</td><td>Step Direction</td></tr><tr><td>13</td><td>NC</td><td></td></tr><tr><td>14</td><td>STEP#</td><td>Step Pulse</td></tr><tr><td>15</td><td>GND</td><td>Ground</td></tr><tr><td>16</td><td>WDATA#</td><td>Write Data</td></tr><tr><td>17</td><td>GND</td><td>Ground</td></tr><tr><td>18</td><td>WGATE#</td><td>Write Gate</td></tr><tr><td>19</td><td>NC</td><td></td></tr><tr><td>20</td><td>TRK0#</td><td>Track 0</td></tr><tr><td>21</td><td>NC</td><td></td></tr><tr><td>22</td><td>WRTPRT#</td><td>Write Protect</td></tr><tr><td>23</td><td>GND</td><td>Ground</td></tr><tr><td>24</td><td>RDATA#</td><td>Read Data</td></tr><tr><td>25</td><td>GND</td><td>Ground</td></tr><tr><td>26</td><td>HDSEL#</td><td>Head Select</td></tr></table>

Table 2-12: Slim Type Floppy Connector Pin Assignment

# PS/2 Keyboard/Mouse Combo Connector (Mini DIN-6)

![Pure electrical component diagram without any text, numbers, or symbols](.pxi-3800-manual-4/371f723ce45fae0eef3e85044664b13a0d9d283bd75ed453ce359e16cf34e797.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>VCC</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

Table 2-13: PS/2 Connector Pin Assignment

J1 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>J1-25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>J1-24</td><td>GND</td><td>AD[1]</td><td>+5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>J1-23</td><td>GND</td><td>+3.3V</td><td>AD[4]</td><td>AD[3]</td><td>+5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>J1-22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>+3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>J1-21</td><td>GND</td><td>+3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>J1-20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>J1-19</td><td>GND</td><td>+3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>J1-18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>J1-17</td><td>GND</td><td>+3.3V</td><td>NC</td><td>NC</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>J1-16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>J1-15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>J1-12~14</td><td colspan="7">Keying Area</td></tr><tr><td>J1-11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>J1-10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>+3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>J1-9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>J1-8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>J1-7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>J1-6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>+3.3V</td><td>CLK0</td><td>AD[31]</td><td>GND</td></tr><tr><td>J1-5</td><td>GND</td><td>NC</td><td>NC</td><td>RST#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>J1-4</td><td>GND</td><td>NC</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>J1-3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>+5V</td><td>INTD#</td><td>GND</td></tr><tr><td>J1-2</td><td>GND</td><td>TCK</td><td>+5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>J1-1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Table 2-14: J1 Connector Pin Assignment

J2 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>J2-22</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>J2-21</td><td>GND</td><td>CLK6</td><td>GND</td><td>NC</td><td>RSV</td><td>RSV#</td><td>GND</td></tr><tr><td>J2-20</td><td>GND</td><td>CLK5</td><td>GND</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>J2-19</td><td>GND</td><td>GND</td><td>GND</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT#</td><td>GND</td></tr><tr><td>J2-18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>J2-17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>REST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>J2-16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>DEG#</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>J2-15</td><td>GND</td><td>NC</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>J2-14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>J2-13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>J2-12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>J2-11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>J2-10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>J2-9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>J2-8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>J2-7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>J2-6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>J2-5</td><td>GND</td><td>C/BE[5]</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>J2-4</td><td>GND</td><td>V(I/O)</td><td>NC</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>J2-3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>J2-2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>J2-1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Table 2-15: J2 Connector Pin Assignment

# 2.4 PXI-3800 Jumper Settings

The PXI-3800 is designed for maximum flexibility with a minimum number of jumpers. Most of the configuration options can be selected through the BIOS menu. However, some options require configuration by jumper.

# Note:

There is no jumper for Front Side Bus (FSB) or CPU frequency selection. The FSB and CPU frequency are set by auto-detection.

The PXI-3800 is assembled with three boards including one core module, one carrier board, and one daughter board. Table 17 lists the functions of the jumpers on the PXI-3800. Please refer to the figure below for the location of the jumpers on PXI-3800 carrier board and Figure 2-20 for the location of JP4 on the PXI-3800DB daughter board.

<table><tr><td>Jumper</td><td>Location</td><td>Description</td></tr><tr><td>JP7</td><td>PXI-3800 Carrier board</td><td>Clear CMOS</td></tr><tr><td>JP2</td><td>PXI-3800 Carrier board</td><td>CF1 Master/Slave Selection</td></tr><tr><td>JP3~5</td><td>PXI-3800 Carrier board</td><td>COM1 RS232/422/RS485 Selection</td></tr><tr><td>JP4</td><td>PXI-3800DB Daughter board</td><td>USB-to-CF/USB-to-IDE selection</td></tr></table>

Table 2-16: Jumpers Definition on the PXI-3800

![JP3\nJP4\nJP5\nJP3~5\nCOM1\nRS232/422/485\nSelection\nJP2\nCF1 Master/Slave\nselection\nJP7\nClear COMS](.pxi-3800-manual-4/b248c786df5ff7977495a927c1004568f2b04116ae8d6470b54d690270a66b6e.jpg)

Figure 2-4: PXI-3800 Carrier Board Jumper Locations

Clear CMOS (PXI-3800, JP7)

<table><tr><td>Status</td><td>JP7</td></tr><tr><td>Normal operation (Default)</td><td>3 2 1&lt;img src="images/973b9e165fe7da0b318ea4c086c2265f4321b10f81973b84db96449f474c20ba.jpg"/&gt;</td></tr><tr><td>Clear CMOS</td><td>3 2 1&lt;img src="images/5789a274bfeba1ffbc458acb5331287d7e3c352dd6f1dc66fe23f62465dd60c2.jpg"/&gt;</td></tr></table>

Table 2-17: Clear CMOS Jumper Setting

JP7 is a 3-pin jumper that can be used to clear the CMOS memory. The CMOS RAM stores the real time clock (RTC) information, BIOS configuration, and default BIOS settings. The CMOS is powered by a button cell battery when the system is powered off.

Follow the steps below to clear the CMOS RAM data:

1. Remove the PXI-3800 CPU module from chassis.
2. Short pins 2 and 3 of JP7, then reinstall the jumper back to its normal location.
3. Insert the PXI-3800 back into the chassis. Turn the power on.

# CompactFlash Master/Slave Selection (PXI-3800, JP2)

<table><tr><td>Status</td><td>JP2</td></tr><tr><td>CF1 Slave (Default)</td><td>1 2 3&lt;img src="images/1c28313f4762aef05b5dccb06231484b398ba2968e810ed21c85502a0b72c712.jpg"/&gt;</td></tr><tr><td>CF1 Master</td><td>&lt;img src="images/d964ad76da490b58f85bd54c3029437558ccacbadfcdab82db9dfd487c70b28d.jpg"/&gt;</td></tr></table>

Table 2-18: CompactFlash Master/Slave Jumper Setting

The CompactFlash Master/Slave jumper (JP2) allows the selection of the CF card to be configured as either a master or slave IDE device if there is more than one storage device installed in the system.

# COM port Operation Mode Selection (PXI-3800, JP3\~JP5)

By setting the JP3\~JP5 jumpers on the PXI-3800 carrier board, COM1 can be selected to operate under RS-232, RS-422, or RS-485 communications protocols. The default factory setting is RS-232 mode.

<table><tr><td>Type</td><td>JP3</td><td colspan="3">JP4</td><td colspan="3">JP5</td></tr><tr><td rowspan="3">RS-232(Default)</td><td rowspan="3">2 4 6&lt;img src="images/048c51fea5eb71fda2ce5a1e52dd932d8c228ac9f7256a9948c1dbbebc32e5be.jpg"/&gt;</td><td>6</td><td rowspan="3">&lt;img src="images/5898099766838b3c78f5c77fedbd7f733c6f21cd50aed469a167ef2c2135c46d.jpg"/&gt;</td><td>3</td><td>6</td><td rowspan="3">&lt;img src="images/22d380031df8a83c954137bbd7a57887ad97459436a461bdf66fc3f5f1af83bb.jpg"/&gt;</td><td>3</td></tr><tr><td>5</td><td>2</td><td>5</td><td>2</td></tr><tr><td>4</td><td>1</td><td>4</td><td>1</td></tr><tr><td rowspan="3">RS-422</td><td rowspan="3">2 4 6&lt;img src="images/e35206566bd54680cebfb66a9fa7839113e46cc15ff2f9382b4ac720f2190edc.jpg"/&gt;</td><td>6</td><td rowspan="3">&lt;img src="images/c413d8cf75b45aebf2f6e7c2a273447515a7103e9f0128389c9b7619c6a9a774.jpg"/&gt;</td><td>3</td><td>6</td><td rowspan="3">&lt;img src="images/6212d568dc88ccb97c7aed006fb4e44309911362110087dcfbfa467924a1952d.jpg"/&gt;</td><td>3</td></tr><tr><td>5</td><td>2</td><td>5</td><td>2</td></tr><tr><td>4</td><td>1</td><td>4</td><td>1</td></tr><tr><td rowspan="3">RS-485</td><td rowspan="3">2 4 6&lt;img src="images/c67b3d7c7f71d1ddf699062cd106882c360454a15f5b2ffea2f9dc488095219c.jpg"/&gt;</td><td>6</td><td rowspan="3">&lt;img src="images/9071eb3a909ba47d9f6b7b49edcefc0f8e7e6a2e14b1e85b64aa50e82786af08.jpg"/&gt;</td><td>3</td><td>6</td><td rowspan="3">&lt;img src="images/acfbc85e680c5f7e86be82d8225554fe2a2d8fdd95d6ed3fd5dc0f9733355281.jpg"/&gt;</td><td>3</td></tr><tr><td>5</td><td>2</td><td>5</td><td>2</td></tr><tr><td>4</td><td>1</td><td>4</td><td>1</td></tr></table>

Table 2-19: COM port Operation Mode Jumper Setting

# USB-to-CF/USB-to-IDE Selection (PXI-3800DB, JP4)

By setting the JP4 jumper on the PXI-3800DB daughter board, the USB port can be set to either USB-to-CF or USB-to-IDE adaptation to support a CompactFlash socket on front panel or a 2.5" IDE HDD. The default factory setting is USB-to-CF mode.

<table><tr><td>Status</td><td>JP4</td></tr><tr><td>Enable USB-to-CF (Default)</td><td>&lt;img src="images/a9610b6c1c8c308c597f87435abe2ebd606ebfc3e00e60f8773ce77346316c50.jpg"/&gt;</td></tr><tr><td>Enable USB-to-IDE</td><td>6 35 &lt;img src="images/3a0647e972f31d1b150514acb409a0a4664990fc95ad9c0ee4396e5929e1eba9.jpg"/&gt; 24 1</td></tr></table>

Table 2-20: USB-to-CF/USB-to-IDE Selection Jumper Setting

# 3 Getting Started

This chapter gives a summary of what is required to set up an operating system using the PXI-3800. Hardware installation and BIOS setup are also discussed. Note that the PXI-3800 is shipped with CPU, RAM and HDD preinstalled. The installations of the CPU, RAM, and HDD are done at the ADLINK factory and the procedures described in the following sections are for users' reference. If the default configuration does not suit your application needs, contact a local ADLINK dealer for special configurations or OEM versions.

# 3.1 Installing the PXI-3800

Use the following procedure to install the PXI-3800 controller into a PXI chassis. Consult your PXI chassis user guide for specific instructions and warnings.

# Step 1:

Plug in your chassis before installing the PXI-3800. Make sure the system power is turned off.

# Step 2:

Remove the blank face panel from the system slot.

# Step 3:

Align the top and bottom edges of the board with the card guides on the chassis, then slide the board into the chassis until resistance is felt.

# Step 4:

Move the locking handle in an inward direction until it is fully latched. Please note that slight resistance will be felt while inserting the board. If this resistance is more than under normal conditions, check to ensure that there are no bent pins on the backplane and that the board's connector pins are aligned properly with the connectors on the backplane.

# Step 5:

Verify that the board is seated properly. Secure the four screws at the top and bottom of the front panel; connect the appropriate cables to the board. The system can now be powered on.

Figure 3-1 shows a PXI-3800 being installed in the system slot of an ADLINK PXIS-2506 chassis.

![Exterior view of a CompactPDT3 PLC internal unit with visible ports, connectors, and external modules (no readable text or symbols beyond branding)](.pxi-3800-manual-4/05685181bb90cea5cf8bfc9b9f696c874f4d61c434e50560a4defbd10bc4bebd.jpg)

Figure 3-1: PXI-3800 System Controller being installed in a PXI Chassis

# How to Remove the Controller from the PXI Chassis

# Step 1:

Power off the chassis.

# Step 2:

Loosen the four screws in the front panel.

# Step 3:

Press down on the ejector handle.

# Step 4:

Slide the controller out of the chassis.

# 3.2 Memory Module Installation

The PXI-3800 controller has two 200-pin DDR SO-DIMM sockets and supports up to 2GB RAM. The memory module that comes with the standard PXI-3800 is a 512MB SDRAM module. You can upgrade the amount of installed RAM by changing the SO-DIMM module or adding a second SDRAM module. It is necessary to disassemble the PXI-3800 to install an SDRAM module in either the DM1 or DM2 socket on the PXI-3800 main board (one on each side), so we recommend that users have SDRAM installed professionally by ADLINK.

For applications requiring memory other than the standard 512MB, please contact a local ADLINK dealer for details.

# Installing the first memory module

Please refer to Figure 3-2 below to install the first memory module. After removing the heatsink, insert the module at a 30 degree angle and push the module firmly but gently into the slot until the security latches on the socket have locked into place on both sides of the module.

![Memory Module\nHeat Sink\nMemory Socket\nPXI-3800 Core Module](.pxi-3800-manual-4/579151e1cb6e954eb7097b8b47c13ffcbe8023e69b7231fbfcd7c0bd7c8bfe12.jpg)

Figure 3-2: First Memory Module Installation (preinstalled by ADLINK)

# Installing the second memory module

After carefully removing the PXI-3800 Core Module from the Carrier Board, insert the second memory module into the slot on the underside of the Main Board as shown in Figure 3-3 below using the same procedure as described above for installation of the first memory module.

![PXI-3800\nCore Module\nMemory\nSocket\nCompactFlash\nSocket\nPXI-3800\nCarrier Board](.pxi-3800-manual-4/e9a7d1217d1a22cf9bcfd6d79c21c124214327009d250bd798fc0ee768a4a6f3.jpg)

Figure 3-3: Second Memory Module Installation

# 3.3 HDD and CF Installation

The PXI-3800 is equipped with a set of slim-type HDD mounting brackets that accommodate a 2.5 inch IDE hard drive. A 40GB HDD is installed by default. For applications with different hard drive requirements, please contact a local ADLINK dealer for details.

You may purchase an off-the-shelf 2.5" HDD. However, due to space limitations and ventilation considerations, a low profile 2.5" HDD that is no thicker than 9.5mm is recommended.

# HDD Installation

To change the HDD, follow these procedures carefully:

# Step 1:

Check that the jumper setting of JP2 on the PXI-3800 is across pins 1 and 2.

# Step 2:

Screw the HDD to the hard drive mounting bracket. Please note the orientation of the HDD. The HDD's pin #1 must match the location of IDE connector pin #1.

# Step 3:

Install the HDD with mounting bracket plate on the Core Module of the PXI-3800

# Step 4:

Use four copper stand-off screws to fasten the HDD to the Core Module

# Step 5:

Connect a 44-pin HDD cable to the HDD. Ensure that pin #1 of the IDE connector, cable and the HDD are properly matched.

# CompactFlash Card Installation

The CompactFlash Card (or CF storage card) is widely used in digital consumer devices like PDAs, digital cameras, and MP3 players. The CF format features anti-shock and anti-vibration properties, improved environmental tolerance, low power consumption, a small form factor, and higher reliability. Plus, it has been widely accepted in the industrial and embedded application field.

The PXI-3800 has an internal as well as an external CompactFlash socket. Please see Figure 3-3 for the internal CF socket location. To install the internal CompactFlash socket which can be used as HDD replacement, simply insert the CF card into the socket. To remove it, push the ejector button on the side of the socket and extract the card. Please note that the internal CF interface is NOT hot swappable, and installation or removal should be done when the system power is off. The external CF interface is hot swappable so users can install or remove via the front panel while the system is running.

# 3.4 BIOS Configuration Overview

The Basic Input/Output System (BIOS) is a program that provides the basic level of communication between the processor and peripherals. In addition, the BIOS also contain code for various advanced features found in the system board. The BIOS setup program includes menus for configuring settings and enabling PXI-3800 controller features. Most users do not need to use the BIOS setup program, as the PXI-3800 controller ships with default settings that work well for most configurations. Please refer to the BIOS Manual in the ADLINK All-In-One CD for more detail information about the BIOS and other utilities. You can find the manual under the directory:

X:\Manual\PXI Platform\PXI Controller\PXI-3800

# CAUTION:

![The image displays a yellow triangular warning sign with a thick black border. Centered inside the triangle is a red exclamation point. The very top tip of the triangle is partially obscured by a black horizontal bar.](.pxi-3800-manual-4/6205f6681525a28af99ca41fee32e66fcab7d73bc2e382539afa85d7646a206d.jpg)

Changing BIOS settings may lead to incorrect controller behavior and possibly an unbootable controller. If this happens, follow the instructions in Section 2.4 to clear CMOS and restore the default settings. In general, do not change a BIOS setting unless you are absolutely certain of what it does.

# 3.5 Operating System Installation

For more detailed information about the operating system, refer to the documentation provided by the operating system vendor.

PXI/CompactPCI devices are automatically configured by the BIOS during the boot sequence.

Most operating systems require initial installation on a hard drive from a floppy or a CD-ROM drive. These devices should be configured, installed, and tested with the supplied drivers before attempting to load the new operating system.

Read the release notes and installation documentation provided by the operating system vendor. Be sure to read all the README files or documents provided on the distribution disks, as these typically note documentation discrepancies or compatibility problems.

Select the appropriate boot device order in the SETUP/BIOS boot menu depending on the OS installation media used. For example, if the OS includes a bootable installation CD, select USB CD-ROM as the first boot device and reboot the system with the installation CD installed in the USB CD-ROM drive.

Proceed with the OS installation as directed and be sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of ADLINK PXI products.

When installation is complete, reboot the system and set the boot device order in the SETUP boot menu appropriately.

# 3.6 Boot PXI-3800 via USB ports or CompactFlash sockets

This section describes how to boot PXI-3800 via USB ports or CompactFlash sockets (onboard or on the front panel). Please follow the instructions below:

# Boot from USB-CDROM Drive

# Step 1:

Connect the USB CDROM Drive via a USB port on the front panel.

# Step 2:

Put a boot CD in the USB CDROM Drive.

# Step 3:

Power on the PXI-3800 and enter BIOS to modify the Boot Device setting as follows:

Advanced BIOS Features > First Boot Device [USB-CDROM]

# Step 4:

Save the change

# Step 5:

Reboot the system

# Boot from USB Floppy Drive

# Step 1:

Connect USB Floppy Drive via a USB port on the front panel.

# Step 2:

Put a boot disk in the USB Floppy Drive.

# Step 3:

Power on the PXI-3800 and enter BIOS to modify the Boot Device setting as follows:

Advanced BIOS Features > First Boot Device [USB-FDD]

# Step 4:

Save the change

# Step 5:

Reboot the system

# Boot from the front panel CompactFlash Drive

# Step 1:

Put a boot CF disk in the CompactFlash socket on the front panel.

# Step 2:

Power on the PXI-3800 and enter BIOS to modify the Boot Device setting as follows.

Advanced BIOS Features > First Boot Device [USB-HDD]

# Step 3:

Save the change

# Step 4:

Reboot the system

# Boot from the onboard CompactFlash Drive

# Step 1:

Put a boot CF disk in the CompactFlash socket embedded inside the PXI-3800.

# Step 2:

Power on the PXI-3800 and enter BIOS to modify the Boot Device setting as follows.

Advanced BIOS Features > First Boot Device [HDD-1]

# Step 3:

Save the change

# Step 4:

Reboot the system

# 4 Driver Installation

The driver installation instructions for Windows 2000 and Windows XP are described below.

To install Windows drivers:

# Step 1:

Fully install Windows properly before installing any drivers. Most of the standard I/O device drivers have been included in Windows.

# Step 2:

Install the chipset driver.

# Step 3:

Install the VGA driver.

# Step 4:

Install the LAN driver.

# Step 5:

Install the Audio driver.

# Step 6:

Install the PXI Trigger driver.

To ensure compatibility, it is recommended that the chipset, VGA, LAN, Audio, and PXI Trigger drivers provided in the ADLINK All-In-One CD are used. For Linux drivers, please contact ADLINK.

To install the Windows drivers for the PXI-3800 system controller, refer to the installation information in this chapter. For installation information for non-Windows operating systems, please contact an ADLINK service center. The Windows drivers are located in the following directories of the ADLINK All-In-One CD:

<table><tr><td>Chipset driver</td><td>\Driver Installation\PXI Platform\PXI controller\PXI-3800\chipset\Win2KXP</td></tr><tr><td>VGA driver</td><td>\Driver Installation\PXI Platform\PXI controller\PXI-3800\VGA\</td></tr><tr><td>LAN driver</td><td>\Driver Installation\PXI Platform\PXI controller\PXI-3800\LAN\</td></tr><tr><td>Audio driver</td><td>\Driver Installation\PXI Platform\PXI controller\PXI-3800\Audio\</td></tr><tr><td>PXI Trigger driver</td><td>\Driver Installation\PXI Platform\PXI controller\PXI-3800\PXI_Trigger\</td></tr></table>

The Bus-mastering IDE drivers are automatically installed by Windows.

For using USB 2.0, please update to the newest Windows Service Pack.

# 4.1 Chipset Driver Installation

This section describes the system requirements of Intel® 855GME chipset device drivers. The drivers are designed for and tested with Windows 2000/XP. The system must contain a supported Intel processor and chipset configuration. Ensure that a mouse is connected to the system. One of the following versions of Windows 2000/XP must be installed on the system prior to running the utility program.

▶ Windows XP Version 2002 (Original release)
▶ Windows 2000 5.00.2195 (Original release)

# Installing Hardware Configuration File

Follow the instructions below to install the hardware configuration file on a Windows 2000/XP system.

Note: Record the location of the Windows 2000/XP directory before installing the drivers.

# Step 1:

Check the System Requirements. Windows 2000/XP must be fully installed and running on the system prior to running this software.

# Step 2:

Close any running applications.

# Step 3:

The files are stored in an integrated Windows 2000/XP application setup program.

# Step 4:

Insert the ADLINK All-In-One CD, run the infinst\_enu.exe file at

X:\Driver Installation\PXI Platform\PXI controller\PXI-3800\chipset\Win2kXP\ (where X is the CD-ROM drive).

# Step 5:

Click Next on the Welcome Screen to read and agree to the license agreement. Click Yes if you agree to continue. NOTE: If you click No, the program will terminate.

# Step 6:

Click Next on the Readme Information screen to install INF files.

# Step 7:

Click Finish to restart the system when prompted.

# Step 8:

Follow the screen instructions and use default settings to complete setup when Windows 2000/XP restarts. Upon restart, Windows may display a dialog box announcing new hardware has been found and installs drivers for them. If a New Hardware Found dialog box is displayed requesting the location of the drivers, click on the scrollbar and select the Windows directory.

# Step 9:

Select Yes, when prompted to restart Windows.

# 4.2 VGA Driver Installation

This section describes the VGA driver installation for the onboard VGA controller Intel® 855E GMCH2. The relative drivers are located in X:\Driver Installation\PXI Platform\PXI Controller\PXI-3800\VGA\ of the ADLINK All-In-One CD, where X: is the drive letter of the CD-ROM drive. The VGA drivers for Windows 2000/XP and Linux are included.

Windows 2000 and Windows XP may try to install the standard VGA driver. To ensure compatibility, manually install the latest driver, which is included in the ADLINK All-In-One CD. To update to the new driver, follow the steps below:

# Step 1:

Boot Windows and execute the win2k\_xp149.exe file under this directory: X:\Driver Installation\PXI Platform\PXI controller\PXI-3800\VGA\Win2kXP

# Step 2:

Follow the prompts. The VGA driver will automatically be installed onto the system.

# Step 3:

Restart the system.

<table><tr><td>Note:</td><td>After installing the VGA/AGP drivers in Windows, it is possible to find the drivers not working correctly. This may be caused by failing to install the Windows service pack beforehand. Ensure that the Windows service pack is installed to enable AGP capability.</td></tr></table>

# 4.3 LAN Driver Installation

This section describes the LAN driver installation for the onboard Intel® 82545EM Gigabit Ethernet controller. The drivers included in the ADLINK All-In-One CD support Windows 2000/XP and Linux.

Windows 2000/XP will attempt to install a LAN driver automatically. To ensure compatibility, manually install the latest LAN driver, which is stored on the ADLINK All-In-One CD. After installing Windows 2000/XP, update to the new driver by following these procedures:

# Step 1:

Boot Windows and execute the pro2kxp.exe file under the directory: X:\Driver Installation\PXI Platform\PXI controller\PXI-3800\LAN\Win2kXP\

# Step 2:

Following prompt instructions, The LAN driver will automatically be installed on the system.

# Step 3:

Restart the system.

# 4.4 Audio Codec Driver Installation

This section outlines the Audio Codec driver installation for the onboard AC97' Codec. The drivers included on the ADLINK All-In-One CD support Windows 2000/XP and Linux. Follow the instructions below to install the Audio driver for Windows 2000/XP.

# Step 1:

Execute the wdm\_a365.exe file in the following path location:

X:\Driver Installation\PXI Platform\PXI controller\PXI-3800\Audio\Win2kXP\

# Step 2:

Click Next on the Welcome audio setup screen to install driver.

# Step 3:

Finally, click Finish to restart.

# 4.5 PXI Trigger Driver Installation

This section outlines the PXI Trigger driver installation. The driver included on the ADLINK All-In-One CD supports Windows 2000. To install the driver for PXI Trigger, follow the instructions below:

# Step 1:

Execute the setup.exe file in the following path location:

X:\Driver Installation\PXI Platform\PXI controller\PXI-3800\PXI\_Trigger\Win2k\

# Step 2:

Click Next on the Welcome PXI Trigger setup screen to install the driver.

# Step 3:

Finally, click Finish to restart.

# 5 Utilities

This chapter explains extended functions of the PXI-3800 controller, including watchdog timer (WDT), Intel Pre-boot Execution Environment (PXE) and hot swappable function.

# 5.1 Watchdog Timer Overview

PXI-3800 has two different type watchdog timers (WDT), one is integrated into the south bridge 6300ESB and another is integrated into the super I/O W83627HF. The primary function of the WDT is to monitor the PXI-3800 operation and to generate IRQs and send a signal to PXI Trigger or reset the system if the software fails to function as programmed. The major features of the watchdog timer are:

1. Enabled and disabled through software control
2. Armed and strobed through software control

# Intel® 6300ESB ICH Watchdog Timer

The Intel® 6300ESB ICH includes a two-stage Watchdog Timer (WDT) that provides a resolution ranging from one micro second to ten minutes. The timer uses a 35-bit Down-Counter. The counter is loaded with the value from the first Preload register. The timer is then enabled and starts counting down. The time at which the WDT first starts counting down is called the first state. If the host fails to reload the WDT before the 35-bit down counter reaches zero the WDT generates an internal interrupt. After the interrupt is generated, the WDT loads the value from the second Preload register into the WDT's 35-bit Down-Counter and starts counting down. The WDT is now in the second stage. If the host still fails to reload the WDT before the second timeout, the WDT drives the WDT\_TOUT# pin low. The WDT\_TOUT# pin is held low until the system is reset. Users can choose to reset the system or send a PXI Trigger signal through BIOS WDT setting.

![**Labeled Blocks:**\n*   PCI\n*   PCI Configuration Registers\n*   Preload Value 1\n*   Preload Value 2\n*   Down-Counter\n*   Reset/Interrupt Control Logic\n*   WDT_TOUT# (External)\n*   IRQ/SMI (Internal)\n\n**Connections:**\n*   A bidirectional arrow connects **PCI** and **PCI Configuration Registers**.\n*   Arrows from **PCI Configuration Registers** point to **Preload Value 1**, **Preload Value 2**, and **Down-Counter**.\n*   Arrows from **Preload Value 1** and **Preload Value 2** point to **Down-Counter**.\n*   An arrow from **Down-Counter** points back to **PCI Configuration Registers**.\n*   An arrow from **Down-Counter** points to **Reset/Interrupt Control Logic**.\n*   An arrow from **Reset/Interrupt Control Logic** points back to **PCI Configuration Registers**.\n*   Arrows from **Reset/Interrupt Control Logic** point to **WDT_TOUT# (External)** and **IRQ/SMI (Internal)**.](.pxi-3800-manual-4/9b2d00e21bc031bffeb12663e83a4aa153cbb7a1168d8b0e174cf98891abe9bc.jpg)

Figure 5-1: Intel® 6300ESB Watchdog Timer Architecture

# Configuration Registers

The Intel® 6300ESB WDT appears to BIOS as PCI Bus -0, Device 29, Function 4, and has the standard set of PCI Configuration register. The configuration registers are described below.

# Offset 10H: Base Address Register (BAR)

This register determines the memory base for WDT down-counter setting. It will be used to set Preload value 1 register, Preload value 2 register, General Interrupt Status register and Reload register.

# Preload Value 1& 2 registers

These two registers are used to hold the preload value for the WDT timer. Its value will be automatically transferred into the down-counter every time the WDT enters the first stage and second stage. Preload Value 1 register locates at Base + 00H and Preload Value 2 register locates at Base + 04H. Only bit [19:0] can be set.

The register unlocking sequence is necessary when writing to the Preload registers. The procedure of writing a value into pre-load value 1 and 2 register is as follows:

1. Write 80H to offset BAR + 0CH.
2. Write 86H to offset BAR + 0CH.
3. Write desired value to preload register. (BAR + 00H or BAR + 04H)

# General Interrupt Status Register

This register is at Base + 08H. Bit 0 is set when the first stage of down-counter reaches zero.

Bit 0 = 0 - No Interrupt

Bit 1 = 1 - Interrupt Active

# Reload Register

This register is at Base + 0CH. Write 1 to bit 8 will reload the down-counter's value. Instructions on preventing a timeout is as follows:

1. Write 80H to offset BAR + 0CH.
2. Write 86H to offset BAR + 0CH.
3. Write a '1' to RELOAD[8] of the reload register.

# Offset 60 - 61H: WDT Configuration Register

Bit 5 indicates whether or not the WDT will toggle the WDT\_TOUT# pin when WDT times out. (0=Enabled, 1=Disabled)

Bit 2 provides two options for prescaling the main down-counter. (0=1ms - 10min, 1=1us—1sec)

Bit [1:0] allows the user to choose the type of interrupt when the WDT reaches the end of the first stage without being reset. (00 = IRQ, 01 = reserved, 10 = SMI, 11 = Disabled)

Note: At present, the WDT does not support SMI. IRQ uses APIC 1, INT 10 and it is active low, level triggered.

# Offset 68H: WDT Lock Register

Bit 1 enables or disables the WDT. (0 = Disabled, 1 = Enabled)

Bit 0 will lock the values of this register until a hard reset occurs or power is cycled. (0 = unlocked, 1 = locked) The default is Unlocked.

# GPIO Control Registers

There are three GPIOs on the PXI-3800 related to the watchdog timer. They are listed as follows. The GPIO control base port is 480H.

# WDT\_TOUT# pin selection

The WDT\_TOUT# signal is multiplexed with GPIO32. When using WDT, this signal must be switched to WDT\_TOUT# function. It uses bit 0 of GPIOBASE + 30H to set WDT\_TOUT function. (0 = WDT\_TOUT#, 1 = GPIO32)

# RESET hardware circuit selection

GPO24 of the 6300ESB is designed to control the reset circuit. When GPO24 is low, the system will reset according to the level of the WDT\_TOUT# signal. When GPO24 is high, the system will not be reset by WDT\_TOUT#. Set bit 24 of GPIOBASE + 04H to 0 for output use. Bit 24 of GPIOBASE + 0CH determines the level of GPO24 (0 = Low, 1 = High). A setting already exists in the BIOS setup menu. The user can set this item before programming WDT.

# WDT LED Control

GPO25 of the 6300ESB is designed to control WDT LED. Two features of the WDT LED are supported on PXI-3800. WDT LED lights or blinks.

WDT LED lights: Set bit 25 of GPIOBASE + 04H to 0. Bit 24 of GPIOBASE + 0CH determines the state of WDT LED. (0 = light, 1= dark)

WDT LED blinks: Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE + 18H enables WDT LED blinking function. (0 = function normally, 1 = enable blinking) The high and low times have approximately 0.5 seconds each.

# WDT Programming Procedure

# Step 1:

Set BIOS Setting in Integrated Peripherals\Onboard Device Page Watch Dog Timer Item to "Enabled".

# Step 2:

Make sure WDT\_TOUT# signal is functional. (Not GPIO32 function).

# Step 3:

Set WDT output enable, presecaler and interrupt type into WDT configuration register.

# Step 4:

Obtain control base from Base Address register.

# Step 5:

Program Preload register's value according to unlocking sequence.

# Step 6:

Set WDT timer mode into WDT Lock Register.

# Step 7:

Enable WDT from WDT Lock register and program the functionality of WDT LED.

To prevent the timer from causing an interrupt or driving WDT\_TOUT#, the timer must be reloaded periodically. The frequency of reloads required is dependent on the value of the preload values. To reload the down-counter, the register unlocking sequence must be performed.

If the user wishes to disable WDT, set bit 1 of WDT lock Register to 0.

# W83627HF (Super IO) Watchdog Timer

The W83627HF watchdog timer circuit is implemented in a programmable logic device. The watchdog timer contains a "Control and Status Register." The register allows the BIOS or user application to determine if a watchdog time out was the source of a particular reset. The timeout period is 1-255 seconds. The watchdog is normally strobed by reading the Watchdog Register (3F0h). IF the host fails to reload the WDT before the timeout, the WDT drives the WDT\_TOUT# pin low. Users can choose to reset the system or send a PXI Trigger signal through BIOS WDT setting.

![The diagram depicts a block diagram with the following components and connections:\n\n*   **Left:** A double-headed arrow labeled **'Address/Data'**.\n*   **Center:** A large rectangular block labeled **'Watchdog Circuit'**. Inside this block are three smaller sub-blocks:\n    *   **'Port 3F0h Control and Status Register'** (top left)\n    *   **'Slow Clock'** (bottom left)\n    *   **'Counter'** (bottom right)\n*   **Right:** Three arrows extending from the right side of the 'Watchdog Circuit' block pointing to the following labels:\n    *   **'Reset'**\n    *   **'NMI'**\n    *   **'CPU Init'**](.pxi-3800-manual-4/7cc43ce34a5c512ed56a1bfb2d7963cd9a7f9299bf1ac59e35a0d245978367ea.jpg)

Figure 5-2: W83267HF Watchdog Timer Architecture

# 5.2 Intel Preboot Execution Environment (PXE)

The PXI-3800 series supports the Intel Preboot Execution Environment (PXE), which provides the capability of boot-up or executing an OS installation through Ethernet ports. There should be a DHCP server in the network with one or more servers running PXE and MTFTP services. It could be a Windows NT or Windows 2000 server running DHCP, PXE and MTFTP service or a dedicated DHCP server with one or more additional server running PXE and MTFTP service. This section describes the major items required for building a network environment with PXE support.

# Step 1:

Setup a DHCP server with PXE tag configuration

# Step 2:

Install the PXE and MTFTP services

# Step 3:

Make boot image file on PXE server (that is the boot server)

# Step 4

Enable the PXE boot function on the client computer

For more detailed information, please refer to pdkrel30.pdf under the directory:

X:\Utility\PXE\_PDK

# 5.3 PICMG 2.1 Hot Swap Support

The PXI-3800 Hot-Swap capability allows non-system slot boards to be added or removed while the system is powered up. PXI-3800 provides independent clocks for each slot and accesses to the ENUM# signal on the backplane, which are compatible with PICMG 2.1 Hot Swap Specification. However, the PXI-3800 itself is not hot swappable.

The hot swappable system is dependent on system controller, peripheral modules, backplane, operating system, driver, application support. If users use I/O modules that are designed to be hot swappable, please contact ADLINK for hot swap function support.

# Appendix A PXI Trigger Function Description

This appendix provides a description of PXI Trigger functions, including data types and function reference.

# Data Types

We have defined some data types in the PXI-3800 header file. This header file can be found in P3800.H under the directory X:\ADLINK\PXI3800\Include after running the setup.exe file (where X is the drive you install the driver). These data types are used by the PXI-3800 Library. It is recommended that you use these data types in your application programs. The following table lists the data type names, their ranges, and the corresponding data types in C/C++, Visual Basic and Delphi.

<table><tr><td rowspan="2">Type Name</td><td rowspan="2">Description</td><td rowspan="2">Range</td><td colspan="3">Type</td></tr><tr><td>C/C++ (for 32-bit compiler)</td><td>Visual Basic</td><td>Pascal (Delphi)</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td><td>Unsigned char</td><td>Byte</td><td>Byte</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td><td>Short</td><td>Integer</td><td>SmallInt</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td><td>Unsigned short</td><td>Not supported by BASIC, use the signed integer (I16) instead</td><td>Word</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td><td>Long</td><td>Long</td><td>LongInt</td></tr></table>

Table 1-1: Data Types

<table><tr><td>U32</td><td>32-bit unsigned integer</td><td>0 to 4294967295</td><td>Unsigned long</td><td>Not supported by BASIC, use the signed long integer (I32) instead</td><td>Cardinal</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td><td>Float</td><td>Single</td><td>Single</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>-1.797683134862315E308 to 1.797683134862315E309</td><td>Double</td><td>Double</td><td>Double</td></tr></table>

Table 1-1: Data Types

# Function Reference

# P3800\_Close

# @ Description

This function is used to tell the PXI-3800 library that a registered card is not currently used and can be released, making room for the new card to register. At the end of a program, use this function to release all cards that were registered.

# @ Cards Support

PXI-3800

# @ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_Close (U16 CardNumber)

# Visual Basic

P3800\_Close (ByVal CardNumber As Integer) As Integer

# @ Parameter

CardNumber: The card ID of the card that want to be released.

# @ Return Code

NoError

# P3800\_GetGPIOBase

# @ Description

Get the GPIO base address of the PXI-3800.

# @ Cards Support

PXI-3800

# @ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_GetGPIOBase(U16 wCardNumber, U32 \*BaseAddr)

# Visual Basic

P3800\_GetGPIOBase (ByVal CardNumber As Integer, BaseAddr As Long) As Integer

# @ Parameter

CardNumber: The card ID of the card to retrieve the DPIO address.

Base Addr: Returns the GPIO base address.

# @ Return Code

NoError

# P3800\_Init

# @ Description

Initializes the hardware and software states of a PXI-3800 device, and returns a numeric card ID that corresponds to the card initialized. P3800\_Init must be called before any other PXI-3800 library functions can be called for that card. The function initializes the card and variables internal to the PXI-3800 library.

# @ Cards Support

PXI-3800

# @ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_Init (U16 card\_num)

# Visual Basic

P3800\_Init (ByVal card\_num As Integer) As Integer

# @ Parameter

card\_num: The sequence number of the device. This must be zero.

# @ Return Code

This function returns a numeric card ID for the card initialized. A negative error code would be returned in the even of an error. Possible error codes:

ERR\_InvalidBoardNumber, ERR\_BoardNoInit, ErrorOpenDriverFailed, ERR\_OpenDriverFail, ERR\_GetGPIOAddress, ERR\_BoardBusy

# P3800\_SetSoftTrg

@ Description

Generates a software trigger signal.

@ Cards Support

PXI-3800

@ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_SetSoftTrg (U16 wCardNumber, U8 status)

# Visual Basic

P3800\_SetSoftTrg (ByVal CardNumber As Integer, ByVal status As Byte) As Integer

@ Parameter

CardNumber: The card ID of the card to perform this operation.

status: The trigger status.

Possible statuses:

1: High

0: Low

@ Return Code

NoError, ERR\_SoftTrg\_Out

# P3800\_Trigger\_Clear

@ Description

Resets all trigger routing configuration to the default settings.

@ Cards Support

PXI-3800

@ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_Trigger\_Clear (U16 wCardNumber)

# Visual Basic

P3800\_Trigger\_Clear (ByVal CardNumber As Integer)
As Integer

@ Parameter

CardNumber: The card ID of the card to perform this operation.

@ Return Code

NoError, ERR\_Trigger\_Clr

P3800\_Trigger\_Route

@ Description

Configures the source, destination, and halfway of the trigger path.

@ Cards Support

PXI-3800

@ Syntax

Microsoft C/C++, Linux C/C++ and Borland C++

I16 P3800\_Trigger\_Route(U16 wCardNumber, U32 source, U32 dest, U32 halfway)

# Visual Basic

P3800\_Trigger\_Route (ByVal CardNumber As Integer, ByVal source As Long, ByVal dest As Long, ByVal halfway As Long) As Integer

# @ Parameter

CardNumber: The card ID of the card to perform this operation.

Source: The trigger signal source or the starting point of the trigger path. Possible values of source:

```csv
P3800_VAL_WDT
P3800_VAL_SMB
P3800_VAL_SOFT
P3800_VAL_TTL0
P3800_VAL_TTL1
P3800_VAL_TTL2
P3800_VAL_TTL3
P3800_VAL_TTL4
P3800_VAL_TTL5
P3800_VAL_TTL6
P3800_VAL_TTL7
```

dest: The endpoint of the trigger path. Possible values of destination:

```csv
P3800_VAL_SMB
P3800_VAL_TTL0
P3800_VAL_TTL1
P3800_VAL_TTL2
P3800_VAL_TTL3
P3800_VAL_TTL4
P3800_VAL_TTL5
```

P3800\_VAL\_TTL6

P3800\_VAL\_TTL7

halfway: Halfway of the trigger path. Possible values of half-way:

P3800\_VAL\_NONE

P3800\_VAL\_TTL0

P3800\_VAL\_TTL1

P3800\_VAL\_TTL2

P3800\_VAL\_TTL3

P3800\_VAL\_TTL4

P3800\_VAL\_TTL5

P3800\_VAL\_TTL6

P3800\_VAL\_TTL7

# @ Return Code

NoError, ERR\_Set\_Path

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/.
2. All ADLINK products come with a limited two-year warranty, one year for products bought in China:

The warranty period starts on the day the product is shipped from ADLINK's factory.
▶ Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for any loss of data.
▶ Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.
For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's guarantee in the following situations:

▶ Damage caused by not following instructions in the User's Manual.
▶ Damage caused by carelessness on the user's part during product transportation.
▶ Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
▶ Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
▶ Damage caused by leakage of battery fluid during or after change of batteries by customer/user.
▶ Damage from improper repair by unauthorized ADLINK technicians.
▶ Products with altered and/or damaged serial numbers are not entitled to our service.
▶ This warranty is not transferable or extendible.
▶ Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please download an RMA application form from our company website: http://rma.adlinktech.com/policy. Damaged products with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff: service@adlinktech.com.
[🔗 Link to the original document](.pxi-3800-manual-4/pxi-3800-manual-4.pdf)